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AccLib SIG 双周例会
by openEuler conference 02 Apr '24

02 Apr '24

您好！ sig-AccLib 邀请您参加 2024-04-03 11:00 召开的Zoom会议会议主题：AccLib SIG 双周例会会议内容：固定会议链接linaro-org.zoom.us/j/91879279131 会议链接：https://us06web.zoom.us/j/81432955622?pwd=KbfGknjEcVt86ce0fxpyetjS59lqtg.1 会议纪要：https://etherpad.openeuler.org/p/sig-AccLib-meetings 更多资讯尽在：https://www.openeuler.org/zh/ Hello! sig-AccLib invites you to attend the Zoom conference will be held at 2024-04-03 11:00, The subject of the conference is AccLib SIG 双周例会, Summary: 固定会议链接linaro-org.zoom.us/j/91879279131 You can join the meeting at https://us06web.zoom.us/j/81432955622?pwd=KbfGknjEcVt86ce0fxpyetjS59lqtg.1. Add topics at https://etherpad.openeuler.org/p/sig-AccLib-meetings. More information: https://www.openeuler.org/en/

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[PATCH 00/11] sync uadk patches
by Qi Tao 29 Mar '24

29 Mar '24

*** BLURB HERE *** Longfang Liu (2): uadk/v1: improve the judgment conditions of tag uadk: modify uadk static compile Qi Tao (3): uadk: fix some cleancode issues uadk: delete useless codes. uadk: simplify repetitive codes Wenkai Lin (6): cipher: optimze input lengths check uadk/v1: fix for sec cipher bd1 ci_gen configuration uadk: fix for shmget shmflag sec: optimze for directly assigning values to structures util: optimize for wd_handle_msg_sync uadk: drv/hisi - optimize qm recv function drv/hisi_comp.c | 8 ++++ drv/hisi_hpre.c | 9 ++++ drv/hisi_qm_udrv.c | 45 ++++++++++--------- drv/hisi_sec.c | 63 +++++++++++--------------- drv/isa_ce_sm4.c | 96 ++++++++++++++++------------------------ include/wd_alg.h | 26 ++++++++--- include/wd_alg_common.h | 17 ++++--- uadk_tool/dfx/uadk_dfx.c | 2 +- v1/drv/hisi_hpre_udrv.c | 4 +- v1/drv/hisi_sec_udrv.c | 12 +++-- v1/wd.c | 3 +- v1/wd_rng.c | 4 +- wd_aead.c | 61 +++++++++++++++++-------- wd_alg.c | 25 ++++++++++- wd_cipher.c | 87 ++++++++++++++++++++++++++++-------- wd_comp.c | 63 +++++++++++++++++--------- wd_dh.c | 61 +++++++++++++++++-------- wd_digest.c | 63 ++++++++++++++++++-------- wd_ecc.c | 61 +++++++++++++++++-------- wd_rsa.c | 61 +++++++++++++++++-------- wd_util.c | 28 +++++++----- 21 files changed, 508 insertions(+), 291 deletions(-) -- 2.33.0

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[PATCH 0/4] uadk_engine: some cleanup
by Zhiqi Song 29 Mar '24

29 Mar '24

This series of patches are mainly used for cleanup. Zhiqi Song (4): uadk_engine: cleanup code style of async functions cipher: cleanup repeated function invoking digest: add ctx allocation check sm2: add ctx allocation check src/uadk_async.c | 126 ++++++++++++++++++++++------------------------ src/uadk_async.h | 3 ++ src/uadk_cipher.c | 7 ++- src/uadk_digest.c | 2 + src/uadk_sm2.c | 6 ++- 5 files changed, 74 insertions(+), 70 deletions(-) -- 2.33.0

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[PATCH 0/4] uadk: support sm3 and md5 multi-buffer calculation
by Weili Qian 23 Mar '24

23 Mar '24

Support sm3 and md5 multi-buffer calculation by SVE instructions. Weili Qian (4): uadk/wd_alg: check whether the platform supports SVE uadk/sched: fix async mode ctx id uadk: initializes ctx resources in SVE mode uadk/hash_mb: support multi-buffer calculation for sm3 and md5 Makefile.am | 15 +- drv/hash_mb/hash_mb.c | 860 ++++++++++++++++++++++++++++++++++ drv/hash_mb/hash_mb.h | 60 +++ drv/hash_mb/md5_mb_asimd_x1.S | 248 ++++++++++ drv/hash_mb/md5_mb_asimd_x4.S | 526 +++++++++++++++++++++ drv/hash_mb/md5_mb_sve.S | 158 +++++++ drv/hash_mb/md5_sve_common.S | 478 +++++++++++++++++++ drv/hash_mb/sm3_mb_asimd_x1.S | 387 +++++++++++++++ drv/hash_mb/sm3_mb_asimd_x4.S | 576 +++++++++++++++++++++++ drv/hash_mb/sm3_mb_sve.S | 161 +++++++ drv/hash_mb/sm3_sve_common.S | 505 ++++++++++++++++++++ include/wd_alg_common.h | 4 + wd_alg.c | 14 + wd_sched.c | 4 +- wd_util.c | 95 +++- 15 files changed, 4074 insertions(+), 17 deletions(-) create mode 100644 drv/hash_mb/hash_mb.c create mode 100644 drv/hash_mb/hash_mb.h create mode 100644 drv/hash_mb/md5_mb_asimd_x1.S create mode 100644 drv/hash_mb/md5_mb_asimd_x4.S create mode 100644 drv/hash_mb/md5_mb_sve.S create mode 100644 drv/hash_mb/md5_sve_common.S create mode 100644 drv/hash_mb/sm3_mb_asimd_x1.S create mode 100644 drv/hash_mb/sm3_mb_asimd_x4.S create mode 100644 drv/hash_mb/sm3_mb_sve.S create mode 100644 drv/hash_mb/sm3_sve_common.S -- 2.33.0

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申请增加sig-Acclib maintainer
by Zhangfei Gao 22 Mar '24

22 Mar '24

申请增加sig-Acclib maintainer Linaro: Zhangfei Gao 请大家review 2024/3/6 sig meeting minutes https://etherpad.openeuler.org/p/sig-AccLib-meetings 议题一： gitee sig 增加maintainer : Zhangfei Gao https://gitee.com/src-openeuler/libwd https://gitee.com/src-openeuler/uadk_engine Zhangfei Gao是 uadk in DPDK，uadk_engine (provider) for OpenSSL 的主要作者之一。目前在虚拟化场景下的uadk使用有持续跟踪。同时也是linux kernel uacce的维护者。需要统计数据 uadk$ git log --author="Zhangfei Gao" --pretty=oneline | wc -l 65 uadk_engine$ git log --author="Zhangfei Gao" --pretty=oneline | wc -l 82 src-openeuler/libwd$ git log --author="Zhangfei Gao" --pretty=oneline | wc -l 1 src-openeuler/uadk_engine$ git log --author="Zhangfei Gao" --pretty=oneline | wc -l 1 pr: https://gitee.com/openeuler/community/pulls/5495 Thanks

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[PATCH v2 0/8] ce instruction for SM4
by Qi Tao 20 Mar '24

20 Mar '24

*** BLURB HERE *** Qi Tao (2): cipher: add support for SM4(ECB) algorithm in CE instruction cipher: fix sm4 ce code defect Wenkai Lin (2): cipher: add support for SM4 CBC and CTR modes in CE instruction uadk: fix calloc zero size problem Yang Shen (3): uadk/cipher: isa_ce - support SM4 cbc_cts mode uadk/cipher: isa_ce - fix memcpy overwrite uadk/cipher: isa - fix code style Yuzeng Zhuang (1): cipher: add support for SM4 CFB and XTS modes in CE instruction Makefile.am | 5 +- drv/isa_ce_sm4.c | 472 +++++++++ drv/isa_ce_sm4.h | 62 ++ drv/isa_ce_sm4_armv8.S | 2296 ++++++++++++++++++++++++++++++++++++++++ wd_cipher.c | 4 +- 5 files changed, 2835 insertions(+), 4 deletions(-) create mode 100644 drv/isa_ce_sm4.c create mode 100644 drv/isa_ce_sm4.h create mode 100644 drv/isa_ce_sm4_armv8.S -- 2.33.0

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[PATCH 8/8] uadk/cipher: isa - fix code style
by Qi Tao 19 Mar '24

19 Mar '24

From: Yang Shen <shenyang39(a)huawei.com> Code the cbc_cts mode as openssl code style. Signed-off-by: Yang Shen <shenyang39(a)huawei.com> --- drv/isa_ce_sm4_armv8.S | 201 +++++++++++++++++++---------------------- 1 file changed, 94 insertions(+), 107 deletions(-) diff --git a/drv/isa_ce_sm4_armv8.S b/drv/isa_ce_sm4_armv8.S index 2f9477a..6ebf39b 100644 --- a/drv/isa_ce_sm4_armv8.S +++ b/drv/isa_ce_sm4_armv8.S @@ -24,11 +24,6 @@ .inst 0xce60c800 | (.L\vm << 16) | (.L\vn << 5) | .L\vd .endm -.macro adr_l, dst, sym - adrp \dst, \sym - add \dst, \dst, :lo12:\sym -.endm - .text .align 6 .Lck: @@ -517,63 +512,62 @@ sm4_v8_cbc_encrypt: .align 5 sm4_v8_cbc_cts_encrypt: AARCH64_VALID_CALL_TARGET - ld1 {v24.16b-v27.16b}, [x3], #64; - ld1 {v28.16b-v31.16b}, [x3]; - - sub x5, x2, #16 - - ld1 {v20.16b}, [x4] - - ld1 {v0.16b}, [x0] - eor v20.16b, v20.16b, v0.16b - rev32 v20.16b, v20.16b; - sm4e v20.4s, v24.4s; - sm4e v20.4s, v25.4s; - sm4e v20.4s, v26.4s; - sm4e v20.4s, v27.4s; - sm4e v20.4s, v28.4s; - sm4e v20.4s, v29.4s; - sm4e v20.4s, v30.4s; - sm4e v20.4s, v31.4s; - rev64 v20.4s, v20.4s; - ext v20.16b, v20.16b, v20.16b, #8; - rev32 v20.16b, v20.16b; + ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x3], #64 + ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x3] + sub x5, x2, #16 + + ld1 {v8.4s}, [x4] + + ld1 {v10.4s}, [x0] + eor v8.16b, v8.16b, v10.16b + rev32 v8.16b, v8.16b; + sm4e v8.4s, v0.4s; + sm4e v8.4s, v1.4s; + sm4e v8.4s, v2.4s; + sm4e v8.4s, v3.4s; + sm4e v8.4s, v4.4s; + sm4e v8.4s, v5.4s; + sm4e v8.4s, v6.4s; + sm4e v8.4s, v7.4s; + rev64 v8.4s, v8.4s; + ext v8.16b, v8.16b, v8.16b, #8; + rev32 v8.16b, v8.16b; /* load permute table */ - adr x6, .Lcts_permute_table - add x7, x6, #32 - add x6, x6, x5 - sub x7, x7, x5 - ld1 {v3.16b}, [x6] - ld1 {v4.16b}, [x7] + adr x6, .cts_permute_table + add x7, x6, #32 + add x6, x6, x5 + sub x7, x7, x5 + ld1 {v13.4s}, [x6] + ld1 {v14.4s}, [x7] /* overlapping loads */ - add x0, x0, x5 - ld1 {v1.16b}, [x0] + add x0, x0, x5 + ld1 {v11.4s}, [x0] /* create Cn from En-1 */ - tbl v0.16b, {v20.16b}, v3.16b + tbl v10.16b, {v8.16b}, v13.16b /* padding Pn with zeros */ - tbl v1.16b, {v1.16b}, v4.16b - - eor v1.16b, v1.16b, v20.16b - rev32 v1.16b, v1.16b; - sm4e v1.4s, v24.4s; - sm4e v1.4s, v25.4s; - sm4e v1.4s, v26.4s; - sm4e v1.4s, v27.4s; - sm4e v1.4s, v28.4s; - sm4e v1.4s, v29.4s; - sm4e v1.4s, v30.4s; - sm4e v1.4s, v31.4s; - rev64 v1.4s, v1.4s; - ext v1.16b, v1.16b, v1.16b, #8; - rev32 v1.16b, v1.16b; + tbl v11.16b, {v11.16b}, v14.16b + + eor v11.16b, v11.16b, v8.16b + rev32 v11.16b, v11.16b; + sm4e v11.4s, v0.4s; + sm4e v11.4s, v1.4s; + sm4e v11.4s, v2.4s; + sm4e v11.4s, v3.4s; + sm4e v11.4s, v4.4s; + sm4e v11.4s, v5.4s; + sm4e v11.4s, v6.4s; + sm4e v11.4s, v7.4s; + rev64 v11.4s, v11.4s; + ext v11.16b, v11.16b, v11.16b, #8; + rev32 v11.16b, v11.16b; /* overlapping stores */ - add x5, x1, x5 - st1 {v0.16b}, [x5] - st1 {v1.16b}, [x1] + add x5, x1, x5 + st1 {v10.16b}, [x5] + st1 {v11.16b}, [x1] ret .size sm4_v8_cbc_cts_encrypt,.-sm4_v8_cbc_cts_encrypt @@ -582,76 +576,69 @@ sm4_v8_cbc_cts_encrypt: .type sm4_v8_cbc_cts_decrypt,%function .align 5 sm4_v8_cbc_cts_decrypt: - ld1 {v24.16b-v27.16b}, [x3], #64; - ld1 {v28.16b-v31.16b}, [x3]; + AARCH64_VALID_CALL_TARGET + ld1 {v0.4s,v1.4s,v2.4s,v3.4s}, [x3], #64 + ld1 {v4.4s,v5.4s,v6.4s,v7.4s}, [x3] - sub x5, x2, #16 + sub x5, x2, #16 - ld1 {v20.16b}, [x4] + ld1 {v8.4s}, [x4] /* load permute table */ - adr_l x6, .Lcts_permute_table - add x7, x6, #32 - add x6, x6, x5 - sub x7, x7, x5 - ld1 {v3.16b}, [x6] - ld1 {v4.16b}, [x7] + adr x6, .cts_permute_table + add x7, x6, #32 + add x6, x6, x5 + sub x7, x7, x5 + ld1 {v13.4s}, [x6] + ld1 {v14.4s}, [x7] /* overlapping loads */ - ld1 {v0.16b}, [x0], x5 - ld1 {v1.16b}, [x0] - - rev32 v0.16b, v0.16b; - sm4e v0.4s, v24.4s; - sm4e v0.4s, v25.4s; - sm4e v0.4s, v26.4s; - sm4e v0.4s, v27.4s; - sm4e v0.4s, v28.4s; - sm4e v0.4s, v29.4s; - sm4e v0.4s, v30.4s; - sm4e v0.4s, v31.4s; - rev64 v0.4s, v0.4s; - ext v0.16b, v0.16b, v0.16b, #8; - rev32 v0.16b, v0.16b; + ld1 {v10.16b}, [x0], x5 + ld1 {v11.16b}, [x0] + + rev32 v10.16b, v10.16b; + sm4e v10.4s, v0.4s; + sm4e v10.4s, v1.4s; + sm4e v10.4s, v2.4s; + sm4e v10.4s, v3.4s; + sm4e v10.4s, v4.4s; + sm4e v10.4s, v5.4s; + sm4e v10.4s, v6.4s; + sm4e v10.4s, v7.4s; + rev64 v10.4s, v10.4s; + ext v10.16b, v10.16b, v10.16b, #8; + rev32 v10.16b, v10.16b; /* select the first Ln bytes of Xn to create Pn */ - tbl v2.16b, {v0.16b}, v3.16b - eor v2.16b, v2.16b, v1.16b + tbl v12.16b, {v10.16b}, v13.16b + eor v12.16b, v12.16b, v11.16b /* overwrite the first Ln bytes with Cn to create En-1 */ - tbx v0.16b, {v1.16b}, v4.16b - - rev32 v0.16b, v0.16b; - sm4e v0.4s, v24.4s; - sm4e v0.4s, v25.4s; - sm4e v0.4s, v26.4s; - sm4e v0.4s, v27.4s; - sm4e v0.4s, v28.4s; - sm4e v0.4s, v29.4s; - sm4e v0.4s, v30.4s; - sm4e v0.4s, v31.4s; - rev64 v0.4s, v0.4s; - ext v0.16b, v0.16b, v0.16b, #8; - rev32 v0.16b, v0.16b; - - eor v0.16b, v0.16b, v20.16b + tbx v10.16b, {v11.16b}, v14.16b + + rev32 v10.16b, v10.16b; + sm4e v10.4s, v0.4s; + sm4e v10.4s, v1.4s; + sm4e v10.4s, v2.4s; + sm4e v10.4s, v3.4s; + sm4e v10.4s, v4.4s; + sm4e v10.4s, v5.4s; + sm4e v10.4s, v6.4s; + sm4e v10.4s, v7.4s; + rev64 v10.4s, v10.4s; + ext v10.16b, v10.16b, v10.16b, #8; + rev32 v10.16b, v10.16b; + + eor v10.16b, v10.16b, v8.16b /* overlapping stores */ - add x5, x1, x5 - st1 {v2.16b}, [x5] - st1 {v0.16b}, [x1] + add x5, x1, x5 + st1 {v12.16b}, [x5] + st1 {v10.16b}, [x1] ret .size sm4_v8_cbc_cts_decrypt,.-sm4_v8_cbc_cts_decrypt -.Lcts_permute_table: - .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff - .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff - .byte 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 - .byte 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf - .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff - .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff - .globl sm4_v8_ecb_encrypt .type sm4_v8_ecb_encrypt,%function .align 5 -- 2.33.0

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[PATCH 0/8] add support for CE instruction
by Qi Tao 19 Mar '24

19 Mar '24

*** BLURB HERE *** Qi Tao (2): cipher: add support for SM4(ECB) algorithm in CE instruction cipher: fix sm4 ce code defect Wenkai Lin (2): cipher: add support for SM4 CBC and CTR modes in CE instruction uadk: fix calloc zero size problem Yang Shen (3): uadk/cipher: isa_ce - support SM4 cbc_cts mode uadk/cipher: isa_ce - fix memcpy overwrite uadk/cipher: isa - fix code style Yuzeng Zhuang (1): cipher: add support for SM4 CFB and XTS modes in CE instruction Makefile.am | 5 +- drv/isa_ce_sm4.c | 473 +++++++++ drv/isa_ce_sm4.h | 62 ++ drv/isa_ce_sm4_armv8.S | 2296 ++++++++++++++++++++++++++++++++++++++++ wd_cipher.c | 4 +- wd_util.c | 5 + 6 files changed, 2841 insertions(+), 4 deletions(-) create mode 100644 drv/isa_ce_sm4.c create mode 100644 drv/isa_ce_sm4.h create mode 100644 drv/isa_ce_sm4_armv8.S -- 2.33.0

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[PATCH 1/2] uadk/digest: modify spelling errors
by Zhiqi Song 15 Mar '24

15 Mar '24

Modify spelling errors related to digest stream mode. Signed-off-by: Zhiqi Song <songzhiqi1(a)huawei.com> --- drv/hash_mb/hash_mb.c | 4 ++-- drv/hisi_sec.c | 8 ++++---- drv/isa_ce_sm3.c | 4 ++-- include/drv/wd_digest_drv.h | 6 +++--- v1/test/hisi_sec_test/test_hisi_sec.c | 4 ++-- v1/test/hisi_sec_test_sgl/test_hisi_sec_sgl.c | 4 ++-- wd_digest.c | 2 +- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drv/hash_mb/hash_mb.c b/drv/hash_mb/hash_mb.c index 0f27c11..4750062 100644 --- a/drv/hash_mb/hash_mb.c +++ b/drv/hash_mb/hash_mb.c @@ -406,7 +406,7 @@ static int hash_do_partial(struct hash_mb_poll_queue *poll_queue, int ret = WD_SUCCESS; switch (bd_type) { - case HASH_FRIST_BLOCK: + case HASH_FIRST_BLOCK: ret = hash_first_block_process(d_msg, job, poll_queue->ops->iv_bytes); break; case HASH_MIDDLE_BLOCK: @@ -434,7 +434,7 @@ static void hash_mb_init_iv(struct hash_mb_poll_queue *poll_queue, job->opad.opad_size = 0; switch (bd_type) { - case HASH_FRIST_BLOCK: + case HASH_FIRST_BLOCK: memcpy(job->result_digest, poll_queue->ops->iv_data, poll_queue->ops->iv_bytes); if (d_msg->mode != WD_DIGEST_HMAC) return; diff --git a/drv/hisi_sec.c b/drv/hisi_sec.c index 2eaac51..e66fb00 100644 --- a/drv/hisi_sec.c +++ b/drv/hisi_sec.c @@ -1536,7 +1536,7 @@ static int fill_digest_long_hash(handle_t h_qp, struct wd_digest_msg *msg, if (ret) return ret; - if (block_type == HASH_FRIST_BLOCK) { + if (block_type == HASH_FIRST_BLOCK) { /* Long hash first */ sqe->ai_apd_cs = AI_GEN_INNER; sqe->ai_apd_cs |= AUTHPAD_NOPAD << AUTHPAD_OFFSET; @@ -1618,7 +1618,7 @@ static int digest_bd2_type_check(struct wd_digest_msg *msg) enum hash_block_type type = get_hash_block_type(msg); /* Long hash first and middle bd */ - if (type == HASH_FRIST_BLOCK || type == HASH_MIDDLE_BLOCK) { + if (type == HASH_FIRST_BLOCK || type == HASH_MIDDLE_BLOCK) { WD_ERR("hardware v2 not supports 0 size in long hash!\n"); return -WD_EINVAL; } @@ -1636,7 +1636,7 @@ static int digest_bd3_type_check(struct wd_digest_msg *msg) { enum hash_block_type type = get_hash_block_type(msg); /* Long hash first and middle bd */ - if (type == HASH_FRIST_BLOCK || type == HASH_MIDDLE_BLOCK) { + if (type == HASH_FIRST_BLOCK || type == HASH_MIDDLE_BLOCK) { WD_ERR("invalid: hardware v3 not supports 0 size in long hash!\n"); return -WD_EINVAL; } @@ -1889,7 +1889,7 @@ static int fill_digest_long_hash3(handle_t h_qp, struct wd_digest_msg *msg, if (ret) return ret; - if (block_type == HASH_FRIST_BLOCK) { + if (block_type == HASH_FIRST_BLOCK) { /* Long hash first */ sqe->auth_mac_key |= AI_GEN_INNER << SEC_AI_GEN_OFFSET_V3; sqe->stream_scene.stream_auth_pad = AUTHPAD_NOPAD; diff --git a/drv/isa_ce_sm3.c b/drv/isa_ce_sm3.c index 2789a08..5fc7acc 100644 --- a/drv/isa_ce_sm3.c +++ b/drv/isa_ce_sm3.c @@ -188,7 +188,7 @@ static int do_sm3_ce(struct wd_digest_msg *msg, __u8 *out_digest) sm3_ce_update(&sctx, data, data_len, sm3_ce_block_compress); sm3_ce_final(&sctx, out_digest, sm3_ce_block_compress); break; - case HASH_FRIST_BLOCK: + case HASH_FIRST_BLOCK: sm3_ce_init(&sctx); sm3_ce_update(&sctx, data, data_len, sm3_ce_block_compress); trans_output_result(out_digest, sctx.word_reg); @@ -306,7 +306,7 @@ static int do_hmac_sm3_ce(struct wd_digest_msg *msg, __u8 *out_hmac) sm3_ce_hmac_update(&hctx, data, data_len); sm3_ce_hmac_final(&hctx, out_hmac); break; - case HASH_FRIST_BLOCK: + case HASH_FIRST_BLOCK: sm3_ce_hmac_init(&hctx, key, key_len); sm3_ce_hmac_update(&hctx, data, data_len); trans_output_result(out_hmac, hctx.sctx.word_reg); diff --git a/include/drv/wd_digest_drv.h b/include/drv/wd_digest_drv.h index 7d86b65..5e3e821 100644 --- a/include/drv/wd_digest_drv.h +++ b/include/drv/wd_digest_drv.h @@ -12,7 +12,7 @@ extern "C" { #endif enum hash_block_type { - HASH_FRIST_BLOCK, + HASH_FIRST_BLOCK, HASH_MIDDLE_BLOCK, HASH_END_BLOCK, HASH_SINGLE_BLOCK, @@ -66,13 +66,13 @@ static inline enum hash_block_type get_hash_block_type(struct wd_digest_msg *msg { /* * [has_next , iv_bytes] - * [ 1 , 0 ] = long hash(frist bd) + * [ 1 , 0 ] = long hash(first bd) * [ 1 , 1 ] = long hash(middle bd) * [ 0 , 1 ] = long hash(end bd) * [ 0 , 0 ] = block hash(single bd) */ if (msg->has_next && !msg->iv_bytes) - return HASH_FRIST_BLOCK; + return HASH_FIRST_BLOCK; else if (msg->has_next && msg->iv_bytes) return HASH_MIDDLE_BLOCK; else if (!msg->has_next && msg->iv_bytes) diff --git a/v1/test/hisi_sec_test/test_hisi_sec.c b/v1/test/hisi_sec_test/test_hisi_sec.c index be4ee9d..05c91ad 100644 --- a/v1/test/hisi_sec_test/test_hisi_sec.c +++ b/v1/test/hisi_sec_test/test_hisi_sec.c @@ -1463,7 +1463,7 @@ static int sec_cipher_async_test(int thread_num, __u64 lcore_mask, SEC_TST_PRT("%s(): create pool fail!\n", __func__); return -ENOMEM; } - /* frist create the async poll thread! */ + /* first create the async poll thread! */ test_thrds_data[0].pool = pool; test_thrds_data[0].q = &q; test_thrds_data[0].thread_num = 1; @@ -2070,7 +2070,7 @@ static int sec_aead_async_test(int thd_num, __u64 lcore_mask, SEC_TST_PRT("%s(): create pool fail!\n", __func__); return -ENOMEM; } - /* frist create the async poll thread! */ + /* first create the async poll thread! */ test_thrds_data[0].pool = pool; test_thrds_data[0].q = &q; test_thrds_data[0].thread_num = 1; diff --git a/v1/test/hisi_sec_test_sgl/test_hisi_sec_sgl.c b/v1/test/hisi_sec_test_sgl/test_hisi_sec_sgl.c index b7513d1..ba5cdfa 100644 --- a/v1/test/hisi_sec_test_sgl/test_hisi_sec_sgl.c +++ b/v1/test/hisi_sec_test_sgl/test_hisi_sec_sgl.c @@ -1733,7 +1733,7 @@ static int sec_cipher_async_test(int thread_num, __u64 lcore_mask, SEC_TST_PRT("%s(): create pool fail!\n", __func__); return -ENOMEM; } - /* frist create the async poll thread! */ + /* first create the async poll thread! */ test_thrds_data[0].pool = pool; test_thrds_data[0].q = &q; test_thrds_data[0].thread_num = 1; @@ -2640,7 +2640,7 @@ static int sec_aead_async_test(int thd_num, __u64 lcore_mask, return -ENOMEM; } - /* frist create the async poll thread! */ + /* first create the async poll thread! */ test_thrds_data[0].pool = pool; test_thrds_data[0].q = &q; test_thrds_data[0].thread_num = 1; diff --git a/wd_digest.c b/wd_digest.c index dfe709b..4832de8 100644 --- a/wd_digest.c +++ b/wd_digest.c @@ -55,7 +55,7 @@ struct wd_digest_stream_data { /* Total data length for stream mode */ __u64 long_data_len; /* - * Notify the stream message state, zero is frist message, + * Notify the stream message state, zero is first message, * non-zero is middle or final message. */ int msg_state; -- 2.30.0

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[PATCH 0/4] Support sm3 ce instruction
by Zhiqi Song 12 Mar '24

12 Mar '24

1. Support sync sm3 ce instruction. 2. Some cleanup and bugfix. Zhiqi Song (4): uadk: remove redundant header file in makefile uadk/isa-ce: support sm3 ce instruction uadk: fix control range of environmemt variable uadk/util: use default sched_type for instruction task Makefile.am | 20 +- configure.ac | 3 + drv/isa_ce_sm3.c | 401 ++++++++++++++++++++ drv/isa_ce_sm3.h | 86 +++++ drv/isa_ce_sm3_armv8.S | 765 ++++++++++++++++++++++++++++++++++++++ include/drv/arm_arch_ce.h | 199 ++++++++++ include/wd_alg.h | 43 +++ include/wd_sched.h | 2 +- wd_alg.c | 32 +- wd_digest.c | 2 +- wd_sched.c | 2 +- wd_util.c | 92 ++++- 12 files changed, 1619 insertions(+), 28 deletions(-) create mode 100644 drv/isa_ce_sm3.c create mode 100644 drv/isa_ce_sm3.h create mode 100644 drv/isa_ce_sm3_armv8.S create mode 100644 include/drv/arm_arch_ce.h -- 2.33.0

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