From: wenglianfa <wenglianfa@huawei.com> driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/IB2HJE ---------------------------------------------------------------------- QP banks 0, 1, 4, and 5 use one HW FIFO, while QP banks 2, 3, 6, and 7 use another. Currently, if HNS_ROCE_CAP_FLAG_LIMIT_BANK is set, only QP banks 0, 1, 4, and 5 are used, resulting in a single HW FIFO being utilized. Instead, it is proposed to use QP banks 0, 1, 6, and 7 to leverage different FIFOs and improve performance. Fixes: 1c16701634e4 ("RDMA/hns: Fix RoCEE hang when multiple QP banks use EXT_SGE") Signed-off-by: wenglianfa <wenglianfa@huawei.com> Signed-off-by: Xinghai Cen <cenxinghai@h-partners.com> --- drivers/infiniband/hw/hns/hns_roce_device.h | 4 ++-- drivers/infiniband/hw/hns/hns_roce_qp.c | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index e4d602bbeaec..a6c4ef631bb7 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -113,9 +113,9 @@ #define CQ_BANKID_MASK GENMASK(1, 0) #define VALID_CQ_BANK_MASK_DEFAULT 0xF -#define VALID_CQ_BANK_MASK_LIMIT 0x5 +#define VALID_CQ_BANK_MASK_LIMIT 0x9 -#define QP_HARDEN_MASK GENMASK(1, 0) +#define VALID_EXT_SGE_QP_BANK_MASK_LIMIT 0x41 #define HNS_ROCE_MAX_CQ_COUNT 0xFFFF #define HNS_ROCE_MAX_CQ_PERIOD 0xFFFF diff --git a/drivers/infiniband/hw/hns/hns_roce_qp.c b/drivers/infiniband/hw/hns/hns_roce_qp.c index f90bff2ff0c0..98d9f3a77997 100644 --- a/drivers/infiniband/hw/hns/hns_roce_qp.c +++ b/drivers/infiniband/hw/hns/hns_roce_qp.c @@ -244,7 +244,8 @@ static u8 select_qp_bankid(struct hns_roce_dev *hr_dev, continue; if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_LIMIT_BANK) && - use_ext_sge(init_attr) && (QP_HARDEN_MASK & i)) + use_ext_sge(init_attr) && + !(VALID_EXT_SGE_QP_BANK_MASK_LIMIT & BIT(i))) continue; valid_qp_bank_mask |= BIT(i); -- 2.33.0