hulk inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/ICX9YF -------------------------------- On specific chip models, the CPBM interface does not permit bits 18 and 17 to be set independently. Therefore, add the validity check for L3 CPBM. Fixes: f3a3763f845e ("arm64/mpam: Add quirk for hisi cpbm_wd field") Signed-off-by: Zeng Heng <zengheng4@huawei.com> --- drivers/platform/mpam/mpam_resctrl.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/platform/mpam/mpam_resctrl.c b/drivers/platform/mpam/mpam_resctrl.c index 658ef77f676c..e3ff6a8354a9 100644 --- a/drivers/platform/mpam/mpam_resctrl.c +++ b/drivers/platform/mpam/mpam_resctrl.c @@ -1322,6 +1322,26 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, struct rdt_domain *d, } } +static bool mpam_cpbm_hisi_check_invalid(struct rdt_resource *r, + unsigned long val) +{ + static const struct midr_range cpus[] = { + MIDR_ALL_VERSIONS(MIDR_HISI_HIP12), + { /* sentinel */ } + }; + + if (!is_midr_in_range_list(cpus)) + return false; + + if (r->cache_level != 3) + return false; + + if (val & ~(BIT(18) | BIT(17))) + return false; + + return true; +} + int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_domain *d, u32 closid, enum resctrl_conf_type t, u32 cfg_val) { @@ -1349,6 +1369,9 @@ int resctrl_arch_update_one(struct rdt_resource *r, struct rdt_domain *d, switch (r->rid) { case RDT_RESOURCE_L2: case RDT_RESOURCE_L3: + if (mpam_cpbm_hisi_check_invalid(r, cfg_val)) + return -EINVAL; + /* TODO: Scaling is not yet supported */ cfg.cpbm = cfg_val; mpam_set_feature(mpam_feat_cpor_part, &cfg); -- 2.25.1