If the GICv5 system has a large number of PEs and IRS components, traversing the linked list to find the irs_data corresponding to a specific SPI interrupt will be very slow. Since the maximum number of IRS nodes, the minimum and maximum SPI interrupt numbers for each IRS is known during the initialization of the IRS nodes, sort the IRS nodes by interrupt number at the initial stage. This way, when allocating SPI interrupts, we can directly perform a binary search on the irs_data using the SPI interrupt number with O(log N) complexity. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> --- drivers/irqchip/irq-gic-v5-irs.c | 85 +++++++++++++++++++++--------- include/linux/irqchip/arm-gic-v5.h | 2 + 2 files changed, 61 insertions(+), 26 deletions(-) diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-irs.c index f845415f9143..5f0324467142 100644 --- a/drivers/irqchip/irq-gic-v5-irs.c +++ b/drivers/irqchip/irq-gic-v5-irs.c @@ -8,6 +8,7 @@ #include <linux/log2.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/sort.h> #include <linux/irqchip.h> #include <linux/irqchip/arm-gic-v5.h> @@ -22,7 +23,7 @@ #define IRS_FLAGS_NON_COHERENT BIT(0) static DEFINE_PER_CPU_READ_MOSTLY(struct gicv5_irs_chip_data *, per_cpu_irs_data); -static LIST_HEAD(irs_nodes); +static struct gicv5_irs_chip_data **irs_nodes; static u32 irs_readl_relaxed(struct gicv5_irs_chip_data *irs_data, const u32 reg_offset) @@ -382,17 +383,19 @@ int gicv5_irs_cpu_to_iaffid(int cpuid, u16 *iaffid) struct gicv5_irs_chip_data *gicv5_irs_lookup_by_spi_id(u32 spi_id) { - struct gicv5_irs_chip_data *irs_data; - u32 min, max; - - list_for_each_entry(irs_data, &irs_nodes, entry) { - if (!irs_data->spi_range) - continue; - - min = irs_data->spi_min; - max = irs_data->spi_min + irs_data->spi_range - 1; - if (spi_id >= min && spi_id <= max) - return irs_data; + int l = 0, r = gicv5_global_data.irs_count - 1; + + while (l <= r) { + int m = (l + r) >> 1; + + if (irs_nodes[m]->spi_min <= spi_id && + spi_id <= irs_nodes[m]->spi_max) { + return irs_nodes[m]; + } else if (spi_id < irs_nodes[m]->spi_min) { + r = m - 1; + } else { + l = m + 1; + } } return NULL; @@ -489,7 +492,7 @@ void gicv5_irs_syncr(void) struct gicv5_irs_chip_data *irs_data; u32 syncr; - irs_data = list_first_entry_or_null(&irs_nodes, struct gicv5_irs_chip_data, entry); + irs_data = irs_nodes[0]; if (WARN_ON_ONCE(!irs_data)) return; @@ -673,7 +676,7 @@ static void irs_setup_pri_bits(u32 idr1) } } -static int __init gicv5_irs_init(struct device_node *node) +static int __init gicv5_irs_init(struct device_node *node, unsigned int *num) { struct gicv5_irs_chip_data *irs_data; void __iomem *irs_base; @@ -725,11 +728,11 @@ static int __init gicv5_irs_init(struct device_node *node) irs_data->spi_range = FIELD_GET(GICV5_IRS_IDR6_SPI_IRS_RANGE, idr); if (irs_data->spi_range) { + irs_data->spi_max = irs_data->spi_min + irs_data->spi_range - 1; pr_info("%s detected SPI range [%u-%u]\n", of_node_full_name(node), irs_data->spi_min, - irs_data->spi_min + - irs_data->spi_range - 1); + irs_data->spi_max); } /* @@ -737,8 +740,7 @@ static int __init gicv5_irs_init(struct device_node *node) * Global properties (iaffid_bits, global spi count) are guaranteed to * be consistent across IRSes by the architecture. */ - if (list_empty(&irs_nodes)) { - + if (*num == 0) { idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR1); irs_setup_pri_bits(idr); @@ -752,7 +754,7 @@ static int __init gicv5_irs_init(struct device_node *node) pr_debug("Detected %u SPIs globally\n", spi_count); } - list_add_tail(&irs_data->entry, &irs_nodes); + irs_nodes[*num] = irs_data; return 0; @@ -765,12 +767,14 @@ static int __init gicv5_irs_init(struct device_node *node) void __init gicv5_irs_remove(void) { - struct gicv5_irs_chip_data *irs_data, *tmp_data; + struct gicv5_irs_chip_data *irs_data; + int i; gicv5_free_lpi_domain(); gicv5_deinit_lpis(); - list_for_each_entry_safe(irs_data, tmp_data, &irs_nodes, entry) { + for (i = 0; i < gicv5_global_data.irs_count; i++) { + irs_data = irs_nodes[i]; iounmap(irs_data->irs_base); list_del(&irs_data->entry); kfree(irs_data); @@ -782,8 +786,7 @@ int __init gicv5_irs_enable(void) struct gicv5_irs_chip_data *irs_data; int ret; - irs_data = list_first_entry_or_null(&irs_nodes, - struct gicv5_irs_chip_data, entry); + irs_data = irs_nodes[0]; if (!irs_data) return -ENODEV; @@ -799,24 +802,54 @@ int __init gicv5_irs_enable(void) void __init gicv5_irs_its_probe(void) { struct gicv5_irs_chip_data *irs_data; + int i; - list_for_each_entry(irs_data, &irs_nodes, entry) + for (i = 0; i < gicv5_global_data.irs_count; i++) { + irs_data = irs_nodes[i]; gicv5_its_of_probe(to_of_node(irs_data->fwnode)); + } +} + +static int spi_min_cmp(const void *a, const void *b) +{ + const struct gicv5_irs_chip_data *irs_data1 = a; + const struct gicv5_irs_chip_data *irs_data2 = b; + + return irs_data1->spi_min - irs_data2->spi_min; } int __init gicv5_irs_of_probe(struct device_node *parent) { + unsigned int irs_count = 0, num = 0; struct device_node *np; int ret; + for_each_available_child_of_node(parent, np) { + if (of_device_is_compatible(np, "arm,gic-v5-irs")) + irs_count++; + } + + if (irs_count == 0) + return -ENODEV; + + irs_nodes = kzalloc(irs_count * sizeof(struct gicv5_irs_chip_data *), + __GFP_ZERO); + if (!irs_nodes) + return -ENOMEM; + for_each_available_child_of_node(parent, np) { if (!of_device_is_compatible(np, "arm,gic-v5-irs")) continue; - ret = gicv5_irs_init(np); + ret = gicv5_irs_init(np, &num); if (ret) pr_err("Failed to init IRS %s\n", np->full_name); + else + num++; } - return list_empty(&irs_nodes) ? -ENODEV : 0; + sort(irs_nodes, num, sizeof(struct gicv5_irs_chip_data *), spi_min_cmp, NULL); + gicv5_global_data.irs_count = num; + + return num > 0 ? 0 : -ENODEV; } diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h index 68ddcdb1cec5..6661b583b8d8 100644 --- a/include/linux/irqchip/arm-gic-v5.h +++ b/include/linux/irqchip/arm-gic-v5.h @@ -278,6 +278,7 @@ struct gicv5_chip_data { u8 cpuif_pri_bits; u8 cpuif_id_bits; u8 irs_pri_bits; + unsigned int irs_count; struct { __le64 *l1ist_addr; u32 l2_size; @@ -294,6 +295,7 @@ struct gicv5_irs_chip_data { void __iomem *irs_base; u32 flags; u32 spi_min; + u32 spi_max; u32 spi_range; raw_spinlock_t spi_config_lock; }; -- 2.34.1