virt inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICVB8V CVE: NA -------------------------------- Add the migration of GICR_INMIR0. vNMI migration for SPI is not supported, only supports SGI and PPI in guest. Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- arch/arm64/kvm/vgic/vgic-mmio-v3.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c index f9f47c91ee03..3289f2501ac0 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -642,6 +642,12 @@ static unsigned long vgic_mmio_read_nmi(struct kvm_vcpu *vcpu, return value; } +static unsigned long vgic_uaccess_read_nmi(struct kvm_vcpu *vcpu, + gpa_t addr, unsigned int len) +{ + return vgic_mmio_read_nmi(vcpu, addr, len); +} + static void vgic_mmio_write_nmi(struct kvm_vcpu *vcpu, gpa_t addr, unsigned int len, unsigned long val) { @@ -671,6 +677,13 @@ static void vgic_mmio_write_nmi(struct kvm_vcpu *vcpu, gpa_t addr, } } +static int vgic_uaccess_write_nmi(struct kvm_vcpu *vcpu, gpa_t addr, + unsigned int len, unsigned long val) +{ + vgic_mmio_write_nmi(vcpu, addr, len, val); + return 0; +} + /* * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the * redistributors, while SPIs are covered by registers in the distributor @@ -831,8 +844,9 @@ static const struct vgic_register_region vgic_v3_rd_registers[] = { REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR, vgic_mmio_read_raz, vgic_mmio_write_wi, 4, VGIC_ACCESS_32bit), - REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_INMIR0, - vgic_mmio_read_nmi, vgic_mmio_write_nmi, 4, + REGISTER_DESC_WITH_LENGTH_UACCESS(SZ_64K + GICR_INMIR0, + vgic_mmio_read_nmi, vgic_mmio_write_nmi, + vgic_uaccess_read_nmi, vgic_uaccess_write_nmi, 4, VGIC_ACCESS_32bit), }; -- 2.33.0