Add detection for the ARM64 Domain-based TLB Invalidation (TLBID) feature as defined in ARMv9.3-A architecture. TLBID allows TLB invalidation operations to be scoped to a specific domain, avoiding the need for global TLB invalidation broadcasts across the system. This reduces cache coherency traffic and improves performance in virtualization scenarios. Signed-off-by: Zeng Heng <zengheng4@huawei.com> --- arch/arm64/Kconfig | 12 ++++++++++++ arch/arm64/include/asm/cpufeature.h | 6 ++++++ arch/arm64/kernel/cpufeature.c | 10 ++++++++++ arch/arm64/tools/cpucaps | 1 + arch/arm64/tools/sysreg | 6 +++++- 5 files changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 74e4639776de..7a7f67435d4f 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -2423,6 +2423,18 @@ config ARM64_HAFT endmenu # "ARMv8.8 architectural features" +menu "ARMv9.3 architectural features" + +config ARM64_TLBID + bool "Domain based ARM64 TLB invalidation" + default y + help + TLBI broadcasting all PEs introduces performance noise. By combining + hardware and software, TLBID (TLBI Domain) limit TLBI to an appropriate + scope, avoiding the performance overhead caused by broadcasting. + +endmenu # "ARMv9.3 architectural features" + menu "ARMv9.5 architectural features" config ARM64_HDBSS diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 6f73a51d2422..ede803987e11 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -887,6 +887,12 @@ static inline bool system_supports_tlb_range(void) cpus_have_const_cap(ARM64_HAS_TLB_RANGE); } +static inline bool system_supports_tlbid(void) +{ + return IS_ENABLED(CONFIG_ARM64_TLBID) && + cpus_have_const_cap(ARM64_HAS_TLBID); +} + static inline bool cpus_support_mpam(void) { return IS_ENABLED(CONFIG_ARM64_MPAM) && diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index a65285802864..661e73ffab89 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -414,6 +414,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_TLBID_SHIFT, 4, 0), S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), ARM64_FTR_END, }; @@ -3161,6 +3162,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_arch_xcall_xint_support, .cpu_enable = cpu_enable_arch_xcall_xint, }, +#endif +#ifdef CONFIG_ARM64_TLBID + { + .desc = "Domain based ARM64 TLB invalidation", + .capability = ARM64_HAS_TLBID, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .matches = has_cpuid_feature, + ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, TLBID, IMP) + }, #endif {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index d8f2db273def..16e8e66ad913 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -50,6 +50,7 @@ HAS_STAGE2_FWB HAS_TCR2 HAS_TIDCP1 HAS_TLB_RANGE +HAS_TLBID HAS_TWED HAS_VIRT_HOST_EXTN HAS_WFXT diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 618fbc647c04..2a5f26b4c960 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1805,7 +1805,11 @@ EndEnum EndSysreg Sysreg ID_AA64MMFR4_EL1 3 0 0 7 4 -Res0 63:40 +Res0 63:44 +UnsignedEnum 43:40 TLBID + 0b0000 NI + 0b0001 IMP +EndEnum UnsignedEnum 39:36 E3DSE 0b0000 NI 0b0001 IMP -- 2.25.1