From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> mainline inclusion from mainline-v6.15-rc1 commit c8c2647e69bedf803244eabc80e2e0757f9c33d6 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/IBN3WI Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?i... ---------------------------------------------------------------------- Subsequent patch will add target implementation CPU support and that will require _midr_in_range_list() to access new data. To avoid exporting the data make _midr_in_range_list() a normal function and export it. No functional changes intended. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20250221140229.12588-5-shameerali.kolothum.thodi@h... Signed-off-by: Oliver Upton <oliver.upton@linux.dev> --- arch/arm64/include/asm/cache.h | 2 +- arch/arm64/include/asm/cputype.h | 10 +++++++--- arch/arm64/kernel/cpu_errata.c | 15 +++++++++++++++ 3 files changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 01dabe4c41fa..62fac127d889 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -124,7 +124,7 @@ static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void) MIDR_REV(MIDR_HISI_LINXICORE9100, 1, 0), { /* sentinel */ } }; - if (is_midr_in_range_list(idc_support_list)) + if (_is_midr_in_range_list(idc_support_list)) ctr |= BIT(CTR_EL0_IDC_SHIFT); #endif diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index d6744cc36d60..6ebb34d1dd21 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -300,20 +300,24 @@ static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min, return _model == model && rv >= rv_min && rv <= rv_max; } -static inline bool is_midr_in_range(struct midr_range const *range) +bool is_midr_in_range_list(struct midr_range const *ranges); + +#ifdef CONFIG_HISILICON_ERRATUM_1980005 +static inline bool _is_midr_in_range(struct midr_range const *range) { return midr_is_cpu_model_range(read_cpuid_id(), range->model, range->rv_min, range->rv_max); } static inline bool -is_midr_in_range_list(struct midr_range const *ranges) +_is_midr_in_range_list(struct midr_range const *ranges) { while (ranges->model) - if (is_midr_in_range(ranges++)) + if (_is_midr_in_range(ranges++)) return true; return false; } +#endif static inline u64 __attribute_const__ read_cpuid_mpidr(void) { diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 5617f4767c2f..803349fdfe31 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -19,6 +19,21 @@ #include <linux/smp.h> #endif +static inline bool is_midr_in_range(struct midr_range const *range) +{ + return midr_is_cpu_model_range(read_cpuid_id(), range->model, + range->rv_min, range->rv_max); +} + +bool is_midr_in_range_list(struct midr_range const *ranges) +{ + while (ranges->model) + if (is_midr_in_range(ranges++)) + return true; + return false; +} +EXPORT_SYMBOL_GPL(is_midr_in_range_list); + static bool __maybe_unused __is_affected_midr_range(const struct arm64_cpu_capabilities *entry, u32 midr, u32 revidr) -- 2.33.0