From: Junhao He <hejunhao3@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- a) Each data flit unit is a byte, not a bit. b) Add support for HiSilicon UC PMU aliasing Signed-off-by: Junhao He <hejunhao3@huawei.com> Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- .../hisilicon/hip09/sys/uncore-ddrc.json | 6 +- .../arm64/hisilicon/hip09/sys/uncore-hha.json | 4 +- .../arm64/hisilicon/hip09/sys/uncore-uc.json | 376 ++++++++++++++++++ 3 files changed, 381 insertions(+), 5 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-uc.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json index 331a44d2eb59..8facfb35ea89 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json @@ -99,7 +99,7 @@ }, { "MetricName": "ddrc_write_bw", - "MetricExpr": "flux_wr * 4 / duration_time / 1e6", + "MetricExpr": "flux_wr * 32 / duration_time / 1e6", "MetricGroup": "DDRC_bw", "BriefDescription": "Average bandwidth of write DDRC memory", "ScaleUnit": "1MB/s", @@ -108,7 +108,7 @@ }, { "MetricName": "ddrc_read_bw", - "MetricExpr": "flux_rd * 4 / duration_time / 1e6", + "MetricExpr": "flux_rd * 32 / duration_time / 1e6", "MetricGroup": "DDRC_bw", "BriefDescription": "Average bandwidth of read DDRC memory", "ScaleUnit": "1MB/s", @@ -117,7 +117,7 @@ }, { "MetricName": "ddrc_rdwr_bw", - "MetricExpr": "(flux_wr + flux_rd) * 4 / duration_time / 1e6", + "MetricExpr": "(flux_wr + flux_rd) * 32 / duration_time / 1e6", "MetricGroup": "DDRC_bw", "BriefDescription": "Average bandwidth of DDRC (including memory read and write)", "ScaleUnit": "1MB/s", diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json index 6e3eac3ba80c..c294aeecd2ca 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json @@ -127,7 +127,7 @@ }, { "MetricName": "hha_read_ddrc_bw", - "MetricExpr": "(hha_rd_ddr_64b * 8 + hha_rd_ddr_128b * 16) / duration_time / 1e6", + "MetricExpr": "(hha_rd_ddr_64b * 64 + hha_rd_ddr_128b * 128) / duration_time / 1e6", "MetricGroup": "HHA_bw", "BriefDescription": "Average bandwidth of reading DDRC", "ScaleUnit": "1MB/s", @@ -136,7 +136,7 @@ }, { "MetricName": "hha_write_ddrc_bw", - "MetricExpr": "(hha_wr_ddr_64b * 8 + hha_wr_ddr_128b * 16) / duration_time / 1e6", + "MetricExpr": "(hha_wr_ddr_64b * 64 + hha_wr_ddr_128b * 128) / duration_time / 1e6", "MetricGroup": "HHA_bw", "BriefDescription": "Average bandwidth of writing DDRC", "ScaleUnit": "1MB/s", diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-uc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-uc.json new file mode 100644 index 000000000000..42e64ecbc4b3 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-uc.json @@ -0,0 +1,376 @@ +[ + { + "EventCode": "0x00", + "EventName": "sq_time", + "Filter": "rd_req_en=1", + "BriefDescription": "Count the total latency that sq completed cpu request", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x01", + "EventName": "pq_time", + "Filter": "rd_req_en=1", + "BriefDescription": "Count the total latency that pq completed cpu request", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x02", + "EventName": "hbm_time", + "Filter": "rd_req_en=1", + "BriefDescription": "Count the total latency that UC requests to access the HBM", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x03", + "EventName": "iq_comp_time_cring", + "Filter": "rd_req_en=1", + "BriefDescription": "Count the total latency that CRING completed cpu request", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x05", + "EventName": "iq_comp_time_uring", + "Filter": "rd_req_en=1", + "BriefDescription": "Count the total latency that URING completed cpu request", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x10", + "EventName": "cpu_rd", + "BriefDescription": "Count of the number of the read request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x11", + "EventName": "cpu_wr", + "BriefDescription": "Count of the number of the write request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x12", + "EventName": "cpu_atomic", + "BriefDescription": "Count of the number of the atomic request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x17", + "EventName": "cpu_rd64", + "BriefDescription": "Count of the number of the cpu_rd64 request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x19", + "EventName": "cpu_rs64", + "BriefDescription": "Count of the number of the cpu_rs64 request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x1C", + "EventName": "cpu_mru", + "BriefDescription": "Count of the number of the cpu_mru request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x2C", + "EventName": "ext2uc_read", + "BriefDescription": "Count of the number of the read request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x2D", + "EventName": "ext2uc_write", + "BriefDescription": "Count of the number of the write request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x2E", + "EventName": "ext2uc_atomic", + "BriefDescription": "Count of the number of the atomic request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x47", + "EventName": "uc2ext_read_uring", + "BriefDescription": "Count of the number of the read request from uc to uring", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x48", + "EventName": "uc2ext_write_uring", + "BriefDescription": "Count of the number of the write request from uc to uring", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x49", + "EventName": "uc2ext_atomic_uring", + "BriefDescription": "Count of the number of the atomic message sent by the UC from the URIING to the EXT", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x5C", + "EventName": "io2uc_atomic", + "BriefDescription": "Count of the number of the I/O Atomic messages received by the UC", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x60", + "EventName": "io2uc_write", + "BriefDescription": "Count of the number of the UC receives a write request from the I/O", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x7E", + "EventName": "uc2cpu_retry", + "BriefDescription": "Count of the number of the retry packets sent from the UC to the CPU", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x7F", + "EventName": "uc2ext_retry", + "BriefDescription": "Count of the number of the retry sent from the UC to the EXT", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x81", + "EventName": "uc2hbm_bank0_rd64", + "BriefDescription": "Count of the number of the 64B read request sent by the UC to HBMC BANK0", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x82", + "EventName": "uc2hbm_bank0_rd128", + "BriefDescription": "Count of the number of the 128B read request sent from the UC to HBMC BANK0", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x83", + "EventName": "uc2hbm_bank0_wr64", + "BriefDescription": "Count of the number of the 64B write request sent by the UC to HBMC BANK0", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x84", + "EventName": "uc2hbm_bank0_wr128", + "BriefDescription": "Count of the number of the 128B write request sent by the UC to HBMC BANK0", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x87", + "EventName": "uc2hbm_bank1_rd64", + "BriefDescription": "Count of the number of the 64B read request sent by the UC to HBMC BANK1", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x88", + "EventName": "uc2hbm_bank1_rd128", + "BriefDescription": "Count of the number of the 128B read request sent by the UC to HBMC BANK1", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x89", + "EventName": "uc2hbm_bank1_wr64", + "BriefDescription": "Count of the number of the 64B write request sent from the UC to HBMC BANK1", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x8A", + "EventName": "uc2hbm_bank1_wr128", + "BriefDescription": "Count of the number of the 128B write request sent from the UC to HBMC BANK1", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x8D", + "EventName": "uc2sdmaa_retry", + "BriefDescription": "Count of the number of retry messages received by the SDMAA module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x8E", + "EventName": "uc2sdmaa_pgnt", + "BriefDescription": "Count of the number of pgnt messages received by the SDMAA module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x8F", + "EventName": "sdmaa2uc_unalign", + "BriefDescription": "Count of the number of Unaligned Small Packets Delivered by SDMAA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x91", + "EventName": "sdmaa2uc_read", + "BriefDescription": "Count of the number of SDMAA Read Requests", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x92", + "EventName": "sdmaa2uc_write", + "BriefDescription": "Count of the number of SDMAA Write Requests", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x93", + "EventName": "sdmaa2uc_memset", + "BriefDescription": "Count of the number of memsets delivered by SDMAA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x94", + "EventName": "sdmaa_tx_preload", + "BriefDescription": "Count of the number of preload operations delivered by the SDMAA module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x95", + "EventName": "cycles", + "BriefDescription": "Count of the nUC cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xB3", + "EventName": "spipe_hit", + "BriefDescription": "Count of the number of spipe hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xDB", + "EventName": "hpipe_hit", + "BriefDescription": "Count of the number of hpipe hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFA", + "EventName": "cring_rxdat_cnt", + "BriefDescription": "Count of the number of packets received by the UC from the cring", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFB", + "EventName": "cring_txdat_cnt", + "BriefDescription": "Count of the number of packets sent from the UC to the CRING", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFC", + "EventName": "uring_rxdat_cnt", + "BriefDescription": "Count of the number of Indicates the number of packets received by the UC from the uring module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFD", + "EventName": "uring_txdat_cnt", + "BriefDescription": "Count of the number of Indicates the number of packets sent from the UC to the enabling module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFE", + "EventName": "uring_rxreqdat_cnt", + "BriefDescription": "Count of the number of data combination request packets received by the UC from the uring module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFF", + "EventName": "uring_txreqdat_cnt", + "BriefDescription": "Count of the number of data combination requests sent by the UC to the uring module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2cring_rxdat_bw", + "MetricExpr": "cring_rxdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC access CRing", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2cring_txdat_bw", + "MetricExpr": "cring_txdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2uring_rxdat_bw", + "MetricExpr": "uring_rxdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2uring_txdat_bw", + "MetricExpr": "uring_txdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2hbm_rd_bw", + "MetricExpr": "(uc2hbm_bank0_rd64 * 64 + uc2hbm_bank0_rd128 * 128 + uc2hbm_bank1_rd64 * 64 + uc2hbm_bank1_rd128 * 128) / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average latency of UC reading HBM", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2hbm_wr_bw", + "MetricExpr": "(uc2hbm_bank0_wr64 * 64 + uc2hbm_bank0_wr128 * 128 + uc2hbm_bank1_wr64 * 64 + uc2hbm_bank1_wr128 * 128) / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average latency of UC writing HBM", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + } +] -- 2.43.0