hulk inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/ICXIBU -------------------------------- On certain platforms, the Cache Storage Usage monitor statistics need to half. Due to the L3 cache compression feature on some hisi chips, the L3 CSU counter shows a value twice the actual usage, which does not reflect the real occupancy. To mitigate this effect as much as possible, the statistic method needs to half the statistic. With L3 compression disabled, the halved value matches the real L3 usage. However, with L3 compression enabled, it becomes slightly lower than the real L3 occupancy. Fixes: bb66b4d115e5 ("arm_mpam: Add mpam_msmon_read() to read monitor value") Signed-off-by: Zeng Heng <zengheng4@huawei.com> --- drivers/platform/mpam/mpam_devices.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/platform/mpam/mpam_devices.c b/drivers/platform/mpam/mpam_devices.c index 1037703e3791..c5b6a2511c93 100644 --- a/drivers/platform/mpam/mpam_devices.c +++ b/drivers/platform/mpam/mpam_devices.c @@ -952,6 +952,23 @@ static bool mpam_ris_has_nrdy_bit(struct mpam_msc_ris *ris) return true; } +static u64 mpam_csu_hisi_need_halved(struct mpam_msc_ris *ris, u64 now) +{ + static const struct midr_range cpus[] = { + MIDR_ALL_VERSIONS(MIDR_HISI_HIP12), + { /* sentinel */ } + }; + + if (!is_midr_in_range_list(read_cpuid_id(), cpus)) + return now; + + if (ris->comp->class->type != MPAM_CLASS_CACHE || + ris->comp->class->level != 3) + return now; + + return now >> 1; +} + static void __ris_msmon_read(void *arg) { bool nrdy = false; @@ -1007,6 +1024,7 @@ static void __ris_msmon_read(void *arg) now = mpam_read_monsel_reg(msc, CSU); nrdy = now & MSMON___NRDY; now = FIELD_GET(MSMON___VALUE, now); + now = mpam_csu_hisi_need_halved(ris, now); break; case mpam_feat_msmon_mbwu: /* -- 2.25.1