From: Marc Zyngier <maz@kernel.org> mainline inclusion from mainline-v5.4-rc1 commit 363518f37a86acc515defae6d1ba91a6c7617de9 category: feature feature: ITS translation cache ------------------------------------------------- If an ITS gets disabled, we need to make sure that further interrupts won't hit in the cache. For that, we invalidate the translation cache when the ITS is disabled. Tested-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Reviewed-by: Hailiang Zhang <zhang.zhanghailiang@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> --- virt/kvm/arm/vgic/vgic-its.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c index aecf55f..d5b2406 100644 --- a/virt/kvm/arm/vgic/vgic-its.c +++ b/virt/kvm/arm/vgic/vgic-its.c @@ -1608,6 +1608,8 @@ static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its, goto out; its->enabled = !!(val & GITS_CTLR_ENABLE); + if (!its->enabled) + vgic_its_invalidate_cache(kvm); /* * Try to process any pending commands. This function bails out early -- 1.8.3