From: He Chuyue <hechuyue@wxiat.com> Sunway inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I56X48 -------------------------------- According to CORE3B core software interface manual, the performance counter PC_1 on sw64 supports event index up to 0x3d. Now fix it, and remove some unused macros from wrperfmon.h. Signed-off-by: He Chuyue <hechuyue@wxiat.com> Signed-off-by: Gu Zitao <guzitao@wxiat.com> --- arch/sw_64/include/asm/wrperfmon.h | 4 +--- arch/sw_64/kernel/perf_event.c | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/sw_64/include/asm/wrperfmon.h b/arch/sw_64/include/asm/wrperfmon.h index 098702573bfc..15f7f6beb07c 100644 --- a/arch/sw_64/include/asm/wrperfmon.h +++ b/arch/sw_64/include/asm/wrperfmon.h @@ -33,10 +33,8 @@ #define PC0_RAW_BASE 0x0 #define PC1_RAW_BASE 0x100 -#define PC0_MIN 0x0 #define PC0_MAX 0xF -#define PC1_MIN 0x0 -#define PC1_MAX 0x37 +#define PC1_MAX 0x3D #define SW64_PERFCTRL_KM 2 #define SW64_PERFCTRL_UM 3 diff --git a/arch/sw_64/kernel/perf_event.c b/arch/sw_64/kernel/perf_event.c index 70f1f2781016..e9aae53a56f6 100644 --- a/arch/sw_64/kernel/perf_event.c +++ b/arch/sw_64/kernel/perf_event.c @@ -244,7 +244,7 @@ static const struct sw64_perf_event *core3_map_cache_event(u64 config) /* * r0xx for counter0, r1yy for counter1. - * According to the datasheet, 00 <= xx <= 0F, 00 <= yy <= 37 + * According to the datasheet, 00 <= xx <= 0F, 00 <= yy <= 3D */ static bool core3_raw_event_valid(u64 config) { -- 2.17.1