From: Yuyu Li <liyuyu6@huawei.com> driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/ICAF19 CVE: NA ---------------------------------------------------------------------- Previously, the DCQCN, LDCP, and HC3 algorithms had incorrect individual parameter ranges, this patch will fix it. Fixes: 41da9cd8456d ("RDMA/hns: Support congestion control algorithm parameter configuration") Signed-off-by: Yuyu Li <liyuyu6@huawei.com> Signed-off-by: Donghua Huang <huangdonghua3@h-partners.com> --- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 22 +++++++++++++++------- drivers/infiniband/hw/hns/hns_roce_sysfs.c | 3 ++- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index fa5a02457af6..3d519b828cbd 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -1483,7 +1483,7 @@ struct hns_roce_wqe_atomic_seg { #define HNS_ROCE_DCQCN_F_MAX ((u8)(~0U)) #define HNS_ROCE_DCQCN_TKP_OFS (HNS_ROCE_DCQCN_F_OFS + HNS_ROCE_DCQCN_F_SZ) #define HNS_ROCE_DCQCN_TKP_SZ sizeof(u8) -#define HNS_ROCE_DCQCN_TKP_MAX 15 +#define HNS_ROCE_DCQCN_TKP_MAX 10 #define HNS_ROCE_DCQCN_TMP_OFS (HNS_ROCE_DCQCN_TKP_OFS + HNS_ROCE_DCQCN_TKP_SZ) #define HNS_ROCE_DCQCN_TMP_SZ sizeof(u16) #define HNS_ROCE_DCQCN_TMP_MAX 15 @@ -1523,47 +1523,55 @@ struct hns_roce_wqe_atomic_seg { #define HNS_ROCE_LDCP_GAMMA_OFS (HNS_ROCE_LDCP_ALPHA_OFS + \ HNS_ROCE_LDCP_ALPHA_SZ) #define HNS_ROCE_LDCP_GAMMA_SZ sizeof(u8) -#define HNS_ROCE_LDCP_GAMMA_MAX ((u8)(~0U)) +#define HNS_ROCE_LDCP_GAMMA_MAX 7 #define HNS_ROCE_LDCP_BETA_OFS (HNS_ROCE_LDCP_GAMMA_OFS + \ HNS_ROCE_LDCP_GAMMA_SZ) #define HNS_ROCE_LDCP_BETA_SZ sizeof(u8) -#define HNS_ROCE_LDCP_BETA_MAX ((u8)(~0U)) +#define HNS_ROCE_LDCP_BETA_MAX 7 #define HNS_ROCE_LDCP_ETA_OFS (HNS_ROCE_LDCP_BETA_OFS + HNS_ROCE_LDCP_BETA_SZ) #define HNS_ROCE_LDCP_ETA_SZ sizeof(u8) -#define HNS_ROCE_LDCP_ETA_MAX ((u8)(~0U)) +#define HNS_ROCE_LDCP_ETA_MAX 7 #define HNS_ROCE_LDCP_LIFESPAN_OFS (4 * sizeof(u32)) #define HNS_ROCE_LDCP_LIFESPAN_SZ sizeof(u32) #define HNS_ROCE_LDCP_LIFESPAN_MAX 1000 #define HNS_ROCE_HC3_INITIAL_WINDOW_OFS 0 #define HNS_ROCE_HC3_INITIAL_WINDOW_SZ sizeof(u32) +#define HNS_ROCE_HC3_INITIAL_WINDOW_MIN 0 #define HNS_ROCE_HC3_INITIAL_WINDOW_MAX ((u32)(~0U)) #define HNS_ROCE_HC3_BANDWIDTH_OFS (HNS_ROCE_HC3_INITIAL_WINDOW_OFS + \ HNS_ROCE_HC3_INITIAL_WINDOW_SZ) #define HNS_ROCE_HC3_BANDWIDTH_SZ sizeof(u32) +#define HNS_ROCE_HC3_BANDWIDTH_MIN 1000 #define HNS_ROCE_HC3_BANDWIDTH_MAX ((u32)(~0U)) #define HNS_ROCE_HC3_QLEN_SHIFT_OFS (HNS_ROCE_HC3_BANDWIDTH_OFS + \ HNS_ROCE_HC3_BANDWIDTH_SZ) #define HNS_ROCE_HC3_QLEN_SHIFT_SZ sizeof(u8) -#define HNS_ROCE_HC3_QLEN_SHIFT_MAX ((u8)(~0U)) +#define HNS_ROCE_HC3_QLEN_SHIFT_MIN 0 +#define HNS_ROCE_HC3_QLEN_SHIFT_MAX 31 #define HNS_ROCE_HC3_PORT_USAGE_SHIFT_OFS (HNS_ROCE_HC3_QLEN_SHIFT_OFS + \ HNS_ROCE_HC3_QLEN_SHIFT_SZ) #define HNS_ROCE_HC3_PORT_USAGE_SHIFT_SZ sizeof(u8) -#define HNS_ROCE_HC3_PORT_USAGE_SHIFT_MAX ((u8)(~0U)) +#define HNS_ROCE_HC3_PORT_USAGE_SHIFT_MIN 0 +#define HNS_ROCE_HC3_PORT_USAGE_SHIFT_MAX 100 #define HNS_ROCE_HC3_OVER_PERIOD_OFS (HNS_ROCE_HC3_PORT_USAGE_SHIFT_OFS + \ HNS_ROCE_HC3_PORT_USAGE_SHIFT_SZ) #define HNS_ROCE_HC3_OVER_PERIOD_SZ sizeof(u8) +#define HNS_ROCE_HC3_OVER_PERIOD_MIN 0 #define HNS_ROCE_HC3_OVER_PERIOD_MAX ((u8)(~0U)) #define HNS_ROCE_HC3_MAX_STAGE_OFS (HNS_ROCE_HC3_OVER_PERIOD_OFS + \ HNS_ROCE_HC3_OVER_PERIOD_SZ) #define HNS_ROCE_HC3_MAX_STAGE_SZ sizeof(u8) +#define HNS_ROCE_HC3_MAX_STAGE_MIN 0 #define HNS_ROCE_HC3_MAX_STAGE_MAX ((u8)(~0U)) #define HNS_ROCE_HC3_GAMMA_SHIFT_OFS (HNS_ROCE_HC3_MAX_STAGE_OFS + \ HNS_ROCE_HC3_MAX_STAGE_SZ) #define HNS_ROCE_HC3_GAMMA_SHIFT_SZ sizeof(u8) +#define HNS_ROCE_HC3_GAMMA_SHIFT_MIN 0 #define HNS_ROCE_HC3_GAMMA_SHIFT_MAX 15 #define HNS_ROCE_HC3_LIFESPAN_OFS (4 * sizeof(u32)) #define HNS_ROCE_HC3_LIFESPAN_SZ sizeof(u32) +#define HNS_ROCE_HC3_LIFESPAN_MIN 0 #define HNS_ROCE_HC3_LIFESPAN_MAX 1000 #define HNS_ROCE_DIP_AI_OFS 0 @@ -1574,7 +1582,7 @@ struct hns_roce_wqe_atomic_seg { #define HNS_ROCE_DIP_F_MAX ((u8)(~0U)) #define HNS_ROCE_DIP_TKP_OFS (HNS_ROCE_DIP_F_OFS + HNS_ROCE_DIP_F_SZ) #define HNS_ROCE_DIP_TKP_SZ sizeof(u8) -#define HNS_ROCE_DIP_TKP_MAX 15 +#define HNS_ROCE_DIP_TKP_MAX 10 #define HNS_ROCE_DIP_TMP_OFS (HNS_ROCE_DIP_TKP_OFS + HNS_ROCE_DIP_TKP_SZ) #define HNS_ROCE_DIP_TMP_SZ sizeof(u16) #define HNS_ROCE_DIP_TMP_MAX 15 diff --git a/drivers/infiniband/hw/hns/hns_roce_sysfs.c b/drivers/infiniband/hw/hns/hns_roce_sysfs.c index 0ccc75ccb434..cebb0229dd08 100644 --- a/drivers/infiniband/hw/hns/hns_roce_sysfs.c +++ b/drivers/infiniband/hw/hns/hns_roce_sysfs.c @@ -279,7 +279,8 @@ static const struct attribute_group ldcp_cc_param_group = { __HNS_SCC_ATTR(_name, HNS_ROCE_SCC_ALGO_HC3, \ HNS_ROCE_HC3_##NAME##_OFS, \ HNS_ROCE_HC3_##NAME##_SZ, \ - 0, HNS_ROCE_HC3_##NAME##_MAX) + HNS_ROCE_HC3_##NAME##_MIN, \ + HNS_ROCE_HC3_##NAME##_MAX) HNS_PORT_HC3_CC_ATTR_RW(initial_window, INITIAL_WINDOW); HNS_PORT_HC3_CC_ATTR_RW(bandwidth, BANDWIDTH); -- 2.33.0