From: lizhi <lizhi206@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/IDC64W CVE: NA ---------------------------------------------------------------------- Lower the priority of HiSilicon's crypto implementations to allow more suitable alternatives to be selected. For example, certain kernel use-cases do not benefit from HiSilicon's symmetric crypto algorithms. This change ensures that more appropriate options are chosen first while retaining HiSilicon's implementations as alternatives. Signed-off-by: lizhi <lizhi206@huawei.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- drivers/crypto/hisilicon/hpre/hpre_crypto.c | 2 +- drivers/crypto/hisilicon/sec2/sec_crypto.c | 2 +- drivers/crypto/hisilicon/zip/zip_crypto.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/hisilicon/hpre/hpre_crypto.c b/drivers/crypto/hisilicon/hpre/hpre_crypto.c index 94d1cc90083d..c83a6868ffc8 100644 --- a/drivers/crypto/hisilicon/hpre/hpre_crypto.c +++ b/drivers/crypto/hisilicon/hpre/hpre_crypto.c @@ -19,7 +19,7 @@ struct hpre_ctx; -#define HPRE_CRYPTO_ALG_PRI 1000 +#define HPRE_CRYPTO_ALG_PRI 80 #define HPRE_ALIGN_SZ 64 #define HPRE_BITS_2_BYTES_SHIFT 3 #define HPRE_RSA_512BITS_KSZ 64 diff --git a/drivers/crypto/hisilicon/sec2/sec_crypto.c b/drivers/crypto/hisilicon/sec2/sec_crypto.c index d8cca441db27..438e7ba8f9ec 100644 --- a/drivers/crypto/hisilicon/sec2/sec_crypto.c +++ b/drivers/crypto/hisilicon/sec2/sec_crypto.c @@ -20,7 +20,7 @@ #include "sec.h" #include "sec_crypto.h" -#define SEC_PRIORITY 4001 +#define SEC_PRIORITY 80 #define SEC_XTS_MIN_KEY_SIZE (2 * AES_MIN_KEY_SIZE) #define SEC_XTS_MID_KEY_SIZE (3 * AES_MIN_KEY_SIZE) #define SEC_XTS_MAX_KEY_SIZE (2 * AES_MAX_KEY_SIZE) diff --git a/drivers/crypto/hisilicon/zip/zip_crypto.c b/drivers/crypto/hisilicon/zip/zip_crypto.c index 21cd47ceed75..4856bedd8b87 100644 --- a/drivers/crypto/hisilicon/zip/zip_crypto.c +++ b/drivers/crypto/hisilicon/zip/zip_crypto.c @@ -21,7 +21,7 @@ #define HZIP_BUF_TYPE_M GENMASK(11, 8) #define HZIP_SGL 0x1 -#define HZIP_ALG_PRIORITY 300 +#define HZIP_ALG_PRIORITY 80 #define HZIP_SGL_SGE_NR 10 #define HZIP_ALG_DEFLATE GENMASK(5, 4) -- 2.43.0