From: lvjianmin <lvjianmin@loongson.cn> LoongArch inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/IC1M5U CVE: NA -------------------------------- Ths first EOP packet with a sequence number as seq-1 seems to confuse some PCIe hardware (e.g. Loongson 7A PCHs). Use the real sequence number instead. Change-Id: I58a07771158df536e8aaedb6dab9b9c29c28f08a Fixes: a9c73a0 ("drm/radeon: workaround for CP HW bug on CIK") Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: lvjianmin <lvjianmin@loongson.cn> --- drivers/gpu/drm/radeon/cik.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index c2d6b723aea8..e5f0daa38f9f 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -3543,9 +3543,7 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, struct radeon_ring *ring = &rdev->ring[fence->ring]; u64 addr = rdev->fence_drv[fence->ring].gpu_addr; - /* Workaround for cache flush problems. First send a dummy EOP - * event down the pipe with seq one below. - */ + /* Workaround for cache flush problems by sending the EOP event twice */ radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | @@ -3554,10 +3552,13 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev, radeon_ring_write(ring, addr & 0xfffffffc); radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(0)); +#ifdef CONFIG_LOONGARCH + radeon_ring_write(ring, fence->seq); +#else radeon_ring_write(ring, fence->seq - 1); +#endif radeon_ring_write(ring, 0); - /* Then send the real EOP event down the pipe. */ radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | -- 2.33.0