[PATCH OLK-6.6 1/2] perf jevents: add some pmu event and metric

driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- Add support for cpa,ddrc,hha,l3c,pa,sllc,uc,mn,topdown pmu-event and metric. Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> --- .../hisilicon/hip09/uncore-cpa-metric.json | 20 + .../hisilicon/hip09/uncore-ddrc-metric.json | 56 +++ .../hisilicon/hip09/uncore-hha-metric.json | 65 +++ .../hisilicon/hip09/uncore-l3c-metric.json | 38 ++ .../hisilicon/hip09/uncore-pa-metric.json | 92 ++++ .../hisilicon/hip09/uncore-sllc-metric.json | 74 +++ .../hisilicon/hip09/uncore-uc-metric.json | 146 ++++++ .../arm64/hisilicon/hip12/core-imp-def.json | 125 +++++ .../arch/arm64/hisilicon/hip12/metrics.json | 459 +++++++++++++++++ .../hisilicon/hip12/uncore-cpa-metric.json | 20 + .../hisilicon/hip12/uncore-ddrc-metric.json | 56 +++ .../hisilicon/hip12/uncore-hha-metric.json | 65 +++ .../hisilicon/hip12/uncore-l3c-metric.json | 38 ++ .../hisilicon/hip12/uncore-mn-metric.json | 58 +++ .../hisilicon/hip12/uncore-noc-metric.json | 38 ++ .../hisilicon/hip12/uncore-pa-metric.json | 92 ++++ .../hisilicon/hip12/uncore-sllc-metric.json | 74 +++ .../{hip09 => hipxx}/sys/uncore-cpa.json | 16 - .../hisilicon/hipxx/sys/uncore-ddrc.json | 100 ++++ .../arm64/hisilicon/hipxx/sys/uncore-hha.json | 128 +++++ .../arm64/hisilicon/hipxx/sys/uncore-l3c.json | 448 +++++++++++++++++ .../arm64/hisilicon/hipxx/sys/uncore-mn.json | 163 ++++++ .../arm64/hisilicon/hipxx/sys/uncore-noc.json | 329 +++++++++++++ .../arm64/hisilicon/hipxx/sys/uncore-pa.json | 184 +++++++ .../hisilicon/hipxx/sys/uncore-sllc.json | 132 +++++ .../arm64/hisilicon/hipxx/sys/uncore-uc.json | 462 ++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + tools/perf/pmu-events/jevents.py | 2 + 28 files changed, 3466 insertions(+), 16 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-cpa-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-ddrc-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-hha-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-l3c-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-pa-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-sllc-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-uc-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/core-imp-def.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/metrics.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-cpa-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-ddrc-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-hha-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-mn-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-noc-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-pa-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-sllc-metric.json rename tools/perf/pmu-events/arch/arm64/hisilicon/{hip09 => hipxx}/sys/uncore-cpa.json (76%) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-ddrc.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-hha.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-mn.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-noc.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-pa.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-sllc.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-uc.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-cpa-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-cpa-metric.json new file mode 100644 index 000000000000..1ead2819abe0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-cpa-metric.json @@ -0,0 +1,20 @@ +[ + { + "MetricName": "cpa_p1_avg_bw", + "MetricExpr": "(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / duration_time / 1e6", + "BriefDescription": "Average bandwidth of CPA Port 1", + "MetricGroup": "CPA_bw", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "MetricName": "cpa_p0_avg_bw", + "MetricExpr": "(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / duration_time / 1e6", + "BriefDescription": "Average bandwidth of CPA Port 0", + "MetricGroup": "CPA_bw", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-ddrc-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-ddrc-metric.json new file mode 100644 index 000000000000..b4a95fd53b76 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-ddrc-metric.json @@ -0,0 +1,56 @@ +[ + { + "MetricName": "ddrc_write_bw", + "MetricExpr": "flux_wr * 32 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of write DDRC memory", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_read_bw", + "MetricExpr": "flux_rd * 32 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of read DDRC memory", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_rdwr_bw", + "MetricExpr": "(flux_wr + flux_rd) * 32 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of DDRC (including memory read and write)", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_read_lat", + "MetricExpr": "ddrc_read_cmd_occupancy / ddrc_read_cmd * (duration_time * 1e9 / ddrc_cycles)", + "MetricGroup": "DDRC_lat", + "BriefDescription": "Average scheduling latency of DDRC read command", + "ScaleUnit": "1ns", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_write_lat", + "MetricExpr": "ddrc_write_cmd_occupancy / ddrc_write_cmd * (duration_time * 1e9 / ddrc_cycles)", + "MetricGroup": "DDRC_lat", + "BriefDescription": "Average scheduling of DDRC write command", + "ScaleUnit": "1ns", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_rowhit_rate", + "MetricExpr": "1 - ddrc_active_cmd / ddrc_cas_cmd", + "MetricGroup": "DDRC", + "BriefDescription": "Row hit rate of DDRC", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-hha-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-hha-metric.json new file mode 100644 index 000000000000..1232f30f5b0a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-hha-metric.json @@ -0,0 +1,65 @@ +[ + { + "MetricName": "hha_read_ddrc_bw", + "MetricExpr": "(hha_rd_ddr_64b * 64 + hha_rd_ddr_128b * 128) / duration_time / 1e6", + "MetricGroup": "HHA_bw", + "BriefDescription": "Average bandwidth of reading DDRC", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_write_ddrc_bw", + "MetricExpr": "(hha_wr_ddr_64b * 64 + hha_wr_ddr_128b * 128) / duration_time / 1e6", + "MetricGroup": "HHA_bw", + "BriefDescription": "Average bandwidth of writing DDRC", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_cross_chip_ops_rate", + "MetricExpr": "rx_outer / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of cross-chip operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_cross_die_ops_rate", + "MetricExpr": "rx_sccl / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of cross-die operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_channel0_ops_rate", + "MetricExpr": "hha_rx_ch0 / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of channel 0 operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_channel1_ops_rate", + "MetricExpr": "hha_rx_ch1 / rx_ops_num", + "MetricGroup": "HHA_lat", + "BriefDescription": "Rate of channel 1 operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_req_average_lat", + "MetricExpr": "hha_req_lat / hha_req_cnt * (duration_time * 1e9 / hha_cycles)", + "MetricGroup": "HHA_lat", + "BriefDescription": "Average latency that HHA completes all requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-l3c-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-l3c-metric.json new file mode 100644 index 000000000000..86cdb39501a1 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-l3c-metric.json @@ -0,0 +1,38 @@ +[ + { + "MetricName": "l3c_hit_rate", + "MetricExpr": "l3c_hit / l3c_ref", + "MetricGroup": "L3C", + "BriefDescription": "hit rate of L3C", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "l3c_access_bw", + "MetricExpr": "l3c_ref * 64 / duration_time / 1e6", + "MetricGroup": "L3C_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "cpu_read_l3c_average_lat", + "MetricExpr": "cpu_read_l3c_lat / cpu_read_l3c_sum * (duration_time * 1e9 / l3c_cycles)", + "MetricGroup": "L3C_lat", + "BriefDescription": "Average latency of CPU reading L3C", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "l3c_read_hha_average_lat", + "MetricExpr": "l3c_read_hha_lat / l3c_read_hha_sum * (duration_time * 1e9 / l3c_cycles)", + "MetricGroup": "L3C_lat", + "BriefDescription": "Average latency of L3C reading HHA", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-pa-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-pa-metric.json new file mode 100644 index 000000000000..94846f1812c0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-pa-metric.json @@ -0,0 +1,92 @@ +[ + { + "MetricName": "pa_rx_bw", + "MetricExpr": "(pa_rx_data_link0 + pa_rx_data_link1 + pa_rx_data_link2 + pa_rx_data_link3) * 20 / duration_time / 1e6", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth from Ring to PA", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_bw", + "MetricExpr": "(pa_tx_data_link0 + pa_tx_data_link1 + pa_tx_data_link2 + pa_tx_data_link3) * 20 / duration_time / 1e6", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth from PA to Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link0_bw_occupancy", + "MetricExpr": "pa_rx_data_link0 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link0", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link1_bw_occupancy", + "MetricExpr": "pa_rx_data_link1 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link1", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link2_bw_occupancy", + "MetricExpr": "pa_rx_data_link2 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link2", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link3_bw_occupancy", + "MetricExpr": "pa_rx_data_link3 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link3", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link0_bw_occupancy", + "MetricExpr": "pa_tx_data_link0 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link0 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link1_bw_occupancy", + "MetricExpr": "pa_tx_data_link1 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link1 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link2_bw_occupancy", + "MetricExpr": "pa_tx_data_link2 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link2 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link3_bw_occupancy", + "MetricExpr": "pa_tx_data_link3 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link3 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-sllc-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-sllc-metric.json new file mode 100644 index 000000000000..62f9abc078d2 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-sllc-metric.json @@ -0,0 +1,74 @@ +[ + { + "MetricName": "sllc_rx_req_average_lat", + "MetricExpr": "sllc_rx_req_lat / sllc_rx_req * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC receive requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_data_average_lat", + "MetricExpr": "sllc_rx_data_lat / sllc_rx_data * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC receive data", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_req_average_lat", + "MetricExpr": "sllc_tx_req_lat / sllc_tx_req * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC transmit requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_data_average_lat", + "MetricExpr": "sllc_tx_data_lat / sllc_tx_data * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC transmit data", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_bw", + "MetricExpr": "sllc_rx_data * 64 / duration_time / 1e6", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth of SLLC receive data", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_bw_occupancy", + "MetricExpr": "sllc_rx_data / sllc_cycles", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth occupancy of SLLC receive data", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_bw", + "MetricExpr": "sllc_tx_data * 64 / duration_time / 1e6", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth of SLLC transmit data", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_bw_occupancy", + "MetricExpr": "sllc_tx_data / sllc_cycles", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth occupancy of SLLC transmit data", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-uc-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-uc-metric.json new file mode 100644 index 000000000000..5e1be1623c2b --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-uc-metric.json @@ -0,0 +1,146 @@ +[ + { + "MetricName": "uc2cring_rxdat_bw", + "MetricExpr": "cring_rxdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC access CRing", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2cring_txdat_bw", + "MetricExpr": "cring_txdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2uring_rxdat_bw", + "MetricExpr": "uring_rxdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2uring_txdat_bw", + "MetricExpr": "uring_txdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2uring_rx_merge_dat_bw", + "MetricExpr": "uring_rxreqdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC received merged data bandwidth", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2uring_tx_merge_dat_bw", + "MetricExpr": "uring_txreqdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC transmit merged data bandwidth", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2hbm_rd_bw", + "MetricExpr": "(uc2hbm_bank0_rd64 * 64 + uc2hbm_bank0_rd128 * 128 + uc2hbm_bank1_rd64 * 64 + uc2hbm_bank1_rd128 * 128) / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC reading HBM", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2hbm_wr_bw", + "MetricExpr": "(uc2hbm_bank0_wr64 * 64 + uc2hbm_bank0_wr128 * 128 + uc2hbm_bank1_wr64 * 64 + uc2hbm_bank1_wr128 * 128) / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC writing HBM", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "spipe_hit_ratio", + "MetricExpr": "spipe_hit / spipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of SPIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "hpipe_hit_ratio", + "MetricExpr": "hpipe_hit / hpipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of HPIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "hc_pipe_hit_ratio", + "MetricExpr": "hc_pipe_hit_1k / hc_pipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of HC_PIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "sc_pipe_hit_ratio", + "MetricExpr": "sc_pipe_hit_sector / sc_pipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of SC_PIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "cring_rd_concurrency_numa", + "MetricExpr": "(cpu_rd64 + cpu_rd128 + cpu_rs64 + cpu_rs128 + cpu_mru) / duration_time", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC cring on NUMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "cring_rd_concurrency_uma", + "MetricExpr": "(cpu_rd64 + cpu_rd128 + cpu_rs64 + cpu_rs128 + cpu_mru) * cring_txdat_cnt / duration_time / (cring_txdat_cnt + uring_txdat_cnt)", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC cring on UMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uring_rd_concurrency_numa", + "MetricExpr": "(ext2uc_ru64 + ext2uc_ru128 + ext2uc_rs64 + ext2uc_rs128) / duration_time", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC uring on UMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "hbm_read_concurrency", + "MetricExpr": "(2 * (uc2hbm_bank0_rd128 + uc2hbm_bank1_rd128) + uc2hbm_bank0_rd64 + uc2hbm_bank1_rd64) / duration_time", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC uring on UMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/core-imp-def.json new file mode 100644 index 000000000000..e4d8124319a5 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/core-imp-def.json @@ -0,0 +1,125 @@ +[ + { + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_TLB_RD" + }, + { + "ArchStdEvent": "L1D_TLB_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL" + }, + { + "EventCode": "0x102e", + "EventName": "L1I_CACHE_PRF", + "BriefDescription": "L1I cache prefetch access count" + }, + { + "EventCode": "0x102f", + "EventName": "L1I_CACHE_PRF_REFILL", + "BriefDescription": "L1I cache miss due to prefetch access count" + }, + { + "EventCode": "0x1043", + "EventName": "IQ_IS_EMPTY", + "BriefDescription": "Instruction queue is empty" + }, + { + "EventCode": "0x1047", + "EventName": "IF_IS_STALL", + "BriefDescription": "Instruction fetch stall cycles" + }, + { + "EventCode": "0x1f21", + "EventName": "FETCH_BUBBLE", + "BriefDescription": "Instructions cannot be sent to back end because of front end stall" + }, + { + "EventCode": "0x1f22", + "EventName": "FETCH_BUBBLE_EQ_MAX", + "BriefDescription": "Instructions cannot be sent to back end because of front end stall when the instruction number is full bandwidth" + }, + { + "EventCode": "0x7001", + "EventName": "EXE_STALL_CYCLE", + "BriefDescription": "Cycles of that the number of issue ups are less than 4" + }, + { + "EventCode": "0x7005", + "EventName": "MEM_STALL_ANYLOAD", + "BriefDescription": "No any micro operation is issued and meanwhile any load operation is not resolved" + }, + { + "EventCode": "0x7006", + "EventName": "MEM_STALL_ANYSTORE", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing L1 cache and pending data refill" + }, + { + "EventCode": "0x7007", + "EventName": "MEM_STALL_L1MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L1 and L2 cache and pending data refill from L3 cache" + }, + { + "EventCode": "0x7008", + "EventName": "MEM_STALL_L2MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L2 and L3 cache and pending data refill from L3 cache" + }, + { + "EventCode": "0x7009", + "EventName": "MEM_STALL_L3MISS", + "BriefDescription": "No any micro operation is issued and meanwhile there is any load operation missing both L3 and LL cache and pending data refill from L3 cache" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/metrics.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/metrics.json new file mode 100644 index 000000000000..331e606e5711 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/metrics.json @@ -0,0 +1,459 @@ +[ + { + "MetricExpr": "FETCH_BUBBLE / (8 * CPU_CYCLES)", + "BriefDescription": "L1 topdown: Frontend bound", + "DefaultMetricgroupName": "TopdownL1", + "MetricGroup": "Default;TopdownL1", + "MetricName": "frontend_bound" + }, + { + "MetricExpr": "(INST_SPEC - INST_RETIRED) / (8 * CPU_CYCLES)", + "BriefDescription": "L1 topdown: Bad Speculation", + "DefaultMetricgroupName": "TopdownL1", + "MetricGroup": "Default;TopdownL1", + "MetricName": "bad_speculation" + }, + { + "MetricExpr": "INST_RETIRED / (CPU_CYCLES * 8)", + "BriefDescription": "L1 topdown: Retiring", + "DefaultMetricgroupName": "TopdownL1", + "MetricGroup": "Default;TopdownL1", + "MetricName": "retiring" + }, + { + "MetricExpr": "1 - (frontend_bound + bad_speculation + retiring)", + "BriefDescription": "L1 topdown: Backend Bound", + "DefaultMetricgroupName": "TopdownL1", + "MetricGroup": "Default;TopdownL1", + "MetricName": "backend_bound" + }, + { + "MetricExpr": "FETCH_BUBBLE_EQ_MAX / CPU_CYCLES", + "BriefDescription": "L2 topdown: Fetch latency bound", + "MetricGroup": "TopdownL2;frontend_bound_group", + "MetricName": "fetch_latency_bound" + }, + { + "MetricExpr": "frontend_bound - fetch_latency_bound", + "BriefDescription": "L2 topdown: Fetch bandwidth bound", + "MetricGroup": "TopdownL2;frontend_bound_group", + "MetricName": "fetch_bandwidth_bound" + }, + { + "MetricExpr": "(bad_speculation * BR_MIS_PRED) / (BR_MIS_PRED + armv8_pmuv3_0@event\\=0x2010@)", + "BriefDescription": "L2 topdown: Branch mispredicts", + "MetricGroup": "TopdownL2;bad_speculation_group", + "MetricName": "branch_mispredicts" + }, + { + "MetricExpr": "bad_speculation - branch_mispredicts", + "BriefDescription": "L2 topdown: Machine clears", + "MetricGroup": "TopdownL2;bad_speculation_group", + "MetricName": "machine_clears" + }, + { + "MetricExpr": "(MEM_STALL_ANYLOAD + MEM_STALL_ANYSTORE) / CPU_CYCLES", + "BriefDescription": "L2 topdown: Memory bound", + "MetricGroup": "TopdownL2;backend_bound_group", + "MetricName": "memory_bound" + }, + { + "MetricExpr": "(EXE_STALL_CYCLE - MEM_STALL_ANYLOAD - MEM_STALL_ANYSTORE) / CPU_CYCLES", + "BriefDescription": "L2 topdown: Core bound", + "MetricGroup": "TopdownL2;backend_bound_group", + "MetricName": "core_bound" + }, + { + "MetricExpr": "(armv8_pmuv3_0@event\\=0x1f10@ + armv8_pmuv3_0@event\\=0x1f11@)/ CPU_CYCLES", + "BriefDescription": "L3 topdown: L1 instruction tlb or cache miss bubble", + "MetricGroup": "TopdownL3;fetch_bandwidth_bound_group", + "MetricName": "l1i_tlb_or_cache_miss" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f12@ / CPU_CYCLES", + "BriefDescription": "L3 topdown: OoO flush bubble", + "MetricGroup": "TopdownL3;fetch_bandwidth_bound_group", + "MetricName": "ooo_flush" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f13@ / CPU_CYCLES", + "BriefDescription": "L3 topdown: Static predictor flush bubble", + "MetricGroup": "TopdownL3;fetch_bandwidth_bound_group", + "MetricName": "sp_flush" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f14@ / CPU_CYCLES", + "BriefDescription": "L3 topdown: Branch unit flush bubble", + "MetricGroup": "TopdownL3;fetch_bandwidth_bound_group", + "MetricName": "bru_flush" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f15@ / CPU_CYCLES", + "BriefDescription": "L3 topdown: Branch unit5 flush bubble", + "MetricGroup": "TopdownL3;fetch_bandwidth_bound_group", + "MetricName": "b5_flush" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f16@ / CPU_CYCLES", + "BriefDescription": "L3 topdown: Branch unit3 flush bubble", + "MetricGroup": "TopdownL3;fetch_bandwidth_bound_group", + "MetricName": "b3_flush" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f17@ / CPU_CYCLES", + "BriefDescription": "L3 topdown: Branch unit2 flush bubble", + "MetricGroup": "TopdownL3;fetch_bandwidth_bound_group", + "MetricName": "b2_flush" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f18@ / CPU_CYCLES", + "BriefDescription": "L3 topdown: Prediction supplement Q stall bubble", + "MetricGroup": "TopdownL3;fetch_bandwidth_bound_group", + "MetricName": "bpu_q_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1010@ / BR_MIS_PRED", + "BriefDescription": "L3 topdown: Indirect branch", + "MetricGroup": "TopdownL3;branch_mispredicts_group", + "MetricName": "indirect_branch" + }, + { + "MetricExpr": "(armv8_pmuv3_0@event\\=0x1013@ + armv8_pmuv3_0@event\\=0x1016@) / BR_MIS_PRED", + "BriefDescription": "L3 topdown: Push branch", + "MetricGroup": "TopdownL3;branch_mispredicts_group", + "MetricName": "push_branch" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x100d@ / BR_MIS_PRED", + "BriefDescription": "L3 topdown: Pop branch", + "MetricGroup": "TopdownL3;branch_mispredicts_group", + "MetricName": "pop_branch" + }, + { + "MetricExpr": "1 - (push_branch + pop_branch)", + "BriefDescription": "L3 topdown: Other branch", + "MetricGroup": "TopdownL3;branch_mispredicts_group", + "MetricName": "other_branch" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x203f@ / armv8_pmuv3_0@event\\=0x2040@", + "BriefDescription": "L3 topdown: Nuke flush", + "MetricGroup": "TopdownL3;machine_clears_group", + "MetricName": "nuke_flush" + }, + { + "MetricExpr": "1 - nuke_flush", + "BriefDescription": "L3 topdown: Other flush", + "MetricGroup": "TopdownL3;machine_clears_group", + "MetricName": "other_flush" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x7000@ / CPU_CYCLES", + "BriefDescription": "L3 topdown: Resource Bound", + "MetricGroup": "TopdownL3;core_bound_group", + "MetricName": "resource_bound" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x7002@ / CPU_CYCLES", + "BriefDescription": "L3 topdown: FSU divqsrt stall", + "MetricGroup": "TopdownL3;core_bound_group", + "MetricName": "fdiv_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x7003@ / CPU_CYCLES", + "BriefDescription": "L3 topdown: divqsrt stall", + "MetricGroup": "TopdownL3;core_bound_group", + "MetricName": "div_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x7004@ / CPU_CYCLES", + "BriefDescription": "L3 topdown: FSU stall", + "MetricGroup": "TopdownL3;core_bound_group", + "MetricName": "fsu_stall" + }, + { + "MetricExpr": "core_bound - resource_bound - fdiv_stall - div_stall - fsu_stall", + "BriefDescription": "L3 topdown: EXE ports util", + "MetricGroup": "TopdownL3;core_bound_group", + "MetricName": "exe_ports_util" + }, + { + "MetricExpr": "(MEM_STALL_ANYLOAD - MEM_STALL_L1MISS) / CPU_CYCLES", + "BriefDescription": "L3 topdown: L1 bound", + "MetricGroup": "TopdownL3;memory_bound_group", + "MetricName": "l1_bound" + }, + { + "MetricExpr": "(MEM_STALL_L1MISS - MEM_STALL_L2MISS) / CPU_CYCLES", + "BriefDescription": "L3 topdown: L2 bound", + "MetricGroup": "TopdownL3;memory_bound_group", + "MetricName": "l2_bound" + }, + { + "MetricExpr": "(MEM_STALL_L2MISS - MEM_STALL_L3MISS) / CPU_CYCLES", + "BriefDescription": "L3 topdown: L3 bound", + "MetricGroup": "TopdownL3;memory_bound_group", + "MetricName": "l3_bound" + }, + { + "MetricExpr": "MEM_STALL_L3MISS / CPU_CYCLES", + "BriefDescription": "L3 topdown: Mem bound", + "MetricGroup": "TopdownL3;memory_bound_group", + "MetricName": "mem_bound" + }, + { + "MetricExpr": "MEM_STALL_ANYSTORE / CPU_CYCLES", + "BriefDescription": "L3 topdown: Store bound", + "MetricGroup": "TopdownL3;memory_bound_group", + "MetricName": "store_bound" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f10@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: L1 instruction tlb miss bubble", + "MetricGroup": "TopdownL4;l1i_tlb_or_cache_miss_group", + "MetricName": "l1i_tlb_miss" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f11@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: L1 instruction cache miss bubble", + "MetricGroup": "TopdownL4;l1i_tlb_or_cache_miss_group", + "MetricName": "l1i_cache_miss" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f19@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: Target fifo full stall bubble", + "MetricGroup": "TopdownL4;bpu_q_stall_group", + "MetricName": "tgt_fifo_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f1a@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: Branch Q stall bubble", + "MetricGroup": "TopdownL4;bpu_q_stall_group", + "MetricName": "branch_q_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f1b@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: Return Stack full stall bubble", + "MetricGroup": "TopdownL4;bpu_q_stall_group", + "MetricName": "rs_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x2006@ + armv8_pmuv3_0@event\\=0x2007@ + armv8_pmuv3_0@event\\=0x2008@ + armv8_pmuv3_0@event\\=0x200a@", + "BriefDescription": "Total ptag stall", + "MetricName": "total_ptag_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x200b@ + armv8_pmuv3_0@event\\=0x200c@ + armv8_pmuv3_0@event\\=0x200d@", + "BriefDescription": "Total mapq stall", + "MetricName": "total_mapq_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x2004@ + armv8_pmuv3_0@event\\=0x2005@ + total_ptag_stall + total_mapq_stall + armv8_pmuv3_0@event\\=0x2010@", + "BriefDescription": "Total OoO stall", + "MetricName": "total_ooo_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x2004@ / total_ooo_stall", + "BriefDescription": "L4 topdown: Rob stall", + "MetricGroup": "TopdownL4;resource_bound_group", + "MetricName": "rob_stall" + }, + { + "MetricExpr": "total_ptag_stall / total_ooo_stall", + "BriefDescription": "L4 topdown: Ptag stall", + "MetricGroup": "TopdownL4;resource_bound_group", + "MetricName": "ptag_stall" + }, + { + "MetricExpr": "total_mapq_stall / total_ooo_stall", + "BriefDescription": "L4 topdown: Mapq stall", + "MetricGroup": "TopdownL4;resource_bound_group", + "MetricName": "Mapq_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x2005@ / total_ooo_stall", + "BriefDescription": "L4 topdown: PC buffer stall", + "MetricGroup": "TopdownL4;resource_bound_group", + "MetricName": "pc_buffer_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x2010@ / total_ooo_stall", + "BriefDescription": "L4 topdown: DSP stall", + "MetricGroup": "TopdownL4;resource_bound_group", + "MetricName": "dsp_stall" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x700a@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: 0 uops of integer instructions are issued with serializing block", + "MetricGroup": "TopdownL4;exe_ports_util_group", + "MetricName": "is_0_ports_serialize" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x700b@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: 0 uops of integer instructions are issued without serializing block", + "MetricGroup": "TopdownL4;exe_ports_util_group", + "MetricName": "is_0_ports_non_serialize" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x700c@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: 1 uop of integer instructions is issued", + "MetricGroup": "TopdownL4;exe_ports_util_group", + "MetricName": "is_1_ports" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x700d@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: 2 uops of integer instructions is issue", + "MetricGroup": "TopdownL4;exe_ports_util_group", + "MetricName": "is_2_ports" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x700e@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: 3 uops of integer instructions is issue", + "MetricGroup": "TopdownL4;exe_ports_util_group", + "MetricName": "is_3_ports" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x700f@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: 4 uops of integer instructions is issue", + "MetricGroup": "TopdownL4;exe_ports_util_group", + "MetricName": "is_4_ports" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x7010@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: 5 uops of integer instructions is issue", + "MetricGroup": "TopdownL4;exe_ports_util_group", + "MetricName": "is_5_ports" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x7011@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: 6 uops of integer instructions is issue", + "MetricGroup": "TopdownL4;exe_ports_util_group", + "MetricName": "is_6_ports" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x7012@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: 7 uops of integer instructions is issue", + "MetricGroup": "TopdownL4;exe_ports_util_group", + "MetricName": "is_7_ports" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x7013@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: no less than 8 uops of integer instructions are issued", + "MetricGroup": "TopdownL4;exe_ports_util_group", + "MetricName": "is_8_ports" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x701e@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: MEM_STALL_L1MISS happens. Any request in wlb/plb/evb pending state", + "MetricGroup": "TopdownL4;l2_bound_group", + "MetricName": "l2_buf_pending" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x701f@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: MEM_STALL_L1MISS happens. Any request in snoop pending state", + "MetricGroup": "TopdownL4;l2_bound_group", + "MetricName": "l2_snp_pending" + }, + { + "MetricExpr": "l2_bound - l2_buf_pending - l2_snp_pending", + "BriefDescription": "L4 topdown: MEM_STALL_L1MISS happens. Any request in snoop pending state", + "MetricGroup": "TopdownL4;l2_bound_group", + "MetricName": "l2_pipeline_bound" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x7020@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: MEM_STALL_L1MISS happens. L2C ARB in idle state", + "MetricGroup": "TopdownL4;l2_bound_group", + "MetricName": "l2_arb_idle" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x7021@", + "BriefDescription": "L4 topdown: MEM_STALL_L3MISS happens. The data source from local die DDR or local chip other die DDR", + "MetricGroup": "TopdownL4;mem_bound_group", + "MetricName": "local_memory_bound" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x7022@", + "BriefDescription": "L4 topdown: MEM_STALL_L3MISS happens. The data source from another chip DDR", + "MetricGroup": "TopdownL4;mem_bound_group", + "MetricName": "remote_memory_bound" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x1f23@", + "BriefDescription": "L4 topdown: MEM_STALL_L3MISS happens. The data source from another chip L3", + "MetricGroup": "TopdownL4;mem_bound_group", + "MetricName": "remote_cache_bound" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x5090@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: ld cancel dtlb miss", + "MetricGroup": "TopdownL4;l1_bound_group", + "MetricName": "ld_cancel_dtlb_miss" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x5091@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: ld cancel misalign", + "MetricGroup": "TopdownL4;l1_bound_group", + "MetricName": "ld_cancel_misalign" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x5092@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: ld cancel resource full", + "MetricGroup": "TopdownL4;l1_bound_group", + "MetricName": "ld_cancel_resource_full" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x5093@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: ld cancel instruction type", + "MetricGroup": "TopdownL4;l1_bound_group", + "MetricName": "ld_cancel_instruction_type" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x5094@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: ld cancel forward hazard", + "MetricGroup": "TopdownL4;l1_bound_group", + "MetricName": "ld_cancel_forward_hazard:" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x5095@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: ld cancel structure hazard", + "MetricGroup": "TopdownL4;l1_bound_group", + "MetricName": "ld_cancel_structure_hazard" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x5096@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: ld cancel pipeline", + "MetricGroup": "TopdownL4;l1_bound_group", + "MetricName": "ld_cancel_pipeline" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x50a0@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: store SCA full", + "MetricGroup": "TopdownL4;store_bound_group", + "MetricName": "st_sca_full" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x50a1@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: store SCD full", + "MetricGroup": "TopdownL4;store_bound_group", + "MetricName": "st_scd_full" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x50a2@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: store head no pgen", + "MetricGroup": "TopdownL4;store_bound_group", + "MetricName": "st_head_no_pgen" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x50a3@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: store order fail", + "MetricGroup": "TopdownL4;store_bound_group", + "MetricName": "st_order_fail" + }, + { + "MetricExpr": "armv8_pmuv3_0@event\\=0x50a4@ / CPU_CYCLES", + "BriefDescription": "L4 topdown: store bound pipeline", + "MetricGroup": "TopdownL4;store_bound_group", + "MetricName": "st_other" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-cpa-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-cpa-metric.json new file mode 100644 index 000000000000..1ead2819abe0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-cpa-metric.json @@ -0,0 +1,20 @@ +[ + { + "MetricName": "cpa_p1_avg_bw", + "MetricExpr": "(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / duration_time / 1e6", + "BriefDescription": "Average bandwidth of CPA Port 1", + "MetricGroup": "CPA_bw", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "MetricName": "cpa_p0_avg_bw", + "MetricExpr": "(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / duration_time / 1e6", + "BriefDescription": "Average bandwidth of CPA Port 0", + "MetricGroup": "CPA_bw", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-ddrc-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-ddrc-metric.json new file mode 100644 index 000000000000..b4a95fd53b76 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-ddrc-metric.json @@ -0,0 +1,56 @@ +[ + { + "MetricName": "ddrc_write_bw", + "MetricExpr": "flux_wr * 32 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of write DDRC memory", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_read_bw", + "MetricExpr": "flux_rd * 32 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of read DDRC memory", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_rdwr_bw", + "MetricExpr": "(flux_wr + flux_rd) * 32 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of DDRC (including memory read and write)", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_read_lat", + "MetricExpr": "ddrc_read_cmd_occupancy / ddrc_read_cmd * (duration_time * 1e9 / ddrc_cycles)", + "MetricGroup": "DDRC_lat", + "BriefDescription": "Average scheduling latency of DDRC read command", + "ScaleUnit": "1ns", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_write_lat", + "MetricExpr": "ddrc_write_cmd_occupancy / ddrc_write_cmd * (duration_time * 1e9 / ddrc_cycles)", + "MetricGroup": "DDRC_lat", + "BriefDescription": "Average scheduling of DDRC write command", + "ScaleUnit": "1ns", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_rowhit_rate", + "MetricExpr": "1 - ddrc_active_cmd / ddrc_cas_cmd", + "MetricGroup": "DDRC", + "BriefDescription": "Row hit rate of DDRC", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-hha-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-hha-metric.json new file mode 100644 index 000000000000..1232f30f5b0a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-hha-metric.json @@ -0,0 +1,65 @@ +[ + { + "MetricName": "hha_read_ddrc_bw", + "MetricExpr": "(hha_rd_ddr_64b * 64 + hha_rd_ddr_128b * 128) / duration_time / 1e6", + "MetricGroup": "HHA_bw", + "BriefDescription": "Average bandwidth of reading DDRC", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_write_ddrc_bw", + "MetricExpr": "(hha_wr_ddr_64b * 64 + hha_wr_ddr_128b * 128) / duration_time / 1e6", + "MetricGroup": "HHA_bw", + "BriefDescription": "Average bandwidth of writing DDRC", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_cross_chip_ops_rate", + "MetricExpr": "rx_outer / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of cross-chip operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_cross_die_ops_rate", + "MetricExpr": "rx_sccl / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of cross-die operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_channel0_ops_rate", + "MetricExpr": "hha_rx_ch0 / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of channel 0 operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_channel1_ops_rate", + "MetricExpr": "hha_rx_ch1 / rx_ops_num", + "MetricGroup": "HHA_lat", + "BriefDescription": "Rate of channel 1 operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_req_average_lat", + "MetricExpr": "hha_req_lat / hha_req_cnt * (duration_time * 1e9 / hha_cycles)", + "MetricGroup": "HHA_lat", + "BriefDescription": "Average latency that HHA completes all requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json new file mode 100644 index 000000000000..86cdb39501a1 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json @@ -0,0 +1,38 @@ +[ + { + "MetricName": "l3c_hit_rate", + "MetricExpr": "l3c_hit / l3c_ref", + "MetricGroup": "L3C", + "BriefDescription": "hit rate of L3C", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "l3c_access_bw", + "MetricExpr": "l3c_ref * 64 / duration_time / 1e6", + "MetricGroup": "L3C_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "cpu_read_l3c_average_lat", + "MetricExpr": "cpu_read_l3c_lat / cpu_read_l3c_sum * (duration_time * 1e9 / l3c_cycles)", + "MetricGroup": "L3C_lat", + "BriefDescription": "Average latency of CPU reading L3C", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "l3c_read_hha_average_lat", + "MetricExpr": "l3c_read_hha_lat / l3c_read_hha_sum * (duration_time * 1e9 / l3c_cycles)", + "MetricGroup": "L3C_lat", + "BriefDescription": "Average latency of L3C reading HHA", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-mn-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-mn-metric.json new file mode 100644 index 000000000000..8d68ce7ffb31 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-mn-metric.json @@ -0,0 +1,58 @@ +[ + { + "MetricName": "snp_dvm_average_latency", + "MetricExpr": "snp_dvm_latency / snp_dvm_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Non-Sync snoop request average latency", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "pa_req_dvm_average_latency", + "MetricExpr": "pa_req_dvm_latency / pa_req_dvm_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Non-Sync request average latency from PA", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "mn_req_dvm_average_latency", + "MetricExpr": "mn_req_dvm_latency / mn_req_dvm_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Non-Sync request average latency from MN", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "l3t_req_dvm_average_latency", + "MetricExpr": "l3t_req_dvm_latency / l3t_req_dvm_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Non-Sync request average latency from L3T", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "snp_dvmsync_average_latency", + "MetricExpr": "snp_dvmsync_latency / snp_dvmsync_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Sync snoop request average latency", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "pa_req_dvmsync_average_latency", + "MetricExpr": "pa_req_dvmsync_latency / pa_req_dvmsync_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Sync request average latency from PA", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "mn_req_dvmsync_average_latency", + "MetricExpr": "mn_req_dvmsync_latency / mn_req_dvmsync_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Sync request average latency from MN", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "l3t_req_dvmsync_average_latency", + "MetricExpr": "l3t_req_dvmsync_latency / l3t_req_dvmsync_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Sync request average latency from L3T", + "ScaleUnit": "1cycle" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-noc-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-noc-metric.json new file mode 100644 index 000000000000..4cee78c5880c --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-noc-metric.json @@ -0,0 +1,38 @@ +[ + { + "MetricName": "ingress_flow_bw", + "MetricExpr": "ingress_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NoC_bw", + "BriefDescription": "Average data bandwidth from subsys to Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "egress_flow_bw", + "MetricExpr": "egress_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NoC_bw", + "BriefDescription": "Average data bandwidth from Ring to subsys", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "cw_main_flow_bw", + "MetricExpr": "cw_main_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NoC_bw", + "BriefDescription": "Average data bandwidth of clockwise main Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "cc_main_flow_bw", + "MetricExpr": "cc_main_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NoC_bw", + "BriefDescription": "Average data bandwidth of counterclockwise main Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-pa-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-pa-metric.json new file mode 100644 index 000000000000..94846f1812c0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-pa-metric.json @@ -0,0 +1,92 @@ +[ + { + "MetricName": "pa_rx_bw", + "MetricExpr": "(pa_rx_data_link0 + pa_rx_data_link1 + pa_rx_data_link2 + pa_rx_data_link3) * 20 / duration_time / 1e6", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth from Ring to PA", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_bw", + "MetricExpr": "(pa_tx_data_link0 + pa_tx_data_link1 + pa_tx_data_link2 + pa_tx_data_link3) * 20 / duration_time / 1e6", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth from PA to Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link0_bw_occupancy", + "MetricExpr": "pa_rx_data_link0 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link0", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link1_bw_occupancy", + "MetricExpr": "pa_rx_data_link1 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link1", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link2_bw_occupancy", + "MetricExpr": "pa_rx_data_link2 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link2", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link3_bw_occupancy", + "MetricExpr": "pa_rx_data_link3 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link3", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link0_bw_occupancy", + "MetricExpr": "pa_tx_data_link0 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link0 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link1_bw_occupancy", + "MetricExpr": "pa_tx_data_link1 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link1 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link2_bw_occupancy", + "MetricExpr": "pa_tx_data_link2 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link2 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link3_bw_occupancy", + "MetricExpr": "pa_tx_data_link3 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link3 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-sllc-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-sllc-metric.json new file mode 100644 index 000000000000..62f9abc078d2 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-sllc-metric.json @@ -0,0 +1,74 @@ +[ + { + "MetricName": "sllc_rx_req_average_lat", + "MetricExpr": "sllc_rx_req_lat / sllc_rx_req * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC receive requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_data_average_lat", + "MetricExpr": "sllc_rx_data_lat / sllc_rx_data * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC receive data", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_req_average_lat", + "MetricExpr": "sllc_tx_req_lat / sllc_tx_req * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC transmit requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_data_average_lat", + "MetricExpr": "sllc_tx_data_lat / sllc_tx_data * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC transmit data", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_bw", + "MetricExpr": "sllc_rx_data * 64 / duration_time / 1e6", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth of SLLC receive data", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_bw_occupancy", + "MetricExpr": "sllc_rx_data / sllc_cycles", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth occupancy of SLLC receive data", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_bw", + "MetricExpr": "sllc_tx_data * 64 / duration_time / 1e6", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth of SLLC transmit data", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_bw_occupancy", + "MetricExpr": "sllc_tx_data / sllc_cycles", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth occupancy of SLLC transmit data", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-cpa.json similarity index 76% rename from tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json rename to tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-cpa.json index 7bcddec8a84f..1103741b921b 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-cpa.json @@ -61,21 +61,5 @@ "BriefDescription": "Number of read ops transmitted by the P0 port which size is 32 bytes", "Compat": "0x00000030", "Unit": "hisi_sicl,cpa" - }, - { - "MetricExpr": "(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / cpa_cycles", - "BriefDescription": "Average bandwidth of CPA Port 1", - "MetricGroup": "CPA", - "MetricName": "cpa_p1_avg_bw", - "Compat": "0x00000030", - "Unit": "hisi_sicl,cpa" - }, - { - "MetricExpr": "(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / cpa_cycles", - "BriefDescription": "Average bandwidth of CPA Port 0", - "MetricGroup": "CPA", - "MetricName": "cpa_p0_avg_bw", - "Compat": "0x00000030", - "Unit": "hisi_sicl,cpa" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-ddrc.json new file mode 100644 index 000000000000..d172125518f1 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-ddrc.json @@ -0,0 +1,100 @@ +[ + { + "EventCode": "0x00", + "EventName": "ddrc_cycles", + "BriefDescription": "Count of DDRC cycles", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x00", + "EventName": "cycles", + "BriefDescription": "Count of DDRC cycles", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x01", + "EventName": "ddrc_active_cmd", + "BriefDescription": "Count of DDRC active commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x02", + "EventName": "ddrc_precharge_cmd", + "BriefDescription": "Count of DDRC precharge commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x03", + "EventName": "ddrc_cas_cmd", + "BriefDescription": "Count of DDRC read and write commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x30", + "EventName": "ddrc_rdwr_changes", + "BriefDescription": "Count the DDRC read and write changes", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x31", + "EventName": "ddrc_rank_changes", + "BriefDescription": "Count the DDRC rank changes", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x32", + "EventName": "ddrc_bg_changes", + "BriefDescription": "Count the DDRC BG changes", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x41", + "EventName": "ddrc_read_cmd", + "BriefDescription": "Count of DDRC read commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x44", + "EventName": "ddrc_write_cmd", + "BriefDescription": "Count of DDRC write commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x80", + "EventName": "ddrc_read_cmd_occupancy", + "BriefDescription": "Count of cycles occupied by the read command in the queue", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x81", + "EventName": "ddrc_write_cmd_occupancy", + "BriefDescription": "Count of cycles occupied by the write command in the queue", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x83", + "EventName": "flux_wr", + "BriefDescription": "Count of DDRC write commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x84", + "EventName": "flux_rd", + "BriefDescription": "Count of DDRC read commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-hha.json new file mode 100644 index 000000000000..9c5f0a633be0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-hha.json @@ -0,0 +1,128 @@ +[ + { + "EventCode": "0x00", + "EventName": "rx_ops_num", + "BriefDescription": "Number of all operations received by the HHA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x01", + "EventName": "rx_outer", + "BriefDescription": "Number of all operations received by the HHA from another socket", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x02", + "EventName": "rx_sccl", + "BriefDescription": "Number of all operations received by the HHA from another SCCL in this socket", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x03", + "EventName": "hha_rx_cxl", + "BriefDescription": "Number of operations that HHA has received from CXL", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x13", + "EventName": "hha_rx_cmo", + "BriefDescription": "Count number of CMO operations received by the HHA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x16", + "EventName": "hha_rx_prefetch_drop", + "BriefDescription": "Count number of prefetch operations dropped by the HHA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1a", + "EventName": "hha_rx_ch0", + "BriefDescription": "Count number of all operations received by the HHA from channel 0", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1b", + "EventName": "hha_rx_ch1", + "BriefDescription": "Count number of all operations received by the HHA from channel 1", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1c", + "EventName": "hha_rd_ddr_64b", + "BriefDescription": "Count number of read operations sent by HHA to DDRC which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1d", + "EventName": "hha_wr_ddr_64b", + "BriefDescription": "Count number of write operations sent by HHA to DDRC which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1e", + "EventName": "hha_rd_ddr_128b", + "BriefDescription": "Count number of read operations sent by HHA to DDRC which size is 128 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1f", + "EventName": "hha_wr_ddr_128b", + "BriefDescription": "Count number of write operations sent by HHA to DDRC which size is 128 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x23", + "EventName": "hha_backinvalid", + "BriefDescription": "Count number of HHA back invalid operations", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x2e", + "EventName": "hha_retry", + "BriefDescription": "Count of the HHA retry", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x55", + "EventName": "hha_cycles", + "BriefDescription": "Count of the HHA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x55", + "EventName": "cycles", + "BriefDescription": "Count of the HHA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0xc5", + "EventName": "hha_req_lat", + "BriefDescription": "Count the total latency that HHA completes all requests", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0xcd", + "EventName": "hha_req_cnt", + "BriefDescription": "Count the total operations that HHA receives", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json new file mode 100644 index 000000000000..ae0d9c6d3b07 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json @@ -0,0 +1,448 @@ +[ + { + "EventCode": "0x29", + "EventName": "l3c_back_invalid", + "BriefDescription": "Count number of L3C back invalid operations", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x3c", + "EventName": "l3c_cpu_evict", + "BriefDescription": "Count number of evict from CPU core", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x40", + "EventName": "l3c_retry_cpu", + "BriefDescription": "Count number of retry that L3C suppresses the CPU operations", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x41", + "EventName": "l3c_retry_ring", + "BriefDescription": "Count number of retry that L3C suppresses the ring operations", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x42", + "EventName": "atomic_tablehsnp_rejecten", + "BriefDescription": "Number of times the hydrasnp in the atomic table is rejected.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x43", + "EventName": "atomic_tablerejecten", + "BriefDescription": "Number of times internal requests in the atomic table are rejected.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x44", + "EventName": "atomic_tablealloc", + "BriefDescription": "Number of times the atomic table is allocated.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x45", + "EventName": "atomic_tablevic", + "BriefDescription": "Number of times the atomic table is replaced.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x46", + "EventName": "atomic_tabletimeout", + "BriefDescription": "Number of times the atomic table times out.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x47", + "EventName": "atomic_tablehmerge", + "BriefDescription": "Number of times the atomic table performs hydrasnp merge protocol.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x48", + "EventName": "l3c_hit", + "BriefDescription": "Count number of hit data from L3C to CPU core", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x7f", + "EventName": "l3c_cycles", + "BriefDescription": "Count of L3C cycles", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x7f", + "EventName": "cycles", + "BriefDescription": "Count of L3C cycles", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xb8", + "EventName": "l3c_ref", + "BriefDescription": "Count number of all CPU accessed L3C", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xb9", + "EventName": "dat_access", + "BriefDescription": "Count number of the cluster CPU accessed L3C", + "Filter": "tt_core=0xff", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xbc", + "EventName": "l3c_ref", + "BriefDescription": "Count number of all CPU accessed L3C", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + + }, + { + "EventCode": "0xbd", + "EventName": "l3c2ring", + "BriefDescription": "Count number of the L3T return data to RING(64B)", + "Filter": "tt_core=0xff,ext=1", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xbd", + "EventName": "l3c2ring_ext", + "BriefDescription": "Count number of the L3T ext return data to RING(64B)", + "Filter": "tt_core=0xff,ext=2", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc0", + "EventName": "cpu_read_l3c_sum", + "Filter": "tt_core=0xff", + "BriefDescription": "Count of the requests issued by the cluster CPU read L3C", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc3", + "EventName": "l3c_read_hha_sum", + "Filter": "tt_core=0xff,tt_req=0x4", + "BriefDescription": "Count number of L3C read access to HHA", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xce", + "EventName": "l3t_retry_alloc", + "Filter": "tt_core=0xff", + "BriefDescription": "Count of the L3C retry CPU", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc1", + "EventName": "l3t_dvmop_alloc", + "Filter": "tt_req=0x3", + "BriefDescription": "Number of DVMOp requests received by L3T", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc4", + "EventName": "l3t_aq_time_alloc", + "BriefDescription": "Total time spent by AQ buffer for marked requests", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc5", + "EventName": "l3t_pq_time_alloc", + "BriefDescription": "Total time spent by PQ buffer for marked requests", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc6", + "EventName": "l3t_snp_cpu_alloc", + "BriefDescription": "Number of SNPs sent by L3T to CPU", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc8", + "EventName": "l3t_rxsnp_l3t_alloc", + "BriefDescription": "Number of SNPs received by L3T from RING", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xca", + "EventName": "l3t_rxhydrasnp_l3t_alloc", + "BriefDescription": "Number of HYDRASNPs received by L3T from RING", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xcb", + "EventName": "l3t_dbid_l3t_alloc", + "BriefDescription": "Number of CPU requests received by L3T", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xcd", + "EventName": "l3t_wrnotram_alloc", + "BriefDescription": "Number of write requests received by L3T for MATA", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x00", + "EventName": "rd_cpipe", + "BriefDescription": "the number of CPIPEs from CPU send read request to L3", + "Filter": "ext=1", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x00", + "EventName": "rd_cpipe_ext", + "BriefDescription": "the number of CPIPEs from CPU send read request to L3 ext", + "Filter": "ext=2", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x01", + "EventName": "rd_hit_cpipe", + "BriefDescription": "the number of CPIPEs from CPU read request hit to L3", + "Filter": "ext=1", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x01", + "EventName": "rd_hit_cpipe_ext", + "BriefDescription": "the number of CPIPEs from CPU read request hit to L3 ext", + "Filter": "ext=2", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x02", + "EventName": "wr_cpipe", + "BriefDescription": "the number of CPIPEs from CPU send stream write request to L3", + "Compat": "0x00000040", + "Filter": "ext=1", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x02", + "EventName": "wr_cpipe_ext", + "BriefDescription": "the number of CPIPEs from CPU send stream write request to L3 ext", + "Compat": "0x00000040", + "Filter": "ext=2", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x03", + "EventName": "wr_hit_cpipe", + "BriefDescription": "the number of CPIPEs from CPU stream write request hit to L3", + "Compat": "0x00000040", + "Filter": "ext=1", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x03", + "EventName": "wr_hit_cpipe_ext", + "BriefDescription": "the number of CPIPEs from CPU stream write request hit to L3 ext", + "Compat": "0x00000040", + "Filter": "ext=2", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x04", + "EventName": "io_rd_cpipe", + "Filter": "ext=1", + "BriefDescription": "the number of IO send read request to CPIPE to L3", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x04", + "EventName": "io_rd_cpipe_ext", + "Filter": "ext=2", + "BriefDescription": "the number of IO send read request to CPIPE to L3 ext", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x05", + "EventName": "io_rd_hit_cpipe", + "Filter": "ext=1", + "BriefDescription": "the number of IO read request hit CPIPE to L3", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x05", + "EventName": "io_rd_hit_cpipe_ext", + "Filter": "ext=2", + "BriefDescription": "the number of IO read request hit CPIPE to L3 ext", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x06", + "EventName": "io_wr_cpipe", + "Filter": "ext=1", + "BriefDescription": "the number of IO send stream write request to CPIPE to L3", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x06", + "EventName": "io_wr_cpipe_ext", + "Filter": "ext=2", + "BriefDescription": "the number of IO send stream write request to CPIPE to L3 ext", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x07", + "EventName": "io_wr_hit_cpipe", + "Filter": "ext=1", + "BriefDescription": "the number of IO stream write request hit CPIPE to L3", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x07", + "EventName": "io_wr_hit_cpipe_ext", + "Filter": "ext=2", + "BriefDescription": "the number of IO stream write request hit CPIPE to L3 ext", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x0c", + "EventName": "victim_num", + "Filter": "ext=1", + "BriefDescription": "the number of victim entries in L3", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x0c", + "EventName": "victim_num_ext", + "Filter": "ext=2", + "BriefDescription": "the number of victim entries in L3 ext", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x0d", + "EventName": "l3d_compress_alloc_solo", + "BriefDescription": "the number of times that data is not compressed when alloc L3D data is compressed", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x0e", + "EventName": "l3d_compress_alloc_twins", + "BriefDescription": "the number of times that data is compressed when alloc L3D data is compressed", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x0f", + "EventName": "l3d_compress_vic_solo", + "BriefDescription": "the number of times that only 64-byte data is compressed during data replacement", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x10", + "EventName": "l3d_compress_vic_twins", + "BriefDescription": "the number of times that only 128-byte data is compressed during data replacement", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x12", + "EventName": "l3d_alloc", + "BriefDescription": "the number of l3d allocs", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x18", + "EventName": "rd_spipe", + "BriefDescription": "the number of SPipe from CPU send read request", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x19", + "EventName": "rd_hit_spipe", + "BriefDescription": "the number of SPipe from CPU read request hit", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1a", + "EventName": "wr_spipe", + "BriefDescription": "the number of SPipe from CPU send stream write request", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1b", + "EventName": "wr_hit_spipe", + "BriefDescription": "the number of SPipe from CPU stream write request hit", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1c", + "EventName": "io_rd_spipe", + "BriefDescription": "the number of IO send read request to SPipe", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1d", + "EventName": "io_rd_hit_spipe", + "BriefDescription": "the number of IO read request hit SPipe", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1e", + "EventName": "io_wr_spipe", + "BriefDescription": "the number of IO send stream write request to SPipe", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1f", + "EventName": "io_wr_hit_spipe", + "BriefDescription": "the number of IO send stream write request hit to SPipe", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-mn.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-mn.json new file mode 100644 index 000000000000..fac1a3300ef8 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-mn.json @@ -0,0 +1,163 @@ +[ + { + "EventCode": "0x82", + "EventName": "l3t_req_dvm_latency", + "BriefDescription": "Count of total DVM Non-Sync requests latency from L3T", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x09", + "EventName": "l3t_req_dvm_num", + "BriefDescription": "Count the number of DVM Non-Sync requests from L3T", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x83", + "EventName": "l3t_req_dvmsync_latency", + "BriefDescription": "Count of total DVM -Sync requests latency from L3T", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x0A", + "EventName": "l3t_req_dvmsync_num", + "BriefDescription": "Count the number of DVM Sync requests from L3T", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x84", + "EventName": "mn_req_dvm_latency", + "BriefDescription": "Count of total DVM Non-Sync requests latency from others MN", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x0B", + "EventName": "mn_req_dvm_num", + "BriefDescription": "Count the number of DVM Non-Sync requests from others MN", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x85", + "EventName": "mn_req_dvmsync_latency", + "BriefDescription": "Count of total DVM -Sync requests latency from others MN", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x0C", + "EventName": "mn_req_dvmsync_num", + "BriefDescription": "Count the number of DVM Sync requests from others MN", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x86", + "EventName": "pa_req_dvm_latency", + "BriefDescription": "Count of total DVM Non-Sync requests latency from PA", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x0D", + "EventName": "pa_req_dvm_num", + "BriefDescription": "Count the number of DVM Non-Sync requests from PA", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x87", + "EventName": "pa_req_dvmsync_latency", + "BriefDescription": "Count of total DVM -Sync requests latency from PA", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x0E", + "EventName": "pa_req_dvmsync_num", + "BriefDescription": "Count the number of DVM Sync requests from PA", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x00", + "EventName": "req_eobarrier_num", + "BriefDescription": "Count the number of eobarrier requests from CPU", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x01", + "EventName": "req_ecbarrier_num", + "BriefDescription": "Count the number of ecbarrier requests from CPU", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x02", + "EventName": "req_dvmop_num", + "BriefDescription": "Count the number of DVM (DVM Sync + DVM Non-Sync) opention requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x03", + "EventName": "req_dvmsync_num", + "BriefDescription": "Count the number of DVM Sync requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x04", + "EventName": "req_retry_num", + "BriefDescription": "Count the number of DVM retry requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x05", + "EventName": "req_writenosnp_num", + "BriefDescription": "Count the number of writenosnp requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x06", + "EventName": "req_readnosnp_num", + "BriefDescription": "Count the number of readnosnp requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x80", + "EventName": "snp_dvm_latency", + "BriefDescription": "Count of total DVM Non-Sync snoop requests latency", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x07", + "EventName": "snp_dvm_num", + "BriefDescription": "Count the number of DVM Non-Sync snoop requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x81", + "EventName": "snp_dvmsync_latency", + "BriefDescription": "Count of total DVM Sync snoop requests latency", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x08", + "EventName": "snp_dvmsync_num", + "BriefDescription": "Count the number of DVM Sync snoop requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-noc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-noc.json new file mode 100644 index 000000000000..5d998dbe963b --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-noc.json @@ -0,0 +1,329 @@ +[ + { + "ConfigCode": "0x0e", + "EventName": "cycles", + "BriefDescription": "Count of noc cycles", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x1a", + "EventName": "req_ingress_flow_sum", + "Filter": "ch=2", + "BriefDescription": "Count the number of req channel data flits from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x1a", + "EventName": "snp_ingress_flow_sum", + "Filter": "ch=4", + "BriefDescription": "Count the number of snp channel data flits from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x1a", + "EventName": "rsp_ingress_flow_sum", + "Filter": "ch=6", + "BriefDescription": "Count the number of rsp channel data flits from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x1a", + "EventName": "ingress_flow_sum", + "Filter": "ch=7", + "BriefDescription": "Count the number of data channel data flits from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x17", + "EventName": "req_egress_flow_sum", + "Filter": "ch=2", + "BriefDescription": "Count the number of req channel data flits from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x17", + "EventName": "snp_egress_flow_sum", + "Filter": "ch=4", + "BriefDescription": "Count the number of snp channel data flits from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x17", + "EventName": "rsp_egress_flow_sum", + "Filter": "ch=6", + "BriefDescription": "Count the number of rsp channel data flits from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x17", + "EventName": "egress_flow_sum", + "Filter": "ch=7", + "BriefDescription": "Count the number of data channel data flits from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x19", + "EventName": "req_ingress_buf_full", + "Filter": "ch=2", + "BriefDescription": "Count the number of req channel data buffer full from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x19", + "EventName": "snp_ingress_buf_full", + "Filter": "ch=4", + "BriefDescription": "Count the number of snp channel data buffer full from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x19", + "EventName": "rsp_ingress_buf_full", + "Filter": "ch=6", + "BriefDescription": "Count the number of rsp channel data buffer full from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x19", + "EventName": "ingress_buf_full", + "Filter": "ch=7", + "BriefDescription": "Count the number of data channel data buffer full from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x12", + "EventName": "req_egress_buf_full", + "Filter": "ch=2", + "BriefDescription": "Count the number of req channel data buffer full from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x12", + "EventName": "snp_egress_buf_full", + "Filter": "ch=4", + "BriefDescription": "Count the number of snp channel data buffer full from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x12", + "EventName": "rsp_egress_buf_full", + "Filter": "ch=6", + "BriefDescription": "Count the number of rsp channel data buffer full from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x12", + "EventName": "egress_buf_full", + "Filter": "ch=7", + "BriefDescription": "Count the number of data channel data buffer full from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x05", + "EventName": "req_cw_main_flow_sum", + "Filter": "ch=2", + "BriefDescription": "Count the number of req channel clockwise main Ring data flits", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x05", + "EventName": "snp_cw_main_flow_sum", + "Filter": "ch=4", + "BriefDescription": "Count the number of snp channel clockwise main Ring data flits", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x05", + "EventName": "rsp_cw_main_flow_sum", + "Filter": "ch=6", + "BriefDescription": "Count the number of rsp channel clockwise main Ring data flits", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x05", + "EventName": "cw_main_flow_sum", + "Filter": "ch=7", + "BriefDescription": "Count the number of data channel clockwise main Ring data flits", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x0d", + "EventName": "req_cc_main_flow_sum", + "Filter": "ch=2", + "BriefDescription": "Count the number of req channel counterclockwise main Ring data flits", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x0d", + "EventName": "snp_cc_main_flow_sum", + "Filter": "ch=4", + "BriefDescription": "Count the number of snp channel counterclockwise main Ring data flits", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x0d", + "EventName": "rsp_cc_main_flow_sum", + "Filter": "ch=6", + "BriefDescription": "Count the number of rsp channel counterclockwise main Ring data flits", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x0d", + "EventName": "cc_main_flow_sum", + "Filter": "ch=7", + "BriefDescription": "Count the number of data channel counterclockwise main Ring data flits", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x01", + "EventName": "req_cw_ingress_fail", + "Filter": "ch=2", + "BriefDescription": "Count the number of req channel retry data flits clockwise from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x01", + "EventName": "snp_cw_ingress_fail", + "Filter": "ch=4", + "BriefDescription": "Count the number of snp channel retry data flits clockwise from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x01", + "EventName": "rsp_cw_ingress_fail", + "Filter": "ch=6", + "BriefDescription": "Count the number of rsp channel retry data flits clockwise from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x01", + "EventName": "cw_ingress_fail", + "Filter": "ch=7", + "BriefDescription": "Count the number of data channel retry data flits clockwise from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x09", + "EventName": "req_cc_ingress_fail", + "Filter": "ch=2", + "BriefDescription": "Count the number of req channel retry data flits counterclockwise from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x09", + "EventName": "snp_cc_ingress_fail", + "Filter": "ch=4", + "BriefDescription": "Count the number of snp channel retry data flits counterclockwise from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x09", + "EventName": "rsp_cc_ingress_fail", + "Filter": "ch=6", + "BriefDescription": "Count the number of rsp channel retry data flits counterclockwise from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x09", + "EventName": "cc_ingress_fail", + "Filter": "ch=7", + "BriefDescription": "Count the number of data channel retry data flits counterclockwise from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x03", + "EventName": "req_cw_egress_fail", + "Filter": "ch=2", + "BriefDescription": "Count the number of req channel retry data flits clockwise from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x03", + "EventName": "snp_cw_egress_fail", + "Filter": "ch=4", + "BriefDescription": "Count the number of snp channel retry data flits clockwise from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x03", + "EventName": "rsp_cw_egress_fail", + "Filter": "ch=6", + "BriefDescription": "Count the number of rsp channel retry data flits clockwise from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x03", + "EventName": "cw_egress_fail", + "Filter": "ch=7", + "BriefDescription": "Count the number of data channel retry data flits clockwise from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x0b", + "EventName": "req_cc_egress_fail", + "Filter": "ch=2", + "BriefDescription": "Count the number of req channel retry data flits counterclockwise from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x0b", + "EventName": "snp_cc_egress_fail", + "Filter": "ch=4", + "BriefDescription": "Count the number of snp channel retry data flits counterclockwise from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x0b", + "EventName": "rsp_cc_egress_fail", + "Filter": "ch=6", + "BriefDescription": "Count the number of rsp channel retry data flits counterclockwise from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "ConfigCode": "0x0b", + "EventName": "cc_egress_fail", + "Filter": "ch=7", + "BriefDescription": "Count the number of data channel retry data flits counterclockwise from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-pa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-pa.json new file mode 100644 index 000000000000..b74dc7801142 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-pa.json @@ -0,0 +1,184 @@ +[ + { + "EventCode": "0x00", + "EventName": "tx_req", + "BriefDescription": "Count of the requests transmitted by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x01", + "EventName": "tx_dat", + "BriefDescription": "Count of the data transmitted by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x02", + "EventName": "tx_snp", + "BriefDescription": "Count of the snoopy transmitted by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x07", + "EventName": "rx_req", + "BriefDescription": "Count of the requests received by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x08", + "EventName": "rx_dat", + "BriefDescription": "Count of the data received by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x09", + "EventName": "rx_snp", + "BriefDescription": "Count of the snoopy received by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x78", + "EventName": "pa_cycles", + "BriefDescription": "Count of PA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x78", + "EventName": "cycle", + "BriefDescription": "Count of PA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x40", + "EventName": "rx_req", + "BriefDescription": "Count of the requests flit from Ring to PA link0", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x40", + "EventName": "pa_rx_req_link0", + "BriefDescription": "Count of the requests flit from Ring to PA link0", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x41", + "EventName": "pa_rx_req_link1", + "BriefDescription": "Count of the requests flit from Ring to PA link1", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x42", + "EventName": "pa_rx_req_link2", + "BriefDescription": "Count of the requests flit from Ring to PA link2", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x43", + "EventName": "pa_rx_req_link3", + "BriefDescription": "Count of the requests flit from Ring to PA link3", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x44", + "EventName": "pa_rx_data_link0", + "BriefDescription": "Count of the data flit from Ring to PA link0", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x45", + "EventName": "pa_rx_data_link1", + "BriefDescription": "Count of the data flit from Ring to PA link1", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x46", + "EventName": "pa_rx_data_link2", + "BriefDescription": "Count of the data flit from Ring to PA link2", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x47", + "EventName": "pa_rx_data_link3", + "BriefDescription": "Count of the data flit from Ring to PA link3", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x5c", + "EventName": "tx_req", + "BriefDescription": "Count of the total flit transmitted by PA link0", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x60", + "EventName": "pa_tx_req_link0", + "BriefDescription": "Count of the requests flit from PA link0 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x61", + "EventName": "pa_tx_req_link1", + "BriefDescription": "Count of the requests flit from PA link1 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x62", + "EventName": "pa_tx_req_link2", + "BriefDescription": "Count of the requests flit from PA link2 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x63", + "EventName": "pa_tx_req_link3", + "BriefDescription": "Count of the requests flit from PA link3 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x64", + "EventName": "pa_tx_data_link0", + "BriefDescription": "Count of the data flit from PA link0 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x65", + "EventName": "pa_tx_data_link1", + "BriefDescription": "Count of the data flit from PA link1 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x66", + "EventName": "pa_tx_data_link2", + "BriefDescription": "Count of the data flit from PA link2 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x67", + "EventName": "pa_tx_data_link3", + "BriefDescription": "Count of the data flit from PA link3 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-sllc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-sllc.json new file mode 100644 index 000000000000..745d649501fc --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-sllc.json @@ -0,0 +1,132 @@ +[ + { + "EventCode": "0x09", + "EventName": "sllc_cycles", + "BriefDescription": "Count of SLLC cycles", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x09", + "EventName": "cycles", + "BriefDescription": "Count of SLLC cycles", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x20", + "EventName": "sllc_rx_req_lat", + "BriefDescription": "Total latency SLLC taken to receive requests", + "Filter": "tracetag_en", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x21", + "EventName": "sllc_rx_data_lat", + "BriefDescription": "Total latency SLLC taken to receive data", + "Filter": "tracetag_en", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x24", + "EventName": "sllc_tx_req_lat", + "BriefDescription": "Total latency SLLC taken to transmit requests", + "Filter": "tracetag_en", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x25", + "EventName": "sllc_tx_data_lat", + "BriefDescription": "Total latency SLLC taken to transmit data", + "Filter": "tracetag_en", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x30", + "EventName": "rx_req", + "BriefDescription": "Count of the requests received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x30", + "EventName": "sllc_rx_req", + "BriefDescription": "Count of the requests received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x31", + "EventName": "rx_data", + "BriefDescription": "Count of the data received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x31", + "EventName": "sllc_rx_data", + "BriefDescription": "Count of the data received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x32", + "EventName": "sllc_rx_snp", + "BriefDescription": "Count of the snoop received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x33", + "EventName": "sllc_rx_rsp", + "BriefDescription": "Count of the response received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x34", + "EventName": "tx_req", + "BriefDescription": "Count of the requests transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x34", + "EventName": "sllc_tx_req", + "BriefDescription": "Count of the requests transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x35", + "EventName": "tx_data", + "BriefDescription": "Count of the data transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x35", + "EventName": "sllc_tx_data", + "BriefDescription": "Count of the data transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x36", + "EventName": "sllc_tx_snp", + "BriefDescription": "Count of the snoop transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x37", + "EventName": "sllc_tx_rsp", + "BriefDescription": "Count of the response transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-uc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-uc.json new file mode 100644 index 000000000000..076b81ca7a21 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-uc.json @@ -0,0 +1,462 @@ +[ + { + "EventCode": "0x00", + "EventName": "sq_time", + "Filter": "rd_req_en=1", + "BriefDescription": "Count the total latency that sq completed cpu request", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x01", + "EventName": "pq_time", + "Filter": "rd_req_en=1", + "BriefDescription": "Count the total latency that pq completed cpu request", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x02", + "EventName": "hbm_time", + "Filter": "rd_req_en=1", + "BriefDescription": "Count the total latency that UC requests to access the HBM", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x03", + "EventName": "iq_comp_time_cring", + "Filter": "rd_req_en=1", + "BriefDescription": "Count the total latency that CRING completed cpu request", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x05", + "EventName": "iq_comp_time_uring", + "Filter": "rd_req_en=1", + "BriefDescription": "Count the total latency that URING completed cpu request", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x10", + "EventName": "cpu_rd", + "BriefDescription": "Count of the number of the read request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x11", + "EventName": "cpu_wr", + "BriefDescription": "Count of the number of the write request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x12", + "EventName": "cpu_atomic", + "BriefDescription": "Count of the number of the atomic request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x17", + "EventName": "cpu_rd64", + "BriefDescription": "Count of the number of the cpu_rd64 request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x18", + "EventName": "cpu_rd128", + "BriefDescription": "Count of the number of the cpu_rd128 request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x19", + "EventName": "cpu_rs64", + "BriefDescription": "Count of the number of the cpu_rs64 request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x1a", + "EventName": "cpu_rs128", + "BriefDescription": "Count of the number of the cpu_rs128 request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x1C", + "EventName": "cpu_mru", + "BriefDescription": "Count of the number of the cpu_mru request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x2C", + "EventName": "ext2uc_read", + "BriefDescription": "Count of the number of the read request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x2D", + "EventName": "ext2uc_write", + "BriefDescription": "Count of the number of the write request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x2E", + "EventName": "ext2uc_atomic", + "BriefDescription": "Count of the number of the atomic request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x33", + "EventName": "ext2uc_ru64", + "BriefDescription": "Count of the number of the 64B ReadUnique request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x34", + "EventName": "ext2uc_ru128", + "BriefDescription": "Count of the number of the 128B ReadUnique request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x35", + "EventName": "ext2uc_rs64", + "BriefDescription": "Count of the number of the 64B ReadShared request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x36", + "EventName": "ext2uc_rs128", + "BriefDescription": "Count of the number of the 128B ReadShared request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x47", + "EventName": "uc2ext_read_uring", + "BriefDescription": "Count of the number of the read request from uc to uring", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x48", + "EventName": "uc2ext_write_uring", + "BriefDescription": "Count of the number of the write request from uc to uring", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x49", + "EventName": "uc2ext_atomic_uring", + "BriefDescription": "Count of the number of the atomic message sent by the UC from the URIING to the EXT", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x5C", + "EventName": "io2uc_atomic", + "BriefDescription": "Count of the number of the I/O Atomic messages received by the UC", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x60", + "EventName": "io2uc_write", + "BriefDescription": "Count of the number of the UC receives a write request from the I/O", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x7E", + "EventName": "uc2cpu_retry", + "BriefDescription": "Count of the number of the retry packets sent from the UC to the CPU", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x7F", + "EventName": "uc2ext_retry", + "BriefDescription": "Count of the number of the retry sent from the UC to the EXT", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x81", + "EventName": "uc2hbm_bank0_rd64", + "BriefDescription": "Count of the number of the 64B read request sent by the UC to HBMC BANK0", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x82", + "EventName": "uc2hbm_bank0_rd128", + "BriefDescription": "Count of the number of the 128B read request sent from the UC to HBMC BANK0", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x83", + "EventName": "uc2hbm_bank0_wr64", + "BriefDescription": "Count of the number of the 64B write request sent by the UC to HBMC BANK0", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x84", + "EventName": "uc2hbm_bank0_wr128", + "BriefDescription": "Count of the number of the 128B write request sent by the UC to HBMC BANK0", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x87", + "EventName": "uc2hbm_bank1_rd64", + "BriefDescription": "Count of the number of the 64B read request sent by the UC to HBMC BANK1", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x88", + "EventName": "uc2hbm_bank1_rd128", + "BriefDescription": "Count of the number of the 128B read request sent by the UC to HBMC BANK1", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x89", + "EventName": "uc2hbm_bank1_wr64", + "BriefDescription": "Count of the number of the 64B write request sent from the UC to HBMC BANK1", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x8A", + "EventName": "uc2hbm_bank1_wr128", + "BriefDescription": "Count of the number of the 128B write request sent from the UC to HBMC BANK1", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x8D", + "EventName": "uc2sdmaa_retry", + "BriefDescription": "Count of the number of retry messages received by the SDMAA module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x8E", + "EventName": "uc2sdmaa_pgnt", + "BriefDescription": "Count of the number of pgnt messages received by the SDMAA module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x8F", + "EventName": "sdmaa2uc_unalign", + "BriefDescription": "Count of the number of Unaligned Small Packets Delivered by SDMAA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x91", + "EventName": "sdmaa2uc_read", + "BriefDescription": "Count of the number of SDMAA Read Requests", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x92", + "EventName": "sdmaa2uc_write", + "BriefDescription": "Count of the number of SDMAA Write Requests", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x93", + "EventName": "sdmaa2uc_memset", + "BriefDescription": "Count of the number of memsets delivered by SDMAA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x94", + "EventName": "sdmaa_tx_preload", + "BriefDescription": "Count of the number of preload operations delivered by the SDMAA module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x95", + "EventName": "cycles", + "BriefDescription": "Count of the nUC cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xB1", + "EventName": "hpipe_lookup", + "BriefDescription": "Count of SPIPE lookup", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xB3", + "EventName": "hpipe_hit", + "BriefDescription": "Count of the number of spipe hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xB4", + "EventName": "hpipe_rd_hit", + "BriefDescription": "Count of SPIPE read hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xB5", + "EventName": "hpipe_wr_hit", + "BriefDescription": "Count of SPIPE write hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xBA", + "EventName": "hc_pipe_lookup", + "BriefDescription": "Count of HC_PIPE lookup", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xBB", + "EventName": "hc_pipe_hit_1k", + "BriefDescription": "Count of HC_PIPE hit 1k", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xBD", + "EventName": "hc_pipe_rd_hit", + "BriefDescription": "Count of HC_PIPE read hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xBE", + "EventName": "hc_pipe_wr_hit", + "BriefDescription": "Count of HC_PIPE write hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xCE", + "EventName": "sc_pipe_lookup", + "BriefDescription": "Count of SC_PIPE lookup", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xCF", + "EventName": "sc_pipe_hit_sector", + "BriefDescription": "Count of SC_PIPE hit sector", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xD1", + "EventName": "sc_pipe_rd_hit", + "BriefDescription": "Count of SC_PIPE read hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xD2", + "EventName": "sc_pipe_wr_hit", + "BriefDescription": "Count of SC_PIPE write hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xD9", + "EventName": "spipe_lookup", + "BriefDescription": "Count of HPIPE lookup", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xDB", + "EventName": "spipe_hit", + "BriefDescription": "Count of the number of hpipe hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xDC", + "EventName": "spipe_rd_hit", + "BriefDescription": "Count of HPIPE read hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xDD", + "EventName": "spipe_wr_hit", + "BriefDescription": "Count of HPIPE write hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFA", + "EventName": "cring_rxdat_cnt", + "BriefDescription": "Count of the number of packets received by the UC from the cring", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFB", + "EventName": "cring_txdat_cnt", + "BriefDescription": "Count of the number of packets sent from the UC to the CRING", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFC", + "EventName": "uring_rxdat_cnt", + "BriefDescription": "Count of the number of Indicates the number of packets received by the UC from the uring module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFD", + "EventName": "uring_txdat_cnt", + "BriefDescription": "Count of the number of Indicates the number of packets sent from the UC to the enabling module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFE", + "EventName": "uring_rxreqdat_cnt", + "BriefDescription": "Count of the number of data combination request packets received by the UC from the uring module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xFF", + "EventName": "uring_txreqdat_cnt", + "BriefDescription": "Count of the number of data combination requests sent by the UC to the uring module", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index 32674ddd2b63..eba566b78ebc 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -40,5 +40,7 @@ 0x00000000430f0af0,v1,cavium/thunderx2,core 0x00000000460f0010,v1,fujitsu/a64fx,core 0x00000000480fd010,v1,hisilicon/hip08,core +0x00000000480fd030,v1,hisilicon/hip10,core +0x00000000480fd060,v1,hisilicon/hip12,core 0x00000000500f0000,v1,ampere/emag,core 0x00000000c00fac30,v1,ampere/ampereone,core diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index a89fc42278f0..c53ff85fca96 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -283,6 +283,8 @@ class JsonEvent: 'hisi_sccl,ddrc': 'hisi_sccl,ddrc', 'hisi_sccl,hha': 'hisi_sccl,hha', 'hisi_sccl,l3c': 'hisi_sccl,l3c', + 'hisi_scl,noc': 'hisi_scl,noc', + 'hisi_scl,mn': 'hisi_scl,mn', 'imx8_ddr': 'imx8_ddr', 'L3PMC': 'amd_l3', 'DFPMC': 'amd_df', -- 2.33.0