From: w00623716 <wushuai51@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I9EMOF CVE: NA Reference: NA --------------------------------- The RDMA driver supports the following features: Supports Huawei SP600 series NICs; Supports RoCEv2; Supports RoCE XRC, UD, UC, and RC modes; Supports RoCE UC, RC, and UD local switching; Supports RoCE MR, PD, CQ, QoS, QP, and SRQ management; Supports RoCE congestion control; Supports RoCE Bond; Supports RoCE FLR; Supports RoCE entry specifications; Supports RoCE error detection and reporting; Signed-off-by: w00623716 <wushuai51@huawei.com> --- arch/arm64/configs/openeuler_defconfig | 1 + arch/x86/configs/openeuler_defconfig | 1 + drivers/infiniband/Kconfig | 1 + drivers/infiniband/hw/Makefile | 1 + drivers/infiniband/hw/hiroce3/Kconfig | 14 + drivers/infiniband/hw/hiroce3/Makefile | 157 + .../infiniband/hw/hiroce3/bond/roce_bond.h | 149 + .../hw/hiroce3/bond/roce_bond_common.c | 950 + drivers/infiniband/hw/hiroce3/cq/roce_cq.h | 265 + .../infiniband/hw/hiroce3/cq/roce_cq_common.c | 202 + .../infiniband/hw/hiroce3/cq/roce_cq_cqe.c | 731 + .../infiniband/hw/hiroce3/cq/roce_cq_create.c | 604 + .../infiniband/hw/hiroce3/cq/roce_cq_ctrl.c | 872 + .../hw/hiroce3/cq/roce_cq_destroy.c | 298 + drivers/infiniband/hw/hiroce3/dfx/roce_dfx.c | 126 + drivers/infiniband/hw/hiroce3/dfx/roce_dfx.h | 184 + .../infiniband/hw/hiroce3/dfx/roce_dfx_cap.c | 676 + .../infiniband/hw/hiroce3/dfx/roce_dfx_cap.h | 184 + .../hw/hiroce3/dfx/roce_dfx_query.c | 615 + .../hiroce3/extension/roce_cdev_extension.c | 18 + .../hiroce3/extension/roce_event_extension.c | 30 + .../hiroce3/extension/roce_main_extension.c | 206 + .../hw/hiroce3/extension/roce_mr_extension.c | 38 + .../hiroce3/extension/roce_netdev_extension.c | 174 + .../hw/hiroce3/extension/roce_qp_extension.c | 251 + .../extension/roce_qp_post_send_extension.c | 20 + .../hw/hiroce3/extension/roce_srq_extension.c | 35 + .../hw/hiroce3/host/crypt/hisec_cfg.c | 148 + .../hw/hiroce3/host/crypt/hisec_cfg.h | 26 + .../hw/hiroce3/host/crypt/hisec_hwrand.c | 229 + .../hw/hiroce3/host/crypt/hisec_hwrand.h | 14 + .../host/crypt/linux/kernel/hisec_crypt_dev.h | 29 + .../crypt/linux/kernel/hisec_crypt_main.c | 123 + .../hw/hiroce3/host/crypt/readme.txt | 1 + .../hw/hiroce3/host/hmm/hmm_buddy.c | 170 + .../hw/hiroce3/host/hmm/hmm_buddy.h | 36 + .../infiniband/hw/hiroce3/host/hmm/hmm_comp.c | 165 + .../infiniband/hw/hiroce3/host/hmm/hmm_comp.h | 225 + .../hw/hiroce3/host/hmm/hmm_comp_init.c | 131 + .../hw/hiroce3/host/hmm/hmm_comp_mtt.c | 497 + .../hw/hiroce3/host/hmm/hmm_comp_mw_mr.c | 222 + .../hw/hiroce3/host/hmm/hmm_comp_res.c | 63 + .../infiniband/hw/hiroce3/host/hmm/hmm_em.c | 348 + .../infiniband/hw/hiroce3/host/hmm/hmm_em.h | 48 + .../infiniband/hw/hiroce3/host/hmm/hmm_mr.c | 403 + .../infiniband/hw/hiroce3/host/hmm/hmm_mr.h | 34 + .../infiniband/hw/hiroce3/host/hmm/hmm_umem.c | 322 + .../infiniband/hw/hiroce3/host/hmm/hmm_umem.h | 124 + .../hw/hiroce3/host/mt/hinic3_devlink.c | 428 + .../hw/hiroce3/host/mt/hinic3_devlink.h | 173 + .../hw/hiroce3/host/mt/hinic3_hw_mt.c | 605 + .../hw/hiroce3/host/mt/hinic3_hw_mt.h | 49 + .../hw/hiroce3/host/mt/hinic3_nictool.c | 982 + .../hw/hiroce3/host/mt/hinic3_nictool.h | 35 + .../infiniband/hw/hiroce3/host/mt/readme.txt | 1 + .../hw/hiroce3/host/vram/vram_common.c | 192 + .../hw/hiroce3/include/crypt/hisec_mpu_cmd.h | 38 + .../include/crypt/hisec_mpu_cmd_defs.h | 118 + .../hw/hiroce3/include/crypt/hisec_npu_cmd.h | 30 + .../include/crypt/hisec_npu_cmd_defs.h | 415 + .../hw/hiroce3/include/hinic3_hmm.h | 83 + .../hw/hiroce3/include/hinic3_rdma.h | 203 + .../hw/hiroce3/include/hinic3_srv_nic.h | 218 + .../hw/hiroce3/include/hw/db_srv_type_pub.h | 126 + .../hw/hiroce3/include/hw/node_id.h | 58 + .../hw/register/infra/cnb_c_union_define.h | 318 + .../hw/register/infra/cnb_reg_offset.h | 42 + .../hw/register/infra/cpb_c_union_define.h | 8234 + .../hw/register/infra/cpb_reg_offset.h | 1157 + .../hw/register/infra/cpi_c_union_define.h | 23677 +++ .../register/infra/cpi_dfx_glb_reg_offset.h | 236 + .../hw/register/infra/cpi_reg_offset.h | 4698 + .../hw/register/infra/crypto_c_union_define.h | 6226 + .../hw/register/infra/crypto_reg_offset.h | 1181 + .../hw/register/infra/esch_c_union_define.h | 1340 + .../hw/register/infra/esch_reg_offset.h | 802 + .../infra/hi1823_csr_sm_addr_define.h | 384 + .../hw/register/infra/hi1823_csr_sm_typedef.h | 12259 ++ .../register/infra/hinic3_csr_addr_common.h | 254 + .../hw/register/infra/icdq_c_union_define.h | 1062 + .../hw/register/infra/icdq_reg_offset.h | 114 + .../hw/register/infra/ipsurx_c_union_define.h | 4805 + .../hw/register/infra/ipsurx_reg_offset.h | 1469 + .../hw/register/infra/ipsurx_typedef.h | 30688 ++++ .../hw/register/infra/ipsutx_c_union_define.h | 2872 + .../hw/register/infra/ipsutx_reg_offset.h | 429 + .../hw/register/infra/lcam_c_union_define.h | 741 + .../hw/register/infra/lcam_reg_offset.h | 72 + .../hw/register/infra/mqm_c_union_define.h | 11885 ++ .../hw/register/infra/mqm_reg_offset.h | 3696 + .../hw/register/infra/oq_c_union_define.h | 2285 + .../include/hw/register/infra/oq_reg_offset.h | 261 + .../hw/register/infra/pe_c_union_define.h | 1819 + .../include/hw/register/infra/pe_reg_offset.h | 493 + .../hw/register/infra/pqm_c_union_define.h | 2091 + .../hw/register/infra/pqm_reg_offset.h | 291 + .../hw/register/infra/prmrx_c_union_define.h | 2937 + .../hw/register/infra/prmrx_reg_offset.h | 258 + .../hw/register/infra/prmtx_c_union_define.h | 2758 + .../hw/register/infra/prmtx_reg_offset.h | 264 + .../register/infra/ring_cnb_c_union_define.h | 314 + .../hw/register/infra/ring_cnb_reg_offset.h | 52 + .../hw/register/infra/sm_c_union_define.h | 6441 + .../include/hw/register/infra/sm_reg_offset.h | 860 + .../hw/register/infra/stffq_c_union_define.h | 6438 + .../hw/register/infra/stffq_reg_offset.h | 1059 + .../hw/register/infra/stfiq_c_union_define.h | 1413 + .../hw/register/infra/stfiq_reg_offset.h | 148 + .../register/infra/stfisch_c_union_define.h | 420 + .../hw/register/infra/stfisch_reg_offset.h | 828 + .../hw/register/infra/stlfq_c_union_define.h | 6358 + .../hw/register/infra/stlfq_reg_offset.h | 535 + .../hw/register/infra/stliq_c_union_define.h | 1109 + .../hw/register/infra/stliq_reg_offset.h | 106 + .../register/infra/stlisch_c_union_define.h | 425 + .../hw/register/infra/stlisch_reg_offset.h | 527 + .../hw/register/infra/tile_c_union_define.h | 3399 + .../hw/register/infra/tile_reg_offset.h | 399 + .../hw/register/infra/virtio_c_union_define.h | 4349 + .../hw/register/infra/virtio_reg_offset.h | 275 + .../hw/register/mag/c_union_define_mag_top.h | 1695 + .../hw/register/mag/c_union_define_smag_cfg.h | 1457 + .../mag/hi1822_csr_mag_offset_union_define.h | 22 + .../hw/register/mag/mac_reg_an_lth60_offset.h | 483 + .../hw/register/mag/mac_reg_com_offset.h | 33 + .../hw/register/mag/mac_reg_mib_offset.h | 26 + .../hw/register/mag/mac_reg_rx_brfec_offset.h | 68 + .../hw/register/mag/mac_reg_rx_mac_offset.h | 95 + .../hw/register/mag/mac_reg_rx_pcs_offset.h | 343 + .../hw/register/mag/mac_reg_rx_rsfec_offset.h | 503 + .../register/mag/mac_reg_rxpma_core_offset.h | 213 + .../register/mag/mac_reg_rxpma_lane_offset.h | 44 + .../hw/register/mag/mac_reg_tx_brfec_offset.h | 62 + .../hw/register/mag/mac_reg_tx_mac_offset.h | 109 + .../hw/register/mag/mac_reg_tx_pcs_offset.h | 169 + .../hw/register/mag/mac_reg_tx_rsfec_offset.h | 75 + .../register/mag/mac_reg_txpma_core_offset.h | 19 + .../register/mag/mac_reg_txpma_lane_offset.h | 43 + .../mag/mag_fc_sds_harden_reg_offset.h | 60 + .../hw/register/mag/mag_top_reg_offset.h | 379 + .../hw/register/mag/smag_cfg_reg_offset.h | 277 + .../hw/register/misc/sfc_c_union_define.h | 721 + .../include/hw/register/misc/sfc_reg_offset.h | 217 + .../hw/register/mpu/c_union_define_crg.h | 625 + .../include/hw/register/mpu/crg_reg_offset.h | 68 + .../hw/register/mpu/mpu_c_union_define.h | 15330 ++ .../register/mpu/mpu_harden_c_union_define.h | 795 + .../hw/register/mpu/mpu_harden_reg_offset.h | 461 + .../include/hw/register/mpu/mpu_reg_offset.h | 2115 + .../hw/register/pcie/hva_peh_c_union_define.h | 3236 + .../hw/register/pcie/hva_peh_reg_offset.h | 214 + .../hw/register/pcie/pcie5_ap_addr_define.h | 40529 +++++ .../hw/register/pcie/pcie5_ap_typedef.h | 42419 ++++++ .../hw/register/pcie/pcie5_core_addr_define.h | 3233 + .../hw/register/pcie/pcie5_core_typedef.h | 118101 +++++++++++++++ .../hw/register/pcie/pcie5_pcs_addr_define.h | 286 + .../hw/register/pcie/pcie5_pcs_typedef.h | 11995 ++ .../hw/register/rxtx/apb2ff_reg_offset.h | 68 + .../hw/register/rxtx/c_union_define_apb2ff.h | 82 + .../register/top/mag_harden_c_union_define.h | 484 + .../hw/register/top/mag_harden_reg_offset.h | 55 + .../register/top/pcie_harden_c_union_define.h | 738 + .../hw/register/top/pcie_harden_reg_offset.h | 65 + .../register/top/smf0_harden_c_union_define.h | 1611 + .../hw/register/top/smf0_harden_reg_offset.h | 69 + .../top/stlqu_harden_c_union_define.h | 662 + .../hw/register/top/stlqu_harden_reg_offset.h | 69 + .../register/top/top_cpb_harden_reg_offset.h | 42 + .../top_encryp_decryp_harden_c_union_define.h | 48 + .../top/top_encryp_decryp_harden_reg_offset.h | 73 + .../hw/register/top/top_iocfg_reg_offset.h | 81 + .../register/totem/arm_ras_c_union_define.h | 192 + .../hw/register/totem/avs_reg_offset.h | 875 + .../register/totem/ddrc_arm_ras_reg_offset.h | 31 + .../hw/register/totem/ddrc_dmc_c_union_def.h | 102 + .../hw/register/totem/ddrc_dmc_reg_offset.h | 314 + .../register/totem/ddrc_rasc_c_union_define.h | 1411 + .../hw/register/totem/ddrc_rasc_reg_offset.h | 192 + .../hw/register/totem/efuse_reg_offset.h | 125 + .../hw/register/totem/fabric_c_union_define.h | 1629 + .../hw/register/totem/fabric_reg_offset.h | 102 + .../hw/register/totem/hha_c_union_def.h | 62 + .../hw/register/totem/hva_c_union_define.h | 1287 + .../hw/register/totem/hva_reg_offset.h | 110 + .../register/totem/hva_sm23_c_union_define.h | 43 + .../hw/register/totem/hva_sm23_reg_offset.h | 37 + .../register/totem/hva_smf_c_union_define.h | 1194 + .../hw/register/totem/hva_smf_reg_offset.h | 189 + .../hw/register/totem/mbigen_c_union_define.h | 643 + .../hw/register/totem/mbigen_reg_offset.h | 956 + .../hw/register/totem/pcie4_c_union_define.h | 5992 + .../hw/register/totem/pcie4_reg_offset.h | 2240 + .../register/totem/phosphor_c_union_define.h | 2841 + .../hw/register/totem/phosphor_reg_offset.h | 149 + .../include/hw/register/totem/plat_efuse.h | 368 + .../hw/register/totem/ras_c_union_define.h | 295 + .../hw/register/totem/ras_reg_offset.h | 110 + .../hw/register/totem/sioe_reg_offset.h | 426 + .../hw/register/totem/sllc_reg_offset.h | 150 + .../hw/register/totem/smmu_c_union_define.h | 2448 + .../hw/register/totem/smmu_reg_offset.h | 256 + .../hw/register/totem/sysctrl_reg_offset.h | 316 + .../hw/hiroce3/include/hw/service_type_pub.h | 135 + .../hw/hiroce3/include/hw/smf_cache_type.h | 142 + .../hw/hiroce3/include/hw/smf_instance_id.h | 168 + .../hw/hiroce3/include/hw/sml_table.h | 4079 + .../include/hw/sml_table_define_cloud.h | 273 + .../include/hw/sml_table_define_compute_dpu.h | 12 + .../hw/sml_table_define_compute_roce.h | 137 + .../hw/sml_table_define_compute_standard.h | 234 + .../include/hw/sml_table_define_fpga.h | 340 + .../hiroce3/include/hw/sml_table_define_llt.h | 361 + .../include/hw/sml_table_define_storage_fc.h | 65 + .../hw/sml_table_define_storage_fc_adapt.h | 65 + .../hw/sml_table_define_storage_roce.h | 149 + .../hw/sml_table_define_storage_roceaa.h | 164 + .../include/hw/sml_table_define_storage_toe.h | 113 + .../hw/hiroce3/include/hw/sml_table_pub.h | 330 + .../hw/hiroce3/include/hw/tile_spec.h | 28 + .../hw/hiroce3/include/mag/mag_mpu_cmd.h | 77 + .../hw/hiroce3/include/mag/mag_mpu_cmd_defs.h | 928 + .../include/micro_log/hinic3_micro_log.c | 1156 + .../include/micro_log/hinic3_micro_log.h | 169 + .../hw/hiroce3/include/nic/nic_cfg_comm.h | 62 + .../hw/hiroce3/include/nic/nic_mpu_cmd.h | 147 + .../hw/hiroce3/include/nic/nic_mpu_cmd_defs.h | 1317 + .../hw/hiroce3/include/nic/nic_npu_cmd.h | 31 + .../hw/hiroce3/include/nic/nic_npu_cmd_defs.h | 140 + .../hw/hiroce3/include/nic/nic_npu_wqe_defs.h | 240 + .../include/public/npu_cmdq_base_defs.h | 241 + .../include/rdma/rdma_context_format.h | 4435 + .../include/rdma/rdma_ext_ctx_format.h | 382 + .../hw/hiroce3/include/rdma/roce_ccf_format.h | 725 + .../hiroce3/include/rdma/roce_compile_macro.h | 91 + .../hw/hiroce3/include/rdma/roce_ctx_api.h | 265 + .../hw/hiroce3/include/rdma/roce_dif_format.h | 459 + .../hw/hiroce3/include/rdma/roce_err_type.h | 125 + .../hiroce3/include/rdma/roce_hmm_context.h | 196 + .../hw/hiroce3/include/rdma/roce_mpu_common.h | 241 + .../include/rdma/roce_mpu_ulp_common.h | 56 + .../hw/hiroce3/include/rdma/roce_pub.h | 262 + .../hw/hiroce3/include/rdma/roce_pub_cmd.h | 264 + .../hw/hiroce3/include/rdma/roce_ulp.h | 177 + .../hw/hiroce3/include/rdma/roce_vbs_format.h | 208 + .../hw/hiroce3/include/rdma/roce_verbs_attr.h | 400 + .../include/rdma/roce_verbs_attr_qpc_chip.h | 355 + .../hw/hiroce3/include/rdma/roce_verbs_cmd.h | 250 + .../hiroce3/include/rdma/roce_verbs_cq_attr.h | 170 + .../include/rdma/roce_verbs_ext_attr.h | 51 + .../hiroce3/include/rdma/roce_verbs_format.h | 134 + .../include/rdma/roce_verbs_gid_attr.h | 112 + .../hiroce3/include/rdma/roce_verbs_mr_attr.h | 299 + .../hw/hiroce3/include/rdma/roce_verbs_pub.h | 226 + .../include/rdma/roce_verbs_srq_attr.h | 229 + .../include/rdma/roce_verbs_ulp_format.h | 94 + .../hw/hiroce3/include/rdma/roce_wqe_format.h | 825 + .../hw/hiroce3/include/rdma/roce_xqe_format.h | 500 + .../infiniband/hw/hiroce3/include/readme.txt | 1 + .../hw/hiroce3/include/roce_cdev_extension.h | 20 + .../hw/hiroce3/include/roce_event_extension.h | 20 + .../hw/hiroce3/include/roce_main_extension.h | 84 + .../hw/hiroce3/include/roce_mr_extension.h | 24 + .../hiroce3/include/roce_netdev_extension.h | 26 + .../hw/hiroce3/include/roce_qp_extension.h | 69 + .../include/roce_qp_post_send_extension.h | 24 + .../hw/hiroce3/include/roce_srq_extension.h | 20 + drivers/infiniband/hw/hiroce3/mr/roce_mr.c | 1305 + drivers/infiniband/hw/hiroce3/mr/roce_mr.h | 105 + drivers/infiniband/hw/hiroce3/qp/roce_post.h | 198 + drivers/infiniband/hw/hiroce3/qp/roce_qp.h | 255 + .../infiniband/hw/hiroce3/qp/roce_qp_create.c | 1296 + .../hw/hiroce3/qp/roce_qp_destroy.c | 289 + .../infiniband/hw/hiroce3/qp/roce_qp_exp.h | 86 + .../infiniband/hw/hiroce3/qp/roce_qp_modify.c | 2162 + .../hw/hiroce3/qp/roce_qp_post_recv.c | 253 + .../hw/hiroce3/qp/roce_qp_post_send.c | 1257 + .../infiniband/hw/hiroce3/qp/roce_qp_query.c | 386 + .../infiniband/hw/hiroce3/rdma/rdma_bitmap.c | 141 + .../infiniband/hw/hiroce3/rdma/rdma_bitmap.h | 41 + .../infiniband/hw/hiroce3/rdma/rdma_comp.c | 29 + .../infiniband/hw/hiroce3/rdma/rdma_comp.h | 138 + .../hw/hiroce3/rdma/rdma_comp_gid.c | 275 + .../hw/hiroce3/rdma/rdma_comp_init.c | 387 + .../hw/hiroce3/rdma/rdma_comp_mw_mr.c | 244 + .../infiniband/hw/hiroce3/rdma/rdma_comp_pd.c | 57 + .../hw/hiroce3/rdma/rdma_comp_res.c | 247 + drivers/infiniband/hw/hiroce3/roce.h | 635 + drivers/infiniband/hw/hiroce3/roce_cdev.c | 1218 + drivers/infiniband/hw/hiroce3/roce_cmd.c | 753 + drivers/infiniband/hw/hiroce3/roce_cmd.h | 78 + drivers/infiniband/hw/hiroce3/roce_compat.h | 60 + drivers/infiniband/hw/hiroce3/roce_cqm_cmd.c | 57 + drivers/infiniband/hw/hiroce3/roce_cqm_cmd.h | 20 + drivers/infiniband/hw/hiroce3/roce_db.c | 103 + drivers/infiniband/hw/hiroce3/roce_db.h | 36 + drivers/infiniband/hw/hiroce3/roce_event.c | 568 + drivers/infiniband/hw/hiroce3/roce_event.h | 43 + drivers/infiniband/hw/hiroce3/roce_k_ioctl.h | 96 + drivers/infiniband/hw/hiroce3/roce_main.c | 1752 + drivers/infiniband/hw/hiroce3/roce_mix.c | 1402 + drivers/infiniband/hw/hiroce3/roce_mix.h | 210 + drivers/infiniband/hw/hiroce3/roce_netdev.c | 858 + drivers/infiniband/hw/hiroce3/roce_netdev.h | 65 + drivers/infiniband/hw/hiroce3/roce_netlink.c | 368 + drivers/infiniband/hw/hiroce3/roce_netlink.h | 171 + drivers/infiniband/hw/hiroce3/roce_pd.c | 137 + drivers/infiniband/hw/hiroce3/roce_pd.h | 31 + drivers/infiniband/hw/hiroce3/roce_sysfs.c | 1787 + drivers/infiniband/hw/hiroce3/roce_sysfs.h | 115 + drivers/infiniband/hw/hiroce3/roce_user.h | 72 + drivers/infiniband/hw/hiroce3/roce_xrc.c | 203 + drivers/infiniband/hw/hiroce3/roce_xrc.h | 30 + drivers/infiniband/hw/hiroce3/srq/roce_srq.h | 204 + .../infiniband/hw/hiroce3/srq/roce_srq_comm.c | 97 + .../hw/hiroce3/srq/roce_srq_create.c | 710 + .../infiniband/hw/hiroce3/srq/roce_srq_ctrl.c | 634 + 316 files changed, 502006 insertions(+) create mode 100644 drivers/infiniband/hw/hiroce3/Kconfig create mode 100755 drivers/infiniband/hw/hiroce3/Makefile create mode 100644 drivers/infiniband/hw/hiroce3/bond/roce_bond.h create mode 100644 drivers/infiniband/hw/hiroce3/bond/roce_bond_common.c create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq.h create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq_common.c create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq_cqe.c create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq_create.c create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq_ctrl.c create mode 100644 drivers/infiniband/hw/hiroce3/cq/roce_cq_destroy.c create mode 100644 drivers/infiniband/hw/hiroce3/dfx/roce_dfx.c create mode 100644 drivers/infiniband/hw/hiroce3/dfx/roce_dfx.h create mode 100644 drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.c create mode 100644 drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.h create mode 100644 drivers/infiniband/hw/hiroce3/dfx/roce_dfx_query.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_cdev_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_event_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_main_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_mr_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_netdev_extension.c create mode 100755 drivers/infiniband/hw/hiroce3/extension/roce_qp_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_qp_post_send_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/extension/roce_srq_extension.c create mode 100644 drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.c create mode 100644 drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.h create mode 100644 drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.c create 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create mode 100644 drivers/infiniband/hw/hiroce3/include/micro_log/hinic3_micro_log.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_cfg_comm.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_mpu_cmd.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_mpu_cmd_defs.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_npu_cmd.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_npu_cmd_defs.h create mode 100644 drivers/infiniband/hw/hiroce3/include/nic/nic_npu_wqe_defs.h create mode 100644 drivers/infiniband/hw/hiroce3/include/public/npu_cmdq_base_defs.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/rdma_context_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/rdma_ext_ctx_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_ccf_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_compile_macro.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_ctx_api.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_dif_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_err_type.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_hmm_context.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_mpu_common.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_mpu_ulp_common.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_pub.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_pub_cmd.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_ulp.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_vbs_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_attr_qpc_chip.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_cmd.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_cq_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_ext_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_gid_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_mr_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_pub.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_srq_attr.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_verbs_ulp_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_wqe_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/rdma/roce_xqe_format.h create mode 100644 drivers/infiniband/hw/hiroce3/include/readme.txt create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_cdev_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_event_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_main_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_mr_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_netdev_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_qp_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_qp_post_send_extension.h create mode 100644 drivers/infiniband/hw/hiroce3/include/roce_srq_extension.h create mode 100755 drivers/infiniband/hw/hiroce3/mr/roce_mr.c create mode 100644 drivers/infiniband/hw/hiroce3/mr/roce_mr.h create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_post.h create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp.h create mode 100755 drivers/infiniband/hw/hiroce3/qp/roce_qp_create.c create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp_destroy.c create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp_exp.h create mode 100755 drivers/infiniband/hw/hiroce3/qp/roce_qp_modify.c create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp_post_recv.c create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp_post_send.c create mode 100644 drivers/infiniband/hw/hiroce3/qp/roce_qp_query.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_bitmap.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_bitmap.h create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp.h create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp_gid.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp_init.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp_mw_mr.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp_pd.c create mode 100644 drivers/infiniband/hw/hiroce3/rdma/rdma_comp_res.c create mode 100755 drivers/infiniband/hw/hiroce3/roce.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_cdev.c create mode 100755 drivers/infiniband/hw/hiroce3/roce_cmd.c create mode 100755 drivers/infiniband/hw/hiroce3/roce_cmd.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_compat.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_cqm_cmd.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_cqm_cmd.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_db.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_db.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_event.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_event.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_k_ioctl.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_main.c create mode 100755 drivers/infiniband/hw/hiroce3/roce_mix.c create mode 100755 drivers/infiniband/hw/hiroce3/roce_mix.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_netdev.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_netdev.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_netlink.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_netlink.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_pd.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_pd.h create mode 100755 drivers/infiniband/hw/hiroce3/roce_sysfs.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_sysfs.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_user.h create mode 100644 drivers/infiniband/hw/hiroce3/roce_xrc.c create mode 100644 drivers/infiniband/hw/hiroce3/roce_xrc.h create mode 100644 drivers/infiniband/hw/hiroce3/srq/roce_srq.h create mode 100644 drivers/infiniband/hw/hiroce3/srq/roce_srq_comm.c create mode 100644 drivers/infiniband/hw/hiroce3/srq/roce_srq_create.c create mode 100644 drivers/infiniband/hw/hiroce3/srq/roce_srq_ctrl.c diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 95bc227d2..2089bb228 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -6167,6 +6167,7 @@ CONFIG_MLX5_INFINIBAND=m # CONFIG_INFINIBAND_MTHCA is not set # CONFIG_INFINIBAND_OCRDMA is not set CONFIG_INFINIBAND_QEDR=m +CONFIG_HIROCE3=m CONFIG_RDMA_RXE=m # CONFIG_RDMA_SIW is not set CONFIG_INFINIBAND_IPOIB=m diff --git a/arch/x86/configs/openeuler_defconfig b/arch/x86/configs/openeuler_defconfig index 8f336547c..087a9f4f1 100644 --- a/arch/x86/configs/openeuler_defconfig +++ b/arch/x86/configs/openeuler_defconfig @@ -6849,6 +6849,7 @@ CONFIG_INFINIBAND_QEDR=m CONFIG_INFINIBAND_USNIC=m CONFIG_INFINIBAND_VMWARE_PVRDMA=m CONFIG_INFINIBAND_RDMAVT=m +CONFIG_HIROCE3=m CONFIG_RDMA_RXE=m # CONFIG_RDMA_SIW is not set CONFIG_INFINIBAND_IPOIB=m diff --git a/drivers/infiniband/Kconfig b/drivers/infiniband/Kconfig index a5827d11e..e8270b8d6 100644 --- a/drivers/infiniband/Kconfig +++ b/drivers/infiniband/Kconfig @@ -95,6 +95,7 @@ source "drivers/infiniband/hw/qedr/Kconfig" source "drivers/infiniband/hw/qib/Kconfig" source "drivers/infiniband/hw/usnic/Kconfig" source "drivers/infiniband/hw/vmw_pvrdma/Kconfig" +source "drivers/infiniband/hw/hiroce3/Kconfig" source "drivers/infiniband/sw/rdmavt/Kconfig" endif # !UML source "drivers/infiniband/sw/rxe/Kconfig" diff --git a/drivers/infiniband/hw/Makefile b/drivers/infiniband/hw/Makefile index 1211f4317..46faec393 100644 --- a/drivers/infiniband/hw/Makefile +++ b/drivers/infiniband/hw/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_INFINIBAND_HNS) += hns/ obj-$(CONFIG_INFINIBAND_QEDR) += qedr/ obj-$(CONFIG_INFINIBAND_BNXT_RE) += bnxt_re/ obj-$(CONFIG_INFINIBAND_ERDMA) += erdma/ +obj-$(CONFIG_HIROCE3) += hiroce3/ diff --git a/drivers/infiniband/hw/hiroce3/Kconfig b/drivers/infiniband/hw/hiroce3/Kconfig new file mode 100644 index 000000000..6657310b7 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Huawei driver configuration +# + +config HIROCE3 + tristate "Huawei Intelligent Network Interface Card Driver for RDMA" + depends on HINIC3 && PCI_MSI && NUMA && PCI_IOV && DCB && (X86 || ARM64) + help + This driver supports HiROCE PCIE Ethernet cards. + To compile this driver as part of the kernel, choose Y here. + If unsure, choose N. + The default is N. + diff --git a/drivers/infiniband/hw/hiroce3/Makefile b/drivers/infiniband/hw/hiroce3/Makefile new file mode 100755 index 000000000..96525f9ae --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/Makefile @@ -0,0 +1,157 @@ +EXPORT_SYMBOL := true + +GLOBAL_VERSION="16.13.8.1" +OFED_VERSION := OFED_MLNX_5_8 + +KBUILD_EXTRA_SYMBOLS += $(srctree)/drivers/net/ethernet/huawei/hinic3/Module.symvers + +EXTRA_CFLAGS += -DHW_CONVERT_ENDIAN +EXTRA_CFLAGS += -DROCE_SERVICE +EXTRA_CFLAGS += -D__ROCE_DFX__ +EXTRA_CFLAGS += -DROCE_CC_EN +EXTRA_CFLAGS += -Werror -Wall + +EXTRA_CFLAGS += -Werror -Wno-implicit-fallthrough + +EXTRA_CFLAGS += -fstack-protector-all + +ORIGN_LINUXINCLUDE := $(LINUXINCLUDE) + +THIRDPARTY_INC = /usr/src/ofa_kernel/default/ +EXTRA_CFLAGS += -D$(OFED_VERSION) +LINUXINCLUDE := -I$(THIRDPARTY_INC)/include/ -I$(THIRDPARTY_INC)/include/uapi $(ORIGN_LINUXINCLUDE) + +EXTRA_CFLAGS += -DROCE_COMPUTE +EXTRA_CFLAGS += -DROCE_BONDING_EN +EXTRA_CFLAGS += -DROCE_STANDARD +EXTRA_CFLAGS += -DOFED_MLNX_5_8 + +# Set CFLAGS from default file directories +EXTRA_CFLAGS += -I$(srctree)/include/linux +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3 +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/host/include +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/host/hmm +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/bond +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/cq +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/dfx +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/extension +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/include +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/include/nic +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/include/rdma +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/include/hw +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/include/mag +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/mr +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/qp +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/rdma +EXTRA_CFLAGS += -I$(srctree)/drivers/infiniband/hw/hiroce3/srq +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3 +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/hw +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/bond +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/cfg_mgmt +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/mpu +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/bond +EXTRA_CFLAGS += -I$(srctree)/drivers/net/ethernet/huawei/hinic3/include/cqm + +export KLIB_BUILD +export KERN_VERSION +export MAKE +export KBUILD_EXTRA_SYMBOLS + +$(info ============== INFO ==============) +$(info Building kernel modules) +$(info Driver Version: $(VERSION)) +$(info Kernel Version: $(KERN_VERSION)) +$(info os type: $(HI1823_OS_TYPE)) +$(info Kernel Sources: $(KSRC)) +$(info Thirdparty Source: $(THIRDPARTY_INC)) +$(info linux include: $(LINUXINCLUDE)) +$(info Thirdparty Symbols: $(KBUILD_EXTRA_SYMBOLS)) +$(info build_dir: $(HI1823_BUILD_DIR)) +$(info ==================================) +$(info linux version $(LINUX_VERSION_CODE)) +$(info $(EXTRA_CFLAGS)) +$(info ==================================) + +obj-$(CONFIG_HIROCE3) += hiroce3.o + +hiroce3-y := cq/roce_cq_common.o \ + cq/roce_cq_cqe.o \ + cq/roce_cq_create.o \ + cq/roce_cq_ctrl.o \ + cq/roce_cq_destroy.o \ + extension/roce_event_extension.o \ + extension/roce_main_extension.o \ + extension/roce_mr_extension.o \ + extension/roce_netdev_extension.o \ + extension/roce_qp_extension.o \ + extension/roce_qp_post_send_extension.o \ + extension/roce_srq_extension.o \ + extension/roce_cdev_extension.o \ + roce_db.o \ + roce_main.o \ + roce_netlink.o \ + roce_event.o \ + roce_netdev.o \ + roce_mix.o \ + mr/roce_mr.o \ + roce_pd.o \ + qp/roce_qp_create.o \ + qp/roce_qp_destroy.o \ + qp/roce_qp_modify.o \ + qp/roce_qp_post_recv.o \ + qp/roce_qp_post_send.o \ + qp/roce_qp_query.o \ + roce_xrc.o \ + dfx/roce_dfx.o \ + dfx/roce_dfx_query.o \ + roce_cdev.o \ + roce_sysfs.o \ + roce_cmd.o \ + roce_cqm_cmd.o \ + bond/roce_bond_common.o \ + rdma/rdma_bitmap.o \ + rdma/rdma_comp.o \ + rdma/rdma_comp_res.o \ + rdma/rdma_comp_gid.o \ + rdma/rdma_comp_init.o \ + rdma/rdma_comp_pd.o \ + rdma/rdma_comp_mw_mr.o \ + srq/roce_srq_comm.o \ + srq/roce_srq_create.o \ + srq/roce_srq_ctrl.o \ + host/hmm/hmm_buddy.o \ + host/hmm/hmm_comp.o \ + host/hmm/hmm_comp_init.o \ + host/hmm/hmm_comp_mtt.o \ + host/hmm/hmm_comp_mw_mr.o \ + host/hmm/hmm_comp_res.o \ + host/hmm/hmm_em.o \ + host/hmm/hmm_mr.o \ + host/hmm/hmm_umem.o + +hiroce3-y +=dfx/roce_dfx_cap.o + + +SYS_TIME=$(shell date +%Y-%m-%d_%H:%M:%S) +ccflags-y += -D __TIME_STR__=\"$(SYS_TIME)\" +ccflags-y += -DGLOBAL_VERSION_STR=\"$(GLOBAL_VERSION)\" + +$(warning cflags, $(ccflags-y)) +V ?= 0 + +ccflags-y += -DHW_CONVERT_ENDIAN + +ccflags-y += -D__LINUX__ + +EXTRA_CFLAGS += -DSECUREC_EXPORT_KERNEL_SYMBOL=0 + +KERNEL_VER := $(shell uname -r 2>null) + +KERNEL_DIR := /lib/modules/$(KERNEL_VER)/build + +default: + $(MAKE) -C $(KERNEL_DIR) M=$(shell pwd) -W modules + +clean: + rm -rf *.o *.ko *.order .*.cmd *.mod.* .H* .tm* .tmp_versions Module.symvers *.ko.unsigned null diff --git a/drivers/infiniband/hw/hiroce3/bond/roce_bond.h b/drivers/infiniband/hw/hiroce3/bond/roce_bond.h new file mode 100644 index 000000000..96e9f9f91 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/bond/roce_bond.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_bond_register.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/3/24 + * Description : The definition of RoCE bond common macros, function prototypes. + */ + +#ifndef ROCE_BOND_H +#define ROCE_BOND_H + +#include <net/bonding.h> +#include <linux/netdevice.h> + +#include "hinic3_bond.h" + +#include "roce.h" +#include "roce_qp.h" +#include "roce_cmd.h" +#include "roce_verbs_attr.h" + +#define ROCE_BOND_MAX_GROUPS 2 +#define ROCE_BOND_2_100G_MAX_GROUPS 1 +#define ROCE_BOND_4_25G_MAX_GROUPS 2 + +/* Adding two roce at a time consumes one bit of the array. + * Currently, a maximum of 33 nodes are supported, and at least 17. + * To support roce hot swap, the code logic needs to be reconstructed. + */ +#define ROCE_BOND_HCA_NUM 17 + +#define ROCE_BOND_MAX_PORTS 4 +#define ROCE_BOND_MAX_FUNCS 4 + +#define ROCE_BOND_NO_VLAN_ID 0 +#define ROCE_BOND_RSVD_VLAN_ID 4095 + +#define ROCE_BOND_PORT_ENABLE 1 +#define ROCE_BOND_PORT_DISABLE 0 + +#define ROCE_BOND_ADD_MAC_TBL 1 +#define ROCE_BOND_DEL_MAC_TBL 0 + +#define ROCE_BOND_FWD_ID_TBL_ALL_BITS 32 +#define ROCE_BOND_FWD_ID_TBL_PER_BITS 3 +#define ROCE_BOND_FWD_ID_TBL_PER_BITS_MASK 0x7 + +#define ROCE_BOND_MAX_ACX_QP_NUM 32 +#define ROCE_BOND_ACX_QP_ENABLE 1 +#define ROCE_BOND_ACX_QP_DISABLE 0 + +#define ROCE_BOND_WAIT_ACTIVE_500MS 500 +enum { + ROCE_BOND_FUNC_OWN_FLAG = (1 << 0) +}; + +enum { + ROCE_BOND_FLAG = (1 << 0) +}; + +enum { + ROCE_BOND_WANT_TWO_SLAVES = 2, /* 2 slaves per bond_dev */ + ROCE_BOND_WANT_THREE_SLAVES = 3, /* 3 slaves per bond_dev */ + ROCE_BOND_WANT_FOUR_SLAVES = 4 /* 4 slaves per bond_dev */ +}; + +enum { + ROCE_BOND_WANT_TWO_SLAVES_MASK = 0x3, + ROCE_BOND_WANT_THREE_SLAVES_MASK = 0x7, + ROCE_BOND_WANT_FOUR_SLAVES_MASK = 0xf +}; + +enum { + ROCE_BOND_2_PORT_NUM = 2, + ROCE_BOND_4_PORT_NUM = 4 +}; + +enum { + ROCE_BOND_25G_PORT_SPEED = 25, + ROCE_BOND_100G_PORT_SPEED = 100 +}; + +enum { + ROCE_BOND_2_FUNC_NUM = 2, + ROCE_BOND_4_FUNC_NUM = 4 +}; + +enum { + ROCE_BOND_INVALID_HCA = -1, + ROCE_BOND_2_100G_HCA = 0, + ROCE_BOND_4_25G_HCA = 1, + ROCE_BOND_2_25G_HCA = 2 +}; + +#define SDI_BOND_SUPPORT_ROCE_FUNC_BIT 1 +#define SDI_BOND_SUPPORT_ROCE_FUNC_CNT 1 +#define SDI_BOND_SLAVES_FUNC_NUM 2 + +struct roce3_bond_slave { + struct net_device *netdev; + struct hinic3_lld_dev *lld_dev; + struct hinic3_lld_dev *ppf_dev; + struct netdev_lag_lower_state_info netdev_state; + u32 update_cnt; + u16 func_id; + u8 er_id; + bool is_ppf; +}; + +typedef void (*roce3_bond_service_func)(const char *bond_name, struct bond_attr *attr); + +struct roce3_bond_device { + char name[IFNAMSIZ]; + struct list_head entry; + struct roce3_bond_slave slaves[ROCE_BOND_MAX_FUNCS]; + struct mutex slave_lock; + u32 slave_cnt; + atomic_t next_port; + struct work_struct detach_work; + struct roce3_device *attached_rdev; + struct bond_attr attr; +}; + +bool roce3_bond_is_active(struct roce3_device *rdev); +struct net_device *roce3_bond_get_netdev(struct roce3_device *rdev); + +int roce3_add_bond_real_slave_mac(struct roce3_device *rdev, u8 *mac); +int roce3_add_bond_vlan_slave_mac(struct roce3_device *rdev, u8 *mac, u16 vlan_id); +void roce3_del_bond_real_slave_mac(struct roce3_device *rdev); +void roce3_del_bond_vlan_slave_mac(struct roce3_device *rdev, u8 *mac, u16 vlan_id); + +int roce3_bond_is_eth_port_of_netdev(struct roce3_device *rdev, struct net_device *event_ndev); + +void roce3_bond_rr_set_flow(struct roce3_device *rdev, struct roce3_qp *rqp, roce_verbs_qp_attr_s *qp_attr); + +int roce3_bond_event_cfg_rdev(struct hinic3_lld_dev *lld_dev, void *uld_dev, struct roce3_device **rdev); +int roce3_bonded_port_event_report(struct roce3_device *rdev, const struct hinic3_event_info *event); +void roce3_handle_bonded_port_state_event(struct roce3_device *rdev); + +bool roce3_get_bond_ipsurx_en(void); +void roce3_set_bond_ipsurx_en(bool ipsurx_en); + +int roce3_bond_attach(struct roce3_device *rdev); +int roce3_bond_init(void); +void roce3_bond_pre_exit(void); +void roce3_bond_exit(void); +#endif + diff --git a/drivers/infiniband/hw/hiroce3/bond/roce_bond_common.c b/drivers/infiniband/hw/hiroce3/bond/roce_bond_common.c new file mode 100644 index 000000000..8fc1eddac --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/bond/roce_bond_common.c @@ -0,0 +1,950 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_bond_register.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/3/24 + * Description : The definition of RoCE bond common functions. + */ + +#ifdef ROCE_BONDING_EN + +#include <rdma/ib_user_verbs.h> +#include <rdma/ib_addr.h> +#include <rdma/ib_cache.h> + +#include <net/bonding.h> + +#include "bond_common_defs.h" + +#include "hinic3_hw.h" +#include "hinic3_srv_nic.h" + +#include "roce_bond.h" +#include "roce_cmd.h" +#include "roce_netdev.h" + +static bool g_roce3_bond_ipsurx_en = true; + +static LIST_HEAD(g_roce3_bond_list); +static DEFINE_MUTEX(g_roce3_bond_mutex); + +static struct workqueue_struct *g_bond_wq; + +struct roce3_detach_work { + u16 bond_id; + struct work_struct work; +}; + +struct roce3_bond_work { + char name[IFNAMSIZ]; + struct work_struct work; +}; + +bool roce3_get_bond_ipsurx_en(void) +{ + return g_roce3_bond_ipsurx_en; +} + +void roce3_set_bond_ipsurx_en(bool ipsurx_en) +{ + g_roce3_bond_ipsurx_en = ipsurx_en; +} + +static enum netdev_lag_tx_type roce3_get_tx_type_by_bond_mode(u16 bond_mode) +{ + switch (bond_mode) { + case BOND_MODE_8023AD: + case BOND_MODE_XOR: + return NETDEV_LAG_TX_TYPE_HASH; + case BOND_MODE_ACTIVEBACKUP: + return NETDEV_LAG_TX_TYPE_ACTIVEBACKUP; + default: + return NETDEV_LAG_TX_TYPE_UNKNOWN; + } +} + +static bool roce3_bond_mode_is_supported(u16 bond_mode) +{ + enum netdev_lag_tx_type tx_type = roce3_get_tx_type_by_bond_mode(bond_mode); + if ((tx_type != NETDEV_LAG_TX_TYPE_ACTIVEBACKUP) && (tx_type != NETDEV_LAG_TX_TYPE_HASH)) { + pr_err("[ROCE, ERR] %s: Failed to support bond mode(%d)\n", __func__, tx_type); + return false; + } + return true; +} + +static bool is_hinic3_netdev(struct net_device *netdev) +{ + return (hinic3_get_lld_dev_by_netdev(netdev) != NULL); +} + +static bool roce3_can_do_bond(struct bonding *bond) +{ + bool ret = false; + int slave_cnt = 0; + struct slave *slave = NULL; + struct list_head *iter = NULL; + struct hinic3_lld_dev *lld_dev = NULL; + struct hinic3_lld_dev *ppf_dev = NULL; + + if (!bond || !roce3_bond_mode_is_supported(bond->params.mode)) { + return ret; + } + + rcu_read_lock(); + bond_for_each_slave_rcu(bond, slave, iter) + { + lld_dev = hinic3_get_lld_dev_by_netdev(slave->dev); + if (!lld_dev) { + goto out; + } + + if (!hinic3_support_roce(lld_dev->hwdev, NULL)) { + goto out; + } + + if (!ppf_dev) { + ppf_dev = hinic3_get_ppf_lld_dev(lld_dev); + if (!ppf_dev) { + goto out; + } + } + + if (hinic3_get_ppf_lld_dev(lld_dev) != ppf_dev) { + goto out; + } + + slave_cnt++; + pr_info("%s:can do bond? slave_cnt(%d), slave_name(%s)", __func__, slave_cnt, slave->dev->name); + } + + ret = (slave_cnt == ROCE_BOND_2_FUNC_NUM); +out: + rcu_read_unlock(); + return ret; +} + +struct net_device *roce3_bond_get_netdev(struct roce3_device *rdev) +{ + int i; + struct roce3_bond_device *bond_dev = rdev->bond_dev; + struct net_device *ret_dev = NULL; + struct slave *slave = NULL; + + mutex_lock(&g_roce3_bond_mutex); + if (!bond_dev) { + mutex_unlock(&g_roce3_bond_mutex); + return ret_dev; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + rcu_read_lock(); + slave = bond_slave_get_rcu(bond_dev->slaves[i].netdev); + rcu_read_unlock(); + if (!slave) { + continue; + } + if (bond_is_active_slave(slave)) { + if (netif_running(bond_dev->slaves[i].netdev) && netif_carrier_ok(bond_dev->slaves[i].netdev)) { + ret_dev = bond_dev->slaves[i].netdev; + } else if (netif_running(bond_dev->slaves[(i + 1) % bond_dev->slave_cnt].netdev) && + netif_carrier_ok(bond_dev->slaves[(i + 1) % bond_dev->slave_cnt].netdev)) { + ret_dev = bond_dev->slaves[(i + 1) % bond_dev->slave_cnt].netdev; + } else { + ret_dev = bond_dev->slaves[i].netdev; + } + dev_hold(ret_dev); + mutex_unlock(&bond_dev->slave_lock); + mutex_unlock(&g_roce3_bond_mutex); + return ret_dev; + } + } + mutex_unlock(&bond_dev->slave_lock); + mutex_unlock(&g_roce3_bond_mutex); + return ret_dev; +} + +void roce3_bond_rr_set_flow(struct roce3_device *rdev, struct roce3_qp *rqp, roce_verbs_qp_attr_s *qp_attr) +{ + u32 bond_tx_hash; + struct roce3_bond_device *bond_dev = rdev->bond_dev; + + if (!bond_dev) { + return; + } + + bond_tx_hash = (u32)atomic_add_return(1, &bond_dev->next_port); + rqp->tx_hash_value = bond_tx_hash; + + qp_attr->path_info.dw0.bs.bond_tx_hash_value = (u16)bond_tx_hash; +} + +static int roce3_bond_modify_mac_tbl_for_sdi(struct roce3_device *rdev, u8 *mac, roce3_modify_mac_tbl modify_mac_tbl) +{ + u16 func_id; + int ret; + + for (func_id = 0; func_id < SDI_BOND_SLAVES_FUNC_NUM; func_id++) { + if (func_id == rdev->glb_func_id) { + continue; + } + + ret = modify_mac_tbl(rdev->hwdev, mac, ROCE_BOND_RSVD_VLAN_ID, rdev->glb_func_id, func_id); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to modify mac table, ret(%d)\n", __func__, ret); + return ret; + } + } + + return 0; +} + +int roce3_add_bond_real_slave_mac(struct roce3_device *rdev, u8 *mac) +{ + struct roce3_bond_device *bond_dev = rdev->bond_dev; + struct roce3_bond_slave *slave = NULL; + int ret; + int i; + + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: Failed to find bond_dev\n", __func__); + return -EINVAL; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + slave = &bond_dev->slaves[i]; + ret = roce3_add_mac_tbl_mac_entry(rdev->hwdev, mac, ROCE_BOND_RSVD_VLAN_ID, rdev->glb_func_id, slave->func_id); + if (ret != 0) { + mutex_unlock(&bond_dev->slave_lock); + pr_err("[ROCE, ERR] %s: Failed to add mac_vlan entry, ret(%d)\n", __func__, ret); + return ret; + } + + if (slave->func_id != rdev->glb_func_id) { + /* The IPSU MAC table is used for fast forwarding. Even if the addition fails, the forwarding information + can still be obtained by checking the MAC table later, without judging the execution result. */ + (void)roce3_add_ipsu_tbl_mac_entry(rdev->hwdev, mac, 0, rdev->glb_func_id, slave->er_id); + } + } + mutex_unlock(&bond_dev->slave_lock); + + if (rdev->sdi_bond_name != NULL) { + ret = roce3_bond_modify_mac_tbl_for_sdi(rdev, mac, roce3_add_mac_tbl_mac_entry); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to modify mac table of sdi, ret(%d)\n", __func__, ret); + return ret; + } + } + + return 0; +} + +int roce3_add_bond_vlan_slave_mac(struct roce3_device *rdev, u8 *mac, u16 vlan_id) +{ + struct roce3_bond_device *bond_dev = rdev->bond_dev; + struct roce3_bond_slave *slave = NULL; + int ret; + int i; + + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: Failed to find bond_dev\n", __func__); + return -EINVAL; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + slave = &bond_dev->slaves[i]; + if (slave->func_id == rdev->glb_func_id) { + continue; + } + + ret = roce3_add_mac_tbl_mac_entry(rdev->hwdev, mac, vlan_id, slave->func_id, slave->func_id); + if (ret != 0) { + mutex_unlock(&bond_dev->slave_lock); + pr_err("[ROCE, ERR] %s: Failed to add mac_vlan entry, ret(%d)\n", __func__, ret); + return ret; + } + + /* The IPSU MAC table is used for fast forwarding. Even if the addition fails, the forwarding information + can still be obtained by checking the MAC table later, without judging the execution result. */ + (void)roce3_add_ipsu_tbl_mac_entry(rdev->hwdev, mac, vlan_id, rdev->glb_func_id, slave->er_id); + } + mutex_unlock(&bond_dev->slave_lock); + + return 0; +} + +void roce3_del_bond_real_slave_mac(struct roce3_device *rdev) +{ + int i; + struct roce3_bond_slave *slave = NULL; + struct roce3_bond_device *bond_dev = rdev->bond_dev; + + if (!bond_dev) { + return; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + slave = &bond_dev->slaves[i]; + if (slave->func_id != rdev->glb_func_id) { + (void)roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, rdev->mac, 0, rdev->glb_func_id, slave->er_id); + } + + (void)roce3_del_mac_tbl_mac_entry(rdev->hwdev, rdev->mac, ROCE_BOND_RSVD_VLAN_ID, rdev->glb_func_id, + slave->func_id); + } + mutex_unlock(&bond_dev->slave_lock); + + if (rdev->sdi_bond_name != NULL) { + (void)roce3_bond_modify_mac_tbl_for_sdi(rdev, rdev->mac, roce3_del_mac_tbl_mac_entry); + } +} + +void roce3_del_bond_vlan_slave_mac(struct roce3_device *rdev, u8 *mac, u16 vlan_id) +{ + int i; + struct roce3_bond_slave *slave = NULL; + struct roce3_bond_device *bond_dev = rdev->bond_dev; + + if (!bond_dev) { + return; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + slave = &bond_dev->slaves[i]; + if (slave->func_id == rdev->glb_func_id) { + continue; + } + + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, mac, vlan_id, slave->func_id, slave->er_id); + + (void)roce3_del_mac_tbl_mac_entry(rdev->hwdev, mac, vlan_id, rdev->glb_func_id, slave->er_id); + } + mutex_unlock(&bond_dev->slave_lock); +} + +bool roce3_bond_is_active(struct roce3_device *rdev) +{ + return (rdev->bond_dev != NULL); +} + +int roce3_bond_event_cfg_rdev(struct hinic3_lld_dev *lld_dev, void *uld_dev, struct roce3_device **rdev) +{ + int i; + struct roce3_bond_device *bond_dev = NULL; + + if (lld_dev == NULL) { + pr_err("[ROCE, ERR] %s: Lld_dev is null\n", __func__); + return -EINVAL; + } + + if (uld_dev != NULL) { + *rdev = (struct roce3_device *)uld_dev; + return 0; + } + + mutex_lock(&g_roce3_bond_mutex); + list_for_each_entry(bond_dev, &g_roce3_bond_list, entry) + { + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + if (bond_dev->slaves[i].lld_dev == lld_dev) { + *rdev = bond_dev->attached_rdev; + mutex_unlock(&bond_dev->slave_lock); + goto out; + } + } + mutex_unlock(&bond_dev->slave_lock); + } + +out: + mutex_unlock(&g_roce3_bond_mutex); + return *rdev ? 0 : -EINVAL; +} + +int roce3_bonded_port_event_report(struct roce3_device *rdev, const struct hinic3_event_info *event) +{ + u32 type = HINIC3_SRV_EVENT_TYPE(event->service, event->type); + if ((type != HINIC3_SRV_EVENT_TYPE(EVENT_SRV_NIC, EVENT_NIC_LINK_UP)) && + (type != HINIC3_SRV_EVENT_TYPE(EVENT_SRV_NIC, EVENT_NIC_LINK_DOWN))) { + pr_err("[ROCE] %s: event_service(%d), type(%d)\n", __func__, event->service, event->type); + return -ERANGE; + } + + return 0; +} + +int roce3_bond_is_eth_port_of_netdev(struct roce3_device *rdev, struct net_device *event_ndev) +{ + struct roce3_bond_device *bond_dev = rdev->bond_dev; + struct net_device *tmp_ndev = NULL; + int ret; + int i; + /* judge current net device */ + tmp_ndev = rdev->ndev; + ret = roce3_is_eth_port_of_netdev(tmp_ndev, event_ndev); + if (ret != 0) { + return 1; + } + + if (!bond_dev) { + return 0; + } + + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + if (roce3_is_eth_port_of_netdev(bond_dev->slaves[i].netdev, event_ndev)) { + mutex_unlock(&bond_dev->slave_lock); + return 1; + } + } + mutex_unlock(&bond_dev->slave_lock); + + return 0; +} + +struct roce3_bond_device *roce3_get_bond_dev(const char *bond_name) +{ + struct roce3_bond_device *bdev = NULL; + + list_for_each_entry(bdev, &g_roce3_bond_list, entry) + { + if (!strcmp(bdev->name, bond_name)) { + return bdev; + } + } + + return NULL; +} + +struct roce3_bond_device *roce3_get_bond_dev_by_name(const char *bond_name) +{ + struct roce3_bond_device *bdev = NULL; + + mutex_lock(&g_roce3_bond_mutex); + bdev = roce3_get_bond_dev(bond_name); + mutex_unlock(&g_roce3_bond_mutex); + return bdev; +} + +void roce3_bond_init_slave(struct roce3_bond_slave *slave, struct bond_tracker *tracker, int index, + struct bond_attr *attr) +{ + void *hwdev; + + slave->func_id = index; + slave->netdev = tracker->ndev[index]; + + dev_hold(slave->netdev); + pr_info("[ROCE, INFO] %s: dev_hold: name(%s),tracker_cnt(%d)\n", + __func__, slave->netdev->name, tracker->cnt); + slave->lld_dev = hinic3_get_lld_dev_by_netdev(slave->netdev); + slave->ppf_dev = hinic3_get_ppf_lld_dev(slave->lld_dev); + hwdev = slave->lld_dev->hwdev; + slave->is_ppf = hinic3_func_type(hwdev) == TYPE_PPF; + slave->er_id = hinic3_er_id(hwdev); + slave->netdev_state.link_up = tracker->netdev_state[index].link_up; + slave->netdev_state.tx_enabled = tracker->netdev_state[index].tx_enabled; + + if (slave->is_ppf) { + attr->first_roce_func = slave->func_id; + } else { + hinic3_detach_service(slave->lld_dev, SERVICE_T_ROCE); + } + return; +} + +bool roce3_bond_before_active_check(struct bond_tracker *tracker, struct bond_attr *attr) +{ + int i; + struct hinic3_lld_dev *lld_dev = NULL; + struct hinic3_lld_dev *ppf_dev = NULL; + + if (!roce3_bond_mode_is_supported(attr->bond_mode)) { + return false; + } + + for (i = 0; i < ROCE_BOND_2_FUNC_NUM; i++) { + lld_dev = hinic3_get_lld_dev_by_netdev(tracker->ndev[i]); + if (!lld_dev) { + pr_err("[ROCE, ERR] %s: get lld dev err\n", __func__); + return false; + } + + if (!hinic3_support_roce(lld_dev->hwdev, NULL)) { + pr_err("[ROCE, ERR] %s: Not support roce\n", __func__); + return false; + } + + if (!ppf_dev) { + ppf_dev = hinic3_get_ppf_lld_dev(lld_dev); + if (!ppf_dev) { + pr_err("[ROCE, ERR] %s: get ppf dev err\n", __func__); + return false; + } + } + + if (hinic3_get_ppf_lld_dev(lld_dev) != ppf_dev) { + return false; + } + } + + return true; +} + +void roce3_detach_nic_bond_work(struct work_struct *work) +{ + struct roce3_detach_work *detach_work = container_of(work, struct roce3_detach_work, work); + + hinic3_bond_detach(detach_work->bond_id, HINIC3_BOND_USER_ROCE); + + kfree(detach_work); +} + +static void roce3_attach_bond_work(struct work_struct *_work) +{ + u16 bond_id; + struct roce3_bond_work *work = container_of(_work, struct roce3_bond_work, work); + pr_info("roce_attach: %s: work_name(%s)\n", __func__, work->name); + hinic3_bond_attach(work->name, HINIC3_BOND_USER_ROCE, &bond_id); + + kfree(work); + return; +} +void roce3_deatch_bond(u16 bond_id) +{ + struct roce3_detach_work *detach_work = NULL; + + detach_work = kmalloc(sizeof *detach_work, GFP_KERNEL); + if (!detach_work) { + pr_err("[ROCE, ERR] %s: malloc failed, bond id(%d)\n", __func__, bond_id); + return; + } + + detach_work->bond_id = bond_id; + INIT_WORK(&detach_work->work, roce3_detach_nic_bond_work); + queue_work(g_bond_wq, &detach_work->work); +} + +bool roce3_bond_tracker_get(const char *bond_name, struct bond_tracker *tracker) +{ + int ret = 0; + + ret = hinic3_get_bond_tracker_by_name(bond_name, tracker); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: get bond tracker failed name(%s), ret(%d)\n", __func__, bond_name, ret); + return false; + } + if (!tracker->is_bonded) { + pr_err("[ROCE, ERR] %s: tracker is NOT bond (%s)\n", __func__, bond_name); + return false; + } + if (tracker->cnt == ROCE_BOND_2_FUNC_NUM) { + return true; + } + + pr_err("[ROCE, ERR] %s: get tracker cnt fail, cnt(%d) name(%s)\n", __func__, tracker->cnt, bond_name); + return false; +} + +void roce3_before_bond_active(const char *bond_name, struct bond_attr *attr) +{ + struct roce3_bond_device *bond_dev = NULL; + struct roce3_bond_slave *slave = NULL; + struct bond_tracker tracker; + int i; + + if (!roce3_bond_tracker_get(bond_name, &tracker)) { + pr_err("[ROCE, ERR] %s: get bond tracker failed\n", __func__); + goto err; + } + + if (!roce3_bond_before_active_check(&tracker, attr)) { + pr_err("[ROCE, ERR] %s: active check failed\n", __func__); + goto err; + } + + bond_dev = roce3_get_bond_dev_by_name(bond_name); + if (bond_dev) { + pr_info("[ROCE, INFO] %s: Find exist bond device\n", __func__); + return; + } + + bond_dev = kzalloc(sizeof *bond_dev, GFP_KERNEL); + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: Malloc memory failed\n", __func__); + goto err; + } + + (void)strncpy(bond_dev->name, bond_name, strlen(bond_name)); + + bond_dev->attr = *attr; + bond_dev->slave_cnt = tracker.cnt; + mutex_init(&bond_dev->slave_lock); + + for (i = 0; i < ROCE_BOND_2_FUNC_NUM; i++) { + slave = &bond_dev->slaves[i]; + roce3_bond_init_slave(slave, &tracker, i, attr); + } + + hinic3_detach_service(bond_dev->slaves[0].ppf_dev, SERVICE_T_ROCE); + mutex_lock(&g_roce3_bond_mutex); + list_add_tail(&bond_dev->entry, &g_roce3_bond_list); + mutex_unlock(&g_roce3_bond_mutex); + return; +err: + roce3_deatch_bond(attr->bond_id); + return; +} + +void roce3_after_bond_active(const char *bond_name, struct bond_attr *attr) +{ + int ret; + struct roce3_bond_device *bond_dev = NULL; + + bond_dev = roce3_get_bond_dev_by_name(bond_name); + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: not find bond device by name(%s)\n", __func__, bond_name); + return; + } + + ret = hinic3_attach_service(bond_dev->slaves[0].ppf_dev, SERVICE_T_ROCE); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to attach roce device, ret(%d), bond name(%s)\n", __func__, ret, bond_name); + } + + return; +} + +void roce3_after_bond_modify(const char *bond_name, struct bond_attr *attr) +{ + struct roce3_bond_device *bond_dev = NULL; + struct bond_tracker tracker; + int i; + int j; + bond_dev = roce3_get_bond_dev_by_name(bond_name); + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: not find bond device by name(%s)\n", __func__, bond_name); + return; + } + + if (hinic3_get_bond_tracker_by_name(bond_name, &tracker) != 0) { + pr_err("[ROCE, ERR] %s: get bond tracker failed\n", __func__); + return; + } + + bond_dev->attr = *attr; + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < BOND_PORT_MAX_NUM; i++) { + for (j = 0; j < bond_dev->slave_cnt; j++) { + if (bond_dev->slaves[j].netdev != tracker.ndev[i]) { + continue; + } + bond_dev->slaves[j].netdev_state.link_up = tracker.netdev_state[i].link_up; + bond_dev->slaves[j].netdev_state.tx_enabled = tracker.netdev_state[i].tx_enabled; + break; + } + } + mutex_unlock(&bond_dev->slave_lock); + + return; +} + +void roce3_before_bond_deactive(const char *bond_name, struct bond_attr *attr) +{ + return; +} + +void roce3_after_bond_deactive(const char *bond_name, struct bond_attr *attr) +{ + return; +} + +void roce3_bond_destroy(const char *bond_name) +{ + int ret; + int i; + struct roce3_bond_device *bond_dev = NULL; + + mutex_lock(&g_roce3_bond_mutex); + bond_dev = roce3_get_bond_dev(bond_name); + if (bond_dev) { + list_del(&bond_dev->entry); + } + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: not find bond device by name(%s)\n", __func__, bond_name); + mutex_unlock(&g_roce3_bond_mutex); + return; + } + if (bond_dev->attached_rdev != NULL) { + bond_dev->attached_rdev->bond_dev = NULL; + } + mutex_unlock(&g_roce3_bond_mutex); + + hinic3_detach_service(bond_dev->slaves[0].ppf_dev, SERVICE_T_ROCE); + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + ret = hinic3_attach_service(bond_dev->slaves[i].lld_dev, SERVICE_T_ROCE); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to attach roce device, ret(%d)\n", __func__, ret); + } + dev_put(bond_dev->slaves[i].netdev); + pr_info("[ROCE, INFO] %s: dev_put: name(%s),slave_cnt(%d), slave_name(%s)\n", + __func__, bond_name, bond_dev->slave_cnt, bond_dev->slaves[i].netdev->name); + } + bond_dev->slave_cnt = 0; + mutex_unlock(&bond_dev->slave_lock); + + hinic3_bond_detach(bond_dev->attr.bond_id, HINIC3_BOND_USER_ROCE); + kfree(bond_dev); + return; +} + +void roce3_before_bond_modify(const char *bond_name, struct bond_attr *attr) +{ + struct roce3_bond_device *bond_dev = NULL; + struct bond_tracker tracker; + int i; + bond_dev = roce3_get_bond_dev_by_name(bond_name); + if (!bond_dev) { + pr_err("[ROCE, ERR] %s: not find bond device by name(%s)\n", __func__, bond_name); + return; + } + + if (hinic3_get_bond_tracker_by_name(bond_name, &tracker) != 0) { + pr_err("[ROCE, ERR] %s: get bond tracker failed\n", __func__); + return; + } + + if (tracker.cnt == bond_dev->slave_cnt) { + bond_dev->attr = *attr; + for (i = 0; i < bond_dev->slave_cnt; i++) { + if (bond_dev->slaves[i].is_ppf) { + attr->first_roce_func = bond_dev->slaves[i].func_id; + break; + } + } + return; + } + + if (tracker.cnt > bond_dev->slave_cnt) { + pr_err("[ROCE, ERR] %s: Add slave is not support, bond name(%s)\n", __func__, bond_name); + return; + } + + if (tracker.cnt < ROCE_BOND_2_FUNC_NUM) { + roce3_bond_destroy(bond_dev->name); + return; + } + + return; +} + +static roce3_bond_service_func g_roce3_bond_proc[] = { + roce3_before_bond_active, + roce3_after_bond_active, + roce3_before_bond_modify, + roce3_after_bond_modify, + roce3_before_bond_deactive, + roce3_after_bond_deactive, +}; + +void roce3_bond_service_proc(const char *bond_name, void *bond_attr, enum bond_service_proc_pos pos) +{ + struct bond_attr *attr = (struct bond_attr *)bond_attr; + + if (bond_name == NULL) { + pr_err("[ROCE, ERR] %s: Bond_name is NULL\n", __func__); + return; + } + + if (pos >= BOND_POS_MAX) { + pr_err("[ROCE, ERR] %s: The pos is out of the range of proc_func\n", __func__); + return; + } + + if (g_roce3_bond_proc[pos] != NULL) { + g_roce3_bond_proc[pos](bond_name, attr); + } +} + +int roce3_bond_attach(struct roce3_device *rdev) +{ + int i; + int ret = 0; + struct roce3_bond_device *bond_dev; + + mutex_lock(&g_roce3_bond_mutex); + list_for_each_entry(bond_dev, &g_roce3_bond_list, entry) + { + mutex_lock(&bond_dev->slave_lock); + for (i = 0; i < bond_dev->slave_cnt; i++) { + if (rdev->ndev != bond_dev->slaves[i].netdev) { + continue; + } + + if (bond_dev->attached_rdev == NULL) { + bond_dev->attached_rdev = rdev; + rdev->bond_dev = bond_dev; + } else { + ret = -EEXIST; + } + mutex_unlock(&bond_dev->slave_lock); + goto out; + } + mutex_unlock(&bond_dev->slave_lock); + } +out: + mutex_unlock(&g_roce3_bond_mutex); + return ret; +} + +static void roce3_detach_bond_work(struct work_struct *_work) +{ + struct roce3_bond_work *work = container_of(_work, struct roce3_bond_work, work); + + roce3_bond_destroy(work->name); + + kfree(work); + return; +} + +void roce3_queue_bond_work(struct net_device *upper_netdev, work_func_t func) +{ + struct roce3_bond_work *work; + struct bonding *bond = netdev_priv(upper_netdev); + + if (!bond) { + pr_info("%s: (name:%s) has no bond dev.\n", __func__, upper_netdev->name); + return; + } + + work = kzalloc(sizeof *work, GFP_KERNEL); + if (!work) { + return; + } + + (void)strncpy(work->name, upper_netdev->name, strlen(upper_netdev->name)); + INIT_WORK(&work->work, func); + queue_work(g_bond_wq, &work->work); + return; +} + +int roce3_bond_netdev_event(struct notifier_block *this, unsigned long event, void *ptr) +{ + struct net_device *net_dev = NULL; + struct netdev_notifier_changeupper_info *info = NULL; + struct net_device *upper_netdev = NULL; + + info = (struct netdev_notifier_changeupper_info *)ptr; + net_dev = netdev_notifier_info_to_dev(ptr); + if (net_eq(dev_net(net_dev), &init_net) == 0) { + return NOTIFY_DONE; + } + + if (event != NETDEV_CHANGEUPPER) { + return NOTIFY_DONE; + } + + if (!is_hinic3_netdev(net_dev)) { + return NOTIFY_DONE; + } + + upper_netdev = info->upper_dev; + if (upper_netdev == NULL) { + return NOTIFY_DONE; + } + + if (!netif_is_lag_master(upper_netdev)) { + return NOTIFY_DONE; + } + + if (!roce3_can_do_bond(netdev_priv(upper_netdev))) { + roce3_queue_bond_work(upper_netdev, roce3_detach_bond_work); + return NOTIFY_DONE; + } + + roce3_queue_bond_work(upper_netdev, roce3_attach_bond_work); + return NOTIFY_DONE; +} + +static struct notifier_block nb_netdevice = { + .notifier_call = roce3_bond_netdev_event +}; + +int roce3_bond_init(void) +{ + int ret; + struct net_device *upper_netdev; + + g_bond_wq = alloc_ordered_workqueue("roce3-bond-wq", 0); + if (!g_bond_wq) { + pr_err("[ROCE, ERR] %s: Failed to alloc workqueue\n", __func__); + return -ENOMEM; + } + + ret = register_netdevice_notifier(&nb_netdevice); + if (ret) { + pr_err("[ROCE, ERR] %s: Failed to register netdevice notifier(%d)\n", __func__, ret); + goto nb_err; + } + + ret = hinic3_bond_register_service_func(HINIC3_BOND_USER_ROCE, roce3_bond_service_proc); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to register bond(%d)\n", __func__, ret); + goto err; + } + + rtnl_lock(); + for_each_netdev(&init_net, upper_netdev) + { + if (netif_is_bond_master(upper_netdev) && roce3_can_do_bond(netdev_priv(upper_netdev))) { + roce3_queue_bond_work(upper_netdev, roce3_attach_bond_work); + } + } + rtnl_unlock(); + + return 0; +err: + unregister_netdevice_notifier(&nb_netdevice); +nb_err: + destroy_workqueue(g_bond_wq); + return ret; +} + +void roce3_bond_pre_exit(void) +{ + int ret; + + ret = hinic3_bond_unregister_service_func(HINIC3_BOND_USER_ROCE); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to unregister service func(%d)\n", __func__, ret); + } + + unregister_netdevice_notifier(&nb_netdevice); + destroy_workqueue(g_bond_wq); +} + +void roce3_bond_exit(void) +{ + struct roce3_bond_device *bond_dev = NULL; + int i; + while (!list_empty(&g_roce3_bond_list)) { + bond_dev = list_first_entry(&g_roce3_bond_list, struct roce3_bond_device, entry); + list_del(&bond_dev->entry); + for (i = 0; i < bond_dev->slave_cnt; i++) { + pr_info("[ROCE, INFO] %s: EXIT dev_put: bond_name(%s),slave_cnt(%d), slave_name(%s)\n", + __func__, bond_dev->name, bond_dev->slave_cnt, bond_dev->slaves[i].netdev->name); + dev_put(bond_dev->slaves[i].netdev); + } + hinic3_bond_detach(bond_dev->attr.bond_id, HINIC3_BOND_USER_ROCE); + kfree(bond_dev); + } +} + +#endif diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq.h b/drivers/infiniband/hw/hiroce3/cq/roce_cq.h new file mode 100644 index 000000000..71259a0d4 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq.h + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/2/21 + * Description : Define standard kernel RoCE CQ common header. + */ + +#ifndef ROCE_CQ_H +#define ROCE_CQ_H + +#include <rdma/ib_verbs.h> +#include <linux/slab.h> + +#include "hinic3_hw.h" +#include "hinic3_rdma.h" + +#include "rdma_context_format.h" + +#include "roce.h" +#include "roce_compat.h" +#include "roce_srq.h" +#include "roce_xrc.h" +#include "roce_user.h" +#include "hinic3_hmm.h" + +#define ROCE_CQN_INVLD 0xFFFFFFFF + +/* DB type of ARM_CQ */ +enum { + ROCE_CQ_DB_REQ_NOT_SOL = 1, + ROCE_CQ_DB_REQ_NOT = 2 +}; + +#define CQ_GPA_SIG_LEN 3 +#define CQ_DW_TO_BYTE 4 + +/* the type of err cqe +IB compliant completion with error syndrome: + 0x01 - Local Length Error () + 0x02 - Local QP Operation Error + 0x04 - Local Protection Error + 0x05 - Work Request Flushed Error + 0x06 - Memory Window Bind Error + 0x10 - Bad Response Error + 0x11 - Local Access Error + 0x12 - Remote Invalid Request Error + 0x13 - Remote Access Error + 0x14 - Remote Operation Error + 0x15 - Transport Retry Counter Exceeded + 0x16 - RNR Retry Counter Exceeded + 0x22 - Remote Aborted Error + other - reserved +Syndrome is defined according to the InfiniBand Architecture Specification, +Volume 1. For a detailed explanation of the syndromes, refer to the Software +Transport Interface and Software Transport Verbs chapters of the IB specifica- +tion. +*/ +enum roce3_cqe_syndrome { + ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01, + ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02, + ROCE_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04, + ROCE_CQE_SYNDROME_WR_FLUSH_ERR = 0x05, + + ROCE_CQE_SYNDROME_MW_BIND_ERR = 0x06, + ROCE_CQE_SYNDROME_BAD_RESP_ERR = 0x10, + + ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11, + ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, + ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13, + ROCE_CQE_SYNDROME_REMOTE_OP_ERR = 0x14, + ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15, + + ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16, + + ROCE_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22, + ROCE_CQE_SYNDROME_MAX = 0x23 +}; + +/* +1.Same type of operation as SQ WQE +8'h00-Send +8'h01-Send with Invalidate +8'h02-Send with Immediate Data +8'h03-reserved + +8'h04-RDMA Write +8'h05-RDMA Write with Immediate Data +8'h06-reserved +8'h07-reserved + +8'h08-RDMA Read +8'h09-reserved +8'h0a-reserved +8'h0b-reserved + +8'h0c-Atomic Compare & Swap +8'h0d-Atomic Fetch & Add +8'h0e-Atomic Masked Compare & Swap (Extended Atomic operation) +8'h0f-Atomic Masked Fetch & Add (Extended Atomic operation) + +8'h10-Fast Register PMR +8'h11-Local Invalidate +8'h12-Bind Memory Window Type1/2 +8'h13-Local opreation(Extended for further local opreation) +other-Reserved + +2.Receive +00000 - RDMA Write with Immediate +00001 - Send +00010 - Send with Immediate +00011 - Send & Invalidate + +3.The following are general +11110 Error coding +10110 Resize coding +*/ +enum roce3_cqe_send_opcode { + ROCE_OPCODE_SEND = 0x0, + ROCE_OPCODE_SEND_WITH_INV = 0x1, + ROCE_OPCODE_SEND_WITH_IMM = 0x2, + /* 0x3 reserved */ + + ROCE_OPCODE_RDMA_WRITE = 0x4, + ROCE_OPCODE_RDMA_WRITE_WITH_IMM = 0x5, + /* 0x6 and 0x7 reserved */ + + ROCE_OPCODE_RDMA_READ = 0x8, + /* 0x9~0xb reserved */ + + ROCE_OPCODE_ATOMIC_COMP_AND_SWP = 0xc, + ROCE_OPCODE_ATOMIC_FETCH_AND_ADD = 0xd, + ROCE_OPCODE_ATOMIC_MASKED_COMP_AND_SWP = 0xe, + ROCE_OPCODE_ATOMIC_MASKED_FETCH_AND_ADD = 0xf, + + ROCE_OPCODE_FAST_REG_PMR = 0x10, + ROCE_OPCODE_LOCAL_INV = 0x11, + ROCE_OPCODE_BIND_TYPE2_MW = 0x12, + ROCE_OPCODE_REG_SIG_MR = 0x13, + + ROCE_OPCODE_RESIZE_CQE = 0x16, + ROCE_OPCODE_ERR = 0x1e, + ROCE_OPCODE_CQE_UNUSED = 0x1f /* Be used in new CQ buf when reszie cq */ +}; + +enum roce3_cqe_recv_opcode { + ROCE_RECV_OPCODE_RDMA_WRITE_WITH_IMM = 0x0, + ROCE_RECV_OPCODE_SEND = 0x1, + ROCE_RECV_OPCODE_SEND_WITH_IMM = 0x2, + ROCE_RECV_OPCODE_SEND_WITH_INV = 0x3 +}; + +/* Define the state type of the CQ */ +enum cq_state { + ROCE_CQ_STATE_INVALID = 0x0, + ROCE_CQ_STATE_ERR = 0x1, + ROCE_CQ_STATE_OVERFLOW = 0x2, + ROCE_CQ_STATE_VALID = 0xf, + ROCE_CQ_STATE_MEM_INIT = 0xa /* Initial value of Host Memory */ +}; + +#define ROCE_CQ_TIME_OUT_CHECK_VALUE 0xe +#define ROCE_CQ_STATE_CHECK_VALUE 0x0 + +#define ROCE_CQE_RQ_INLINE 1 +#define ROCE_CQE_RQ_NORMAL 0 +#define ROCE_CQE_SEND_COMP 1 +#define ROCE_CQE_RECV_COMP 0 + +#define ATOMIC_DATA_LEN 8 /* Specified as 8B by protocol */ + +#define ROCE_CQE_INVALID_VALUE 0xff +#define ROCE_CQ_RESIZE_POLL_TIMES 100 + +/* roce Commands, bufs and data structures related to cq */ +struct roce3_cq_query_outbuf { + struct roce_cq_context cqc; +}; + +struct roce3_cq_buf { + struct tag_cqm_buf *buf; /* pointer to describe the buf structure b cqm */ + struct rdma_mtt mtt; /* the mtt struct used by kernel mode and user mode to discribe buf */ + int entry_size; /* the size of cqe */ + int buf_size; /* the size of cq_buf */ +}; + +struct roce3_cq_resize_buf { + struct roce3_cq_buf buf; /* the size of buf that was resized */ + int cqe; /* the number of resized cqe */ +}; + +struct roce3_cq { + struct ib_cq ibcq; + cqm_queue_s *cqm_cq; /* Save the handle obtained from cqm */ + struct roce3_db db; /* The address information of the software DB that stores the CI user mode/kernel mode */ + __be32 *set_ci_db; /* Kernel-mode software DB */ + u32 cons_index; /* consumer pointer */ + + u32 arm_sn; /* the serial number of arm */ + int arm_flag; /* Used to determine whether the arm command has been sent, to avoid repeated sending */ + u32 cqn; + unsigned int vector; /* associated to the eq used */ + struct roce3_cq_buf buf; /* pointer describing the buf structure of cqm */ + struct roce3_cq_resize_buf *resize_buf; /* resize buf struction */ + + spinlock_t lock; /* Need to lock when operating cq */ + struct mutex resize_mutex; /* resize the mutex of cq */ + struct ib_umem *umem; /* record the infomation mapped by User-mode buf */ + struct ib_umem *resize_umem; /* record the infomation mapped by buf which the User-mode resized */ + + struct list_head send_qp_list; /* send queue qp */ + struct list_head recv_qp_list; /* receive queue qp */ + + int reset_notify_added; + struct list_head reset_notify; + + void (*reset_flow_comp)(struct roce3_cq *); +}; + +/* cross ibcroce3_e_cq */ +static inline struct roce3_cq *to_roce3_cq(const struct ib_cq *ibcq) +{ + return container_of(ibcq, struct roce3_cq, ibcq); +} + +/* obroce3_roce_cq crossing cqm */ +static inline struct roce3_cq *cqmobj_to_roce3_cq(const cqm_object_s *object) +{ + cqm_queue_s *cqm_cq; + cqm_cq = container_of(object, cqm_queue_s, object); + return (struct roce3_cq *)cqm_cq->priv; +} + +/* Used when destroy QP */ +void roce3_cq_clean(struct roce3_cq *cq, u32 qpn, struct roce3_srq *srq); +void roce3_cq_async_event(struct roce3_device *rdev, struct roce3_cq *cq, int type); +void roce3_cq_clean_process(struct roce3_cq *cq, u32 qpn, struct roce3_srq *srq); +void roce3_cq_put_umem(struct roce3_device *rdev, struct roce3_cq_buf *buf, struct ib_umem **umem); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) || defined(OFED_MLNX_5_8) +int roce3_cq_get_umem(struct roce3_device *rdev, struct ib_udata *udata, struct roce3_cq_buf *buf, + struct ib_umem **umem, u64 buf_addr, int cqe); +int roce3_create_cq_common(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_udata *udata, struct roce3_cq *rcq, u32 index); +#else +int roce3_cq_get_umem(struct roce3_device *rdev, struct ib_ucontext *context, struct roce3_cq_buf *buf, + struct ib_umem **umem, u64 buf_addr, int cqe); +struct ib_cq *roce3_create_cq_common(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_ucontext *ibcontext, struct ib_udata *udata, u32 index); +#endif + +void *roce3_get_sw_cqe(struct roce3_cq *cq, unsigned int n); +void *roce3_get_cqe_from_buf(struct roce3_cq_buf *buf, unsigned int n); +void roce3_cq_set_ci(struct roce3_cq *cq); +void roce3_cq_buf_init(struct roce3_cq_buf *buf); +void *roce3_get_cqe(struct roce3_cq *cq, unsigned int n); +void roce_reset_flow_comp(struct roce3_cq *rcq); + +void roce3_lock_cqs(struct roce3_cq *roce3_send_cq, struct roce3_cq *roce3_recv_cq) __acquires(&roce3_send_cq->lock) + __acquires(&roce3_recv_cq->lock); +void roce3_unlock_cqs(struct roce3_cq *roce3_send_cq, struct roce3_cq *roce3_recv_cq) __releases(&roce3_send_cq->lock) + __releases(&roce3_recv_cq->lock); + +#endif // ROCE_CQ_H diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq_common.c b/drivers/infiniband/hw/hiroce3/cq/roce_cq_common.c new file mode 100644 index 000000000..d6fbef241 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq_common.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq_common.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/3/24 + * Description : The definition of RoCE CQ kernel functions. + */ + +#include <linux/slab.h> + +#include "hinic3_hw.h" + +#include "roce.h" +#include "roce_srq.h" +#include "roce_qp.h" +#include "roce_mix.h" +#include "roce_xrc.h" +#include "roce_user.h" +#include "roce_cq.h" +#include "roce_pub_cmd.h" +#include "hinic3_hmm.h" + +/* **************************************************************************** + Prototype : roce3_cq_async_event + Description : roce3_cq_async_event + Input : struct roce3_device *rdev + struct roce3_cq *cq + int type + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +void roce3_cq_async_event(struct roce3_device *rdev, struct roce3_cq *cq, int type) +{ + struct ib_cq *ibcq = &cq->ibcq; + struct ib_event event; + + memset(&event, 0, sizeof(event)); + if (type != ROCE_EVENT_TYPE_CQ_ERROR) { + dev_warn_ratelimited(rdev->hwdev_hdl, "[ROCE] %s: Unexpected event type(0x%x) on CQ(%06x), func_id(%d)\n", + __func__, type, cq->cqn, rdev->glb_func_id); + return; + } + + if (ibcq->event_handler) { + event.device = ibcq->device; + event.event = IB_EVENT_CQ_ERR; + event.element.cq = ibcq; + ibcq->event_handler(&event, ibcq->cq_context); + } +} + +/* **************************************************************************** + Prototype : roce3_cq_buf_init + Description : roce3_cq_buf_init + Input : struct roce3_cq_buf *buf + Output : None + + 1.Date : 2015/11/9 + Modification : Created function + +**************************************************************************** */ +void roce3_cq_buf_init(struct roce3_cq_buf *buf) +{ + /* optype was initialized into ROCE_OPCODE_CQE_UNUSED(0x1f) */ + memset(buf->buf->direct.va, ROCE_CQE_INVALID_VALUE, + (unsigned long)((unsigned)buf->buf_size)); +} + +/* **************************************************************************** + Prototype : roce3_cq_put_umem + Description : Release umem and corresponding mtt, corresponding to put + Input : struct roce3_device *rdev + struct roce3_cq_buf *buf + struct ib_umem **umem + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +void roce3_cq_put_umem(struct roce3_device *rdev, struct roce3_cq_buf *buf, struct ib_umem **umem) +{ + /* free MTT of Buffer */ + hmm_rdma_mtt_free(rdev->hwdev, &buf->mtt, SERVICE_T_ROCE); + + /* release umem */ + ib_umem_release(*umem); +} + +static void *roce3_cq_buf_offset(struct tag_cqm_buf *buf, unsigned int offset) +{ + return (void *)((char *)buf->direct.va + offset); +} + +void *roce3_get_cqe_from_buf(struct roce3_cq_buf *buf, unsigned int n) +{ + return roce3_cq_buf_offset(buf->buf, (n * buf->entry_size)); +} + +void *roce3_get_cqe(struct roce3_cq *cq, unsigned int n) +{ + return roce3_get_cqe_from_buf(&cq->buf, n); +} + +/* **************************************************************************** + Prototype : roce3_get_sw_cqe + Description : roce3_get_sw_cqe + Input : struct roce3_cq *cq + unsigned int n + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +void *roce3_get_sw_cqe(struct roce3_cq *cq, unsigned int n) +{ + struct roce_cqe *cqe = (struct roce_cqe *)roce3_get_cqe(cq, (n & ((unsigned int)cq->ibcq.cqe))); + struct roce_cqe tmp_cqe; + unsigned int tmp_val; + + tmp_cqe.dw0.value = roce3_convert_cpu32(cqe->dw0.value); + tmp_cqe.dw1.value = roce3_convert_cpu32(cqe->dw1.value); + + /* Add judgment condition: the optype of CQE cannot be UNUSED, UNUSED means that it has been initialized in resize + cq */ + tmp_val = ((n & ((unsigned int)cq->ibcq.cqe + 1)) == 0) ? 1 : 0; + if ((ROCE_LIKELY(tmp_cqe.dw1.bs.op_type != ROCE_OPCODE_CQE_UNUSED)) && ((tmp_cqe.dw0.bs.owner ^ tmp_val) != 0)) { + return cqe; + } + + return NULL; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) || defined(OFED_MLNX_5_8) +int roce3_cq_get_umem(struct roce3_device *rdev, struct ib_udata *udata, struct roce3_cq_buf *buf, + struct ib_umem **umem, u64 buf_addr, int cqe) +#else +int roce3_cq_get_umem(struct roce3_device *rdev, struct ib_ucontext *context, struct roce3_cq_buf *buf, + struct ib_umem **umem, u64 buf_addr, int cqe) +#endif +{ + int ret = 0; + u32 npages = 0; + int page_shift = 0; + int cqe_size = (int)rdev->rdma_cap.cqe_size; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) + *umem = ib_umem_get(&rdev->ib_dev, buf_addr, (unsigned long)(cqe * cqe_size), IB_ACCESS_LOCAL_WRITE); +#elif defined(OFED_MLNX_5_8) + *umem = ib_umem_get(udata, buf_addr, (unsigned long)(cqe * cqe_size), IB_ACCESS_LOCAL_WRITE); +#else + *umem = ib_umem_get(context, buf_addr, (unsigned long)(unsigned)(cqe * cqe_size), IB_ACCESS_LOCAL_WRITE, 1); +#endif + if (IS_ERR(*umem)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get ib_umem, func_id(%d)\n", __func__, rdev->glb_func_id); + return (int)PTR_ERR(*umem); + } + + npages = (u32)ib_umem_num_pages(*umem); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + page_shift = PAGE_SHIFT; +#else + page_shift = (*umem)->page_shift; +#endif + + buf->mtt.mtt_type = MTT_CMTT_TYPE; + ret = hmm_rdma_mtt_alloc(rdev->hwdev, npages, (u32)page_shift, &buf->mtt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma_mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_buf; + } + + ret = roce3_umem_write_mtt(rdev, &buf->mtt, *umem); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write mtt for umem, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_mtt; + } + + return 0; + +err_mtt: + hmm_rdma_mtt_free(rdev->hwdev, &buf->mtt, SERVICE_T_ROCE); + +err_buf: + ib_umem_release(*umem); + + return ret; +} + +void roce_reset_flow_comp(struct roce3_cq *rcq) +{ + struct ib_cq *ibcq = &rcq->ibcq; + + ibcq->comp_handler(ibcq, ibcq->cq_context); +} diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq_cqe.c b/drivers/infiniband/hw/hiroce3/cq/roce_cq_cqe.c new file mode 100644 index 000000000..40737a0a1 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq_cqe.c @@ -0,0 +1,731 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq_cqe.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/3/24 + * Description : The definition of RoCE CQ kernel CQE related functions. + */ + +#include <linux/slab.h> + +#include "hinic3_hw.h" + +#include "roce.h" +#include "roce_srq.h" +#include "roce_qp.h" +#include "roce_mix.h" +#include "roce_xrc.h" +#include "roce_cq.h" + +#include "roce_main_extension.h" + +/* **************************************************************************** + Prototype : roce3_next_cqe_sw + Description : roce3_next_cqe_sw + Input : struct roce3_cq *cq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static struct roce_cqe *roce3_next_cqe_sw(struct roce3_cq *cq) +{ + return (struct roce_cqe *)roce3_get_sw_cqe(cq, cq->cons_index); +} + +/*lint -e26*/ +static int g_error_cqe_to_wc[ROCE_CQE_SYNDROME_MAX] = { + [ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR] = IB_WC_LOC_LEN_ERR, + [ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR] = IB_WC_LOC_QP_OP_ERR, + [ROCE_CQE_SYNDROME_LOCAL_PROT_ERR] = IB_WC_LOC_PROT_ERR, + [ROCE_CQE_SYNDROME_WR_FLUSH_ERR] = IB_WC_WR_FLUSH_ERR, + + [ROCE_CQE_SYNDROME_MW_BIND_ERR] = IB_WC_MW_BIND_ERR, + [ROCE_CQE_SYNDROME_BAD_RESP_ERR] = IB_WC_BAD_RESP_ERR, + + [ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR] = IB_WC_LOC_ACCESS_ERR, + [ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR] = IB_WC_REM_INV_REQ_ERR, + [ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR] = IB_WC_REM_ACCESS_ERR, + [ROCE_CQE_SYNDROME_REMOTE_OP_ERR] = IB_WC_REM_OP_ERR, + [ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR] = IB_WC_RETRY_EXC_ERR, + + [ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR] = IB_WC_RNR_RETRY_EXC_ERR, + + [ROCE_CQE_SYNDROME_REMOTE_ABORTED_ERR] = IB_WC_REM_ABORT_ERR, +}; +/*lint +e26*/ + +/* **************************************************************************** + Prototype : roce3_handle_error_cqe + Description : roce3_handle_error_cqe + Input : struct roce_err_cqe *cqe + struct ib_wc *wc + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_handle_error_cqe(struct roce_err_cqe *cqe, struct ib_wc *wc) +{ + if (cqe->dw7.bs.syndrome >= ROCE_CQE_SYNDROME_MAX) { + wc->status = IB_WC_GENERAL_ERR; + } else if (cqe->dw7.bs.syndrome > 0) { + wc->status = g_error_cqe_to_wc[cqe->dw7.bs.syndrome]; + if (wc->status == 0) { + wc->status = IB_WC_GENERAL_ERR; + } + } + + wc->vendor_err = cqe->dw7.bs.vendor_err; +} + +static void roce3_get_local_opcode_from_cqe(const struct roce_cqe *cqe, struct ib_wc *wc) +{ + switch (cqe->dw1.bs.op_type) { + case ROCE_OPCODE_LOCAL_INV: + wc->opcode = IB_WC_LOCAL_INV; + break; + case ROCE_OPCODE_REG_SIG_MR: + wc->opcode = IB_WC_REG_MR; + break; + + default: + pr_warn("[ROCE] %s: Unknown cqe optype\n", __func__); + break; + } +} + +static void roce3_get_opcode_type_part_1(struct roce_cqe *cqe, struct ib_wc *wc) +{ + switch (cqe->dw1.bs.op_type) { + case ROCE_OPCODE_RDMA_WRITE_WITH_IMM: + wc->opcode = IB_WC_RDMA_WRITE; + wc->wc_flags = (int)((u32)wc->wc_flags | IB_WC_WITH_IMM); + break; + + case ROCE_OPCODE_RDMA_WRITE: + wc->opcode = IB_WC_RDMA_WRITE; + break; + + case ROCE_OPCODE_SEND_WITH_IMM: + wc->opcode = IB_WC_SEND; + wc->wc_flags = (int)((u32)wc->wc_flags | IB_WC_WITH_IMM); + break; + + case ROCE_OPCODE_SEND: + wc->opcode = IB_WC_SEND; + break; + + case ROCE_OPCODE_SEND_WITH_INV: + wc->opcode = IB_WC_SEND; + break; + default: + roce3_get_local_opcode_from_cqe(cqe, wc); + break; + } +} + +static void roce3_get_opcode_type_part_2(struct roce_cqe *cqe, struct ib_wc *wc) +{ + switch (cqe->dw1.bs.op_type) { + case ROCE_OPCODE_RDMA_READ: + wc->opcode = IB_WC_RDMA_READ; + wc->byte_len = cqe->byte_cnt; + break; + + case ROCE_OPCODE_ATOMIC_COMP_AND_SWP: + wc->opcode = IB_WC_COMP_SWAP; + wc->byte_len = ATOMIC_DATA_LEN; + break; + + case ROCE_OPCODE_ATOMIC_FETCH_AND_ADD: + wc->opcode = IB_WC_FETCH_ADD; + wc->byte_len = ATOMIC_DATA_LEN; + break; + + case ROCE_OPCODE_ATOMIC_MASKED_COMP_AND_SWP: + wc->opcode = IB_WC_MASKED_COMP_SWAP; + wc->byte_len = ATOMIC_DATA_LEN; + break; + + case ROCE_OPCODE_ATOMIC_MASKED_FETCH_AND_ADD: + wc->opcode = IB_WC_MASKED_FETCH_ADD; + wc->byte_len = ATOMIC_DATA_LEN; + break; + case ROCE_OPCODE_FAST_REG_PMR: + wc->opcode = IB_WC_REG_MR; + break; + + default: + roce3_get_local_opcode_from_cqe(cqe, wc); + break; + } +} + +/* **************************************************************************** + Prototype : roce3_get_opcode_from_scqe + Description : Set the opcode/flag/byte_len of wc according to the opcode of send_cqe + Input : struct roce_cqe *cqe + struct ib_wc *wc + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_get_opcode_from_scqe(struct roce_cqe *cqe, struct ib_wc *wc) +{ + wc->wc_flags = 0; + + if (cqe->dw1.bs.op_type < ROCE_OPCODE_RDMA_READ) { + roce3_get_opcode_type_part_1(cqe, wc); + } else { + roce3_get_opcode_type_part_2(cqe, wc); + } +} + +/* **************************************************************************** + Prototype : roce3_get_opcode_from_rcqe + Description : Set the opcode/flag/byte_len of wc according to the opcode of send_cqe + Input : struct roce_cqe *cqe + struct ib_wc *wc + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_get_opcode_from_rcqe(struct roce_cqe *cqe, struct ib_wc *wc) +{ + wc->byte_len = cqe->byte_cnt; + + switch (cqe->dw1.bs.op_type) { + case ROCE_RECV_OPCODE_RDMA_WRITE_WITH_IMM: + wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; + wc->wc_flags = IB_WC_WITH_IMM; + /* The driver does not perform big or small endian conversion for immediate data, but the incoming CQE + has been converted to the CPU endian, so it needs to be converted back */ + wc->ex.imm_data = roce3_convert_be32(cqe->imm_invalid_rkey); + break; + + case ROCE_RECV_OPCODE_SEND_WITH_INV: + wc->opcode = IB_WC_RECV; + wc->wc_flags = IB_WC_WITH_INVALIDATE; + wc->ex.invalidate_rkey = cqe->imm_invalid_rkey; + break; + + case ROCE_RECV_OPCODE_SEND: + wc->opcode = IB_WC_RECV; + wc->wc_flags = 0; + break; + + case ROCE_RECV_OPCODE_SEND_WITH_IMM: + wc->opcode = IB_WC_RECV; + wc->wc_flags = IB_WC_WITH_IMM; + /* The driver does not perform big or small endian conversion for immediate data, but the incoming CQE + has been converted to the CPU endian, so it needs to be converted back */ + wc->ex.imm_data = roce3_convert_be32(cqe->imm_invalid_rkey); + break; + + default: + pr_warn("[ROCE] %s: Not supported\n", __func__); + break; + } +} + +/* **************************************************************************** + Prototype : roce3_cq_poll_and_resize + Description : roce3_cq_poll_and_resize + Input : struct roce3_cq *cq + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static void roce3_cq_poll_and_resize(struct roce3_device *rdev, struct roce3_cq *cq) +{ + if (ROCE_LIKELY(cq->resize_buf != NULL)) { + /* Release the original Buffer of CQ */ + hiudk_cqm_object_resize_free_old(rdev->hwdev, &cq->cqm_cq->object); + cq->buf = cq->resize_buf->buf; + cq->ibcq.cqe = cq->resize_buf->cqe; + + kfree(cq->resize_buf); + cq->resize_buf = NULL; + } + + --cq->cons_index; + + return; +} + +/* **************************************************************************** + Prototype : roce3_cq_get_cur_qp + Description : roce3_cq_get_cur_qp + Input : struct roce3_cq *cq + struct roce3_qp **cur_qp + struct roce_cqe *cqe + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_get_cur_qp(struct roce3_cq *cq, struct roce3_qp **cur_qp, struct roce_cqe *cqe) +{ + struct roce3_device *rdev = NULL; + cqm_object_s *cqm_obj_qp = NULL; + + if ((!*cur_qp) || (cqe->dw0.bs.qpn != (u32)(*cur_qp)->qpn)) { + /* + * We do not have to take the QP table lock here, + * because CQs will be locked while QPs are removed + * from the table. + */ + rdev = to_roce3_dev(cq->ibcq.device); + cqm_obj_qp = cqm_object_get(rdev->hwdev, CQM_OBJECT_SERVICE_CTX, cqe->dw0.bs.qpn, false); + if (cqm_obj_qp == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: CQ(%06x) with entry for unknown QPN(%06x), func_id(%d)\n", + __func__, cq->cqn, cqe->dw0.bs.qpn, rdev->glb_func_id); + return -EINVAL; + } + + *cur_qp = cqmobj_to_roce_qp(cqm_obj_qp); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_qp); + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_cq_get_xrc_srq + Description : roce3_cq_get_xrc_srq + Input : struct roce3_cq *cq + struct roce3_srq **srq + struct roce_cqe *cqe + u32 qp_type + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_get_xrc_srq(struct roce3_cq *cq, struct roce3_srq **srq, struct roce_cqe *cqe, u32 qp_type) +{ + u32 srq_num = 0; + struct roce3_device *rdev = NULL; + cqm_object_s *cqm_obj_srq = NULL; + + if (qp_type == IB_QPT_XRC_TGT) { + srq_num = cqe->dw6.bs.srqn_rqpn; + + /* SRQ is also in the radix tree */ + rdev = to_roce3_dev(cq->ibcq.device); + cqm_obj_srq = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SRQ, srq_num, false); + if (cqm_obj_srq == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: CQ(%06x) with entry for unknown SRQN(%06x), func_id(%d)\n", + __func__, cq->cqn, srq_num, rdev->glb_func_id); + return -EINVAL; + } + + /* Get roce3__srq structure through cqm object */ + *srq = cqmobj_to_roce3_srq(cqm_obj_srq); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_srq); + } + + return 0; +} + +static int roce3_poll_recv_cqe(struct roce3_qp *cur_qp, struct roce3_srq *srq, struct roce_cqe trans_cqe, + struct ib_wc *wc) +{ + u16 wqe_ctr = 0; + unsigned int tail = 0; + struct roce3_srq *srq_tmp; + + if (cur_qp->ibqp.srq) { + srq_tmp = to_roce3_srq(cur_qp->ibqp.srq); + + wqe_ctr = (u16)trans_cqe.dw1.bs.wqebb_cnt; + /* Determine whether to overflow */ + if (wqe_ctr > srq_tmp->max_depth) { + pr_err("[ROCE, ERR] %s: Get wqe index(0x%x) from cqe\n", __func__, wqe_ctr); + return -EINVAL; + } + + wc->wr_id = srq_tmp->wrid[wqe_ctr]; + roce3_free_srq_wqe(srq_tmp, wqe_ctr); + } else if (srq) { + wqe_ctr = (u16)trans_cqe.dw1.bs.wqebb_cnt; + /* Determine whether to overflow */ + if (wqe_ctr > srq->max_depth) { + pr_err("[ROCE, ERR] %s: Get wqe index(0x%x) from cqe\n", __func__, wqe_ctr); + return -EINVAL; + } + + wc->wr_id = srq->wrid[wqe_ctr]; + roce3_free_srq_wqe(srq, wqe_ctr); + } else { + struct roce3_wq *wq = &(cur_qp->rq); + tail = (u32)(wq->tail & ((unsigned int)wq->wqebb_cnt - 1)); + wc->wr_id = wq->wrid[tail]; + ++wq->tail; + } + + return 0; +} + +static void roce3_poll_move_tail(const struct roce3_qp *cur_qp, struct roce3_wq *wq, struct roce_cqe *trans_cqe) +{ + u16 wqe_ctr = 0; + if (cur_qp->sq_signal_bits == 0) { + wqe_ctr = trans_cqe->dw7.bs.wqe_cnt; + wq->tail += (u16)(wqe_ctr - (u16)wq->tail); + } +} + +static void roce3_poll_one_get_av_info(const struct roce3_qp *cur_qp, struct ib_wc *wc, struct roce_cqe trans_cqe, + struct roce_cqe *cqe) +{ + if ((cur_qp->qp_type == IB_QPT_UD) || (cur_qp->qp_type == IB_QPT_GSI)) { + wc->sl = trans_cqe.dw4.bs.vlan_pri; + wc->src_qp = trans_cqe.dw6.bs.srqn_rqpn; + wc->network_hdr_type = trans_cqe.dw6.bs.stp; + wc->smac[0] = (u8)(trans_cqe.dw4.bs.smac_h >> 8); /* Take the first Byte data, shift 8bit */ + wc->smac[1] = (u8)(trans_cqe.dw4.bs.smac_h & 0xff); + memcpy(&wc->smac[2], &cqe->smac_l, sizeof(cqe->smac_l)); // 2 : smac array idx + wc->wc_flags = (int)((u32)wc->wc_flags | IB_WC_WITH_SMAC); + if (trans_cqe.dw6.bs.vlan_pre != 0) { + wc->vlan_id = trans_cqe.dw4.bs.vlan_id; + wc->wc_flags = (int)((u32)wc->wc_flags | IB_WC_WITH_VLAN); + } + } +} + +static int roce3_poll_one_get_qp_and_srq(struct roce3_cq *cq, struct roce3_qp **cur_qp, struct ib_wc *wc, + struct roce_cqe *trans_cqe, struct roce3_srq **srq) +{ + int ret = 0; + ret = roce3_cq_get_cur_qp(cq, cur_qp, trans_cqe); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get current qp\n", __func__); + return ret; + } + + wc->qp = &((*cur_qp)->ibqp); + + ret = roce3_cq_get_xrc_srq(cq, srq, trans_cqe, wc->qp->qp_type); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to get xrc srq\n", __func__); + return ret; + } + + return ret; +} + +static void roce3_bytes_trans(u32 *addr, int dw_num) +{ + u32 *dw = addr; + int i = 0; + + for (i = 0; i < dw_num; i++) { + *dw = roce3_convert_cpu32(*dw); + dw++; + } +} + +static int roce3_get_and_trans_cqe(struct roce3_device *rdev, struct roce3_cq *cq, struct roce_cqe *trans_cqe, + int *is_send, struct roce_cqe **cqe) +{ + do { + *cqe = roce3_next_cqe_sw(cq); + if (*cqe == NULL) { + return -EAGAIN; + } + + /* Later, it is necessary to perform big and small end conversion on CQE. + In order to avoid turning back after processing, copy a copy */ + memcpy((void *)trans_cqe, (void *)*cqe, sizeof(struct roce_cqe)); + ++cq->cons_index; + + /* + * Make sure we read CQ entry contents after we've checked the + * ownership bit. + */ + rmb(); + + /* Convert the CQE into the CPU endian corresponding to the running environment */ + roce3_bytes_trans((u32 *)(void *)trans_cqe, (int)(sizeof(struct roce_cqe) / CQ_DW_TO_BYTE)); + + *is_send = trans_cqe->dw1.bs.s_r; + /* Resize CQ operation in progress */ + if (ROCE_UNLIKELY(trans_cqe->dw1.bs.op_type == ROCE_OPCODE_RESIZE_CQE)) { + roce3_cq_poll_and_resize(rdev, cq); + } + } while (ROCE_UNLIKELY(trans_cqe->dw1.bs.op_type == ROCE_OPCODE_RESIZE_CQE)); + + return 0; +} + +static void roce3_poll_send_cqe(struct roce3_qp *cur_qp, struct roce_cqe *trans_cqe, struct ib_wc *wc) +{ + struct roce3_wq *wq = &(cur_qp->sq); + /* QP of type IB_SIGNAL_REQ_WR, tail needs to skip several WRs that do not generate CQE */ + roce3_poll_move_tail(cur_qp, wq, trans_cqe); + + wc->wr_id = wq->wrid[wq->tail & ((unsigned int)wq->wqebb_cnt - 1)]; + ++wq->tail; + + if (trans_cqe->dw1.bs.op_type == ROCE_OPCODE_ERR) { + roce3_handle_error_cqe((struct roce_err_cqe *)(void *)trans_cqe, wc); + return; + } + + roce3_get_opcode_from_scqe(trans_cqe, wc); +} + +/* **************************************************************************** + Prototype : roce3_poll_one + Description : roce3_poll_one + Input : struct roce3_cq *cq + struct roce3_qp **cur_qp + struct ib_wc *wc + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_poll_one(struct roce3_device *rdev, struct roce3_cq *cq, struct roce3_qp **cur_qp, struct ib_wc *wc) +{ + int ret = 0; + struct roce_cqe *cqe = NULL; + struct roce_cqe trans_cqe; + struct roce3_srq *srq = NULL; + int is_send = 0; + bool need_poll = true; + + while (need_poll) { + ret = roce3_get_and_trans_cqe(rdev, cq, &trans_cqe, &is_send, &cqe); + if (ret != 0) { + return -EAGAIN; + } + + ret = roce3_poll_one_get_qp_and_srq(cq, cur_qp, wc, &trans_cqe, &srq); + if (ret != 0) { + return ret; + } + + /* Poll cq exception handling, generally cq judges user state information, xrc judges wrid */ + if ((*cur_qp)->umem || ((*cur_qp)->ibqp.xrcd && !(srq->wrid))) { + pr_err("[ROCE, ERR] %s: qp(%u) create in user space , but poll cq in kernel. NOT PERMIT!\n", __func__, + (*cur_qp)->qpn); + return -EACCES; + } + + if (trans_cqe.dw1.bs.fake != 0) { + pr_info("[ROCE] %s: Fake cqe go repoll.\n", __FUNCTION__); + continue; + } + + wc->status = IB_WC_SUCCESS; + if (is_send != 0) { + roce3_poll_send_cqe(*cur_qp, &trans_cqe, wc); + return 0; + } else { + ret = roce3_poll_recv_cqe(*cur_qp, srq, trans_cqe, wc); + if (ret != 0) { + return ret; + } + } + + if (trans_cqe.dw1.bs.op_type == ROCE_OPCODE_ERR) { + roce3_handle_error_cqe((struct roce_err_cqe *)(void *)&trans_cqe, wc); + return 0; + } + + roce3_get_opcode_from_rcqe(&trans_cqe, wc); + wc->wc_flags = (int)((unsigned int)wc->wc_flags | IB_WC_GRH); + wc->pkey_index = 0; + wc->vlan_id = 0xffff; + wc->sl = 0; + + /* avoid cm_req_handler()->ib_lid_be16() trigger call trace */ + wc->slid = 0; + + roce3_poll_one_get_av_info((*cur_qp), wc, trans_cqe, cqe); + + /* Kernel mode does not support receiving inline */ + if (trans_cqe.dw1.bs.inline_r == ROCE_CQE_RQ_INLINE) { + pr_err("[ROCE, ERR] %s: Receive inline not supported in kernel space\n", __func__); + return -EINVAL; + } + need_poll = false; + } + + return 0; +} + +static int sw_send_comp(struct roce3_qp *rqp, int num_entries, int *npolled, struct ib_wc *wc) +{ + struct roce3_wq *wq = &rqp->sq; + unsigned int cur = wq->head - wq->tail; + unsigned int i; + + if (cur == 0) { + goto out; + } + + for (i = 0; (i < cur) && (*npolled < num_entries); i++) { + wc[*npolled].wr_id = wq->wrid[wq->tail & (wq->wqebb_cnt - 1)]; + wc[*npolled].status = IB_WC_WR_FLUSH_ERR; + wc[*npolled].vendor_err = ROCE_CQE_SYNDROME_WR_FLUSH_ERR; + wc[*npolled].qp = &rqp->ibqp; + wq->tail++; + (*npolled)++; + } + +out: + return (*npolled >= num_entries); +} + +static int sw_recv_comp(struct roce3_qp *rqp, int num_entries, int *npolled, struct ib_wc *wc) +{ + struct roce3_wq *wq = &rqp->rq; + unsigned int cur = wq->head - wq->tail; + unsigned int i; + + if (cur == 0) { + goto out; + } + + for (i = 0; (i < cur) && (*npolled < num_entries); i++) { + wc[*npolled].wr_id = wq->wrid[wq->tail & (wq->wqebb_cnt - 1)]; + wc[*npolled].status = IB_WC_WR_FLUSH_ERR; + wc[*npolled].vendor_err = ROCE_CQE_SYNDROME_WR_FLUSH_ERR; + wc[*npolled].qp = &rqp->ibqp; + wq->tail++; + (*npolled)++; + } + +out: + return (*npolled >= num_entries); +} + +static int roce_poll_sw_comp(const struct roce3_cq *rcq, int num_entries, struct ib_wc *wc) +{ + struct roce3_qp *rqp = NULL; + int npolled = 0; + + list_for_each_entry(rqp, &rcq->send_qp_list, cq_send_list) + { + if (sw_send_comp(rqp, num_entries, &npolled, wc) != 0) { + return npolled; + } + } + + list_for_each_entry(rqp, &rcq->recv_qp_list, cq_recv_list) + { + if (sw_recv_comp(rqp, num_entries, &npolled, wc) != 0) { + return npolled; + } + } + + return npolled; +} + +/* the format of cq_ci DB:the bits of ci less than 24bit */ +void roce3_cq_set_ci(struct roce3_cq *cq) +{ + *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff); +} + +int roce3_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc) +{ + struct roce3_device *rdev = NULL; + struct roce3_cq *rcq = to_roce3_cq(ibcq); + struct roce3_qp *cur_qp = NULL; + unsigned long flags = 0; + int npolled = 0; + int ret = 0; + + spin_lock_irqsave(&rcq->lock, flags); + + rdev = to_roce3_dev(ibcq->device); + if (roce3_hca_is_present(rdev) == 0) { + npolled = roce_poll_sw_comp(rcq, num_entries, wc); + goto poll_out; + } + + for (npolled = 0; npolled < num_entries; ++npolled) { + ret = roce3_poll_one(rdev, rcq, &cur_qp, wc + npolled); + if (ret != 0) { + break; + } + } + + roce3_cq_set_ci(rcq); + +poll_out: + spin_unlock_irqrestore(&rcq->lock, flags); + + if ((ret == 0) || (ret == -EAGAIN)) { + return npolled; + } + + return ret; +} + +static void roce3_cq_arm(struct roce3_cq *cq, u32 cmd, void __iomem *uar_page) +{ + struct roce_db_cq_arm db_value; + + memset(&db_value, 0, sizeof(db_value)); + + db_value.dw0.bs.type = 3; + db_value.dw0.bs.cos = 0; /* arm_cq don't need cos */ + db_value.dw0.bs.cp = 1; /* 1 for cp */ + db_value.dw0.bs.non_filter = 1; + db_value.dw0.bs.cqc_type = 0; + db_value.dw0.bs.cqn = cq->cqn; + db_value.dw0.value = roce3_convert_be32(db_value.dw0.value); + + db_value.dw1.bs.cmd_sn = cq->arm_sn; + db_value.dw1.bs.cmd = cmd; + db_value.dw1.bs.ci = cq->cons_index; + db_value.dw1.value = roce3_convert_be32(db_value.dw1.value); + + /* + * Make sure that the doorbell record in host memory is + * written before ringing the doorbell via PCI MMIO. + */ + wmb(); + + roce3_write64((u32 *)(void *)&db_value, uar_page); +} + +int roce3_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) +{ + unsigned long lock_flags = 0; + struct roce3_cq *cq = to_roce3_cq(ibcq); + + spin_lock_irqsave(&cq->lock, lock_flags); + if (cq->arm_flag != 0) { + spin_unlock_irqrestore(&cq->lock, lock_flags); + return 0; + } + + cq->arm_flag = 1; + spin_unlock_irqrestore(&cq->lock, lock_flags); + + /* Only 64-bit is supported, 64-bit writes are atomic, no need to lock */ + roce3_cq_arm(to_roce3_cq(ibcq), + (((unsigned int)flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED) ? ROCE_CQ_DB_REQ_NOT_SOL : ROCE_CQ_DB_REQ_NOT, + to_roce3_dev(ibcq->device)->kernel_db_map); + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq_create.c b/drivers/infiniband/hw/hiroce3/cq/roce_cq_create.c new file mode 100644 index 000000000..f05942b5c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq_create.c @@ -0,0 +1,604 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq_create.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/2/21 + * Description : Define standard kernel RoCE CQ create realted functions. + */ + +#include "roce_cq.h" +#include "roce_pub_cmd.h" +#include "roce_cqm_cmd.h" +#include "roce_main_extension.h" + +/* **************************************************************************** + Prototype : roce_cq_attr_assign + Description : Assign value to CQC + Input : struct roce_cq_attr *cq_attr + struct roce3_cq *rcq + int eqn + int page_shift + Output : None + + 1.Date : 2019/10/13 + Modification : Created function + +**************************************************************************** */ +static void roce_cq_attr_assign(roce_verbs_cq_attr_s *cq_attr, struct roce3_cq *rcq, int eqn, int page_shift) +{ + /* Assign value to CQ */ + /* dw0 */ + cq_attr->dw0.bs.size = (u32)ROCE_ILOG2((unsigned)(rcq->ibcq.cqe + 1)); + cq_attr->dw0.bs.page_size = (u32)page_shift; + cq_attr->dw0.bs.cqe_size = + (u32)ROCE_ILOG2((unsigned)(rcq->buf.entry_size / 16)); /* entry_size=(2^cq_cqe_size)*16B. */ + cq_attr->dw0.bs.mtt_page_size = rcq->buf.mtt.mtt_page_shift - PAGE_SHIFT_4K; + cq_attr->dw0.bs.tss_timer_num = 7; /* 7 : The maximum number of timers supported by cq */ + cq_attr->dw0.bs.arm_timer_en = 0; + cq_attr->dw0.bs.timer_mode = 0; + cq_attr->dw0.bs.cnt_adjust_en = 1; + cq_attr->dw0.bs.cnt_clear_en = 1; + cq_attr->dw0.bs.ci_on_chip = 0; + cq_attr->dw0.value = cpu_to_be32(cq_attr->dw0.value); + + /* dw1 */ + cq_attr->dw1.bs.dma_attr_idx = 0; + cq_attr->dw1.bs.so_ro = 0; + cq_attr->dw1.bs.state = ROCE_CQ_STATE_VALID; + cq_attr->dw1.value = cpu_to_be32(cq_attr->dw1.value); + + /* dw2 */ + cq_attr->dw2.bs.idle_max_count = 0; + cq_attr->dw2.bs.cqecnt_lth = 6; /* update ci threshhold: 2^6=64 */ + cq_attr->dw2.bs.cqecnt_rctl_en = 0; + cq_attr->dw2.bs.ceqe_en = 1; + cq_attr->dw2.bs.arm_ceqe_en = 1; + cq_attr->dw2.bs.ceqn = (u8)eqn; + cq_attr->dw2.value = cpu_to_be32(cq_attr->dw2.value); + + /* dw3 */ + cq_attr->dw3.bs.timeout = 0; /* The timeout mechanism is disabled by default when CQ is created */ + cq_attr->dw3.bs.max_cnt = 0; /* The overtime mechanism is disabled by default when CQ is created */ + cq_attr->dw3.value = cpu_to_be32(cq_attr->dw3.value); + + /* dw4 - dw5 */ + cq_attr->cqc_l0mtt_gpa = rcq->buf.mtt.mtt_paddr; + cq_attr->cqc_l0mtt_gpa = cpu_to_be64(cq_attr->cqc_l0mtt_gpa); + + /* dw6 - dw7 */ + cq_attr->ci_record_gpa_at_hop_num = cpu_to_be64((rcq->db.dma & (~0x3uLL)) | rcq->buf.mtt.mtt_layers); + + return; +} + +static int roce3_cq_fill_create_inbuf(struct roce3_device *rdev, struct roce3_cq *rcq, int vector, int page_shift, + cqm_cmd_buf_s *cqm_cmd_inbuf) +{ + int eqn = 0; + roce_verbs_cq_attr_s *cq_attr = NULL; + roce_uni_cmd_creat_cq_s *cq_sw2hw_inbuf = NULL; + + cq_sw2hw_inbuf = (roce_uni_cmd_creat_cq_s *)cqm_cmd_inbuf->buf; + cq_sw2hw_inbuf->com.index = cpu_to_be32(rcq->cqn); + cq_sw2hw_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); //lint !e778 + cq_attr = &cq_sw2hw_inbuf->cq_attr; + + /* Get the EQN of the CEQ based on the Vector index */ + eqn = hinic3_vector_to_eqn(rdev->hwdev, SERVICE_T_ROCE, vector); + if (eqn < 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get eqn from hinic vector, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EINVAL; + } + + roce_cq_attr_assign(cq_attr, rcq, eqn, page_shift); + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_cq_sw2hw + Description : Send the cqc configuration command + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int vector + int page_shift + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_sw2hw(struct roce3_device *rdev, struct roce3_cq *rcq, int vector, int page_shift) +{ + int ret = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_uni_cmd_creat_cq_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + ret = roce3_cq_fill_create_inbuf(rdev, rcq, vector, page_shift, cqm_cmd_inbuf); + if (ret != 0) { + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return ret; + } + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_SW2HW_CQ, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send SW2HW_CQ command, ret(%d), func_id(%d)\n", + __func__, ret, rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(SW2HW_CQ), CQN(0x%x), func_id(%hu)\n", __func__, + rcq->cqn, rdev->glb_func_id); + + /* CMDq times out or CMDq does not work, update the device status, notify the PCIe module to reset + the device through OFED */ + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + ret = -1; + goto err_send_cmd; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + rcq->cons_index = 0; + rcq->arm_sn = 1; + rcq->arm_flag = 0; + rcq->vector = (u32)vector; + + return 0; + +err_send_cmd: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_create_cq_check + Description : roce3_create_cq_check + Input : struct ib_device *ibdev + int entries + int vector + struct ib_ucontext *ibcontext + struct ib_udata *udata + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_create_cq_check(struct ib_device *ibdev, int entries, int vector, const struct ib_ucontext *ibcontext, + const struct ib_udata *udata) +{ + struct roce3_device *rdev = NULL; + + if (ibdev == NULL) { + pr_err("[ROCE, ERR] %s: Ibdev is null\n", __func__); + return -EINVAL; + } + + if ((ibcontext != NULL) && (udata == NULL)) { + pr_err("[ROCE, ERR] %s: Udata is null ptr, but ibcontext is not null ptr\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibdev); + if ((entries < 1) || (entries > (int)rdev->rdma_cap.max_cqes)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Cqe number invalid, entries(%d), func_id(%d)\n", __func__, entries, + rdev->glb_func_id); + return -EINVAL; + } + + if (vector > (int)rdev->rdma_cap.num_comp_vectors) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Vector over range, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; + } + + return 0; +} + +static int roce3_check_cq_create_flags(u32 flags) +{ + /* + * It returns non-zero value for unsupported CQ + * create flags, otherwise it returns zero. + */ + return (int)(flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); /*lint !e40*/ +} + +static int roce3_cq_cqc_cfg(struct roce3_device *rdev, struct roce3_cq *rcq, int vector, struct ib_udata *udata) +{ + int ret = 0; + int page_shift = 0; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) + page_shift = rcq->umem->page_shift - PAGE_SHIFT_4K; +#endif + + /* configurate CQC */ + ret = roce3_cq_sw2hw(rdev, rcq, vector, page_shift); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to handle cq sw2hw, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + /* User mode requires outgoing CQN */ + if (ib_copy_to_udata(udata, &rcq->cqn, sizeof(u32)) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy data to user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + ret = -EFAULT; + return ret; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_create_user_cq + Description : roce3_create_user_cq + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + int vector + struct ib_ucontext *ibcontext + struct ib_udata *udata + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_create_user_cq(struct roce3_device *rdev, struct roce3_cq *rcq, int entries, int vector, + struct ib_ucontext *ibcontext, struct ib_udata *udata, u32 index) +{ + int ret = 0; + struct roce3_create_cq_cmd ucmd = { 0 }; + + rcq->cqm_cq = cqm_object_rdma_queue_create(rdev->hwdev, SERVICE_T_ROCE, CQM_OBJECT_RDMA_SCQ, 0, rcq, false, index); + if (rcq->cqm_cq == NULL) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed to create rdma queue from cqm object, func_id(%d), index(%d)\n", __func__, + rdev->glb_func_id, index); + return -ENOMEM; + } + + /* record CQN */ + rcq->cqn = rcq->cqm_cq->index; + + if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy from user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + ret = -EFAULT; + goto err_free_cqm_cq; + } + + /* Entries has been decreased by one when it was input by User Mode, and it is the expected value exactly + after increased by one by Kernel Mode */ +#if defined(OFED_MLNX_5_8) + ret = roce3_cq_get_umem(rdev, udata, &rcq->buf, &rcq->umem, ucmd.buf_addr, entries); +#else + ret = roce3_cq_get_umem(rdev, ibcontext, &rcq->buf, &rcq->umem, ucmd.buf_addr, entries); +#endif + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get umem, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_free_cqm_cq; + } + + ret = roce3_db_map_user(to_roce3_ucontext(ibcontext), (unsigned long)ucmd.db_addr, &rcq->db); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to map kernel_mem to user_mem, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_free_mtt; + } + + ret = roce3_cq_cqc_cfg(rdev, rcq, vector, udata); + if (ret != 0) { + goto err_unmap_db; + } + + return 0; + +err_unmap_db: + roce3_db_unmap_user(to_roce3_ucontext(ibcontext), &rcq->db); + +err_free_mtt: + roce3_cq_put_umem(rdev, &rcq->buf, &rcq->umem); + rcq->umem = NULL; + +err_free_cqm_cq: + hiudk_cqm_object_delete(rdev->hwdev, &rcq->cqm_cq->object); + + return ret; +} + +static void roce3_fill_rcq_info(struct roce3_cq *rcq) +{ + rcq->cqn = rcq->cqm_cq->index; + rcq->buf.buf = &rcq->cqm_cq->q_room_buf_1; + + /* Initialize buf to unused */ + roce3_cq_buf_init(&rcq->buf); + + /* Software DB assignment */ + rcq->set_ci_db = (__be32 *)(void *)(&rcq->cqm_cq->q_header_vaddr->doorbell_record); + *rcq->set_ci_db = 0; + rcq->db.db_record = (__be32 *)(void *)(&rcq->cqm_cq->q_header_vaddr->doorbell_record); + rcq->db.dma = rcq->cqm_cq->q_header_paddr; +} + +/* **************************************************************************** + Prototype : roce3_create_kernel_cq + Description : roce3_create_kernel_cq + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + int vector + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_create_kernel_cq(struct roce3_device *rdev, struct roce3_cq *rcq, int entries, int vector, u32 index) +{ + int ret = 0; + int page_shift = 0; + + rcq->buf.buf_size = entries * (int)rdev->rdma_cap.cqe_size; + rcq->cqm_cq = cqm_object_rdma_queue_create(rdev->hwdev, SERVICE_T_ROCE, CQM_OBJECT_RDMA_SCQ, (u32)rcq->buf.buf_size, + rcq, true, index); + if (rcq->cqm_cq == NULL) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed to create rdma_queue from cqm_object, func_id(%d), index(%d)\n", __func__, + rdev->glb_func_id, index); + return (-ENOMEM); + } + + /* Buffer is obtained from room1 when the queue is just created */ + if (rcq->cqm_cq->current_q_room != CQM_RDMA_Q_ROOM_1) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Not use CQM_RDMA_Q_ROOM_1, func_id(%d)\n", __func__, + rdev->glb_func_id); + ret = -EINVAL; + goto err_free_cqm_cq; + } + + roce3_fill_rcq_info(rcq); + + page_shift = ROCE_ILOG2(rcq->cqm_cq->q_room_buf_1.buf_size); + + /* allocate MTT */ + rcq->buf.mtt.mtt_type = MTT_CMTT_TYPE; + ret = hmm_rdma_mtt_alloc(rdev->hwdev, rcq->buf.buf->buf_number, (u32)page_shift, &rcq->buf.mtt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_free_cqm_cq; + } + + /* Write the PA of the CQ Buffer to the MTT */ + ret = roce3_buf_write_mtt(rdev, &rcq->buf.mtt, rcq->buf.buf); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write rdma mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_free_mtt; + } + + /*lint -e834*/ + page_shift = ROCE_ILOG2(rcq->cqm_cq->q_room_buf_1.buf_size) - PAGE_SHIFT_4K; + /*lint +e834*/ + + /* configurate CQC */ + ret = roce3_cq_sw2hw(rdev, rcq, vector, page_shift); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to configure CQC, func_id(%d)\n", __func__, rdev->glb_func_id); + goto err_free_mtt; + } + + return 0; + +err_free_mtt: + hmm_rdma_mtt_free(rdev->hwdev, &rcq->buf.mtt, SERVICE_T_ROCE); + +err_free_cqm_cq: + hiudk_cqm_object_delete(rdev->hwdev, &rcq->cqm_cq->object); + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_do_create_cq + Description : OFED_3_12 + Input : struct ib_device *ibdev + struct ib_ucontext *ibcontext + struct ib_ucontext *ibcontext + struct ib_udata *udata + struct roce3_cq *rcq + u32 index + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + 2.Date : 2015/8/10 + Modification : modify function + 3.Date : 2017/11/10 + Modification : modify function + +**************************************************************************** */ +static int roce3_do_create_cq(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_ucontext *ibcontext, struct ib_udata *udata, struct roce3_cq *rcq, u32 index) +{ + struct roce3_device *rdev = NULL; + int ret = 0; + int vector = attr->comp_vector; + int entries = (int)attr->cqe; + + /* The CQE queue should reserve a special CQE for resize cq */ + entries++; + entries = (int)(ROCE_ROUNDUP_POW_OF_TWO((u32)entries) & 0xffffffff); /*lint !e587*/ + + rdev = to_roce3_dev(ibdev); + /* Chip Constraints: Minimum queue depth needs to be page-aligned */ + if ((u32)((u32)entries * rdev->rdma_cap.cqe_size) < PAGE_SIZE) { + entries = (PAGE_SIZE >> (u32)ROCE_ILOG2(rdev->rdma_cap.cqe_size)); + } + + /* Check if max spec is exceeded */ + if (entries > ((int)rdev->rdma_cap.max_cqes + 1)) { + ret = (-EINVAL); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Over range after align, entries(%d), max_cqes(%d), func_id(%d)\n", + __func__, entries, rdev->rdma_cap.max_cqes + 1, rdev->glb_func_id); + return ret; + } + + rcq->ibcq.cqe = entries - 1; + mutex_init(&rcq->resize_mutex); + /*lint -e708*/ + spin_lock_init(&rcq->lock); + /*lint +e708*/ + rcq->resize_buf = NULL; + rcq->resize_umem = NULL; + rcq->buf.entry_size = (int)rdev->rdma_cap.cqe_size; + + INIT_LIST_HEAD(&rcq->send_qp_list); + INIT_LIST_HEAD(&rcq->recv_qp_list); + if (ibcontext) { + ret = roce3_create_user_cq(rdev, rcq, entries, vector, ibcontext, udata, index); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create user_cq, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + } else { + ret = roce3_create_kernel_cq(rdev, rcq, entries, vector, index); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to create kernel_cq, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + } + + rcq->reset_flow_comp = roce_reset_flow_comp; + + return 0; +} + +#if defined(OFED_MLNX_5_8) +int roce3_create_cq_common(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_udata *udata, struct roce3_cq *rcq, u32 index) +{ + int ret; + struct roce3_device *rdev = to_roce3_dev(ibdev); + struct roce3_ucontext *context = rdma_udata_to_drv_context( + udata, struct roce3_ucontext, ibucontext); + int vector = attr->comp_vector; + int entries = (int)attr->cqe; + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -EPERM; + } + + if (roce3_check_cq_create_flags(attr->flags) != 0) { + pr_err("[ROCE, ERR] %s: Not support the cq_create flag(%x)\n", __func__, attr->flags); + return -EOPNOTSUPP; + } + + ret = roce3_create_cq_check(ibdev, entries, vector, &context->ibucontext, udata); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to check cq information\n", __func__); + return ret; + } + + return roce3_do_create_cq(ibdev, attr, &context->ibucontext, udata, rcq, index); +} + +int roce3_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, struct ib_udata *udata) +{ + struct roce3_cq *rcq = to_roce3_cq(ibcq); + return roce3_create_cq_common(ibcq->device, attr, udata, rcq, ROCE_CQN_INVLD); +} +#else +struct ib_cq *roce3_create_cq_common(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_ucontext *ibcontext, struct ib_udata *udata, u32 index) +{ + int ret = 0; + struct roce3_cq *rcq = NULL; + int vector = attr->comp_vector; + int entries = (int)attr->cqe; + struct roce3_device *rdev = to_roce3_dev(ibdev); + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return ERR_PTR((long)-EPERM); + } + + if (roce3_check_cq_create_flags(attr->flags) != 0) { + pr_err("[ROCE, ERR] %s: Not support the cq_create flag(%x)\n", __func__, attr->flags); + return ERR_PTR((long)(-EOPNOTSUPP)); + } + + ret = roce3_create_cq_check(ibdev, entries, vector, ibcontext, udata); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to check cq information\n", __func__); + goto err_out; + } + + rcq = (struct roce3_cq *)kzalloc(sizeof(*rcq), GFP_KERNEL); + if (rcq == NULL) { + ret = -ENOMEM; + pr_err("[ROCE, ERR] %s: Failed to alloc rcq\n", __func__); + goto err_out; + } + + ret = roce3_do_create_cq(ibdev, attr, ibcontext, udata, rcq, index); + if (ret != 0) { + goto err_free_cq; + } + + return &rcq->ibcq; + +err_free_cq: + kfree(rcq); + +err_out: + return (struct ib_cq *)ERR_PTR((long)ret); +} + +/* **************************************************************************** + Prototype : roce3_create_cq + Description : OFED_3_12 + Input : struct ib_device *ibdev + struct ib_cq_init_attr *attr(flags for exp) + struct ib_ucontext *ibcontext + struct ib_udata *udata + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + 2.Date : 2015/8/10 + Modification : modify function + 3.Date : 2017/11/10 + Modification : modify function + 4.Date : 2021/1/7 + Modification : modified function + +**************************************************************************** */ +struct ib_cq *roce3_create_cq(struct ib_device *ibdev, const struct ib_cq_init_attr *attr, + struct ib_ucontext *ibcontext, struct ib_udata *udata) +{ + return roce3_create_cq_common(ibdev, attr, ibcontext, udata, ROCE_CQN_INVLD); +} +#endif + diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq_ctrl.c b/drivers/infiniband/hw/hiroce3/cq/roce_cq_ctrl.c new file mode 100644 index 000000000..60315e9e4 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq_ctrl.c @@ -0,0 +1,872 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq_ctrl.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/2/21 + * Description : Define standard kernel RoCE CQ control realted functions. + */ + +#include "roce_cq.h" +#include "roce_cqm_cmd.h" +#include "roce_pub_cmd.h" +#include "roce_main_extension.h" + +/* **************************************************************************** + Prototype : roce3_cq_modify + Description : Send the command of cq_modify + Input : struct roce3_device *rdev + struct roce3_cq *cq + u32 cnt + u32 period + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_modify(struct roce3_device *rdev, struct roce3_cq *cq, u32 cnt, u32 period) +{ + int ret = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_cmd_modify_cq_s *cq_modify_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_modify_cq_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + cq_modify_inbuf = (roce_cmd_modify_cq_s *)cqm_cmd_inbuf->buf; + cq_modify_inbuf->com.index = cpu_to_be32(cq->cqn); + cq_modify_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); //lint !e778 + cq_modify_inbuf->max_cnt = cpu_to_be32(cnt); + cq_modify_inbuf->timeout = cpu_to_be32(period); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_MODIFY_CQ, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to send MODIFY_CQ, cqn(0x%x), ret(%d), func_id(%hu)\n", __func__, + cq->cqn, ret, rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(MODIFY_CQ), cqn(0x%x), func_id(%hu)\n", __func__, + cq->cqn, rdev->glb_func_id); + + /* CMDq times out or CMDq does not work, update the device status, + notify the PCIe module to reset the device through OFED */ + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + /* CMDq may return a positive number, so its return value cannot be used directly */ + return -1; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return 0; +} + +/* **************************************************************************** + Prototype : roce3_modify_cq + Description : OFED_3_12 + Input : struct ib_cq *ibcq + u16 cq_count + u16 cq_period + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +int roce3_modify_cq(struct ib_cq *ibcq, u16 cq_count, u16 cq_period) +{ + int ret = 0; + struct roce3_cq *cq = NULL; + struct roce3_device *rdev = NULL; + + if (ibcq == NULL) { + pr_err("[ROCE, ERR] %s: Ibcq is null\n", __func__); + return -EINVAL; + } + + cq = to_roce3_cq(ibcq); + rdev = to_roce3_dev(ibcq->device); + + ret = roce3_cq_modify(rdev, cq, cq_count, cq_period); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify cq, func_id(%d)\n", __func__, rdev->glb_func_id); + return ret; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_cq_alloc_resize_buf + Description : Kernel mode applies for resize_buf, and its corresponding MTT + When there is an error in execution, this function ensures that all intermediate resources are released; + when the execution is successful, this function can confirm that all resources are acquired. + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_alloc_resize_buf(struct roce3_device *rdev, struct roce3_cq *rcq, int entries) +{ + int ret = 0; + int page_shift = 0; + + if (rcq->resize_buf) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Resize buffer is busy, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EBUSY; + } + + /* Apply for resize_buf and assign it */ + rcq->resize_buf = (struct roce3_cq_resize_buf *)kmalloc(sizeof(*rcq->resize_buf), GFP_ATOMIC); + if (rcq->resize_buf == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc resize buffer, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -ENOMEM; + } + + rcq->resize_buf->buf.entry_size = rcq->buf.entry_size; + rcq->resize_buf->buf.buf_size = entries * rcq->buf.entry_size; + ret = hiudk_cqm_object_resize_alloc_new(rdev->hwdev, &rcq->cqm_cq->object, (u32)rcq->resize_buf->buf.buf_size); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to resize cq buffer, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_resize_buf_alloc; + } + + /* If the application is successful, record the buffer information of the new buffer */ + rcq->resize_buf->cqe = entries - 1; + rcq->resize_buf->buf.buf = &rcq->cqm_cq->q_room_buf_2; + + /* Initialize new buf to unused state */ + roce3_cq_buf_init(&rcq->resize_buf->buf); + + page_shift = (int)ROCE_ILOG2(rcq->resize_buf->buf.buf->buf_size); + + /* Apply MTT for resize_buf */ + rcq->buf.mtt.mtt_type = MTT_CMTT_TYPE; + ret = hmm_rdma_mtt_alloc(rdev->hwdev, rcq->resize_buf->buf.buf->buf_number, + (u32)page_shift, &rcq->resize_buf->buf.mtt, SERVICE_T_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc rdma mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_mtt_alloc; + } + + /* configurate MTT, write PA of resize_buf to MTT */ + ret = roce3_buf_write_mtt(rdev, &rcq->resize_buf->buf.mtt, rcq->resize_buf->buf.buf); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to write rdma mtt, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto err_mtt_write; + } + + return 0; + +err_mtt_write: + hmm_rdma_mtt_free(rdev->hwdev, &rcq->buf.mtt, SERVICE_T_ROCE); + +err_mtt_alloc: + /* free resize_buf */ + hiudk_cqm_object_resize_free_new(rdev->hwdev, &rcq->cqm_cq->object); + +err_resize_buf_alloc: + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_cq_free_resize_buf + Description : Kernel Mode releases resize_buf and its corresponding MTT + Input : struct roce3_device *rdev + struct roce3_cq *rcq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_cq_free_resize_buf(struct roce3_device *rdev, struct roce3_cq *rcq) +{ + /* Release the MTT of resize_buf first */ + hmm_rdma_mtt_free(rdev->hwdev, &rcq->buf.mtt, SERVICE_T_ROCE); + + /* free resize_buf */ + hiudk_cqm_object_resize_free_new(rdev->hwdev, &rcq->cqm_cq->object); + + /* free the resize_buf pointer itself */ + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; +} + +/* **************************************************************************** + Prototype : roce3_cq_alloc_resize_umem + Description : User mode applies for umem of resize_buf, and MTT corresponding to user mode buf + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + struct ib_udata *udata + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_alloc_resize_umem(struct roce3_device *rdev, struct roce3_cq *rcq, int entries, + struct ib_udata *udata) +{ + int ret = 0; + struct roce3_resize_cq_cmd ucmd = { 0 }; + + /* If a resize is being executed, it is not allowed to execute another resize at the same time */ + if (rcq->resize_umem) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Resize_umem is busy, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EBUSY; + } + + if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy from user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EFAULT; + } + + rcq->resize_buf = (struct roce3_cq_resize_buf *)kmalloc(sizeof(*rcq->resize_buf), GFP_ATOMIC); + if (rcq->resize_buf == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cq resize buffer, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -ENOMEM; + } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) + ret = roce3_cq_get_umem(rdev, udata, &rcq->resize_buf->buf, &rcq->resize_umem, ucmd.buf_addr, entries); +#else + ret = roce3_cq_get_umem(rdev, rcq->umem->context, &rcq->resize_buf->buf, &rcq->resize_umem, ucmd.buf_addr, entries); +#endif + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get umem, func_id(%d)\n", __func__, rdev->glb_func_id); + + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; + + return ret; + } + + rcq->resize_buf->buf.entry_size = rcq->buf.entry_size; + rcq->resize_buf->buf.buf_size = entries * rcq->buf.entry_size; + rcq->resize_buf->cqe = entries - 1; + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_cq_free_resize_umem + Description : User mode applies for umem of resize_buf, and MTT corresponding to user mode buf + Input : struct roce3_device *rdev + struct roce3_cq *rcq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static void roce3_cq_free_resize_umem(struct roce3_device *rdev, struct roce3_cq *rcq) +{ + /* Free MTT and umem of resize_buf */ + roce3_cq_put_umem(rdev, &rcq->resize_buf->buf, &rcq->resize_umem); + rcq->resize_umem = NULL; + + /* free resize_buf itself */ + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; + + return; +} + +/* **************************************************************************** + Prototype : roce3_cq_get_outstanding_cqes + Description : roce3_cq_get_outstanding_cqes + Input : struct roce3_cq *cq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_get_outstanding_cqes(struct roce3_cq *cq) +{ + u32 i = 0; + + i = cq->cons_index; + while (roce3_get_sw_cqe(cq, i)) { + ++i; + } + + return (int)(i - cq->cons_index); +} + +static int roce3_cq_get_next_cqe(struct roce_cqe **cqe, struct roce3_cq *cq, unsigned int *i, u32 *times, + const struct roce_cqe *start_cqe) +{ + int ret = 0; + do { + *cqe = (struct roce_cqe *)roce3_get_sw_cqe(cq, ++(*i)); + if (*cqe == NULL) { + ROCE_MDELAY(MS_DELAY); + --(*times); + } + } while ((*cqe == NULL) && (*times != 0)); + + if ((*cqe == start_cqe) || (*cqe == NULL)) { + pr_err("[ROCE, ERR] %s: Failed to get resize CQE, CQN(0x%x)\n", __func__, cq->cqn); + return -ENOMEM; + } + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_cq_resize_copy_cqes + Description : roce3_cq_resize_copy_cqes + Input : struct roce3_cq *cq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_resize_copy_cqes(struct roce3_cq *cq) +{ + struct roce_cqe *cqe = NULL; + struct roce_cqe *new_cqe = NULL; + struct roce_cqe *start_cqe = NULL; + u32 times; + unsigned int i = 0; + int ret = 0; + + i = cq->cons_index; + + times = ROCE_CQ_RESIZE_POLL_TIMES; + do { + cqe = (struct roce_cqe *)roce3_get_sw_cqe(cq, i); + if (cqe == NULL) { + ROCE_MDELAY(MS_DELAY); + --times; + } + } while ((cqe == NULL) && (times != 0)); + + if (cqe == NULL) { + pr_err("[ROCE, ERR] %s: Failed to get resize CQE, CQN(0x%x)\n", __func__, cq->cqn); + return -ENOMEM; + } + + start_cqe = cqe; + + /* r_cqe:resize_cqe + CI + +--------+-----+-----+-----+----------+ + old_buf: | | CQE | CQE |R_CQE| | + +--------+-----+-----+-----+----------+ + | | + | | + +--------+-----+-----+-----+----------+ + new_buf: | | CQE | CQE | | | + +--------+-----+-----+-----+----------+ + */ + /* Convert the fields needed by CQE to little endian */ + cqe->dw0.value = roce3_convert_cpu32(cqe->dw0.value); + cqe->dw1.value = roce3_convert_cpu32(cqe->dw1.value); + while (cqe->dw1.bs.op_type != ROCE_OPCODE_RESIZE_CQE) { + /* The resized PI can be inherited, and the index of the original CQE remains unchanged in resize_buf */ + new_cqe = + (struct roce_cqe *)roce3_get_cqe_from_buf(&cq->resize_buf->buf, (i & ((unsigned)cq->resize_buf->cqe))); + + memcpy((void *)new_cqe, (void *)cqe, sizeof(struct roce_cqe)); + + /* If the CQE has been wrapped in resize_buf, the corresponding Owner bit needs to be modified + to be owned by the software. + * The rule is: when the owner bit is owned by CQE software, the O bit is opposite to the high bit of ci; + when the owner bit is owned by hardware, the O bit is the same as the high bit of CI. + */ + new_cqe->dw0.bs.owner = ((i & ((unsigned)cq->resize_buf->cqe + 1)) != 0) ? 1 : 0; + + /* After processing, turn the DW0/DW1 of CQE back to big endian */ + cqe->dw0.value = roce3_convert_be32(cqe->dw0.value); + cqe->dw1.value = roce3_convert_be32(cqe->dw1.value); + + /* Convert DW0/DW1 of the CQE in the new queue back to big endian */ + new_cqe->dw0.value = roce3_convert_be32(new_cqe->dw0.value); + new_cqe->dw1.value = roce3_convert_be32(new_cqe->dw1.value); + + /* Get the next CQE */ + ret = roce3_cq_get_next_cqe(&cqe, cq, &i, ×, start_cqe); + if (ret != 0) { + return ret; + } + + /* Convert DW0/DW1 of CQE to little endian */ + cqe->dw0.value = roce3_convert_cpu32(cqe->dw0.value); + cqe->dw1.value = roce3_convert_cpu32(cqe->dw1.value); + } + + return 0; +} + +static void roce3_cq_fill_resize_inbuf(struct roce3_device *rdev, struct roce3_cq *rcq, int page_shift, + cqm_cmd_buf_s *cqm_cmd_inbuf) +{ + struct rdma_service_cap *rdma_cap = NULL; + u32 cq_size = 0; + u32 mtt_layer = 0; + u64 mtt_paddr = 0; + u32 mtt_page_size = 0; + roce_cmd_resize_cq_s *cq_resize_inbuf = NULL; + + rdma_cap = &rdev->rdma_cap; + cq_size = (u32)rcq->resize_buf->cqe + 1; + cq_size = (u32)ROCE_ILOG2(cq_size); + mtt_layer = rcq->resize_buf->buf.mtt.mtt_layers; + mtt_paddr = rcq->resize_buf->buf.mtt.mtt_paddr; + mtt_page_size = rcq->resize_buf->buf.mtt.mtt_page_shift - PAGE_SHIFT_4K; + + cq_resize_inbuf = (roce_cmd_resize_cq_s *)cqm_cmd_inbuf->buf; + cq_resize_inbuf->com.index = cpu_to_be32(rcq->cqn); + cq_resize_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); //lint !e778 + cq_resize_inbuf->page_size = cpu_to_be32((u32)page_shift); + cq_resize_inbuf->log_cq_size = cpu_to_be32(cq_size); + cq_resize_inbuf->mtt_layer_num = cpu_to_be32(mtt_layer); + cq_resize_inbuf->mtt_base_addr = mtt_paddr; + cq_resize_inbuf->mtt_base_addr = cpu_to_be64(cq_resize_inbuf->mtt_base_addr); + cq_resize_inbuf->mtt_page_size = cpu_to_be32(mtt_page_size); + + cq_resize_inbuf->mtt_info.mtt_flags = 0; + cq_resize_inbuf->mtt_info.mtt_num = 0; + cq_resize_inbuf->mtt_info.mtt_cache_line_start = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_start); + cq_resize_inbuf->mtt_info.mtt_cache_line_end = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_end); + cq_resize_inbuf->mtt_info.mtt_cache_line_size = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_sz); +} + +/* **************************************************************************** + Prototype : roce3_cq_resize + Description : roce3_cq_resize + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int page_shift + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +static int roce3_cq_resize(struct roce3_device *rdev, struct roce3_cq *rcq, int page_shift) +{ + int ret = 0; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_resize_cq_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + roce3_cq_fill_resize_inbuf(rdev, rcq, page_shift, cqm_cmd_inbuf); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_RESIZE_CQ, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send RESIZE_CQ command, ret(%d), func_id(%d)\n", + __func__, ret, rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(RESIZE_CQ), cqn(0x%x), func_id(%hu)\n", __func__, + rcq->cqn, rdev->glb_func_id); + + /* When CMDq times out or CMDq cannot work, update the device status and notify the PCIe module to reset + the device through OFED */ + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + + ret = -1; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return ret; +} + +/* **************************************************************************** + Prototype : roce3_user_cq_resize + Description : roce3_user_cq_resize + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + struct ib_udata *udata + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_user_cq_resize(struct roce3_device *rdev, struct roce3_cq *rcq, int entries, struct ib_udata *udata) +{ + int page_shift = 0; + int ret = 0; + + /* Cannot exceed max size after power-of-2 alignment */ + if (entries > ((int)rdev->rdma_cap.max_cqes + 1)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Over range after align, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; + } + + ret = roce3_cq_alloc_resize_umem(rdev, rcq, entries, udata); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc resize_umem, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) && !defined(OFED_MLNX_5_8) + page_shift = rcq->resize_umem->page_shift - PAGE_SHIFT_4K; +#endif + + /* Send the cq_resize command to configure CQC. After the configuration is successful, the new CQE is written to + resize_buf, and the old buffer may still retain the old CQE. */ + ret = roce3_cq_resize(rdev, rcq, page_shift); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to resize cq, func_id(%d)\n", __func__, rdev->glb_func_id); + roce3_cq_free_resize_umem(rdev, rcq); + return ret; + } + + rcq->ibcq.cqe = rcq->resize_buf->cqe; + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_resize_user_cq + Description : roce3_resize_user_cq + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + struct ib_udata *udata + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_resize_user_cq(struct roce3_device *rdev, struct roce3_cq *rcq, int entries, struct ib_udata *udata) +{ + int ret = 0; + struct roce3_resize_cq_cmd ucmd = { 0 }; + int cqe_entries = entries; + + if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy from user space, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -EFAULT; + } + + if (ucmd.stage == 1) { + goto release_flow; + } + + mutex_lock(&rcq->resize_mutex); + + cqe_entries++; + cqe_entries = (int)(ROCE_ROUNDUP_POW_OF_TWO((u32)cqe_entries) & 0xffffffff); /*lint !e587*/ + // Minimum queue depth needs to be aligned by page + if ((u32)(cqe_entries * (int)rdev->rdma_cap.cqe_size) < PAGE_SIZE) { + cqe_entries = (int)(PAGE_SIZE >> (unsigned int)ROCE_ILOG2(rdev->rdma_cap.cqe_size)); + } + + /* The new depth of CQ cannot be the same as the old depth. A special CQE space is reserved when CQ is created, + so the value of ibcq->cqe is 1 smaller than the actual value */ + if (cqe_entries == (rcq->ibcq.cqe + 1)) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: No need to resize cq, func_id(%d)\n", __func__, rdev->glb_func_id); + ret = 0; + goto out; + } + + ret = roce3_user_cq_resize(rdev, rcq, cqe_entries, udata); + if (ret != 0) { + goto out; + } + + mutex_unlock(&rcq->resize_mutex); + + return 0; + +release_flow: + /* free old MTT */ + hmm_rdma_mtt_free(rdev->hwdev, &rcq->buf.mtt, SERVICE_T_ROCE); + + rcq->buf = rcq->resize_buf->buf; + ib_umem_release(rcq->umem); + rcq->umem = rcq->resize_umem; + + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; + rcq->resize_umem = NULL; + +out: + mutex_unlock(&rcq->resize_mutex); + + return ret; +} + +/* **************************************************************************** + Prototype : roce3_kernel_cq_resize + Description : roce3_kernel_cq_resize + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_kernel_cq_resize(struct roce3_device *rdev, struct roce3_cq *rcq, int entries) +{ + int outst_cqe = 0; + int page_shift = 0; + int ret = 0; + + /* Cannot exceed max size after power-of-2 alignment */ + if (entries > ((int)rdev->rdma_cap.max_cqes + 1)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Over range after align, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; + } + + /* The number of resized CQEs cannot be smaller than the number of outstanding CQEs */ + outst_cqe = roce3_cq_get_outstanding_cqes(rcq); + if (entries < (outst_cqe + 1)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Can't resize, \ + because smaller than the number of outstanding CQES, func_id(%d)\n", + __func__, rdev->glb_func_id); + return -EINVAL; + } + + ret = roce3_cq_alloc_resize_buf(rdev, rcq, entries); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc resize buffer, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + + /*lint -e834*/ + page_shift = ROCE_ILOG2(rcq->cqm_cq->q_room_buf_2.buf_size) - PAGE_SHIFT_4K; + /*lint +e834*/ + + /* Send the cq_resize command to configure CQC. After the configuration is successful, the new CQE is written to + resize_buf, and the old buffer may still retain the old CQE. */ + ret = roce3_cq_resize(rdev, rcq, page_shift); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to resize cq, func_id(%d)\n", __func__, rdev->glb_func_id); + roce3_cq_free_resize_buf(rdev, rcq); + return ret; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_resize_kernel_cq + Description : roce3_resize_kernel_cq + Input : struct roce3_device *rdev + struct roce3_cq *rcq + int entries + Output : None + + 1.Date : 2017/5/4 + Modification : Created function + +**************************************************************************** */ +static int roce3_resize_kernel_cq(struct roce3_device *rdev, struct roce3_cq *rcq, int entries) +{ + int ret = 0; + int tmp_cqe = 0; + int cqe_entries = entries; + + mutex_lock(&rcq->resize_mutex); + + cqe_entries++; + cqe_entries = (int)(ROCE_ROUNDUP_POW_OF_TWO((u32)cqe_entries) & 0xffffffff); /*lint !e587*/ + /* Minimum queue depth needs to be aligned by page */ + if ((u32)(cqe_entries * (int)rdev->rdma_cap.cqe_size) < PAGE_SIZE) { + cqe_entries = (PAGE_SIZE >> (unsigned int)ROCE_ILOG2(rdev->rdma_cap.cqe_size)); + } + + /* The new depth of CQ cannot be the same as the old depth. A special CQE space is reserved when CQ is created, + so the value of ibcq->cqe is 1 smaller than the actual value */ + if (cqe_entries == (rcq->ibcq.cqe + 1)) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: No need to resize cq, func_id(%d)\n", __func__, rdev->glb_func_id); + mutex_unlock(&rcq->resize_mutex); + return 0; + } + + ret = roce3_kernel_cq_resize(rdev, rcq, cqe_entries); + if (ret != 0) { + goto out; + } + + /* free old MTT */ + hmm_rdma_mtt_free(rdev->hwdev, &rcq->buf.mtt, SERVICE_T_ROCE); + + /* When copying CQE from the old buffer to resize_buf, the user may be polling cqe from the old buf, so + it needs to be locked.If CQE of the old buffer has been polled in the polling process, polling process will + free old buffer and switch to new buffer. + */ + spin_lock_irq(&rcq->lock); + + /* If the new buf has been switched to, nothing needs to be done */ + if (rcq->resize_buf) { + ret = roce3_cq_resize_copy_cqes(rcq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Have not polled resize cqe(fuc:%d, cqn:%u, ret:%d)\n", __func__, + rdev->glb_func_id, rcq->cqn, ret); + spin_unlock_irq(&rcq->lock); + mutex_unlock(&rcq->resize_mutex); + return ret; + } + tmp_cqe = rcq->ibcq.cqe; + rcq->buf = rcq->resize_buf->buf; + rcq->ibcq.cqe = rcq->resize_buf->cqe; + + kfree(rcq->resize_buf); + rcq->resize_buf = NULL; + } + + spin_unlock_irq(&rcq->lock); + + /* Non-0 means that the above resize_buf non-empty branch has been entered, the old buffer needs to be released */ + if (tmp_cqe != 0) { + hiudk_cqm_object_resize_free_old(rdev->hwdev, &rcq->cqm_cq->object); + } + +out: + mutex_unlock(&rcq->resize_mutex); + + return ret; +} + +static int roce3_resize_cq_check(struct ib_cq *ibcq, int entries, const struct ib_udata *udata) +{ + struct roce3_device *rdev = NULL; + + if (ibcq == NULL) { + pr_err("[ROCE, ERR] %s: Ibcq is null\n", __func__); + return -EINVAL; + } + + if ((ibcq->uobject != NULL) && (udata == NULL)) { + pr_err("[ROCE, ERR] %s: Udata is null, but uobject is not null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibcq->device); + if ((entries < 1) || (entries > (int)rdev->rdma_cap.max_cqes)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: resize CQEs invalid. entries(%d), func_id(%d)\n", __func__, entries, + rdev->glb_func_id); + return -EINVAL; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_resize_cq + Description : roce3_resize_cq + Input : struct ib_cq *ibcq + int entries + struct ib_udata *udata + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +int roce3_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) +{ + int ret = 0; + struct roce3_cq *rcq = NULL; + struct roce3_device *rdev = NULL; + + ret = roce3_resize_cq_check(ibcq, entries, udata); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: failed to check resize_cq\n", __func__); + return ret; + } + + rcq = to_roce3_cq(ibcq); + rdev = to_roce3_dev(ibcq->device); + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return fail), func_id(%hu)\n", __func__, + rdev->glb_func_id); + return -1; + } + + if (ibcq->uobject) { + ret = roce3_resize_user_cq(rdev, rcq, entries, udata); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to resize user cq, func_id(%u) ret(%d)\n", __func__, + (u32)rdev->glb_func_id, ret); + return ret; + } + } else { + ret = roce3_resize_kernel_cq(rdev, rcq, entries); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to resize kernel cq, func_id(%d)\n", __func__, + rdev->glb_func_id); + return ret; + } + } + + return 0; +} + +void roce3_lock_cqs(struct roce3_cq *roce3_send_cq, struct roce3_cq *roce3_recv_cq) __acquires(&roce3_send_cq->lock) + __acquires(&roce3_recv_cq->lock) +{ + if (roce3_send_cq == roce3_recv_cq) { + spin_lock_irq(&roce3_send_cq->lock); + __acquire(&roce3_recv_cq->lock); + } else if (roce3_send_cq->cqn < roce3_recv_cq->cqn) { + spin_lock_irq(&roce3_send_cq->lock); + spin_lock_nested(&roce3_recv_cq->lock, SINGLE_DEPTH_NESTING); + } else { + spin_lock_irq(&roce3_recv_cq->lock); + spin_lock_nested(&roce3_send_cq->lock, SINGLE_DEPTH_NESTING); + } +} + +void roce3_unlock_cqs(struct roce3_cq *roce3_send_cq, struct roce3_cq *roce3_recv_cq) __releases(&roce3_send_cq->lock) + __releases(&roce3_recv_cq->lock) +{ + if (roce3_send_cq == roce3_recv_cq) { + __release(&roce3_recv_cq->lock); + spin_unlock_irq(&roce3_send_cq->lock); + } else if (roce3_send_cq->cqn < roce3_recv_cq->cqn) { + spin_unlock(&roce3_recv_cq->lock); + spin_unlock_irq(&roce3_send_cq->lock); + } else { + spin_unlock(&roce3_send_cq->lock); + spin_unlock_irq(&roce3_recv_cq->lock); + } +} diff --git a/drivers/infiniband/hw/hiroce3/cq/roce_cq_destroy.c b/drivers/infiniband/hw/hiroce3/cq/roce_cq_destroy.c new file mode 100644 index 000000000..418159413 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/cq/roce_cq_destroy.c @@ -0,0 +1,298 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * File Name : roce_cq_destroy.c + * Version : v2.0 + * Created : 2021/12/7 + * Last Modified : 2022/2/21 + * Description : Define standard kernel RoCE CQ destroy realted functions. + */ + +#include <linux/slab.h> + +#include "hinic3_hw.h" + +#include "roce.h" +#include "roce_srq.h" +#include "roce_qp.h" +#include "roce_mix.h" +#include "roce_xrc.h" +#include "roce_cq.h" +#include "roce_cqm_cmd.h" +#include "roce_pub_cmd.h" +#include "hinic3_hmm.h" +#include "roce_main_extension.h" + +static int roce3_check_cqc_data_state(struct roce3_device *rdev, const struct roce3_cq *cq, + struct roce_cq_context *cqc_data, u32 check_state) +{ + int read_back_flag = 0; + int times = rdev->try_times; + struct roce_cq_context check_cqc_data; + + while ((times--) != 0) { + if (roce3_hca_is_present(rdev) == 0) { + return 0; + } + + check_cqc_data.dw2.value = be32_to_cpu(cqc_data->dw2.value); + if (check_cqc_data.dw2.bs.state == check_state) { + read_back_flag = 1; + break; + } + ROCE_UDELAY(US_PERF_DELAY); + } + + if (read_back_flag == 0) { + dev_err(rdev->hwdev_hdl, + "[ROCE, ERR] %s: Failed to read back after try %d times, CQ state(0x%x), func_id(%u)\n", __func__, + rdev->try_times, cqc_data->dw2.value, (u32)rdev->glb_func_id); + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Cqn(0x%x), timer_dw(0x%x), func_id(%u)\n", __func__, cq->cqn, + cqc_data->dw2.value, (u32)rdev->glb_func_id); + return -1; + } + + return 0; +} + +/* **************************************************************************** + Prototype : roce3_cq_hw2sw + Description : roce3_cq_hw2sw + Input : struct roce3_device *rdev + struct roce3_cq *cq + Output : None + + 1.Date : 2015/5/27 + Modification : Created function + +**************************************************************************** */ +int roce3_cq_hw2sw(struct roce3_device *rdev, struct roce3_cq *cq) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + struct roce_cq_context *cqc_data = NULL; + roce_cmd_cq_hw2sw_s *cq_hw2sw_inbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_cq_hw2sw_s), NULL, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + cq_hw2sw_inbuf = (roce_cmd_cq_hw2sw_s *)cqm_cmd_inbuf->buf; + cq_hw2sw_inbuf->com.index = cpu_to_be32((u32)cq->cqn); + cq_hw2sw_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); //lint !e778 + + cqc_data = (struct roce_cq_context *)((void *)cq->cqm_cq->q_ctx_vaddr); + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_HW2SW_CQ, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send HW2SW_CQ command, func_id(%u), cqn(0x%x), (ret:%d)\n", + __func__, (u32)rdev->glb_func_id, cq->cqn, ret); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(HW2SW_CQ), cqn(0x%x), func_id(%hu)\n", __func__, + cq->cqn, rdev->glb_func_id); + + /* When CMDq times out or CMDq cannot work, update the device status and notify the PCIe module to reset + the device through OFED */ + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + } + + /* CMDq may return a positive number, so its return value cannot be used directly */ + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return -1; + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + return roce3_check_cqc_data_state(rdev, cq, cqc_data, ROCE_CQ_TIME_OUT_CHECK_VALUE); +} + +static int roce3_cq_cache_out(struct roce3_device *rdev, struct roce3_cq *cq) +{ + int ret = 0; + struct rdma_service_cap *rdma_cap = NULL; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + roce_cmd_cq_cache_invalidate_s *cq_cache_invld_inbuf = NULL; + + /* Send the cache out command */ + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_cq_cache_invalidate_s), NULL, + 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc cqm_cmd_inoutbuf, func_id(%d), ret(%d)\n", __func__, + rdev->glb_func_id, ret); + return -ENOMEM; + } + + dev_dbg(rdev->hwdev_hdl, "[ROCE, INFO] %s: func_id(%d) cqn(%d)\n", __func__, rdev->glb_func_id, cq->cqn); + rdma_cap = &rdev->rdma_cap; + cq_cache_invld_inbuf = (roce_cmd_cq_cache_invalidate_s *)cqm_cmd_inbuf->buf; + cq_cache_invld_inbuf->com.index = cpu_to_be32((u32)cq->cqn); + cq_cache_invld_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); //lint !e778 + cq_cache_invld_inbuf->mtt_info.mtt_flags = 0; + cq_cache_invld_inbuf->mtt_info.mtt_num = 0; + cq_cache_invld_inbuf->mtt_info.mtt_cache_line_start = + cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_start); + cq_cache_invld_inbuf->mtt_info.mtt_cache_line_end = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_end); + cq_cache_invld_inbuf->mtt_info.mtt_cache_line_size = cpu_to_be32(rdma_cap->dev_rdma_cap.roce_own_cap.cmtt_cl_sz); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_MISC_CQ_CACHE_INVLD, cqm_cmd_inbuf, NULL, NULL, + ROCE_CMD_TIME_CLASS_A, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to send CQ_CACHE_INVLD command, ret(%d), func_id(%d)\n", + __func__, ret, rdev->glb_func_id); + + if (roce3_hca_is_present(rdev) != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA is present(CQ_CACHE_INVLD), cqn(0x%x), func_id(%hu)\n", __func__, + cq->cqn, rdev->glb_func_id); + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + /* When CMDq times out or CMDq cannot work, update the device status and notify the PCIe module to reset + the device through OFED */ + if ((ret == -ETIMEDOUT) || (ret == -EPERM)) { + rdev->dev_status_to_ofed = ROCE_DEV_STATUS_CMDQ_TIMEOUT; + } + return -1; + } + } + + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, NULL); + + return 0; +} + + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || defined(OFED_MLNX_5_8) +static void destroy_cq_user(struct roce3_cq *cq, struct ib_udata *udata) +{ + struct roce3_ucontext *context = rdma_udata_to_drv_context( + udata, struct roce3_ucontext, ibucontext); + + roce3_db_unmap_user(context, &cq->db); + ib_umem_release(cq->umem); +} + +int roce3_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata) +{ + int ret = 0; + struct roce3_device *rdev = NULL; + struct roce3_cq *cq = NULL; + struct roce_cq_context *cqc_data = NULL; + + if (ibcq == NULL) { + pr_err("[ROCE, ERR] %s: Ibcq is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibcq->device); + cq = to_roce3_cq(ibcq); + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return ok), func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_roce_cq_free; + } + + /* Modify CQC to be owned by the software */ + ret = roce3_cq_hw2sw(rdev, cq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify CQC, ret(%d), func_id(%hu), cqn(0x%x)\n", + __func__, ret, rdev->glb_func_id, cq->cqn); + return ret; + } + + /* Send the cache out command */ + ret = roce3_cq_cache_out(rdev, cq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to modify cqc, ret(%d), func_id(%hu)\n", __func__, ret, + rdev->glb_func_id); + return ret; + } + + cqc_data = (struct roce_cq_context *)((void *)cq->cqm_cq->q_ctx_vaddr); + ret = roce3_check_cqc_data_state(rdev, cq, cqc_data, ROCE_CQ_STATE_CHECK_VALUE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: check cqc data state fail, func_id(%hu)\n", __func__, rdev->glb_func_id); + return ret; + } + +err_roce_cq_free: + /* Release the MTT corresponding to cq_buf */ + hmm_rdma_mtt_free(rdev->hwdev, &cq->buf.mtt, SERVICE_T_ROCE); + + /* Call the CQM interface to release CQN and CQC. Since there is no cq_buf and software DB in user mode, + it does not need to be released; since kernel mode has both, it needs to be released */ + hiudk_cqm_object_delete(rdev->hwdev, &cq->cqm_cq->object); + + /* If it is user mode, you also need to cancel the mapping of the corresponding software DB */ + if (ibcq->uobject) { + destroy_cq_user(cq, udata); + } + + return 0; +} +#else +int roce3_destroy_cq(struct ib_cq *ibcq) +{ + int ret = 0; + struct roce3_device *rdev = NULL; + struct roce3_cq *cq = NULL; + struct roce_cq_context *cqc_data = NULL; + + if (ibcq == NULL) { + pr_err("[ROCE, ERR] %s: Ibcq is null\n", __func__); + return -EINVAL; + } + + rdev = to_roce3_dev(ibcq->device); + cq = to_roce3_cq(ibcq); + + if (roce3_hca_is_present(rdev) == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: HCA not present(return ok), func_id(%hu)\n", __func__, rdev->glb_func_id); + goto err_roce_cq_free; + } + + /* Modify CQC to be owned by the software */ + ret = roce3_cq_hw2sw(rdev, cq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to modify CQC, ret(%d), func_id(%d), cqn(0x%x)\n", + __func__, ret, rdev->glb_func_id, cq->cqn); + return ret; + } + + /* Send the cache out command */ + ret = roce3_cq_cache_out(rdev, cq); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to modify cqc, ret(%d), func_id(%hu)\n", __func__, ret, + rdev->glb_func_id); + return ret; + } + + cqc_data = (struct roce_cq_context *)((void *)cq->cqm_cq->q_ctx_vaddr); + ret = roce3_check_cqc_data_state(rdev, cq, cqc_data, ROCE_CQ_STATE_CHECK_VALUE); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: check cqc data state fail, func_id(%hu)\n", __func__, rdev->glb_func_id); + return ret; + } + +err_roce_cq_free: + /* Release the MTT corresponding to cq_buf */ + hmm_rdma_mtt_free(rdev->hwdev, &cq->buf.mtt, SERVICE_T_ROCE); + + /* Call the CQM interface to release CQN and CQC. Since there is no cq_buf and software DB in user mode, + it does not need to be released; since kernel mode has both, it needs to be released */ + hiudk_cqm_object_delete(rdev->hwdev, &cq->cqm_cq->object); + + /* If it is user mode, you also need to cancel the mapping of the corresponding software DB */ + if (ibcq->uobject) { + roce3_db_unmap_user(to_roce3_ucontext(ibcq->uobject->context), &cq->db); + ib_umem_release(cq->umem); + } + + kfree(cq); + + return 0; +} +#endif diff --git a/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.c b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.c new file mode 100644 index 000000000..8afffe554 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.c @@ -0,0 +1,126 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * + * File Name : roce_dfx.c + * Version : v2.1 + * Created : 2020/8/29 + * Last Modified : 2021/10/16 + * Description : The definition of callback functions and internal functions of RoCE driver dfx features. + */ + +#ifdef __ROCE_DFX__ + +#include <linux/fs.h> +#include <linux/slab.h> + +#include "hinic3_mt.h" + +#include "roce.h" +#include "roce_cmd.h" +#include "roce_pub_cmd.h" +#include "roce_dfx.h" + + +void roce3_dfx_clean_up(struct roce3_device *rdev) +{ +#ifdef ROCE_PKT_CAP_EN + (void)roce3_dfx_stop_cap_pkt(rdev, NULL, NULL); +#endif +} + +int roce3_get_drv_version(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + struct drv_version_info *ver_info = buf_out; + int rc; + + if (!buf_out) { + pr_err("Buf_out is NULL.\n"); + return -EINVAL; + } + + if (*out_size != sizeof(*ver_info)) { + pr_err("Unexpect out buf size from user :%u, expect: %lu\n", *out_size, sizeof(*ver_info)); + return -EINVAL; + } + + rc = snprintf(ver_info->ver, sizeof(ver_info->ver), "%s %s", + HIROCE3_DRV_VERSION, __TIME_STR__); + if (rc == -1) { + pr_err("Snprintf roce version err\n"); + return -EFAULT; + } + + return 0; +} + +static int roce3_dfx_enable_bw_ctrl(struct roce3_device *rdev, struct roce3_bw_ctrl_inbuf *inbuf, + struct roce3_bw_ctrl_outbuf *outbuf) +{ + if (rdev->hw_info.hca_type == ROCE3_2_100G_HCA) { + inbuf->ctrl_param.cir = ROCE3_100G_CIR; + inbuf->ctrl_param.pir = ROCE3_100G_PIR; + inbuf->ctrl_param.cnp = ROCE3_100G_CNP; + } else { + inbuf->ctrl_param.cir = ROCE3_25G_CIR; + inbuf->ctrl_param.pir = ROCE3_25G_PIR; + inbuf->ctrl_param.cnp = ROCE3_25G_CNP; + } + return roce3_set_bw_ctrl_state(rdev, ROCE_BW_CTRL_EN, inbuf); +} + +static int roce3_dfx_disable_bw_ctrl(struct roce3_device *rdev, struct roce3_bw_ctrl_inbuf *inbuf, + struct roce3_bw_ctrl_outbuf *outbuf) +{ + inbuf->ctrl_param.cir = 0; + inbuf->ctrl_param.pir = 0; + inbuf->ctrl_param.cnp = 0; + return roce3_set_bw_ctrl_state(rdev, ROCE_BW_CTRL_DIS, inbuf); +} + +static int roce3_dfx_change_bw_ctrl_param(struct roce3_device *rdev, struct roce3_bw_ctrl_inbuf *inbuf, + struct roce3_bw_ctrl_outbuf *outbuf) +{ + return roce3_set_bw_ctrl_state(rdev, ROCE_BW_CTRL_RESET, inbuf); +} + +static int roce3_dfx_query_bw_ctrl_param(struct roce3_device *rdev, struct roce3_bw_ctrl_inbuf *inbuf, + struct roce3_bw_ctrl_outbuf *outbuf) +{ + return roce3_query_bw_ctrl_state(rdev, &outbuf->bw_ctrl_param); +} + +typedef int (*roce3_adm_dfx_bw_ctrl_func_t)(struct roce3_device *rdev, struct roce3_bw_ctrl_inbuf *inbuf, + struct roce3_bw_ctrl_outbuf *outbuf); + +/*lint -e26*/ +static roce3_adm_dfx_bw_ctrl_func_t g_roce3_adm_dfx_bw_ctrl_funcs[COMMON_CMD_VM_COMPAT_TEST] = { + [ROCE_CMD_ENABLE_BW_CTRL] = roce3_dfx_enable_bw_ctrl, + [ROCE_CMD_DISABLE_BW_CTRL] = roce3_dfx_disable_bw_ctrl, + [ROCE_CMD_CHANGE_BW_CTRL_PARAM] = roce3_dfx_change_bw_ctrl_param, + [ROCE_CMD_QUERY_BW_CTRL_PARAM] = roce3_dfx_query_bw_ctrl_param, +}; +/*lint +e26*/ + +int roce3_adm_dfx_bw_ctrl(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + struct roce3_bw_ctrl_inbuf *inbuf = (struct roce3_bw_ctrl_inbuf *)buf_in; + struct roce3_bw_ctrl_outbuf *outbuf = (struct roce3_bw_ctrl_outbuf *)buf_out; + roce3_adm_dfx_bw_ctrl_func_t roce3_adm_dfx_bw_ctrl_func; + + memset(buf_out, 0, sizeof(struct roce3_bw_ctrl_outbuf)); + *out_size = sizeof(struct roce3_bw_ctrl_outbuf); + + if (inbuf->cmd_type >= COMMON_CMD_VM_COMPAT_TEST) { + dev_err(rdev->hwdev_hdl, "Not support this type(%d)\n", inbuf->cmd_type); + return -EINVAL; + } + + roce3_adm_dfx_bw_ctrl_func = g_roce3_adm_dfx_bw_ctrl_funcs[inbuf->cmd_type]; + if (roce3_adm_dfx_bw_ctrl_func == NULL) { + dev_err(rdev->hwdev_hdl, "Not support this type(%d)\n", inbuf->cmd_type); + return -EINVAL; + } + + return roce3_adm_dfx_bw_ctrl_func(rdev, inbuf, outbuf); +} +#endif /* __ROCE_DFX__ */ diff --git a/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.h b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.h new file mode 100644 index 000000000..86f099002 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * + * File Name : roce_dfx.h + * Version : v2.1 + * Created : 2020/8/29 + * Last Modified : 2021/10/16 + * Description : The definition of macros, data structure, function prototype etc of RoCE driver dfx features. + */ + +#ifndef ROCE_DFX_H +#define ROCE_DFX_H + +#include <linux/types.h> + +#include "hinic3_rdma.h" + +#include "roce_sysfs.h" +#include "roce.h" +#include "roce_verbs_cmd.h" +#include "rdma_context_format.h" + +#ifdef ROCE_PKT_CAP_EN +#include "roce_dfx_cap.h" +#endif + +#define MR_KEY_2_INDEX_SHIFT 8 + +#define ROCE_IO_DFX_CFG_VADDR_ID 0 +#define ROCE_IO_DFX_CFG_PADDR_ID 1 +#define ROCE_IO_DFX_CFG_ADDR_NUM 2 + +struct roce3_mpt_query_outbuf { + struct roce_mpt_context mpt_entry; +}; + +#define roce3_dfx_print(fmt, args...) \ + do { \ + (void)printk("[roce3_dfx] : " fmt "\n", ##args); \ + } while (0) + +struct roce3_dfx_query_inbuf { + u32 cmd_type; + /*lint -e658*/ + union { + u32 qpn; + u32 cqn; + u32 srqn; + u32 mpt_key; + u32 gid_index; + struct { + u32 qpn; + u32 cqn; + } query_pi_ci; + }; + /*lint +e658*/ +}; + +struct roce3_dfx_pi_ci { + u32 qpc_sq_pi_on_chip; + u32 qpc_sq_pi; + u32 qpc_sq_load_pi; + u32 qpc_rq_pi_on_chip; + u32 qpc_rq_load_pi; + u32 qpc_rq_pi; + u32 qpc_rc_pi; + u32 qpc_sq_ci; + u32 qpc_sq_wqe_prefetch_ci; + u32 qpc_sq_mtt_prefetch_wqe_ci; + u32 qpc_sqa_ci; + u32 qpc_sqa_wqe_prefetch_ci; + u32 qpc_rq_ci; + u32 qpc_rq_wqe_prefetch_ci; + u32 qpc_rq_mtt_prefetch_wqe_ci; + u32 qpc_rq_base_ci; + u32 qpc_rc_ci; + u32 qpc_rc_prefetch_ci; + u32 cq_ci_on_chip; + u32 cq_ci; + u32 cq_load_ci; + u64 cq_ci_record_gpa_at_hop_num; + u32 cq_last_solicited_pi; + u32 cq_pi; + u32 cq_last_notified_pi; +}; + +struct roce3_dfx_qp_count { + u32 qp_alloced; + u32 qp_deleted; + u32 qp_alive; +}; + +union roce3_dfx_query_outbuf { + struct roce_qp_context qp_ctx; + struct roce_cq_context cq_ctx; + struct roce_srq_context srq_ctx; + struct roce_mpt_context mpt; + struct rdma_gid_entry gid_entry; + struct roce3_dfx_pi_ci pi_ci; + struct roce3_dfx_qp_count qp_count; + u32 algo_type; +}; + +enum roce3_bw_ctrl_cmd_e { + ROCE_BW_CTRL_DIS, + ROCE_BW_CTRL_EN, + ROCE_BW_CTRL_RESET +}; +struct rdma_gid_query_outbuf { + struct rdma_gid_entry gid_entry; +}; + +struct roce3_bw_ctrl_inbuf { + u32 cmd_type; + struct { + u32 cir; + u32 pir; + u32 cnp; + } ctrl_param; +}; + +struct roce3_bw_ctrl_param { + u8 color_type; + u16 ptype; + u8 hw_wred_mode; + + u32 cir; + u32 pir; + u32 cbs; + u32 xbs; + u32 cnp; + u32 enable; +}; + +struct roce3_bw_ctrl_outbuf { + struct roce3_bw_ctrl_param bw_ctrl_param; +}; + +enum roce3_dfx_io_cmd_type { + ROCE_IO_CTRL_DIS, + ROCE_IO_CTRL_EN +}; + +struct roce3_dfx_io_alarm { + enum roce3_dfx_io_cmd_type en_flag; + u16 pf_id; + u16 rsvd; + u16 io_latency_thd; + u16 exec_time; + u32 exp_qpn; + void *rcd_uaddr; + struct timespec64 start; + struct mutex io_alarm_mutex; +}; + +struct roce3_dfx_io_inbuf { + u32 cmd_type; + struct roce3_dfx_io_alarm io_alarm; +}; + +struct roce3_dfx_io_outbuf { + struct roce3_dfx_io_alarm io_alarm; +}; + +int roce3_get_drv_version(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size); +int roce3_adm_dfx_query(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size); +int roce3_adm_dfx_bw_ctrl(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size); +void roce3_dfx_clean_up(struct roce3_device *rdev); + +void *global_roce3_io_alarm_va_get(void); + +void global_roce3_io_alarm_va_set(u64 va); + +void global_roce3_io_alarm_pa_set(dma_addr_t pa); + +dma_addr_t global_roce3_io_alarm_pa_get(void); + +int roce3_dfx_cmd_query_qp(struct roce3_device *rdev, u32 qpn, struct roce_qp_context *qp_ctx); + +int roce3_dfx_cmd_query_cq(struct roce3_device *rdev, u32 cqn, struct roce_cq_context *cq_ctx); + +int roce3_dfx_cmd_query_srq(struct roce3_device *rdev, u32 srqn, struct roce_srq_context *srq_ctx); + +#endif // __ROCE_DFX_H__ diff --git a/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.c b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.c new file mode 100644 index 000000000..c511a4dfd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.c @@ -0,0 +1,676 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022-2022. All rights reserved. + * + * File Name : roce_dfx_cap.c + * Version : v2.1 + * Created : 2022/7/28 + * Last Modified : 2022/7/28 + * Description : The definition of callback functions and internal functions of RoCE driver dfx cap features. + */ + +#ifdef ROCE_PKT_CAP_EN + +#include <linux/mutex.h> +#include <linux/kthread.h> +#include <linux/dma-mapping.h> +#include <linux/pci.h> +#include <linux/vmalloc.h> +#include <linux/etherdevice.h> +#include <rdma/ib_verbs.h> + +#include "hinic3_hw.h" + +#include "roce.h" +#include "roce_cmd.h" +#include "roce_pub_cmd.h" +#include "roce_dfx.h" +#include "roce_dfx_cap.h" +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +static struct roce3_cap_block_num_attr g_nattr[8] = { + { .block_num_idx = 0, .shift = 4, .num = 16 }, + { .block_num_idx = 1, .shift = 5, .num = 32 }, + { .block_num_idx = 2, .shift = 6, .num = 64 }, + { .block_num_idx = 3, .shift = 7, .num = 128 }, + { .block_num_idx = 4, .shift = 8, .num = 256 }, + { .block_num_idx = 5, .shift = 9, .num = 512 }, + { .block_num_idx = 6, .shift = 10, .num = 1024 }, + { .block_num_idx = 7, .shift = 11, .num = 2048 }, +}; + +struct roce3_pkt_cap_info g_roce3_cap_info = { + .cap_status = ROCE_CAPTURE_STOP, + .cap_mode = 1, + .poll_ci = 0, + .rdev = NULL, + .func_id = 0, + // Configurable, currently using 4, when modifying, the size of cfg bl needs to be modified synchronously + .block_num_idx = 4, + .mode = 0, + .qp_list_cnt = 0, + .qp_list_head = LIST_HEAD_INIT(g_roce3_cap_info.qp_list_head), +}; + +static void roce3_stop_thread(struct sdk_thread_info *thread_info) +{ + if (thread_info->thread_obj) { + (void)kthread_stop(thread_info->thread_obj); + thread_info->thread_obj = NULL; + } +} + +static int roce3_linux_thread_func(void *thread) +{ + struct sdk_thread_info *info = (struct sdk_thread_info *)thread; + + while (!kthread_should_stop()) { + info->thread_fn(info->data); + + // Warning: kernel thread should reschedule + schedule(); + } + + return 0; +} +#ifdef ROCE_BONDING_EN +static struct net_device *roce3_get_roce_bond_ndev(struct roce3_device *rdev) +{ + struct bonding *bond = NULL; + struct slave *slave = NULL; + struct net_device *netdev = rdev->ndev; + + if (netif_is_lag_master(netdev)) { + bond = netdev_priv(netdev); + } else if (netif_is_bond_slave(netdev)) { + rcu_read_lock(); + slave = bond_slave_get_rcu(netdev); + rcu_read_unlock(); + if (slave) { + bond = bond_get_bond_by_slave(slave); + } + } + + if ((bond == NULL) || (bond->dev == NULL)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Bond/bond->dev is NULL\n", __func__); + return NULL; + } + + return bond->dev; +} +#endif +static void roce3_netif_skb_info(struct roce3_device *rdev, const char *pkt, u8 len) +{ + struct sk_buff *skb = NULL; + unsigned char *packet = NULL; + struct net_device *netdev = rdev->ndev; +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + netdev = roce3_get_roce_bond_ndev(rdev); + if (netdev == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get roce_bond ndev\n", __func__); + return; + } + } +#endif + /* alloc skb and set skb->dev */ + skb = netdev_alloc_skb_ip_align(netdev, CAP_NUM_PER_BLOCK + 1); + if (unlikely(skb == NULL)) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to alloc skb\n", __func__); + return; + } + + skb_reserve(skb, CAP_COUNTER_TWO); + + /* put space for pkt */ + packet = (unsigned char *)skb_put(skb, len); + if (packet == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to get packet\n", __func__); + kfree_skb(skb); + return; + } + + /* copy pkt hdr */ + memcpy(packet, pkt, len); + + prefetchw(skb->data); + + /* resolve protocol and type */ + skb->protocol = eth_type_trans(skb, netdev); + + /* force to host */ + skb->pkt_type = 0; + + netif_receive_skb(skb); +} + +static int roce3_set_cap_func_disable(struct roce3_device *rdev) +{ + int ret; + + ret = hinic3_set_func_capture_en(rdev->hwdev, rdev->glb_func_id, 0); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set capture disable, ret(%d)\n", __func__, ret); + return ret; + } + + return 0; +} + +static int roce3_create_thread(struct sdk_thread_info *thread_info) +{ + thread_info->thread_obj = kthread_run(roce3_linux_thread_func, thread_info, thread_info->name); + if (!thread_info->thread_obj) { + pr_err("[ROCE, ERR] %s: Failed to create thread\n", __func__); + return (-EFAULT); + } + + return 0; +} + +static int roce3_set_cap_func_en(struct roce3_device *rdev) +{ + int ret; + + ret = hinic3_set_func_capture_en(rdev->hwdev, rdev->glb_func_id, 1); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set capture func enable, ret(%d)\n", __func__, ret); + return ret; + } + + return 0; +} + +static int roce3_pkt_cap_poll_check(struct roce3_device *rdev) +{ + if (rdev == NULL) { + pr_err("[ROCE] %s: Rdev is null\n", __func__); + return (-EINVAL); + } + + if (rdev->hwdev == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Rdev->hwdev is null\n", __func__); + return (-EINVAL); + } + + if (g_roce3_cap_info.cap_status == ROCE_CAPTURE_STOP) { + /* Don't add log here */ + return (-EINVAL); + } + + return 0; +} + +static int roce3_cap_hdr_vld(const roce3_cap_hdr_u *cap_hdr) +{ + return (cap_hdr->value != 0); +} + +static void roce3_fill_cap_cfg(struct roce3_dfx_cap_cfg_tbl *cfg_info, u32 state, u32 ci_index, u8 mode) +{ + cfg_info->ci_index = ci_index; + + cfg_info->dw1.bs.cap_block_num_shift = (u8)g_nattr[g_roce3_cap_info.block_num_idx].shift; // 8 + cfg_info->dw1.bs.cap_mode = (u8)g_roce3_cap_info.cap_mode; + cfg_info->dw1.bs.qp_mode = mode; + + cfg_info->dw2.bs.state = state; + cfg_info->dw2.bs.cap_func = g_roce3_cap_info.func_id; + + cfg_info->maxnum = g_nattr[g_roce3_cap_info.block_num_idx].num * CAP_NUM_PER_BLOCK; +} + +static void roce3_pkt_cap_poll_hdr(struct roce3_pkt_cap_info *cap_info, union roce3_cap_hdr **cap_hdr, + union roce3_cap_hdr *hdr_value) +{ + u32 lt_index; + u32 lt_offset; + u8 sel; + u32 block_num_per_entry = g_nattr[g_roce3_cap_info.block_num_idx].num; + u32 block_num_shift = g_nattr[g_roce3_cap_info.block_num_idx].shift; + + /* resolve index and offset */ + lt_index = (((cap_info->poll_ci) / block_num_per_entry) % CAP_PA_TBL_ENTRY_NUM); + lt_offset = ((cap_info->poll_ci) % (block_num_per_entry >> 1)); + sel = ((cap_info->poll_ci >> (block_num_shift - 1)) & 0x1); + + *cap_hdr = (roce3_cap_hdr_u *)(cap_info->que_addr[sel][0][lt_index] + (lt_offset * CAP_PKT_ITEM_SIZE)); + + hdr_value->value = (*cap_hdr)->value; + /* First, execute big endian and small endian switch operation for ctrl information */ + hdr_value->value = ntohl(hdr_value->value); +} + +static void roce3_pkt_cap_poll(void *data) +{ + int ret; + u32 count = 0; + struct roce3_dfx_cap_cfg_tbl cfg_info = { 0 }; + union roce3_cap_hdr hdr_value = { { 0 } }; + struct roce3_pkt_cap_info *cap_info = (struct roce3_pkt_cap_info *)data; + struct roce3_device *rdev = cap_info->rdev; + union roce3_cap_hdr *cap_hdr = NULL; + + if (roce3_pkt_cap_poll_check(rdev) != 0) { + return; + } + + roce3_pkt_cap_poll_hdr(cap_info, &cap_hdr, &hdr_value); + + if (roce3_cap_hdr_vld(&hdr_value) == 0) { + return; + } + + do { + if (g_roce3_cap_info.cap_status == ROCE_CAPTURE_STOP) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Cap is stopped\n", __func__); + return; + } + + roce3_netif_skb_info(rdev, ((u8 *)cap_hdr + CAP_HDR_OFFSET + hdr_value.cap_ctrl_info.pad), CAP_SKB_LEN); + + /* reset to 0 */ + cap_hdr->value = 0; + cap_info->poll_ci++; + + if (g_roce3_cap_info.cap_mode != 0) { + count++; + if (count >= (FILL_CAP_CFG_PKT_NUM)) { + roce3_fill_cap_cfg(&cfg_info, 0, cap_info->poll_ci, 0); + + (void)roce3_set_cap_cfg(rdev->hwdev, CAP_PA_TBL_ENTRY_NUM, (u32 *)&cfg_info); + + count = 0; + } + } + + roce3_pkt_cap_poll_hdr(cap_info, &cap_hdr, &hdr_value); + + if (unlikely(kthread_should_stop())) { + break; + } + + schedule(); + } while (roce3_cap_hdr_vld(&hdr_value) != 0); + + roce3_fill_cap_cfg(&cfg_info, 0, cap_info->poll_ci, 0); + + ret = roce3_set_cap_cfg(rdev->hwdev, CAP_PA_TBL_ENTRY_NUM, (u32 *)&cfg_info); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set cap cfg, ret(%d)\n", __func__, ret); + return; + } +} + +static int roce3_dfx_dma_alloc_addr(struct roce3_device *rdev, int cap_index, int que_index, + struct roce3_dfx_cap_tbl *pa_info) +{ + u64 v_addr; + u64 p_addr = 0; + + v_addr = (uintptr_t)(u64 *)dma_alloc_coherent(&rdev->pdev->dev, + (unsigned long)(CAP_PKT_ITEM_SIZE * ((g_nattr[g_roce3_cap_info.block_num_idx].num) >> 1)), &p_addr, GFP_KERNEL); + if (v_addr == 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to alloc v_addr for que_index %d\n", __func__, que_index); + return -ENOMEM; + } + + g_roce3_cap_info.que_addr[que_index][0][cap_index] = v_addr; + g_roce3_cap_info.que_addr[que_index][1][cap_index] = p_addr; + + pa_info->pa[que_index].wr_init_pc_h32 = (u32)((p_addr >> CAP_ADDR_COMBIN_SHIFT) & 0xffffffff); + pa_info->pa[que_index].wr_init_pc_l32 = (u32)(p_addr & 0xffffffff); + + dev_info(rdev->hwdev_hdl, "[ROCE] %s: v_addr que_index(%d), cap_index(%d), PA:0x%x %x\n", __func__, que_index, + cap_index, pa_info->pa[que_index].wr_init_pc_h32, pa_info->pa[que_index].wr_init_pc_l32); + + return 0; +} + +static void roce3_dfx_dma_free_addr(struct roce3_device *rdev, int cap_index, int que_index) +{ + u64 v_addr; + u64 p_addr; + + v_addr = g_roce3_cap_info.que_addr[que_index][0][cap_index]; + p_addr = g_roce3_cap_info.que_addr[que_index][1][cap_index]; + dma_free_coherent(&rdev->pdev->dev, + (unsigned long)(CAP_PKT_ITEM_SIZE * ((g_nattr[g_roce3_cap_info.block_num_idx].num) >> 1)), (void *)v_addr, + (dma_addr_t)p_addr); +} + +static int roce3_dfx_alloc_mem_for_one_cap(struct roce3_device *rdev, int cap_index) +{ + struct roce3_dfx_cap_tbl pa_info; + int ret; + + memset(&pa_info, 0x0, sizeof(pa_info)); + + ret = roce3_dfx_dma_alloc_addr(rdev, cap_index, 0, &pa_info); + if (ret != 0) { + return ret; + } + + ret = roce3_dfx_dma_alloc_addr(rdev, cap_index, 1, &pa_info); + if (ret != 0) { + goto err_dma_mem_alloc_free_1; + } + + ret = roce3_set_cap_cfg(rdev->hwdev, (u16)cap_index, (u32 *)&pa_info); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set cap cfg, ret(%d)\n", __func__, ret); + goto err_dma_mem_alloc_free; + } + + return 0; + +err_dma_mem_alloc_free: + roce3_dfx_dma_free_addr(rdev, cap_index, 1); + +err_dma_mem_alloc_free_1: + roce3_dfx_dma_free_addr(rdev, cap_index, 0); + return ret; +} + +static void roce3_dfx_free_mem_for_one_cap(struct roce3_device *rdev, int cap_index) +{ + roce3_dfx_dma_free_addr(rdev, cap_index, 1); + roce3_dfx_dma_free_addr(rdev, cap_index, 0); +} + +static int roce3_dfx_alloc_cap(struct roce3_device *rdev) +{ + u32 counter, times; + int ret; + int i; + + /* alloc lt memory resource */ + for (i = 0; i < CAP_PA_TBL_ENTRY_NUM; i++) { + ret = roce3_dfx_alloc_mem_for_one_cap(rdev, i); + if (ret != 0) { + goto err_dma_mem_alloc_free; + } + } + + for (times = 0; times < CLEAR_CAP_TRYING_TIMES; times++) { + if (times == CLEAR_CAP_TRYING_TIMES - 1) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to clear pi\n", __func__); + goto err_dma_mem_alloc_free; + } + + /* clear pi */ + ret = roce3_clear_cap_counter(rdev->hwdev, ROCE_CAP_COUNTER_INDEX, &counter); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to read counter(lt index %x), ret(%d)\n", __func__, + ROCE_CAP_COUNTER_INDEX, ret); + goto err_dma_mem_alloc_free; + } + + if (counter == 0) { + break; + } + + msleep(CLEAR_SLEEP_TIME); + } + + return 0; + +err_dma_mem_alloc_free: + for (i--; i >= 0; i--) { + roce3_dfx_free_mem_for_one_cap(rdev, i); + } + + return ret; +} + +static void roce3_dfx_free_cap(struct roce3_device *rdev) +{ + int i; + + for (i = 0; i < CAP_PA_TBL_ENTRY_NUM; i++) { + roce3_dfx_free_mem_for_one_cap(rdev, i); + } +} + +static void roce3_dfx_init_g_cap_info(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf) +{ + u32 mode = inbuf->mode; + + g_roce3_cap_info.func_id = rdev->glb_func_id; + g_roce3_cap_info.task.data = &g_roce3_cap_info; + g_roce3_cap_info.task.thread_fn = roce3_pkt_cap_poll; + g_roce3_cap_info.task.name = "capture_thread"; + g_roce3_cap_info.rdev = rdev; + g_roce3_cap_info.poll_ci = 0; + g_roce3_cap_info.block_num_per_entry = g_nattr[g_roce3_cap_info.block_num_idx].num; + g_roce3_cap_info.maxnum = (g_nattr[g_roce3_cap_info.block_num_idx].num) * CAP_PA_TBL_ENTRY_NUM; + g_roce3_cap_info.mode = mode; + g_roce3_cap_info.qp_list_cnt = 0; +} + +static int roce3_dfx_start_cap_pkt(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf, + union roce3_dfx_capture_outbuf *outbuf) +{ + struct roce3_dfx_cap_cfg_tbl cfg_info; + int ret; + + mutex_lock(&cap_mutex); + if (g_roce3_cap_info.cap_status == ROCE_CAPTURE_START) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Capture is running\n", __func__); + mutex_unlock(&cap_mutex); + return (-EBUSY); + } + + ret = roce3_dfx_alloc_cap(rdev); + if (ret != 0) { + mutex_unlock(&cap_mutex); + return ret; + } + + roce3_dfx_init_g_cap_info(rdev, inbuf); + + memset(&cfg_info, 0, sizeof(cfg_info)); + roce3_fill_cap_cfg(&cfg_info, 0, 0, 0); + + ret = roce3_set_cap_cfg(rdev->hwdev, CAP_PA_TBL_ENTRY_NUM, (u32 *)&cfg_info); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set cap cfg, ret(%d)\n", __func__, ret); + goto err_alloc_cap; + } + + dev_err(rdev->hwdev_hdl, "[ROCE] %s: roce create thread\n", __func__); + ret = roce3_create_thread(&(g_roce3_cap_info.task)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to create thread, ret(%d)\n", __func__, ret); + goto err_alloc_cap; + } + + ret = roce3_set_cap_func_en(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set cap enable, ret(%d)\n", __func__, ret); + goto err_thread_release; + } + + g_roce3_cap_info.cap_status = ROCE_CAPTURE_START; + INIT_LIST_HEAD(&g_roce3_cap_info.qp_list_head); + mutex_unlock(&cap_mutex); + + dev_info(rdev->hwdev_hdl, "[ROCE] %s: Start to capture pkt, func(%u)\n", __func__, g_roce3_cap_info.func_id); + return 0; + +err_thread_release: + roce3_stop_thread(&(g_roce3_cap_info.task)); + msleep(CAP_STOP_SLEEP_TIME); + +err_alloc_cap: + roce3_dfx_free_cap(rdev); + + g_roce3_cap_info.cap_status = ROCE_CAPTURE_STOP; + mutex_unlock(&cap_mutex); + + return ret; +} + +static int roce3_clear_cap_counter_encap(struct roce3_device *rdev, u16 lt_index) +{ + int ret; + u32 counter = 0; + u32 times; + + for (times = 0; times < CLEAR_CAP_TRYING_TIMES; times++) { + if (times == CLEAR_CAP_TRYING_TIMES - 1) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to clear pi\n", __func__); + return -EFAULT; + } + + ret = roce3_clear_cap_counter(rdev->hwdev, lt_index, &counter); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to clear cap counter(lt index 1), ret(%d)\n", __func__, ret); + return -EFAULT; + } + + if (counter == 0) { + break; + } + + msleep(CLEAR_SLEEP_TIME); + } + + return 0; +} + +int roce3_dfx_stop_cap_pkt(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf, + union roce3_dfx_capture_outbuf *outbuf) +{ + int ret = 0; + + dev_info(rdev->hwdev_hdl, "[ROCE] %s: start to stop cap, \n", __func__); + + mutex_lock(&cap_mutex); + if (g_roce3_cap_info.cap_status != ROCE_CAPTURE_START) { // 1:RUNNING + mutex_unlock(&cap_mutex); + return 0; + } + + if (g_roce3_cap_info.func_id != rdev->glb_func_id) { + mutex_unlock(&cap_mutex); + return 0; + } + + roce3_stop_thread(&(g_roce3_cap_info.task)); + + /* stop cap */ + ret = roce3_set_cap_func_disable(rdev); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to set cap enable, ret(%d)\n", __func__, ret); + ret = -EFAULT; + goto err; + } + + msleep(CAP_STOP_SLEEP_TIME); + + /* release lt mem resource */ + roce3_dfx_free_cap(rdev); + + /* lt index_1 */ + ret = roce3_clear_cap_counter_encap(rdev, ROCE_CAP_COUNTER_INDEX); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE] %s: Failed to clear pi(lt index %x), ret(%d)\n", __func__, + ROCE_CAP_COUNTER_INDEX, ret); + goto err; + } + + g_roce3_cap_info.cap_status = ROCE_CAPTURE_STOP; + g_roce3_cap_info.poll_ci = 0; + g_roce3_cap_info.func_id = 0; + g_roce3_cap_info.rdev = NULL; + dev_info(rdev->hwdev_hdl, "[ROCE] %s: Stop capture pkt, func(%d)\n", __func__, rdev->glb_func_id); + +err: + mutex_unlock(&cap_mutex); + return ret; +} + +static int roce3_dfx_query_cap_pkt(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf, + union roce3_dfx_capture_outbuf *outbuf) +{ + int ret; + u32 pi = 0; + u32 total = 0; + struct roce3_dfx_cap_cfg_tbl cfg_info; + struct roce3_dfx_capture_info *capture_info = &outbuf->capture_info; + + memset(&cfg_info, 0, sizeof(cfg_info)); + ret = roce3_get_cap_cfg(rdev->hwdev, CAP_NUM_PER_BLOCK, (u32 *)&cfg_info); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to read table, ret(%d)\n", __func__, ret); + return -EFAULT; + } + + ret = roce3_read_cap_counter(rdev->hwdev, CAP_COUNTER_TWO, &total); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to read counter(lt index 2), ret(%d)\n", __func__, ret); + return -EFAULT; + } + + ret = roce3_read_cap_counter(rdev->hwdev, ROCE_CAP_COUNTER_INDEX, &pi); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to read counter(lt index %x), ret(%d)\n", __func__, + ROCE_CAP_COUNTER_INDEX, ret); + return -EFAULT; + } + + capture_info->cap_status = g_roce3_cap_info.cap_status; + capture_info->cap_mode = cfg_info.dw1.bs.cap_mode; + capture_info->qp_mode = cfg_info.dw1.bs.qp_mode; + capture_info->cap_block_num_shift = cfg_info.dw1.bs.cap_block_num_shift; + capture_info->cap_func = cfg_info.dw2.bs.cap_func; + capture_info->cap_state = cfg_info.dw2.bs.state; + capture_info->cap_max_num = cfg_info.maxnum; + capture_info->cap_ci = g_roce3_cap_info.poll_ci; + capture_info->cap_pi = pi; + capture_info->cap_total = total; + + return 0; +} + +typedef int (*roce3_adm_dfx_capture_func_t)(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf, + union roce3_dfx_capture_outbuf *outbuf); + +/*lint -e26*/ +static roce3_adm_dfx_capture_func_t g_roce3_adm_dfx_capture_funcs[COMMON_CMD_VM_COMPAT_TEST] = { + [ROCE_CMD_START_CAP_PACKET] = roce3_dfx_start_cap_pkt, + [ROCE_CMD_STOP_CAP_PACKET] = roce3_dfx_stop_cap_pkt, + [ROCE_CMD_QUERY_CAP_INFO] = roce3_dfx_query_cap_pkt, + [ROCE_CMD_ENABLE_QP_CAP_PACKET] = NULL, + [ROCE_CMD_DISABLE_QP_CAP_PACKET] = NULL, + [ROCE_CMD_QUERY_QP_CAP_INFO] = NULL, +}; +/*lint +e26*/ + +int roce3_adm_dfx_capture(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + int ret; + const struct roce3_dfx_capture_inbuf *inbuf = (struct roce3_dfx_capture_inbuf *)buf_in; + union roce3_dfx_capture_outbuf *outbuf = (union roce3_dfx_capture_outbuf *)buf_out; + roce3_adm_dfx_capture_func_t roce3_adm_dfx_capture_func; + + memset(buf_out, 0, sizeof(union roce3_dfx_capture_outbuf)); + *out_size = sizeof(union roce3_dfx_capture_outbuf); + + if (inbuf->cmd_type >= COMMON_CMD_VM_COMPAT_TEST) { + dev_err(rdev->hwdev_hdl, "Not support this type(%d)\n", inbuf->cmd_type); + return -EINVAL; + } + + roce3_adm_dfx_capture_func = g_roce3_adm_dfx_capture_funcs[inbuf->cmd_type]; + if (roce3_adm_dfx_capture_func == NULL) { + dev_err(rdev->hwdev_hdl, "Not support this type(%d)\n", inbuf->cmd_type); + return -EINVAL; + } + + return roce3_adm_dfx_capture_func(rdev, inbuf, outbuf); +} + +#endif /* ROCE_PKT_CAP_EN */ diff --git a/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.h b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.h new file mode 100644 index 000000000..0800ff4b9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_cap.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * + * File Name : roce_dfx.h + * Version : v2.1 + * Created : 2020/8/29 + * Last Modified : 2021/10/16 + * Description : The definition of macros, data structure, function prototype etc of RoCE driver dfx features. + */ + +#ifndef ROCE_DFX_CAP_H +#define ROCE_DFX_CAP_H + +#include <linux/types.h> + +#include "hinic3_rdma.h" + +#include "roce_sysfs.h" +#include "roce.h" + +#define CAP_PKT_ITEM_SIZE 128 + +#define CAP_NUM_PER_BLOCK 255 + +#define CAP_SKB_LEN 120 + +#define CAP_HDR_OFFSET 4 + +#define FILL_CAP_CFG_PKT_NUM 8192 + +#define CAP_LOOP 255 + +#define CLEAR_MAX_TRY_TIME 10 + +#define CLEAR_SLEEP_TIME 2 + +#define CAP_STOP_SLEEP_TIME 50 + +#define CAP_COUNTER_TWO 2 + +#define CAP_PA_TBL_ENTRY_NUM 255 + +#define CAP_ADDR_COMBIN_SHIFT 32 + +#define CLEAR_CAP_TRYING_TIMES 10 + +#define ROCE_CAP_COUNTER_INDEX 0x39ff + +typedef union roce3_cap_hdr { + struct { + u32 rsvd : 16; + u32 pad : 8; + u32 rsvd0 : 2; + u32 col_num : 4; + u32 tx_rx : 1; + u32 vld : 1; + } cap_ctrl_info; + u32 value; +} roce3_cap_hdr_u; + +typedef struct roce3_dfx_cap_pa_entry { + u32 wr_init_pc_h32; + u32 wr_init_pc_l32; +} roce3_dfx_cap_pa_entry_s; + +typedef struct roce3_dfx_cap_tbl { + roce3_dfx_cap_pa_entry_s pa[2]; +} roce3_dfx_cap_tbl_s; + +typedef struct roce3_dfx_cap_cfg_tbl { + u32 ci_index; + + union { + struct { + /* Driver configurate bit offset by the number of per pa block, for example, 7 means 128, 8 means 256 */ + u8 cap_block_num_shift; + u8 cap_mode; /* Packet Capture mode */ + u8 qp_mode; /* according to qp Packet Capture */ + u8 rsvd; /* reserved */ + } bs; + u32 value; + } dw1; + + union { + struct { + u32 state : 8; /* Packet Capture rate control */ + u32 rsvd : 8; + u32 cap_func : 16; /* Packet Capture function */ + } bs; + u32 value; + } dw2; + + u32 maxnum; +} roce3_dfx_cap_cfg_tbl_s; + +struct roce3_qp_cap_pkt_list { + u32 xid; + struct list_head list; +}; + +struct roce3_cap_block_num_attr { + u32 block_num_idx; + u32 shift; + u32 num; +}; + +struct sdk_thread_info { + struct task_struct *thread_obj; + char *name; + void (*thread_fn)(void *); + void *thread_event; + void *data; +}; + +struct roce3_pkt_cap_info { + struct roce3_device *rdev; + u32 func_id; + u32 poll_ci; + u32 cap_mode; /* 0 : drop mode 1: overwrite mode */ + u32 mode; /* 0 : func mode 1: qp mode */ + u32 cap_status; /* 0 : stopped 1: running */ + u32 block_num_idx; + u32 block_num_per_entry; + u32 maxnum; + struct sdk_thread_info task; + char thread_name[20]; + u64 que_addr[2][2][256]; + struct list_head qp_list_head; /* Based on qp Packet Capture linked list */ + u32 qp_list_cnt; +}; + +#define ROCE_DFX_MAX_CAPTURE_QP_NUM 511 + +struct roce3_qp_cap_pkt { + __be32 xid; +}; + +struct roce3_dfx_capture_inbuf { + u32 cmd_type; + u32 mode; + u32 qpn; +}; + +struct roce3_dfx_capture_info { + u32 cap_status; + u32 cap_mode; + u32 qp_mode; + u32 cap_block_num_shift; + u32 cap_func; + u32 cap_state; + u32 cap_max_num; + u32 cap_pi; + u32 cap_ci; + u32 cap_total; +}; + +struct roce3_dfx_qp_capture_info { + u32 qp_num; + u32 qpn[ROCE_DFX_MAX_CAPTURE_QP_NUM]; +}; + +union roce3_dfx_capture_outbuf { + struct roce3_dfx_capture_info capture_info; + struct roce3_dfx_qp_capture_info qp_capture_info; +}; + +enum roce3_dfx_capture_mode { + ROCE_CAPTURE_MODE_CAP_FUNC = 0, + ROCE_CAPTURE_MODE_CAP_QP, +}; + +enum roce3_dfx_capture_state { + ROCE_CAPTURE_START = 0, + ROCE_CAPTURE_STOP, +}; + +extern int hinic3_set_func_capture_en(void *hwdev, u16 func_id, bool cap_en); + +int roce3_adm_dfx_capture(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size); +int roce3_dfx_stop_cap_pkt(struct roce3_device *rdev, const struct roce3_dfx_capture_inbuf *inbuf, + union roce3_dfx_capture_outbuf *outbuf); +static DEFINE_MUTEX(cap_mutex); + +#endif /* ROCE_DFX_CAP_H */ diff --git a/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_query.c b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_query.c new file mode 100644 index 000000000..804a3235d --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/dfx/roce_dfx_query.c @@ -0,0 +1,615 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * + * File Name : roce_dfx_query.c + * Version : v2.1 + * Created : 2020/8/29 + * Last Modified : 2021/10/16 + * Description : The definition of callback functions and internal functions of RoCE driver dfx features on qp level. + */ + +#ifdef __ROCE_DFX__ + +#include <linux/fs.h> +#include <linux/slab.h> +#include <linux/mutex.h> +#include <linux/kthread.h> + +#include <rdma/ib_verbs.h> +#include "roce_compat.h" +#include "roce.h" +#include "roce_dfx.h" +#include "roce_srq.h" +#include "roce_qp.h" +#include "roce_cq.h" +#include "hinic3_hw.h" +#include "roce_cmd.h" +#include "roce_pub_cmd.h" +#include "roce_cqm_cmd.h" + +int roce3_dfx_cmd_query_qp(struct roce3_device *rdev, u32 qpn, struct roce_qp_context *qp_ctx) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_qp_query_s *qp_query_inbuf = NULL; + struct roce3_qp_query_outbuf *qp_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_qp_query_s), &cqm_cmd_outbuf, + (u16)sizeof(struct roce3_qp_query_outbuf)); + if (ret != 0) { + roce3_dfx_print("Failed to alloc cqm_cmd_inoutbuf, ret=%d", ret); + return ret; + } + + qp_query_inbuf = (roce_cmd_qp_query_s *)cqm_cmd_inbuf->buf; + qp_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_QP_BITMASK); + qp_query_inbuf->com.index = cpu_to_be32(qpn); + + if ((rdev->cfg_info.lb_en != 0) && (rdev->cfg_info.lb_mode == ROCE_LB_MODE_1)) { + u8 cos = qpn & 0x3; + roce3_dfx_print("lb_mode1 roce3_dfx_cmd_query_qp func_id(%d) qpn:%u cos:%u \n", rdev->glb_func_id, qpn, cos); + ret = cqm_lb_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_QP, cos, cqm_cmd_inbuf, cqm_cmd_outbuf, + NULL, ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + } else { + roce3_dfx_print("Not lb_mode1 roce3_dfx_cmd_query_qp func_id(%d) qpn:%u\n", rdev->glb_func_id, qpn); + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_QP, cqm_cmd_inbuf, cqm_cmd_outbuf, NULL, + ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + } + + if (ret != 0) { + roce3_dfx_print("Failed to send cmd QUERY_QP"); + ret = -1; + goto out; + } + + qp_query_outbuf = (struct roce3_qp_query_outbuf *)cqm_cmd_outbuf->buf; + memcpy(qp_ctx, &qp_query_outbuf->qpc, sizeof(struct roce_qp_context)); +out: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + return ret; +} + +static int roce3_dfx_get_dev_algo(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + u32 cc_algo; + struct roce3_ecn_ctx ecn_ctx; + u32 *algo_type = &outbuf->algo_type; + + if (rdev == NULL) { + pr_err("[ROCE, ERR] %s: Failed to get roce device.\n", __func__); + return -EINVAL; + } + ecn_ctx = rdev->ecn_ctx; + cc_algo = ecn_ctx.cc_algo; + *algo_type = cc_algo; + + return 0; +} + +static int roce3_dfx_get_qp_count(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + struct roce3_dfx_qp_count *qp_count = &outbuf->qp_count; + + qp_count->qp_alloced = rdev->qp_cnt.alloc_qp_cnt; + qp_count->qp_deleted = rdev->qp_cnt.del_qp_cnt; + qp_count->qp_alive = rdev->qp_cnt.alloc_qp_cnt - rdev->qp_cnt.del_qp_cnt; + + return 0; +} + +/* QPC is statically allocated, so it is not necessary to judge whether it exists when querying the cache content */ +static int roce3_dfx_query_cache_qpc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + u32 qpn = inbuf->qpn; + struct roce_qp_context *qp_ctx = &outbuf->qp_ctx; + + memset(qp_ctx, 0, sizeof(struct roce_qp_context)); + ret = roce3_dfx_cmd_query_qp(rdev, qpn, qp_ctx); + if (ret != 0) { + roce3_dfx_print("Failed to query QPC from cache!"); + roce3_dfx_print("******************From Cache: qpn(%#x) ********************", qpn); + roce3_dfx_print(">>>>>>>>>>>>>>>> QUERY QPC FROM CACHE FAILED <<<<<<<<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: qpn(%#x) ********************", qpn); + + return ret; + } + + return 0; +} + +static int roce3_dfx_query_host_qpc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + cqm_object_s *cqm_obj_qp = NULL; + struct roce3_qp *rqp = NULL; + u32 qpn = inbuf->qpn; + struct roce_qp_context *qp_ctx = &outbuf->qp_ctx; + + cqm_obj_qp = cqm_object_get(rdev->hwdev, CQM_OBJECT_SERVICE_CTX, qpn, false); + if (cqm_obj_qp == NULL) { + roce3_dfx_print("Failed to get cqm_obj_qp."); + roce3_dfx_print("******************From Host: qpn(%#x) ********************", qpn); + roce3_dfx_print(">>>>>>>>>>> QUERY QPC FROM HOST FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Host: qpn(%#x) ********************", qpn); + + return -EINVAL; + } + + rqp = cqmobj_to_roce_qp(cqm_obj_qp); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_qp); + + memcpy(qp_ctx, rqp->qpc_info->vaddr, sizeof(struct roce_qp_context)); + + return 0; +} + +int roce3_dfx_cmd_query_cq(struct roce3_device *rdev, u32 cqn, struct roce_cq_context *cq_ctx) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_cq_query_s *cq_query_inbuf = NULL; + struct roce3_cq_query_outbuf *cq_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_cq_query_s), &cqm_cmd_outbuf, + (u16)sizeof(struct roce3_cq_query_outbuf)); + if (ret != 0) { + roce3_dfx_print("Failed to alloc cqm_cmd_inoutbuf, ret=%d", ret); + return ret; + } + + cq_query_inbuf = (roce_cmd_cq_query_s *)cqm_cmd_inbuf->buf; + cq_query_inbuf->com.index = cpu_to_be32(cqn); + cq_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_CQ_BITMASK); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_CQ, cqm_cmd_inbuf, cqm_cmd_outbuf, NULL, + ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + roce3_dfx_print("Failed to send cmd QUERY_CQ, ret=%d", ret); + ret = -1; + goto out; + } + + cq_query_outbuf = (struct roce3_cq_query_outbuf *)cqm_cmd_outbuf->buf; + memcpy(cq_ctx, &cq_query_outbuf->cqc, sizeof(struct roce_cq_context)); +out: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + + return ret; +} + +/* CQC is dynamic allocation. When querying cache content, you need to determine whether it exists or not. */ +static int roce3_dfx_query_cache_cqc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + cqm_object_s *cqm_obj_cq = NULL; + u32 cqn = inbuf->cqn; + struct roce_cq_context *cq_ctx = &outbuf->cq_ctx; + + cqm_obj_cq = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SCQ, cqn, false); + if (cqm_obj_cq == NULL) { + roce3_dfx_print("Failed to get cqm_obj_cq."); + roce3_dfx_print("******************From Cache: cqn(%#x) ********************", cqn); + roce3_dfx_print(">>>>>>>>>>> QUERY CQC FROM CACHE FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: cqn(%#x) ********************", cqn); + + return -EINVAL; + } + + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_cq); + + memset(cq_ctx, 0, sizeof(struct roce_cq_context)); + ret = roce3_dfx_cmd_query_cq(rdev, cqn, cq_ctx); + if (ret != 0) { + roce3_dfx_print("Failed to query cq from cache!"); + roce3_dfx_print("******************From Cache: cqn(%#x) ********************", cqn); + roce3_dfx_print(">>>>>>>>>>>>>>>> QUERY CQC FROM CACHE FAILED <<<<<<<<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: cqn(%#x) ********************", cqn); + + return -EINVAL; + } + + return 0; +} + +static int roce3_dfx_query_host_cqc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + cqm_object_s *cqm_obj_cq = NULL; + struct roce3_cq *rcq = NULL; + u32 cqn = inbuf->cqn; + struct roce_cq_context *cq_ctx = &outbuf->cq_ctx; + + cqm_obj_cq = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SCQ, cqn, false); + if (cqm_obj_cq == NULL) { + roce3_dfx_print("Failed to get cqm_obj_cq."); + roce3_dfx_print("******************From Host: cqn(%#x) ********************", cqn); + roce3_dfx_print(">>>>>>>>>>> QUERY CQC FROM HOST FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Host: cqn(%#x) ********************", cqn); + + return -EINVAL; + } + + rcq = cqmobj_to_roce3_cq(cqm_obj_cq); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_cq); + + memcpy(cq_ctx, rcq->cqm_cq->q_ctx_vaddr, sizeof(struct roce_cq_context)); + + return 0; +} + +int roce3_dfx_cmd_query_srq(struct roce3_device *rdev, u32 srqn, struct roce_srq_context *srq_ctx) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_srq_query_s *srq_query_inbuf = NULL; + struct roce3_srq_query_outbuf *srq_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_srq_query_s), &cqm_cmd_outbuf, + (u16)sizeof(struct roce3_srq_query_outbuf)); + if (ret != 0) { + roce3_dfx_print("Failed to alloc cqm_cmd_inoutbuf, ret=%d", ret); + return ret; + } + + srq_query_inbuf = (roce_cmd_srq_query_s *)cqm_cmd_inbuf->buf; + srq_query_inbuf->com.index = cpu_to_be32(srqn); + srq_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_SRQ_BITMASK); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_SRQ, cqm_cmd_inbuf, cqm_cmd_outbuf, NULL, + ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + roce3_dfx_print("Failed to send cmd QUERY_SRQ, ret=%d", ret); + ret = -1; + goto out; + } + + srq_query_outbuf = (struct roce3_srq_query_outbuf *)cqm_cmd_outbuf->buf; + memcpy(srq_ctx, srq_query_outbuf, + sizeof(struct roce3_srq_query_outbuf)); +out: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + + return ret; +} + +/* SRQC is dynamic allocation. When querying the cache content, you need to determine whether it exists or not. */ +static int roce3_dfx_query_cache_srqc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + cqm_object_s *cqm_obj_srq = NULL; + u32 srqn = inbuf->srqn; + struct roce_srq_context *srq_ctx = &outbuf->srq_ctx; + + cqm_obj_srq = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SRQ, srqn, false); + if (cqm_obj_srq == NULL) { + roce3_dfx_print("Failed to get cqm_obj_srq"); + roce3_dfx_print("******************From Cache: srqn(%#x) ********************", srqn); + roce3_dfx_print(">>>>>>>>>>> QUERY CQC FROM CACHE FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: srqn(%#x) ********************", srqn); + + return -EINVAL; + } + + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_srq); + + memset(srq_ctx, 0, sizeof(struct roce_srq_context)); + ret = roce3_dfx_cmd_query_srq(rdev, srqn, srq_ctx); + if (ret != 0) { + roce3_dfx_print("Failed to query srq from cache"); + roce3_dfx_print("******************From Cache: srqn(%#x) ********************", srqn); + roce3_dfx_print(">>>>>>>>>>>>>>>> QUERY SRQC FROM CACHE FAILED <<<<<<<<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: srqn(%#x) ********************", srqn); + + return -EINVAL; + } + + return 0; +} + +static int roce3_dfx_query_host_srqc(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + cqm_object_s *cqm_obj_srq = NULL; + struct roce3_srq *rsrq = NULL; + u32 srqn = inbuf->srqn; + struct roce_srq_context *srq_ctx = &outbuf->srq_ctx; + + cqm_obj_srq = cqm_object_get(rdev->hwdev, CQM_OBJECT_RDMA_SRQ, srqn, false); + if (cqm_obj_srq == NULL) { + roce3_dfx_print("Failed to get cqm_obj_srq."); + roce3_dfx_print("******************From Host: srqn(%#x) ********************", srqn); + roce3_dfx_print(">>>>>>>>>>> QUERY SRQC FROM HOST FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Host: srqn(%#x) ********************", srqn); + + return -EINVAL; + } + + rsrq = cqmobj_to_roce3_srq(cqm_obj_srq); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_srq); + + memcpy(srq_ctx, rsrq->cqm_srq->q_ctx_vaddr, sizeof(struct roce_srq_context)); + + return 0; +} + +static int roce3_dfx_cmd_query_mpt(struct roce3_device *rdev, u32 key, struct roce_mpt_context *mpt_entry) +{ + int ret; + u32 mpt_index; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_mpt_query_s *mpt_query_inbuf = NULL; + struct roce3_mpt_query_outbuf *mpt_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_mpt_query_s), &cqm_cmd_outbuf, + (u16)sizeof(struct roce3_mpt_query_outbuf)); + if (ret != 0) { + roce3_dfx_print("Failed to alloc cqm_cmd_inoutbuf, ret=%d", ret); + return ret; + } + + mpt_query_inbuf = (roce_cmd_mpt_query_s *)cqm_cmd_inbuf->buf; + mpt_index = (key >> MR_KEY_2_INDEX_SHIFT) & 0xFFFFFF; + mpt_query_inbuf->com.index = cpu_to_be32(mpt_index); + mpt_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_MR_BITMASK); + + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_MPT, cqm_cmd_inbuf, cqm_cmd_outbuf, NULL, + ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + roce3_dfx_print("Failed to send cmd QUERY_MPT"); + ret = -1; + goto out; + } + + mpt_query_outbuf = (struct roce3_mpt_query_outbuf *)cqm_cmd_outbuf->buf; + memcpy(mpt_entry, &mpt_query_outbuf->mpt_entry, + sizeof(struct roce_mpt_context)); +out: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + return ret; +} + +static int roce3_dfx_cmd_query_gid(struct roce3_device *rdev, u32 port, u32 gid_index, struct rdma_gid_entry *gid_entry) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + cqm_cmd_buf_s *cqm_cmd_outbuf = NULL; + roce_cmd_query_gid_s *gid_query_inbuf = NULL; + struct rdma_gid_query_outbuf *gid_query_outbuf = NULL; + + ret = roce3_cqm_cmd_zalloc_inoutbuf(rdev->hwdev, &cqm_cmd_inbuf, (u16)sizeof(roce_cmd_query_gid_s), &cqm_cmd_outbuf, + (u16)sizeof(struct rdma_gid_query_outbuf)); + if (ret != 0) { + roce3_dfx_print("Failed to alloc cqm_cmd_inoutbuf, ret=%d", ret); + return ret; + } + + gid_query_inbuf = (roce_cmd_query_gid_s *)cqm_cmd_inbuf->buf; + gid_query_inbuf->port = cpu_to_be32(port); + gid_query_inbuf->com.index = cpu_to_be32(gid_index); + gid_query_inbuf->com.dw0.bs.cmd_bitmask = cpu_to_be16(VERBS_CMD_TYPE_GID_BITMASK); + ret = cqm_send_cmd_box(rdev->hwdev, HINIC3_MOD_ROCE, ROCE_CMD_QUERY_GID, cqm_cmd_inbuf, cqm_cmd_outbuf, NULL, + ROCE_CMD_TIME_CLASS_B, HINIC3_CHANNEL_ROCE); + if (ret != 0) { + roce3_dfx_print("Failed to send cmd QUERY_GID"); + ret = -1; + goto out; + } + + gid_query_outbuf = (struct rdma_gid_query_outbuf *)cqm_cmd_outbuf->buf; + memcpy(gid_entry, &gid_query_outbuf->gid_entry, sizeof(struct rdma_gid_entry)); +out: + roce3_cqm_cmd_free_inoutbuf(rdev->hwdev, cqm_cmd_inbuf, cqm_cmd_outbuf); + + return ret; +} + +/* MPT is statically allocated, so it is not necessary to judge whether it exists when querying the cache content */ +static int roce3_dfx_query_cache_mpt(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + u32 mpt_key = inbuf->mpt_key; + struct roce_mpt_context *mpt_entry = &outbuf->mpt; + + memset(mpt_entry, 0, sizeof(struct roce_mpt_context)); + ret = roce3_dfx_cmd_query_mpt(rdev, mpt_key, mpt_entry); + if (ret != 0) { + roce3_dfx_print("Failed to query mpt from cache!"); + roce3_dfx_print("******************From Cache: mpt_key(%#x) ********************", mpt_key); + roce3_dfx_print(">>>>>>>>>>>>>>>> QUERY MPT FROM CACHE FAILED <<<<<<<<<<<<<<<<<"); + roce3_dfx_print("******************From Cache: mpt_key(%#x) ********************", mpt_key); + + return ret; + } + + return 0; +} + +static int roce3_dfx_query_host_mpt(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + u32 mpt_index = 0; + cqm_object_s *cqm_obj_mpt = NULL; + cqm_qpc_mpt_s *cqm_mpt = NULL; + struct rdma_mpt *rmpt = NULL; + u32 mpt_key = inbuf->mpt_key; + struct roce_mpt_context *mpt_entry = &outbuf->mpt; + + mpt_index = (mpt_key >> MR_KEY_2_INDEX_SHIFT) & 0xFFFFFF; + cqm_obj_mpt = cqm_object_get(rdev->hwdev, CQM_OBJECT_MPT, mpt_index, false); + if (cqm_obj_mpt == NULL) { + roce3_dfx_print("Failed to get cqm_obj_mpt."); + roce3_dfx_print("******************From Host: mpt_key(%#x) ********************", mpt_key); + roce3_dfx_print(">>>>>>>>>>> QUERY MPT FROM HOST FAILED, NOT EXIST <<<<<<<<<<<"); + roce3_dfx_print("******************From Host: mpt_key(%#x) ********************", mpt_key); + + return -EINVAL; + } + + cqm_mpt = container_of(cqm_obj_mpt, cqm_qpc_mpt_s, object); + rmpt = (struct rdma_mpt *)cqm_mpt->priv; + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_mpt); + + memcpy(mpt_entry, rmpt->vaddr, sizeof(struct roce_mpt_context)); + + return 0; +} + +static int roce3_dfx_query_cache_gid(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + u32 gid_index = inbuf->gid_index; + struct rdma_gid_entry *gid_entry = &outbuf->gid_entry; + + memset(gid_entry, 0, sizeof(struct rdma_gid_entry)); + ret = roce3_dfx_cmd_query_gid(rdev, 0, gid_index, gid_entry); + if (ret != 0) { + roce3_dfx_print("***************port(1), gid_index(%d) *****************", gid_index); + roce3_dfx_print("Failed to query gid from cache!"); + roce3_dfx_print("***************port(1), gid_index(%d) *****************", gid_index); + + return -EINVAL; + } + + return 0; +} + +static void roce3_dfx_query_pi_ci_b32_to_cpu(struct roce_qp_context *qp_ctx) +{ + qp_ctx->chip_seg.sqc.dw0.value = be32_to_cpu(qp_ctx->chip_seg.sqc.dw0.value); + qp_ctx->chip_seg.sqc.dw2.value = be32_to_cpu(qp_ctx->chip_seg.sqc.dw2.value); + qp_ctx->chip_seg.sqc.dw3.value = be32_to_cpu(qp_ctx->chip_seg.sqc.dw3.value); + qp_ctx->chip_seg.sqc.dw7.value = be32_to_cpu(qp_ctx->chip_seg.sqc.dw7.value); + qp_ctx->chip_seg.sqc.dw14.value = be32_to_cpu(qp_ctx->chip_seg.sqc.dw14.value); + qp_ctx->chip_seg.rqc.dw0.value = be32_to_cpu(qp_ctx->chip_seg.rqc.dw0.value); + qp_ctx->chip_seg.rqc.dw3.value = be32_to_cpu(qp_ctx->chip_seg.rqc.dw3.value); + qp_ctx->chip_seg.rqc.dw7.value = be32_to_cpu(qp_ctx->chip_seg.rqc.dw7.value); + qp_ctx->chip_seg.rqc.dw14.value = be32_to_cpu(qp_ctx->chip_seg.rqc.dw14.value); + qp_ctx->chip_seg.sqac.dw3.value = be32_to_cpu(qp_ctx->chip_seg.sqac.dw3.value); + qp_ctx->chip_seg.sqac.dw7.value = be32_to_cpu(qp_ctx->chip_seg.sqac.dw7.value); + qp_ctx->chip_seg.rcc.dw5.value = be32_to_cpu(qp_ctx->chip_seg.rcc.dw5.value); + qp_ctx->chip_seg.rcc.dw6.value = be32_to_cpu(qp_ctx->chip_seg.rcc.dw6.value); + qp_ctx->chip_seg.rcc.dw7.value = be32_to_cpu(qp_ctx->chip_seg.rcc.dw7.value); + qp_ctx->chip_seg.qpcc.dw4.value = be32_to_cpu(qp_ctx->chip_seg.qpcc.dw4.value); +} + +static void roce3_dfx_query_pi_ci_set(struct roce_qp_context qp_ctx, struct roce3_dfx_pi_ci *pi_ci) +{ + pi_ci->qpc_sq_pi_on_chip = qp_ctx.chip_seg.sqc.dw0.bs.sq_pi_on_chip; + pi_ci->qpc_sq_pi = qp_ctx.chip_seg.sqc.dw2.bs.sq_pi; + pi_ci->qpc_sq_load_pi = qp_ctx.chip_seg.sqc.dw3.bs.sq_load_pi; + pi_ci->qpc_rq_pi_on_chip = qp_ctx.chip_seg.rqc.dw0.bs.rq_pi_on_chip; + pi_ci->qpc_rq_load_pi = qp_ctx.chip_seg.rqc.dw3.bs.rq_load_pi; + pi_ci->qpc_rq_pi = qp_ctx.chip_seg.rqc.dw7.bs.rq_pi; + pi_ci->qpc_rc_pi = qp_ctx.chip_seg.rcc.dw5.bs.rc_pi; + pi_ci->qpc_sq_ci = qp_ctx.chip_seg.sqc.dw3.bs.sq_ci; + pi_ci->qpc_sq_wqe_prefetch_ci = qp_ctx.chip_seg.sqc.dw7.bs.sq_wqe_prefetch_ci; + pi_ci->qpc_sq_mtt_prefetch_wqe_ci = qp_ctx.chip_seg.sqc.dw14.bs.sq_mtt_prefetch_wqe_ci; + pi_ci->qpc_sqa_ci = qp_ctx.chip_seg.sqac.dw3.bs.sqa_ci; + pi_ci->qpc_sqa_wqe_prefetch_ci = qp_ctx.chip_seg.sqac.dw7.bs.sqa_wqe_prefetch_ci; + pi_ci->qpc_rq_ci = qp_ctx.chip_seg.rqc.dw3.bs.rq_ci; + pi_ci->qpc_rq_wqe_prefetch_ci = qp_ctx.chip_seg.rqc.dw7.bs.rq_wqe_prefetch_ci; + pi_ci->qpc_rq_mtt_prefetch_wqe_ci = qp_ctx.chip_seg.rqc.dw14.bs.rq_mtt_prefetch_wqe_ci; + pi_ci->qpc_rq_base_ci = qp_ctx.chip_seg.qpcc.dw4.bs.rq_base_ci; + pi_ci->qpc_rc_ci = qp_ctx.chip_seg.rcc.dw6.bs.rc_ci; + pi_ci->qpc_rc_prefetch_ci = qp_ctx.chip_seg.rcc.dw7.bs.rc_prefetch_ci; +} + +static int roce3_dfx_query_pi_ci(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf) +{ + int ret; + struct roce_qp_context qp_ctx; + struct roce_cq_context cq_ctx; + u32 qpn = inbuf->query_pi_ci.qpn; + u32 cqn = inbuf->query_pi_ci.cqn; + struct roce3_dfx_pi_ci *pi_ci = &outbuf->pi_ci; + + memset(pi_ci, 0, sizeof(struct roce3_dfx_pi_ci)); + + memset(&qp_ctx, 0, sizeof(qp_ctx)); + ret = roce3_dfx_cmd_query_qp(rdev, qpn, &qp_ctx); + if (ret != 0) { + return ret; + } + + roce3_dfx_query_pi_ci_b32_to_cpu(&qp_ctx); + roce3_dfx_query_pi_ci_set(qp_ctx, pi_ci); + + memset(&cq_ctx, 0, sizeof(cq_ctx)); + ret = roce3_dfx_cmd_query_cq(rdev, cqn, &cq_ctx); + if (ret != 0) { + return ret; + } + + cq_ctx.dw0.value = be32_to_cpu(cq_ctx.dw0.value); + cq_ctx.dw1.value = be32_to_cpu(cq_ctx.dw1.value); + cq_ctx.dw2.value = be32_to_cpu(cq_ctx.dw2.value); + cq_ctx.dw3.value = be32_to_cpu(cq_ctx.dw3.value); + cq_ctx.dw9.value = be32_to_cpu(cq_ctx.dw9.value); + cq_ctx.ci_record_gpa_at_hop_num = be32_to_cpu(cq_ctx.ci_record_gpa_at_hop_num); + + pi_ci->cq_ci_on_chip = cq_ctx.dw0.bs.ci_on_chip; + pi_ci->cq_ci = cq_ctx.dw1.bs.ci; + pi_ci->cq_load_ci = cq_ctx.dw3.bs.load_ci; + pi_ci->cq_ci_record_gpa_at_hop_num = cq_ctx.ci_record_gpa_at_hop_num; + pi_ci->cq_last_solicited_pi = cq_ctx.dw0.bs.last_solicited_pi; + pi_ci->cq_pi = cq_ctx.dw2.bs.pi; + pi_ci->cq_last_notified_pi = cq_ctx.dw9.bs.last_notified_pi; + + return 0; +} + +typedef int (*roce3_adm_dfx_query_t)(const struct roce3_dfx_query_inbuf *inbuf, struct roce3_device *rdev, + union roce3_dfx_query_outbuf *outbuf); + +static roce3_adm_dfx_query_t roce3_adm_dfx_query_funcs[COMMON_CMD_VM_COMPAT_TEST] = { + [ROCE_CMD_GET_QPC_FROM_CACHE] = roce3_dfx_query_cache_qpc, + [ROCE_CMD_GET_QPC_FROM_HOST] = roce3_dfx_query_host_qpc, + [ROCE_CMD_GET_CQC_FROM_CACHE] = roce3_dfx_query_cache_cqc, + [ROCE_CMD_GET_CQC_FROM_HOST] = roce3_dfx_query_host_cqc, + [ROCE_CMD_GET_SRQC_FROM_CACHE] = roce3_dfx_query_cache_srqc, + [ROCE_CMD_GET_SRQC_FROM_HOST] = roce3_dfx_query_host_srqc, + [ROCE_CMD_GET_MPT_FROM_CACHE] = roce3_dfx_query_cache_mpt, + [ROCE_CMD_GET_MPT_FROM_HOST] = roce3_dfx_query_host_mpt, + [ROCE_CMD_GET_GID_FROM_CACHE] = roce3_dfx_query_cache_gid, + [ROCE_CMD_GET_QPC_CQC_PI_CI] = roce3_dfx_query_pi_ci, + [ROCE_CMD_GET_QP_COUNT] = roce3_dfx_get_qp_count, + [ROCE_CMD_GET_DEV_ALGO] = roce3_dfx_get_dev_algo, +}; + +int roce3_adm_dfx_query(struct roce3_device *rdev, const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + const struct roce3_dfx_query_inbuf *inbuf = (struct roce3_dfx_query_inbuf *)buf_in; + union roce3_dfx_query_outbuf *outbuf = (union roce3_dfx_query_outbuf *)buf_out; + roce3_adm_dfx_query_t roce3_adm_dfx_query_func; + + memset(buf_out, 0, sizeof(union roce3_dfx_query_outbuf)); + *out_size = (u32)sizeof(union roce3_dfx_query_outbuf); + + if (inbuf->cmd_type >= COMMON_CMD_VM_COMPAT_TEST) { + roce3_dfx_print("Not support this type(%d)", inbuf->cmd_type); + return -EINVAL; + } + + roce3_adm_dfx_query_func = roce3_adm_dfx_query_funcs[inbuf->cmd_type]; + if (roce3_adm_dfx_query_func == NULL) { + roce3_dfx_print("Not support this type(%d)", inbuf->cmd_type); + return -EINVAL; + } + + return roce3_adm_dfx_query_func(inbuf, rdev, outbuf); +} + +#endif diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_cdev_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_cdev_extension.c new file mode 100644 index 000000000..d56e35bab --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_cdev_extension.c @@ -0,0 +1,18 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_cdev_extension.c + * Version : v2.0 + * Created : 2021/7/1 + * Last Modified : 2022/7/1 + * Description : The definition of RoCE Async Event realated functions in kernel space. + */ +#ifndef PANGEA_NOF + +#include "roce_cdev_extension.h" + +long ioctl_non_bonding_extend(unsigned int cmd, struct roce3_device *rdev, unsigned long arg) +{ + return NOT_SUPOORT_TYPE; +} +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_event_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_event_extension.c new file mode 100644 index 000000000..803d059dd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_event_extension.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2022-2022. All rights reserved. + * + * File Name : roce_event_extension.c + * Version : v1.0 + * Created : 2022/1/27 + * Last Modified : 2022/1/27 + * Description : The definition of RoCE async event module standard callback functions. + */ + +#include "roce_event_extension.h" + +#ifndef PANGEA_NOF +void roce3_event_report_extend(const struct roce3_device *rdev, int event_str_index) +{ + /*lint -e160 -e522*/ + roce3_pr_err_once("[ROCE] %s: [non ofed event type] Invalid extend event type error. function id: %u\n", __func__, + rdev->glb_func_id); + /*lint +e160 +e522*/ +} + +int roce3_async_event_handle_extend(u8 event_type, u8 *val, struct roce3_device *rdev) +{ + int event_str_index = 0; + + event_str_index = to_unkown_event_str_index(event_type, val); + + return event_str_index; +} +#endif diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_main_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_main_extension.c new file mode 100644 index 000000000..9b6649ee4 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_main_extension.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_main_extension.c + * Version : v1.0 + * Created : 2021/10/18 + * Last Modified : 2021/12/7 + * Description : The definition of RoCE MAIN extended functions. + */ + +#include "roce_main_extension.h" + +#ifndef PANGEA_NOF + +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" + +static struct mutex g_rdev_mutex; +#endif + +void roce3_service_init_pre(void) +{ +#ifdef ROCE_BONDING_EN + mutex_init(&g_rdev_mutex); +#endif + + return; +} + +void roce3_service_init_ext(void) +{ + return; +} + +void roce3_lock_rdev(void) +{ +#ifdef ROCE_BONDING_EN + mutex_lock(&g_rdev_mutex); +#endif +} + +void roce3_unlock_rdev(void) +{ +#ifdef ROCE_BONDING_EN + mutex_unlock(&g_rdev_mutex); +#endif +} + +int roce3_get_rdev_by_uld(struct hinic3_lld_dev *lld_dev, void *uld_dev, struct roce3_device **rdev, + struct hinic3_event_info *event) +{ +#ifdef ROCE_BONDING_EN + int ret; + + ret = roce3_bond_event_cfg_rdev(lld_dev, uld_dev, rdev); + if (ret != 0) { + pr_err("[ROCE] %s: Cfg bond rdev failed(%d)\n", __func__, ret); + return ret; + } + ret = roce3_bonded_port_event_report(*rdev, event); + if (ret != 0) { + pr_err("[ROCE] %s: Report bond event failed(%d)\n", __func__, ret); + return ret; + } +#else + if ((lld_dev == NULL) || (uld_dev == NULL)) { + pr_err("[ROCE] %s: Input params is null\n", __func__); + return -ENODEV; + } + *rdev = (struct roce3_device *)uld_dev; +#endif + return 0; +} +#endif /* !PANGEA_NOF */ + +#ifdef ROCE_STANDARD +void roce3_init_dev_ext_handlers(struct roce3_device *rdev) +{ + return; +} +#endif /* ROCE_STANDARD */ + +#ifndef PANGEA_NOF +void roce3_remove_clean_res_ext(struct roce3_device *rdev) +{ +#ifdef __ROCE_DFX__ + roce3_dfx_clean_up(rdev); +#endif +} +#endif /* PANGEA_NOF */ + +#ifndef PANGEA_NOF +int roce3_board_cfg_check(struct roce3_device *rdev) +{ + int ret = 0; + int port_num = 0; + int port_speed = 0; + + port_num = rdev->board_info.port_num; + port_speed = rdev->board_info.port_speed; + if ((port_num == ROCE3_2_PORT_NUM) && (port_speed == ROCE3_100G_PORT_SPEED)) { + rdev->hw_info.hca_type = ROCE3_2_100G_HCA; + } else if ((port_num == ROCE3_4_PORT_NUM) && (port_speed == ROCE3_25G_PORT_SPEED)) { + rdev->hw_info.hca_type = ROCE3_4_25G_HCA; + } else if ((port_num == ROCE3_2_PORT_NUM) && (port_speed == ROCE3_25G_PORT_SPEED)) { + rdev->hw_info.hca_type = ROCE3_2_25G_HCA; + } else { + pr_err("[ROCE] %s: Invalid fw cfg\n", __func__); + ret = (-EINVAL); + } + + return ret; +} + +int roce3_mmap_ext(struct roce3_device *rdev, struct roce3_ucontext *ucontext, struct vm_area_struct *vma) +{ + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Not support, func_id(%d)\n", __func__, rdev->glb_func_id); + return -EINVAL; +} + +int roce3_dfx_mem_alloc(struct roce3_device *rdev) +{ + return 0; +} + +void roce3_dfx_mem_free(struct roce3_device *rdev) +{ + return; +} + +void *roce3_ucontext_alloc_ext(void) +{ + return kzalloc(sizeof(struct roce3_ucontext), GFP_KERNEL); +} + +void *roce3_resp_alloc_ext(void) +{ + return kzalloc(sizeof(struct roce3_alloc_ucontext_resp), GFP_KERNEL); +} + +void roce3_resp_set_ext(struct roce3_device *rdev, struct roce3_alloc_ucontext_resp *resp) +{ + return; +} + +void roce3_ucontext_set_ext(struct roce3_device *rdev, struct roce3_ucontext *context) +{ + return; +} + +void *roce3_rdev_alloc_ext(void) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) \ + || defined(OFED_MLNX_5_8) + return (void *)ib_alloc_device(roce3_device, ib_dev); +#else + return (void *)ib_alloc_device(sizeof(struct roce3_device)); +#endif +} + +void roce3_rdev_set_ext(struct roce3_device *rdev) +{ + return; +} + +int ib_copy_to_udata_ext(struct ib_udata *udata, struct roce3_alloc_ucontext_resp *resp) +{ + return ib_copy_to_udata(udata, resp, sizeof(struct roce3_alloc_ucontext_resp)); +} + +int roce3_set_comm_event(const struct roce3_device *rdev, const struct hinic3_event_info *event) +{ + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Comm event unsupported, func_id(%d), event(%d)\n", __func__, + rdev->glb_func_id, event->type); + return -1; +} + +bool roce3_hca_is_present(const struct roce3_device *rdev) +{ + return true; +} +#endif /* PANGEA_NOF */ + +#if !defined(NOF_AA) +int roce3_init_dev_ext(struct roce3_device *rdev) +{ + return 0; +} + +#if defined(EULER_2_10_OFED_4_19) || defined(KY10_OFED_4_19) +void roce3_rdma_cap_ext(struct rdma_service_cap *rdma_cap) +{ + rdma_cap->max_sq_desc_sz = RDMA_MAX_SQ_DESC_SZ_COMPUTE; + rdma_cap->dev_rdma_cap.roce_own_cap.max_wqes = ROCE_MAX_WQES_COMPUTE; + rdma_cap->dev_rdma_cap.roce_own_cap.max_sq_inline_data_sz = ROCE_MAX_SQ_INLINE_DATA_SZ_COMPUTE; + + return; +} +#else +void roce3_rdma_cap_ext(struct rdma_service_cap *rdma_cap) +{ + return; +} +#endif + +#endif diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_mr_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_mr_extension.c new file mode 100644 index 000000000..d176e9033 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_mr_extension.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_mr_standard.c + * Version : v1.1 + * Created : 2021/7/14 + * Last Modified : 2021/11/24 + * Description : The definition of RoCE MR module standard callback functions. + */ +#include "roce_mr.h" +#include "roce_main_extension.h" +#include "roce_mr_extension.h" + +#ifdef ROCE_STANDARD +int roce3_check_alloc_mr_type(enum ib_mr_type mr_type) +{ + int ret = 0; + + if (mr_type != IB_MR_TYPE_MEM_REG) { + ret = -EINVAL; + pr_err("[ROCE, ERR] %s: mr_type is invalid. mr_type:%u\n", __func__, mr_type); + } + + return ret; +} + +enum rdma_mr_type roce3_get_mrtype(enum ib_mr_type ib_mr_type) +{ + switch (ib_mr_type) { + case IB_MR_TYPE_MEM_REG: + return RDMA_DMA_MR; + + default: + return RDMA_DMA_MR; + } +} +#endif + diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_netdev_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_netdev_extension.c new file mode 100644 index 000000000..fa700f226 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_netdev_extension.c @@ -0,0 +1,174 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_netdev_extension.c + * Version : v1.1 + * Created : 2021/10/18 + * Last Modified : 2022/1/26 + * Description : The definition of RoCE net devices realated extended functions. + */ + +#include "roce_netdev_extension.h" +#include "roce_mpu_common.h" + +#ifdef ROCE_BONDING_EN +#include "roce_bond.h" +#endif + +#ifdef ROCE_VROCE_EN +static int roce3_get_vni_by_func_id(void *hwdev, u16 func_id, u32 *vni) +{ + int ret; + vroce_mac_cfg_vni_info_s mac_vni_info; + u16 out_size = (u16)sizeof(vroce_mac_cfg_vni_info_s); + + if (!hwdev || !vni) { + pr_err("[ROCE, ERR] %s: null pointer hwdev %p vni %p\n", __func__, hwdev, vni); + return -EINVAL; + } + + memset(&mac_vni_info, 0, sizeof(mac_vni_info)); + + mac_vni_info.func_id = func_id; + ret = roce3_msg_to_mgmt_sync(hwdev, ROCE_MPU_CMD_GET_MAC_VNI, &mac_vni_info, sizeof(mac_vni_info), &mac_vni_info, + &out_size); + if ((ret != 0) || (out_size == 0) || (mac_vni_info.head.status != 0)) { + pr_err("[ROCE, ERR] %s: Failed to get mac vni, err(%d), status(0x%x), out size(0x%x)\n", __func__, ret, + mac_vni_info.head.status, out_size); + return -EINVAL; + } + + *vni = (mac_vni_info.vni_en) ? mac_vni_info.vlan_vni : 0; + + return ret; +} +#endif + +#ifndef PANGEA_NOF +int roce3_add_real_device_mac(struct roce3_device *rdev, struct net_device *netdev) +{ + int ret; + u32 vlan_id = 0; + +#ifndef ROCE_VROCE_EN + /* no need to configure IPSURX vf table for vroce here, this action has been done in vroce driver */ + roce3_add_ipsu_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, vlan_id, rdev->glb_func_id, + hinic3_er_id(rdev->hwdev)); +#else + /* vroce uses vni to filt invalid packets */ + ret = roce3_get_vni_by_func_id(rdev->hwdev, rdev->glb_func_id, &vlan_id); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: get roce3_get_vni_by_func_id failed, vlan_id(0x%x) ret(%d)\n", __func__, vlan_id, ret); + } + + ret = + roce3_add_mac_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, vlan_id, rdev->glb_func_id, rdev->glb_func_id); + if (ret != 0) { + pr_err("[ROCE, ERR] %s: Failed to add mac_vlan entry, ret(%d)\n", __func__, ret); + return ret; + } +#endif + +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + ret = roce3_add_bond_real_slave_mac(rdev, (u8 *)netdev->dev_addr); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to add bond read device ipsu mac, func_id(%d)\n", __func__, + rdev->glb_func_id); + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, 0, rdev->glb_func_id, + hinic3_er_id(rdev->hwdev)); + return ret; + } + } +#endif + + memcpy(rdev->mac, netdev->dev_addr, sizeof(rdev->mac)); + + return 0; +} + +int roce3_add_vlan_device_mac(struct roce3_device *rdev, struct net_device *netdev) +{ + int ret = 0; + u32 vlan_id = 0; + + vlan_id = ROCE_GID_SET_VLAN_32BIT_VLAID(((u32)rdma_vlan_dev_vlan_id(netdev))); + dev_info(rdev->hwdev_hdl, "[ROCE] %s: enter roce3_add_vlan_device_mac, vlan_id(0x%x), func_id(%d)\n", __func__, + vlan_id, rdev->glb_func_id); + ret = + roce3_add_mac_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, vlan_id, rdev->glb_func_id, rdev->glb_func_id); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to set vlan device mac, vlan_id(0x%x), func_id(%d)\n", + __func__, vlan_id, rdev->glb_func_id); + return ret; + } + + roce3_add_ipsu_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, vlan_id, rdev->glb_func_id, + hinic3_er_id(rdev->hwdev)); + +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + ret = roce3_add_bond_vlan_slave_mac(rdev, (u8 *)netdev->dev_addr, (u16)vlan_id); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to set bond vlan slave mac, vlan_id(0x%x), func_id(%d)\n", + __func__, vlan_id, rdev->glb_func_id); + goto err_add_bond_vlan_slave_mac; + } + } +#endif + + return ret; + +#ifdef ROCE_BONDING_EN +err_add_bond_vlan_slave_mac: + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, (u8 *)netdev->dev_addr, vlan_id, rdev->glb_func_id, + hinic3_er_id(rdev->hwdev)); + + (void)hinic3_del_mac(rdev->hwdev, (u8 *)netdev->dev_addr, (u16)vlan_id, rdev->glb_func_id, HINIC3_CHANNEL_ROCE); + + return ret; +#endif +} + +void roce3_del_real_device_mac(struct roce3_device *rdev) +{ + u32 vlan_id = 0; +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + roce3_del_bond_real_slave_mac(rdev); + } +#endif + +#ifndef ROCE_VROCE_EN + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, rdev->mac, vlan_id, rdev->glb_func_id, hinic3_er_id(rdev->hwdev)); +#else + /* vroce uses vni to filt invalid packets */ + (void)roce3_get_vni_by_func_id(rdev->hwdev, rdev->glb_func_id, &vlan_id); + + (void)roce3_del_mac_tbl_mac_entry(rdev->hwdev, rdev->mac, vlan_id, rdev->glb_func_id, rdev->glb_func_id); +#endif +} + +void roce3_del_vlan_device_mac(struct roce3_device *rdev, struct roce3_vlan_dev_list *old_list) +{ +#ifdef ROCE_BONDING_EN + if (roce3_bond_is_active(rdev)) { + roce3_del_bond_vlan_slave_mac(rdev, old_list->mac, (u16)old_list->vlan_id); + } +#endif + + roce3_del_ipsu_tbl_mac_entry(rdev->hwdev, old_list->mac, old_list->vlan_id, rdev->glb_func_id, + hinic3_er_id(rdev->hwdev)); + + (void)roce3_del_mac_tbl_mac_entry(rdev->hwdev, old_list->mac, old_list->vlan_id, rdev->glb_func_id, + rdev->glb_func_id); +} + +void roce3_event_up_extend(struct roce3_device *rdev) +{ + if (test_and_set_bit(ROCE3_PORT_EVENT, &rdev->status) == 0) { + roce3_ifconfig_up_down_event_report(rdev, IB_EVENT_PORT_ACTIVE); + } +} + +#endif /* PANGEA_NOF */ diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_qp_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_qp_extension.c new file mode 100755 index 000000000..a101f7dcd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_qp_extension.c @@ -0,0 +1,251 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_extension.c + * Version : v1.1 + * Created : 2021/12/18 + * Last Modified : 2021/12/18 + * Description : Define standard kernel QP realted function prototype. + */ + +#include "roce_qp_extension.h" +#include "cfg_mgmt_mpu_cmd_defs.h" + +#ifdef ROCE_EXTEND +#include "roce_ctx_api.h" +#include "roce_pd.h" +#endif + +int to_roce3_qp_type(enum ib_qp_type qp_type) +{ + switch (qp_type) { + case IB_QPT_RC: + return ROCE_QP_ST_RC; + + case IB_QPT_UC: + return ROCE_QP_ST_UC; + + case IB_QPT_UD: + return ROCE_QP_ST_UD; + + case IB_QPT_XRC_INI: + case IB_QPT_XRC_TGT: + return ROCE_QP_ST_XRC; + + case IB_QPT_GSI: + return ROCE_QP_ST_UD; + + default: + return -1; + } +} + +bool roce3_check_qp_modify_ok(enum ib_qp_state cur_state, enum ib_qp_state next_state, enum ib_qp_type type, + enum ib_qp_attr_mask mask, enum rdma_link_layer ll) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) \ + || defined(OFED_MLNX_5_8) + return ib_modify_qp_is_ok(cur_state, next_state, type, mask); +#else + return ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll); +#endif +} + +#ifndef PANGEA_NOF +int roce3_create_qp_pre_ext(struct roce3_device *rdev, struct roce3_qp *rqp, struct ib_qp_init_attr *init_attr) +{ + return 0; +} + +int roce3_create_qp_user_pre_ext(struct ib_qp_init_attr *init_attr, struct roce3_qp *rqp, u32 *qpn) +{ + *qpn = ROCE_QP_INVLID_QP_NUM; + + return 0; +} + +int roce3_create_qp_user_post_ext(struct ib_pd *ibpd, struct roce3_device *rdev, struct roce3_qp *rqp, + struct ib_qp_init_attr *init_attr) +{ + return 0; +} + +int roce3_qp_modify_cmd_ext(cqm_cmd_buf_s *cqm_cmd_inbuf, struct roce3_qp *rqp, roce_verbs_qp_attr_s *qp_attr, + u32 optpar) +{ + return 0; +} + +bool roce3_need_qpn_lb1_consistent_srqn(const struct roce3_qp *rqp, const struct roce3_device *rdev, + const struct ib_qp_init_attr *init_attr) +{ + if (init_attr->srq == NULL) { + return false; + } + + if ((rdev->cfg_info.scence_id == SCENES_ID_CLOUD) || + (rdev->cfg_info.scence_id == SCENES_ID_COMPUTE_ROCE) || + (rdev->cfg_info.scence_id == SCENES_ID_COMPUTE_STANDARD)) { + return true; + } + + return false; +} + +int roce3_is_qp_normal(struct roce3_qp *rqp, struct ib_qp_init_attr *init_attr) +{ + return 1; +} + +#ifdef ROCE_EXTEND +static struct roce3_qp *roce3_cdev_lookup_and_check_rqp(struct roce3_device *rdev, u32 qpn) +{ + cqm_object_s *cqm_obj_qp = NULL; + struct roce3_qp *rqp = NULL; + + cqm_obj_qp = cqm_object_get(rdev->hwdev, CQM_OBJECT_SERVICE_CTX, qpn, false); + if (cqm_obj_qp == NULL) { + pr_err("[ROCE, ERR] %s: Can't find rqp according to qpn(0x%x), func_id(%d)\n", __func__, qpn, + rdev->glb_func_id); + return NULL; + } + + rqp = cqmobj_to_roce_qp(cqm_obj_qp); + hiudk_cqm_object_put(rdev->hwdev, cqm_obj_qp); + + if (rqp->qpn >= QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: qpn[%u] more than sqpc num offset(%d) for sqpc.\n", __func__, + rqp->qpn, QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC); + return NULL; + } + + return rqp; +} + +static int roce3_alloc_sqpc(struct roce3_device *rdev, struct roce3_qp *rqp, struct roce3_vbs_qp *vbs_rqp) +{ + cqm_qpc_mpt_s *qpc_info = NULL; + + /* Call the CQM interface to allocate QPNs and QPCs */ + /* For SQPC, do not need to allocate QPN, QPN is directly spcified in rsvd segment */ + qpc_info = cqm_object_qpc_mpt_create(rdev->hwdev, SERVICE_T_ROCE, CQM_OBJECT_SERVICE_CTX, + rdev->rdma_cap.dev_rdma_cap.roce_own_cap.qpc_entry_sz, NULL, rqp->qpn + QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC, + false); + if (qpc_info == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: Failed to create qpc by cqm object, func_id(%d), qpn(%u)\n", + __func__, rdev->glb_func_id, rqp->qpn + QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC); + return -ENOMEM; + } + + if (qpc_info->xid != (rqp->qpn + QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC)) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: Create qpc error, func_id(%d), expect qpn(%d), actual qpn(%d)\n", + __func__, rdev->glb_func_id, rqp->qpn + QPC_ROCE_VBS_QPC_OFFSET_FOR_SQPC, qpc_info->xid); + hiudk_cqm_object_delete(rdev->hwdev, &(qpc_info->object)); + return -EFAULT; + } + + vbs_rqp->vbs_sqpc_info = qpc_info; + rqp->vbs_qp_ptr = (void *)vbs_rqp; + + return 0; +} + +long roce3_set_qp_ext_attr(struct roce3_device *rdev, void *buf) +{ + int ret; + struct roce3_qp *rqp = NULL; + struct roce3_set_qp_ext_attr_cmd cmd; + struct roce_qp_context *context = NULL; + + ret = (int)copy_from_user(&cmd, buf, sizeof(cmd)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy data from user\n", __func__); + return (long)ret; + } + + rqp = roce3_cdev_lookup_and_check_rqp(rdev, cmd.qpn); + if (rqp == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to look up rqp\n", __func__); + return -EINVAL; + } + + context = (struct roce_qp_context *)((void *)rqp->qpc_info->vaddr); + if (((cmd.attr_mask) & ROCE_QP_VBS_FLAG) != 0) { /* IBV_QP_VBS_OSD_FLAG */ + context->sw_seg.ucode_seg.common.dw0.bs.ulp_type = ROCE_ULP_VBS; + } + + return (long)ret; +} + +long roce3_vbs_create_sqpc(struct roce3_device *rdev, void *buf) +{ + struct roce3_modify_qp_vbs_cmd cmd; + struct roce3_vbs_qp *vbs_rqp = NULL; + struct roce3_qp *rqp = NULL; + struct roce3_pd *pd = NULL; + int ret; + + ret = (int)copy_from_user(&cmd, buf, sizeof(cmd)); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to copy data from user\n", __func__); + return (long)ret; + } + + rqp = roce3_cdev_lookup_and_check_rqp(rdev, cmd.qpn); + if (rqp == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE, ERR] %s: Failed to look up rqp\n", __func__); + return -EINVAL; + } + + vbs_rqp = (struct roce3_vbs_qp *)kzalloc(sizeof(*vbs_rqp), GFP_KERNEL); + if (vbs_rqp == NULL) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: Failed to alloc vbs_rqp, func_id(%d)\n", __func__, + rdev->glb_func_id); + return -ENOMEM; + } + + pd = roce3_get_pd(rqp); + ret = roce3_db_map_user(to_roce3_ucontext(pd->ibpd.uobject->context), cmd.ci_record_addr, &vbs_rqp->db); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: Failed to map db page to user, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto free_rqp; + } + + ret = roce3_alloc_sqpc(rdev, rqp, vbs_rqp); + if (ret != 0) { + dev_err(rdev->hwdev_hdl, "[ROCE_VBS, ERR] %s: Failed to alloc sqpc, func_id(%d)\n", __func__, + rdev->glb_func_id); + goto free_rqp; + } + + return 0; + +free_rqp: + kfree(vbs_rqp); + + return (long)ret; +} +#endif + +#endif /* !PANGEA_NOF */ + +#ifndef ROCE_CHIP_TEST +void roce3_set_qp_dif_attr(struct roce3_qp *rqp, const struct ib_qp_init_attr *init_attr, + const struct roce3_device *rdev) +{ + if (((unsigned int)init_attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) != 0) { + rqp->signature_en = true; + dev_info(rdev->hwdev_hdl, "[ROCE] %s: func(%d) qp(%u) roce3_create_qp signature_en.\n", __func__, + rdev->glb_func_id, rqp->qpn); + } + return; +} +#endif + +#ifndef ROCE_VBS_EN +int roce3_qp_modify_pre_extend(struct roce3_qp *rqp, struct ib_qp_attr *attr, int attr_mask, struct ib_udata *udata) +{ + return 0; +} +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_qp_post_send_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_qp_post_send_extension.c new file mode 100644 index 000000000..14005a04d --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_qp_post_send_extension.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_qp_post_send_standard.c + * Version : v1.2 + * Created : 2021/8/20 + * Last Modified : 2021/11/23 + * Description : Define standard kernel post_send realted function prototype. + */ + +#include "roce_qp_post_send_extension.h" +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 19, 90)) \ + || (LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0)) || defined(OFED_MLNX_5_8) +int roce3_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr) +#else +int roce3_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, struct ib_send_wr **bad_wr) +#endif +{ + return roce3_post_send_standard(ibqp, (const struct ib_send_wr *)wr, (const struct ib_send_wr **)bad_wr); +} diff --git a/drivers/infiniband/hw/hiroce3/extension/roce_srq_extension.c b/drivers/infiniband/hw/hiroce3/extension/roce_srq_extension.c new file mode 100644 index 000000000..a9736d10e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/extension/roce_srq_extension.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : roce_srq_extension.c + * Version : v1.0 + * Created : 2021/12/7 + * Last Modified : 2021/12/24 + * Description : The definition of RoCE SRQ module standard callback functions. + */ + +#include "roce_srq_extension.h" + +#ifndef ROCE_CHIP_TEST +void roce3_srq_container_init(struct ib_srq_init_attr *init_attr, struct roce3_srq *rsrq, struct roce3_device *rdev) +{ + rsrq->xrc_en = (init_attr->srq_type == IB_SRQT_XRC); + + if (rsrq->xrc_en != 0) { + rsrq->container_flag = rdev->cfg_info.srq_container_en; + } + + rsrq->container_mode = + (rsrq->xrc_en != 0) ? rdev->cfg_info.xrc_srq_container_mode : rdev->cfg_info.srq_container_mode; + rsrq->container_warn_th = roce3_calculate_cont_th(init_attr->attr.srq_limit); + rsrq->rqe_cnt_th = rdev->cfg_info.warn_th; + rsrq->container_size = roce3_get_container_sz(rsrq->container_mode); +} +#endif + +#ifndef PANGEA_NOF +void roce3_create_user_srq_update_ext(u32 *cqn, u32 srqn) +{ + return; +} +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.c b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.c new file mode 100644 index 000000000..7f8229ece --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.c @@ -0,0 +1,148 @@ +/* + * Huawei HiNIC PCI Express Linux driver + * Copyright(c) 2017 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + */ +#define pr_fmt(fmt) KBUILD_MODNAME ": [NIC]" fmt + +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/etherdevice.h> +#include <linux/if_vlan.h> +#include <linux/ethtool.h> +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/pci.h> +#include <linux/netdevice.h> +#include <linux/module.h> + +#include "ossl_knl.h" +#include "hinic3_crm.h" +#include "hinic3_hw.h" +#include "hinic3_common.h" +#include "hinic3_nic.h" +#include "hisec_mpu_cmd.h" +#include "hisec_mpu_cmd_defs.h" +#include "hisec_cfg.h" + +static int hisec_send_msg_to_mpu_sync(void *hwdev, u8 cmd, void *buf_in, + u16 in_size, void *buf_out, + u16 *out_size) +{ + /* todo:: vf need to mpu com or not ? */ + return hinic3_msg_to_mgmt_sync(hwdev, HINIC3_MOD_CRYPT, cmd, buf_in, + in_size, buf_out, out_size, + 0, HINIC3_CHANNEL_CRYPT); +} + +int hisec_set_ipsec_offload_mode(void *hwdev, u8 offload_mode) +{ + struct hinic3_nic_io *nic_io = NULL; + struct hisec_cmd_ipsec_offload_mode ipsec_cfg; + u16 out_size = sizeof(ipsec_cfg); + int err; + + if (!hwdev) + return -EINVAL; + + nic_io = hinic3_get_service_adapter(hwdev, SERVICE_T_NIC); + if (!nic_io) + return -EINVAL; + + memset(&ipsec_cfg, 0, sizeof(ipsec_cfg)); + ipsec_cfg.func_id = hinic3_global_func_id(hwdev); + ipsec_cfg.offload_mode = offload_mode; + + err = hisec_send_msg_to_mpu_sync(hwdev, + HISEC_MPU_CMD_SET_IPSEC_OFFLOAD_MODE, + &ipsec_cfg, sizeof(ipsec_cfg), + &ipsec_cfg, &out_size); + if (err || !out_size || ipsec_cfg.msg_head.status) { + nic_err(nic_io->dev_hdl, "Failed to set ipsec offload mode, err: %d, status: 0x%x, out size: 0x%x\n", + err, ipsec_cfg.msg_head.status, out_size); + return -EINVAL; + } + + return 0; +} + +int hisec_get_crypto_stats(void *hwdev, struct hisec_crypto_stats *stats) +{ + struct hisec_cmd_cryptodev_stats cdev_stats; + u16 out_size = sizeof(cdev_stats); + struct hinic3_nic_io *nic_io = NULL; + int err; + + if (!hwdev || !stats) + return -EINVAL; + + nic_io = hinic3_get_service_adapter(hwdev, SERVICE_T_NIC); + if (!nic_io) + return -EINVAL; + + memset(&cdev_stats, 0, sizeof(cdev_stats)); + + err = hisec_send_msg_to_mpu_sync(hwdev, HISEC_MPU_CMD_GET_CRYPTO_STATS, + &cdev_stats, sizeof(cdev_stats), + &cdev_stats, &out_size); + if (err || !out_size || cdev_stats.msg_head.status) { + nic_err(nic_io->dev_hdl, "Failed to get cryptodev statistics, err: %d, status: 0x%x, out size: 0x%x\n", + err, cdev_stats.msg_head.status, out_size); + return -EFAULT; + } + + memcpy(stats, &cdev_stats.stats, sizeof(*stats)); + + return 0; +} + +int hisec_flush_ipsec_resource(void *hwdev, u32 flush_flag) +{ + struct hinic3_nic_io *nic_io = NULL; + struct hinic3_cmd_buf *cmd_buf = NULL; + hisec_cmd_flush_ipsec_res_s *flush_buf = NULL; + int ret = 0; + u64 out_param = 0; + + if (!hwdev) + return -EINVAL; + + nic_io = hinic3_get_service_adapter(hwdev, SERVICE_T_NIC); + if (!nic_io) + return -EINVAL; + + cmd_buf = hinic3_alloc_cmd_buf(hwdev); + if (!cmd_buf) { + sdk_err(nic_io->dev_hdl, "Failed to alloc cmd buf\n"); + return -ENOMEM; + } + + cmd_buf->size = sizeof(*flush_buf); + flush_buf = (hisec_cmd_flush_ipsec_res_s *)cmd_buf->buf; + flush_buf->func_id = cpu_to_be16(hinic3_global_func_id(hwdev)); + flush_buf->flush_flag = cpu_to_be32(flush_flag); + flush_buf->cmdhdr.dw0.bs.cmd_type = HISEC_NPU_CMD_FLUSH_IPSEC_RES; + flush_buf->cmdhdr.dw0.value = cpu_to_be32(flush_buf->cmdhdr.dw0.value); + + ret = hinic3_cmdq_direct_resp(hwdev, HINIC3_MOD_CRYPT, + HISEC_NPU_CMD_FLUSH_IPSEC_RES, cmd_buf, + &out_param, 0, HINIC3_CHANNEL_CRYPT); + if (ret || out_param) { + sdk_err(nic_io->dev_hdl, "Failed to flush IPsec res, ret: %d, out_param: 0x%llx\n", + ret, out_param); + ret = -EFAULT; + } + + hinic3_free_cmd_buf(hwdev, cmd_buf); + + return ret; +} diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.h b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.h new file mode 100644 index 000000000..2d1e56d09 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_cfg.h @@ -0,0 +1,26 @@ +/* + * Huawei HiNIC PCI Express Linux driver + * Copyright(c) 2017 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + */ + +#ifndef HISEC_CFG_H +#define HISEC_CFG_H + +#include "hinic3_cqm.h" +#include "hisec_mpu_cmd_defs.h" + +int hisec_flush_ipsec_resource(void *hwdev, u32 flush_flag); +int hisec_set_ipsec_offload_mode(void *hwdev, u8 offload_mode); +int hisec_get_crypto_stats(void *hwdev, struct hisec_crypto_stats *stats); + +#endif diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.c b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.c new file mode 100644 index 000000000..2c450b69f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * Description: Source File, hisec hwrand + * Create: 2023/02/02 + */ +#include <linux/types.h> +#include <linux/cdev.h> +#include <linux/device.h> +#include <linux/kdebug.h> +#include <linux/rtnetlink.h> +#include <linux/proc_fs.h> +#include <linux/miscdevice.h> + +#include "hinic3_hw.h" + +#include "hisec_npu_cmd.h" +#include "hisec_npu_cmd_defs.h" +#include "hisec_hwrand.h" + +/* Register this as a misc driver */ +#define HW_RAND_PATH "/dev/hwrand" +#define HW_RAND_CLASS "hwrand_class" +#define HW_RAND_NAME "hwrand" + +#define HW_RAND_CMDQ_MAX_BYTES 128 +#define HW_RAND_CMDQ_MIN_BYTES 16 +#define HW_RAND_READ_MAX_BYTES 256 + +#define HISEC_CDEV_CLASS_MODE ((umode_t)(S_IRUGO|S_IWUSR)) + +static struct hinic3_hwdev *ppf_hwdev; +static atomic_t g_hwrand_ref_cnt; +static dev_t g_dev_id = {0}; +/*lint -save -e104 -e808*/ +static struct class *g_hwrand_class; +/*lint -restore*/ +static struct cdev g_hwrand_cdev; + +static int file_open(struct inode* node, struct file* file) +{ + return 0; +} + +static int file_close(struct inode* inode, struct file* file) +{ + return 0; +} + +static int hisec_get_trng_from_npu(struct hinic3_hwdev *hwdev, size_t count, char *random_data) +{ + int ret = 0; + size_t data_len; + struct hinic3_cmd_buf *cmd_buf = NULL; + hisec_cmd_trng_module_s *trng_cmd = NULL; + + cmd_buf = hinic3_alloc_cmd_buf(hwdev); + if (!cmd_buf) { + pr_err("Allocate cmd buf failed.\n"); + return -ENOMEM; + } + + cmd_buf->size = sizeof(hisec_cmd_trng_module_s); + trng_cmd = (hisec_cmd_trng_module_s *)cmd_buf->buf; + trng_cmd->cmdhdr.dw0.bs.cmd_type = HISEC_NPU_CMD_HW_RANDOM; + trng_cmd->cmdhdr.dw0.value = cpu_to_be32(trng_cmd->cmdhdr.dw0.value); + + do { + data_len = (count > HW_RAND_CMDQ_MAX_BYTES) ? HW_RAND_CMDQ_MAX_BYTES: count; + trng_cmd->length = (u32)ALIGN(data_len, HW_RAND_CMDQ_MIN_BYTES); + trng_cmd->length = cpu_to_be32(trng_cmd->length); + + ret = hinic3_cmdq_detail_resp(hwdev, HINIC3_MOD_CRYPT, HISEC_NPU_CMD_HW_RANDOM, cmd_buf, + cmd_buf, NULL, 0, HINIC3_CHANNEL_CRYPT); + if (ret != 0) { + break; + } + + memcpy(random_data, (trng_cmd->resp).data_out, data_len); + random_data += data_len; + + count -= data_len; + } while (count > 0); + + hinic3_free_cmd_buf(hwdev, cmd_buf); + return ret; +} + +static ssize_t file_read(struct file* file, char __user *buff, size_t count, loff_t *off) +{ + int err; + u32 *random_data = NULL; + + if (count > HW_RAND_READ_MAX_BYTES) { + pr_err("Invalid length"); + return 0; + } + + random_data = (u32 *)vmalloc(HW_RAND_READ_MAX_BYTES); + if (random_data == NULL) { + pr_err("Vmalloc failed."); + return 0; + } + err = hisec_get_trng_from_npu(ppf_hwdev, count, (char *)random_data); + if (err != 0) { + pr_err("get hw rand from npu failed, err 0x%x.\n", err); + vfree(random_data); + return 0; + } + + if (copy_to_user(buff, random_data, (u32)count) != 0) { + pr_err("hw rand copy to user failed!"); + vfree(random_data); + return 0; + } + + vfree(random_data); + return (ssize_t)count; +} + +/* Supported driver operations */ +static const struct file_operations hw_rand_fops = { + .open = file_open, + .release = file_close, + .read = file_read +}; + +static char *hisec_cdev_class_devnode(struct device *dev, umode_t *mode) +{ + if (mode != NULL) + *mode = HISEC_CDEV_CLASS_MODE; + return NULL; +} + +int hisec_trng_init(struct hinic3_hwdev *hwdev) +{ + struct device *pdevice = NULL; + int err; + + atomic_inc(&g_hwrand_ref_cnt); + if (g_hwrand_ref_cnt.counter != 1) { + /* already initialized */ + return 0; + } + ppf_hwdev = hwdev; + + err = alloc_chrdev_region(&g_dev_id, 0, 1, HW_RAND_NAME); + if (err) { + pr_err("Register hwrand failed(0x%x)\n", err); + goto alloc_chdev_fail; + } + + /* Create equipment */ + /*lint -save -e160*/ + g_hwrand_class = class_create(THIS_MODULE, HW_RAND_CLASS); + /*lint -restore*/ + if (IS_ERR(g_hwrand_class)) { + pr_err("Create hwrand_class fail\n"); + err = -EFAULT; + goto class_create_err; + } + + g_hwrand_class->devnode = hisec_cdev_class_devnode; //lint !e10 !e63 !e40 + + /* Initializing the character device */ + cdev_init(&g_hwrand_cdev, &hw_rand_fops); + + /* Add devices to the operating system */ + err = cdev_add(&g_hwrand_cdev, g_dev_id, 1); + if (err < 0) { + pr_err("Add hwrand to operating system fail(0x%x)\n", err); + goto cdev_add_err; + } + + /* Export device information to user space + * (/sys/class/class name/device name) + */ + pdevice = device_create(g_hwrand_class, NULL, + g_dev_id, NULL, HW_RAND_NAME); + if (IS_ERR(pdevice)) { + pr_err("Export hwrand device information to user space fail\n"); + err = -EFAULT; + goto device_create_err; + } + + pr_info("Register hwrand to system succeed\n"); + + return 0; + +device_create_err: + cdev_del(&g_hwrand_cdev); + +cdev_add_err: + class_destroy(g_hwrand_class); + +class_create_err: + g_hwrand_class = NULL; + unregister_chrdev_region(g_dev_id, 1); + +alloc_chdev_fail: + atomic_dec(&g_hwrand_ref_cnt); + + return err; +} + +void hisec_trng_deinit(void) +{ + if (!(g_hwrand_ref_cnt.counter)) { + return; + } + + if ((g_hwrand_ref_cnt.counter) != 1) { + atomic_dec(&g_hwrand_ref_cnt); + return; + } + + if (!g_hwrand_class || IS_ERR(g_hwrand_class)) { + pr_err("Hwrand class is NULL.\n"); + return; + } + + device_destroy(g_hwrand_class, g_dev_id); + cdev_del(&g_hwrand_cdev); + class_destroy(g_hwrand_class); + g_hwrand_class = NULL; + + unregister_chrdev_region(g_dev_id, 1); + + pr_info("Unregister hwrand succeed\n"); +} \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.h b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.h new file mode 100644 index 000000000..ae994ad36 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/hisec_hwrand.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * Description: Header File, hisec hwrand + * Create: 2023/02/02 + */ +#ifndef HISEC_HWRAND_H +#define HISEC_HWRAND_H + +#include "../../hwsdk/crm/hinic3_hwdev.h" + +int hisec_trng_init(struct hinic3_hwdev *hwdev); +void hisec_trng_deinit(void); + +#endif \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_dev.h b/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_dev.h new file mode 100644 index 000000000..f1921737b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_dev.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2021-2022. All rights reserved. + * + * File Name : crypt.h + * Version : v3.0 + * Created : 2023/10/19 + * Last Modified : 2023/10/19 + * Description : The definition of CRYPT MAIN function prototype, macros etc,. in kernel space. + */ +#ifndef CRYPT_DEV_H +#define CRYPT_DEV_H + +#include "hinic3_hw.h" +#include "hinic3_crm.h" +#include "hinic3_hw_cfg.h" +#include "hinic3_lld.h" + +struct crypt_device { + struct hinic3_lld_dev *lld_dev; + struct pci_dev *pdev; + void *hwdev; +}; + +#define HICRYPT_DRV_NAME "crypt_drv" +#define HICRYPT_DRV_AUTHOR "Huawei Technologies CO., Ltd" +#define HICRYPT_DRV_DESC "Huawei(R) Intelligent Network Interface Card, crypt Driver" +#define HICRYPT_DRV_VERSION GLOBAL_VERSION_STR + +#endif // CRYPT_DEV_H \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_main.c b/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_main.c new file mode 100644 index 000000000..d99c13e08 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/linux/kernel/hisec_crypt_main.c @@ -0,0 +1,123 @@ + +/** + * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023. All rights reserved. + * Description: implementation of dtoe driver for hi1822 chip + * Create: 2023-10-19 + * Author: Huawei + */ +#ifdef _PCLINT_ +#include "toe_pclint.h" +#else +#include <linux/module.h> +#include <linux/version.h> +#include <linux/pm.h> +#include "hinic3_hw.h" +#include "hinic3_lld.h" +#endif + +#include "hisec_hwrand.h" +#include "hisec_crypt_dev.h" + +static struct crypt_device *crypt_cryptdev_alloc(struct hinic3_lld_dev *lld_dev) +{ + struct crypt_device *crypt_dev = NULL; + crypt_dev = (struct crypt_device *)kzalloc(sizeof(struct crypt_device), GFP_KERNEL); + crypt_dev->lld_dev = lld_dev; + crypt_dev->hwdev = lld_dev->hwdev; + crypt_dev->pdev = lld_dev->pdev; + + return crypt_dev; +} + +static void crypt_cryptdev_free(struct crypt_device *crypt_dev) +{ + if (crypt_dev != NULL) { + kfree(crypt_dev); + crypt_dev = NULL; + } +} + +static int crypt_cryptserv_init(struct crypt_device *crypt_dev) +{ + int ret = 0; + if (hinic3_func_type(crypt_dev->hwdev) == TYPE_PPF) { + ret = hisec_trng_init(crypt_dev->hwdev); + } + if (ret != 0) { + pr_err("Init trng failed, ret = %d\n", ret); + return ret; + } + return 0; +} + +static void crypt_cryptserv_deinit(struct crypt_device *crypt_dev) +{ + if (hinic3_func_type(crypt_dev->hwdev) == TYPE_PPF) { + hisec_trng_deinit(); + } +} + +static int crypt_probe(struct hinic3_lld_dev *lld_dev, void **uld_dev, char *uld_dev_name) +{ + struct crypt_device *crypt_dev = NULL; + int ret = 0; + crypt_dev = crypt_cryptdev_alloc(lld_dev); + if (crypt_dev == NULL) { + pr_err("Alloc cryptdev failed, crypt_dev = NULL\n"); + goto err_dev_alloc; + } + *uld_dev = (void *)crypt_dev; + ret = crypt_cryptserv_init(crypt_dev); + if (ret != 0) { + pr_err("Init cryptserv failed, ret = %d\n", ret); + goto err_serv_init; + } + return 0; + +err_serv_init: + crypt_cryptdev_free(crypt_dev); +err_dev_alloc: + return -EINVAL; +} + +static void crypt_remove(struct hinic3_lld_dev *lld_dev, void *uld_dev) +{ + struct crypt_device *crypt_dev = NULL; + crypt_dev = (struct crypt_device *)uld_dev; + crypt_cryptserv_deinit(crypt_dev); + crypt_cryptdev_free(crypt_dev); +} + +struct hinic3_uld_info g_crypt_uld_info = { + .probe = crypt_probe, + .remove = crypt_remove, + .suspend = NULL, + .resume = NULL, + .event = NULL, + .ioctl = NULL, +}; + +static int __init crypt_init(void) +{ + int ret = 0; + ret = hinic3_register_uld(SERVICE_T_CRYPT, &g_crypt_uld_info); + if (ret) { + pr_err("Register crypt hinic3 uld failed, ret = %d\n", ret); + return ret; + } + + return 0; +} + +static void __exit crypt_exit(void) +{ + hinic3_unregister_uld(SERVICE_T_CRYPT); +} + +module_init(crypt_init); +module_exit(crypt_exit); + +MODULE_AUTHOR(HICRYPT_DRV_AUTHOR); +MODULE_DESCRIPTION(HICRYPT_DRV_DESC); +MODULE_VERSION(HICRYPT_DRV_VERSION); +MODULE_LICENSE("GPL"); \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/crypt/readme.txt b/drivers/infiniband/hw/hiroce3/host/crypt/readme.txt new file mode 100644 index 000000000..3094243db --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/crypt/readme.txt @@ -0,0 +1 @@ +本目录是主机软件代码中加解密业务实现的代码目录 \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.c new file mode 100644 index 000000000..b1b2cead9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.c @@ -0,0 +1,170 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_buddy.c + Version : Initial Draft + Description : realize the management of buddy +***************************************************************************** */ + +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include "hinic3_hw.h" +#include "hmm_comp.h" +#include "hmm_buddy.h" + + +u32 hmm_buddy_alloc(struct hmm_buddy *buddy, u32 order) +{ + u32 first_index = 0; + u32 cur_order = 0; + u32 cur_bit_num = 0; + + if (buddy == NULL) { + pr_err("%s: Buddy is null\n", __FUNCTION__); + return HMM_INVALID_INDEX; + } + if (order > buddy->max_order) { + pr_err("%s: Order(%d) is bigger than max order(%d)\n", __FUNCTION__, order, buddy->max_order); + return HMM_INVALID_INDEX; + } + spin_lock(&buddy->lock); + + for (cur_order = order; cur_order <= buddy->max_order; ++cur_order) { + if (buddy->num_free[cur_order] != 0) { + cur_bit_num = 1U << (buddy->max_order - cur_order); + first_index = (u32)find_first_bit(buddy->bits[cur_order], (unsigned long)cur_bit_num); + if (first_index < cur_bit_num) { + goto found; + } + } + } + spin_unlock(&buddy->lock); + pr_err("%s: Get a invalid index\n", __FUNCTION__); + return HMM_INVALID_INDEX; + +found: + clear_bit((int)first_index, buddy->bits[cur_order]); + --buddy->num_free[cur_order]; + + while (cur_order > order) { + --cur_order; + first_index <<= 1; + set_bit(first_index ^ 1, buddy->bits[cur_order]); + ++buddy->num_free[cur_order]; + } + first_index <<= order; + spin_unlock(&buddy->lock); + return first_index; +} + +void hmm_buddy_free(struct hmm_buddy *buddy, u32 first_index, u32 order) +{ + u32 tmp_first_index = first_index; + u32 tmp_order = order; + if (buddy == NULL) { + pr_err("%s: Buddy is null\n", __FUNCTION__); + return; + } + if (tmp_order > buddy->max_order) { + pr_err("%s: Order(%d) is bigger than max order(%d)\n", __FUNCTION__, tmp_order, buddy->max_order); + return; + } + tmp_first_index >>= tmp_order; + spin_lock(&buddy->lock); + while (test_bit((int)(tmp_first_index ^ 1), buddy->bits[tmp_order]) != 0) { + clear_bit((int)(tmp_first_index ^ 1), buddy->bits[tmp_order]); + --buddy->num_free[tmp_order]; + tmp_first_index >>= 1; + ++tmp_order; + } + set_bit(tmp_first_index, buddy->bits[tmp_order]); + ++buddy->num_free[tmp_order]; + spin_unlock(&buddy->lock); + return; +} + +static void hmm_buddy_alloc_bitmap_fail(struct hmm_buddy *buddy, u32 i) +{ + u32 j = 0; + for (j = 0; j < i; j++) { + if (is_vmalloc_addr(buddy->bits[j])) { + vfree(buddy->bits[j]); + } else { + kfree(buddy->bits[j]); + } + buddy->bits[j] = NULL; + } + kfree(buddy->bits); + buddy->bits = NULL; + return; +} + +int hmm_buddy_init(struct hmm_buddy *buddy, u32 max_order) +{ + u32 i = 0; + u32 bit_num = 0; + + if (buddy == NULL) { + pr_err("%s: Buddy is null\n", __FUNCTION__); + return -EINVAL; + } + buddy->max_order = max_order; + /*lint -e708*/ + spin_lock_init(&buddy->lock); + /*lint +e708*/ + buddy->num_free = (unsigned int *)kcalloc((unsigned long)(buddy->max_order + 1UL), sizeof(int), GFP_KERNEL); + if (buddy->num_free == NULL) { + pr_err("%s: Alloc memory for buddy->num_free failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + buddy->bits = (unsigned long **)kcalloc((unsigned long)(buddy->max_order + 1UL), sizeof(long *), GFP_KERNEL); + if (buddy->bits == NULL) { + pr_err("%s: Alloc memory for buddy->bits failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + goto alloc_bits_fail; + } + + for (i = 0; i <= buddy->max_order; i++) { + bit_num = (u32)BITS_TO_LONGS(1UL << (buddy->max_order - i)); + buddy->bits[i] = (unsigned long *)kcalloc((unsigned long)bit_num, sizeof(long), GFP_KERNEL | __GFP_NOWARN); + if (buddy->bits[i] == NULL) { + pr_err("%s: Kcalloc memory for buddy->bits[%d] failed, ret(%d)\n", __FUNCTION__, i, -ENOMEM); + buddy->bits[i] = (unsigned long *)vzalloc((unsigned long)bit_num * sizeof(long)); + if (buddy->bits[i] == NULL) { + pr_err("%s: Vzalloc memory for buddy->bits[%d] failed, ret(%d)\n", __FUNCTION__, i, -ENOMEM); + goto alloc_bitmap_fail; + } + } + } + set_bit(0, buddy->bits[buddy->max_order]); + buddy->num_free[buddy->max_order] = 1; + return 0; + +alloc_bitmap_fail: + hmm_buddy_alloc_bitmap_fail(buddy, i); +alloc_bits_fail: + kfree(buddy->num_free); + buddy->num_free = NULL; + return -ENOMEM; +} + +void hmm_buddy_cleanup(struct hmm_buddy *buddy) +{ + u32 i; + + if (buddy == NULL) { + pr_err("%s: Buddy is null\n", __FUNCTION__); + return; + } + for (i = 0; i <= buddy->max_order; i++) { + if (is_vmalloc_addr(buddy->bits[i])) { + vfree(buddy->bits[i]); + } else { + kfree(buddy->bits[i]); + } + buddy->bits[i] = NULL; + } + kfree(buddy->bits); + buddy->bits = NULL; + kfree(buddy->num_free); + buddy->num_free = NULL; + return; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.h b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.h new file mode 100644 index 000000000..858ff780b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_buddy.h @@ -0,0 +1,36 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_buddy.h + Version : Initial Draft + Description : define buddy related macro and structure +***************************************************************************** */ + +#ifndef HMM_BUDDY_H +#define HMM_BUDDY_H + +#include <linux/spinlock.h> +#include <linux/mm.h> + +#if defined(__i386__) +#include <asm/highmem.h> +#endif + +#ifndef HMM_INVALID_INDEX +#define HMM_INVALID_INDEX 0xFFFFFFFF +#endif + +struct hmm_buddy { + unsigned long **bits; /* 指向多级bitmap的内存 */ + unsigned int *num_free; /* 指示各级bitmap中可用的索引个数 */ + u32 max_order; /* 指bitmap的级数 */ + spinlock_t lock; /* buddy的自旋锁 */ +}; + +u32 hmm_buddy_alloc(struct hmm_buddy *buddy, u32 order); +void hmm_buddy_free(struct hmm_buddy *buddy, u32 first_index, u32 order); + +int hmm_buddy_init(struct hmm_buddy *buddy, u32 max_order); +void hmm_buddy_cleanup(struct hmm_buddy *buddy); + + +#endif // HMM_BUDDY_H diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.c new file mode 100644 index 000000000..886788ba9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.c @@ -0,0 +1,165 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_comp.c + Version : Initial Draft + Last Modified : + Description : implement the management of PDID, XRCD, MPT, MTT, RDMARC, + GID and GUID +***************************************************************************** */ + +#include <linux/module.h> +#include <linux/netdevice.h> +#include "hinic3_hw.h" +#include "hmm_comp.h" + + +struct hmm_comp_priv *get_hmm_comp_priv(void *hwdev, u32 service_type) +{ + return (struct hmm_comp_priv *)hinic3_get_service_adapter(hwdev, (enum hinic3_service_type)service_type); +} + +static void assemble_mpt_hw2sw(struct rdma_mpt_hw2sw_inbuf **mpt_hw2sw_inbuf, struct hmm_comp_priv *comp_priv, + cqm_cmd_buf_s *cqm_cmd_inbuf) +{ + *mpt_hw2sw_inbuf = (struct rdma_mpt_hw2sw_inbuf *)cqm_cmd_inbuf->buf; + memset(*mpt_hw2sw_inbuf, 0, sizeof(struct rdma_mpt_hw2sw_inbuf)); + + (*mpt_hw2sw_inbuf)->dmtt_flags = 0; /* 默认按VF踢除cache */ + (*mpt_hw2sw_inbuf)->dmtt_num = 0; + (*mpt_hw2sw_inbuf)->dmtt_cache_line_start = cpu_to_be32(comp_priv->rdma_cap.dmtt_cl_start); + (*mpt_hw2sw_inbuf)->dmtt_cache_line_end = cpu_to_be32(comp_priv->rdma_cap.dmtt_cl_end); + (*mpt_hw2sw_inbuf)->dmtt_cache_line_size = cpu_to_be32(comp_priv->rdma_cap.dmtt_cl_sz); + return; +} + +int hmm_enable_roce_mpt(void *hwdev, cqm_cmd_buf_s *cqm_cmd_inbuf, u16 channel) +{ + int ret; + + ret = cqm_send_cmd_box(hwdev, HINIC3_MOD_ROCE, RDMA_ROCE_CMD_SW2HW_MPT, cqm_cmd_inbuf, NULL, NULL, + RDMA_CMD_TIME_OUT_A, channel); + if (ret != 0) { + if (hinic3_get_heartbeat_status(hwdev) != PCIE_LINK_DOWN) { + pr_err("%s: Send cmd rdma_roce_cmd_sw2hw_mpt failed, ret(%d)\n", __FUNCTION__, ret); + if ((ret == (-ETIMEDOUT)) || (ret == (-EPERM))) { + return -RDMA_CMDQ_TIMEOUT; + } + return -RDMA_CMDQ_ERR; + } + pr_err("%s: Card not present, return err\n", __FUNCTION__); + return -RDMA_CMDQ_ERR; + } + + return 0; +} + +static int hmm_mpt_read_back_test(struct hmm_comp_priv *comp_priv, struct rdma_mpt *mpt) +{ + int retry; + struct rdma_mpt_entry *mpt_entry = NULL; + struct rdma_mpt_entry check_mpt_entry; + + /* 获取Host MPT内容 */ + mpt_entry = (struct rdma_mpt_entry *)mpt->vaddr; + for (retry = 0; retry < RDMA_MAX_RETRY; retry++) { + if (hinic3_get_heartbeat_status(comp_priv->hwdev) == PCIE_LINK_DOWN) { + pr_err("%s: Card not present, return ok\n", __FUNCTION__); + return 0; + } + /* 通过比较MPT State字段,确认芯片操作完成 + * 回读状态正确则跳出,否则强制延迟后继续读取比较，直至循环结束 */ + check_mpt_entry.roce_mpt_ctx.dw2.value = be32_to_cpu(mpt_entry->roce_mpt_ctx.dw2.value); + if (check_mpt_entry.roce_mpt_ctx.dw2.bs.status == RDMA_MPT_STATUS_INVALID) { + return 0; + } +#ifndef _lint + /*lint -e160 -e506*/ + mdelay(RDMA_MS_DELAY); + /*lint +e160 +e506*/ +#endif + } + + pr_err("%s: RoCE mpt state read times(%d), mpt_index(0x%x), state_dw(0x%x)\n", __FUNCTION__, retry, + mpt->mpt_index, mpt_entry->roce_mpt_ctx.dw2.value); + return -RDMA_CMDQ_ERR; +} + +int hmm_disable_roce_mpt(struct hmm_comp_priv *comp_priv, struct rdma_mpt *mpt, u16 channel) +{ + int ret; + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + struct rdma_mpt_hw2sw_inbuf *mpt_hw2sw_inbuf = NULL; + + cqm_cmd_inbuf = cqm_cmd_alloc(comp_priv->hwdev); + if (cqm_cmd_inbuf == NULL) { + pr_err("%s: RoCE alloc cmd_buf failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + cqm_cmd_inbuf->size = (u16)sizeof(struct rdma_mpt_hw2sw_inbuf); + assemble_mpt_hw2sw(&mpt_hw2sw_inbuf, comp_priv, cqm_cmd_inbuf); + mpt_hw2sw_inbuf->com.index = cpu_to_be32(mpt->mpt_index); + mpt_hw2sw_inbuf->com.dw0.bs.cmd_bitmask = (u16)cpu_to_be16(VERBS_CMD_TYPE_MR_BITMASK); + ret = cqm_send_cmd_box(comp_priv->hwdev, HINIC3_MOD_ROCE, RDMA_ROCE_CMD_HW2SW_MPT, cqm_cmd_inbuf, NULL, NULL, + RDMA_CMD_TIME_OUT_A, channel); + if (ret != 0) { + if (hinic3_get_heartbeat_status(comp_priv->hwdev) != PCIE_LINK_DOWN) { + pr_err("%s: Send cmd rdma_roce_cmd_hw2sw_mpt failed, ret(%d)\n", __FUNCTION__, ret); + cqm_cmd_free(comp_priv->hwdev, cqm_cmd_inbuf); + if ((ret == (-ETIMEDOUT)) || (ret == (-EPERM))) { + return -RDMA_CMDQ_TIMEOUT; + } + return -RDMA_CMDQ_ERR; + } + pr_err("%s: Card not present, return ok\n", __FUNCTION__); + cqm_cmd_free(comp_priv->hwdev, cqm_cmd_inbuf); + return 0; + } + cqm_cmd_free(comp_priv->hwdev, cqm_cmd_inbuf); + + ret = hmm_mpt_read_back_test(comp_priv, mpt); + return ret; +} + + +int hmm_modify_roce_mpt(void *hwdev, u32 mpt_index, u32 new_key, u64 length, u64 iova, u16 channel) +{ + cqm_cmd_buf_s *cqm_cmd_inbuf; + struct rdma_mpt_modify_inbuf *mpt_modify_inbuf = NULL; + int ret; + + cqm_cmd_inbuf = cqm_cmd_alloc(hwdev); + if (cqm_cmd_inbuf == NULL) { + pr_err("%s: RoCE alloc cmd_buf failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + cqm_cmd_inbuf->size = (u16)sizeof(struct rdma_mpt_modify_inbuf); + mpt_modify_inbuf = (struct rdma_mpt_modify_inbuf *)cqm_cmd_inbuf->buf; + memset(mpt_modify_inbuf, 0, sizeof(*mpt_modify_inbuf)); + + mpt_modify_inbuf->com.dw0.bs.cmd_bitmask = (u16)cpu_to_be16(VERBS_CMD_TYPE_MR_BITMASK); + mpt_modify_inbuf->com.index = cpu_to_be32(mpt_index); + mpt_modify_inbuf->new_key = cpu_to_be32(new_key); + mpt_modify_inbuf->length = cpu_to_be64(length); + mpt_modify_inbuf->iova = cpu_to_be64(iova); + + ret = cqm_send_cmd_box(hwdev, HINIC3_MOD_ROCE, RDMA_ROCE_CMD_MODIFY_MPT, cqm_cmd_inbuf, NULL, NULL, + RDMA_CMD_TIME_OUT_A, channel); + if (ret != 0) { + if (hinic3_get_heartbeat_status(hwdev) != PCIE_LINK_DOWN) { + pr_err("%s: Send cmd rdma_roce_cmd_modify_mpt failed, ret(%d)\n", __FUNCTION__, ret); + cqm_cmd_free(hwdev, cqm_cmd_inbuf); + if ((ret == (-ETIMEDOUT)) || (ret == (-EPERM))) { + return -RDMA_CMDQ_TIMEOUT; + } + return -RDMA_CMDQ_ERR; + } + pr_err("%s: Card not present, return ok\n", __FUNCTION__); + cqm_cmd_free(hwdev, cqm_cmd_inbuf); + return 0; + } + + cqm_cmd_free(hwdev, cqm_cmd_inbuf); + + return 0; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.h b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.h new file mode 100644 index 000000000..96293a677 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp.h @@ -0,0 +1,225 @@ +/* Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_comp.h + Version : Initial Draft + Description : define rdma component related macro, structure and interface */ + +#ifndef HMM_COMP_H +#define HMM_COMP_H + +#ifndef ROCE_SERVICE +#include "ossl_knl.h" +#endif +#include <linux/delay.h> +#include <linux/types.h> +#include "roce_hmm_context.h" +#include "hinic3_crm.h" +#include "hinic3_cqm.h" +#include "hinic3_rdma.h" +#include "hmm_buddy.h" +#include "hmm_em.h" + +/* x86 */ +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +#ifndef BYTE_ORDER +#define BYTE_ORDER LITTLE_ENDIAN +#endif + +#define PCIE_LINK_DOWN 0xFFFFFFFF + +#define RDMA_MPT_STATUS_INVALID 0xf +#define RDMA_MPT_STATUS_FREE 0x3 +#define RDMA_MPT_STATUS_VALID 0x1 +#define RDMA_MPT_STATUS_MEM_INIT 0xa + +#define RDMA_MS_DELAY 5 +#define RDMA_MAX_RETRY 200 + +#define RDMA_MPT_DMA_ATTR_IDX 0 +#define RDMA_MPT_SO_RO 0x1 + +#define RDMA_PA_SIZE ((u32)sizeof(dma_addr_t)) + +#define PAGE_SIZE_4k 4096 /* page size is 4K */ +#define PAGE_SHIFT_4K 12 /* page size is 1 left shift 12 */ + +#define PAGE_SIZE_64k (64 * 4096) /* page size is 64K */ +#define PAGE_SHIFT_64K 16 /* page size is 1 left shift 16 */ + +#define PAGE_SIZE_2M (2 * 1024 * 1024) /* page size is 2M */ +#define PAGE_SHIFT_2M 21 /* page size is 1 left shift 21 */ + +#define RDMA_MTT_PA_VALID 0x1 + +#define HMM_MTT_NUM_PER_CACHELINE 32 /* 256B Cache line has 32 records */ + +#define BLOCK_SIZE_DEVIDE_SECTOR 8 /* Chip logic: 8 */ + + +#define MPT_GPA_SIG_LEN 3 + +#define RDMA_CMDQ_ERR 1 +#define RDMA_CMDQ_TIMEOUT 2 + +#ifndef VERBS_CMD_TYPE_MR_BITMASK +#define VERBS_CMD_TYPE_MR_BITMASK (1u << 12) /* verbs_mr_bitmask */ +#endif + +enum { + RDMA_MTT_PAGE_SIZE_4K = 0, + RDMA_MTT_PAGE_SIZE_64K = 1, + RDMA_MTT_PAGE_SIZE_2M = 2 +}; + +#ifdef __EMU_X86__ +enum { + RDMA_CMD_TIME_OUT_A = 30000000, + RDMA_CMD_TIME_OUT_B = 40000000, + RDMA_CMD_TIME_OUT_C = 50000000 +}; +#else +enum { + RDMA_CMD_TIME_OUT_A = 30000, + RDMA_CMD_TIME_OUT_B = 40000, + RDMA_CMD_TIME_OUT_C = 50000 +}; +#endif + +enum rdma_mr_mw { + RDMA_MPT_MW = 0, + RDMA_MPT_MR = 1 +}; + +enum rdma_roce_cmd { + RDMA_ROCE_CMD_SW2HW_MPT = 0x70, + RDMA_ROCE_CMD_HW2SW_MPT = 0x71, + RDMA_ROCE_CMD_MODIFY_MPT = 0x72, + RDMA_ROCE_CMD_QUERY_MPT = 0x73, + RDMA_ROCE_CMD_FLUSH_TPT = 0x74, + RDMA_ROCE_CMD_SYNC_TPT = 0x75 +}; + + +enum mtt_layer { + RDMA_MTT_NO_LAYER = -1, /* dma mr needs no mtt */ + RDMA_MTT_ZERO_LAYER = 0, /* 1 page mr has 0 level mtt */ + RDMA_MTT_ONE_LAYER = 1, + RDMA_MTT_TWO_LAYER = 2, + RDMA_MTT_THREE_LAYER = 3 +}; + +typedef struct rdma_verbs_cmd_com { + union { + __be32 value; + + struct { + __be32 version : 8; + __be32 rsvd : 8; + __be32 cmd_bitmask : 16; + } bs; + } dw0; + + __be32 index; +} rdma_verbs_cmd_com_s; + +struct hmm_service_cap { + struct dev_rdma_svc_cap dev_rdma_cap; + u8 log_mtt; /* 1. the number of MTT PA must be integer power of 2 + * 2. represented by logarithm. Each MTT table can + * contain 1, 2, 4, 8, and 16 PA) + */ + /* todo: need to check whether related to max_mtt_seg */ + u32 num_mtts; /* Number of MTT table (4M), + * is actually MTT seg number + */ + /* todo: max value needs to be confirmed */ + /* MTT table number of Each MTT seg(3) */ + u32 log_mtt_seg; + u32 mtt_entry_sz; /* MTT table size 8B, including 1 PA(64bits) */ + u32 mpt_entry_sz; /* MPT table size (64B) */ + + u32 dmtt_cl_start; + u32 dmtt_cl_end; + u32 dmtt_cl_sz; + u32 mtt_page_size; /* 4K, 8K, 16K, 32K */ + u32 mtt_page_shift; /* 12, 13, 14, 15 */ +}; + + +struct hmm_comp_priv { + struct rdma_comp_resource rdma_comp_res; /* gid & guid */ + struct hmm_buddy mtt_buddy; + struct hmm_em_table mtt_em_table; + void *hwdev; + struct pci_dev *pdev; + struct rdma_mr rsvd_lkey; + struct rdma_mr fixed_mr; + u32 mtt_page_size; /* 4K, 8K, 16K, 32K */ + u32 mtt_page_shift; /* 12, 13, 14, 15 */ + + struct hmm_service_cap rdma_cap; +}; + +typedef struct rdma_mpt_entry { + struct roce_mpt_context roce_mpt_ctx; +} rdma_mpt_entry_s; + +struct rdma_mpt_sw2hw_inbuf { + rdma_verbs_cmd_com_s com; + struct rdma_mpt_entry mpt_entry; +}; + +struct rdma_mpt_hw2sw_inbuf { + rdma_verbs_cmd_com_s com; + + __be32 dmtt_flags; + __be32 dmtt_num; + __be32 dmtt_cache_line_start; + __be32 dmtt_cache_line_end; + __be32 dmtt_cache_line_size; +}; + +struct rdma_mpt_modify_inbuf { + rdma_verbs_cmd_com_s com; + __be32 new_key; + __be64 length; + __be64 iova; +}; + + +/* for llt to set stub */ +int hmm_disable_roce_mpt(struct hmm_comp_priv *comp_priv, struct rdma_mpt *mpt, u16 channel); + +int hmm_modify_roce_mpt(void *hwdev, u32 mpt_index, u32 new_key, u64 length, u64 iova, u16 channel); + +struct hmm_comp_priv *get_hmm_comp_priv(void *hwdev, u32 service_type); + +int hmm_rdma_mpt_alloc(void *hwdev, struct rdma_mpt *mpt, u32 service_type); + +int hmm_enable_roce_mpt(void *hwdev, cqm_cmd_buf_s *cqm_cmd_inbuf, u16 channel); + +#ifdef RDMA_SIGN_MTT_EN +u64 hmm_gen_mtt_sign(u64 mtt_base_gpa, enum mtt_data_type_e type); + +#define RDMA_CMTT_SIGN_MASK 0x7ff +#define RDMA_CMTT_SIGN_SHIFT0 3 +#define RDMA_CMTT_SIGN_SHIFT1 14 +#define RDMA_CMTT_SIGN_SHIFT2 25 + +#define RDMA_DMTT_SIGN_MASK 0x3ff + +#define RDMA_DMTT_ADD_SHIFT0 7 +#define RDMA_DMTT_SIGN_SHIFT0 3 +#define RDMA_DMTT_SIGN_SHIFT1 6 +#define RDMA_DMTT_SIGN_SHIFT2 16 +#define RDMA_DMTT_SIGN_SHIFT3 26 + +#endif + +#endif // HMM_COMP_H \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_init.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_init.c new file mode 100644 index 000000000..85c342edd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_init.c @@ -0,0 +1,131 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_comp_init.c + Version : Initial Draft + Last Modified : + Description : implement the management of MPT, MTT +***************************************************************************** */ +#include <linux/module.h> +#include <linux/netdevice.h> +#include "hinic3_hw.h" +#include "hinic3_hw_cfg.h" +#include "hinic3_crm.h" + +#include "hmm_comp.h" +#include "hinic3_hmm.h" + +#define ROCE_MAX_RDMA_RC_EXTEND 384 /* 扩展表为12K */ + +u32 g_mtt_page_size = 0U; +module_param(g_mtt_page_size, uint, S_IRUGO); +MODULE_PARM_DESC(g_mtt_page_size, "0:4K,1:64K,2:2M,default:4K"); + +static int hmm_init_table(void *hwdev, struct hmm_comp_priv *comp_priv, u32 srv_type) +{ + int ret; + + ret = hmm_init_mtt_table(comp_priv); + if (ret != 0) { + pr_err("%s: Initialize mtt's table failed, ret(%d)\n", __FUNCTION__, ret); + kfree(comp_priv); + return ret; + } + + ret = hinic3_register_service_adapter((void *)hwdev, (void *)comp_priv, (enum hinic3_service_type)srv_type); + if (ret != 0) { + pr_err("%s: put hmm_comp_res failed, ret(%d)\n", __FUNCTION__, ret); + goto err_init; + } + pr_info("%s: Hmm init resource successful\n", __FUNCTION__); + return 0; + +err_init: + hmm_cleanup_mtt_table(comp_priv); + kfree(comp_priv); + return ret; +} + +void hmm_cleanup_resource(void *hwdev, u32 service_type) +{ + struct rdma_service_cap rdma_cap; + struct hmm_comp_priv *comp_priv = NULL; + + if (hwdev == NULL) { + pr_err("%s: Hwdev is null\n", __FUNCTION__); + return; + } + + if (!hinic3_support_rdma(hwdev, &rdma_cap)) { + pr_err("%s: Not support rdma service\n", __FUNCTION__); + return; + } + + comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return; + } + + hmm_cleanup_mtt_table(comp_priv); + + kfree(comp_priv); + + hinic3_unregister_service_adapter((void *)hwdev, (enum hinic3_service_type)service_type); + + pr_info("%s: Rdma cleanup resource successful", __FUNCTION__); + + return; +} + +int hmm_init_resource(void *hwdev, u32 service_type) +{ + struct hmm_comp_priv *comp_priv = NULL; + struct rdma_service_cap rdma_cap; + int ret; + + if (hwdev == NULL) { + pr_err("%s: Hwdev is null\n", __FUNCTION__); + return -EINVAL; + } + if (!hinic3_support_rdma(hwdev, &rdma_cap)) { + pr_info("%s: Don't support hmm dev\n", __FUNCTION__); + return 0; + } + comp_priv = (struct hmm_comp_priv *)kzalloc(sizeof(struct hmm_comp_priv), GFP_KERNEL); + if (comp_priv == NULL) { + pr_err("%s: Alloc memory for comp_priv failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + comp_priv->hwdev = hwdev; + comp_priv->pdev = (struct pci_dev *)((struct hinic3_hwdev *)hwdev)->pcidev_hdl; + comp_priv->rdma_cap.log_mtt = rdma_cap.log_mtt; + comp_priv->rdma_cap.log_mtt_seg = rdma_cap.log_mtt_seg; + comp_priv->rdma_cap.mtt_entry_sz = rdma_cap.mtt_entry_sz; + comp_priv->rdma_cap.mpt_entry_sz = rdma_cap.mpt_entry_sz; + comp_priv->rdma_cap.num_mtts = rdma_cap.num_mtts; + + comp_priv->rdma_cap.dmtt_cl_start = rdma_cap.dev_rdma_cap.roce_own_cap.dmtt_cl_start; + comp_priv->rdma_cap.dmtt_cl_end = rdma_cap.dev_rdma_cap.roce_own_cap.dmtt_cl_end; + comp_priv->rdma_cap.dmtt_cl_sz = rdma_cap.dev_rdma_cap.roce_own_cap.dmtt_cl_sz; + + switch (g_mtt_page_size) { + case RDMA_MTT_PAGE_SIZE_4K: + comp_priv->mtt_page_size = PAGE_SIZE_4k; /* page size is 4K */ + comp_priv->mtt_page_shift = PAGE_SHIFT_4K; /* page size is 1 left shift 12 */ + break; + case RDMA_MTT_PAGE_SIZE_64K: + comp_priv->mtt_page_size = PAGE_SIZE_64k; /* page size is 64K */ + comp_priv->mtt_page_shift = PAGE_SHIFT_64K; /* page size is 1 left shift 16 */ + break; + case RDMA_MTT_PAGE_SIZE_2M: + comp_priv->mtt_page_size = PAGE_SIZE_2M; /* page size is 2M */ + comp_priv->mtt_page_shift = PAGE_SHIFT_2M; /* page size is 1 left shift 21 */ + break; + default: + comp_priv->mtt_page_size = PAGE_SIZE_4k; /* page size is 4K */ + comp_priv->mtt_page_shift = PAGE_SHIFT_4K; /* page size is 1 left shift 12 */ + break; + } + ret = hmm_init_table(hwdev, comp_priv, service_type); + return ret; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mtt.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mtt.c new file mode 100644 index 000000000..f9478e2c8 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mtt.c @@ -0,0 +1,497 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + + Description : implement the management of MPT, MTT +***************************************************************************** */ + +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "hinic3_rdma.h" +#include "hmm_comp.h" +#include "hmm_mr.h" + +static int hmm_set_mtt_layer(const struct hmm_comp_priv *comp_priv, struct rdma_mtt *mtt, u32 npages) +{ + u32 one_layer_flag = 0; + u64 two_layer_flag = 0; + u64 three_layer_flag = 0; + + one_layer_flag = comp_priv->mtt_page_size / RDMA_PA_SIZE; + two_layer_flag = ((u64)one_layer_flag) * ((u64)one_layer_flag); + three_layer_flag = (u64)one_layer_flag * two_layer_flag; + + if (npages <= 1) { + mtt->mtt_layers = RDMA_MTT_ZERO_LAYER; + return 0; + } else if (npages <= one_layer_flag) { + mtt->mtt_layers = RDMA_MTT_ONE_LAYER; + } else if (npages <= two_layer_flag) { + mtt->mtt_layers = RDMA_MTT_TWO_LAYER; + } else if ((u64)npages <= three_layer_flag) { + mtt->mtt_layers = RDMA_MTT_THREE_LAYER; + } else { + pr_err("%s: Npages(0x%x) over range, ret(%d)\n", __FUNCTION__, npages, -EINVAL); + return -EINVAL; + } + + return 0; +} + +#ifdef RDMA_SIGN_MTT_EN + +u16 hmm_gen_cmtt_sign(u64 mtt_base_gpa) +{ + u16 sign0 = (mtt_base_gpa >> RDMA_CMTT_SIGN_SHIFT0) & RDMA_CMTT_SIGN_MASK; + u16 sign1 = (mtt_base_gpa >> RDMA_CMTT_SIGN_SHIFT1) & RDMA_CMTT_SIGN_MASK; + u16 sign2 = (mtt_base_gpa >> RDMA_CMTT_SIGN_SHIFT2) & RDMA_CMTT_SIGN_MASK; + u16 cmtt_sign = ~(sign0 ^ sign1 ^ sign2); + cmtt_sign &= RDMA_CMTT_SIGN_MASK; + return cmtt_sign; +} + +u16 hmm_gen_dmtt_sign(u64 mtt_base_gpa) +{ + u16 sign0 = ((u16)(mtt_base_gpa >> RDMA_DMTT_SIGN_SHIFT0) << RDMA_DMTT_ADD_SHIFT0) & RDMA_DMTT_SIGN_MASK; + u16 sign1 = (mtt_base_gpa >> RDMA_DMTT_SIGN_SHIFT1) & RDMA_DMTT_SIGN_MASK; + u16 sign2 = (mtt_base_gpa >> RDMA_DMTT_SIGN_SHIFT2) & RDMA_DMTT_SIGN_MASK; + u16 sign3 = (mtt_base_gpa >> RDMA_DMTT_SIGN_SHIFT3) & RDMA_DMTT_SIGN_MASK; + u16 dmtt_sign = ~(sign0 ^ sign1 ^ sign2 ^ sign3); + dmtt_sign &= RDMA_DMTT_SIGN_MASK; + return dmtt_sign; +} + + +u64 hmm_gen_mtt_sign(u64 mtt_base_gpa, enum mtt_data_type_e type) +{ + if (type == MTT_CMTT_TYPE) { + return hmm_gen_cmtt_sign(mtt_base_gpa); + } + return (u64)hmm_gen_dmtt_sign(mtt_base_gpa) << 1; +} + +#endif + +static int hmm_find_mtt_page_list(struct hmm_comp_priv *comp_priv, struct rdma_mtt_seg *mtt_seg, u32 npages, + u64 *page_list) +{ + void *vaddr = NULL; + u32 i = 0; + u32 mtt_index = 0; + u32 mtts_per_page = 0; + + mtts_per_page = comp_priv->mtt_page_size / RDMA_PA_SIZE; + if ((mtt_seg->offset % mtts_per_page) != 0) { + pr_err("%s: First mtt isn't in the head of page, ret(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } + + mtt_index = mtt_seg->offset; + for (i = 0; i < npages; i++) { + vaddr = hmm_em_table_find(&comp_priv->mtt_em_table, mtt_index, &page_list[i]); + if (vaddr == NULL) { + pr_err("%s: Can't find va and pa of mtt entry, ret(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } + + mtt_index += comp_priv->mtt_page_size / RDMA_PA_SIZE; + } + + return 0; +} + +static int hmm_write_mtt_chunk(struct hmm_comp_priv *comp_priv, struct rdma_mtt *mtt, u32 mtt_level_index, + u32 start_index, u32 npages, const u64 *page_list) +{ + u32 i = 0; + u16 sign_val = 0; + __be64 *mtts = NULL; + + mtts = (__be64 *)hmm_em_table_find(&comp_priv->mtt_em_table, mtt->mtt_seg[mtt_level_index]->offset + start_index, + NULL); + if (mtts == NULL) { + pr_err("%s: Can't find va and pa of mtt entry, ret(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } +#ifdef RDMA_SIGN_MTT_EN + sign_val = hmm_gen_mtt_sign(mtt->mtt_paddr, mtt->mtt_type); +#endif + for (i = 0; i < npages; i++) { + mtts[i] = cpu_to_be64(page_list[i] | RDMA_MTT_PA_VALID | (sign_val << 1)); + } + + return 0; +} + +static int hmm_write_mtt_seg(struct hmm_comp_priv *comp_priv, struct rdma_mtt *mtt, u32 mtt_level_index, + u32 start_index, u32 npages, u64 *page_list) +{ + int ret = 0; + u32 chunk = 0; + u32 mtts_per_page = 0; + u32 max_mtts_first_page = 0; + u32 tmp_npages = npages; + u32 tmp_start_index = start_index; + u64 *tmp_page_list = page_list; + + /* caculate how may mtts fit in the first page */ + mtts_per_page = comp_priv->mtt_page_size / RDMA_PA_SIZE; + max_mtts_first_page = mtts_per_page - ((mtt->mtt_seg[mtt_level_index]->offset + tmp_start_index) % mtts_per_page); + + chunk = (tmp_npages < max_mtts_first_page) ? tmp_npages : max_mtts_first_page; + + while ((int)tmp_npages > 0) { + ret = hmm_write_mtt_chunk(comp_priv, mtt, mtt_level_index, tmp_start_index, chunk, tmp_page_list); + if (ret != 0) { + pr_err("%s: Write mtt chunk failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + tmp_npages -= chunk; + tmp_start_index += chunk; + tmp_page_list += chunk; + + chunk = (tmp_npages < mtts_per_page) ? tmp_npages : mtts_per_page; + } + + return 0; +} + +static int hmm_alloc_mtt_seg(struct hmm_comp_priv *comp_priv, struct rdma_mtt_seg *mtt_seg) +{ + int ret = 0; + u32 seg_offset = 0; + u32 seg_order = 0; + u32 log_mtts_per_seg = 0; + + log_mtts_per_seg = comp_priv->rdma_cap.log_mtt_seg; + + seg_order = (mtt_seg->order > log_mtts_per_seg) ? (mtt_seg->order - log_mtts_per_seg) : 0; + mtt_seg->order = seg_order + log_mtts_per_seg; + + seg_offset = hmm_buddy_alloc(&comp_priv->mtt_buddy, seg_order); + if (seg_offset == HMM_INVALID_INDEX) { + pr_err("%s: Alloc mtt index failed\n", __FUNCTION__); + return -ENOMEM; + } + + mtt_seg->offset = seg_offset << log_mtts_per_seg; + + ret = hmm_em_table_get_range(comp_priv->pdev, &comp_priv->mtt_em_table, mtt_seg->offset, + mtt_seg->offset + (u32)(1U << mtt_seg->order) - 1); + if (ret != 0) { + pr_err("%s: Alloc mtt entry failed, ret(%d)\n", __FUNCTION__, ret); + goto err_get_entry; + } + + mtt_seg->vaddr = hmm_em_table_find(&comp_priv->mtt_em_table, mtt_seg->offset, &mtt_seg->paddr); + if (mtt_seg->vaddr == NULL) { + pr_err("%s: Can't find start address of mtt_seg\n", __FUNCTION__); + goto err_find_entry; + } + + return 0; + +err_find_entry: + hmm_em_table_put_range(comp_priv->pdev, &comp_priv->mtt_em_table, mtt_seg->offset, + mtt_seg->offset + (u32)(1U << mtt_seg->order) - 1); + +err_get_entry: + hmm_buddy_free(&comp_priv->mtt_buddy, seg_offset, seg_order); + + return -ENOMEM; +} + +static void hmm_free_mtt_seg(struct hmm_comp_priv *comp_priv, struct rdma_mtt_seg *mtt_seg) +{ + u32 seg_offset = 0; + u32 seg_order = 0; + int log_mtts_per_seg = 0; + + hmm_em_table_put_range(comp_priv->pdev, &comp_priv->mtt_em_table, mtt_seg->offset, + mtt_seg->offset + (1U << mtt_seg->order) - 1); + + log_mtts_per_seg = (int)comp_priv->rdma_cap.log_mtt_seg; + seg_order = mtt_seg->order - (u32)log_mtts_per_seg; + seg_offset = mtt_seg->offset >> (unsigned int)log_mtts_per_seg; + + hmm_buddy_free(&comp_priv->mtt_buddy, seg_offset, seg_order); +} + +static int hmm_init_mtt_seg(struct hmm_comp_priv *comp_priv, struct rdma_mtt *mtt, u32 npages) +{ + u32 i; + int ret; + + if ((comp_priv == NULL) || (mtt == NULL)) { + pr_err("%s: Comp_priv or mtt is null\n", __FUNCTION__); + return -EINVAL; + } + + if (npages >= comp_priv->rdma_cap.num_mtts) { + pr_err("%s: Npages(0x%x) over range, ret(%d)\n", __FUNCTION__, npages, -EINVAL); + return -EINVAL; + } + + ret = hmm_set_mtt_layer(comp_priv, mtt, npages); + if (ret != 0) { + return ret; + } + + mtt->mtt_seg = (struct rdma_mtt_seg **)kzalloc(mtt->mtt_layers * sizeof(struct rdma_mtt_seg *), GFP_KERNEL); + if (mtt->mtt_seg == NULL) { + pr_err("%s: Alloc memory for mtt->mtt_seg failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + for (i = 0; i < mtt->mtt_layers; i++) { + mtt->mtt_seg[i] = (struct rdma_mtt_seg *)kzalloc(sizeof(struct rdma_mtt_seg), GFP_KERNEL); + if (mtt->mtt_seg[i] == NULL) { + pr_err("%s: Alloc memory for mtt->mtt_seg[i] failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + goto err_out; + } + } + + return 0; + +err_out: + for (i = 0; i < mtt->mtt_layers; i++) { + if (mtt->mtt_seg[i]) { + kfree(mtt->mtt_seg[i]); + mtt->mtt_seg[i] = NULL; + } + } + + kfree(mtt->mtt_seg); + mtt->mtt_seg = NULL; + + return -ENOMEM; +} + +static int hmm_rdma_mtt_alloc_prepare(void *hwdev, u32 npages, struct rdma_mtt *mtt, struct hmm_comp_priv **comp_priv, + u32 service_type) +{ + int ret = 0; + if ((hwdev == NULL) || (mtt == NULL)) { + pr_err("%s: Hwdev or mtt is null\n", __FUNCTION__); + return -EINVAL; + } + + *comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (*comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + ret = hmm_init_mtt_seg(*comp_priv, mtt, npages); + if (ret != 0) { + pr_err("%s: Initialize mtt_seg failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + return ret; +} + +static int hmm_enable_mtt_related(struct hmm_comp_priv *comp_priv, struct rdma_mtt *mtt, u32 low_layer_index) +{ + u64 *page_list = NULL; + struct rdma_mtt_seg *low_mtt_seg = NULL; + u32 npages = 0; + int ret = 0; + + low_mtt_seg = mtt->mtt_seg[low_layer_index]; + npages = (u32)((1UL << low_mtt_seg->order) / (comp_priv->mtt_page_size / RDMA_PA_SIZE)); + page_list = (u64 *)kzalloc(npages * RDMA_PA_SIZE, GFP_KERNEL); + if (page_list == NULL) { + pr_err("%s: Alloc memory for page_list failed, ret(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + ret = hmm_find_mtt_page_list(comp_priv, low_mtt_seg, npages, page_list); + if (ret != 0) { + pr_err("%s: Can't find page_list of mtt_seg, ret(%d)\n", __FUNCTION__, ret); + goto out; + } + + ret = hmm_write_mtt_seg(comp_priv, mtt, low_layer_index + 1, 0, npages, page_list); + if (ret != 0) { + pr_err("%s: Write mtt_seg failed, ret(%d)\n", __FUNCTION__, ret); + goto out; + } + +out: + kfree(page_list); + + return ret; +} + +static void hmm_cleanup_mtt_seg(struct rdma_mtt *mtt) +{ + u32 i = 0; + + for (i = 0; i < mtt->mtt_layers; i++) { + if (mtt->mtt_seg[i]) { + kfree(mtt->mtt_seg[i]); + mtt->mtt_seg[i] = NULL; + } + } + + kfree(mtt->mtt_seg); + mtt->mtt_seg = NULL; +} + +int hmm_rdma_mtt_alloc(void *hwdev, u32 npages, u32 page_shift, struct rdma_mtt *mtt, u32 service_type) +{ + struct hmm_comp_priv *comp_priv = NULL; + int ret = 0; + u32 i = 0; + u32 cur_layer = 0; + u32 order = 0; + u32 tmp_npages = npages; + ret = hmm_rdma_mtt_alloc_prepare(hwdev, npages, mtt, &comp_priv, service_type); + if (ret != 0) { + return ret; + } + + for (cur_layer = 1; cur_layer <= mtt->mtt_layers; cur_layer++) { + tmp_npages = (tmp_npages < HMM_MTT_NUM_PER_CACHELINE) ? HMM_MTT_NUM_PER_CACHELINE : tmp_npages; + for (i = 1; i < tmp_npages; i <<= 1) { + order++; + } + + mtt->mtt_seg[cur_layer - 1]->order = order; + ret = hmm_alloc_mtt_seg(comp_priv, mtt->mtt_seg[cur_layer - 1]); + if (ret != 0) { + pr_err("%s: Alloc mtt_seg failed, npages(%d), ret(%d)\n", __FUNCTION__, tmp_npages, ret); + goto err_out; + } + + tmp_npages = (u32)(1U << mtt->mtt_seg[cur_layer - 1]->order) / (comp_priv->mtt_page_size / RDMA_PA_SIZE); + order = 0; + } + if (mtt->mtt_layers > 0) { + mtt->mtt_vaddr = (__be64 *)mtt->mtt_seg[mtt->mtt_layers - 1]->vaddr; + mtt->mtt_paddr = mtt->mtt_seg[mtt->mtt_layers - 1]->paddr; + } + for (i = 1; i < mtt->mtt_layers; i++) { + ret = hmm_enable_mtt_related(comp_priv, mtt, i - 1); + if (ret != 0) { + pr_err("%s: Cant't get multi mtt_seg related, i(%d), ret(%d)\n", __FUNCTION__, i, ret); + goto err_out; + } + } + mtt->buf_page_shift = page_shift; + mtt->mtt_page_shift = comp_priv->mtt_page_shift; + return 0; +err_out: + for (i = cur_layer - 1; i > 0; i--) { + hmm_free_mtt_seg(comp_priv, mtt->mtt_seg[i - 1]); + } + hmm_cleanup_mtt_seg(mtt); + return -ENOMEM; +} + +void hmm_rdma_mtt_free(void *hwdev, struct rdma_mtt *mtt, u32 service_type) +{ + struct hmm_comp_priv *comp_priv = NULL; + u32 i = 0; + + if ((hwdev == NULL) || (mtt == NULL)) { + pr_err("%s: Hwdev or mtt is null\n", __FUNCTION__); + return; + } + + comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return; + } + + if (mtt->mtt_layers == 0) { + return; + } + + for (i = 0; i < mtt->mtt_layers; i++) { + hmm_free_mtt_seg(comp_priv, mtt->mtt_seg[i]); + } + + hmm_cleanup_mtt_seg(mtt); +} + +int hmm_rdma_write_mtt(void *hwdev, struct rdma_mtt *mtt, u32 start_index, u32 npages, u64 *page_list, u32 service_type) +{ + struct hmm_comp_priv *comp_priv = NULL; + int ret = 0; + + if ((hwdev == NULL) || (mtt == NULL)) { + pr_err("%s: Hwdev or mtt is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + if (mtt->mtt_layers == 0) { + mtt->mtt_paddr = page_list[0]; + return 0; + } + + ret = hmm_write_mtt_seg(comp_priv, mtt, 0, start_index, npages, page_list); + if (ret != 0) { + pr_err("%s: Write mtt seg failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + return 0; +} + +int hmm_init_mtt_table(struct hmm_comp_priv *comp_priv) +{ + int ret = 0; + u32 i = 0; + u32 max_order = 0; + u32 mtt_num = 0; + u32 mtt_size = 0; + u32 log_mtts_per_seg = 0; + + mtt_num = comp_priv->rdma_cap.num_mtts; + log_mtts_per_seg = comp_priv->rdma_cap.log_mtt_seg; + mtt_size = comp_priv->rdma_cap.mtt_entry_sz; + + for (i = 1; i < mtt_num; i <<= 1) { + max_order++; + } + + max_order = (max_order > log_mtts_per_seg) ? (max_order - log_mtts_per_seg) : 0; + + ret = hmm_buddy_init(&comp_priv->mtt_buddy, max_order); + if (ret != 0) { + pr_err("%s: Initialize mtt's buddy failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + ret = hmm_em_init_table(comp_priv->pdev, &comp_priv->mtt_em_table, mtt_size, mtt_num, 0, + (int)(comp_priv->mtt_page_shift - PAGE_SHIFT_4K)); + if (ret != 0) { + pr_err("%s: Initialize mtt's em_table failed, ret(%d)\n", __FUNCTION__, ret); + goto err_out; + } + + return 0; + +err_out: + hmm_buddy_cleanup(&comp_priv->mtt_buddy); + + return ret; +} + +void hmm_cleanup_mtt_table(struct hmm_comp_priv *comp_priv) +{ + hmm_em_cleanup_table(comp_priv->pdev, &comp_priv->mtt_em_table); + + hmm_buddy_cleanup(&comp_priv->mtt_buddy); +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mw_mr.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mw_mr.c new file mode 100644 index 000000000..d21fb9dbc --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_mw_mr.c @@ -0,0 +1,222 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + Description : implement the management of MPT, MTT +***************************************************************************** */ + +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "hmm_comp.h" + +static void hmm_roce_mpt_to_big_endian(struct roce_mpt_context *mpt_ctx) +{ + mpt_ctx->dw0.value = cpu_to_be32(mpt_ctx->dw0.value); + mpt_ctx->dw1.value = cpu_to_be32(mpt_ctx->dw1.value); + mpt_ctx->dw2.value = cpu_to_be32(mpt_ctx->dw2.value); + mpt_ctx->dw3.value = cpu_to_be32(mpt_ctx->dw3.value); + mpt_ctx->iova = cpu_to_be64(mpt_ctx->iova); + mpt_ctx->length = cpu_to_be64(mpt_ctx->length); + mpt_ctx->mtt_base_addr = cpu_to_be64(mpt_ctx->mtt_base_addr); + mpt_ctx->mtt_sz = cpu_to_be32(mpt_ctx->mtt_sz); +} + +static void hmm_set_roce_mr_access(struct roce_mpt_context *mpt_ctx, const struct rdma_mr *mr) +{ + mpt_ctx->dw0.bs.access_lr = 1; /* Local access enabled by default */ + + if ((RDMA_IB_ACCESS_LOCAL_WRITE & mr->access) != 0) { + mpt_ctx->dw0.bs.access_lw = 1; + } + if ((RDMA_IB_ACCESS_REMOTE_READ & mr->access) != 0) { + mpt_ctx->dw0.bs.access_rr = 1; + } + if ((RDMA_IB_ACCESS_REMOTE_WRITE & mr->access) != 0) { + mpt_ctx->dw0.bs.access_rw = 1; + } + if ((RDMA_IB_ACCESS_REMOTE_ATOMIC & mr->access) != 0) { + mpt_ctx->dw0.bs.access_ra = 1; + } + if ((RDMA_IB_ACCESS_MW_BIND & mr->access) != 0) { + mpt_ctx->dw0.bs.access_bind = 1; + } +} + +static void hmm_set_mptc_type_above_phy_mr(struct roce_mpt_context *mpt_ctx, struct rdma_mr *mr) +{ + switch (mr->mr_type) { + case RDMA_PHYS_MR: + mpt_ctx->mtt_base_addr = mr->mtt.mtt_paddr; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_VALID; + break; + + case RDMA_RSVD_LKEY: + mpt_ctx->dw0.bs.rkey = 1; + mpt_ctx->dw0.bs.bpd = 0; + mpt_ctx->dw0.bs.invalid_en = 0; + mpt_ctx->dw0.bs.remote_invalid_en = 0; + mpt_ctx->dw0.bs.pa = 1; + mpt_ctx->mtt_base_addr = 0; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_VALID; + break; + + case RDMA_SIG_MR: + mpt_ctx->mtt_base_addr = mr->mtt.mtt_paddr; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_FREE; + break; + + case RDMA_INDIRECT_MR: + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_FREE; + break; + default: + pr_err("%s: RoCE unsupport mr type(%d)\n", __FUNCTION__, mr->mr_type); + break; + } +} + +static void hmm_set_mptc_type_below_phy_mr(struct roce_mpt_context *mpt_ctx, struct rdma_mr *mr) +{ + switch (mr->mr_type) { + case RDMA_DMA_MR: + mpt_ctx->dw0.bs.pa = 1; + mpt_ctx->mtt_base_addr = 0; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_VALID; + break; + + case RDMA_USER_MR: + mpt_ctx->mtt_base_addr = mr->mtt.mtt_paddr; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_VALID; + break; + + case RDMA_FRMR: + mpt_ctx->mtt_base_addr = mr->mtt.mtt_paddr; + mpt_ctx->dw0.bs.fast_reg_en = 1; + mpt_ctx->dw0.bs.remote_access_en = 1; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_FREE; + mpt_ctx->mtt_sz = (mr->mtt.mtt_layers > 0) ? 1U << mr->mtt.mtt_seg[mr->mtt.mtt_layers - 1]->order : 0; + break; + + case RDMA_FMR: + mpt_ctx->mtt_base_addr = mr->mtt.mtt_paddr; + mpt_ctx->dw2.bs.status = RDMA_MPT_STATUS_VALID; + break; + default: + pr_err("%s: RoCE unsupport mr type(%d)\n", __FUNCTION__, mr->mr_type); + break; + } +} + +static void hmm_set_mptc_according_to_mr_type(struct roce_mpt_context *mpt_ctx, struct rdma_mr *mr) +{ + if (mr->mr_type < RDMA_PHYS_MR) { + hmm_set_mptc_type_below_phy_mr(mpt_ctx, mr); + } else { + hmm_set_mptc_type_above_phy_mr(mpt_ctx, mr); + } +} + +static void hmm_set_roce_mr_cmd_buf(struct roce_mpt_context *mpt_ctx, struct rdma_mr *mr) +{ + hmm_set_roce_mr_access(mpt_ctx, mr); + + mpt_ctx->dw0.bs.invalid_en = 1; + mpt_ctx->dw0.bs.remote_invalid_en = 1; + mpt_ctx->dw0.bs.r_w = RDMA_MPT_MR; + mpt_ctx->dw0.bs.bpd = 1; + mpt_ctx->dw2.bs.pdn = mr->pdn & 0x3ffff; + + if (mr->mr_type != RDMA_INDIRECT_MR) { + mpt_ctx->dw0.bs.mtt_page_size = + (mr->mtt.mtt_page_shift > PAGE_SHIFT_4K) ? (mr->mtt.mtt_page_shift - PAGE_SHIFT_4K) : 0; + mpt_ctx->dw0.bs.mtt_layer_num = mr->mtt.mtt_layers; + mpt_ctx->dw0.bs.buf_page_size = + (mr->mtt.buf_page_shift > PAGE_SHIFT_4K) ? (mr->mtt.buf_page_shift - PAGE_SHIFT_4K) : 0; + mpt_ctx->dw1.bs.dma_attr_idx = RDMA_MPT_DMA_ATTR_IDX; + mpt_ctx->dw1.bs.so_ro = 0; + mpt_ctx->dw2.bs.block_size = (mr->block_size / BLOCK_SIZE_DEVIDE_SECTOR) & 0x3f; + if (mr->block_size > 0) { + mpt_ctx->dw3.bs.page_mode = 1; + } + + mpt_ctx->iova = mr->iova; + mpt_ctx->length = mr->size; + mpt_ctx->dw3.bs.fbo = 0; + if ((mr->access & RDMA_IB_ACCESS_ZERO_BASED) != 0) { + mpt_ctx->dw0.bs.zbva = 1; + mpt_ctx->dw3.bs.fbo = mr->iova & PAGE_MASK; + mpt_ctx->iova = 0; + } + } else { + mpt_ctx->dw2.bs.indirect_mr = 1; + } + + mpt_ctx->dw3.bs.mkey = mr->key & 0xFF; + + hmm_set_mptc_according_to_mr_type(mpt_ctx, mr); + hmm_roce_mpt_to_big_endian(mpt_ctx); +} + +int hmm_rdma_disable_mr_mpt(void *hwdev, struct rdma_mr *mr, u32 service_type, u16 channel) +{ + struct hmm_comp_priv *comp_priv = NULL; + int ret = 0; + + if ((hwdev == NULL) || (mr == NULL)) { + pr_err("%s: Hwdev or mr is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + + if (mr->enabled == RDMA_MPT_EN_HW) { + ret = hmm_disable_roce_mpt(comp_priv, &mr->mpt, channel); + if (ret != 0) { + pr_err("%s: Disable mr's mpt failed, ret(%d)\n", __FUNCTION__, ret); + return ret; + } + + mr->enabled = RDMA_MPT_EN_SW; + } + return 0; +} + +int hmm_rdma_enable_mr_mpt(void *hwdev, struct rdma_mr *mr, u16 channel) +{ + cqm_cmd_buf_s *cqm_cmd_inbuf = NULL; + struct rdma_mpt_entry *mpt_entry = NULL; + struct rdma_mpt_sw2hw_inbuf *mpt_sw2hw_inbuf = NULL; + int ret = 0; + + if ((hwdev == NULL) || (mr == NULL)) { + pr_err("%s: Hwdev or mr is null\n", __FUNCTION__); + return -EINVAL; + } + + cqm_cmd_inbuf = cqm_cmd_alloc(hwdev); + if (cqm_cmd_inbuf == NULL) { + pr_err("%s: Alloc cmd_buf failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + cqm_cmd_inbuf->size = (u16)sizeof(struct rdma_mpt_sw2hw_inbuf); + mpt_sw2hw_inbuf = (struct rdma_mpt_sw2hw_inbuf *)cqm_cmd_inbuf->buf; + memset(mpt_sw2hw_inbuf, 0, sizeof(*mpt_sw2hw_inbuf)); + mpt_sw2hw_inbuf->com.dw0.bs.cmd_bitmask = (u16)cpu_to_be16(VERBS_CMD_TYPE_MR_BITMASK); + mpt_sw2hw_inbuf->com.index = cpu_to_be32(mr->mpt.mpt_index); + mpt_entry = &mpt_sw2hw_inbuf->mpt_entry; + + hmm_set_roce_mr_cmd_buf(&mpt_entry->roce_mpt_ctx, mr); + ret = hmm_enable_roce_mpt(hwdev, cqm_cmd_inbuf, channel); + if (ret != 0) { + pr_err("%s: Enable mr's mpt failed, ret(%d)\n", __FUNCTION__, ret); + goto out; + } + mr->enabled = RDMA_MPT_EN_HW; +out: + cqm_cmd_free(hwdev, cqm_cmd_inbuf); + return ret; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_res.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_res.c new file mode 100644 index 000000000..e6e2d541f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_comp_res.c @@ -0,0 +1,63 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + File Name : hmm_comp_res.c + Version : Initial Draft + Description : implement the management of MPT, MTT +***************************************************************************** */ + +#include <linux/module.h> +#include <linux/netdevice.h> + +#include "hinic3_hw.h" +#include "hmm_comp.h" + +int hmm_rdma_mpt_alloc(void *hwdev, struct rdma_mpt *mpt, u32 service_type) +{ + struct hmm_comp_priv *comp_priv = NULL; + struct rdma_mpt_entry *mpt_entry = NULL; + u32 mpt_entry_size = 0; + + if ((hwdev == NULL) || (mpt == NULL)) { + pr_err("%s: Hwdev or mpt is null\n", __FUNCTION__); + return -EINVAL; + } + + comp_priv = get_hmm_comp_priv(hwdev, service_type); + if (comp_priv == NULL) { + pr_err("%s: Comp_priv is null\n", __FUNCTION__); + return -EINVAL; + } + mpt_entry_size = comp_priv->rdma_cap.mpt_entry_sz; + + mpt->mpt_object = + (void *)cqm_object_qpc_mpt_create(hwdev, service_type, CQM_OBJECT_MPT, mpt_entry_size, mpt, CQM_INDEX_INVALID, + false); + if (mpt->mpt_object == NULL) { + pr_err("%s: Alloc mpt_object failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return -ENOMEM; + } + + mpt->mpt_index = ((cqm_qpc_mpt_s *)mpt->mpt_object)->xid; + mpt->vaddr = (void *)((cqm_qpc_mpt_s *)mpt->mpt_object)->vaddr; + if (!cqm_need_secure_mem(hwdev)) { + memset(mpt->vaddr, 0, sizeof(struct rdma_mpt_entry)); + + mpt_entry = (struct rdma_mpt_entry *)mpt->vaddr; + mpt_entry->roce_mpt_ctx.dw2.bs.status = RDMA_MPT_STATUS_MEM_INIT; + mpt_entry->roce_mpt_ctx.dw2.value = cpu_to_be32(mpt_entry->roce_mpt_ctx.dw2.value); + } + return 0; +} + + +void hmm_rdma_mpt_free(void *hwdev, struct rdma_mpt *mpt) +{ + if ((hwdev == NULL) || (mpt == NULL)) { + pr_err("%s: Hwdev or mpt is null\n", __FUNCTION__); + return; + } + hiudk_cqm_object_delete(hwdev, &((cqm_qpc_mpt_s *)mpt->mpt_object)->object); + mpt->vaddr = NULL; + mpt->mpt_object = NULL; + return; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.c new file mode 100644 index 000000000..8d52724d1 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.c @@ -0,0 +1,348 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + Description : management of entry + ***************************************************************************** */ +#include <linux/mm.h> +#include <linux/scatterlist.h> +#include <linux/slab.h> + +#include "hmm_em.h" + +static void hmm_em_chunk_free(struct pci_dev *pdev, struct hmm_em_chunk *em_chunk) +{ + struct hmm_em_buf *cur_buf = NULL; + struct hmm_em_buf *next_buf = NULL; + + cur_buf = &em_chunk->em_buf_list; + next_buf = cur_buf->next_buf; + + while (next_buf != NULL) { + cur_buf = next_buf; + next_buf = cur_buf->next_buf; + + if ((cur_buf->buf != NULL) && (cur_buf->length > 0)) { + memset(cur_buf->buf, 0, cur_buf->length); + dma_free_coherent(&pdev->dev, (unsigned long)cur_buf->length, cur_buf->buf, cur_buf->dma_addr); + cur_buf->buf = NULL; + cur_buf->length = 0; + } + + kfree(cur_buf); + cur_buf = NULL; + } + + kfree(em_chunk); +} + +static int hmm_em_chunk_alloc_npages(struct pci_dev *pdev, struct hmm_em_chunk *em_chunk, int min_order) +{ + int cur_order = 0; + int npages = 0; + unsigned int chunk_size = HMM_EM_CHUNK_SIZE; + struct hmm_em_buf* cur_buf = &em_chunk->em_buf_list; + struct hmm_em_buf* next_buf = NULL; + + cur_buf->next_buf = NULL; + cur_buf->length = 0; + cur_order = get_order(chunk_size); //lint !e834 !e587 + npages = (int)(1U << (unsigned int)cur_order); + while (npages > 0) { + if (next_buf == NULL) { + next_buf = (struct hmm_em_buf *)kzalloc(sizeof(struct hmm_em_buf), GFP_KERNEL); + if (next_buf == NULL) { + dev_err(&pdev->dev, "[HMM] %s: Alloc memory for em_buf failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return (-ENOMEM); + } + + next_buf->length = 0; + next_buf->next_buf = NULL; + } + cur_buf->next_buf = next_buf; + + next_buf->buf = dma_alloc_coherent(&pdev->dev, (size_t)HMM_EM_PAGE_SIZE << (unsigned int)cur_order, + &next_buf->dma_addr, GFP_KERNEL); + if (next_buf->buf == NULL) { + cur_order--; + if (cur_order < min_order) { + dev_err(&pdev->dev, "[HMM] %s:em_chunk alloc dma buf failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return (-ENOMEM); + } else { + dev_err(&pdev->dev, "[HMM, WARN] %s: em_chunk alloc %d o dma failed. cont alloc small mem.\n", + __FUNCTION__, cur_order); + continue; + } + } + + next_buf->length = (u32)HMM_EM_PAGE_SIZE << (unsigned int)cur_order; + em_chunk->buf_num++; + npages -= (int)(1U << (unsigned int)cur_order); + + cur_buf = next_buf; + next_buf = NULL; + } + + return 0; +} +static struct hmm_em_chunk *hmm_em_chunk_alloc(struct pci_dev *pdev, int min_order) +{ + struct hmm_em_chunk *em_chunk = NULL; + int ret; + + em_chunk = (struct hmm_em_chunk *)kzalloc(sizeof(struct hmm_em_chunk), GFP_KERNEL); + if (em_chunk == NULL) { + dev_err(&pdev->dev, "[HMM] %s: Alloc memory for em_chunk failed, err(%d)\n", __FUNCTION__, -ENOMEM); + return (struct hmm_em_chunk *)ERR_PTR((long)-ENOMEM); + } + + em_chunk->buf_num = 0; + ret = hmm_em_chunk_alloc_npages(pdev, em_chunk, min_order); + if (ret != 0) { + hmm_em_chunk_free(pdev, em_chunk); + return (struct hmm_em_chunk *)ERR_PTR((long)ret); + } + + em_chunk->refcount = 0; + + return em_chunk; +} + +static void hmm_em_table_put(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 obj) +{ + u32 i = 0; + + if (obj >= em_table->obj_num) { + dev_err(&pdev->dev, "[HMM] %s: Obj over range, obj(0x%x), max(0x%x)\n", __FUNCTION__, obj, + em_table->obj_num - 1); + return; + } + + i = obj / (HMM_EM_CHUNK_SIZE / em_table->obj_size); + + mutex_lock(&em_table->mutex); + + if ((em_table->em_chunk[i] == NULL) || (IS_ERR(em_table->em_chunk[i]))) { + dev_err(&pdev->dev, "[HMM] %s: Em_table->em_chunk[%d] not alloced, obj(0x%x)\n", __FUNCTION__, i, obj); + mutex_unlock(&em_table->mutex); + return; + } + + if (em_table->em_chunk[i]->refcount == 1) { + em_table->em_chunk[i]->refcount = 0; + hmm_em_chunk_free(pdev, em_table->em_chunk[i]); + em_table->em_chunk[i] = NULL; + } else { + --em_table->em_chunk[i]->refcount; + } + + mutex_unlock(&em_table->mutex); +} + +static int hmm_em_table_get(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 obj) +{ + int ret = 0; + u32 i; + + if (obj >= em_table->obj_num) { + dev_err(&pdev->dev, "[HMM] %s: Obj over range, obj(0x%x), max(0x%x)\n", __FUNCTION__, obj, + em_table->obj_num - 1); + return -EINVAL; + } + + i = obj / (HMM_EM_CHUNK_SIZE / em_table->obj_size); + + mutex_lock(&em_table->mutex); + + if (em_table->em_chunk[i]) { + ++em_table->em_chunk[i]->refcount; + goto out; + } + + em_table->em_chunk[i] = hmm_em_chunk_alloc(pdev, em_table->min_order); + if (IS_ERR(em_table->em_chunk[i])) { + ret = (int)PTR_ERR(em_table->em_chunk[i]); + dev_err(&pdev->dev, "[HMM] %s: Alloc em_chunk failed, ret(%d)\n", __FUNCTION__, ret); + goto out; + } + + ++em_table->em_chunk[i]->refcount; + +out: + mutex_unlock(&em_table->mutex); + + return ret; +} + +void *hmm_em_table_find(struct hmm_em_table *em_table, u32 obj, dma_addr_t *dma_handle) +{ + void *vaddr = NULL; + struct hmm_em_chunk *em_chunk = NULL; + struct hmm_em_buf *cur_buf = NULL; + struct hmm_em_buf *next_buf = NULL; + u64 table_offset; + u32 offset; + + if (em_table == NULL) { + pr_err("%s: Em_table is null, err(%d)\n", __FUNCTION__, -EINVAL); + return NULL; + } + + if (obj >= em_table->obj_num) { + pr_err("%s: Obj over range, obj(0x%x), max(0x%x)\n", __FUNCTION__, obj, em_table->obj_num - 1); + return NULL; + } + + mutex_lock(&em_table->mutex); + + table_offset = (u64)obj * em_table->obj_size; + em_chunk = em_table->em_chunk[table_offset / HMM_EM_CHUNK_SIZE]; + offset = table_offset % HMM_EM_CHUNK_SIZE; + + if (em_chunk == NULL) { + pr_err("%s: Em_chunk has not been alloced, err(%d)\n", __FUNCTION__, -EINVAL); + goto err_out; + } + + cur_buf = &em_chunk->em_buf_list; + next_buf = cur_buf->next_buf; + + while (next_buf != NULL) { + cur_buf = next_buf; + if (offset < cur_buf->length) { + if (dma_handle) { + *dma_handle = cur_buf->dma_addr + offset; + } + + vaddr = (void *)((char *)(cur_buf->buf) + offset); + mutex_unlock(&em_table->mutex); + return vaddr; + } + + offset -= cur_buf->length; + next_buf = cur_buf->next_buf; + } + +err_out: + mutex_unlock(&em_table->mutex); + + return NULL; +} + +void hmm_em_table_put_range(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 start, u32 end) +{ + int i = 0; + int inc = 0; + + if ((pdev == NULL) || (em_table == NULL)) { + dev_err(&pdev->dev, "[HMM] %s: Pdev or em_table is null, err(%d)\n", __FUNCTION__, -EINVAL); + return; + } + + inc = (int)(HMM_EM_CHUNK_SIZE / em_table->obj_size); + for (i = (int)start; i <= (int)end; i += inc) { + hmm_em_table_put(pdev, em_table, (u32)i); + } + + return; +} + +int hmm_em_table_get_range(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 start, u32 end) +{ + int ret = 0; + int i = 0; + int inc = 0; + + if ((pdev == NULL) || (em_table == NULL)) { + dev_err(&pdev->dev, "[HMM] %s: Pdev or em_table is null, err(%d)\n", __FUNCTION__, -EINVAL); + return -EINVAL; + } + + inc = (int)(HMM_EM_CHUNK_SIZE / em_table->obj_size); + + for (i = (int)start; i <= (int)end; i += inc) { + ret = hmm_em_table_get(pdev, em_table, (u32)i); + if (ret != 0) { + dev_err(&pdev->dev, "[HMM] %s: Get entry failed, start(%d), end(%d), i(%d), ret(%d)\n", __FUNCTION__, start, + end, i, ret); + goto err_out; + } + } + + return 0; + +err_out: + while (i > (int)start) { + i -= inc; + hmm_em_table_put(pdev, em_table, (u32)i); + } + + return ret; +} + +int hmm_em_init_table(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 obj_size, u32 nobj, u32 reserved_bot, + int min_order) +{ + u32 obj_per_chunk = 0; + u32 chunk_num = 0; + + if ((pdev == NULL) || (em_table == NULL)) { + dev_err(&pdev->dev, "[HMM] %s: Pdev or em_table is null\n", __FUNCTION__); + return -EINVAL; + } + + if (nobj == 0) { + dev_err(&pdev->dev, "[HMM] %s: Nobj is invalid\n", __FUNCTION__); + return -EINVAL; + } + + /*lint -e587 */ + if (nobj != HMM_EM_ROUNDUP_POW_OF_TWO(nobj)) { + dev_err(&pdev->dev, "[HMM] %s: Obj isn't pow of two, nobj(0x%x)\n", __FUNCTION__, nobj); + return -EINVAL; + } + + if (obj_size != HMM_EM_ROUNDUP_POW_OF_TWO(obj_size)) { + dev_err(&pdev->dev, "[HMM] %s: Obj_size isn't pow of two, obj_size(0x%x)\n", __FUNCTION__, obj_size); + return -EINVAL; + } + /*lint +e587 */ + + obj_per_chunk = HMM_EM_CHUNK_SIZE / obj_size; + chunk_num = (nobj + obj_per_chunk - 1) / obj_per_chunk; + + em_table->em_chunk = (struct hmm_em_chunk **)kcalloc((size_t)chunk_num, sizeof(struct hmm_em_chunk *), GFP_KERNEL); + if (em_table->em_chunk == NULL) { + dev_err(&pdev->dev, "[HMM] %s: Em_table->em_chunk create failed\n", __FUNCTION__); + return -ENOMEM; + } + + em_table->chunk_num = chunk_num; + em_table->obj_num = nobj; + em_table->obj_size = obj_size; + em_table->min_order = min_order; + + mutex_init(&em_table->mutex); + + return 0; +} + +void hmm_em_cleanup_table(struct pci_dev *pdev, struct hmm_em_table *em_table) +{ + u32 i = 0; + + if ((pdev == NULL) || (em_table == NULL)) { + dev_err(&pdev->dev, "[HMM] %s: Pdev or em_table is null\n", __FUNCTION__); + return; + } + + for (i = 0; i < em_table->chunk_num; i++) { + if (em_table->em_chunk[i]) { + hmm_em_chunk_free(pdev, em_table->em_chunk[i]); + em_table->em_chunk[i] = NULL; + } + } + + kfree(em_table->em_chunk); + em_table->em_chunk = NULL; + + return; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.h b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.h new file mode 100644 index 000000000..4523ae863 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_em.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + * Description : structure and interface about management of entry + */ + +#ifndef HMM_EM_H +#define HMM_EM_H + +#include <linux/pci.h> +#include <linux/mutex.h> +#include "hmm_umem.h" + +#define HMM_EM_CHUNK_SIZE (1 << 21) +#define HMM_EM_PAGE_SIZE PAGE_SIZE // (4096UL) + +#define HMM_EM_ROUNDUP_POW_OF_TWO roundup_pow_of_two + +struct hmm_em_buf { + u32 length; + void *buf; + dma_addr_t dma_addr; + struct hmm_em_buf *next_buf; +}; + +struct hmm_em_chunk { + u32 buf_num; + u32 refcount; + struct hmm_em_buf em_buf_list; +}; + +struct hmm_em_table { + u32 chunk_num; + u32 obj_num; + u32 obj_size; + int min_order; + struct mutex mutex; + struct hmm_em_chunk **em_chunk; +}; + + +void *hmm_em_table_find(struct hmm_em_table *em_table, u32 obj, dma_addr_t *dma_handle); +void hmm_em_table_put_range(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 start, u32 end); +int hmm_em_table_get_range(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 start, u32 end); +int hmm_em_init_table(struct pci_dev *pdev, struct hmm_em_table *em_table, u32 obj_size, u32 nobj, u32 reserved_bot, + int min_order); +void hmm_em_cleanup_table(struct pci_dev *pdev, struct hmm_em_table *em_table); + +#endif diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.c new file mode 100644 index 000000000..5cca85f14 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.c @@ -0,0 +1,403 @@ +/* ***************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + Description : implement the verbs of momory region +***************************************************************************** */ +#include <linux/pci.h> +#include <linux/dma-mapping.h> +#include <linux/vmalloc.h> +#include <linux/semaphore.h> + +#include "hinic3_crm.h" +#include "hmm_umem.h" +#include "hmm_comp.h" +#include "hinic3_hmm.h" +#include "hmm_mr.h" + +/* **************************************************************************** + Prototype : get_key_from_index + Description : mr key的计算算法，通过index移位计算得到 + Input : u32 mpt_index + Output : None +**************************************************************************** */ +static u32 get_key_from_index(u32 mpt_index) +{ + return (mpt_index >> MR_KEY_RIGHT_SHIFT_OFS) | (mpt_index << MR_KEY_LEFT_SHIFT_OFS); +} + +/* **************************************************************************** + Prototype : hmm_alloc_tpt + Description : alloc mpt and mtt + Input : struct hinic3_hwdev *hwdev + struct rdma_mr *mr + u32 npages + u32 page_shift + Output : None +**************************************************************************** */ +static int hmm_alloc_tpt(struct hinic3_hwdev *hwdev, struct rdma_mr *mr, u32 npages, u32 page_shift, u32 service_type) +{ + int ret; + + ret = hmm_rdma_mpt_alloc(hwdev, &mr->mpt, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc mpt, ret(%d), func_id(%d)\n", __func__, __LINE__, + ret, hinic3_global_func_id(hwdev)); + return ret; + } + mr->enabled = RDMA_MPT_EN_SW; + + /* npages = 0 or 1, means not need mtt */ + ret = hmm_rdma_mtt_alloc(hwdev, npages, page_shift, &mr->mtt, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc mtt, ret(%d), func_id(%d)\n", __func__, __LINE__, + ret, hinic3_global_func_id(hwdev)); + goto err_alloc_mtt; + } + return 0; + +err_alloc_mtt: + hmm_rdma_mpt_free(hwdev, &mr->mpt); + mr->enabled = HMM_MPT_DISABLED; + + return ret; +} + +/* **************************************************************************** + Prototype : hmm_free_tpt + Description : free mpt and mtt + Input : struct hinic3_hwdev *hwdev + struct rdma_mr *mr +**************************************************************************** */ +void hmm_free_tpt(void *hwdev, struct rdma_mr *mr, u32 service_type) +{ + hmm_rdma_mtt_free(hwdev, &mr->mtt, service_type); + hmm_rdma_mpt_free(hwdev, &mr->mpt); + mr->enabled = HMM_MPT_DISABLED; +} + +/* **************************************************************************** + Prototype : hmm_set_rdma_mr + Description : set the member of rdma_mr + Input : struct rdma_mr *mr + enum rdma_mr_type mr_type + u32 pdn + u64 iova + u64 size + u32 access + Output : None +**************************************************************************** */ +static void hmm_set_rdma_mr(struct rdma_mr *mr, enum rdma_mr_type mr_type, u32 pdn, u64 iova, u64 size, u32 access) +{ + mr->iova = iova; + mr->size = size; + mr->pdn = pdn; + mr->access = access; + mr->key = get_key_from_index(mr->mpt.mpt_index); /* 由mpt index转换为key */ + mr->mr_type = mr_type; +} + +/* **************************************************************************** + Prototype : hmm_alloc_mr + Description : register DMA_MR + Input : struct hinic3_hwdev *hwdev + enum rdma_mr_type mr_type + u32 max_num_sg + u32 service_type + Output : None +**************************************************************************** */ +struct hmm_mr *hmm_alloc_mr(struct hinic3_hwdev *hwdev, u32 pdn, enum rdma_mr_type mr_type, u32 max_num_sg, + u32 service_type, u16 channel) +{ + u32 access_flag; + int ret = 0; + struct hmm_mr *mr = NULL; + + if (hwdev == NULL) { + ret = -EINVAL; + pr_err("[HMM, ERR] %s(%d): dev is null\n", __func__, __LINE__); + goto err_out; + } +#ifndef PANGEA_V6 + if (mr_type != RDMA_DMA_MR && mr_type != RDMA_INDIRECT_MR) { +#else + if (mr_type != RDMA_DMA_MR) { +#endif + ret = -EINVAL; + pr_err("[HMM, ERR] %s(%d): mr_type is invalid\n", __func__, __LINE__); + goto err_out; + } + + mr = (struct hmm_mr *)kzalloc(sizeof *mr, GFP_KERNEL); + if (mr == NULL) { + ret = -ENOMEM; + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc memory for dma mr, func_id(%d)\n", __func__, + __LINE__, hinic3_global_func_id(hwdev)); + goto err_out; + } + + ret = hmm_alloc_tpt(hwdev->dev_hdl, &mr->rdmamr, 0, 0, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc mpt and mtt, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_alloc_tpt; + } + + access_flag = (RDMA_IB_ACCESS_REMOTE_READ | RDMA_IB_ACCESS_REMOTE_WRITE | RDMA_IB_ACCESS_LOCAL_WRITE | + RDMA_IB_ACCESS_REMOTE_ATOMIC); + + hmm_set_rdma_mr(&mr->rdmamr, mr_type, pdn, 0ULL, ROCE_DMA_MR_SIZE, access_flag); + + ret = hmm_rdma_enable_mr_mpt(hwdev->dev_hdl, &(mr->rdmamr), channel); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to enable mpt of DMA mr, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_enable_mpt; + } + + return mr; + +err_enable_mpt: + hmm_free_tpt(hwdev->dev_hdl, &mr->rdmamr, service_type); + +err_alloc_tpt: + kfree(mr); + +err_out: + return (struct hmm_mr *)ERR_PTR((long)ret); +} + +static int hmm_umem_write_mtt_check(const void *hwdev, const struct rdma_mtt *mtt, const struct hmm_umem *umem) +{ + if ((hwdev == NULL) || (mtt == NULL) || (umem == NULL)) { + pr_err("[HMM, ERR] %s(%d): hwdev or mtt or umem is null\n", __func__, __LINE__); + return -EINVAL; + } + return 0; +} + +static int hmm_umem_write_mtt_update(struct hinic3_hwdev *hwdev, struct rdma_mtt *mtt, + struct hmm_umem *umem, u64 *page_list, u32 service_type) +{ + int ret = 0; + int i = 0; + u32 j = 0; + u32 pages_in_chunk = 0; /* umem_chunk中单个内存块的页个数 */ + u32 npages = 0; /* 已经记录的页个数 */ + u32 start_index = 0; /* 要写入mtt的页 */ + struct scatterlist *sg = NULL; + u64 page_size = 0; + + page_size = BIT((unsigned int)umem->page_shift); + for_each_sg(umem->sg_head.sgl, sg, umem->nmap, i) + { + /* cal page num in truck */ + pages_in_chunk = sg_dma_len(sg) >> mtt->buf_page_shift; + for (j = 0; j < pages_in_chunk; ++j) { + page_list[npages] = sg_dma_address(sg) + (page_size * j); + npages++; + + /* one page can hold (PAGE_SIZE / sizeof(u64)) addrs */ + if (npages == (PAGE_SIZE / sizeof(u64))) { + ret = hmm_rdma_write_mtt(hwdev, mtt, start_index, npages, page_list, service_type); + start_index += npages; + npages = 0; + } + if ((npages == (PAGE_SIZE / sizeof(u64))) && (ret != 0)) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to write mtt, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto out; + } + } + } + + if (npages != 0) { + ret = hmm_rdma_write_mtt(hwdev, mtt, start_index, npages, page_list, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to write mtt, ret(%d), start_index(%d), func_id(%d)\n", + __func__, __LINE__, ret, start_index, hinic3_global_func_id(hwdev)); + goto out; + } + } + +out: + kfree(page_list); + + return ret; +} + +/* **************************************************************************** + Prototype : hmm_umem_write_mtt + Description : write mtt for umem(get from memory alloced by user) + Input : struct hinic3_hwdev *hwdev + struct rdma_mtt *mtt + struct hmm_umem *umem + Output : None +**************************************************************************** */ +int hmm_umem_write_mtt(struct hinic3_hwdev *hwdev, struct rdma_mtt *mtt, struct hmm_umem *umem, u32 service_type) +{ + int ret; + u64 *page_list = NULL; /* 要写入mtt的page_list */ + + ret = hmm_umem_write_mtt_check(hwdev, mtt, umem); + if (ret != 0) { + return ret; + } + page_list = (u64 *)kzalloc(PAGE_SIZE, GFP_KERNEL); + if (page_list == NULL) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc memory for page list, func_id(%d)\n", __func__, + __LINE__, hinic3_global_func_id(hwdev)); + return -ENOMEM; + } + ret = hmm_umem_write_mtt_update(hwdev, mtt, umem, page_list, service_type); + return ret; +} + +int hmm_reg_user_mr_update(struct hinic3_hwdev *hwdev, struct hmm_mr *mr, u32 pdn, u64 length, u64 virt_addr, + int access, u32 service_type, u16 channel) +{ + int ret = 0; + u32 npages = 0; + u32 page_shift = 0; + + if (hwdev == NULL) { + pr_err("[HMM, ERR] %s(%d): hwdev is null\n", __func__, __LINE__); + return 0; + } + mr->rdmamr.mtt.mtt_type = MTT_DMTT_TYPE; + npages = (u32)hmm_umem_page_count(mr->umem); + page_shift = (u32)(mr->umem->page_shift); + ret = hmm_alloc_tpt(hwdev, &mr->rdmamr, npages, page_shift, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc mpt and mtt, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_alloc_tpt; + } + + hmm_set_rdma_mr(&mr->rdmamr, RDMA_USER_MR, pdn, virt_addr, length, (u32)access); + + ret = hmm_umem_write_mtt(hwdev, &mr->rdmamr.mtt, mr->umem, service_type); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to write mtt, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_write_mtt; + } + + ret = hmm_rdma_enable_mr_mpt(hwdev, &mr->rdmamr, channel); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to enable mpt of user mr, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_write_mtt; + } + + return 0; + +err_write_mtt: + hmm_free_tpt(hwdev, &mr->rdmamr, service_type); + +err_alloc_tpt: + return ret; +} + +int hmm_dereg_mr_update(struct hinic3_hwdev *hwdev, struct rdma_mr *mr, u32 service_type, u16 channel) +{ + int ret = 0; + ret = hmm_rdma_disable_mr_mpt(hwdev, mr, service_type, channel); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to disable mpt of mr, ret(%d)\n", __func__, __LINE__, ret); + return ret; + } + + hmm_free_tpt(hwdev, mr, service_type); + return ret; +} + +#ifndef ROCE_SERVICE +/* **************************************************************************** + Prototype : hmm_reg_user_mr + Description : register MR for user + Input : struct hinic3_hwdev *hwdev + u64 start + u64 length + u64 virt_addr + int hmm_acess + Output : None +**************************************************************************** */ +struct hmm_mr *hmm_reg_user_mr(struct hinic3_hwdev *hwdev, u64 start, u32 pd, u64 length, u64 virt_addr, int hmm_acess, + u32 service_type, u16 channel) +{ + int ret = 0; + struct hmm_mr *mr = NULL; + + if (hwdev == NULL) { + pr_err("[HMM, ERR] %s(%d): hwdev is null\n", __func__, __LINE__); + goto err_out; + } + + mr = (struct hmm_mr *)kzalloc(sizeof(*mr), GFP_KERNEL); + if (mr == NULL) { + ret = -ENOMEM; + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to alloc memory for roce mr, func_id(%d)\n", __func__, + __LINE__, hinic3_global_func_id(hwdev)); + goto err_out; + } + + mr->hwdev = hwdev; + mr->rdmamr.iova = virt_addr; + mr->umem = hmm_umem_get(hwdev->dev_hdl, start, (size_t)length, hmm_acess, 0); + if (IS_ERR(mr->umem)) { + ret = (int)PTR_ERR(mr->umem); + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to get ib umem, func_id(%d)\n", __func__, __LINE__, + hinic3_global_func_id(hwdev)); + goto err_empty; + } + + rcu_read_lock(); + mr->umem->context->tgid = get_task_pid(current->group_leader, PIDTYPE_PID); + rcu_read_unlock(); + ret = hmm_reg_user_mr_update(hwdev, mr, pd, length, virt_addr, hmm_acess, service_type, channel); + if (ret != 0) { + goto err_get_umem; + } + return mr; + +err_get_umem: + hmm_umem_release(mr->umem); +err_empty: + kfree(mr); + +err_out: + return (struct hmm_mr *)ERR_PTR((long)ret); +} + +/* **************************************************************************** + Prototype : hmm_dereg_mr + Description : dereg DMA_MR, user_MR or FRMR + Input : struct hmm_mr *mr + Output : None + +**************************************************************************** */ +int hmm_dereg_mr(struct hmm_mr *mr, u32 service_type, u16 channel) +{ + int ret = 0; + struct hinic3_hwdev *hwdev = NULL; + + if (mr == NULL) { + pr_err("[HMM, ERR] %s(%d): Ibmr is null\n", __func__, __LINE__); + return -EINVAL; + } + + hwdev = (struct hinic3_hwdev *)mr->hwdev; + ret = hmm_dereg_mr_update(hwdev, &(mr->rdmamr), service_type, channel); + if (ret != 0) { + dev_err(hwdev->dev_hdl, "[HMM, ERR] %s(%d): Failed to de-reg mr update, ret(%d), func_id(%d)\n", __func__, __LINE__, + ret, hinic3_global_func_id(hwdev)); + return ret; + } + + if (mr->umem) { + hmm_umem_release(mr->umem); + } + kfree(mr); + return ret; +} +#endif + diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.h b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.h new file mode 100644 index 000000000..dfcae013c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_mr.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + * Description : structure related to mr + */ + +#ifndef HMM_MR_H +#define HMM_MR_H + +#include "hmm_umem.h" +#include "hmm_comp.h" + + +#define ROCE_DMA_MR_SIZE (~0ULL) +#define ROCE_FRMR_MAX_PAGES 512 +#define MR_KEY_RIGHT_SHIFT_OFS 24 +#define MR_KEY_LEFT_SHIFT_OFS 8 + +struct hmm_mr { + struct hmm_umem *umem; + struct rdma_mr rdmamr; + void *hwdev; +}; + +int hmm_rdma_enable_mr_mpt(void *hwdev, struct rdma_mr *mr, u16 channel); + +int hmm_rdma_disable_mr_mpt(void *hwdev, struct rdma_mr *mr, u32 service_type, u16 channel); + +void hmm_rdma_mpt_free(void *hwdev, struct rdma_mpt *mpt); + +int hmm_init_resource(void *hwdev, u32 service_type); + +void hmm_cleanup_resource(void *hwdev, u32 service_type); + +#endif // HMM_MR_H_ diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.c b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.c new file mode 100644 index 000000000..944a86203 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.c @@ -0,0 +1,322 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + Description : get the dma sglist from virtal memory address +***************************************************************************** */ + +#include <linux/mm.h> +#include <linux/dma-mapping.h> +#include <linux/signal.h> +#include <linux/sched/mm.h> +#include <linux/sched/signal.h> +#include <linux/hugetlb.h> +#include <linux/slab.h> +#include <linux/version.h> +#include "hinic3_rdma.h" +#include "hmm_umem.h" + +#ifndef ROCE_SERVICE +static void hmm_umemsg_release(struct device *device, struct hmm_umem *hmm_umem, int dirty) +{ + struct scatterlist *sg = NULL; + struct page *page = NULL; + int i; + + if (hmm_umem->nmap > 0) + dma_unmap_sg(device, hmm_umem->sg_head.sgl, hmm_umem->npages, DMA_BIDIRECTIONAL); + + for_each_sg(hmm_umem->sg_head.sgl, sg, hmm_umem->npages, i) + { + page = sg_page(sg); + if (!PageDirty(page) && hmm_umem->writable && dirty) + set_page_dirty_lock(page); + put_page(page); + } + + sg_free_table(&hmm_umem->sg_head); + return; +} + +/** + * hmm_umem_get - Pin and DMA map userspace memory. + * + * If access flags indicate ODP memory, avoid pinning. Instead, stores + * the mm for future page fault handling in conjunction with MMU notifiers. + * + * @context: userspace context to pin memory for + * @addr: userspace virtual address to start at + * @size: length of region to pin + * @access: RDMA_IB_ACCESS_xxx flags for memory being pinned + * @dmasync: flush in-flight DMA when the memory region is written + */ +struct hmm_umem *hmm_umem_get(struct device *device, unsigned long addr, size_t size, int access, int dmasync) +{ + int ret; + int i; + struct hmm_umem *hmem = NULL; + struct page **page_list = NULL; + struct vm_area_struct **vma_list = NULL; + unsigned long locked_pages; + unsigned long lock_limit; + unsigned long current_base; + unsigned long npages; + +#ifdef HAVE_STRUCT_DMA_ATTRS + DEFINE_DMA_ATTRS(dma_attrs); +#else + unsigned long dma_attrs = 0; +#endif + struct scatterlist *sg = NULL, *sg_list_start = NULL; + int need_release = 0; +#ifdef HAVE_GET_USER_PAGES_GUP_FLAGS + unsigned int gup_flags = FOLL_WRITE; +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 5, 0) + if (dmasync) +#ifdef HAVE_STRUCT_DMA_ATTRS + dma_set_attr(DMA_ATTR_WRITE_BARRIER, &dma_attrs); +#else + dma_attrs |= DMA_ATTR_WRITE_BARRIER; +#endif +#endif + + /* + * If the combination of the addr and size requested for this memory + * region causes an integer overflow, return error. + */ + if (((addr + size) < addr) || PAGE_ALIGN(addr + size) < (addr + size)) { + return ERR_PTR(-EINVAL); + } + + if (can_do_mlock() == 0) { + return ERR_PTR(-EPERM); + } + + hmem = kzalloc(sizeof *hmem, GFP_KERNEL); + if (hmem == NULL) { + return ERR_PTR(-ENOMEM); + } + hmem->context = kzalloc(sizeof(*(hmem->context)), GFP_KERNEL); + if ((hmem->context) == NULL) { + kfree(hmem); + return ERR_PTR(-ENOMEM); + } + hmem->context->device = device; + hmem->length = size; + hmem->address = addr; + hmem->page_shift = PAGE_SHIFT; + /* + * We ask for writable memory if any of the following + * access flags are set. "Local write" and "remote write" + * obviously require write access. "Remote atomic" can do + * things like fetch and add, which will modify memory, and + * "MW bind" can change permissions by binding a window. + */ + hmem->writable = !!(access & (RDMA_IB_ACCESS_LOCAL_WRITE | RDMA_IB_ACCESS_REMOTE_WRITE | + RDMA_IB_ACCESS_REMOTE_ATOMIC | RDMA_IB_ACCESS_MW_BIND)); + + if ((access & RDMA_IB_ACCESS_ON_DEMAND) != 0) { + kfree(hmem->context); + kfree(hmem); + dev_err(device, "[HMM, ERR] %s(%d): don't support odp \n", __func__, __LINE__); + return ERR_PTR(-ENOMEM); + } + hmem->odp_data = NULL; + + /* We assume the memory is from hugetlb until proved otherwise */ + hmem->hugetlb = 1; + page_list = (struct page **)__get_free_page(GFP_KERNEL); + if (page_list == NULL) { + kfree(hmem->context); + kfree(hmem); + return ERR_PTR(-ENOMEM); + } + + /* + * if we can't alloc the vma_list, it's not so bad; + * just assume the memory is not hugetlb memory + */ + vma_list = (struct vm_area_struct **)__get_free_page(GFP_KERNEL); + if (vma_list == NULL) { + hmem->hugetlb = 0; + } + npages = hmm_umem_num_pages(hmem); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + down_write(¤t->mm->mmap_sem); +#else + mmap_write_lock(current->mm); +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0) + locked_pages = npages + current->mm->pinned_vm; +#else + locked_pages = npages + atomic64_read(¤t->mm->pinned_vm); +#endif + lock_limit = rlimit(RLIMIT_MEMLOCK) >> PAGE_SHIFT; + if ((locked_pages > lock_limit) && !capable(CAP_IPC_LOCK)) { + ret = -ENOMEM; + goto out; + } + current_base = addr & PAGE_MASK; + if (npages == 0 || npages > UINT_MAX) { + ret = -EINVAL; + goto out; + } + ret = sg_alloc_table(&hmem->sg_head, (unsigned int)npages, GFP_KERNEL); + if (ret != 0) { + goto out; + } + +#ifdef HAVE_GET_USER_PAGES_GUP_FLAGS + if (hmem->writable == 0) { + gup_flags |= FOLL_FORCE; + } +#endif + + need_release = 1; + sg_list_start = hmem->sg_head.sgl; + + while (npages != 0) { +#ifdef HAVE_GET_USER_PAGES_8_PARAMS + ret = get_user_pages(current, current->mm, current_base, + min_t(unsigned long, npages, PAGE_SIZE / sizeof(struct page *)), 1, !hmem->writable, page_list, vma_list); +#else +#ifdef HAVE_GET_USER_PAGES_LONGTERM +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0)) + ret = get_user_pages(current_base, +#else + ret = get_user_pages_longterm(current_base, +#endif +#else + ret = get_user_pages(current_base, +#endif + min_t(unsigned long, npages, PAGE_SIZE / sizeof(struct page *)), +#ifdef HAVE_GET_USER_PAGES_GUP_FLAGS + gup_flags, page_list, vma_list); +#else + 1, !hmem->writable, page_list, vma_list); +#endif +#endif + + if (ret < 0) { + goto out; + } + hmem->npages += ret; + current_base += ret * PAGE_SIZE; + npages = (unsigned long)(npages - ret); + + for_each_sg(sg_list_start, sg, ret, i) + { + if (vma_list != NULL && !is_vm_hugetlb_page(vma_list[i])) { + hmem->hugetlb = 0; + } + sg_set_page(sg, page_list[i], PAGE_SIZE, 0); + } + + /* preparing for next loop */ + sg_list_start = sg; + } + + hmem->nmap = dma_map_sg_attrs(device, hmem->sg_head.sgl, hmem->npages, DMA_BIDIRECTIONAL, +#ifdef HAVE_STRUCT_DMA_ATTRS + &dma_attrs); +#else + dma_attrs); +#endif + if (hmem->nmap <= 0) { + ret = -ENOMEM; + goto out; + } + ret = 0; + +out: + if (ret < 0) { + if (need_release != 0) { + hmm_umemsg_release(device, hmem, 0); + } + kfree(hmem->context); + kfree(hmem); + } else { +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0) + current->mm->pinned_vm = locked_pages; +#else + atomic64_set(¤t->mm->pinned_vm, locked_pages); +#endif + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + up_write(¤t->mm->mmap_sem); +#else + mmap_write_unlock(current->mm); +#endif + if (vma_list != NULL) { + free_page((unsigned long)(uintptr_t)vma_list); + } + free_page((unsigned long)(uintptr_t)page_list); + return (ret < 0) ? ERR_PTR(ret) : hmem; +} + +/** + * hmm_umem_release - release memory pinned with ib_umem_get + * @hmem: umem struct to release + */ +void hmm_umem_release(struct hmm_umem *hmem) +{ + struct ib_ucontext *context = hmem->context; + struct mm_struct *mm = NULL; + struct task_struct *task = NULL; + unsigned long diff; + + if (hmem->odp_data) { + pr_err("[HMM, ERR] %s(%d): Don't support odp \n", __func__, __LINE__); + return; + } + + hmm_umemsg_release(context->device, hmem, 1); + task = get_pid_task(context->tgid, PIDTYPE_PID); + if (task == NULL) { + goto out; + } + mm = get_task_mm(task); + put_task_struct(task); + if (mm == NULL) { + goto out; + } + + diff = hmm_umem_num_pages(hmem); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + down_write(&mm->mmap_sem); +#else + mmap_write_lock(mm); +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0) + mm->pinned_vm -= diff; +#else + atomic64_sub(diff, &mm->pinned_vm); +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0) + up_write(&mm->mmap_sem); +#else + mmap_write_unlock(mm); +#endif + mmput(mm); +out: + kfree(context); + kfree(hmem); +} +#endif + +u32 hmm_umem_page_count(struct hmm_umem *hmem) +{ + u32 i; + u32 n; + struct scatterlist *sg = NULL; + + if (hmem->odp_data) { + return (u32)(hmm_umem_num_pages(hmem)); + } + + n = 0; + for_each_sg(hmem->sg_head.sgl, sg, hmem->nmap, i) n += sg_dma_len(sg) >> ((u32)hmem->page_shift); + + return n; +} diff --git a/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.h b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.h new file mode 100644 index 000000000..8daebd9c7 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/hmm/hmm_umem.h @@ -0,0 +1,124 @@ +/* *************************************************************************** + Copyright (c) Huawei Technologies Co., Ltd. 2018-2021. All rights reserved. + Description : structure and interface about umem +***************************************************************************** */ + +#ifndef HMM_UMEM_H +#define HMM_UMEM_H + +#include <linux/list.h> +#include <linux/scatterlist.h> +#include <linux/workqueue.h> +#include <linux/uaccess.h> +#include <linux/types.h> +#include <linux/mmu_notifier.h> +#include <linux/kernel.h> + +#ifdef ROCE_SERVICE +#include <rdma/ib_verbs.h> +#include <rdma/ib_umem.h> +#endif + + +#ifndef ROCE_SERVICE + +enum rdma_remove_reason { + /* Userspace requested uobject deletion. Call could fail */ + RDMA_REMOVE_DESTROY, + /* Context deletion. This call should delete the actual object itself */ + RDMA_REMOVE_CLOSE, + /* Driver is being hot-unplugged. This call should delete the actual object itself */ + RDMA_REMOVE_DRIVER_REMOVE, + /* Context is being cleaned-up, but commit was just completed */ + RDMA_REMOVE_DURING_CLEANUP, +}; + +struct ib_uverbs_file; +struct ib_rdmacg_object {}; +struct rb_root_cached_struct { + struct rb_node *rb_root; + struct rb_node *rb_leftmost; +}; + +struct ib_ucontext { + struct device *device; + struct ib_uverbs_file *ufile; + int closing; + + /* locking the uobjects_list */ + struct mutex uobjects_lock; + struct list_head uobjects; + /* protects cleanup process from other actions */ + struct rw_semaphore cleanup_rwsem; + enum rdma_remove_reason cleanup_reason; + + struct pid *tgid; + struct rb_root_cached_struct umem_tree; + /* + * Protects .umem_rbroot and tree, as well as odp_mrs_count and + * mmu notifiers registration. + */ + struct rw_semaphore umem_rwsem; + void (*invalidate_range)(void *umem, unsigned long start, unsigned long end); + + struct mmu_notifier mn; + atomic_t notifier_count; + /* A list of umems that don't have private mmu notifier counters yet. */ + struct list_head no_private_counters; + int odp_mrs_count; + + struct ib_rdmacg_object cg_obj; +}; + +struct ib_umem_odp; + +struct hmm_umem *hmm_umem_get(struct device *device, unsigned long addr, size_t size, int access, int dmasync); + +void hmm_umem_release(struct hmm_umem *hmem); + +#endif + +struct hmm_umem { + struct ib_ucontext *context; + size_t length; + unsigned long address; + int page_shift; + int writable; + int hugetlb; + struct work_struct work; + struct mm_struct *mm; + unsigned long diff; + struct ib_umem_odp *odp_data; + struct sg_table sg_head; + int nmap; + int npages; +}; + + +/* Returns the offset of the umem start relative to the first page. */ +static inline int hmm_umem_offset(const struct hmm_umem *umem) +{ + return umem->address & ~PAGE_MASK; +} + +/* Returns the first page of an ODP umem. */ +static inline unsigned long hmm_umem_start(struct hmm_umem *umem) +{ + return umem->address - hmm_umem_offset(umem); +} + +/* Returns the address of the page after the last one of an ODP umem. */ +static inline unsigned long hmm_umem_end(const struct hmm_umem *umem) +{ + return ALIGN(umem->address + umem->length, BIT((unsigned int)umem->page_shift)); +} + +static inline size_t hmm_umem_num_pages(struct hmm_umem *umem) +{ + return (size_t)(((unsigned long)(hmm_umem_end(umem) - hmm_umem_start(umem))) >> (unsigned long)umem->page_shift); +} + +u32 hmm_umem_page_count(struct hmm_umem *hmem); + + +#endif /* HMM_UMEM_H */ diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.c b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.c new file mode 100644 index 000000000..025c24efe --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.c @@ -0,0 +1,428 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": [COMM]" fmt + +#include <linux/netlink.h> +#include <linux/pci.h> +#include <linux/firmware.h> + +#include "hinic3_devlink.h" +#ifdef HAVE_DEVLINK_FLASH_UPDATE_PARAMS +#include "hinic3_common.h" +#include "hinic3_api_cmd.h" +#include "hinic3_mgmt.h" +#include "hinic3_hw.h" + +static bool check_image_valid(struct hinic3_hwdev *hwdev, const u8 *buf, + u32 size, struct host_image *host_image) +{ + struct firmware_image *fw_image = NULL; + u32 len = 0; + u32 i; + + fw_image = (struct firmware_image *)buf; + if (fw_image->fw_magic != FW_MAGIC_NUM) { + sdk_err(hwdev->dev_hdl, "Wrong fw magic read from file, fw_magic: 0x%x\n", + fw_image->fw_magic); + return false; + } + + if (fw_image->fw_info.section_cnt > FW_TYPE_MAX_NUM) { + sdk_err(hwdev->dev_hdl, "Wrong fw type number read from file, fw_type_num: 0x%x\n", + fw_image->fw_info.section_cnt); + return false; + } + + for (i = 0; i < fw_image->fw_info.section_cnt; i++) { + len += fw_image->section_info[i].section_len; + memcpy(&host_image->section_info[i], &fw_image->section_info[i], + sizeof(struct firmware_section)); + } + + if (len != fw_image->fw_len || + (u32)(fw_image->fw_len + FW_IMAGE_HEAD_SIZE) != size) { + sdk_err(hwdev->dev_hdl, "Wrong data size read from file\n"); + return false; + } + + host_image->image_info.total_len = fw_image->fw_len; + host_image->image_info.fw_version = fw_image->fw_version; + host_image->type_num = fw_image->fw_info.section_cnt; + host_image->device_id = fw_image->device_id; + + return true; +} + +static bool check_image_integrity(struct hinic3_hwdev *hwdev, struct host_image *host_image) +{ + u64 collect_section_type = 0; + u32 type, i; + + for (i = 0; i < host_image->type_num; i++) { + type = host_image->section_info[i].section_type; + if (collect_section_type & (1ULL << type)) { + sdk_err(hwdev->dev_hdl, "Duplicate section type: %u\n", type); + return false; + } + collect_section_type |= (1ULL << type); + } + + if ((collect_section_type & IMAGE_COLD_SUB_MODULES_MUST_IN) == + IMAGE_COLD_SUB_MODULES_MUST_IN && + (collect_section_type & IMAGE_CFG_SUB_MODULES_MUST_IN) != 0) + return true; + + sdk_err(hwdev->dev_hdl, "Failed to check file integrity, valid: 0x%llx, current: 0x%llx\n", + (IMAGE_COLD_SUB_MODULES_MUST_IN | IMAGE_CFG_SUB_MODULES_MUST_IN), + collect_section_type); + + return false; +} + +static bool check_image_device_type(struct hinic3_hwdev *hwdev, u32 device_type) +{ + struct comm_cmd_board_info board_info; + + memset(&board_info, 0, sizeof(board_info)); + if (hinic3_get_board_info(hwdev, &board_info.info, HINIC3_CHANNEL_COMM)) { + sdk_err(hwdev->dev_hdl, "Failed to get board info\n"); + return false; + } + + if (device_type == board_info.info.board_type) + return true; + + sdk_err(hwdev->dev_hdl, "The image device type: 0x%x doesn't match the firmware device type: 0x%x\n", + device_type, board_info.info.board_type); + + return false; +} + +static void encapsulate_update_cmd(struct hinic3_cmd_update_firmware *msg, + struct firmware_section *section_info, + const int *remain_len, u32 *send_len, u32 *send_pos) +{ + memset(msg->data, 0, sizeof(msg->data)); + msg->ctl_info.sf = (*remain_len == section_info->section_len) ? true : false; + msg->section_info.section_crc = section_info->section_crc; + msg->section_info.section_type = section_info->section_type; + msg->section_version = section_info->section_version; + msg->section_len = section_info->section_len; + msg->section_offset = *send_pos; + msg->ctl_info.bit_signed = section_info->section_flag & 0x1; + + if (*remain_len <= FW_FRAGMENT_MAX_LEN) { + msg->ctl_info.sl = true; + msg->ctl_info.fragment_len = (u32)(*remain_len); + *send_len += section_info->section_len; + } else { + msg->ctl_info.sl = false; + msg->ctl_info.fragment_len = FW_FRAGMENT_MAX_LEN; + *send_len += FW_FRAGMENT_MAX_LEN; + } +} + +static int hinic3_flash_firmware(struct hinic3_hwdev *hwdev, const u8 *data, + struct host_image *image) +{ + u32 send_pos, send_len, section_offset, i; + struct hinic3_cmd_update_firmware *update_msg = NULL; + u16 out_size = sizeof(*update_msg); + bool total_flag = false; + int remain_len, err; + + update_msg = kzalloc(sizeof(*update_msg), GFP_KERNEL); + if (!update_msg) { + sdk_err(hwdev->dev_hdl, "Failed to alloc update message\n"); + return -ENOMEM; + } + + for (i = 0; i < image->type_num; i++) { + section_offset = image->section_info[i].section_offset; + remain_len = (int)(image->section_info[i].section_len); + send_len = 0; + send_pos = 0; + + while (remain_len > 0) { + if (!total_flag) { + update_msg->total_len = image->image_info.total_len; + total_flag = true; + } else { + update_msg->total_len = 0; + } + + encapsulate_update_cmd(update_msg, &image->section_info[i], + &remain_len, &send_len, &send_pos); + + memcpy(update_msg->data, + ((data + FW_IMAGE_HEAD_SIZE) + section_offset) + send_pos, + update_msg->ctl_info.fragment_len); + + err = hinic3_pf_to_mgmt_sync(hwdev, HINIC3_MOD_COMM, COMM_MGMT_CMD_UPDATE_FW, + update_msg, sizeof(*update_msg), update_msg, &out_size, FW_UPDATE_MGMT_TIMEOUT); + if (err || !out_size || update_msg->msg_head.status) { + sdk_err(hwdev->dev_hdl, "Failed to update firmware, err: %d, status: 0x%x, out size: 0x%x\n", + err, update_msg->msg_head.status, out_size); + err = update_msg->msg_head.status ? + update_msg->msg_head.status : -EIO; + kfree(update_msg); + return err; + } + + send_pos = send_len; + remain_len = (int)(image->section_info[i].section_len - send_len); + } + } + + kfree(update_msg); + + return 0; +} + +static int hinic3_flash_update_notify(struct devlink *devlink, const struct firmware *fw, + struct host_image *image, struct netlink_ext_ack *extack) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + struct hinic3_hwdev *hwdev = devlink_dev->hwdev; + int err; + +#ifdef HAVE_DEVLINK_FW_FILE_NAME_MEMBER + devlink_flash_update_begin_notify(devlink); +#endif + devlink_flash_update_status_notify(devlink, "Flash firmware begin", NULL, 0, 0); + sdk_info(hwdev->dev_hdl, "Flash firmware begin\n"); + err = hinic3_flash_firmware(hwdev, fw->data, image); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to flash firmware, err: %d\n", err); + NL_SET_ERR_MSG_MOD(extack, "Flash firmware failed"); + devlink_flash_update_status_notify(devlink, "Flash firmware failed", NULL, 0, 0); + } else { + sdk_info(hwdev->dev_hdl, "Flash firmware end\n"); + devlink_flash_update_status_notify(devlink, "Flash firmware end", NULL, 0, 0); + } +#ifdef HAVE_DEVLINK_FW_FILE_NAME_MEMBER + devlink_flash_update_end_notify(devlink); +#endif + + return err; +} + +#ifdef HAVE_DEVLINK_FW_FILE_NAME_PARAM +static int hinic3_devlink_flash_update(struct devlink *devlink, const char *file_name, + const char *component, struct netlink_ext_ack *extack) +#else +static int hinic3_devlink_flash_update(struct devlink *devlink, + struct devlink_flash_update_params *params, + struct netlink_ext_ack *extack) +#endif +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + struct hinic3_hwdev *hwdev = devlink_dev->hwdev; +#ifdef HAVE_DEVLINK_FW_FILE_NAME_MEMBER + const struct firmware *fw = NULL; +#else + const struct firmware *fw = params->fw; +#endif + struct host_image *image = NULL; + int err; + + image = kzalloc(sizeof(*image), GFP_KERNEL); + if (!image) { + sdk_err(hwdev->dev_hdl, "Failed to alloc host image\n"); + err = -ENOMEM; + goto devlink_param_reset; + } + +#ifdef HAVE_DEVLINK_FW_FILE_NAME_MEMBER +#ifdef HAVE_DEVLINK_FW_FILE_NAME_PARAM + err = request_firmware_direct(&fw, file_name, hwdev->dev_hdl); +#else + err = request_firmware_direct(&fw, params->file_name, hwdev->dev_hdl); +#endif + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to request firmware\n"); + goto devlink_request_fw_err; + } +#endif + + if (!check_image_valid(hwdev, fw->data, (u32)(fw->size), image) || + !check_image_integrity(hwdev, image) || + !check_image_device_type(hwdev, image->device_id)) { + sdk_err(hwdev->dev_hdl, "Failed to check image\n"); + NL_SET_ERR_MSG_MOD(extack, "Check image failed"); + err = -EINVAL; + goto devlink_update_out; + } + + err = hinic3_flash_update_notify(devlink, fw, image, extack); + +devlink_update_out: +#ifdef HAVE_DEVLINK_FW_FILE_NAME_MEMBER + release_firmware(fw); + +devlink_request_fw_err: +#endif + kfree(image); + +devlink_param_reset: + /* reset activate_fw and switch_cfg after flash update operation */ + devlink_dev->activate_fw = FW_CFG_DEFAULT_INDEX; + devlink_dev->switch_cfg = FW_CFG_DEFAULT_INDEX; + + return err; +} + +static const struct devlink_ops hinic3_devlink_ops = { + .flash_update = hinic3_devlink_flash_update, +}; + +static int hinic3_devlink_get_activate_firmware_config(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + + ctx->val.vu8 = devlink_dev->activate_fw; + + return 0; +} + +static int hinic3_devlink_set_activate_firmware_config(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + struct hinic3_hwdev *hwdev = devlink_dev->hwdev; + int err; + + devlink_dev->activate_fw = ctx->val.vu8; + sdk_info(hwdev->dev_hdl, "Activate firmware begin\n"); + + err = hinic3_activate_firmware(hwdev, devlink_dev->activate_fw); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to activate firmware, err: %d\n", err); + return err; + } + + sdk_info(hwdev->dev_hdl, "Activate firmware end\n"); + + return 0; +} + +static int hinic3_devlink_get_switch_config(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + + ctx->val.vu8 = devlink_dev->switch_cfg; + + return 0; +} + +static int hinic3_devlink_set_switch_config(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + struct hinic3_hwdev *hwdev = devlink_dev->hwdev; + int err; + + devlink_dev->switch_cfg = ctx->val.vu8; + sdk_info(hwdev->dev_hdl, "Switch cfg begin"); + + err = hinic3_switch_config(hwdev, devlink_dev->switch_cfg); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to switch cfg, err: %d\n", err); + return err; + } + + sdk_info(hwdev->dev_hdl, "Switch cfg end\n"); + + return 0; +} + +static int hinic3_devlink_firmware_config_validate(struct devlink *devlink, u32 id, + union devlink_param_value val, + struct netlink_ext_ack *extack) +{ + struct hinic3_devlink *devlink_dev = devlink_priv(devlink); + struct hinic3_hwdev *hwdev = devlink_dev->hwdev; + u8 cfg_index = val.vu8; + + if (cfg_index > FW_CFG_MAX_INDEX) { + sdk_err(hwdev->dev_hdl, "Firmware cfg index out of range [0,7]\n"); + NL_SET_ERR_MSG_MOD(extack, "Firmware cfg index out of range [0,7]"); + return -ERANGE; + } + + return 0; +} + +static const struct devlink_param hinic3_devlink_params[] = { + DEVLINK_PARAM_DRIVER(HINIC3_DEVLINK_PARAM_ID_ACTIVATE_FW, + "activate_fw", DEVLINK_PARAM_TYPE_U8, + BIT(DEVLINK_PARAM_CMODE_PERMANENT), + hinic3_devlink_get_activate_firmware_config, + hinic3_devlink_set_activate_firmware_config, + hinic3_devlink_firmware_config_validate), + DEVLINK_PARAM_DRIVER(HINIC3_DEVLINK_PARAM_ID_SWITCH_CFG, + "switch_cfg", DEVLINK_PARAM_TYPE_U8, + BIT(DEVLINK_PARAM_CMODE_PERMANENT), + hinic3_devlink_get_switch_config, + hinic3_devlink_set_switch_config, + hinic3_devlink_firmware_config_validate), +}; + +int hinic3_init_devlink(struct hinic3_hwdev *hwdev) +{ + struct devlink *devlink = NULL; + struct pci_dev *pdev = NULL; + int err; + + devlink = devlink_alloc(&hinic3_devlink_ops, sizeof(struct hinic3_devlink)); + if (!devlink) { + sdk_err(hwdev->dev_hdl, "Failed to alloc devlink\n"); + return -ENOMEM; + } + + hwdev->devlink_dev = devlink_priv(devlink); + hwdev->devlink_dev->hwdev = hwdev; + hwdev->devlink_dev->activate_fw = FW_CFG_DEFAULT_INDEX; + hwdev->devlink_dev->switch_cfg = FW_CFG_DEFAULT_INDEX; + + pdev = hwdev->hwif->pdev; + err = devlink_register(devlink, &pdev->dev); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to register devlink\n"); + goto register_devlink_err; + } + + err = devlink_params_register(devlink, hinic3_devlink_params, + ARRAY_SIZE(hinic3_devlink_params)); + if (err) { + sdk_err(hwdev->dev_hdl, "Failed to register devlink params\n"); + goto register_devlink_params_err; + } + + devlink_params_publish(devlink); + + return 0; + +register_devlink_params_err: + devlink_unregister(devlink); + +register_devlink_err: + devlink_free(devlink); + + return -EFAULT; +} + +void hinic3_uninit_devlink(struct hinic3_hwdev *hwdev) +{ + struct devlink *devlink = priv_to_devlink(hwdev->devlink_dev); + + devlink_params_unpublish(devlink); + devlink_params_unregister(devlink, hinic3_devlink_params, + ARRAY_SIZE(hinic3_devlink_params)); + devlink_unregister(devlink); + devlink_free(devlink); +} +#endif diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.h b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.h new file mode 100644 index 000000000..a0c14ea17 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_devlink.h @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#ifndef HINIC3_DEVLINK_H +#define HINIC3_DEVLINK_H + +#include "ossl_knl.h" +#include "hinic3_hwdev.h" + +#define FW_MAGIC_NUM 0x5a5a1100 +#define FW_IMAGE_HEAD_SIZE 4096 +#define FW_FRAGMENT_MAX_LEN 1536 +#define FW_CFG_DEFAULT_INDEX 0xFF +#define FW_TYPE_MAX_NUM 0x40 +#define FW_CFG_MAX_INDEX 7 + +#ifdef HAVE_DEVLINK_FLASH_UPDATE_PARAMS +enum hinic3_devlink_param_id { + HINIC3_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, + HINIC3_DEVLINK_PARAM_ID_ACTIVATE_FW, + HINIC3_DEVLINK_PARAM_ID_SWITCH_CFG, +}; +#endif + +enum hinic3_firmware_type { + UP_FW_UPDATE_MIN_TYPE1 = 0x0, + UP_FW_UPDATE_UP_TEXT = 0x0, + UP_FW_UPDATE_UP_DATA = 0x1, + UP_FW_UPDATE_UP_DICT = 0x2, + UP_FW_UPDATE_TILE_PCPTR = 0x3, + UP_FW_UPDATE_TILE_TEXT = 0x4, + UP_FW_UPDATE_TILE_DATA = 0x5, + UP_FW_UPDATE_TILE_DICT = 0x6, + UP_FW_UPDATE_PPE_STATE = 0x7, + UP_FW_UPDATE_PPE_BRANCH = 0x8, + UP_FW_UPDATE_PPE_EXTACT = 0x9, + UP_FW_UPDATE_MAX_TYPE1 = 0x9, + UP_FW_UPDATE_CFG0 = 0xa, + UP_FW_UPDATE_CFG1 = 0xb, + UP_FW_UPDATE_CFG2 = 0xc, + UP_FW_UPDATE_CFG3 = 0xd, + UP_FW_UPDATE_MAX_TYPE1_CFG = 0xd, + + UP_FW_UPDATE_MIN_TYPE2 = 0x14, + UP_FW_UPDATE_MAX_TYPE2 = 0x14, + + UP_FW_UPDATE_MIN_TYPE3 = 0x18, + UP_FW_UPDATE_PHY = 0x18, + UP_FW_UPDATE_BIOS = 0x19, + UP_FW_UPDATE_HLINK_ONE = 0x1a, + UP_FW_UPDATE_HLINK_TWO = 0x1b, + UP_FW_UPDATE_HLINK_THR = 0x1c, + UP_FW_UPDATE_MAX_TYPE3 = 0x1c, + + UP_FW_UPDATE_MIN_TYPE4 = 0x20, + UP_FW_UPDATE_L0FW = 0x20, + UP_FW_UPDATE_L1FW = 0x21, + UP_FW_UPDATE_BOOT = 0x22, + UP_FW_UPDATE_SEC_DICT = 0x23, + UP_FW_UPDATE_HOT_PATCH0 = 0x24, + UP_FW_UPDATE_HOT_PATCH1 = 0x25, + UP_FW_UPDATE_HOT_PATCH2 = 0x26, + UP_FW_UPDATE_HOT_PATCH3 = 0x27, + UP_FW_UPDATE_HOT_PATCH4 = 0x28, + UP_FW_UPDATE_HOT_PATCH5 = 0x29, + UP_FW_UPDATE_HOT_PATCH6 = 0x2a, + UP_FW_UPDATE_HOT_PATCH7 = 0x2b, + UP_FW_UPDATE_HOT_PATCH8 = 0x2c, + UP_FW_UPDATE_HOT_PATCH9 = 0x2d, + UP_FW_UPDATE_HOT_PATCH10 = 0x2e, + UP_FW_UPDATE_HOT_PATCH11 = 0x2f, + UP_FW_UPDATE_HOT_PATCH12 = 0x30, + UP_FW_UPDATE_HOT_PATCH13 = 0x31, + UP_FW_UPDATE_HOT_PATCH14 = 0x32, + UP_FW_UPDATE_HOT_PATCH15 = 0x33, + UP_FW_UPDATE_HOT_PATCH16 = 0x34, + UP_FW_UPDATE_HOT_PATCH17 = 0x35, + UP_FW_UPDATE_HOT_PATCH18 = 0x36, + UP_FW_UPDATE_HOT_PATCH19 = 0x37, + UP_FW_UPDATE_MAX_TYPE4 = 0x37, + + UP_FW_UPDATE_MIN_TYPE5 = 0x3a, + UP_FW_UPDATE_OPTION_ROM = 0x3a, + UP_FW_UPDATE_MAX_TYPE5 = 0x3a, + + UP_FW_UPDATE_MIN_TYPE6 = 0x3e, + UP_FW_UPDATE_MAX_TYPE6 = 0x3e, + + UP_FW_UPDATE_MIN_TYPE7 = 0x40, + UP_FW_UPDATE_MAX_TYPE7 = 0x40, +}; + +#define IMAGE_MPU_ALL_IN (BIT_ULL(UP_FW_UPDATE_UP_TEXT) | \ + BIT_ULL(UP_FW_UPDATE_UP_DATA) | \ + BIT_ULL(UP_FW_UPDATE_UP_DICT)) + +#define IMAGE_NPU_ALL_IN (BIT_ULL(UP_FW_UPDATE_TILE_PCPTR) | \ + BIT_ULL(UP_FW_UPDATE_TILE_TEXT) | \ + BIT_ULL(UP_FW_UPDATE_TILE_DATA) | \ + BIT_ULL(UP_FW_UPDATE_TILE_DICT) | \ + BIT_ULL(UP_FW_UPDATE_PPE_STATE) | \ + BIT_ULL(UP_FW_UPDATE_PPE_BRANCH) | \ + BIT_ULL(UP_FW_UPDATE_PPE_EXTACT)) + +#define IMAGE_COLD_SUB_MODULES_MUST_IN (IMAGE_MPU_ALL_IN | IMAGE_NPU_ALL_IN) + +#define IMAGE_CFG_SUB_MODULES_MUST_IN (BIT_ULL(UP_FW_UPDATE_CFG0) | \ + BIT_ULL(UP_FW_UPDATE_CFG1) | \ + BIT_ULL(UP_FW_UPDATE_CFG2) | \ + BIT_ULL(UP_FW_UPDATE_CFG3)) + +struct firmware_section { + u32 section_len; + u32 section_offset; + u32 section_version; + u32 section_type; + u32 section_crc; + u32 section_flag; +}; + +struct firmware_image { + u32 fw_version; + u32 fw_len; + u32 fw_magic; + struct { + u32 section_cnt : 16; + u32 rsvd : 16; + } fw_info; + struct firmware_section section_info[FW_TYPE_MAX_NUM]; + u32 device_id; /* cfg fw board_type value */ + u32 rsvd0[101]; /* device_id and rsvd0[101] is update_head_extend_info */ + u32 rsvd1[534]; /* big bin file total size 4096B */ + u32 bin_data; /* obtain the address for use */ +}; + +struct host_image { + struct firmware_section section_info[FW_TYPE_MAX_NUM]; + struct { + u32 total_len; + u32 fw_version; + } image_info; + u32 type_num; + u32 device_id; +}; + +struct hinic3_cmd_update_firmware { + struct mgmt_msg_head msg_head; + + struct { + u32 sl : 1; + u32 sf : 1; + u32 flag : 1; + u32 bit_signed : 1; + u32 reserved : 12; + u32 fragment_len : 16; + } ctl_info; + + struct { + u32 section_crc; + u32 section_type; + } section_info; + + u32 total_len; + u32 section_len; + u32 section_version; + u32 section_offset; + u32 data[384]; +}; + +int hinic3_init_devlink(struct hinic3_hwdev *hwdev); +void hinic3_uninit_devlink(struct hinic3_hwdev *hwdev); + +#endif diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.c b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.c new file mode 100644 index 000000000..8eaa332b8 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.c @@ -0,0 +1,605 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#include "ossl_knl.h" +#include "hinic3_mt.h" +#include "hinic3_crm.h" +#include "hinic3_hw.h" +#include "mpu_inband_cmd.h" +#include "hinic3_hw_mt.h" + +#define HINIC3_CMDQ_BUF_MAX_SIZE 2048U +#define DW_WIDTH 4 + +#define MSG_MAX_IN_SIZE (2048 * 1024) +#define MSG_MAX_OUT_SIZE (2048 * 1024) + +#define API_CSR_MAX_RD_LEN (4 * 1024 * 1024) + +/* completion timeout interval, unit is millisecond */ +#define MGMT_MSG_UPDATE_TIMEOUT 200000U + +void free_buff_in(void *hwdev, const struct msg_module *nt_msg, void *buf_in) +{ + if (!buf_in) + return; + + if (nt_msg->module == SEND_TO_NPU) + hinic3_free_cmd_buf(hwdev, buf_in); + else + kfree(buf_in); +} + +void free_buff_out(void *hwdev, struct msg_module *nt_msg, + void *buf_out) +{ + if (!buf_out) + return; + + if (nt_msg->module == SEND_TO_NPU && + !nt_msg->npu_cmd.direct_resp) + hinic3_free_cmd_buf(hwdev, buf_out); + else + kfree(buf_out); +} + +int alloc_buff_in(void *hwdev, struct msg_module *nt_msg, + u32 in_size, void **buf_in) +{ + void *msg_buf = NULL; + + if (!in_size) + return 0; + + if (nt_msg->module == SEND_TO_NPU) { + struct hinic3_cmd_buf *cmd_buf = NULL; + + if (in_size > HINIC3_CMDQ_BUF_MAX_SIZE) { + pr_err("Cmdq in size(%u) more than 2KB\n", in_size); + return -ENOMEM; + } + + cmd_buf = hinic3_alloc_cmd_buf(hwdev); + if (!cmd_buf) { + pr_err("Alloc cmdq cmd buffer failed in %s\n", + __func__); + return -ENOMEM; + } + msg_buf = cmd_buf->buf; + *buf_in = (void *)cmd_buf; + cmd_buf->size = (u16)in_size; + } else { + if (in_size > MSG_MAX_IN_SIZE) { + pr_err("In size(%u) more than 2M\n", in_size); + return -ENOMEM; + } + msg_buf = kzalloc(in_size, GFP_KERNEL); + *buf_in = msg_buf; + } + if (!(*buf_in)) { + pr_err("Alloc buffer in failed\n"); + return -ENOMEM; + } + + if (copy_from_user(msg_buf, nt_msg->in_buf, in_size)) { + pr_err("%s:%d: Copy from user failed\n", + __func__, __LINE__); + free_buff_in(hwdev, nt_msg, *buf_in); + return -EFAULT; + } + + return 0; +} + +int alloc_buff_out(void *hwdev, struct msg_module *nt_msg, + u32 out_size, void **buf_out) +{ + if (!out_size) + return 0; + + if (nt_msg->module == SEND_TO_NPU && + !nt_msg->npu_cmd.direct_resp) { + struct hinic3_cmd_buf *cmd_buf = NULL; + + if (out_size > HINIC3_CMDQ_BUF_MAX_SIZE) { + pr_err("Cmdq out size(%u) more than 2KB\n", out_size); + return -ENOMEM; + } + + cmd_buf = hinic3_alloc_cmd_buf(hwdev); + *buf_out = (void *)cmd_buf; + } else { + if (out_size > MSG_MAX_OUT_SIZE) { + pr_err("out size(%u) more than 2M\n", out_size); + return -ENOMEM; + } + *buf_out = kzalloc(out_size, GFP_KERNEL); + } + if (!(*buf_out)) { + pr_err("Alloc buffer out failed\n"); + return -ENOMEM; + } + + return 0; +} + +int copy_buf_out_to_user(struct msg_module *nt_msg, + u32 out_size, void *buf_out) +{ + int ret = 0; + void *msg_out = NULL; + + if (out_size == 0 || !buf_out) + return 0; + + if (nt_msg->module == SEND_TO_NPU && + !nt_msg->npu_cmd.direct_resp) + msg_out = ((struct hinic3_cmd_buf *)buf_out)->buf; + else + msg_out = buf_out; + + if (copy_to_user(nt_msg->out_buf, msg_out, out_size)) + ret = -EFAULT; + + return ret; +} + +int get_func_type(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + u16 func_type; + + if (*out_size != sizeof(u16) || !buf_out) { + pr_err("Unexpect out buf size from user :%u, expect: %lu\n", + *out_size, sizeof(u16)); + return -EFAULT; + } + + func_type = hinic3_func_type(hinic3_get_sdk_hwdev_by_lld(lld_dev)); + + *(u16 *)buf_out = func_type; + return 0; +} + +int get_func_id(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + u16 func_id; + + if (*out_size != sizeof(u16) || !buf_out) { + pr_err("Unexpect out buf size from user :%u, expect: %lu\n", + *out_size, sizeof(u16)); + return -EFAULT; + } + + func_id = hinic3_global_func_id(hinic3_get_sdk_hwdev_by_lld(lld_dev)); + *(u16 *)buf_out = func_id; + + return 0; +} + +int get_hw_driver_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + return hinic3_dbg_get_hw_stats(hinic3_get_sdk_hwdev_by_lld(lld_dev), + buf_out, out_size); +} + +int clear_hw_driver_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + u16 size; + + size = hinic3_dbg_clear_hw_stats(hinic3_get_sdk_hwdev_by_lld(lld_dev)); + if (*out_size != size) { + pr_err("Unexpect out buf size from user :%u, expect: %u\n", + *out_size, size); + return -EFAULT; + } + + return 0; +} + +int get_self_test_result(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + u32 result; + + if (*out_size != sizeof(u32) || !buf_out) { + pr_err("Unexpect out buf size from user :%u, expect: %lu\n", + *out_size, sizeof(u32)); + return -EFAULT; + } + + result = hinic3_get_self_test_result(hinic3_get_sdk_hwdev_by_lld(lld_dev)); + *(u32 *)buf_out = result; + + return 0; +} + +int get_chip_faults_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + u32 offset = 0; + struct nic_cmd_chip_fault_stats *fault_info = NULL; + + if (!buf_in || !buf_out || *out_size != sizeof(*fault_info) || + in_size != sizeof(*fault_info)) { + pr_err("Unexpect out buf size from user: %u, expect: %lu\n", + *out_size, sizeof(*fault_info)); + return -EFAULT; + } + fault_info = (struct nic_cmd_chip_fault_stats *)buf_in; + offset = fault_info->offset; + + fault_info = (struct nic_cmd_chip_fault_stats *)buf_out; + hinic3_get_chip_fault_stats(hinic3_get_sdk_hwdev_by_lld(lld_dev), + fault_info->chip_fault_stats, offset); + + return 0; +} + +static u32 get_up_timeout_val(enum hinic3_mod_type mod, u16 cmd) +{ + if (mod == HINIC3_MOD_COMM && + (cmd == COMM_MGMT_CMD_UPDATE_FW || + cmd == COMM_MGMT_CMD_UPDATE_BIOS || + cmd == COMM_MGMT_CMD_ACTIVE_FW || + cmd == COMM_MGMT_CMD_SWITCH_CFG || + cmd == COMM_MGMT_CMD_HOT_ACTIVE_FW)) + return MGMT_MSG_UPDATE_TIMEOUT; + + return 0; /* use default mbox/apichain timeout time */ +} + +static int api_csr_read(void *hwdev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + struct up_log_msg_st *up_log_msg = (struct up_log_msg_st *)buf_in; + u8 *buf_out_tmp = (u8 *)buf_out; + int ret = 0; + u32 rd_len; + u32 rd_addr; + u32 rd_cnt = 0; + u32 offset = 0; + u8 node_id; + u32 i; + + if (!buf_in || !buf_out || in_size != sizeof(*up_log_msg) || + *out_size != up_log_msg->rd_len || up_log_msg->rd_len % DW_WIDTH != 0) + return -EINVAL; + + rd_len = up_log_msg->rd_len; + rd_addr = up_log_msg->addr; + node_id = (u8)nt_msg->mpu_cmd.mod; + + rd_cnt = rd_len / DW_WIDTH; + + for (i = 0; i < rd_cnt; i++) { + ret = hinic3_api_csr_rd32(hwdev, node_id, + rd_addr + offset, + (u32 *)(buf_out_tmp + offset)); + if (ret) { + pr_err("Csr rd fail, err: %d, node_id: %u, csr addr: 0x%08x\n", + ret, node_id, rd_addr + offset); + return ret; + } + offset += DW_WIDTH; + } + *out_size = rd_len; + + return ret; +} + +static int api_csr_write(void *hwdev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, + u32 *out_size) +{ + struct csr_write_st *csr_write_msg = (struct csr_write_st *)buf_in; + int ret = 0; + u32 rd_len; + u32 rd_addr; + u32 rd_cnt = 0; + u32 offset = 0; + u8 node_id; + u32 i; + u8 *data = NULL; + + if (!buf_in || in_size != sizeof(*csr_write_msg) || csr_write_msg->rd_len == 0 || + csr_write_msg->rd_len > API_CSR_MAX_RD_LEN || csr_write_msg->rd_len % DW_WIDTH != 0) + return -EINVAL; + + rd_len = csr_write_msg->rd_len; + rd_addr = csr_write_msg->addr; + node_id = (u8)nt_msg->mpu_cmd.mod; + + rd_cnt = rd_len / DW_WIDTH; + + data = kzalloc(rd_len, GFP_KERNEL); + if (!data) { + pr_err("No more memory\n"); + return -EFAULT; + } + if (copy_from_user(data, (void *)csr_write_msg->data, rd_len)) { + pr_err("Copy information from user failed\n"); + kfree(data); + return -EFAULT; + } + + for (i = 0; i < rd_cnt; i++) { + ret = hinic3_api_csr_wr32(hwdev, node_id, + rd_addr + offset, + *((u32 *)(data + offset))); + if (ret) { + pr_err("Csr wr fail, ret: %d, node_id: %u, csr addr: 0x%08x\n", + ret, rd_addr + offset, node_id); + kfree(data); + return ret; + } + offset += DW_WIDTH; + } + + *out_size = 0; + kfree(data); + return ret; +} + +int send_to_mpu(void *hwdev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + enum hinic3_mod_type mod; + u32 timeout; + int ret = 0; + u16 cmd; + + mod = (enum hinic3_mod_type)nt_msg->mpu_cmd.mod; + cmd = nt_msg->mpu_cmd.cmd; + + if (nt_msg->mpu_cmd.api_type == API_TYPE_MBOX || nt_msg->mpu_cmd.api_type == API_TYPE_CLP) { + timeout = get_up_timeout_val(mod, cmd); + + if (nt_msg->mpu_cmd.api_type == API_TYPE_MBOX) + ret = hinic3_msg_to_mgmt_sync(hwdev, mod, cmd, buf_in, (u16)in_size, + buf_out, (u16 *)(u8 *)out_size, timeout, + HINIC3_CHANNEL_DEFAULT); + else + ret = hinic3_clp_to_mgmt(hwdev, mod, cmd, buf_in, (u16)in_size, + buf_out, (u16 *)out_size); + if (ret) { + pr_err("Message to mgmt cpu return fail, mod: %d, cmd: %u\n", mod, cmd); + return ret; + } + } else if (nt_msg->mpu_cmd.api_type == API_TYPE_API_CHAIN_BYPASS) { + if (nt_msg->mpu_cmd.cmd == API_CSR_WRITE) + return api_csr_write(hwdev, nt_msg, buf_in, in_size, buf_out, out_size); + + ret = api_csr_read(hwdev, nt_msg, buf_in, in_size, buf_out, out_size); + } else if (nt_msg->mpu_cmd.api_type == API_TYPE_API_CHAIN_TO_MPU) { + timeout = get_up_timeout_val(mod, cmd); + if (hinic3_pcie_itf_id(hwdev) != SPU_HOST_ID) + ret = hinic3_msg_to_mgmt_api_chain_sync(hwdev, mod, cmd, buf_in, + (u16)in_size, buf_out, + (u16 *)(u8 *)out_size, timeout); + else + ret = hinic3_msg_to_mgmt_sync(hwdev, mod, cmd, buf_in, (u16)in_size, + buf_out, (u16 *)(u8 *)out_size, timeout, + HINIC3_CHANNEL_DEFAULT); + if (ret) { + pr_err("Message to mgmt api chain cpu return fail, mod: %d, cmd: %u\n", + mod, cmd); + return ret; + } + } else { + pr_err("Unsupported api_type %u\n", nt_msg->mpu_cmd.api_type); + return -EINVAL; + } + + return ret; +} + +int send_to_npu(void *hwdev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + int ret = 0; + u8 cmd; + enum hinic3_mod_type mod; + + mod = (enum hinic3_mod_type)nt_msg->npu_cmd.mod; + cmd = nt_msg->npu_cmd.cmd; + + if (nt_msg->npu_cmd.direct_resp) { + ret = hinic3_cmdq_direct_resp(hwdev, mod, cmd, + buf_in, buf_out, 0, + HINIC3_CHANNEL_DEFAULT); + if (ret) + pr_err("Send direct cmdq failed, err: %d\n", ret); + } else { + ret = hinic3_cmdq_detail_resp(hwdev, mod, cmd, buf_in, buf_out, + NULL, 0, HINIC3_CHANNEL_DEFAULT); + if (ret) + pr_err("Send detail cmdq failed, err: %d\n", ret); + } + + return ret; +} + +static int sm_rd16(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u16 val1; + int ret; + + ret = hinic3_sm_ctr_rd16(hwdev, node, instance, id, &val1); + if (ret != 0) { + pr_err("Get sm ctr information (16 bits)failed!\n"); + val1 = 0xffff; + } + + buf_out->val1 = val1; + + return ret; +} + +static int sm_rd32(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u32 val1; + int ret; + + ret = hinic3_sm_ctr_rd32(hwdev, node, instance, id, &val1); + if (ret) { + pr_err("Get sm ctr information (32 bits)failed!\n"); + val1 = ~0; + } + + buf_out->val1 = val1; + + return ret; +} + +static int sm_rd32_clear(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u32 val1; + int ret; + + ret = hinic3_sm_ctr_rd32_clear(hwdev, node, instance, id, &val1); + if (ret) { + pr_err("Get sm ctr clear information(32 bits) failed!\n"); + val1 = ~0; + } + + buf_out->val1 = val1; + + return ret; +} + +static int sm_rd64_pair(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u64 val1 = 0, val2 = 0; + int ret; + + ret = hinic3_sm_ctr_rd64_pair(hwdev, node, instance, id, &val1, &val2); + if (ret) { + pr_err("Get sm ctr information (64 bits pair)failed!\n"); + val1 = ~0; + val2 = ~0; + } + + buf_out->val1 = val1; + buf_out->val2 = val2; + + return ret; +} + +static int sm_rd64_pair_clear(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u64 val1 = 0; + u64 val2 = 0; + int ret; + + ret = hinic3_sm_ctr_rd64_pair_clear(hwdev, node, instance, id, &val1, + &val2); + if (ret) { + pr_err("Get sm ctr clear information(64 bits pair) failed!\n"); + val1 = ~0; + val2 = ~0; + } + + buf_out->val1 = val1; + buf_out->val2 = val2; + + return ret; +} + +static int sm_rd64(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u64 val1; + int ret; + + ret = hinic3_sm_ctr_rd64(hwdev, node, instance, id, &val1); + if (ret) { + pr_err("Get sm ctr information (64 bits)failed!\n"); + val1 = ~0; + } + buf_out->val1 = val1; + + return ret; +} + +static int sm_rd64_clear(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out) +{ + u64 val1; + int ret; + + ret = hinic3_sm_ctr_rd64_clear(hwdev, node, instance, id, &val1); + if (ret) { + pr_err("Get sm ctr clear information(64 bits) failed!\n"); + val1 = ~0; + } + buf_out->val1 = val1; + + return ret; +} + +typedef int (*sm_module)(void *hwdev, u32 id, u8 instance, + u8 node, struct sm_out_st *buf_out); + +struct sm_module_handle { + enum sm_cmd_type sm_cmd_name; + sm_module sm_func; +}; + +const struct sm_module_handle sm_module_cmd_handle[] = { + {SM_CTR_RD16, sm_rd16}, + {SM_CTR_RD32, sm_rd32}, + {SM_CTR_RD64_PAIR, sm_rd64_pair}, + {SM_CTR_RD64, sm_rd64}, + {SM_CTR_RD32_CLEAR, sm_rd32_clear}, + {SM_CTR_RD64_PAIR_CLEAR, sm_rd64_pair_clear}, + {SM_CTR_RD64_CLEAR, sm_rd64_clear} +}; + +int send_to_sm(void *hwdev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + struct sm_in_st *sm_in = buf_in; + struct sm_out_st *sm_out = buf_out; + u32 msg_formate; + int index, num_cmds = ARRAY_LEN(sm_module_cmd_handle); + int ret = 0; + + if (!nt_msg || !buf_in || !buf_out || in_size != sizeof(*sm_in) || *out_size != sizeof(*sm_out)) { + pr_err("Unexpect out buf size :%u, in buf size: %u\n", + *out_size, in_size); + return -EINVAL; + } + msg_formate = nt_msg->msg_formate; + + for (index = 0; index < num_cmds; index++) { + if (msg_formate != sm_module_cmd_handle[index].sm_cmd_name) + continue; + + ret = sm_module_cmd_handle[index].sm_func(hwdev, (u32)sm_in->id, + (u8)sm_in->instance, + (u8)sm_in->node, sm_out); + break; + } + + if (index == num_cmds) { + pr_err("Can't find callback for %d\n", msg_formate); + return -EINVAL; + } + if (ret != 0) + pr_err("Get sm information fail, id:%d, instance:%d, node:%d\n", + sm_in->id, sm_in->instance, sm_in->node); + + *out_size = sizeof(struct sm_out_st); + + return ret; +} + diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.h b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.h new file mode 100644 index 000000000..933020082 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_hw_mt.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#ifndef HINIC3_HW_MT_H +#define HINIC3_HW_MT_H + +#include "hinic3_lld.h" + +struct sm_in_st { + int node; + int id; + int instance; +}; + +struct sm_out_st { + u64 val1; + u64 val2; +}; + +struct up_log_msg_st { + u32 rd_len; + u32 addr; +}; + +struct csr_write_st { + u32 rd_len; + u32 addr; + u8 *data; +}; + +int get_func_type(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +int get_func_id(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +int get_hw_driver_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +int clear_hw_driver_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +int get_self_test_result(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +int get_chip_faults_stats(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size); + +#endif diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.c b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.c new file mode 100644 index 000000000..782f314c3 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.c @@ -0,0 +1,982 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": [COMM]" fmt + +#include <net/sock.h> +#include <linux/cdev.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/pci.h> + +#include "ossl_knl.h" +#include "hinic3_mt.h" +#include "hinic3_crm.h" +#include "hinic3_hw.h" +#include "hinic3_hw_cfg.h" +#include "hinic3_dev_mgmt.h" +#include "hinic3_hwdev.h" +#include "hinic3_lld.h" +#include "hinic3_hw_mt.h" +#include "hinic3_nictool.h" + +static int g_nictool_ref_cnt; + +static dev_t g_dev_id = {0}; +static struct class *g_nictool_class; +static struct cdev g_nictool_cdev; + +#define HINIC3_MAX_BUF_SIZE (2048 * 1024) + +void *g_card_node_array[MAX_CARD_NUM] = {0}; +void *g_card_vir_addr[MAX_CARD_NUM] = {0}; +u64 g_card_phy_addr[MAX_CARD_NUM] = {0}; +int card_id; + +#define HIADM3_DEV_PATH "/dev/hinic3_nictool_dev" +#define HIADM3_DEV_CLASS "hinic3_nictool_class" +#define HIADM3_DEV_NAME "hinic3_nictool_dev" + +typedef int (*hw_driv_module)(struct hinic3_lld_dev *lld_dev, const void *buf_in, + u32 in_size, void *buf_out, u32 *out_size); +struct hw_drv_module_handle { + enum driver_cmd_type driv_cmd_name; + hw_driv_module driv_func; +}; + +static int get_single_card_info(struct hinic3_lld_dev *lld_dev, const void *buf_in, + u32 in_size, void *buf_out, u32 *out_size) +{ + if (!buf_out || *out_size != sizeof(struct card_info)) { + pr_err("buf_out is NULL, or out_size != %lu\n", sizeof(struct card_info)); + return -EINVAL; + } + + hinic3_get_card_info(hinic3_get_sdk_hwdev_by_lld(lld_dev), buf_out); + + return 0; +} + +static int is_driver_in_vm(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + bool in_host = false; + + if (!buf_out || (*out_size != sizeof(u8))) { + pr_err("buf_out is NULL, or out_size != %lu\n", sizeof(u8)); + return -EINVAL; + } + + in_host = hinic3_is_in_host(); + if (in_host) + *((u8 *)buf_out) = 0; + else + *((u8 *)buf_out) = 1; + + return 0; +} + +static int get_all_chip_id_cmd(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + if (*out_size != sizeof(struct nic_card_id) || !buf_out) { + pr_err("Invalid parameter: out_buf_size %u, expect %lu\n", + *out_size, sizeof(struct nic_card_id)); + return -EFAULT; + } + + hinic3_get_all_chip_id(buf_out); + + return 0; +} + +static int get_card_usr_api_chain_mem(int card_idx) +{ + unsigned char *tmp = NULL; + int i; + + card_id = card_idx; + if (!g_card_vir_addr[card_idx]) { + g_card_vir_addr[card_idx] = + (void *)ossl_get_free_pages(GFP_KERNEL, + DBGTOOL_PAGE_ORDER); + if (!g_card_vir_addr[card_idx]) { + pr_err("Alloc api chain memory fail for card %d!\n", card_idx); + return -EFAULT; + } + + memset(g_card_vir_addr[card_idx], 0, + PAGE_SIZE * (1 << DBGTOOL_PAGE_ORDER)); + + g_card_phy_addr[card_idx] = + virt_to_phys(g_card_vir_addr[card_idx]); + if (!g_card_phy_addr[card_idx]) { + pr_err("phy addr for card %d is 0\n", card_idx); + free_pages((unsigned long)g_card_vir_addr[card_idx], DBGTOOL_PAGE_ORDER); + g_card_vir_addr[card_idx] = NULL; + return -EFAULT; + } + + tmp = g_card_vir_addr[card_idx]; + for (i = 0; i < (1 << DBGTOOL_PAGE_ORDER); i++) { + SetPageReserved(virt_to_page(tmp)); + tmp += PAGE_SIZE; + } + } + + return 0; +} + +static void chipif_get_all_pf_dev_info(struct pf_dev_info *dev_info, int card_idx, + void **g_func_handle_array) +{ + u32 func_idx; + void *hwdev = NULL; + struct pci_dev *pdev = NULL; + + for (func_idx = 0; func_idx < PF_DEV_INFO_NUM; func_idx++) { + hwdev = (void *)g_func_handle_array[func_idx]; + + dev_info[func_idx].phy_addr = g_card_phy_addr[card_idx]; + + if (!hwdev) { + dev_info[func_idx].bar0_size = 0; + dev_info[func_idx].bus = 0; + dev_info[func_idx].slot = 0; + dev_info[func_idx].func = 0; + } else { + pdev = (struct pci_dev *)hinic3_get_pcidev_hdl(hwdev); + dev_info[func_idx].bar0_size = + pci_resource_len(pdev, 0); + dev_info[func_idx].bus = pdev->bus->number; + dev_info[func_idx].slot = PCI_SLOT(pdev->devfn); + dev_info[func_idx].func = PCI_FUNC(pdev->devfn); + } + } +} + +static int get_pf_dev_info(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct pf_dev_info *dev_info = buf_out; + struct card_node *card_info = hinic3_get_chip_node_by_lld(lld_dev); + int id, err; + + if (!buf_out || *out_size != sizeof(struct pf_dev_info) * PF_DEV_INFO_NUM) { + pr_err("Invalid parameter: out_buf_size %u, expect %lu\n", + *out_size, sizeof(*dev_info) * PF_DEV_INFO_NUM); + return -EFAULT; + } + + err = sscanf(card_info->chip_name, HINIC3_CHIP_NAME "%d", &id); + if (err <= 0) { + pr_err("Failed to get card id\n"); + return err; + } + + if (id >= MAX_CARD_NUM || id < 0) { + pr_err("chip id %d exceed limit[0-%d]\n", id, MAX_CARD_NUM - 1); + return -EINVAL; + } + + chipif_get_all_pf_dev_info(dev_info, id, card_info->func_handle_array); + + err = get_card_usr_api_chain_mem(id); + if (err) { + pr_err("Faile to get api chain memory for userspace %s\n", + card_info->chip_name); + return -EFAULT; + } + + return 0; +} + +static void dbgtool_knl_free_mem(int id) +{ + unsigned char *tmp = NULL; + int i; + + if (id < 0 || id >= MAX_CARD_NUM) { + pr_err("Invalid card id\n"); + return; + } + + if (!g_card_vir_addr[id]) + return; + + tmp = g_card_vir_addr[id]; + for (i = 0; i < (1 << DBGTOOL_PAGE_ORDER); i++) { + ClearPageReserved(virt_to_page(tmp)); + tmp += PAGE_SIZE; + } + + free_pages((unsigned long)g_card_vir_addr[id], DBGTOOL_PAGE_ORDER); + g_card_vir_addr[id] = NULL; + g_card_phy_addr[id] = 0; +} + +static int free_knl_mem(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct card_node *card_info = hinic3_get_chip_node_by_lld(lld_dev); + int id, err; + + err = sscanf(card_info->chip_name, HINIC3_CHIP_NAME "%d", &id); + if (err <= 0) { + pr_err("Failed to get card id\n"); + return err; + } + + if (id >= MAX_CARD_NUM || id < 0) { + pr_err("chip id %d exceed limit[0-%d]\n", id, MAX_CARD_NUM - 1); + return -EINVAL; + } + + dbgtool_knl_free_mem(id); + + return 0; +} + +static int card_info_param_valid(const char *dev_name, const void *buf_out, + u32 buf_out_size, int *id) +{ + int err; + + if (!buf_out || buf_out_size != sizeof(struct hinic3_card_func_info)) { + pr_err("Invalid parameter: out_buf_size %u, expect %lu\n", + buf_out_size, sizeof(struct hinic3_card_func_info)); + return -EINVAL; + } + + err = memcmp(dev_name, HINIC3_CHIP_NAME, strlen(HINIC3_CHIP_NAME)); + if (err) { + pr_err("Invalid chip name %s\n", dev_name); + return err; + } + + err = sscanf(dev_name, HINIC3_CHIP_NAME "%d", id); + if (err <= 0) { + pr_err("Failed to get card id\n"); + return err; + } + + if (*id >= MAX_CARD_NUM || *id < 0) { + pr_err("chip id %d exceed limit[0-%d]\n", + *id, MAX_CARD_NUM - 1); + return -EINVAL; + } + + return 0; +} + +static int get_card_func_info(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct hinic3_card_func_info *card_func_info = buf_out; + struct card_node *card_info = hinic3_get_chip_node_by_lld(lld_dev); + int err, id = 0; + + err = card_info_param_valid(card_info->chip_name, buf_out, *out_size, &id); + if (err) + return err; + + hinic3_get_card_func_info_by_card_name(card_info->chip_name, card_func_info); + + if (!card_func_info->num_pf) { + pr_err("None function found for %s\n", card_info->chip_name); + return -EFAULT; + } + + err = get_card_usr_api_chain_mem(id); + if (err) { + pr_err("Faile to get api chain memory for userspace %s\n", + card_info->chip_name); + return -EFAULT; + } + + card_func_info->usr_api_phy_addr = g_card_phy_addr[id]; + + return 0; +} + +static int get_pf_cap_info(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct service_cap *func_cap = NULL; + struct hinic3_hwdev *hwdev = NULL; + struct card_node *card_info = hinic3_get_chip_node_by_lld(lld_dev); + struct svc_cap_info *svc_cap_info_in = (struct svc_cap_info *)buf_in; + struct svc_cap_info *svc_cap_info_out = (struct svc_cap_info *)buf_out; + + if (*out_size != sizeof(struct svc_cap_info) || in_size != sizeof(struct svc_cap_info) || + !buf_in || !buf_out) { + pr_err("Invalid parameter: out_buf_size %u, in_size: %u, expect %lu\n", + *out_size, in_size, sizeof(struct svc_cap_info)); + return -EINVAL; + } + + if (svc_cap_info_in->func_idx >= MAX_FUNCTION_NUM) { + pr_err("func_idx is illegal. func_idx: %u, max_num: %u\n", + svc_cap_info_in->func_idx, MAX_FUNCTION_NUM); + return -EINVAL; + } + + lld_hold(); + hwdev = (struct hinic3_hwdev *)(card_info->func_handle_array)[svc_cap_info_in->func_idx]; + if (!hwdev) { + lld_put(); + return -EINVAL; + } + + func_cap = &hwdev->cfg_mgmt->svc_cap; + memcpy(&svc_cap_info_out->cap, func_cap, sizeof(struct service_cap)); + lld_put(); + + return 0; +} + +static int get_hw_drv_version(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct drv_version_info *ver_info = buf_out; + int err; + + if (!buf_out) { + pr_err("Buf_out is NULL.\n"); + return -EINVAL; + } + + if (*out_size != sizeof(*ver_info)) { + pr_err("Unexpect out buf size from user :%u, expect: %lu\n", + *out_size, sizeof(*ver_info)); + return -EINVAL; + } + + err = snprintf(ver_info->ver, sizeof(ver_info->ver), "%s %s", + HINIC3_DRV_VERSION, __TIME_STR__); + if (err < 0) + return -EINVAL; + + return 0; +} + +static int get_pf_id(struct hinic3_lld_dev *lld_dev, const void *buf_in, u32 in_size, + void *buf_out, u32 *out_size) +{ + struct hinic3_pf_info *pf_info = NULL; + struct card_node *chip_node = hinic3_get_chip_node_by_lld(lld_dev); + u32 port_id; + int err; + + if (!chip_node) + return -ENODEV; + + if (!buf_out || (*out_size != sizeof(*pf_info)) || !buf_in || in_size != sizeof(u32)) { + pr_err("Unexpect out buf size from user :%u, expect: %lu, in size:%u\n", + *out_size, sizeof(*pf_info), in_size); + return -EINVAL; + } + + port_id = *((u32 *)buf_in); + pf_info = (struct hinic3_pf_info *)buf_out; + err = hinic3_get_pf_id(chip_node, port_id, &pf_info->pf_id, &pf_info->isvalid); + if (err) + return err; + + *out_size = sizeof(*pf_info); + + return 0; +} + +struct hw_drv_module_handle hw_driv_module_cmd_handle[] = { + {FUNC_TYPE, get_func_type}, + {GET_FUNC_IDX, get_func_id}, + {GET_HW_STATS, (hw_driv_module)get_hw_driver_stats}, + {CLEAR_HW_STATS, clear_hw_driver_stats}, + {GET_SELF_TEST_RES, get_self_test_result}, + {GET_CHIP_FAULT_STATS, (hw_driv_module)get_chip_faults_stats}, + {GET_SINGLE_CARD_INFO, (hw_driv_module)get_single_card_info}, + {IS_DRV_IN_VM, is_driver_in_vm}, + {GET_CHIP_ID, get_all_chip_id_cmd}, + {GET_PF_DEV_INFO, get_pf_dev_info}, + {CMD_FREE_MEM, free_knl_mem}, + {GET_CHIP_INFO, get_card_func_info}, + {GET_FUNC_CAP, get_pf_cap_info}, + {GET_DRV_VERSION, get_hw_drv_version}, + {GET_PF_ID, get_pf_id}, +}; + +static int alloc_tmp_buf(void *hwdev, struct msg_module *nt_msg, u32 in_size, + void **buf_in, u32 out_size, void **buf_out) +{ + int ret; + + ret = alloc_buff_in(hwdev, nt_msg, in_size, buf_in); + if (ret) { + pr_err("Alloc tool cmd buff in failed\n"); + return ret; + } + + ret = alloc_buff_out(hwdev, nt_msg, out_size, buf_out); + if (ret) { + pr_err("Alloc tool cmd buff out failed\n"); + goto out_free_buf_in; + } + + return 0; + +out_free_buf_in: + free_buff_in(hwdev, nt_msg, *buf_in); + + return ret; +} + +static void free_tmp_buf(void *hwdev, struct msg_module *nt_msg, + void *buf_in, void *buf_out) +{ + free_buff_out(hwdev, nt_msg, buf_out); + free_buff_in(hwdev, nt_msg, buf_in); +} + +static int send_to_hw_driver(struct hinic3_lld_dev *lld_dev, struct msg_module *nt_msg, + const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + int index, num_cmds = (int)(sizeof(hw_driv_module_cmd_handle) / + sizeof(hw_driv_module_cmd_handle[0])); + enum driver_cmd_type cmd_type = + (enum driver_cmd_type)(nt_msg->msg_formate); + int err = 0; + + for (index = 0; index < num_cmds; index++) { + if (cmd_type == + hw_driv_module_cmd_handle[index].driv_cmd_name) { + err = hw_driv_module_cmd_handle[index].driv_func + (lld_dev, buf_in, in_size, buf_out, out_size); + break; + } + } + + if (index == num_cmds) { + pr_err("Can't find callback for %d\n", cmd_type); + return -EINVAL; + } + + return err; +} + +static int send_to_service_driver(struct hinic3_lld_dev *lld_dev, struct msg_module *nt_msg, + const void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + const char **service_name = NULL; + enum hinic3_service_type type; + void *uld_dev = NULL; + int ret = -EINVAL; + + service_name = hinic3_get_uld_names(); + type = nt_msg->module - SEND_TO_SRV_DRV_BASE; + if (type >= SERVICE_T_MAX) { + pr_err("Ioctl input module id: %u is incorrectly\n", nt_msg->module); + return -EINVAL; + } + + uld_dev = hinic3_get_uld_dev(lld_dev, type); + if (!uld_dev) { + if (nt_msg->msg_formate == GET_DRV_VERSION) + return 0; + + pr_err("Can not get the uld dev correctly: %s driver may be not register\n", + service_name[type]); + return -EINVAL; + } + + if (g_uld_info[type].ioctl) + ret = g_uld_info[type].ioctl(uld_dev, nt_msg->msg_formate, + buf_in, in_size, buf_out, out_size); + uld_dev_put(lld_dev, type); + + return ret; +} + +static int nictool_exec_cmd(struct hinic3_lld_dev *lld_dev, struct msg_module *nt_msg, + void *buf_in, u32 in_size, void *buf_out, u32 *out_size) +{ + int ret = 0; + + switch (nt_msg->module) { + case SEND_TO_HW_DRIVER: + ret = send_to_hw_driver(lld_dev, nt_msg, buf_in, in_size, buf_out, out_size); + break; + case SEND_TO_MPU: + ret = send_to_mpu(hinic3_get_sdk_hwdev_by_lld(lld_dev), + nt_msg, buf_in, in_size, buf_out, out_size); + break; + case SEND_TO_SM: + ret = send_to_sm(hinic3_get_sdk_hwdev_by_lld(lld_dev), + nt_msg, buf_in, in_size, buf_out, out_size); + break; + case SEND_TO_NPU: + ret = send_to_npu(hinic3_get_sdk_hwdev_by_lld(lld_dev), + nt_msg, buf_in, in_size, buf_out, out_size); + break; + default: + ret = send_to_service_driver(lld_dev, nt_msg, buf_in, in_size, buf_out, out_size); + break; + } + + return ret; +} + +static int cmd_parameter_valid(struct msg_module *nt_msg, unsigned long arg, + u32 *out_size_expect, u32 *in_size) +{ + if (copy_from_user(nt_msg, (void *)arg, sizeof(*nt_msg))) { + pr_err("Copy information from user failed\n"); + return -EFAULT; + } + + *out_size_expect = nt_msg->buf_out_size; + *in_size = nt_msg->buf_in_size; + if (*out_size_expect > HINIC3_MAX_BUF_SIZE || + *in_size > HINIC3_MAX_BUF_SIZE) { + pr_err("Invalid in size: %u or out size: %u\n", + *in_size, *out_size_expect); + return -EFAULT; + } + + nt_msg->device_name[IFNAMSIZ - 1] = '\0'; + + return 0; +} + +static struct hinic3_lld_dev *get_lld_dev_by_nt_msg(struct msg_module *nt_msg) +{ + struct hinic3_lld_dev *lld_dev = NULL; + + if (nt_msg->module == SEND_TO_NIC_DRIVER && (nt_msg->msg_formate == GET_XSFP_INFO || + nt_msg->msg_formate == GET_XSFP_PRESENT)) { + lld_dev = hinic3_get_lld_dev_by_chip_and_port(nt_msg->device_name, nt_msg->port_id); + } else if (nt_msg->module == SEND_TO_CUSTOM_DRIVER && nt_msg->msg_formate == CMD_CUSTOM_BOND_GET_CHIP_NAME) { + lld_dev = hinic3_get_lld_dev_by_dev_name(nt_msg->device_name, SERVICE_T_MAX); + } else if (nt_msg->module == SEND_TO_VBS_DRIVER) { + lld_dev = hinic3_get_lld_dev_by_chip_name(nt_msg->device_name); + } else if (nt_msg->module >= SEND_TO_SRV_DRV_BASE && nt_msg->module < SEND_TO_DRIVER_MAX + && nt_msg->msg_formate != GET_DRV_VERSION) { + lld_dev = hinic3_get_lld_dev_by_dev_name(nt_msg->device_name, + nt_msg->module - SEND_TO_SRV_DRV_BASE); + } else { + lld_dev = hinic3_get_lld_dev_by_chip_name(nt_msg->device_name); + if (!lld_dev) + lld_dev = hinic3_get_lld_dev_by_dev_name(nt_msg->device_name, SERVICE_T_MAX); + } + + return lld_dev; +} + +static long hinicadm_k_unlocked_ioctl(struct file *pfile, unsigned long arg) +{ + struct hinic3_lld_dev *lld_dev = NULL; + struct msg_module nt_msg; + void *buf_out = NULL; + void *buf_in = NULL; + u32 out_size_expect = 0; + u32 out_size = 0; + u32 in_size = 0; + int ret = 0; + + memset(&nt_msg, 0, sizeof(nt_msg)); + if (cmd_parameter_valid(&nt_msg, arg, &out_size_expect, &in_size)) + return -EFAULT; + + lld_dev = get_lld_dev_by_nt_msg(&nt_msg); + if (!lld_dev) { + if (nt_msg.msg_formate != DEV_NAME_TEST) + pr_err("Can not find device %s for module %u\n", + nt_msg.device_name, nt_msg.module); + + return -ENODEV; + } + + if (nt_msg.msg_formate == DEV_NAME_TEST) { + lld_dev_put(lld_dev); + return 0; + } + + ret = alloc_tmp_buf(hinic3_get_sdk_hwdev_by_lld(lld_dev), &nt_msg, + in_size, &buf_in, out_size_expect, &buf_out); + if (ret) { + pr_err("Alloc tmp buff failed\n"); + goto out_free_lock; + } + + out_size = out_size_expect; + + ret = nictool_exec_cmd(lld_dev, &nt_msg, buf_in, in_size, buf_out, &out_size); + if (ret) { + pr_err("nictool_exec_cmd failed, module: %u, ret: %d.\n", nt_msg.module, ret); + goto out_free_buf; + } + + if (out_size > out_size_expect) { + ret = -EFAULT; + pr_err("Out size is greater than expected out size from user: %u, out size: %u\n", + out_size_expect, out_size); + goto out_free_buf; + } + + ret = copy_buf_out_to_user(&nt_msg, out_size, buf_out); + if (ret) + pr_err("Copy information to user failed\n"); + +out_free_buf: + free_tmp_buf(hinic3_get_sdk_hwdev_by_lld(lld_dev), &nt_msg, buf_in, buf_out); + +out_free_lock: + lld_dev_put(lld_dev); + return (long)ret; +} + +/** + * dbgtool_knl_ffm_info_rd - Read ffm information + * @para: the dbgtool parameter + * @dbgtool_info: the dbgtool info + **/ +static long dbgtool_knl_ffm_info_rd(struct dbgtool_param *para, + struct dbgtool_k_glb_info *dbgtool_info) +{ + if (!para->param.ffm_rd || !dbgtool_info->ffm) + return -EINVAL; + + /* Copy the ffm_info to user mode */ + if (copy_to_user(para->param.ffm_rd, dbgtool_info->ffm, + (unsigned int)sizeof(struct ffm_record_info))) { + pr_err("Copy ffm_info to user fail\n"); + return -EFAULT; + } + + return 0; +} + +static long dbgtool_k_unlocked_ioctl(struct file *pfile, + unsigned int real_cmd, + unsigned long arg) +{ + long ret; + struct dbgtool_param param; + struct dbgtool_k_glb_info *dbgtool_info = NULL; + struct card_node *card_info = NULL; + int i; + + memset(¶m, 0, sizeof(param)); + + if (copy_from_user(¶m, (void *)arg, sizeof(param))) { + pr_err("Copy param from user fail\n"); + return -EFAULT; + } + + lld_hold(); + for (i = 0; i < MAX_CARD_NUM; i++) { + card_info = (struct card_node *)g_card_node_array[i]; + if (!card_info) + continue; + if (memcmp(param.chip_name, card_info->chip_name, strlen(card_info->chip_name) + 1) == 0) + break; + } + + if (i == MAX_CARD_NUM || !card_info) { + lld_put(); + pr_err("Can't find this card.\n"); + return -EFAULT; + } + + card_id = i; + dbgtool_info = (struct dbgtool_k_glb_info *)card_info->dbgtool_info; + + down(&dbgtool_info->dbgtool_sem); + + switch (real_cmd) { + case DBGTOOL_CMD_FFM_RD: + ret = dbgtool_knl_ffm_info_rd(¶m, dbgtool_info); + break; + case DBGTOOL_CMD_MSG_2_UP: + pr_err("Not suppose to use this cmd(0x%x).\n", real_cmd); + ret = 0; + break; + default: + pr_err("Dbgtool cmd(0x%x) not support now\n", real_cmd); + ret = -EFAULT; + break; + } + + up(&dbgtool_info->dbgtool_sem); + + lld_put(); + + return ret; +} + +static int nictool_k_release(struct inode *pnode, struct file *pfile) +{ + return 0; +} + +static int nictool_k_open(struct inode *pnode, struct file *pfile) +{ + return 0; +} + +static ssize_t nictool_k_read(struct file *pfile, char __user *ubuf, + size_t size, loff_t *ppos) +{ + return 0; +} + +static ssize_t nictool_k_write(struct file *pfile, const char __user *ubuf, + size_t size, loff_t *ppos) +{ + return 0; +} + +static long nictool_k_unlocked_ioctl(struct file *pfile, + unsigned int cmd, unsigned long arg) +{ + unsigned int real_cmd; + + real_cmd = _IOC_NR(cmd); + + return (real_cmd == NICTOOL_CMD_TYPE) ? + hinicadm_k_unlocked_ioctl(pfile, arg) : + dbgtool_k_unlocked_ioctl(pfile, real_cmd, arg); +} + +static int hinic3_mem_mmap(struct file *filp, struct vm_area_struct *vma) +{ + pgprot_t vm_page_prot; + unsigned long vmsize = vma->vm_end - vma->vm_start; + phys_addr_t offset = (phys_addr_t)vma->vm_pgoff << PAGE_SHIFT; + phys_addr_t phy_addr; + int err = 0; + + if (vmsize > (PAGE_SIZE * (1 << DBGTOOL_PAGE_ORDER))) { + pr_err("Map size = %lu is bigger than alloc\n", vmsize); + return -EAGAIN; + } + + /* old version of tool set vma->vm_pgoff to 0 */ + phy_addr = offset ? offset : g_card_phy_addr[card_id]; + /* check phy_addr valid */ + if (phy_addr != g_card_phy_addr[card_id]) { + err = hinic3_bar_mmap_param_valid(phy_addr, vmsize); + if (err != 0) { + pr_err("mmap param invalid, err: %d\n", err); + return err; + } + } + + /* Disable cache and write buffer in the mapping area */ + vm_page_prot = pgprot_noncached(vma->vm_page_prot); + vma->vm_page_prot = vm_page_prot; + if (remap_pfn_range(vma, vma->vm_start, (phy_addr >> PAGE_SHIFT), + vmsize, vma->vm_page_prot)) { + pr_err("Remap pfn range failed.\n"); + return -EAGAIN; + } + + return 0; +} + +static const struct file_operations fifo_operations = { + .owner = THIS_MODULE, + .release = nictool_k_release, + .open = nictool_k_open, + .read = nictool_k_read, + .write = nictool_k_write, + .unlocked_ioctl = nictool_k_unlocked_ioctl, + .mmap = hinic3_mem_mmap, +}; + +static void free_dbgtool_info(void *hwdev, struct card_node *chip_info) +{ + struct dbgtool_k_glb_info *dbgtool_info = NULL; + + if (hinic3_func_type(hwdev) != TYPE_VF) + chip_info->func_handle_array[hinic3_global_func_id(hwdev)] = NULL; + + if (--chip_info->func_num) + return; + + if (chip_info->chip_id >= 0 && chip_info->chip_id < MAX_CARD_NUM) + g_card_node_array[chip_info->chip_id] = NULL; + + dbgtool_info = chip_info->dbgtool_info; + /* FFM deinit */ + if (dbgtool_info && dbgtool_info->ffm) { + kfree(dbgtool_info->ffm); + dbgtool_info->ffm = NULL; + } + + if (dbgtool_info) + kfree(dbgtool_info); + + chip_info->dbgtool_info = NULL; + + if (chip_info->chip_id >= 0 && chip_info->chip_id < MAX_CARD_NUM) + dbgtool_knl_free_mem(chip_info->chip_id); +} + +static int alloc_dbgtool_info(void *hwdev, struct card_node *chip_info) +{ + struct dbgtool_k_glb_info *dbgtool_info = NULL; + int err, id = 0; + + if (hinic3_func_type(hwdev) != TYPE_VF) + chip_info->func_handle_array[hinic3_global_func_id(hwdev)] = hwdev; + + if (chip_info->func_num++) + return 0; + + dbgtool_info = (struct dbgtool_k_glb_info *) + kzalloc(sizeof(struct dbgtool_k_glb_info), GFP_KERNEL); + if (!dbgtool_info) { + pr_err("Failed to allocate dbgtool_info\n"); + goto dbgtool_info_fail; + } + + chip_info->dbgtool_info = dbgtool_info; + + /* FFM init */ + dbgtool_info->ffm = (struct ffm_record_info *) + kzalloc(sizeof(struct ffm_record_info), GFP_KERNEL); + if (!dbgtool_info->ffm) { + pr_err("Failed to allocate cell contexts for a chain\n"); + goto dbgtool_info_ffm_fail; + } + + sema_init(&dbgtool_info->dbgtool_sem, 1); + + err = sscanf(chip_info->chip_name, HINIC3_CHIP_NAME "%d", &id); + if (err <= 0) { + pr_err("Failed to get card id\n"); + goto sscanf_chdev_fail; + } + + g_card_node_array[id] = chip_info; + + return 0; + +sscanf_chdev_fail: + kfree(dbgtool_info->ffm); + +dbgtool_info_ffm_fail: + kfree(dbgtool_info); + chip_info->dbgtool_info = NULL; + +dbgtool_info_fail: + if (hinic3_func_type(hwdev) != TYPE_VF) + chip_info->func_handle_array[hinic3_global_func_id(hwdev)] = NULL; + chip_info->func_num--; + return -ENOMEM; +} + +/** + * nictool_k_init - initialize the hw interface + **/ +/* temp for dbgtool_info */ + +int nictool_k_init(void *hwdev, void *chip_node) +{ + struct card_node *chip_info = (struct card_node *)chip_node; + struct device *pdevice = NULL; + int err; + + err = alloc_dbgtool_info(hwdev, chip_info); + if (err) + return err; + + if (g_nictool_ref_cnt++) { + /* already initialized */ + return 0; + } + + err = alloc_chrdev_region(&g_dev_id, 0, 1, HIADM3_DEV_NAME); + if (err) { + pr_err("Register nictool_dev failed(0x%x)\n", err); + goto alloc_chdev_fail; + } + + /* Create equipment */ + g_nictool_class = class_create(THIS_MODULE, HIADM3_DEV_CLASS); + if (IS_ERR(g_nictool_class)) { + pr_err("Create nictool_class fail\n"); + err = -EFAULT; + goto class_create_err; + } + + /* Initializing the character device */ + cdev_init(&g_nictool_cdev, &fifo_operations); + + /* Add devices to the operating system */ + err = cdev_add(&g_nictool_cdev, g_dev_id, 1); + if (err < 0) { + pr_err("Add nictool_dev to operating system fail(0x%x)\n", err); + goto cdev_add_err; + } + + /* Export device information to user space + * (/sys/class/class name/device name) + */ + pdevice = device_create(g_nictool_class, NULL, + g_dev_id, NULL, HIADM3_DEV_NAME); + if (IS_ERR(pdevice)) { + pr_err("Export nictool device information to user space fail\n"); + err = -EFAULT; + goto device_create_err; + } + + pr_info("Register nictool_dev to system succeed\n"); + + return 0; + +device_create_err: + cdev_del(&g_nictool_cdev); + +cdev_add_err: + class_destroy(g_nictool_class); + +class_create_err: + g_nictool_class = NULL; + unregister_chrdev_region(g_dev_id, 1); + +alloc_chdev_fail: + g_nictool_ref_cnt--; + free_dbgtool_info(hwdev, chip_info); + + return err; +} + +void nictool_k_uninit(void *hwdev, void *chip_node) +{ + struct card_node *chip_info = (struct card_node *)chip_node; + + free_dbgtool_info(hwdev, chip_info); + + if (!g_nictool_ref_cnt) + return; + + if (--g_nictool_ref_cnt) + return; + + if (IS_ERR(g_nictool_class)) { + pr_err("Nictool class is NULL.\n"); + return; + } + + device_destroy(g_nictool_class, g_dev_id); + cdev_del(&g_nictool_cdev); + class_destroy(g_nictool_class); + g_nictool_class = NULL; + + unregister_chrdev_region(g_dev_id, 1); + + pr_info("Unregister nictool_dev succeed\n"); +} + diff --git a/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.h b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.h new file mode 100644 index 000000000..f368133e3 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/hinic3_nictool.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2021 Huawei Technologies Co., Ltd */ + +#ifndef HINIC3_NICTOOL_H +#define HINIC3_NICTOOL_H + +#include "hinic3_mt.h" +#include "hinic3_crm.h" + +#ifndef MAX_SIZE +#define MAX_SIZE (16) +#endif + +#define DBGTOOL_PAGE_ORDER (10) + +#define MAX_CARD_NUM (64) + +int nictool_k_init(void *hwdev, void *chip_node); +void nictool_k_uninit(void *hwdev, void *chip_node); + +void hinic3_get_all_chip_id(void *id_info); + +void hinic3_get_card_func_info_by_card_name + (const char *chip_name, struct hinic3_card_func_info *card_func); + +void hinic3_get_card_info(const void *hwdev, void *bufin); + +bool hinic3_is_in_host(void); + +int hinic3_get_pf_id(struct card_node *chip_node, u32 port_id, u32 *pf_id, u32 *isvalid); + +extern struct hinic3_uld_info g_uld_info[SERVICE_T_MAX]; + +#endif + diff --git a/drivers/infiniband/hw/hiroce3/host/mt/readme.txt b/drivers/infiniband/hw/hiroce3/host/mt/readme.txt new file mode 100644 index 000000000..08ab9134c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/mt/readme.txt @@ -0,0 +1 @@ +本目录是诊断维护代码目录 \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/host/vram/vram_common.c b/drivers/infiniband/hw/hiroce3/host/vram/vram_common.c new file mode 100644 index 000000000..4a12a7c74 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/host/vram/vram_common.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved. + * Description: Header File, vram common + * Create: 2023/7/19 + */ +#include <linux/kallsyms.h> +#include <linux/errno.h> +#include <linux/version.h> + +#include "ossl_knl.h" +#include "vram_common.h" + +static int g_use_vram = 0; +static int g_in_kexec = 0; + +static register_nvwa_notifier_t _register_nvwa_notifier = NULL; +static unregister_nvwa_notifier_t _unregister_nvwa_notifier = NULL; +static register_euleros_reboot_notifier_t _register_euleros_reboot_notifier = NULL; +static unregister_euleros_reboot_notifier_t _unregister_euleros_reboot_notifier = NULL; +static vram_kalloc_t _vram_kalloc = NULL; +static vram_kfree_t _vram_kfree = NULL; +static vram_get_gfp_vram _vram_get_gfp_vram = NULL; + +int hi_register_nvwa_notifier(int hook, struct notifier_block *nb) +{ + if (_register_nvwa_notifier) { + return _register_nvwa_notifier(hook, nb); + } + + return -EINVAL; +} +EXPORT_SYMBOL(hi_register_nvwa_notifier); + +int hi_unregister_nvwa_notifier(int hook, struct notifier_block *nb) +{ + if (_unregister_nvwa_notifier) { + return _unregister_nvwa_notifier(hook, nb); + } + + return -EINVAL; +} +EXPORT_SYMBOL(hi_unregister_nvwa_notifier); + +int hi_register_euleros_reboot_notifier(struct notifier_block *nb) +{ + if (_register_euleros_reboot_notifier) + return _register_euleros_reboot_notifier(nb); + + return -EINVAL; +} +EXPORT_SYMBOL(hi_register_euleros_reboot_notifier); + +int hi_unregister_euleros_reboot_notifier(struct notifier_block *nb) +{ + if (_unregister_euleros_reboot_notifier) + return _unregister_euleros_reboot_notifier(nb); + + return -EINVAL; +} +EXPORT_SYMBOL(hi_unregister_euleros_reboot_notifier); + +void __iomem *hi_vram_kalloc(char *name, u64 size) +{ + if (_vram_kalloc) { + return _vram_kalloc(name, size); + } + + return NULL; +} +EXPORT_SYMBOL(hi_vram_kalloc); + +void hi_vram_kfree(void __iomem *vaddr, char *name, u64 size) +{ + if (_vram_kfree && vaddr) { + _vram_kfree(vaddr, name, size); + } + + return; +} +EXPORT_SYMBOL(hi_vram_kfree); + +gfp_t hi_vram_get_gfp_vram(void) +{ + if (_vram_get_gfp_vram) { + return _vram_get_gfp_vram(); + } + return 0; +} +EXPORT_SYMBOL(hi_vram_get_gfp_vram); + +void lookup_vram_related_symbols(void) +{ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) + _register_nvwa_notifier = (register_nvwa_notifier_t) + kallsyms_lookup_name("register_nvwa_notifier"); + + _unregister_nvwa_notifier = (unregister_nvwa_notifier_t) + kallsyms_lookup_name("unregister_nvwa_notifier"); + + _register_euleros_reboot_notifier = (register_euleros_reboot_notifier_t) + kallsyms_lookup_name("register_euleros_reboot_notifier"); + + _unregister_euleros_reboot_notifier = (unregister_euleros_reboot_notifier_t) + kallsyms_lookup_name("unregister_euleros_reboot_notifier"); + + _vram_kalloc = (vram_kalloc_t) + kallsyms_lookup_name("vram_kalloc"); + + _vram_kfree = (vram_kfree_t) + kallsyms_lookup_name("vram_kfree"); + + _vram_get_gfp_vram = (vram_get_gfp_vram) + kallsyms_lookup_name("vram_get_vram_gfp_t"); +#else +// openEuler: the symbol table cannot be scanned in kernel versions later than 5.10. +#if (!defined(HIUDK_OPENEULER)) + _register_nvwa_notifier = (register_nvwa_notifier_t) + kallsyms_lookup_name_wrap("register_nvwa_notifier"); + + _unregister_nvwa_notifier = (unregister_nvwa_notifier_t) + kallsyms_lookup_name_wrap("unregister_nvwa_notifier"); + + _register_euleros_reboot_notifier = (register_euleros_reboot_notifier_t) + kallsyms_lookup_name_wrap("register_euleros_reboot_notifier"); + + _unregister_euleros_reboot_notifier = (unregister_euleros_reboot_notifier_t) + kallsyms_lookup_name_wrap("unregister_euleros_reboot_notifier"); + + _vram_kalloc = (vram_kalloc_t) + kallsyms_lookup_name_wrap("vram_kalloc"); + + _vram_kfree = (vram_kfree_t) + kallsyms_lookup_name_wrap("vram_kfree"); + + _vram_get_gfp_vram = (vram_get_gfp_vram) + kallsyms_lookup_name_wrap("vram_get_vram_gfp_t"); +#endif +#endif +} +EXPORT_SYMBOL(lookup_vram_related_symbols); + +int hi_set_kexec_status(int status) +{ + int *kexec_status_addr = NULL; + + kexec_status_addr = hi_vram_kalloc(KEXEC_SIGN, VRAM_BLOCK_SIZE_2M); + if (!kexec_status_addr) { + pr_err("set kexec status vram kalloc failed.\n"); + return -ENOMEM; + } + + *kexec_status_addr = status; + g_in_kexec = *kexec_status_addr; + + return 0; +} +EXPORT_SYMBOL(hi_set_kexec_status); + +int hi_get_kexec_status(void) +{ + int *kexec_status_addr = NULL; + + kexec_status_addr = hi_vram_kalloc(KEXEC_SIGN, VRAM_BLOCK_SIZE_2M); + if (!kexec_status_addr) { + pr_err("get kexec status vram kalloc failed.\n"); + return -ENOMEM; + } + + g_in_kexec = *kexec_status_addr; + hi_vram_kfree((void *)kexec_status_addr, KEXEC_SIGN, VRAM_BLOCK_SIZE_2M); + + return 0; +} +EXPORT_SYMBOL(hi_get_kexec_status); + +int get_use_vram_flag(void) +{ + return g_use_vram; +} +EXPORT_SYMBOL(get_use_vram_flag); + +void set_use_vram_flag(bool flag) +{ + g_use_vram = flag; +} +EXPORT_SYMBOL(set_use_vram_flag); + +int vram_get_kexec_flag(void) +{ + return g_in_kexec; +} +EXPORT_SYMBOL(vram_get_kexec_flag); diff --git a/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd.h b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd.h new file mode 100644 index 000000000..c146d17de --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd.h @@ -0,0 +1,38 @@ +/* ***************************************************************************** + + Copyright (C), 2023-2023, Huawei Tech. Co., Ltd. + + ****************************************************************************** + File Name : hisec_mpu_cmd.h + Version : Initial Draft + Created : 2023/8/21 + Last Modified : + Description : secure commands between Driver and MPU/uCode + Function List : +***************************************************************************** */ + +#ifndef HISEC_MPU_CMD_H +#define HISEC_MPU_CMD_H + +/** + * @brief Crypto driver to MPU Commands + * + */ +typedef enum hisec_mpu_cmd { + HISEC_MPU_CMD_SET_IPSEC_OFFLOAD_MODE = 2, /**< MPU crypt set IPsec offload mode + @see struct hisec_cmd_ipsec_offload_mode */ + HISEC_MPU_CMD_GET_CRYPTO_STATS = 3, /**< MPU crypt get crypto states + @see struct hisec_cmd_cryptodev_stats */ + HISEC_MPU_CMD_GET_IPSEC_SAD = 4, /**< MPU crypt get IPsec SAD + @see struct hisec_cmd_sml_table */ + HISEC_MPU_CMD_GET_IPSEC_SPD = 5, /**< MPU crypt get IPsec SPD + @see struct hisec_cmd_sml_table */ + HISEC_MPU_CMD_GET_IPSEC_ITEM_CNT = 6, /**< MPU crypt get IPsec item count + @see struct hisec_cmd_ipsec_item_cnt */ + HISEC_MPU_CMD_SET_IPSEC_CTRL_HOST = 7, /**< MPU cpypt set IPsec ctrl host + @see struct hisec_cmd_ipsec_ctrl_host */ + + HISEC_MPU_CMD_MAX = 255 +} hisec_mpu_cmd_type_e; + +#endif /* HISEC_MPU_CMD_H */ \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd_defs.h b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd_defs.h new file mode 100644 index 000000000..02ed077a2 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_mpu_cmd_defs.h @@ -0,0 +1,118 @@ +/* ***************************************************************************** + + Copyright (C), 2023-2023, Huawei Tech. Co., Ltd. + + ****************************************************************************** + File Name : hisec_mpu_cmd_defs.h + Version : Initial Draft + Created : 2023/8/21 + Last Modified : + Description : secure commands between Driver and MPU/uCode + Function List : +***************************************************************************** */ + +#ifndef HISEC_MPU_CMD_DEFS_H +#define HISEC_MPU_CMD_DEFS_H + +#include "mpu_cmd_base_defs.h" + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +#define IPSEC_SML_TBL_BUF_MAX 768 + +/** + * @brief HISec set ipsec offload mode command struct defination + * @see HISEC_MPU_CMD_SET_IPSEC_OFFLOAD_MODE + * + */ +struct hisec_cmd_ipsec_offload_mode { + struct comm_info_head msg_head; /**< Common information head */ + u16 func_id; /**< Function id */ + u8 offload_mode; /**< Offload mode, 0: disable 1: xfrm offload 2:ipsec full offload */ + u8 rsvd1[5]; +}; + +/** + * @brief HISec set ipsec ctrl host command struct defination + * @see HISEC_MPU_CMD_SET_IPSEC_CTRL_HOST + * + */ +struct hisec_cmd_ipsec_ctrl_host { + struct comm_info_head msg_head; /**< Common information head */ + u16 func_id; /**< IPSec Function ID */ + u16 host_id; /**< IPSec owner controller host */ + u8 rsvd1[4]; +}; + +/** + * @brief HISec crypto state description + * + */ +struct hisec_crypto_stats { + u64 cryrx_auth_err; /**< Crypto rx authority error */ + u64 cryrx_tfc_pad_err; /**< Crypto rx tfc pad error */ + u64 cryrx_other_err; /**< Crypto rx other error */ + u64 crytx_bd_err; /**< Crypto tx bd error */ + u64 crytx_len_err; /**< Crypto tx length error */ +}; + +/** + * @brief HISec get crypto device states command struct defination + * @see HISEC_MPU_CMD_GET_CRYPTO_STATS + * + */ +struct hisec_cmd_cryptodev_stats { + struct comm_info_head msg_head; /**< Common information head */ + struct hisec_crypto_stats stats; /**< Crypto device states */ +}; + +/** + * @brief HISec get ipsec item count command struct defination + * @see HISEC_MPU_CMD_GET_IPSEC_ITEM_CNT + * + */ +struct hisec_cmd_ipsec_item_cnt { + struct comm_info_head msg_head; /**< Common information head */ + u32 sp_item_cnt; /**< SP item count */ + u32 sa_item_cnt; /**< SA item count */ + u16 func_id; /**< Function id */ + u16 pad; +}; + +/** + * @brief IPSec SML table arguments, used by struct hisec_cmd_sml_table + * + */ +typedef union { + struct { + u32 tbl_index; + u32 cnt; + u32 total_cnt; + u32 pad; + } tbl_arg; + + u32 args[4]; +} ipsec_sml_tbl_args; + +/** + * @brief HISec get ipsec sad or spd command struct defination + * @see HISEC_MPU_CMD_GET_IPSEC_SAD + * @see HISEC_MPU_CMD_GET_IPSEC_SPD + * + */ +struct hisec_cmd_sml_table { + struct comm_info_head msg_head; /**< Common information head */ + u16 func_id; /**< Function ID */ + u16 pad; + u32 tbl_type; /**< SML table type, unused */ + ipsec_sml_tbl_args args; /**< SML table arguments */ + u8 tbl_buf[IPSEC_SML_TBL_BUF_MAX]; /**< SML table data buffer */ +}; + +#endif /** HISEC_MPU_CMD_DEFS_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd.h b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd.h new file mode 100644 index 000000000..6c229ae62 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd.h @@ -0,0 +1,30 @@ +/* ***************************************************************************** + + Copyright (C), 2023-2023, Huawei Tech. Co., Ltd. + + ****************************************************************************** + File Name : hisec_npu_cmd.h + Version : Initial Draft + Created : 2023/8/21 + Last Modified : + Description : secure commands between Driver and MPU/uCode + Function List : +***************************************************************************** */ + +#ifndef HISEC_NPU_CMD_H +#define HISEC_NPU_CMD_H + +/** Crypto driver to NPU Commands */ +typedef enum hisec_npu_cmd_type { + HISEC_NPU_CMD_SET_IPSEC_SA, /**< IPsec SA child context 256B @see struct tag_hisec_cmd_set_ipsec_sa */ + HISEC_NPU_CMD_SET_IPSEC_SP, /**< IPsec Secure Policy @see struct tag_hisec_cmd_set_ipsec_sp */ + HISEC_NPU_CMD_CALC_DH, /**< IPsec Calculate DH @see struct tag_hisec_cmd_calc_dh */ + HISEC_NPU_CMD_FLUSH_IPSEC_RES, /**< IPsec flush resource @see struct tag_hisec_cmd_flush_ipsec_res */ + HISEC_NPU_CMD_INIT_SCQC, /**< IPsec init scqc @see struct tag_hisec_cmd_init_scqc */ + HISEC_NPU_CMD_DEINIT_SCQC, /**< IPsec uninit scqc @see struct tag_hisec_cmd_deinit_scqc */ + HISEC_NPU_CMD_HW_RANDOM, /**< IPsec hardware random @see struct hisec_cmd_trng_module */ + + HISEC_NPU_CMD_MAX = 255 +} hisec_npu_cmd_type_e; + +#endif /* HISEC_NPU_CMD_H */ \ No newline at end of file diff --git a/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd_defs.h b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd_defs.h new file mode 100644 index 000000000..3f0826591 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/crypt/hisec_npu_cmd_defs.h @@ -0,0 +1,415 @@ +/* ***************************************************************************** + + Copyright (C), 2023-2023, Huawei Tech. Co., Ltd. + + ****************************************************************************** + File Name : hisec_npu_cmd_defs.h + Version : Initial Draft + Created : 2023/8/21 + Last Modified : + Description : secure commands between Driver and MPU/uCode + Function List : +***************************************************************************** */ + +#ifndef HISEC_NPU_CMD_DEFS_H +#define HISEC_NPU_CMD_DEFS_H + +#include "mpu_cmd_base_defs.h" + +#ifndef BIG_ENDIAN +#define BIG_ENDIAN 0x4321 +#endif + +#ifndef LITTLE_ENDIAN +#define LITTLE_ENDIAN 0x1234 +#endif + +#define RESP_DATA_LEN_MAX 32 + +/** + * @brief hisec command common header + * + */ +typedef struct tag_hisec_cmd_hdr { + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 rsvd0 : 16; + + /** Logical concurrency channel */ + u32 channel_id : 8; + + /** Command type, @see hisec_npu_cmd_type_e */ + u32 cmd_type : 8; +#else + /** Command type, @see hisec_npu_cmd_type_e */ + u32 cmd_type : 8; + + /** Logical concurrency channel */ + u32 channel_id : 8; + u32 rsvd0 : 16; +#endif + } bs; + u32 value; + } dw0; + + /** Command serial number */ + u32 cmd_sn; + u32 rsvd1[2]; +} hisec_cmd_hdr_s; + +/** + * @brief HiSec init scqc command struct defination + * @see HISEC_NPU_CMD_INIT_SCQC + * + */ +typedef struct tag_hisec_cmd_init_scqc { + hisec_cmd_hdr_s cmdhdr; + + u32 scqn; + u32 rsvd; + u32 scqc[10]; +} hisec_cmd_init_scqc_s; + +/** + * @brief Hisec deinit scqc command struct defination + * @see HISEC_NPU_CMD_DEINIT_SCQC + * + */ +typedef struct tag_hisec_cmd_deinit_scqc { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header */ + + u32 scqn; + u32 resvd[11]; +} hisec_cmd_deinit_scqc_s; + +/** + * @brief HISec flush ipsec resource struct defination + * @see HISEC_NPU_CMD_FLUSH_IPSEC_RES + * + */ +typedef struct tag_hisec_cmd_flush_ipsec_res { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header */ + + u16 func_id; + u16 rsvd0; + u32 flush_flag; + u32 rsvd1; +} hisec_cmd_flush_ipsec_res_s; + +/** + * @brief HISec SA encrypt information + * + */ +typedef struct tag_hisec_sa_enc_info { + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 proto : 8; /**< tcp/udp */ + u32 direction : 8; /**< out/in */ + u32 mode : 8; /**< 0 transport/ 1 tunnel */ + u32 flag : 8; /**< 1 -esn */ +#else + u32 flag : 8; + u32 mode : 8; + u32 direction : 8; + u32 proto : 8; +#endif + } bs; + u32 value; + } enc_dw0; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 replaywindow : 16; /**< 32-64 */ + u32 alg_type : 8; /**< 0- aead 1-enc 2-auth 3-enc & auth */ + u32 alg_standard : 8; /**< 0 - aes, 3 - SM4 */ +#else + u32 alg_standard : 8; + u32 alg_type : 8; + u32 replaywindow : 16; +#endif + } bs; + u32 value; + } enc_dw1; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 enc_type : 8; /**< hisec_crypto_alg_type */ + u32 auth_type : 8; /**< hisec_crypto_alg_type */ + u32 cipher_key_len : 16; /**< in bit */ +#else + u32 cipher_key_len : 16; + u32 auth_type : 8; + u32 enc_type : 8; +#endif + } bs; + u32 value; + } enc_dw2; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 auth_key_len : 16; /**< in bit */ + u32 auth_trunc_len : 16; /**< in bit */ +#else + u32 auth_trunc_len : 16; + u32 auth_key_len : 16; +#endif + } bs; + u32 value; + } enc_dw3; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 icv_mac_len : 16; /**< in bit */ + u32 rsvd1 : 16; +#else + u32 rsvd1 : 16; + u32 icv_mac_len : 16; + +#endif + } bs; + u32 value; + } enc_dw4; + + u32 salt; /**< 32bit */ + + u32 pad[2]; + + u32 cipher_key[8]; /**< 128bit 192bit 256bit */ + u32 auth_key[8]; /**< 256bit */ +} hisec_sa_enc_info_s; + +/** + * @brief HISec SA tuples + * + */ +typedef struct tag_hisec_sa_tuples { + u32 daddr[4]; /**< ipv4 in daddr[0] */ + u32 spi; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 ipsec_proto : 8; + u32 iptype : 8; /**< 0-ipv4 1-ipv6 */ + u32 rsvd : 16; +#else + u32 rsvd : 16; + u32 iptype : 8; + u32 ipsec_proto : 8; +#endif + } bs; + u32 value; + } tup_dw0; + + u32 pad[2]; +} hisec_sa_tuples_s; + +/** + * @brief IPsec SA msg 160B struct defination + * @see HISEC_NPU_CMD_SET_IPSEC_SA + * + */ +typedef struct tag_hisec_cmd_set_ipsec_sa { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header, 16B */ + + hisec_sa_tuples_s tuples; /**< 32B */ + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 opid : 8; /**< 0-add 1-del 2-update 3-flush */ + u32 rsvd0 : 24; +#else + u32 rsvd0 : 24; + u32 opid : 8; +#endif + } bs; + u32 value; + } sa_dw0; + + u32 scqn; /**< used for scqe sa aging update msg notify */ + + u32 pad[2]; + + hisec_sa_enc_info_s enc_info; +} hisec_cmd_set_ipsec_sa_s; + +/** + * @brief HISec SP tuples + * + */ +typedef struct tag_hisec_sp_tuples { + u32 saddr[4]; /**< ipv4 in saddr[0] */ + u32 daddr[4]; /**< ipv4 in daddr[0] */ + u32 sa_masklen; + u32 da_masklen; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 dport : 16; + u32 sport : 16; +#else + u32 sport : 16; + u32 dport : 16; +#endif + } bs; + u32 value; + } tup_dw0; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 dport_mask : 16; + u32 sport_mask : 16; +#else + u32 sport_mask : 16; + u32 dport_mask : 16; +#endif + } bs; + u32 value; + } tup_dw1; + + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 ulp_proto : 8; /**< tcp/udp */ + u32 iptype : 8; /**< 0-ipv4 1-ipv6 */ + u32 rsvd0 : 16; +#else + u16 rsvd0; + u8 iptype; + u8 ulp_proto; +#endif + } bs; + u32 value; + } tup_dw2; + + u32 pad[3]; +} hisec_sp_tuples_s; + +/** + * @brief HISec set ipsec SP command struct defination + * @see HISEC_NPU_CMD_SET_IPSEC_SP, IPsec SP msg 128B + * + */ +typedef struct tag_hisec_cmd_set_ipsec_sp { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header */ + hisec_sp_tuples_s tuples; + u32 spi; + union { + struct { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u32 ipsec_proto : 8; /**< 50-esp 51-ah */ + u32 opid : 8; /**< 0-add 1-del 2-update */ + u32 action : 8; /**< 0-bypass 1-encrypted */ + u32 rsvd0 : 8; +#else + u32 rsvd0 : 8; + u32 action : 8; + u32 opid : 8; + u32 ipsec_proto : 8; +#endif + } bs; + u32 value; + } sp_dw0; + + u32 pad[10]; +} hisec_cmd_set_ipsec_sp_s; + +/** + * @brief HISec DH parameters, used by hisec_cmd_calc_dh_s + * + */ +typedef struct tag_hisec_cmd_dh_param { +#if (BYTE_ORDER == LITTLE_ENDIAN) + u16 generator; + /** DH phase, 1:DH Phase1 2:DH Phase 2 */ + u8 dh_phase; + /** DH group id */ + u8 dh_groupid; +#else + /** DH group id */ + u8 dh_groupid; + /** DH phase, 1:DH Phase1 2:DH Phase 2 */ + u8 dh_phase; + u16 generator; +#endif + +#if (BYTE_ORDER == LITTLE_ENDIAN) + u16 privkey_len; + u16 modp_len; +#else + u16 modp_len; + u16 privkey_len; +#endif + +#if (BYTE_ORDER == LITTLE_ENDIAN) + u16 rsvd0; + u16 pubkey_len; +#else + u16 pubkey_len; + u16 rsvd0; +#endif + + u32 rsvd1[13]; + + u32 modprime[128]; /**< public prime number */ + u32 private_key[128]; /**< private Xa */ + u32 public_key[128]; /**< public Yb */ +} hisec_cmd_dh_param_s; + +/** + * @brief HISec calculate DH command struct defination + * @see HISEC_NPU_CMD_CALC_DH + * + */ +typedef struct tag_hisec_cmd_calc_dh { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header */ + + /** writeback result PhyAddr */ + u32 buf_len; + u32 buf_gpah; + u32 buf_gpal; + + /** writeback result LogicalVirtualAddr */ + u32 buf_vah; + u32 buf_val; + + /** detect memory tramp */ + u32 magic_h; + u32 magic_l; + + u32 scqn; + u32 rsvd[4]; + + hisec_cmd_dh_param_s dh_param; +} hisec_cmd_calc_dh_s; + +/** + * @brief HISec hardware random calculation response data, used by hisec_cmd_trng_module_s + * + */ +typedef struct trng_data_resp { + u32 status; + u32 data_out[RESP_DATA_LEN_MAX]; +} trng_data_resp_s; + +/** + * @brief HISec hardware random command struct defination + * @see HISEC_NPU_CMD_HW_RANDOM + * + */ +typedef struct hisec_cmd_trng_module { + hisec_cmd_hdr_s cmdhdr; /**< HISec command header */ + u32 length; + trng_data_resp_s resp; +} hisec_cmd_trng_module_s; + +#endif /* HISEC_NPU_CMD_DEFS_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hinic3_hmm.h b/drivers/infiniband/hw/hiroce3/include/hinic3_hmm.h new file mode 100644 index 000000000..5a8f76e2d --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hinic3_hmm.h @@ -0,0 +1,83 @@ +/* *************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2018-2022. All rights reserved. + ******************************************************************************/ + +#ifndef HINIC_HMM_H__ +#define HINIC_HMM_H__ + +/* has no mpt entry */ +#define HMM_MPT_EN_SW 1 /* has mpt, state INVALID */ +#define HMM_MPT_EN_HW 2 /* has mpt, state FREE or VALID */ +#define HMM_MPT_DISABLED 0 /* has no mpt entry */ +#define HMM_MPT_FIX_BUG_LKEY 0 + +#include "hinic3_cqm.h" +#include "hinic3_hwdev.h" +#include "hmm_comp.h" +#include "hmm_mr.h" + +/* **************************************************************************** + Prototype : hmm_reg_user_mr_update + Description : MR注册生成和更新MPT和MTT表 + Input : struct hinic3_hwdev *hwdev + hmm_mr *mr MR结构，包含已经完成用户态内存的物理地址获取umem + u32 pdn PD号，如果不支持的pd的特性直接填0. + u64 length 需要注册的用户态地址长度 + u64 virt_addr 需要注册的IOV虚拟地址首地址 + int hmm_acess填入enum rdma_ib_access的值 + u32 service_type enum hinic3_service_type的值 + Output : None +**************************************************************************** */ +int hmm_reg_user_mr_update(struct hinic3_hwdev *hwdev, struct hmm_mr *mr, u32 pdn, u64 length, + u64 virt_addr, int access, u32 service_type, u16 channel); + + +/* **************************************************************************** + Prototype : hmm_reg_user_mr_update + Description : MR去注册删除MPT和MTT表 + Input : struct hinic3_hwdev *hwdev + rdma_mr *mr MR结构 + u32 service_type enum hinic3_service_type的值 + Output : None +**************************************************************************** */ +int hmm_dereg_mr_update(struct hinic3_hwdev *hwdev, struct rdma_mr *mr, u32 service_type, u16 channel); + +#ifndef ROCE_SERVICE +/* **************************************************************************** + Prototype : hmm_reg_user_mr + Description : register MR for user + Input : struct hinic3_hwdev *hwdev + u32 pdn PD�� + u64 start ע��memory����ʼ��ַ + u64 length ע���ڴ�ij��� + u64 virt_addr io�������ַ + int hmm_acess ����enum rdma_ib_access��ֵ + u32 service_type enum hinic3_service_type��ֵ + Output : None +**************************************************************************** */ +struct hmm_mr *hmm_reg_user_mr(struct hinic3_hwdev *hwdev, u64 start, u32 pdn, u64 length, + u64 virt_addr, int hmm_acess, u32 service_type, u16 channel); + +/* **************************************************************************** + Prototype : hmm_dereg_mr + Description : dereg DMA_MR, user_MR or FRMR + Input : struct hmm_mr *mr + : u32 service_type enum hinic3_service_type的值 + Output : None + +**************************************************************************** */ +int hmm_dereg_mr(struct hmm_mr *mr, u32 service_type, u16 channel); +#endif + +int hmm_rdma_write_mtt(void *hwdev, struct rdma_mtt *mtt, u32 start_index, u32 npages, + u64 *page_list, u32 service_type); + +int hmm_rdma_mtt_alloc(void *hwdev, u32 npages, u32 page_shift, struct rdma_mtt *mtt, u32 service_type); + +void hmm_rdma_mtt_free(void *hwdev, struct rdma_mtt *mtt, u32 service_type); + +int hmm_init_mtt_table(struct hmm_comp_priv *comp_priv); + +void hmm_cleanup_mtt_table(struct hmm_comp_priv *comp_priv); + +#endif /* HINIC_RDMA_H__ */ diff --git a/drivers/infiniband/hw/hiroce3/include/hinic3_rdma.h b/drivers/infiniband/hw/hiroce3/include/hinic3_rdma.h new file mode 100644 index 000000000..3742c28fa --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hinic3_rdma.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2018-2022. All rights reserved. + ****************************************************************************** + History : + 1.Date : 2018/3/8 + Modification: Created file +***************************************************************************** */ + +#ifndef HINIC_RDMA_H__ +#define HINIC_RDMA_H__ + +#define RDMA_ROCE_ENABLE 1 +#define RDMA_IWARP_ENABLE 1 +#define RDMA_ROCE_DISABLE 0 +#define RDMA_IWARP_DISABLE 0 + +#define RDMA_MPT_DISABLED 0 /* has no mpt entry */ +#define RDMA_MPT_EN_SW 1 /* has mpt, state INVALID */ +#define RDMA_MPT_EN_HW 2 /* has mpt, state FREE or VALID */ + +#define RDMA_MPT_FIX_BUG_LKEY 0 + +struct mutex; +struct tag_cqm_qpc_mpt; +struct tag_cqm_object; +struct net_device; +struct rdma_gid_entry; + +#include "hinic3_cqm.h" + +enum mtt_check_type_e { + MTT_CHECK_TYPE_0 = 0, + MTT_CHECK_TYPE_1 +}; + +enum mtt_data_type_e { + MTT_DMTT_TYPE = 0, + MTT_CMTT_TYPE +}; + +enum rdma_ib_access { + RDMA_IB_ACCESS_LOCAL_WRITE = 1, + RDMA_IB_ACCESS_REMOTE_WRITE = (1 << 1), + RDMA_IB_ACCESS_REMOTE_READ = (1 << 2), + RDMA_IB_ACCESS_REMOTE_ATOMIC = (1 << 3), + RDMA_IB_ACCESS_MW_BIND = (1 << 4), + RDMA_IB_ACCESS_ZERO_BASED = (1 << 5), + RDMA_IB_ACCESS_ON_DEMAND = (1 << 6), +}; + +struct rdma_gid_entry { + union { + u8 raw[16]; + struct { + __be64 subnet_prefix; + __be64 interface_id; + } global; + }; + union { + struct { + u32 rsvd : 7; + u32 is_vroce : 1; + u32 cvlan : 12; /* 内层vlan customer vlan */ + u32 svlan : 12; /* 外层vlan */ + } bs; + u32 value; + } dw4; + + union { + u32 hdr_len_value; + }; + + union { + struct { + u16 tag : 2; /* 0:没有vlan； 1：一层vlan； 2: 2层vlan； 3：stag */ + u16 tunnel : 1; // rsvd for ppe, don't use. 'tunnel' + u16 gid_type : 2; + u16 ppe_rsvd1 : 1; + u16 outer_tag : 2; // rsvd for ppe, don't use. 'outer_tag' + u16 ppe_rsvd3 : 1; // rsvd for ppe, don't use. 'stag' + u16 gid_update : 1; + u16 rsvd : 6; + } bs; + u16 value; + } dw6_h; + + u8 smac[6]; +}; + +struct rdma_comp_resource { + struct mutex mutex; /* gid_entry使用的互斥量 */ + __be64 node_guid; /* 与ibdev中的node_guid一致 */ + struct rdma_gid_entry **gid_table; /* gid_entry在rdma组件初始化时分配内存 */ +}; + +struct rdma_mpt { + u32 mpt_index; /* 封装cqm提供的mpt_index */ + void *vaddr; /* 封装cqm提供的mpt_entry的虚拟地址 */ + void *mpt_object; /* 封装的cqm提供的指针 */ +}; + + +struct rdma_mtt_seg { + u32 offset; /* 分配连续索引的首个索引 */ + u32 order; /* mtt索引个数为1<<order，每个索引对应一个mtt entry */ + void *vaddr; /* mtt_seg第一个MTT的起始虚拟地址 */ + dma_addr_t paddr; /* mtt_seg第一个MTT的起始物理地址 */ +}; + +struct rdma_mtt { + u32 mtt_layers; /* mtt的级数,该值为0时表示不使用mtt做地址转换 */ + u32 mtt_page_shift; /* MTT的页大小 */ + u32 buf_page_shift; /* buffer页大小 */ + dma_addr_t mtt_paddr; /* 写入context中的物理地址 */ + __be64 *mtt_vaddr; /* 写入context中的虚拟地址 */ + struct rdma_mtt_seg **mtt_seg; /* 指向多级mtt */ + enum mtt_data_type_e mtt_type; +}; + +enum rdma_mr_type { + RDMA_DMA_MR = 0, + RDMA_USER_MR = 1, + RDMA_FRMR = 2, + RDMA_FMR = 3, + RDMA_PHYS_MR = 4, + RDMA_RSVD_LKEY = 5, + RDMA_SIG_MR = 6, + RDMA_INDIRECT_MR = 8, + RDMA_ODP_IMPLICIT_MR = 9, + RDMA_ODP_EXPLICIT_MR = 10, +}; + +struct rdma_mr { + struct rdma_mpt mpt; + struct rdma_mtt mtt; + u64 iova; /* mr指向内存的起始地址(虚拟地址,ZBVA时为0) */ + u64 size; /* mr指向内存的大小 */ + u32 key; /* mr对应的key */ + u32 pdn; /* mr绑定的pdn */ + u32 access; /* mr的访问权限 */ + int enabled; /* mr的状态,DISABLE、EN_SW、EN_HW */ + int mr_type; /* mr类型 */ + u32 block_size; +}; + +enum rdma_mw_type { + RDMA_MW_TYPE_1 = 1, + RDMA_MW_TYPE_2 = 2 +}; + +struct rdma_mw { + struct rdma_mpt mpt; + u32 key; /* mw对应的key */ + u32 pdn; /* mw绑定的pdn */ + enum rdma_mw_type type; /* mw的类型,type1,type2 */ + int enabled; /* mw的状态 */ +}; + +struct rdma_fmr { + struct rdma_mr mr; + u32 max_pages; /* fmr的最大映射页个数 */ + u32 max_maps; /* fmr的最大映射次数 */ + u32 maps; /* fmr的当前映射次数 */ + u32 page_shift; /* fmr指定的页偏移 */ +}; + +struct rdma_rdmarc { + u32 offset; /* 分配连续索引的首个索引 */ + u32 order; /* 分配的rdmarc的order,代表了个数 */ + u32 ext_order; /* 包含rc表和扩展表的个数 */ + dma_addr_t dma_addr; + void *vaddr; +}; + +int roce3_rdma_pd_alloc(void *hwdev, u32 *pdn); + +void roce3_rdma_pd_free(void *hwdev, u32 pdn); + +int roce3_rdma_enable_mw_mpt(void *hwdev, struct rdma_mw *mw, u32 service_type); + +int roce3_rdma_disable_mw_mpt(void *hwdev, struct rdma_mw *mw, u32 service_type); + +int roce3_rdma_map_phys_fmr(void *hwdev, struct rdma_fmr *fmr, u64 *page_list, int npages, u64 iova, u32 service_type); + +int roce3_rdma_unmap_fmr(void *hwdev, struct rdma_fmr *fmr, u32 service_type); + +int roce3_rdma_rdmarc_alloc(void *hwdev, u32 num, struct rdma_rdmarc *rdmarc); + +void roce3_rdma_rdmarc_free(void *hwdev, struct rdma_rdmarc *rdmarc); + +int roce3_rdma_update_gid_mac(void *hwdev, u32 port, struct rdma_gid_entry *gid_entry); +int roce3_rdma_update_gid(void *hwdev, u32 port, u32 update_index, struct rdma_gid_entry *gid_entry); +int roce3_rdma_reset_gid_table(void *hwdev, u32 port); + +int roce3_rdma_get_gid(void *hwdev, u32 port, u32 gid_index, struct rdma_gid_entry *gid); + +/* 该接口在pf初始化时调用 */ +int roce3_rdma_init_resource(void *hwdev); + +/* 该接口在pf卸载时调用 */ +void roce3_rdma_cleanup_resource(void *hwdev); + +#endif /* HINIC_RDMA_H__ */ diff --git a/drivers/infiniband/hw/hiroce3/include/hinic3_srv_nic.h b/drivers/infiniband/hw/hiroce3/include/hinic3_srv_nic.h new file mode 100644 index 000000000..245097b3a --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hinic3_srv_nic.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) Huawei Technologies Co., Ltd. 2018-2022. All rights reserved. + ****************************************************************************** + * @file hinic3_srv_nic.h + * @details nic service interface + History : + 1.Date : 2018/3/8 + Modification: Created file +***************************************************************************** */ + +#ifndef HINIC3_SRV_NIC_H +#define HINIC3_SRV_NIC_H + +#include "nic_mpu_cmd_defs.h" +#include "mag_mpu_cmd.h" +#include "mag_mpu_cmd_defs.h" +#include "hinic3_lld.h" + +enum hinic3_queue_type { + HINIC3_SQ, + HINIC3_RQ, + HINIC3_MAX_QUEUE_TYPE +}; + +struct hinic3_lld_dev *hinic3_get_lld_dev_by_netdev(struct net_device *netdev); +struct net_device *hinic3_get_netdev_by_lld(struct hinic3_lld_dev *lld_dev); + +struct hinic3_event_link_info { + u8 valid; + u8 port_type; + u8 autoneg_cap; + u8 autoneg_state; + u8 duplex; + u8 speed; +}; + +enum link_err_type { + LINK_ERR_MODULE_UNRECOGENIZED, + LINK_ERR_NUM, +}; + +enum port_module_event_type { + HINIC3_PORT_MODULE_CABLE_PLUGGED, + HINIC3_PORT_MODULE_CABLE_UNPLUGGED, + HINIC3_PORT_MODULE_LINK_ERR, + HINIC3_PORT_MODULE_MAX_EVENT, +}; + +struct hinic3_port_module_event { + enum port_module_event_type type; + enum link_err_type err_type; +}; + +struct hinic3_dcb_info { + u8 dcb_on; + u8 default_cos; + u8 up_cos[NIC_DCB_COS_MAX]; +}; + +enum hinic3_nic_event_type { + EVENT_NIC_LINK_DOWN, + EVENT_NIC_LINK_UP, + EVENT_NIC_PORT_MODULE_EVENT, + EVENT_NIC_DCB_STATE_CHANGE, + EVENT_NIC_BOND_DOWN, + EVENT_NIC_BOND_UP, +}; + +/* * + * @brief hinic3_set_mac - set mac address + * @param hwdev: device pointer to hwdev + * @param mac_addr: mac address from hardware + * @param vlan_id: vlan id + * @param func_id: function index + * @param channel: channel id + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_set_mac(void *hwdev, const u8 *mac_addr, u16 vlan_id, u16 func_id, u16 channel); + +/* * + * @brief hinic3_del_mac - delete mac address + * @param hwdev: device pointer to hwdev + * @param mac_addr: mac address from hardware + * @param vlan_id: vlan id + * @param func_id: function index + * @param channel: channel id + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_del_mac(void *hwdev, const u8 *mac_addr, u16 vlan_id, u16 func_id, u16 channel); + +/* * + * @brief hinic3_set_vport_enable - set function valid status + * @param hwdev: device pointer to hwdev + * @param func_id: global function index + * @param enable: 0-disable, 1-enable + * @param channel: channel id + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_set_vport_enable(void *hwdev, u16 func_id, bool enable, u16 channel); + +/* * + * @brief hinic3_set_port_enable - set port status + * @param hwdev: device pointer to hwdev + * @param enable: 0-disable, 1-enable + * @param channel: channel id + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_set_port_enable(void *hwdev, bool enable, u16 channel); + +/* * + * @brief hinic3_flush_qps_res - flush queue pairs resource in hardware + * @param hwdev: device pointer to hwdev + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_flush_qps_res(void *hwdev); + +/* * + * @brief hinic3_cache_out_qps_res - cache out queue pairs wqe resource in hardware + * @param hwdev: device pointer to hwdev + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_cache_out_qps_res(void *hwdev); + +/* * + * @brief hinic3_init_nic_hwdev - init nic hwdev + * @param hwdev: device pointer to hwdev + * @param pcidev_hdl: pointer to pcidev or handler + * @param dev_hdl: pointer to pcidev->dev or handler, for sdk_err() or + * dma_alloc() + * @param rx_buff_len: rx_buff_len is receive buffer length + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_init_nic_hwdev(void *hwdev, void *pcidev_hdl, void *dev_hdl, u16 rx_buff_len); + +/* * + * @brief hinic3_free_nic_hwdev - free nic hwdev + * @param hwdev: device pointer to hwdev + * @retval zero: success + * @retval non-zero: failure + */ +void hinic3_free_nic_hwdev(void *hwdev); + +/* * + * @brief hinic3_get_speed - set link speed + * @param hwdev: device pointer to hwdev + * @param port_info: link speed + * @param channel: channel id + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_get_speed(void *hwdev, enum mag_cmd_port_speed *speed, u16 channel); + +int hinic3_get_dcb_state(void *hwdev, struct hinic3_dcb_state *dcb_state); + +int hinic3_get_pf_dcb_state(void *hwdev, struct hinic3_dcb_state *dcb_state); + +int hinic3_get_cos_by_pri(void *hwdev, u8 pri, u8 *cos); + +/* * + * @brief hinic3_create_qps - create queue pairs + * @param hwdev: device pointer to hwdev + * @param num_qp: number of queue pairs + * @param sq_depth: sq depth + * @param rq_depth: rq depth + * @param qps_msix_arry: msix info + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_create_qps(void *hwdev, u16 num_qp, u32 sq_depth, u32 rq_depth, + struct irq_info *qps_msix_arry); + +/* * + * @brief hinic3_destroy_qps - destroy queue pairs + * @param hwdev: device pointer to hwdev + */ +void hinic3_destroy_qps(void *hwdev); + +/* * + * @brief hinic3_get_nic_queue - get nic queue + * @param hwdev: device pointer to hwdev + * @param q_id: queue index + * @param q_type: queue type + * @retval queue address + */ +void *hinic3_get_nic_queue(void *hwdev, u16 q_id, enum hinic3_queue_type q_type); + +/* * + * @brief hinic3_init_qp_ctxts - init queue pair context + * @param hwdev: device pointer to hwdev + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_init_qp_ctxts(void *hwdev); + +/* * + * @brief hinic3_free_qp_ctxts - free queue pairs + * @param hwdev: device pointer to hwdev + */ +void hinic3_free_qp_ctxts(void *hwdev); + +/* * + * @brief hinic3_pf_set_vf_link_state pf set vf link state + * @param hwdev: device pointer to hwdev + * @param vf_link_forced: set link forced + * @param link_state: Set link state, This parameter is valid only when vf_link_forced is true + * @retval zero: success + * @retval non-zero: failure + */ +int hinic3_pf_set_vf_link_state(void *hwdev, bool vf_link_forced, bool link_state); + +#endif diff --git a/drivers/infiniband/hw/hiroce3/include/hw/db_srv_type_pub.h b/drivers/infiniband/hw/hiroce3/include/hw/db_srv_type_pub.h new file mode 100644 index 000000000..85fd83f38 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/db_srv_type_pub.h @@ -0,0 +1,126 @@ +/* ***************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2015-2022. All rights reserved. + ****************************************************************************** + File name: Db_srv_type_pub.h + Version No.: Draft + Generated on May 28,: 2015 + Latest modification: + Function Description: Sml_table.h header file + Function list: + Modification history: + 1. Date: 2015 May 28 + Modify content: Create a file. + +***************************************************************************** */ + +#ifndef DB_SRV_TYPE_H +#define DB_SRV_TYPE_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +typedef enum { + DOORBELL_CMDQ_SRV_TYPE = 0, + DOORBELL_L2NIC_SRV_TYPE = 1, + DOORBELL_ROCE_SRV_TYPE = 2, + DOORBELL_ROCE_ARM_CQ_SRV_TYPE = 3, + DOORBELL_NOF1_SRV_TYPE = 4, + + DOORBELL_VIRTIO_SRV_TYPE = 5, + + DOORBELL_TOE_RQ1_SRV_TYPE = 6, + DOORBELL_TOE_RQ2_SRV_TYPE = 7, + DOORBELL_TOE_RQ4_SRV_TYPE = 8, + + DOORBELL_TOE_ISCSI_TGT_SRV_TYPE = 9, + DOORBELL_TOE_ISCSI_TGT_AA_HARD_SRV_TYPE = 10, + DOORBELL_TOE_ISCSI_TGT_AA_PROTOCOL_SRV_TYPE = 11, + + DOORBELL_FC_PARENT_RQ1_SRV_TYPE = 12, + DOORBELL_FC_PARENT_RQ2_SRV_TYPE = 13, + DOORBELL_FC_PARENT_RQ4_SRV_TYPE = 14, + + REMOTE_DB_ROCE_SRV_TYPE = 15, + DOORBELL_NOF2_SRV_TYPE = 16, + + DOORBELL_OVS_DPIF_TX_SRV_TYPE = 17, + DOORBELL_NVME_SQ_SRV_TYPE = 18, + DOORBELL_NVME_CQ_SRV_TYPE = 19, + DOORBELL_PCQ_SRV_TYPE = 20, /* dsw volq doorbell(producer and consumer) */ + + DOORBELL_ROCE_RQ_CNP_TYPE = 21, + DOORBELL_ROCE_SQA_CNP_TYPE = 22, + + DOORBELL_RSVD25 = 25, + DOORBELL_RSVD26 = 26, + DOORBELL_NOF3_SRV_TYPE = 27, + + DOORBELL_FC_CHILD0_SRV_TYPE = 28, + DOORBELL_FC_CHILD1_SRV_TYPE = 29, + DOORBELL_FC_CHILD2_SRV_TYPE = 30, + DOORBELL_RSV2 = 31, // For stateless timer +} doorbell_srv_type_e; + +/* * + * Enum name : armcq_type_e + * @brief xxxxxxxx + * Description: xxxxxxxxxxxxxxx + */ +typedef enum { + ARMCQ_RDMA = 0, + ARMCQ_TIFOE, + ARMCQ_IWARP +} armcq_type_e; + +typedef enum { + NO_QUEUE_Q_TYPE, + TOE_SQ_Q_TYPE, + TOE_RQ_Q_TYPE, + IOE_SQ_Q_TYPE, + IOE_RQ_Q_TYPE, + EMBEDED_CQ_Q_TYPE, + ROCE_SQ_Q_TYPE, + ROCE_RQ_Q_TYPE, + EXTERNAL_CQ_Q_TYPE, + SRQ_Q_TYPE +} doorbell_queue_type_e; + +typedef enum { + DB_CONTEXT_SIZE_256B, + DB_CONTEXT_SIZE_512B, + DB_CONTEXT_SIZE_RSVD, + DB_CONTEXT_SIZE_1024B +} doorbell_context_size_e; + +typedef enum { + DB_KEY_SIZE_RSVD, + DB_KEY_SIZE_10B, + DB_KEY_SIZE_26B, + DB_KEY_SIZE_42B +} doorbell_key_size_e; + + +/* * DB_SUBTYPE_E */ +enum DB_SUBTYPE_E { + DB_SUBTYPE_NONE = 0, + DB_SUBTYPE_RC_SEND = 1, + DB_SUBTYPE_RC_SEND_IMME = 2, + DB_SUBTYPE_RC_WRITE = 3, + DB_SUBTYPE_RC_WRITE_IMME = 4, + DB_SUBTYPE_RC_READ = 5, + DB_SUBTYPE_RC_ATOMIC_CMPSWP = 6, + DB_SUBTYPE_RC_ATOMIC_FETCHADD = 7 +}; + + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + + +#endif /* DB_SRV_TYPE_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/node_id.h b/drivers/infiniband/hw/hiroce3/include/hw/node_id.h new file mode 100644 index 000000000..7d30fb009 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/node_id.h @@ -0,0 +1,58 @@ +/****************************************************************************** + * Copyright (c) Huawei Technologies Co., Ltd. 2022. All rights reserved. + ****************************************************************************** + * @file node_id.h + * @brief node_id.h header file + * @date 2022/4/27 + * History: +******************************************************************************/ +#ifndef NODE_ID_H +#define NODE_ID_H + +#ifdef __cplusplus +#if __cplusplus +extern "C"{ +#endif +#endif /* __cplusplus */ + +/** RING NODE ID */ +typedef enum { + NODE_ID_CPI = 0, + NODE_ID_MQM = 1, + NODE_ID_QUF = 2, + NODE_ID_Reserved0 = 3, + NODE_ID_SMF0 = 4, + NODE_ID_TILE_F0 = 5, + NODE_ID_TILE_F1 = 6, + NODE_ID_SMF1 = 7, + NODE_ID_DP_NETWORK = 8, + NODE_ID_CPB = 9, + NODE_ID_QUL = 10, + NODE_ID_TS = 11, + NODE_ID_TILE_L1 = 12, + NODE_ID_SML1 = 13, + NODE_ID_SML0 = 14, + NODE_ID_TILE_L0 = 15, + NODE_ID_SMF2 = 16, + NODE_ID_TILE_F2 = 17, + NODE_ID_TILE_F3 = 18, + NODE_ID_SMF3 = 19, + NODE_ID_TILE_L3 = 20, + NODE_ID_SML3 = 21, + NODE_ID_SML2 = 22, + NODE_ID_TILE_L2 = 23, + NODE_ID_CRYPTO = 24, + NODE_ID_LCAM = 25, + NODE_ID_MPU = 26, + NODE_ID_DP_HOST = 27, + NODE_ID_UP_HOST = 31 /* Used for API chain function in the CPI */ +} INTERNAL_RING_NODE_ID_E; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +#endif /* NODE_ID_H */ + diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_c_union_define.h new file mode 100644 index 000000000..3c67c555f --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_c_union_define.h @@ -0,0 +1,318 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cnb_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/10/23 11:25:21 Create file +// ****************************************************************************** + +#ifndef CNB_C_UNION_DEFINE_H +#define CNB_C_UNION_DEFINE_H + +/* Define the union csr_cnb_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_version_u; + +/* Define the union csr_cnb_tmout_cnt_thd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tmout_cnt_thd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_tmout_cnt_thd_u; + +/* Define the union csr_cnb_empty_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_err_addr : 26; /* [25:0] */ + u32 rsv_0 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_empty_addr_u; + +/* Define the union csr_cnb_api_err_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_err_flit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_err_flit_cnt_u; + +/* Define the union csr_cnb_api_crt_msge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_crt_msge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_crt_msge_cnt_u; + +/* Define the union csr_cnb_api_tx_msge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_tx_msge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_tx_msge_cnt_u; + +/* Define the union csr_cnb_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_1 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_2 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_vector_u; + +/* Define the union csr_cnb_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_3 : 10; /* [15:6] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_u; + +/* Define the union csr_cnb_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 6; /* [5:0] */ + u32 rsv_4 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_en_u; + +/* Define the union csr_cnb_api_op_code_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 opcode_err : 1; /* [0] */ + u32 opcode_err_insrt : 1; /* [1] */ + u32 opcode_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_op_code_err_u; + +/* Define the union csr_cnb_csr_cmd_parity_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmdpar_err : 1; /* [0] */ + u32 cmdpar_err_insrt : 1; /* [1] */ + u32 cmdpar_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_cmd_parity_err_u; + +/* Define the union csr_cnb_csr_wr_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wrcmd_err : 1; /* [0] */ + u32 wrcmd_err_insrt : 1; /* [1] */ + u32 wrcmd_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_wr_err_u; + +/* Define the union csr_cnb_csr_rddat_parity_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdatpar_err : 1; /* [0] */ + u32 rdatpar_err_insrt : 1; /* [1] */ + u32 rdatpar_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_rddat_parity_err_u; + +/* Define the union csr_cnb_csr_rd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdcmd_err : 1; /* [0] */ + u32 rdcmd_err_insrt : 1; /* [1] */ + u32 rdcmd_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_rd_err_u; + +/* Define the union csr_cnb_merr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmout_err : 1; /* [0] */ + u32 tmout_err_insrt : 1; /* [1] */ + u32 intpar_err : 1; /* [2] */ + u32 intpar_err_insrt : 1; /* [3] */ + u32 api_e1_err : 1; /* [4] */ + u32 api_e1_err_insrt : 1; /* [5] */ + u32 api_e0_err : 1; /* [6] */ + u32 api_e0_err_insrt : 1; /* [7] */ + u32 api_token_err : 1; /* [8] */ + u32 api_token_err_insrt : 1; /* [9] */ + u32 api_prot_err : 1; /* [10] */ + u32 api_prot_err_insrt : 1; /* [11] */ + u32 rsv_5 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_merr_u; + +/* Define the union csr_cnb_merr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tmout_err_en : 1; /* [0] */ + u32 intpar_err_en : 1; /* [1] */ + u32 api_e1_err_en : 1; /* [2] */ + u32 api_e0_err_en : 1; /* [3] */ + u32 api_token_err_en : 1; /* [4] */ + u32 api_prot_err_en : 1; /* [5] */ + u32 rsv_6 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_merr_en_u; + +/* Define the union csr_rs_nd_pe_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crdt_sta : 10; /* [9:0] */ + u32 rsv_7 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rs_nd_pe_crdt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cnb_version_u cnb_version; /* 0 */ + volatile csr_cnb_tmout_cnt_thd_u cnb_tmout_cnt_thd; /* 4 */ + volatile csr_cnb_empty_addr_u cnb_empty_addr; /* 8 */ + volatile csr_cnb_api_err_flit_cnt_u cnb_api_err_flit_cnt; /* C */ + volatile csr_cnb_api_crt_msge_cnt_u cnb_api_crt_msge_cnt; /* 10 */ + volatile csr_cnb_api_tx_msge_cnt_u cnb_api_tx_msge_cnt; /* 14 */ + volatile csr_cnb_int_vector_u cnb_int_vector; /* 18 */ + volatile csr_cnb_int_u cnb_int; /* 1C */ + volatile csr_cnb_int_en_u cnb_int_en; /* 20 */ + volatile csr_cnb_api_op_code_err_u cnb_api_op_code_err; /* 24 */ + volatile csr_cnb_csr_cmd_parity_err_u cnb_csr_cmd_parity_err; /* 28 */ + volatile csr_cnb_csr_wr_err_u cnb_csr_wr_err; /* 2C */ + volatile csr_cnb_csr_rddat_parity_err_u cnb_csr_rddat_parity_err; /* 30 */ + volatile csr_cnb_csr_rd_err_u cnb_csr_rd_err; /* 34 */ + volatile csr_cnb_merr_u cnb_merr; /* 38 */ + volatile csr_cnb_merr_en_u cnb_merr_en; /* 3C */ + volatile csr_rs_nd_pe_crdt_u rs_nd_pe_crdt; /* 40 */ +} S_cnb_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cnb_csr */ +extern volatile S_cnb_csr_REGS_TYPE *gopcnb_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCNB_VERSION_cnb_version(unsigned int ucnb_version); +int iSetCNB_TMOUT_CNT_THD_rp_tmout_cnt_thd(unsigned int urp_tmout_cnt_thd); +int iSetCNB_EMPTY_ADDR_api_err_addr(unsigned int uapi_err_addr); +int iSetCNB_API_ERR_FLIT_CNT_cnb_api_err_flit_cnt(unsigned int ucnb_api_err_flit_cnt); +int iSetCNB_API_CRT_MSGE_CNT_cnb_api_crt_msge_cnt(unsigned int ucnb_api_crt_msge_cnt); +int iSetCNB_API_TX_MSGE_CNT_cnb_api_tx_msge_cnt(unsigned int ucnb_api_tx_msge_cnt); +int iSetCNB_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetCNB_INT_VECTOR_enable(unsigned int uenable); +int iSetCNB_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetCNB_INT_int_data(unsigned int uint_data); +int iSetCNB_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetCNB_INT_EN_int_en(unsigned int uint_en); +int iSetCNB_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetCNB_API_OP_CODE_ERR_opcode_err(unsigned int uopcode_err); +int iSetCNB_API_OP_CODE_ERR_opcode_err_insrt(unsigned int uopcode_err_insrt); +int iSetCNB_API_OP_CODE_ERR_opcode_err_info(unsigned int uopcode_err_info); +int iSetCNB_CSR_CMD_PARITY_ERR_cmdpar_err(unsigned int ucmdpar_err); +int iSetCNB_CSR_CMD_PARITY_ERR_cmdpar_err_insrt(unsigned int ucmdpar_err_insrt); +int iSetCNB_CSR_CMD_PARITY_ERR_cmdpar_err_info(unsigned int ucmdpar_err_info); +int iSetCNB_CSR_WR_ERR_wrcmd_err(unsigned int uwrcmd_err); +int iSetCNB_CSR_WR_ERR_wrcmd_err_insrt(unsigned int uwrcmd_err_insrt); +int iSetCNB_CSR_WR_ERR_wrcmd_err_info(unsigned int uwrcmd_err_info); +int iSetCNB_CSR_RDDAT_PARITY_ERR_rdatpar_err(unsigned int urdatpar_err); +int iSetCNB_CSR_RDDAT_PARITY_ERR_rdatpar_err_insrt(unsigned int urdatpar_err_insrt); +int iSetCNB_CSR_RDDAT_PARITY_ERR_rdatpar_err_info(unsigned int urdatpar_err_info); +int iSetCNB_CSR_RD_ERR_rdcmd_err(unsigned int urdcmd_err); +int iSetCNB_CSR_RD_ERR_rdcmd_err_insrt(unsigned int urdcmd_err_insrt); +int iSetCNB_CSR_RD_ERR_rdcmd_err_info(unsigned int urdcmd_err_info); +int iSetCNB_MERR_tmout_err(unsigned int utmout_err); +int iSetCNB_MERR_tmout_err_insrt(unsigned int utmout_err_insrt); +int iSetCNB_MERR_intpar_err(unsigned int uintpar_err); +int iSetCNB_MERR_intpar_err_insrt(unsigned int uintpar_err_insrt); +int iSetCNB_MERR_api_e1_err(unsigned int uapi_e1_err); +int iSetCNB_MERR_api_e1_err_insrt(unsigned int uapi_e1_err_insrt); +int iSetCNB_MERR_api_e0_err(unsigned int uapi_e0_err); +int iSetCNB_MERR_api_e0_err_insrt(unsigned int uapi_e0_err_insrt); +int iSetCNB_MERR_api_token_err(unsigned int uapi_token_err); +int iSetCNB_MERR_api_token_err_insrt(unsigned int uapi_token_err_insrt); +int iSetCNB_MERR_api_prot_err(unsigned int uapi_prot_err); +int iSetCNB_MERR_api_prot_err_insrt(unsigned int uapi_prot_err_insrt); +int iSetCNB_MERR_EN_tmout_err_en(unsigned int utmout_err_en); +int iSetCNB_MERR_EN_intpar_err_en(unsigned int uintpar_err_en); +int iSetCNB_MERR_EN_api_e1_err_en(unsigned int uapi_e1_err_en); +int iSetCNB_MERR_EN_api_e0_err_en(unsigned int uapi_e0_err_en); +int iSetCNB_MERR_EN_api_token_err_en(unsigned int uapi_token_err_en); +int iSetCNB_MERR_EN_api_prot_err_en(unsigned int uapi_prot_err_en); +int iSetRS_ND_PE_CRDT_crdt_sta(unsigned int ucrdt_sta); + + +#endif // CNB_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_reg_offset.h new file mode 100644 index 000000000..139d687f2 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cnb_reg_offset.h @@ -0,0 +1,42 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cnb_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/10/23 11:25:21 Create file +// ****************************************************************************** + +#ifndef CNB_REG_OFFSET_H +#define CNB_REG_OFFSET_H + +/* CNB_CSR Base address of Module's Register */ +#define CSR_CNB_CSR_BASE (0x0) + +/* **************************************************************************** */ +/* CNB_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CNB_CSR_CNB_VERSION_REG (CSR_CNB_CSR_BASE + 0x0) /* 版本寄存器和EC寄存器。 */ +#define CSR_CNB_CSR_CNB_TMOUT_CNT_THD_REG (CSR_CNB_CSR_BASE + 0x4) /* CNB超时配置寄存器。 */ +#define CSR_CNB_CSR_CNB_EMPTY_ADDR_REG (CSR_CNB_CSR_BASE + 0x8) /* 错误地址记录。 */ +#define CSR_CNB_CSR_CNB_API_ERR_FLIT_CNT_REG (CSR_CNB_CSR_BASE + 0xC) /* Flit错误统计。 */ +#define CSR_CNB_CSR_CNB_API_CRT_MSGE_CNT_REG (CSR_CNB_CSR_BASE + 0x10) /* 接收API统计。 */ +#define CSR_CNB_CSR_CNB_API_TX_MSGE_CNT_REG (CSR_CNB_CSR_BASE + 0x14) /* 发送API统计。 */ +#define CSR_CNB_CSR_CNB_INT_VECTOR_REG (CSR_CNB_CSR_BASE + 0x18) /* 中断向量 */ +#define CSR_CNB_CSR_CNB_INT_REG (CSR_CNB_CSR_BASE + 0x1C) /* 中断状态。 */ +#define CSR_CNB_CSR_CNB_INT_EN_REG (CSR_CNB_CSR_BASE + 0x20) /* 中断使能。 */ +#define CSR_CNB_CSR_CNB_API_OP_CODE_ERR_REG (CSR_CNB_CSR_BASE + 0x24) /* 非法OPCODE错误。 */ +#define CSR_CNB_CSR_CNB_CSR_CMD_PARITY_ERR_REG (CSR_CNB_CSR_BASE + 0x28) /* 奇偶校验错误。 */ +#define CSR_CNB_CSR_CNB_CSR_WR_ERR_REG (CSR_CNB_CSR_BASE + 0x2C) /* 写操作错误。 */ +#define CSR_CNB_CSR_CNB_CSR_RDDAT_PARITY_ERR_REG (CSR_CNB_CSR_BASE + 0x30) /* 读数据奇偶错误。 */ +#define CSR_CNB_CSR_CNB_CSR_RD_ERR_REG (CSR_CNB_CSR_BASE + 0x34) /* 读操作错误。 */ +#define CSR_CNB_CSR_CNB_MERR_REG (CSR_CNB_CSR_BASE + 0x38) /* CNB异常状态。 */ +#define CSR_CNB_CSR_CNB_MERR_EN_REG (CSR_CNB_CSR_BASE + 0x3C) /* CNB异常中断使能寄存器。 */ +#define CSR_CNB_CSR_RS_ND_PE_CRDT_REG (CSR_CNB_CSR_BASE + 0x40) /* 信用统计。 */ + +#endif // CNB_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_c_union_define.h new file mode 100644 index 000000000..589025e74 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_c_union_define.h @@ -0,0 +1,8234 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cpb_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2020/3 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2020/03/24 21:10:00 Create file +// ****************************************************************************** + +#ifndef CPB_C_UNION_DEFINE_H +#define CPB_C_UNION_DEFINE_H + +/* Define the union csr_cpb_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fpga_ver_u; + +/* Define the union csr_cpb_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_emu_ver_u; + +/* Define the union csr_cpb_bank_row_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_bk_row_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_bank_row_en_u; + +/* Define the union csr_cpb_dat_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_datmem_init_start : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_dat_init_start_u; + +/* Define the union csr_cpb_cd_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_cdmem_init_start : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_cd_init_start_u; + +/* Define the union csr_cpb_nptr_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_nptrmem_init_start : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_nptr_init_start_u; + +/* Define the union csr_cpb_ti_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_timem_init_start : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ti_init_start_u; + +/* Define the union csr_cpb_dat_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_datmem_init_done : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_dat_init_done_u; + +/* Define the union csr_cpb_cd_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_cdmem_init_done : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_cd_init_done_u; + +/* Define the union csr_cpb_nptr_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_nptrmem_init_done : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_nptr_init_done_u; + +/* Define the union csr_cpb_ti_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_timem_init_done : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ti_init_done_u; + +/* Define the union csr_cpb_bmp_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_bmp_init_start : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_bmp_init_start_u; + +/* Define the union csr_cpb_bmp_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_bmp_init_done : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_bmp_init_done_u; + +/* Define the union csr_cpb_init_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fpa_init_start : 1; /* [0] */ + u32 rsv_0 : 3; /* [3:1] */ + u32 tso_ctxm_init_start : 1; /* [4] */ + u32 rsv_1 : 3; /* [7:5] */ + u32 tx_port_fp_init_start : 8; /* [15:8] */ + u32 rxlb_fp_init_start : 1; /* [16] */ + u32 rsv_2 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_init_start_u; + +/* Define the union csr_cpb_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_init_done : 1; /* [0] */ + u32 rsv_3 : 3; /* [3:1] */ + u32 fpa_init_done : 1; /* [4] */ + u32 tso_ctxm_init_done : 1; /* [5] */ + u32 rsv_4 : 2; /* [7:6] */ + u32 tx_port_fp_init_done : 8; /* [15:8] */ + u32 rxlb_fp_init_done : 1; /* [16] */ + u32 rsv_5 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_init_done_u; + +/* Define the union csr_cpb_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_cpi_int_index : 24; /* [23:0] */ + u32 rsv_6 : 3; /* [26:24] */ + u32 cpb_int_enable : 1; /* [27] */ + u32 cpb_int_issue : 1; /* [28] */ + u32 rsv_7 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_int_vector_u; + +/* Define the union csr_cpb_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_int_data : 15; /* [14:0] */ + u32 rsv_8 : 1; /* [15] */ + u32 cpb_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_int_u; + +/* Define the union csr_cpb_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_int_en : 15; /* [14:0] */ + u32 rsv_9 : 1; /* [15] */ + u32 cpb_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_int_en_u; + +/* Define the union csr_cpb_ram_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ucerr : 1; /* [0] */ + u32 cpb_ram_ucerr_inj : 1; /* [1] */ + u32 cpb_ram_ucerr_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ucerr_u; + +/* Define the union csr_cpb_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_cerr : 1; /* [0] */ + u32 cpb_ram_cerr_inj : 1; /* [1] */ + u32 cpb_ram_cerr_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_cerr_u; + +/* Define the union csr_cpb_fifo_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_fifo_of_err : 1; /* [0] */ + u32 cpb_fifo_of_err_inj : 1; /* [1] */ + u32 cpb_fifo_of_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fifo_of_err_u; + +/* Define the union csr_cpb_fifo_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_fifo_uf_err : 1; /* [0] */ + u32 cpb_fifo_uf_err_inj : 1; /* [1] */ + u32 cpb_fifo_uf_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fifo_uf_err_u; + +/* Define the union csr_cpb_rx_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_rx_crdt_of_err : 1; /* [0] */ + u32 cpb_rx_crdt_uf_err : 1; /* [1] */ + u32 sge_zero_err : 1; /* [2] */ + u32 cpb_rx_crdt_of_err_inj : 1; /* [3] */ + u32 cpb_rx_crdt_uf_err_inj : 1; /* [4] */ + u32 sge_zero_err_inj : 1; /* [5] */ + u32 cpb_rx_crdt_err_stickey : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_crdt_err_u; + +/* Define the union csr_cpb_tx_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_tx_crdt_of_err : 1; /* [0] */ + u32 cpb_tx_crdt_uf_err : 1; /* [1] */ + u32 cpb_tx_crdt_of_err_inj : 1; /* [2] */ + u32 cpb_tx_crdt_uf_err_inj : 1; /* [3] */ + u32 cpb_tx_crdt_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_crdt_err_u; + +/* Define the union csr_tx_prealc_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_prealc_crdt_err : 1; /* [0] */ + u32 tx_prealc_crdt_err_inj : 1; /* [1] */ + u32 tx_prealc_crdt_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_prealc_crdt_err_u; + +/* Define the union csr_cpb_bp_drop_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_bp_drop_err : 1; /* [0] */ + u32 cpb_bp_drop_err_inj : 1; /* [1] */ + u32 cpb_bp_drop_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_bp_drop_err_u; + +/* Define the union csr_cir_cit_abn_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_abn_err : 1; /* [0] */ + u32 cit_abn_err : 1; /* [1] */ + u32 cir_abn_err_inj : 1; /* [2] */ + u32 cit_abn_err_inj : 1; /* [3] */ + u32 cir_cit_abn_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_cit_abn_err_u; + +/* Define the union csr_cpr_cpt_abn_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_abn_err : 1; /* [0] */ + u32 cpt_abn_err : 1; /* [1] */ + u32 cpr_abn_err_inj : 1; /* [2] */ + u32 cpt_abn_err_inj : 1; /* [3] */ + u32 cpr_cpt_abn_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_cpt_abn_err_u; + +/* Define the union csr_ct_abn_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cstl_abn_err : 1; /* [0] */ + u32 cstf_abn_err : 1; /* [1] */ + u32 cstl_abn_err_inj : 1; /* [2] */ + u32 cstf_abn_err_inj : 1; /* [3] */ + u32 ct_abn_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ct_abn_err_u; + +/* Define the union csr_cq_abn_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ciq_abn_err : 1; /* [0] */ + u32 coq_abn_err : 1; /* [1] */ + u32 ciq_abn_err_inj : 1; /* [2] */ + u32 coq_abn_err_inj : 1; /* [3] */ + u32 cq_abn_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cq_abn_err_u; + +/* Define the union csr_rx_tx_abn_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_rx_abn_err : 1; /* [0] */ + u32 cpb_tx_abn_err : 1; /* [1] */ + u32 cpb_rx_abn_err_inj : 1; /* [2] */ + u32 cpb_tx_abn_err_inj : 1; /* [3] */ + u32 rx_tx_abn_err_stickey : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_tx_abn_err_u; + +/* Define the union csr_cpb_bmu_rsc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_bmu_err : 1; /* [0] */ + u32 cpb_bmu_err_inj : 1; /* [1] */ + u32 cpb_bmu_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_bmu_rsc_err_u; + +/* Define the union csr_cpb_aging_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_aging_err : 1; /* [0] */ + u32 cpb_aging_err_inj : 1; /* [1] */ + u32 cpb_aging_err_stickey : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_aging_err_u; + +/* Define the union csr_cpb_fatal_err_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ucerr_fatal_en : 1; /* [0] */ + u32 cpb_fifo_of_fatal_en : 1; /* [1] */ + u32 cpb_fifo_uf_fatal_en : 1; /* [2] */ + u32 cpb_rx_crdt_err_fatal_en : 1; /* [3] */ + u32 cpb_tx_crdt_err_fatal_en : 1; /* [4] */ + u32 cpb_ipsu_itf_err_fatal_en : 1; /* [5] */ + u32 cpb_pe_itf_err_fatal_en : 1; /* [6] */ + u32 cpb_tile_itf_err_fatal_en : 1; /* [7] */ + u32 cpb_qu_itf_err_fatal_en : 1; /* [8] */ + u32 cpb_rxtx_itf_err_fatal_en : 1; /* [9] */ + u32 cpb_bmp_err_fatal_en : 1; /* [10] */ + u32 rsv_10 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fatal_err_en_u; + +/* Define the union csr_cpb_fatal_err_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ucerr_fatal_sta : 1; /* [0] */ + u32 cpb_fifo_of_fatal_sta : 1; /* [1] */ + u32 cpb_fifo_uf_fatal_sta : 1; /* [2] */ + u32 cpb_rx_crdt_err_fatal_sta : 1; /* [3] */ + u32 cpb_tx_crdt_err_fatal_sta : 1; /* [4] */ + u32 cpb_ipsu_itf_err_fatal_sta : 1; /* [5] */ + u32 cpb_pe_itf_err_fatal_sta : 1; /* [6] */ + u32 cpb_tile_itf_err_fatal_sta : 1; /* [7] */ + u32 cpb_qu_itf_err_fatal_sta : 1; /* [8] */ + u32 cpb_rxtx_itf_err_fatal_sta : 1; /* [9] */ + u32 cpb_bmp_err_fatal_sta : 1; /* [10] */ + u32 rsv_11 : 5; /* [15:11] */ + u32 cpb_ram_ucerr_fatal_clr : 1; /* [16] */ + u32 cpb_fifo_of_fatal_clr : 1; /* [17] */ + u32 cpb_fifo_uf_fatal_clr : 1; /* [18] */ + u32 cpb_rx_crdt_err_fatal_clr : 1; /* [19] */ + u32 cpb_tx_crdt_err_fatal_clr : 1; /* [20] */ + u32 cpb_ipsu_itf_err_fatal_clr : 1; /* [21] */ + u32 cpb_pe_itf_err_fatal_clr : 1; /* [22] */ + u32 cpb_tile_itf_err_fatal_clr : 1; /* [23] */ + u32 cpb_qu_itf_err_fatal_clr : 1; /* [24] */ + u32 cpb_rxtx_itf_err_fatal_clr : 1; /* [25] */ + u32 cpb_bmp_err_fatal_clr : 1; /* [26] */ + u32 rsv_12 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fatal_err_sta_u; + +/* Define the union csr_cpb_itf_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ipsurx_bp_sta : 1; /* [0] */ + u32 cpb_ipsutx_bp_sta : 1; /* [1] */ + u32 iq_cpb_rx_bp_sta : 1; /* [2] */ + u32 iq_cpb_tx_bp_sta : 1; /* [3] */ + u32 cpb_stliq_req_bp_sta : 5; /* [8:4] */ + u32 cpb_stfiq_req_bp_sta : 4; /* [12:9] */ + u32 stlfq_cpb_ackstr_bp_sta : 1; /* [13] */ + u32 stffq_cpb_ackstr_bp_sta : 2; /* [15:14] */ + u32 prm_cpb_alloc_rx_bp_sta : 1; /* [16] */ + u32 prm_cpb_alloc_tx_bp_sta : 1; /* [17] */ + u32 prm_cpb_dealloc_rx_bp_sta : 1; /* [18] */ + u32 prm_cpb_dealloc_tx_bp_sta : 1; /* [19] */ + u32 prm_cpb_prls_bp_sta : 1; /* [20] */ + u32 cpb_oq_rx_bp_sta : 1; /* [21] */ + u32 cpb_oq_tx_bp_sta : 1; /* [22] */ + u32 cpb_oq_drp_bp_sta : 1; /* [23] */ + u32 cpb_pqm_host_bp_sta : 4; /* [27:24] */ + u32 rx_prm_bp_sta : 1; /* [28] */ + u32 tx_mag_bp_sta : 1; /* [29] */ + u32 rx_crdt_bp_sta : 1; /* [30] */ + u32 tx_crdt_bp_sta : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_itf_bp_sta_u; + +/* Define the union csr_cpb_itf_bp_his_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ipsurx_bp_his : 1; /* [0] */ + u32 cpb_ipsutx_bp_his : 1; /* [1] */ + u32 iq_cpb_rx_bp_his : 1; /* [2] */ + u32 iq_cpb_tx_bp_his : 1; /* [3] */ + u32 cpb_stliq_req_bp_his : 5; /* [8:4] */ + u32 cpb_stfiq_req_bp_his : 4; /* [12:9] */ + u32 stlfq_cpb_ackstr_bp_his : 1; /* [13] */ + u32 stffq_cpb_ackstr_bp_his : 2; /* [15:14] */ + u32 prm_cpb_alloc_rx_bp_his : 1; /* [16] */ + u32 prm_cpb_alloc_tx_bp_his : 1; /* [17] */ + u32 prm_cpb_dealloc_rx_bp_his : 1; /* [18] */ + u32 prm_cpb_dealloc_tx_bp_his : 1; /* [19] */ + u32 prm_cpb_prls_bp_his : 1; /* [20] */ + u32 cpb_oq_rx_bp_his : 1; /* [21] */ + u32 cpb_oq_tx_bp_his : 1; /* [22] */ + u32 cpb_oq_drp_bp_his : 1; /* [23] */ + u32 cpb_pqm_host_bp_his : 4; /* [27:24] */ + u32 rx_prm_bp_his : 1; /* [28] */ + u32 tx_mag_bp_his : 1; /* [29] */ + u32 rx_crdt_bp_his : 1; /* [30] */ + u32 tx_crdt_bp_his : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_itf_bp_his_u; + +/* Define the union csr_cpb_api_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_api_err : 1; /* [0] */ + u32 rsv_13 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_api_err_u; + +/* Define the union csr_cpb_fifo_err_col_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_fifo_uf_col : 1; /* [0] */ + u32 stl_fifo_uf_col : 1; /* [1] */ + u32 cpt_fifo_uf_col : 1; /* [2] */ + u32 cpr_fifo_uf_col : 1; /* [3] */ + u32 cit_fifo_uf_col : 1; /* [4] */ + u32 cir_fifo_uf_col : 1; /* [5] */ + u32 ct_ext_dealc_rx_fifo_uf : 1; /* [6] */ + u32 ct_ext_dealc_tx_fifo_uf : 1; /* [7] */ + u32 ciq_fifo_uf_col : 1; /* [8] */ + u32 coq_fifo_uf_col : 1; /* [9] */ + u32 crx_fifo_uf_col : 1; /* [10] */ + u32 ctx_fifo_uf_col : 1; /* [11] */ + u32 cdt_fifo_uf_col : 1; /* [12] */ + u32 rsv_14 : 3; /* [15:13] */ + u32 stf_fifo_ov_col : 1; /* [16] */ + u32 stl_fifo_ov_col : 1; /* [17] */ + u32 cpt_fifo_ov_col : 1; /* [18] */ + u32 cpr_fifo_ov_col : 1; /* [19] */ + u32 cit_fifo_ov_col : 1; /* [20] */ + u32 cir_fifo_ov_col : 1; /* [21] */ + u32 ct_ext_dealc_rx_fifo_ov : 1; /* [22] */ + u32 ct_ext_dealc_tx_fifo_ov : 1; /* [23] */ + u32 ciq_fifo_of_col : 1; /* [24] */ + u32 coq_fifo_of_col : 1; /* [25] */ + u32 crx_fifo_of_col : 1; /* [26] */ + u32 ctx_fifo_of_col : 1; /* [27] */ + u32 cdt_fifo_of_col : 1; /* [28] */ + u32 rsv_15 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_fifo_err_col_u; + +/* Define the union csr_tl_req_invld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_iq_push_len_err : 4; /* [3:0] */ + u32 stf_iq_push_len_err : 4; /* [7:4] */ + u32 stl_cmd_crc_len_err : 4; /* [11:8] */ + u32 stf_cmd_crc_len_err : 4; /* [15:12] */ + u32 stl_cmd_rd_link_err : 4; /* [19:16] */ + u32 stf_cmd_rd_link_err : 4; /* [23:20] */ + u32 rsv_16 : 4; /* [27:24] */ + u32 stf_psh_len_lt_tp_lho : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl_req_invld_u; + +/* Define the union csr_tl_str_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_pe_cmd_len_err : 4; /* [3:0] */ + u32 stf_str_pe_cmd_len_err : 4; /* [7:4] */ + u32 stl_str_cm_len_err : 4; /* [11:8] */ + u32 stf_str_cm_len_err : 4; /* [15:12] */ + u32 stl_str_ext_len_err : 4; /* [19:16] */ + u32 stf_str_ext_len_err : 4; /* [23:20] */ + u32 stl_str_ov_len_err : 4; /* [27:24] */ + u32 stf_str_ov_len_err : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl_str_err_0_u; + +/* Define the union csr_tl_str_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_mio_len_err : 4; /* [3:0] */ + u32 stf_str_mio_len_err : 4; /* [7:4] */ + u32 stl_str_pld_len_err : 4; /* [11:8] */ + u32 stf_str_pld_len_err : 4; /* [15:12] */ + u32 stl_str_ext_omd_len_err : 4; /* [19:16] */ + u32 stf_str_ext_omd_len_err : 4; /* [23:20] */ + u32 stl_str_mc_cmd_num_err : 4; /* [27:24] */ + u32 stf_str_mc_cmd_num_err : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl_str_err_1_u; + +/* Define the union csr_tl_str_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_cmd_len_err : 4; /* [3:0] */ + u32 stf_str_cmd_len_err : 4; /* [7:4] */ + u32 stl_str_para_cmd_cnum_err : 4; /* [11:8] */ + u32 stf_str_para_cmd_cnum_err : 4; /* [15:12] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl_str_err_2_u; + +/* Define the union csr_cpb_ram_ctrl_bus_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ctrl_bus_0_u; + +/* Define the union csr_cpb_ram_ctrl_bus_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ctrl_bus_1_u; + +/* Define the union csr_cpb_ram_ctrl_bus_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ctrl_bus_2_u; + +/* Define the union csr_cpb_ram_ctrl_bus_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ctrl_bus_3_u; + +/* Define the union csr_cpb_ram_ctrl_bus_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_18 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ctrl_bus_4_u; + +/* Define the union csr_cpb_ram_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_ram_ecc_bypass : 1; /* [0] */ + u32 rsv_19 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_ram_ecc_bypass_u; + +/* Define the union csr_cpb_indir_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_indir_addr : 20; /* [19:0] */ + u32 rsv_20 : 4; /* [23:20] */ + u32 cpb_indir_tab : 4; /* [27:24] */ + u32 cpb_indir_state : 2; /* [29:28] */ + u32 cpb_indir_mode : 1; /* [30] */ + u32 cpb_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_indir_ctrl_u; + +/* Define the union csr_cpb_indir_to_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_indir_to_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_indir_to_th_u; + +/* Define the union csr_bank_weak_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_weak_en : 1; /* [0] */ + u32 rsv_21 : 3; /* [3:1] */ + u32 weak_diff_th : 9; /* [12:4] */ + u32 rsv_22 : 3; /* [15:13] */ + u32 weak_low_th : 12; /* [27:16] */ + u32 rsv_23 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bank_weak_cfg_u; + +/* Define the union csr_bmu_alt_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmu_alt_bp_on_th : 9; /* [8:0] */ + u32 rsv_24 : 7; /* [15:9] */ + u32 bmu_alt_bp_off_th : 10; /* [25:16] */ + u32 rsv_25 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_alt_bp_cfg_u; + +/* Define the union csr_bmu_fat_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmu_fatal_bp_on_th : 8; /* [7:0] */ + u32 bmu_fatal_bp_off_th : 8; /* [15:8] */ + u32 ct_fatal_bp_en : 1; /* [16] */ + u32 rsv_26 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_fat_bp_cfg_u; + +/* Define the union csr_bmu_ap_acc_wt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_acc_wt0 : 3; /* [2:0] */ + u32 rsv_27 : 1; /* [3] */ + u32 ap_acc_wt1 : 3; /* [6:4] */ + u32 rsv_28 : 1; /* [7] */ + u32 ap_acc_wt2 : 3; /* [10:8] */ + u32 rsv_29 : 1; /* [11] */ + u32 ap_acc_wt3 : 3; /* [14:12] */ + u32 rsv_30 : 1; /* [15] */ + u32 ap_acc_wt4 : 3; /* [18:16] */ + u32 rsv_31 : 1; /* [19] */ + u32 ap_acc_wt5 : 3; /* [22:20] */ + u32 rsv_32 : 1; /* [23] */ + u32 ap_acc_wt6 : 3; /* [26:24] */ + u32 rsv_33 : 1; /* [27] */ + u32 ap_acc_wt7 : 3; /* [30:28] */ + u32 rsv_34 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_ap_acc_wt0_u; + +/* Define the union csr_bmu_ap_acc_wt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ap_acc_wt8 : 3; /* [2:0] */ + u32 rsv_35 : 1; /* [3] */ + u32 ap_acc_wt9 : 3; /* [6:4] */ + u32 rsv_36 : 1; /* [7] */ + u32 ap_acc_wt10 : 3; /* [10:8] */ + u32 rsv_37 : 1; /* [11] */ + u32 ap_acc_wt11 : 3; /* [14:12] */ + u32 rsv_38 : 1; /* [15] */ + u32 ap_acc_wt12 : 3; /* [18:16] */ + u32 rsv_39 : 1; /* [19] */ + u32 ap_acc_wt13 : 3; /* [22:20] */ + u32 rsv_40 : 1; /* [23] */ + u32 ap_acc_wt14 : 3; /* [26:24] */ + u32 rsv_41 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_ap_acc_wt1_u; + +/* Define the union csr_ti_acc_to_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ti_nm_rreq_to_th0 : 5; /* [4:0] */ + u32 rsv_42 : 3; /* [7:5] */ + u32 ti_nm_rreq_to_th1 : 5; /* [12:8] */ + u32 rsv_43 : 3; /* [15:13] */ + u32 ti_nm_rreq_to_th2 : 5; /* [20:16] */ + u32 rsv_44 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ti_acc_to_th_u; + +/* Define the union csr_bmp_am_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmp_aempty_th : 6; /* [5:0] */ + u32 rsv_45 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmp_am_th_u; + +/* Define the union csr_bk_exht_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_exht_th : 8; /* [7:0] */ + u32 rsv_46 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_exht_th_u; + +/* Define the union csr_cell_rd_rls_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cell_rd_rls_en : 1; /* [0] */ + u32 rsv_47 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cell_rd_rls_en_u; + +/* Define the union csr_cpb_age_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_timer_unit_th : 19; /* [18:0] */ + u32 rsv_48 : 1; /* [19] */ + u32 age_auto_rls_en : 1; /* [20] */ + u32 rsv_49 : 3; /* [23:21] */ + u32 cpb_age_en : 1; /* [24] */ + u32 rsv_50 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_age_cfg_u; + +/* Define the union csr_cpb_age_to_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_age_to_th : 23; /* [22:0] */ + u32 rsv_51 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_age_to_th_u; + +/* Define the union csr_bk_age_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_bmp_addr : 8; /* [7:0] */ + u32 bk_age_addr_found : 1; /* [8] */ + u32 rsv_52 : 3; /* [11:9] */ + u32 bk_cur_age_st : 4; /* [15:12] */ + u32 bk_age_scan_busy : 1; /* [16] */ + u32 rsv_53 : 3; /* [19:17] */ + u32 bk_age_scan_req : 1; /* [20] */ + u32 rsv_54 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_age_cfg_u; + +/* Define the union csr_bk_age_bmp_line_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_bmp_line : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_age_bmp_line_u; + +/* Define the union csr_bk_age_rls_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_rls_addr : 13; /* [12:0] */ + u32 rsv_55 : 3; /* [15:13] */ + u32 bk_age_rls_req : 1; /* [16] */ + u32 rsv_56 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_age_rls_cfg_u; + +/* Define the union csr_bk_age_find_nxt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_find_nxt : 1; /* [0] */ + u32 rsv_57 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_age_find_nxt_u; + +/* Define the union csr_bk_free_rsc_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk0_free_rsc_cnt : 14; /* [13:0] */ + u32 rsv_58 : 2; /* [15:14] */ + u32 bk1_free_rsc_cnt : 14; /* [29:16] */ + u32 rsv_59 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_free_rsc_cnt0_u; + +/* Define the union csr_bk_free_rsc_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk2_free_rsc_cnt : 14; /* [13:0] */ + u32 rsv_60 : 2; /* [15:14] */ + u32 bk3_free_rsc_cnt : 14; /* [29:16] */ + u32 rsv_61 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_free_rsc_cnt1_u; + +/* Define the union csr_bk_free_rsc_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk4_free_rsc_cnt : 14; /* [13:0] */ + u32 rsv_62 : 2; /* [15:14] */ + u32 bk5_free_rsc_cnt : 14; /* [29:16] */ + u32 rsv_63 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_free_rsc_cnt2_u; + +/* Define the union csr_bk_free_rsc_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk6_free_rsc_cnt : 14; /* [13:0] */ + u32 rsv_64 : 2; /* [15:14] */ + u32 bk7_free_rsc_cnt : 14; /* [29:16] */ + u32 rsv_65 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_free_rsc_cnt3_u; + +/* Define the union csr_bk_min_rsc_his_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk0_min_rsc_his_cnt : 14; /* [13:0] */ + u32 rsv_66 : 2; /* [15:14] */ + u32 bk1_min_rsc_his_cnt : 14; /* [29:16] */ + u32 rsv_67 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_min_rsc_his_cnt0_u; + +/* Define the union csr_bk_min_rsc_his_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk2_min_rsc_his_cnt : 14; /* [13:0] */ + u32 rsv_68 : 2; /* [15:14] */ + u32 bk3_min_rsc_his_cnt : 14; /* [29:16] */ + u32 rsv_69 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_min_rsc_his_cnt1_u; + +/* Define the union csr_bk_min_rsc_his_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk4_min_rsc_his_cnt : 14; /* [13:0] */ + u32 rsv_70 : 2; /* [15:14] */ + u32 bk5_min_rsc_his_cnt : 14; /* [29:16] */ + u32 rsv_71 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_min_rsc_his_cnt2_u; + +/* Define the union csr_bk_min_rsc_his_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk6_min_rsc_his_cnt : 14; /* [13:0] */ + u32 rsv_72 : 2; /* [15:14] */ + u32 bk7_min_rsc_his_cnt : 14; /* [29:16] */ + u32 rsv_73 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bk_min_rsc_his_cnt3_u; + +/* Define the union csr_cpb_min_rsc_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_min_rsc_his_cnt : 17; /* [16:0] */ + u32 rsv_74 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_min_rsc_his_cnt_u; + +/* Define the union csr_bmu_rsc_his_cnt_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_min_rsc_his_cnt_clr : 8; /* [7:0] */ + u32 cpb_min_rsc_his_cnt_clr : 1; /* [8] */ + u32 rsv_75 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_rsc_his_cnt_clr_u; + +/* Define the union csr_bmu_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmu_alt_bp : 1; /* [0] */ + u32 rsv_76 : 3; /* [3:1] */ + u32 bmu_fatal_bp : 1; /* [4] */ + u32 rsv_77 : 3; /* [7:5] */ + u32 bk_weak_bp : 8; /* [15:8] */ + u32 bmu_alt_bp_his : 1; /* [16] */ + u32 rsv_78 : 3; /* [19:17] */ + u32 bmu_fatal_bp_his : 1; /* [20] */ + u32 rsv_79 : 3; /* [23:21] */ + u32 bk_weak_bp_his : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmu_bp_sta_u; + +/* Define the union csr_row_bmp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 row_bmp_free_rsc_cnt : 12; /* [11:0] */ + u32 row_bmp_aempty : 1; /* [12] */ + u32 row_bmp_empty : 1; /* [13] */ + u32 rsv_80 : 2; /* [15:14] */ + u32 row_bmp_aempty_his : 1; /* [16] */ + u32 row_bmp_empty_his : 1; /* [17] */ + u32 rsv_81 : 2; /* [19:18] */ + u32 row_bmp_refrain_err_his : 1; /* [20] */ + u32 row_bmp_leak_err_his : 1; /* [21] */ + u32 rsv_82 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_row_bmp_sta_u; + +/* Define the union csr_age_rls_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_rls_cnt0 : 16; /* [15:0] */ + u32 bk_age_rls_cnt1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_age_rls_cnt_0_u; + +/* Define the union csr_age_rls_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_rls_cnt2 : 16; /* [15:0] */ + u32 bk_age_rls_cnt3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_age_rls_cnt_1_u; + +/* Define the union csr_age_rls_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_rls_cnt4 : 16; /* [15:0] */ + u32 bk_age_rls_cnt5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_age_rls_cnt_2_u; + +/* Define the union csr_age_rls_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bk_age_rls_cnt6 : 16; /* [15:0] */ + u32 bk_age_rls_cnt7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_age_rls_cnt_3_u; + +/* Define the union csr_stf_rsp_api_fifo_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_npt_fifo_crdt : 5; /* [4:0] */ + u32 rsv_83 : 3; /* [7:5] */ + u32 stf_rsp_dat_fifo_crdt : 6; /* [13:8] */ + u32 rsv_84 : 2; /* [15:14] */ + u32 stf_rsp_api_hdr_fifo_crdt : 4; /* [19:16] */ + u32 stf_rsp_crc_fifo_crdt : 4; /* [23:20] */ + u32 stf_rsp_api_fifo_crdt_init : 1; /* [24] */ + u32 rsv_85 : 3; /* [27:25] */ + u32 stf_str_rsp_hdr_crdt : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rsp_api_fifo_crdt_init_u; + +/* Define the union csr_stf_psh_cmd_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_cmd_req_wt : 4; /* [3:0] */ + u32 stf_psh_req_wt : 4; /* [7:4] */ + u32 rsv_86 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_psh_cmd_wt_u; + +/* Define the union csr_stf_col_del_md_hdr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_col_del_md_hdr_en : 1; /* [0] */ + u32 rsv_87 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_col_del_md_hdr_en_u; + +/* Define the union csr_stf_rd_req_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rd_req_fifo_af_th : 4; /* [3:0] */ + u32 rsv_88 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rd_req_fifo_af_th_u; + +/* Define the union csr_stf_rd_ctrl_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rd_ctrl_fifo_af_th : 4; /* [3:0] */ + u32 rsv_89 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rd_ctrl_fifo_af_th_u; + +/* Define the union csr_cpb_stf_api_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_stf_api_crdt : 5; /* [4:0] */ + u32 rsv_90 : 3; /* [7:5] */ + u32 cpb_stf_api_crdt_init : 1; /* [8] */ + u32 rsv_91 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_stf_api_crdt_init_u; + +/* Define the union csr_stf_str_di_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_str_di_fifo_af_th : 6; /* [5:0] */ + u32 rsv_92 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_str_di_fifo_af_th_u; + +/* Define the union csr_stf_str_api_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_str_api_fifo_af_th : 6; /* [5:0] */ + u32 rsv_93 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_str_api_fifo_af_th_u; + +/* Define the union csr_stf_cmd_api_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_cmd_api_fifo_af_th : 4; /* [3:0] */ + u32 rsv_94 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_cmd_api_fifo_af_th_u; + +/* Define the union csr_stf_ackstr_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_ackstr_fifo_af_th : 3; /* [2:0] */ + u32 rsv_95 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_ackstr_fifo_af_th_u; + +/* Define the union csr_stf_msg_vfid_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fake_vfid_start_bit : 4; /* [3:0] */ + u32 fake_vfid_end_bit : 4; /* [7:4] */ + u32 rsv_96 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_msg_vfid_ctl_u; + +/* Define the union csr_ct_dma_nret_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_nret_psh2pptr_en : 1; /* [0] */ + u32 rsv_97 : 3; /* [3:1] */ + u32 dma_nret_psh2pptr_fix : 1; /* [4] */ + u32 rsv_98 : 3; /* [7:5] */ + u32 psh_pptr_cmd_len : 4; /* [11:8] */ + u32 rsv_99 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ct_dma_nret_cfg_u; + +/* Define the union csr_ct_col_src_tag_h_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osd_id_i : 4; /* [3:0] */ + u32 osd_id_l : 4; /* [7:4] */ + u32 osd_id_m : 4; /* [11:8] */ + u32 rsv_100 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ct_col_src_tag_h_cfg_u; + +/* Define the union csr_ct_dealc_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ct_dealc_fifo_af_th : 7; /* [6:0] */ + u32 rsv_101 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ct_dealc_fifo_af_th_u; + +/* Define the union csr_stfiq_psh_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfpsh_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_102 : 2; /* [7:6] */ + u32 stfpsh_fifo_af_th : 6; /* [13:8] */ + u32 rsv_103 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_psh_fifo_cfg_u; + +/* Define the union csr_stfiq_link_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_104 : 2; /* [7:6] */ + u32 link_fifo_af_th : 6; /* [13:8] */ + u32 rsv_105 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_link_fifo_cfg_u; + +/* Define the union csr_link_wr_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 linkwr_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_106 : 2; /* [7:6] */ + u32 linkwr_fifo_af_th : 6; /* [13:8] */ + u32 rsv_107 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_link_wr_fifo_cfg_u; + +/* Define the union csr_stf_cmd_api_rd_req_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_cmd_api_fifo_sta : 11; /* [10:0] */ + u32 rsv_108 : 5; /* [15:11] */ + u32 stf_rd_req_fifo_sta : 11; /* [26:16] */ + u32 rsv_109 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_cmd_api_rd_req_fifo_sta_u; + +/* Define the union csr_stf_str_api_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_str_api_fifo_sta : 11; /* [10:0] */ + u32 rsv_110 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_str_api_fifo_sta_u; + +/* Define the union csr_stf_wr_rd_dat_in_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_wr_di_fifo_sta : 11; /* [10:0] */ + u32 rsv_111 : 5; /* [15:11] */ + u32 stf_rd_di_fifo_sta : 11; /* [26:16] */ + u32 rsv_112 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_wr_rd_dat_in_fifo_sta_u; + +/* Define the union csr_stf_rsp_api_hdr_dat_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_api_dat_fifo_sta : 11; /* [10:0] */ + u32 rsv_113 : 5; /* [15:11] */ + u32 stf_rsp_api_hdr_fifo_sta : 11; /* [26:16] */ + u32 rsv_114 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rsp_api_hdr_dat_fifo_sta_u; + +/* Define the union csr_stf_rsp_api_cd_crc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_api_crc_fifo_sta : 11; /* [10:0] */ + u32 rsv_115 : 5; /* [15:11] */ + u32 stf_rsp_api_cd_fifo_sta : 11; /* [26:16] */ + u32 rsv_116 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rsp_api_cd_crc_fifo_sta_u; + +/* Define the union csr_stf_rsp_api_cs_nptr_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_api_nptr_fifo_sta : 11; /* [10:0] */ + u32 rsv_117 : 5; /* [15:11] */ + u32 stf_rsp_api_cs_fifo_sta : 11; /* [26:16] */ + u32 rsv_118 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_rsp_api_cs_nptr_fifo_sta_u; + +/* Define the union csr_stf_str_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_cmd_cnt : 16; /* [15:0] */ + u32 stf_str_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_str_cmd_cnt_u; + +/* Define the union csr_stf_ack_rsp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_cnt : 16; /* [15:0] */ + u32 stf_ack_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_ack_rsp_cnt_u; + +/* Define the union csr_stf_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_psh_tl_cnt : 16; /* [15:0] */ + u32 stf_iq_psh_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_psh_cnt_u; + +/* Define the union csr_stf_cell_mdf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_cell_mdf_cnt : 16; /* [15:0] */ + u32 stf_iq_psh_rm_scol_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_cell_mdf_cnt_u; + +/* Define the union csr_stf_wr_di_ctrl_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_wr_di_ctrl_fifo_sta : 11; /* [10:0] */ + u32 rsv_119 : 5; /* [15:11] */ + u32 stf_ackstr_fifo_sta : 11; /* [26:16] */ + u32 rsv_120 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_wr_di_ctrl_fifo_sta_u; + +/* Define the union csr_stf_fifo_ov_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rd_req_fifo_ov : 4; /* [3:0] */ + u32 stf_cmd_api_fifo_ov : 4; /* [7:4] */ + u32 stf_str_api_fifo_ov : 4; /* [11:8] */ + u32 stf_rd_di_fifo_ov : 2; /* [13:12] */ + u32 rsv_121 : 2; /* [15:14] */ + u32 stf_wr_di_fifo_ov : 2; /* [17:16] */ + u32 rsv_122 : 2; /* [19:18] */ + u32 stf_wr_di_ctrl_fifo_ov : 2; /* [21:20] */ + u32 rsv_123 : 2; /* [23:22] */ + u32 stf_ackstr_fifo_ov : 2; /* [25:24] */ + u32 rsv_124 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_fifo_ov_err_0_u; + +/* Define the union csr_stf_fifo_ov_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_api_hdr_fifo_ov : 4; /* [3:0] */ + u32 stf_rsp_api_dat_fifo_ov : 4; /* [7:4] */ + u32 stf_rsp_api_cd_fifo_ov : 4; /* [11:8] */ + u32 stf_rsp_api_crc_fifo_ov : 4; /* [15:12] */ + u32 stf_rsp_api_cs_fifo_ov : 4; /* [19:16] */ + u32 stf_rsp_api_nptr_fifo_ov : 4; /* [23:20] */ + u32 rsv_125 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_fifo_ov_err_1_u; + +/* Define the union csr_stf_fifo_uf_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rd_req_fifo_uf : 4; /* [3:0] */ + u32 stf_cmd_api_fifo_uf : 4; /* [7:4] */ + u32 stf_str_api_fifo_uf : 4; /* [11:8] */ + u32 stf_rd_di_fifo_uf : 2; /* [13:12] */ + u32 rsv_126 : 2; /* [15:14] */ + u32 stf_wr_di_fifo_uf : 2; /* [17:16] */ + u32 rsv_127 : 2; /* [19:18] */ + u32 stf_wr_di_ctrl_fifo_uf : 2; /* [21:20] */ + u32 rsv_128 : 2; /* [23:22] */ + u32 stf_ackstr_fifo_uf : 2; /* [25:24] */ + u32 rsv_129 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_fifo_uf_err_0_u; + +/* Define the union csr_stf_fifo_uf_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_rsp_api_hdr_fifo_uf : 4; /* [3:0] */ + u32 stf_rsp_api_dat_fifo_uf : 4; /* [7:4] */ + u32 stf_rsp_api_cd_fifo_uf : 4; /* [11:8] */ + u32 stf_rsp_api_crc_fifo_uf : 4; /* [15:12] */ + u32 stf_rsp_api_cs_fifo_uf : 4; /* [19:16] */ + u32 stf_rsp_api_nptr_fifo_uf : 4; /* [23:20] */ + u32 rsv_130 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_fifo_uf_err_1_u; + +/* Define the union csr_ct_ext_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ct_ext_dealc_rx_fifo_sta : 11; /* [10:0] */ + u32 rsv_131 : 5; /* [15:11] */ + u32 ct_ext_dealc_tx_fifo_sta : 11; /* [26:16] */ + u32 rsv_132 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ct_ext_dealc_fifo_sta_u; + +/* Define the union csr_stf_pcol_num_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_pcol_num_err : 4; /* [3:0] */ + u32 rsv_133 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stf_pcol_num_err_u; + +/* Define the union csr_stfwr_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfwr_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_134 : 7; /* [11:5] */ + u32 stfwr_fifo_mem_err_cerr : 1; /* [12] */ + u32 stfwr_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_135 : 2; /* [15:14] */ + u32 stfwr_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfwr_fifo_ram_err_u; + +/* Define the union csr_stfstr_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfstr_fifo_mem_err_addr : 6; /* [5:0] */ + u32 rsv_136 : 6; /* [11:6] */ + u32 stfstr_fifo_mem_err_cerr : 1; /* [12] */ + u32 stfstr_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_137 : 2; /* [15:14] */ + u32 stfstr_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfstr_fifo_ram_err_u; + +/* Define the union csr_stfrsp_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfrsp_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_138 : 7; /* [11:5] */ + u32 stfrsp_fifo_mem_err_cerr : 1; /* [12] */ + u32 stfrsp_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_139 : 2; /* [15:14] */ + u32 stfrsp_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfrsp_fifo_ram_err_u; + +/* Define the union csr_stfiq_pkt_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_pkt_psh_cnt : 16; /* [15:0] */ + u32 rsv_140 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_pkt_psh_cnt_u; + +/* Define the union csr_stfiq_msg_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_msg_psh_cnt : 16; /* [15:0] */ + u32 rsv_141 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_msg_psh_cnt_u; + +/* Define the union csr_stfiq_col_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_col_psh_cnt : 16; /* [15:0] */ + u32 rsv_142 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_col_psh_cnt_u; + +/* Define the union csr_stfiq_link_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_link_req_cnt : 16; /* [15:0] */ + u32 rsv_143 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_link_req_cnt_u; + +/* Define the union csr_stfiq_psh_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_psh_fifo_sta : 10; /* [9:0] */ + u32 rsv_144 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_psh_fifo_sta_u; + +/* Define the union csr_stfiq_link_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_link_fifo_sta : 10; /* [9:0] */ + u32 rsv_145 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stfiq_link_fifo_sta_u; + +/* Define the union csr_link_wr_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 link_wr_fifo_sta : 10; /* [9:0] */ + u32 rsv_146 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_link_wr_fifo_sta_u; + +/* Define the union csr_ciq_fifo_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_psh_fifo_of_err : 4; /* [3:0] */ + u32 stfiq_psh_fifo_of_err : 4; /* [7:4] */ + u32 stfiq_link_fifo_of_err : 4; /* [11:8] */ + u32 link_wr_fifo_of_err : 1; /* [12] */ + u32 rob_psh_fifo_of_err : 1; /* [13] */ + u32 rsv_147 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ciq_fifo_of_err_u; + +/* Define the union csr_ciq_fifo_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_psh_fifo_uf_err : 4; /* [3:0] */ + u32 stfiq_psh_fifo_uf_err : 4; /* [7:4] */ + u32 stfiq_link_fifo_uf_err : 4; /* [11:8] */ + u32 link_wr_fifo_uf_err : 1; /* [12] */ + u32 rob_psh_fifo_uf_err : 1; /* [13] */ + u32 rsv_148 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ciq_fifo_uf_err_u; + +/* Define the union csr_ciq_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_psh_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_149 : 3; /* [7:5] */ + u32 stfiq_psh_fifo_mem_cerr : 1; /* [8] */ + u32 stfiq_psh_fifo_mem_ucerr : 1; /* [9] */ + u32 rsv_150 : 6; /* [15:10] */ + u32 stfiq_psh_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ciq_ram_err_u; + +/* Define the union csr_ciq_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_col_psh_err : 1; /* [0] */ + u32 rsv_151 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ciq_err_u; + +/* Define the union csr_dat_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_mem_err_addr : 13; /* [12:0] */ + u32 rsv_152 : 1; /* [13] */ + u32 dat_mem_err_cerr : 1; /* [14] */ + u32 dat_mem_err_ucerr : 1; /* [15] */ + u32 dat_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dat_ram_err_u; + +/* Define the union csr_cd_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cd_mem_err_addr : 13; /* [12:0] */ + u32 rsv_153 : 1; /* [13] */ + u32 cd_mem_err_cerr : 1; /* [14] */ + u32 cd_mem_err_ucerr : 1; /* [15] */ + u32 cd_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cd_ram_err_u; + +/* Define the union csr_nptr_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nptr_mem_err_addr : 13; /* [12:0] */ + u32 rsv_154 : 1; /* [13] */ + u32 nptr_mem_err_cerr : 1; /* [14] */ + u32 nptr_mem_err_ucerr : 1; /* [15] */ + u32 nptr_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nptr_ram_err_u; + +/* Define the union csr_ti_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ti_mem_err_addr : 13; /* [12:0] */ + u32 rsv_155 : 1; /* [13] */ + u32 ti_mem_err_cerr : 1; /* [14] */ + u32 ti_mem_err_ucerr : 1; /* [15] */ + u32 ti_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ti_ram_err_u; + +/* Define the union csr_bmp_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmp_mem_err_addr : 8; /* [7:0] */ + u32 bmp_mem_err_cerr : 1; /* [8] */ + u32 bmp_mem_err_ucerr : 1; /* [9] */ + u32 rsv_156 : 6; /* [15:10] */ + u32 bmp_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bmp_ram_err_u; + +/* Define the union csr_age_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 age_mem_err_addr : 8; /* [7:0] */ + u32 age_mem_err_cerr : 1; /* [8] */ + u32 age_mem_err_ucerr : 1; /* [9] */ + u32 rsv_157 : 6; /* [15:10] */ + u32 age_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_age_ram_err_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cpb_fpga_ver_u cpb_fpga_ver; /* 0 */ + volatile csr_cpb_emu_ver_u cpb_emu_ver; /* 4 */ + volatile csr_cpb_bank_row_en_u cpb_bank_row_en; /* C */ + volatile csr_cpb_dat_init_start_u cpb_dat_init_start; /* 10 */ + volatile csr_cpb_cd_init_start_u cpb_cd_init_start; /* 14 */ + volatile csr_cpb_nptr_init_start_u cpb_nptr_init_start; /* 18 */ + volatile csr_cpb_ti_init_start_u cpb_ti_init_start; /* 1C */ + volatile csr_cpb_dat_init_done_u cpb_dat_init_done; /* 20 */ + volatile csr_cpb_cd_init_done_u cpb_cd_init_done; /* 24 */ + volatile csr_cpb_nptr_init_done_u cpb_nptr_init_done; /* 28 */ + volatile csr_cpb_ti_init_done_u cpb_ti_init_done; /* 2C */ + volatile csr_cpb_bmp_init_start_u cpb_bmp_init_start; /* 30 */ + volatile csr_cpb_bmp_init_done_u cpb_bmp_init_done; /* 34 */ + volatile csr_cpb_init_start_u cpb_init_start; /* 38 */ + volatile csr_cpb_init_done_u cpb_init_done; /* 3C */ + volatile csr_cpb_int_vector_u cpb_int_vector; /* 40 */ + volatile csr_cpb_int_u cpb_int; /* 44 */ + volatile csr_cpb_int_en_u cpb_int_en; /* 48 */ + volatile csr_cpb_ram_ucerr_u cpb_ram_ucerr; /* 4C */ + volatile csr_cpb_ram_cerr_u cpb_ram_cerr; /* 50 */ + volatile csr_cpb_fifo_of_err_u cpb_fifo_of_err; /* 54 */ + volatile csr_cpb_fifo_uf_err_u cpb_fifo_uf_err; /* 58 */ + volatile csr_cpb_rx_crdt_err_u cpb_rx_crdt_err; /* 5C */ + volatile csr_cpb_tx_crdt_err_u cpb_tx_crdt_err; /* 60 */ + volatile csr_tx_prealc_crdt_err_u tx_prealc_crdt_err; /* 64 */ + volatile csr_cpb_bp_drop_err_u cpb_bp_drop_err; /* 68 */ + volatile csr_cir_cit_abn_err_u cir_cit_abn_err; /* 6C */ + volatile csr_cpr_cpt_abn_err_u cpr_cpt_abn_err; /* 70 */ + volatile csr_ct_abn_err_u ct_abn_err; /* 74 */ + volatile csr_cq_abn_err_u cq_abn_err; /* 78 */ + volatile csr_rx_tx_abn_err_u rx_tx_abn_err; /* 7C */ + volatile csr_cpb_bmu_rsc_err_u cpb_bmu_rsc_err; /* 80 */ + volatile csr_cpb_aging_err_u cpb_aging_err; /* 84 */ + volatile csr_cpb_fatal_err_en_u cpb_fatal_err_en; /* 90 */ + volatile csr_cpb_fatal_err_sta_u cpb_fatal_err_sta; /* 94 */ + volatile csr_cpb_itf_bp_sta_u cpb_itf_bp_sta; /* A0 */ + volatile csr_cpb_itf_bp_his_u cpb_itf_bp_his; /* A4 */ + volatile csr_cpb_api_err_u cpb_api_err; /* D0 */ + volatile csr_cpb_fifo_err_col_u cpb_fifo_err_col; /* D4 */ + volatile csr_tl_req_invld_u tl_req_invld; /* D8 */ + volatile csr_tl_str_err_0_u tl_str_err_0; /* DC */ + volatile csr_tl_str_err_1_u tl_str_err_1; /* E0 */ + volatile csr_tl_str_err_2_u tl_str_err_2; /* E4 */ + volatile csr_cpb_ram_ctrl_bus_0_u cpb_ram_ctrl_bus_0; /* 100 */ + volatile csr_cpb_ram_ctrl_bus_1_u cpb_ram_ctrl_bus_1; /* 104 */ + volatile csr_cpb_ram_ctrl_bus_2_u cpb_ram_ctrl_bus_2; /* 108 */ + volatile csr_cpb_ram_ctrl_bus_3_u cpb_ram_ctrl_bus_3; /* 10C */ + volatile csr_cpb_ram_ctrl_bus_4_u cpb_ram_ctrl_bus_4; /* 110 */ + volatile csr_cpb_ram_ecc_bypass_u cpb_ram_ecc_bypass; /* 114 */ + volatile csr_cpb_indir_ctrl_u cpb_indir_ctrl; /* 170 */ + volatile csr_cpb_indir_to_th_u cpb_indir_to_th; /* 174 */ + volatile csr_bank_weak_cfg_u bank_weak_cfg; /* 200 */ + volatile csr_bmu_alt_bp_cfg_u bmu_alt_bp_cfg; /* 204 */ + volatile csr_bmu_fat_bp_cfg_u bmu_fat_bp_cfg; /* 208 */ + volatile csr_bmu_ap_acc_wt0_u bmu_ap_acc_wt0; /* 210 */ + volatile csr_bmu_ap_acc_wt1_u bmu_ap_acc_wt1; /* 214 */ + volatile csr_ti_acc_to_th_u ti_acc_to_th; /* 218 */ + volatile csr_bmp_am_th_u bmp_am_th; /* 220 */ + volatile csr_bk_exht_th_u bk_exht_th; /* 224 */ + volatile csr_cell_rd_rls_en_u cell_rd_rls_en; /* 228 */ + volatile csr_cpb_age_cfg_u cpb_age_cfg; /* 258 */ + volatile csr_cpb_age_to_th_u cpb_age_to_th; /* 25C */ + volatile csr_bk_age_cfg_u bk_age_cfg[8]; /* 260 */ + volatile csr_bk_age_bmp_line_u bk_age_bmp_line[8]; /* 280 */ + volatile csr_bk_age_rls_cfg_u bk_age_rls_cfg[8]; /* 2A0 */ + volatile csr_bk_age_find_nxt_u bk_age_find_nxt[8]; /* 2C0 */ + volatile csr_bk_free_rsc_cnt0_u bk_free_rsc_cnt0; /* 300 */ + volatile csr_bk_free_rsc_cnt1_u bk_free_rsc_cnt1; /* 304 */ + volatile csr_bk_free_rsc_cnt2_u bk_free_rsc_cnt2; /* 308 */ + volatile csr_bk_free_rsc_cnt3_u bk_free_rsc_cnt3; /* 30C */ + volatile csr_bk_min_rsc_his_cnt0_u bk_min_rsc_his_cnt0; /* 310 */ + volatile csr_bk_min_rsc_his_cnt1_u bk_min_rsc_his_cnt1; /* 314 */ + volatile csr_bk_min_rsc_his_cnt2_u bk_min_rsc_his_cnt2; /* 318 */ + volatile csr_bk_min_rsc_his_cnt3_u bk_min_rsc_his_cnt3; /* 31C */ + volatile csr_cpb_min_rsc_his_cnt_u cpb_min_rsc_his_cnt; /* 320 */ + volatile csr_bmu_rsc_his_cnt_clr_u bmu_rsc_his_cnt_clr; /* 324 */ + volatile csr_bmu_bp_sta_u bmu_bp_sta; /* 328 */ + volatile csr_row_bmp_sta_u row_bmp_sta[32]; /* 330 */ + volatile csr_age_rls_cnt_0_u age_rls_cnt_0; /* 3B0 */ + volatile csr_age_rls_cnt_1_u age_rls_cnt_1; /* 3B4 */ + volatile csr_age_rls_cnt_2_u age_rls_cnt_2; /* 3B8 */ + volatile csr_age_rls_cnt_3_u age_rls_cnt_3; /* 3BC */ + volatile csr_stf_rsp_api_fifo_crdt_init_u stf_rsp_api_fifo_crdt_init; /* 830 */ + volatile csr_stf_psh_cmd_wt_u stf_psh_cmd_wt; /* 834 */ + volatile csr_stf_col_del_md_hdr_en_u stf_col_del_md_hdr_en; /* 838 */ + volatile csr_stf_rd_req_fifo_af_th_u stf_rd_req_fifo_af_th; /* 83C */ + volatile csr_stf_rd_ctrl_fifo_af_th_u stf_rd_ctrl_fifo_af_th; /* 840 */ + volatile csr_cpb_stf_api_crdt_init_u cpb_stf_api_crdt_init; /* 844 */ + volatile csr_stf_str_di_fifo_af_th_u stf_str_di_fifo_af_th; /* 848 */ + volatile csr_stf_str_api_fifo_af_th_u stf_str_api_fifo_af_th; /* 84C */ + volatile csr_stf_cmd_api_fifo_af_th_u stf_cmd_api_fifo_af_th; /* 850 */ + volatile csr_stf_ackstr_fifo_af_th_u stf_ackstr_fifo_af_th; /* 854 */ + volatile csr_stf_msg_vfid_ctl_u stf_msg_vfid_ctl; /* 860 */ + volatile csr_ct_dma_nret_cfg_u ct_dma_nret_cfg; /* 864 */ + volatile csr_ct_col_src_tag_h_cfg_u ct_col_src_tag_h_cfg; /* 868 */ + volatile csr_ct_dealc_fifo_af_th_u ct_dealc_fifo_af_th; /* 870 */ + volatile csr_stfiq_psh_fifo_cfg_u stfiq_psh_fifo_cfg; /* 910 */ + volatile csr_stfiq_link_fifo_cfg_u stfiq_link_fifo_cfg; /* 920 */ + volatile csr_link_wr_fifo_cfg_u link_wr_fifo_cfg; /* 924 */ + volatile csr_stf_cmd_api_rd_req_fifo_sta_u stf_cmd_api_rd_req_fifo_sta[4]; /* 1500 */ + volatile csr_stf_str_api_fifo_sta_u stf_str_api_fifo_sta[4]; /* 1510 */ + volatile csr_stf_wr_rd_dat_in_fifo_sta_u stf_wr_rd_dat_in_fifo_sta[2]; /* 1520 */ + volatile csr_stf_rsp_api_hdr_dat_fifo_sta_u stf_rsp_api_hdr_dat_fifo_sta[4]; /* 1530 */ + volatile csr_stf_rsp_api_cd_crc_fifo_sta_u stf_rsp_api_cd_crc_fifo_sta[4]; /* 1540 */ + volatile csr_stf_rsp_api_cs_nptr_fifo_sta_u stf_rsp_api_cs_nptr_fifo_sta[4]; /* 1550 */ + volatile csr_stf_str_cmd_cnt_u stf_str_cmd_cnt[4]; /* 1560 */ + volatile csr_stf_ack_rsp_cnt_u stf_ack_rsp_cnt[4]; /* 1570 */ + volatile csr_stf_psh_cnt_u stf_psh_cnt[4]; /* 1580 */ + volatile csr_stf_cell_mdf_cnt_u stf_cell_mdf_cnt[4]; /* 1590 */ + volatile csr_stf_wr_di_ctrl_fifo_sta_u stf_wr_di_ctrl_fifo_sta[2]; /* 15A4 */ + volatile csr_stf_fifo_ov_err_0_u stf_fifo_ov_err_0; /* 15B0 */ + volatile csr_stf_fifo_ov_err_1_u stf_fifo_ov_err_1; /* 15B4 */ + volatile csr_stf_fifo_uf_err_0_u stf_fifo_uf_err_0; /* 15B8 */ + volatile csr_stf_fifo_uf_err_1_u stf_fifo_uf_err_1; /* 15BC */ + volatile csr_ct_ext_dealc_fifo_sta_u ct_ext_dealc_fifo_sta; /* 15C0 */ + volatile csr_stf_pcol_num_err_u stf_pcol_num_err; /* 15C4 */ + volatile csr_stfwr_fifo_ram_err_u stfwr_fifo_ram_err[2]; /* 15D8 */ + volatile csr_stfstr_fifo_ram_err_u stfstr_fifo_ram_err[4]; /* 15E0 */ + volatile csr_stfrsp_fifo_ram_err_u stfrsp_fifo_ram_err[4]; /* 15F0 */ + volatile csr_stfiq_pkt_psh_cnt_u stfiq_pkt_psh_cnt[4]; /* 1620 */ + volatile csr_stfiq_msg_psh_cnt_u stfiq_msg_psh_cnt[4]; /* 1630 */ + volatile csr_stfiq_col_psh_cnt_u stfiq_col_psh_cnt[4]; /* 1640 */ + volatile csr_stfiq_link_req_cnt_u stfiq_link_req_cnt[4]; /* 1650 */ + volatile csr_stfiq_psh_fifo_sta_u stfiq_psh_fifo_sta[4]; /* 1690 */ + volatile csr_stfiq_link_fifo_sta_u stfiq_link_fifo_sta[4]; /* 16A0 */ + volatile csr_link_wr_fifo_sta_u link_wr_fifo_sta; /* 16B0 */ + volatile csr_ciq_fifo_of_err_u ciq_fifo_of_err; /* 16C0 */ + volatile csr_ciq_fifo_uf_err_u ciq_fifo_uf_err; /* 16C4 */ + volatile csr_ciq_ram_err_u ciq_ram_err[4]; /* 16C8 */ + volatile csr_ciq_err_u ciq_err; /* 16E0 */ + volatile csr_dat_ram_err_u dat_ram_err[8]; /* 1BA0 */ + volatile csr_cd_ram_err_u cd_ram_err[8]; /* 1BC0 */ + volatile csr_nptr_ram_err_u nptr_ram_err[8]; /* 1BE0 */ + volatile csr_ti_ram_err_u ti_ram_err[8]; /* 1C00 */ + volatile csr_bmp_ram_err_u bmp_ram_err[8]; /* 1C20 */ + volatile csr_age_ram_err_u age_ram_err[8]; /* 1C40 */ +} S_cpb_csr_0_REGS_TYPE; + +/* Declare the struct pointor of the module cpb_csr_0 */ +extern volatile S_cpb_csr_0_REGS_TYPE *gopcpb_csr_0AllReg; + +/* Declare the functions that set the member value */ +int iSetCPB_FPGA_VER_cpb_fpga_ver(unsigned int ucpb_fpga_ver); +int iSetCPB_EMU_VER_cpb_emu_ver(unsigned int ucpb_emu_ver); +int iSetCPB_BANK_ROW_EN_cpb_bk_row_en(unsigned int ucpb_bk_row_en); +int iSetCPB_DAT_INIT_START_cpb_datmem_init_start(unsigned int ucpb_datmem_init_start); +int iSetCPB_CD_INIT_START_cpb_cdmem_init_start(unsigned int ucpb_cdmem_init_start); +int iSetCPB_NPTR_INIT_START_cpb_nptrmem_init_start(unsigned int ucpb_nptrmem_init_start); +int iSetCPB_TI_INIT_START_cpb_timem_init_start(unsigned int ucpb_timem_init_start); +int iSetCPB_DAT_INIT_DONE_cpb_datmem_init_done(unsigned int ucpb_datmem_init_done); +int iSetCPB_CD_INIT_DONE_cpb_cdmem_init_done(unsigned int ucpb_cdmem_init_done); +int iSetCPB_NPTR_INIT_DONE_cpb_nptrmem_init_done(unsigned int ucpb_nptrmem_init_done); +int iSetCPB_TI_INIT_DONE_cpb_timem_init_done(unsigned int ucpb_timem_init_done); +int iSetCPB_BMP_INIT_START_cpb_bmp_init_start(unsigned int ucpb_bmp_init_start); +int iSetCPB_BMP_INIT_DONE_cpb_bmp_init_done(unsigned int ucpb_bmp_init_done); +int iSetCPB_INIT_START_fpa_init_start(unsigned int ufpa_init_start); +int iSetCPB_INIT_START_tso_ctxm_init_start(unsigned int utso_ctxm_init_start); +int iSetCPB_INIT_START_tx_port_fp_init_start(unsigned int utx_port_fp_init_start); +int iSetCPB_INIT_START_rxlb_fp_init_start(unsigned int urxlb_fp_init_start); +int iSetCPB_INIT_DONE_cpb_init_done(unsigned int ucpb_init_done); +int iSetCPB_INIT_DONE_fpa_init_done(unsigned int ufpa_init_done); +int iSetCPB_INIT_DONE_tso_ctxm_init_done(unsigned int utso_ctxm_init_done); +int iSetCPB_INIT_DONE_tx_port_fp_init_done(unsigned int utx_port_fp_init_done); +int iSetCPB_INIT_DONE_rxlb_fp_init_done(unsigned int urxlb_fp_init_done); +int iSetCPB_INT_VECTOR_cpb_cpi_int_index(unsigned int ucpb_cpi_int_index); +int iSetCPB_INT_VECTOR_cpb_int_enable(unsigned int ucpb_int_enable); +int iSetCPB_INT_VECTOR_cpb_int_issue(unsigned int ucpb_int_issue); +int iSetCPB_INT_cpb_int_data(unsigned int ucpb_int_data); +int iSetCPB_INT_cpb_program_csr_id_ro(unsigned int ucpb_program_csr_id_ro); +int iSetCPB_INT_EN_cpb_int_en(unsigned int ucpb_int_en); +int iSetCPB_INT_EN_cpb_program_csr_id(unsigned int ucpb_program_csr_id); +int iSetCPB_RAM_UCERR_cpb_ram_ucerr(unsigned int ucpb_ram_ucerr); +int iSetCPB_RAM_UCERR_cpb_ram_ucerr_inj(unsigned int ucpb_ram_ucerr_inj); +int iSetCPB_RAM_UCERR_cpb_ram_ucerr_stickey(unsigned int ucpb_ram_ucerr_stickey); +int iSetCPB_RAM_CERR_cpb_ram_cerr(unsigned int ucpb_ram_cerr); +int iSetCPB_RAM_CERR_cpb_ram_cerr_inj(unsigned int ucpb_ram_cerr_inj); +int iSetCPB_RAM_CERR_cpb_ram_cerr_stickey(unsigned int ucpb_ram_cerr_stickey); +int iSetCPB_FIFO_OF_ERR_cpb_fifo_of_err(unsigned int ucpb_fifo_of_err); +int iSetCPB_FIFO_OF_ERR_cpb_fifo_of_err_inj(unsigned int ucpb_fifo_of_err_inj); +int iSetCPB_FIFO_OF_ERR_cpb_fifo_of_err_stickey(unsigned int ucpb_fifo_of_err_stickey); +int iSetCPB_FIFO_UF_ERR_cpb_fifo_uf_err(unsigned int ucpb_fifo_uf_err); +int iSetCPB_FIFO_UF_ERR_cpb_fifo_uf_err_inj(unsigned int ucpb_fifo_uf_err_inj); +int iSetCPB_FIFO_UF_ERR_cpb_fifo_uf_err_stickey(unsigned int ucpb_fifo_uf_err_stickey); +int iSetCPB_RX_CRDT_ERR_cpb_rx_crdt_of_err(unsigned int ucpb_rx_crdt_of_err); +int iSetCPB_RX_CRDT_ERR_cpb_rx_crdt_uf_err(unsigned int ucpb_rx_crdt_uf_err); +int iSetCPB_RX_CRDT_ERR_sge_zero_err(unsigned int usge_zero_err); +int iSetCPB_RX_CRDT_ERR_cpb_rx_crdt_of_err_inj(unsigned int ucpb_rx_crdt_of_err_inj); +int iSetCPB_RX_CRDT_ERR_cpb_rx_crdt_uf_err_inj(unsigned int ucpb_rx_crdt_uf_err_inj); +int iSetCPB_RX_CRDT_ERR_sge_zero_err_inj(unsigned int usge_zero_err_inj); +int iSetCPB_RX_CRDT_ERR_cpb_rx_crdt_err_stickey(unsigned int ucpb_rx_crdt_err_stickey); +int iSetCPB_TX_CRDT_ERR_cpb_tx_crdt_of_err(unsigned int ucpb_tx_crdt_of_err); +int iSetCPB_TX_CRDT_ERR_cpb_tx_crdt_uf_err(unsigned int ucpb_tx_crdt_uf_err); +int iSetCPB_TX_CRDT_ERR_cpb_tx_crdt_of_err_inj(unsigned int ucpb_tx_crdt_of_err_inj); +int iSetCPB_TX_CRDT_ERR_cpb_tx_crdt_uf_err_inj(unsigned int ucpb_tx_crdt_uf_err_inj); +int iSetCPB_TX_CRDT_ERR_cpb_tx_crdt_err_stickey(unsigned int ucpb_tx_crdt_err_stickey); +int iSetTX_PREALC_CRDT_ERR_tx_prealc_crdt_err(unsigned int utx_prealc_crdt_err); +int iSetTX_PREALC_CRDT_ERR_tx_prealc_crdt_err_inj(unsigned int utx_prealc_crdt_err_inj); +int iSetTX_PREALC_CRDT_ERR_tx_prealc_crdt_err_stickey(unsigned int utx_prealc_crdt_err_stickey); +int iSetCPB_BP_DROP_ERR_cpb_bp_drop_err(unsigned int ucpb_bp_drop_err); +int iSetCPB_BP_DROP_ERR_cpb_bp_drop_err_inj(unsigned int ucpb_bp_drop_err_inj); +int iSetCPB_BP_DROP_ERR_cpb_bp_drop_err_stickey(unsigned int ucpb_bp_drop_err_stickey); +int iSetCIR_CIT_ABN_ERR_cir_abn_err(unsigned int ucir_abn_err); +int iSetCIR_CIT_ABN_ERR_cit_abn_err(unsigned int ucit_abn_err); +int iSetCIR_CIT_ABN_ERR_cir_abn_err_inj(unsigned int ucir_abn_err_inj); +int iSetCIR_CIT_ABN_ERR_cit_abn_err_inj(unsigned int ucit_abn_err_inj); +int iSetCIR_CIT_ABN_ERR_cir_cit_abn_err_stickey(unsigned int ucir_cit_abn_err_stickey); +int iSetCPR_CPT_ABN_ERR_cpr_abn_err(unsigned int ucpr_abn_err); +int iSetCPR_CPT_ABN_ERR_cpt_abn_err(unsigned int ucpt_abn_err); +int iSetCPR_CPT_ABN_ERR_cpr_abn_err_inj(unsigned int ucpr_abn_err_inj); +int iSetCPR_CPT_ABN_ERR_cpt_abn_err_inj(unsigned int ucpt_abn_err_inj); +int iSetCPR_CPT_ABN_ERR_cpr_cpt_abn_err_stickey(unsigned int ucpr_cpt_abn_err_stickey); +int iSetCT_ABN_ERR_cstl_abn_err(unsigned int ucstl_abn_err); +int iSetCT_ABN_ERR_cstf_abn_err(unsigned int ucstf_abn_err); +int iSetCT_ABN_ERR_cstl_abn_err_inj(unsigned int ucstl_abn_err_inj); +int iSetCT_ABN_ERR_cstf_abn_err_inj(unsigned int ucstf_abn_err_inj); +int iSetCT_ABN_ERR_ct_abn_err_stickey(unsigned int uct_abn_err_stickey); +int iSetCQ_ABN_ERR_ciq_abn_err(unsigned int uciq_abn_err); +int iSetCQ_ABN_ERR_coq_abn_err(unsigned int ucoq_abn_err); +int iSetCQ_ABN_ERR_ciq_abn_err_inj(unsigned int uciq_abn_err_inj); +int iSetCQ_ABN_ERR_coq_abn_err_inj(unsigned int ucoq_abn_err_inj); +int iSetCQ_ABN_ERR_cq_abn_err_stickey(unsigned int ucq_abn_err_stickey); +int iSetRX_TX_ABN_ERR_cpb_rx_abn_err(unsigned int ucpb_rx_abn_err); +int iSetRX_TX_ABN_ERR_cpb_tx_abn_err(unsigned int ucpb_tx_abn_err); +int iSetRX_TX_ABN_ERR_cpb_rx_abn_err_inj(unsigned int ucpb_rx_abn_err_inj); +int iSetRX_TX_ABN_ERR_cpb_tx_abn_err_inj(unsigned int ucpb_tx_abn_err_inj); +int iSetRX_TX_ABN_ERR_rx_tx_abn_err_stickey(unsigned int urx_tx_abn_err_stickey); +int iSetCPB_BMU_RSC_ERR_cpb_bmu_err(unsigned int ucpb_bmu_err); +int iSetCPB_BMU_RSC_ERR_cpb_bmu_err_inj(unsigned int ucpb_bmu_err_inj); +int iSetCPB_BMU_RSC_ERR_cpb_bmu_err_stickey(unsigned int ucpb_bmu_err_stickey); +int iSetCPB_AGING_ERR_cpb_aging_err(unsigned int ucpb_aging_err); +int iSetCPB_AGING_ERR_cpb_aging_err_inj(unsigned int ucpb_aging_err_inj); +int iSetCPB_AGING_ERR_cpb_aging_err_stickey(unsigned int ucpb_aging_err_stickey); +int iSetCPB_FATAL_ERR_EN_cpb_ram_ucerr_fatal_en(unsigned int ucpb_ram_ucerr_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_fifo_of_fatal_en(unsigned int ucpb_fifo_of_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_fifo_uf_fatal_en(unsigned int ucpb_fifo_uf_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_rx_crdt_err_fatal_en(unsigned int ucpb_rx_crdt_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_tx_crdt_err_fatal_en(unsigned int ucpb_tx_crdt_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_ipsu_itf_err_fatal_en(unsigned int ucpb_ipsu_itf_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_pe_itf_err_fatal_en(unsigned int ucpb_pe_itf_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_tile_itf_err_fatal_en(unsigned int ucpb_tile_itf_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_qu_itf_err_fatal_en(unsigned int ucpb_qu_itf_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_rxtx_itf_err_fatal_en(unsigned int ucpb_rxtx_itf_err_fatal_en); +int iSetCPB_FATAL_ERR_EN_cpb_bmp_err_fatal_en(unsigned int ucpb_bmp_err_fatal_en); +int iSetCPB_FATAL_ERR_STA_cpb_ram_ucerr_fatal_sta(unsigned int ucpb_ram_ucerr_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_fifo_of_fatal_sta(unsigned int ucpb_fifo_of_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_fifo_uf_fatal_sta(unsigned int ucpb_fifo_uf_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_rx_crdt_err_fatal_sta(unsigned int ucpb_rx_crdt_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_tx_crdt_err_fatal_sta(unsigned int ucpb_tx_crdt_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_ipsu_itf_err_fatal_sta(unsigned int ucpb_ipsu_itf_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_pe_itf_err_fatal_sta(unsigned int ucpb_pe_itf_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_tile_itf_err_fatal_sta(unsigned int ucpb_tile_itf_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_qu_itf_err_fatal_sta(unsigned int ucpb_qu_itf_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_rxtx_itf_err_fatal_sta(unsigned int ucpb_rxtx_itf_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_bmp_err_fatal_sta(unsigned int ucpb_bmp_err_fatal_sta); +int iSetCPB_FATAL_ERR_STA_cpb_ram_ucerr_fatal_clr(unsigned int ucpb_ram_ucerr_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_fifo_of_fatal_clr(unsigned int ucpb_fifo_of_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_fifo_uf_fatal_clr(unsigned int ucpb_fifo_uf_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_rx_crdt_err_fatal_clr(unsigned int ucpb_rx_crdt_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_tx_crdt_err_fatal_clr(unsigned int ucpb_tx_crdt_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_ipsu_itf_err_fatal_clr(unsigned int ucpb_ipsu_itf_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_pe_itf_err_fatal_clr(unsigned int ucpb_pe_itf_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_tile_itf_err_fatal_clr(unsigned int ucpb_tile_itf_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_qu_itf_err_fatal_clr(unsigned int ucpb_qu_itf_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_rxtx_itf_err_fatal_clr(unsigned int ucpb_rxtx_itf_err_fatal_clr); +int iSetCPB_FATAL_ERR_STA_cpb_bmp_err_fatal_clr(unsigned int ucpb_bmp_err_fatal_clr); +int iSetCPB_ITF_BP_STA_cpb_ipsurx_bp_sta(unsigned int ucpb_ipsurx_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_ipsutx_bp_sta(unsigned int ucpb_ipsutx_bp_sta); +int iSetCPB_ITF_BP_STA_iq_cpb_rx_bp_sta(unsigned int uiq_cpb_rx_bp_sta); +int iSetCPB_ITF_BP_STA_iq_cpb_tx_bp_sta(unsigned int uiq_cpb_tx_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_stliq_req_bp_sta(unsigned int ucpb_stliq_req_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_stfiq_req_bp_sta(unsigned int ucpb_stfiq_req_bp_sta); +int iSetCPB_ITF_BP_STA_stlfq_cpb_ackstr_bp_sta(unsigned int ustlfq_cpb_ackstr_bp_sta); +int iSetCPB_ITF_BP_STA_stffq_cpb_ackstr_bp_sta(unsigned int ustffq_cpb_ackstr_bp_sta); +int iSetCPB_ITF_BP_STA_prm_cpb_alloc_rx_bp_sta(unsigned int uprm_cpb_alloc_rx_bp_sta); +int iSetCPB_ITF_BP_STA_prm_cpb_alloc_tx_bp_sta(unsigned int uprm_cpb_alloc_tx_bp_sta); +int iSetCPB_ITF_BP_STA_prm_cpb_dealloc_rx_bp_sta(unsigned int uprm_cpb_dealloc_rx_bp_sta); +int iSetCPB_ITF_BP_STA_prm_cpb_dealloc_tx_bp_sta(unsigned int uprm_cpb_dealloc_tx_bp_sta); +int iSetCPB_ITF_BP_STA_prm_cpb_prls_bp_sta(unsigned int uprm_cpb_prls_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_oq_rx_bp_sta(unsigned int ucpb_oq_rx_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_oq_tx_bp_sta(unsigned int ucpb_oq_tx_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_oq_drp_bp_sta(unsigned int ucpb_oq_drp_bp_sta); +int iSetCPB_ITF_BP_STA_cpb_pqm_host_bp_sta(unsigned int ucpb_pqm_host_bp_sta); +int iSetCPB_ITF_BP_STA_rx_prm_bp_sta(unsigned int urx_prm_bp_sta); +int iSetCPB_ITF_BP_STA_tx_mag_bp_sta(unsigned int utx_mag_bp_sta); +int iSetCPB_ITF_BP_STA_rx_crdt_bp_sta(unsigned int urx_crdt_bp_sta); +int iSetCPB_ITF_BP_STA_tx_crdt_bp_sta(unsigned int utx_crdt_bp_sta); +int iSetCPB_ITF_BP_HIS_cpb_ipsurx_bp_his(unsigned int ucpb_ipsurx_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_ipsutx_bp_his(unsigned int ucpb_ipsutx_bp_his); +int iSetCPB_ITF_BP_HIS_iq_cpb_rx_bp_his(unsigned int uiq_cpb_rx_bp_his); +int iSetCPB_ITF_BP_HIS_iq_cpb_tx_bp_his(unsigned int uiq_cpb_tx_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_stliq_req_bp_his(unsigned int ucpb_stliq_req_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_stfiq_req_bp_his(unsigned int ucpb_stfiq_req_bp_his); +int iSetCPB_ITF_BP_HIS_stlfq_cpb_ackstr_bp_his(unsigned int ustlfq_cpb_ackstr_bp_his); +int iSetCPB_ITF_BP_HIS_stffq_cpb_ackstr_bp_his(unsigned int ustffq_cpb_ackstr_bp_his); +int iSetCPB_ITF_BP_HIS_prm_cpb_alloc_rx_bp_his(unsigned int uprm_cpb_alloc_rx_bp_his); +int iSetCPB_ITF_BP_HIS_prm_cpb_alloc_tx_bp_his(unsigned int uprm_cpb_alloc_tx_bp_his); +int iSetCPB_ITF_BP_HIS_prm_cpb_dealloc_rx_bp_his(unsigned int uprm_cpb_dealloc_rx_bp_his); +int iSetCPB_ITF_BP_HIS_prm_cpb_dealloc_tx_bp_his(unsigned int uprm_cpb_dealloc_tx_bp_his); +int iSetCPB_ITF_BP_HIS_prm_cpb_prls_bp_his(unsigned int uprm_cpb_prls_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_oq_rx_bp_his(unsigned int ucpb_oq_rx_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_oq_tx_bp_his(unsigned int ucpb_oq_tx_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_oq_drp_bp_his(unsigned int ucpb_oq_drp_bp_his); +int iSetCPB_ITF_BP_HIS_cpb_pqm_host_bp_his(unsigned int ucpb_pqm_host_bp_his); +int iSetCPB_ITF_BP_HIS_rx_prm_bp_his(unsigned int urx_prm_bp_his); +int iSetCPB_ITF_BP_HIS_tx_mag_bp_his(unsigned int utx_mag_bp_his); +int iSetCPB_ITF_BP_HIS_rx_crdt_bp_his(unsigned int urx_crdt_bp_his); +int iSetCPB_ITF_BP_HIS_tx_crdt_bp_his(unsigned int utx_crdt_bp_his); +int iSetCPB_API_ERR_cpb_api_err(unsigned int ucpb_api_err); +int iSetCPB_FIFO_ERR_COL_stf_fifo_uf_col(unsigned int ustf_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_stl_fifo_uf_col(unsigned int ustl_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_cpt_fifo_uf_col(unsigned int ucpt_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_cpr_fifo_uf_col(unsigned int ucpr_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_cit_fifo_uf_col(unsigned int ucit_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_cir_fifo_uf_col(unsigned int ucir_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_ct_ext_dealc_rx_fifo_uf(unsigned int uct_ext_dealc_rx_fifo_uf); +int iSetCPB_FIFO_ERR_COL_ct_ext_dealc_tx_fifo_uf(unsigned int uct_ext_dealc_tx_fifo_uf); +int iSetCPB_FIFO_ERR_COL_ciq_fifo_uf_col(unsigned int uciq_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_coq_fifo_uf_col(unsigned int ucoq_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_crx_fifo_uf_col(unsigned int ucrx_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_ctx_fifo_uf_col(unsigned int uctx_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_cdt_fifo_uf_col(unsigned int ucdt_fifo_uf_col); +int iSetCPB_FIFO_ERR_COL_stf_fifo_ov_col(unsigned int ustf_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_stl_fifo_ov_col(unsigned int ustl_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_cpt_fifo_ov_col(unsigned int ucpt_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_cpr_fifo_ov_col(unsigned int ucpr_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_cit_fifo_ov_col(unsigned int ucit_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_cir_fifo_ov_col(unsigned int ucir_fifo_ov_col); +int iSetCPB_FIFO_ERR_COL_ct_ext_dealc_rx_fifo_ov(unsigned int uct_ext_dealc_rx_fifo_ov); +int iSetCPB_FIFO_ERR_COL_ct_ext_dealc_tx_fifo_ov(unsigned int uct_ext_dealc_tx_fifo_ov); +int iSetCPB_FIFO_ERR_COL_ciq_fifo_of_col(unsigned int uciq_fifo_of_col); +int iSetCPB_FIFO_ERR_COL_coq_fifo_of_col(unsigned int ucoq_fifo_of_col); +int iSetCPB_FIFO_ERR_COL_crx_fifo_of_col(unsigned int ucrx_fifo_of_col); +int iSetCPB_FIFO_ERR_COL_ctx_fifo_of_col(unsigned int uctx_fifo_of_col); +int iSetCPB_FIFO_ERR_COL_cdt_fifo_of_col(unsigned int ucdt_fifo_of_col); +int iSetTL_REQ_INVLD_stl_iq_push_len_err(unsigned int ustl_iq_push_len_err); +int iSetTL_REQ_INVLD_stf_iq_push_len_err(unsigned int ustf_iq_push_len_err); +int iSetTL_REQ_INVLD_stl_cmd_crc_len_err(unsigned int ustl_cmd_crc_len_err); +int iSetTL_REQ_INVLD_stf_cmd_crc_len_err(unsigned int ustf_cmd_crc_len_err); +int iSetTL_REQ_INVLD_stl_cmd_rd_link_err(unsigned int ustl_cmd_rd_link_err); +int iSetTL_REQ_INVLD_stf_cmd_rd_link_err(unsigned int ustf_cmd_rd_link_err); +int iSetTL_REQ_INVLD_stf_psh_len_lt_tp_lho(unsigned int ustf_psh_len_lt_tp_lho); +int iSetTL_STR_ERR_0_stl_str_pe_cmd_len_err(unsigned int ustl_str_pe_cmd_len_err); +int iSetTL_STR_ERR_0_stf_str_pe_cmd_len_err(unsigned int ustf_str_pe_cmd_len_err); +int iSetTL_STR_ERR_0_stl_str_cm_len_err(unsigned int ustl_str_cm_len_err); +int iSetTL_STR_ERR_0_stf_str_cm_len_err(unsigned int ustf_str_cm_len_err); +int iSetTL_STR_ERR_0_stl_str_ext_len_err(unsigned int ustl_str_ext_len_err); +int iSetTL_STR_ERR_0_stf_str_ext_len_err(unsigned int ustf_str_ext_len_err); +int iSetTL_STR_ERR_0_stl_str_ov_len_err(unsigned int ustl_str_ov_len_err); +int iSetTL_STR_ERR_0_stf_str_ov_len_err(unsigned int ustf_str_ov_len_err); +int iSetTL_STR_ERR_1_stl_str_mio_len_err(unsigned int ustl_str_mio_len_err); +int iSetTL_STR_ERR_1_stf_str_mio_len_err(unsigned int ustf_str_mio_len_err); +int iSetTL_STR_ERR_1_stl_str_pld_len_err(unsigned int ustl_str_pld_len_err); +int iSetTL_STR_ERR_1_stf_str_pld_len_err(unsigned int ustf_str_pld_len_err); +int iSetTL_STR_ERR_1_stl_str_ext_omd_len_err(unsigned int ustl_str_ext_omd_len_err); +int iSetTL_STR_ERR_1_stf_str_ext_omd_len_err(unsigned int ustf_str_ext_omd_len_err); +int iSetTL_STR_ERR_1_stl_str_mc_cmd_num_err(unsigned int ustl_str_mc_cmd_num_err); +int iSetTL_STR_ERR_1_stf_str_mc_cmd_num_err(unsigned int ustf_str_mc_cmd_num_err); +int iSetTL_STR_ERR_2_stl_str_cmd_len_err(unsigned int ustl_str_cmd_len_err); +int iSetTL_STR_ERR_2_stf_str_cmd_len_err(unsigned int ustf_str_cmd_len_err); +int iSetTL_STR_ERR_2_stl_str_para_cmd_cnum_err(unsigned int ustl_str_para_cmd_cnum_err); +int iSetTL_STR_ERR_2_stf_str_para_cmd_cnum_err(unsigned int ustf_str_para_cmd_cnum_err); +int iSetCPB_RAM_CTRL_BUS_0_cpb_ram_ctrl_bus_0(unsigned int ucpb_ram_ctrl_bus_0); +int iSetCPB_RAM_CTRL_BUS_1_cpb_ram_ctrl_bus_1(unsigned int ucpb_ram_ctrl_bus_1); +int iSetCPB_RAM_CTRL_BUS_2_cpb_ram_ctrl_bus_2(unsigned int ucpb_ram_ctrl_bus_2); +int iSetCPB_RAM_CTRL_BUS_3_cpb_ram_ctrl_bus_3(unsigned int ucpb_ram_ctrl_bus_3); +int iSetCPB_RAM_CTRL_BUS_4_cpb_ram_ctrl_bus_4(unsigned int ucpb_ram_ctrl_bus_4); +int iSetCPB_RAM_ECC_BYPASS_cpb_ram_ecc_bypass(unsigned int ucpb_ram_ecc_bypass); +int iSetCPB_INDIR_CTRL_cpb_indir_addr(unsigned int ucpb_indir_addr); +int iSetCPB_INDIR_CTRL_cpb_indir_tab(unsigned int ucpb_indir_tab); +int iSetCPB_INDIR_CTRL_cpb_indir_state(unsigned int ucpb_indir_state); +int iSetCPB_INDIR_CTRL_cpb_indir_mode(unsigned int ucpb_indir_mode); +int iSetCPB_INDIR_CTRL_cpb_indir_vld(unsigned int ucpb_indir_vld); +int iSetCPB_INDIR_TO_TH_cpb_indir_to_th(unsigned int ucpb_indir_to_th); +int iSetBANK_WEAK_CFG_bk_weak_en(unsigned int ubk_weak_en); +int iSetBANK_WEAK_CFG_weak_diff_th(unsigned int uweak_diff_th); +int iSetBANK_WEAK_CFG_weak_low_th(unsigned int uweak_low_th); +int iSetBMU_ALT_BP_CFG_bmu_alt_bp_on_th(unsigned int ubmu_alt_bp_on_th); +int iSetBMU_ALT_BP_CFG_bmu_alt_bp_off_th(unsigned int ubmu_alt_bp_off_th); +int iSetBMU_FAT_BP_CFG_bmu_fatal_bp_on_th(unsigned int ubmu_fatal_bp_on_th); +int iSetBMU_FAT_BP_CFG_bmu_fatal_bp_off_th(unsigned int ubmu_fatal_bp_off_th); +int iSetBMU_FAT_BP_CFG_ct_fatal_bp_en(unsigned int uct_fatal_bp_en); +int iSetBMU_AP_ACC_WT0_ap_acc_wt0(unsigned int uap_acc_wt0); +int iSetBMU_AP_ACC_WT0_ap_acc_wt1(unsigned int uap_acc_wt1); +int iSetBMU_AP_ACC_WT0_ap_acc_wt2(unsigned int uap_acc_wt2); +int iSetBMU_AP_ACC_WT0_ap_acc_wt3(unsigned int uap_acc_wt3); +int iSetBMU_AP_ACC_WT0_ap_acc_wt4(unsigned int uap_acc_wt4); +int iSetBMU_AP_ACC_WT0_ap_acc_wt5(unsigned int uap_acc_wt5); +int iSetBMU_AP_ACC_WT0_ap_acc_wt6(unsigned int uap_acc_wt6); +int iSetBMU_AP_ACC_WT0_ap_acc_wt7(unsigned int uap_acc_wt7); +int iSetBMU_AP_ACC_WT1_ap_acc_wt8(unsigned int uap_acc_wt8); +int iSetBMU_AP_ACC_WT1_ap_acc_wt9(unsigned int uap_acc_wt9); +int iSetBMU_AP_ACC_WT1_ap_acc_wt10(unsigned int uap_acc_wt10); +int iSetBMU_AP_ACC_WT1_ap_acc_wt11(unsigned int uap_acc_wt11); +int iSetBMU_AP_ACC_WT1_ap_acc_wt12(unsigned int uap_acc_wt12); +int iSetBMU_AP_ACC_WT1_ap_acc_wt13(unsigned int uap_acc_wt13); +int iSetBMU_AP_ACC_WT1_ap_acc_wt14(unsigned int uap_acc_wt14); +int iSetTI_ACC_TO_TH_ti_nm_rreq_to_th0(unsigned int uti_nm_rreq_to_th0); +int iSetTI_ACC_TO_TH_ti_nm_rreq_to_th1(unsigned int uti_nm_rreq_to_th1); +int iSetTI_ACC_TO_TH_ti_nm_rreq_to_th2(unsigned int uti_nm_rreq_to_th2); +int iSetBMP_AM_TH_bmp_aempty_th(unsigned int ubmp_aempty_th); +int iSetBK_EXHT_TH_bk_exht_th(unsigned int ubk_exht_th); +int iSetCELL_RD_RLS_EN_cell_rd_rls_en(unsigned int ucell_rd_rls_en); +int iSetCPB_AGE_CFG_cpb_timer_unit_th(unsigned int ucpb_timer_unit_th); +int iSetCPB_AGE_CFG_age_auto_rls_en(unsigned int uage_auto_rls_en); +int iSetCPB_AGE_CFG_cpb_age_en(unsigned int ucpb_age_en); +int iSetCPB_AGE_TO_TH_cpb_age_to_th(unsigned int ucpb_age_to_th); +int iSetBK_AGE_CFG_bk_age_bmp_addr(unsigned int ubk_age_bmp_addr); +int iSetBK_AGE_CFG_bk_age_addr_found(unsigned int ubk_age_addr_found); +int iSetBK_AGE_CFG_bk_cur_age_st(unsigned int ubk_cur_age_st); +int iSetBK_AGE_CFG_bk_age_scan_busy(unsigned int ubk_age_scan_busy); +int iSetBK_AGE_CFG_bk_age_scan_req(unsigned int ubk_age_scan_req); +int iSetBK_AGE_BMP_LINE_bk_age_bmp_line(unsigned int ubk_age_bmp_line); +int iSetBK_AGE_RLS_CFG_bk_age_rls_addr(unsigned int ubk_age_rls_addr); +int iSetBK_AGE_RLS_CFG_bk_age_rls_req(unsigned int ubk_age_rls_req); +int iSetBK_AGE_FIND_NXT_bk_age_find_nxt(unsigned int ubk_age_find_nxt); +int iSetBK_FREE_RSC_CNT0_bk0_free_rsc_cnt(unsigned int ubk0_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT0_bk1_free_rsc_cnt(unsigned int ubk1_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT1_bk2_free_rsc_cnt(unsigned int ubk2_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT1_bk3_free_rsc_cnt(unsigned int ubk3_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT2_bk4_free_rsc_cnt(unsigned int ubk4_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT2_bk5_free_rsc_cnt(unsigned int ubk5_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT3_bk6_free_rsc_cnt(unsigned int ubk6_free_rsc_cnt); +int iSetBK_FREE_RSC_CNT3_bk7_free_rsc_cnt(unsigned int ubk7_free_rsc_cnt); +int iSetBK_MIN_RSC_HIS_CNT0_bk0_min_rsc_his_cnt(unsigned int ubk0_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT0_bk1_min_rsc_his_cnt(unsigned int ubk1_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT1_bk2_min_rsc_his_cnt(unsigned int ubk2_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT1_bk3_min_rsc_his_cnt(unsigned int ubk3_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT2_bk4_min_rsc_his_cnt(unsigned int ubk4_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT2_bk5_min_rsc_his_cnt(unsigned int ubk5_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT3_bk6_min_rsc_his_cnt(unsigned int ubk6_min_rsc_his_cnt); +int iSetBK_MIN_RSC_HIS_CNT3_bk7_min_rsc_his_cnt(unsigned int ubk7_min_rsc_his_cnt); +int iSetCPB_MIN_RSC_HIS_CNT_cpb_min_rsc_his_cnt(unsigned int ucpb_min_rsc_his_cnt); +int iSetBMU_RSC_HIS_CNT_CLR_bk_min_rsc_his_cnt_clr(unsigned int ubk_min_rsc_his_cnt_clr); +int iSetBMU_RSC_HIS_CNT_CLR_cpb_min_rsc_his_cnt_clr(unsigned int ucpb_min_rsc_his_cnt_clr); +int iSetBMU_BP_STA_bmu_alt_bp(unsigned int ubmu_alt_bp); +int iSetBMU_BP_STA_bmu_fatal_bp(unsigned int ubmu_fatal_bp); +int iSetBMU_BP_STA_bk_weak_bp(unsigned int ubk_weak_bp); +int iSetBMU_BP_STA_bmu_alt_bp_his(unsigned int ubmu_alt_bp_his); +int iSetBMU_BP_STA_bmu_fatal_bp_his(unsigned int ubmu_fatal_bp_his); +int iSetBMU_BP_STA_bk_weak_bp_his(unsigned int ubk_weak_bp_his); +int iSetROW_BMP_STA_row_bmp_free_rsc_cnt(unsigned int urow_bmp_free_rsc_cnt); +int iSetROW_BMP_STA_row_bmp_aempty(unsigned int urow_bmp_aempty); +int iSetROW_BMP_STA_row_bmp_empty(unsigned int urow_bmp_empty); +int iSetROW_BMP_STA_row_bmp_aempty_his(unsigned int urow_bmp_aempty_his); +int iSetROW_BMP_STA_row_bmp_empty_his(unsigned int urow_bmp_empty_his); +int iSetROW_BMP_STA_row_bmp_refrain_err_his(unsigned int urow_bmp_refrain_err_his); +int iSetROW_BMP_STA_row_bmp_leak_err_his(unsigned int urow_bmp_leak_err_his); +int iSetAGE_RLS_CNT_0_bk_age_rls_cnt0(unsigned int ubk_age_rls_cnt0); +int iSetAGE_RLS_CNT_0_bk_age_rls_cnt1(unsigned int ubk_age_rls_cnt1); +int iSetAGE_RLS_CNT_1_bk_age_rls_cnt2(unsigned int ubk_age_rls_cnt2); +int iSetAGE_RLS_CNT_1_bk_age_rls_cnt3(unsigned int ubk_age_rls_cnt3); +int iSetAGE_RLS_CNT_2_bk_age_rls_cnt4(unsigned int ubk_age_rls_cnt4); +int iSetAGE_RLS_CNT_2_bk_age_rls_cnt5(unsigned int ubk_age_rls_cnt5); +int iSetAGE_RLS_CNT_3_bk_age_rls_cnt6(unsigned int ubk_age_rls_cnt6); +int iSetAGE_RLS_CNT_3_bk_age_rls_cnt7(unsigned int ubk_age_rls_cnt7); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_rsp_npt_fifo_crdt(unsigned int ustf_rsp_npt_fifo_crdt); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_rsp_dat_fifo_crdt(unsigned int ustf_rsp_dat_fifo_crdt); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_rsp_api_hdr_fifo_crdt(unsigned int ustf_rsp_api_hdr_fifo_crdt); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_rsp_crc_fifo_crdt(unsigned int ustf_rsp_crc_fifo_crdt); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_rsp_api_fifo_crdt_init(unsigned int ustf_rsp_api_fifo_crdt_init); +int iSetSTF_RSP_API_FIFO_CRDT_INIT_stf_str_rsp_hdr_crdt(unsigned int ustf_str_rsp_hdr_crdt); +int iSetSTF_PSH_CMD_WT_stf_cmd_req_wt(unsigned int ustf_cmd_req_wt); +int iSetSTF_PSH_CMD_WT_stf_psh_req_wt(unsigned int ustf_psh_req_wt); +int iSetSTF_COL_DEL_MD_HDR_EN_stf_col_del_md_hdr_en(unsigned int ustf_col_del_md_hdr_en); +int iSetSTF_RD_REQ_FIFO_AF_TH_stf_rd_req_fifo_af_th(unsigned int ustf_rd_req_fifo_af_th); +int iSetSTF_RD_CTRL_FIFO_AF_TH_stf_rd_ctrl_fifo_af_th(unsigned int ustf_rd_ctrl_fifo_af_th); +int iSetCPB_STF_API_CRDT_INIT_cpb_stf_api_crdt(unsigned int ucpb_stf_api_crdt); +int iSetCPB_STF_API_CRDT_INIT_cpb_stf_api_crdt_init(unsigned int ucpb_stf_api_crdt_init); +int iSetSTF_STR_DI_FIFO_AF_TH_stf_str_di_fifo_af_th(unsigned int ustf_str_di_fifo_af_th); +int iSetSTF_STR_API_FIFO_AF_TH_stf_str_api_fifo_af_th(unsigned int ustf_str_api_fifo_af_th); +int iSetSTF_CMD_API_FIFO_AF_TH_stf_cmd_api_fifo_af_th(unsigned int ustf_cmd_api_fifo_af_th); +int iSetSTF_ACKSTR_FIFO_AF_TH_stf_ackstr_fifo_af_th(unsigned int ustf_ackstr_fifo_af_th); +int iSetSTF_MSG_VFID_CTL_fake_vfid_start_bit(unsigned int ufake_vfid_start_bit); +int iSetSTF_MSG_VFID_CTL_fake_vfid_end_bit(unsigned int ufake_vfid_end_bit); +int iSetCT_DMA_NRET_CFG_dma_nret_psh2pptr_en(unsigned int udma_nret_psh2pptr_en); +int iSetCT_DMA_NRET_CFG_dma_nret_psh2pptr_fix(unsigned int udma_nret_psh2pptr_fix); +int iSetCT_DMA_NRET_CFG_psh_pptr_cmd_len(unsigned int upsh_pptr_cmd_len); +int iSetCT_COL_SRC_TAG_H_CFG_osd_id_i(unsigned int uosd_id_i); +int iSetCT_COL_SRC_TAG_H_CFG_osd_id_l(unsigned int uosd_id_l); +int iSetCT_COL_SRC_TAG_H_CFG_osd_id_m(unsigned int uosd_id_m); +int iSetCT_DEALC_FIFO_AF_TH_ct_dealc_fifo_af_th(unsigned int uct_dealc_fifo_af_th); +int iSetSTFIQ_PSH_FIFO_CFG_stfpsh_fifo_ae_th(unsigned int ustfpsh_fifo_ae_th); +int iSetSTFIQ_PSH_FIFO_CFG_stfpsh_fifo_af_th(unsigned int ustfpsh_fifo_af_th); +int iSetSTFIQ_LINK_FIFO_CFG_link_fifo_ae_th(unsigned int ulink_fifo_ae_th); +int iSetSTFIQ_LINK_FIFO_CFG_link_fifo_af_th(unsigned int ulink_fifo_af_th); +int iSetLINK_WR_FIFO_CFG_linkwr_fifo_ae_th(unsigned int ulinkwr_fifo_ae_th); +int iSetLINK_WR_FIFO_CFG_linkwr_fifo_af_th(unsigned int ulinkwr_fifo_af_th); +int iSetSTF_CMD_API_RD_REQ_FIFO_STA_stf_cmd_api_fifo_sta(unsigned int ustf_cmd_api_fifo_sta); +int iSetSTF_CMD_API_RD_REQ_FIFO_STA_stf_rd_req_fifo_sta(unsigned int ustf_rd_req_fifo_sta); +int iSetSTF_STR_API_FIFO_STA_stf_str_api_fifo_sta(unsigned int ustf_str_api_fifo_sta); +int iSetSTF_WR_RD_DAT_IN_FIFO_STA_stf_wr_di_fifo_sta(unsigned int ustf_wr_di_fifo_sta); +int iSetSTF_WR_RD_DAT_IN_FIFO_STA_stf_rd_di_fifo_sta(unsigned int ustf_rd_di_fifo_sta); +int iSetSTF_RSP_API_HDR_DAT_FIFO_STA_stf_rsp_api_dat_fifo_sta(unsigned int ustf_rsp_api_dat_fifo_sta); +int iSetSTF_RSP_API_HDR_DAT_FIFO_STA_stf_rsp_api_hdr_fifo_sta(unsigned int ustf_rsp_api_hdr_fifo_sta); +int iSetSTF_RSP_API_CD_CRC_FIFO_STA_stf_rsp_api_crc_fifo_sta(unsigned int ustf_rsp_api_crc_fifo_sta); +int iSetSTF_RSP_API_CD_CRC_FIFO_STA_stf_rsp_api_cd_fifo_sta(unsigned int ustf_rsp_api_cd_fifo_sta); +int iSetSTF_RSP_API_CS_NPTR_FIFO_STA_stf_rsp_api_nptr_fifo_sta(unsigned int ustf_rsp_api_nptr_fifo_sta); +int iSetSTF_RSP_API_CS_NPTR_FIFO_STA_stf_rsp_api_cs_fifo_sta(unsigned int ustf_rsp_api_cs_fifo_sta); +int iSetSTF_STR_CMD_CNT_stf_cmd_cnt(unsigned int ustf_cmd_cnt); +int iSetSTF_STR_CMD_CNT_stf_str_cnt(unsigned int ustf_str_cnt); +int iSetSTF_ACK_RSP_CNT_stf_rsp_cnt(unsigned int ustf_rsp_cnt); +int iSetSTF_ACK_RSP_CNT_stf_ack_cnt(unsigned int ustf_ack_cnt); +int iSetSTF_PSH_CNT_stf_psh_tl_cnt(unsigned int ustf_psh_tl_cnt); +int iSetSTF_PSH_CNT_stf_iq_psh_cnt(unsigned int ustf_iq_psh_cnt); +int iSetSTF_CELL_MDF_CNT_stf_cell_mdf_cnt(unsigned int ustf_cell_mdf_cnt); +int iSetSTF_CELL_MDF_CNT_stf_iq_psh_rm_scol_cnt(unsigned int ustf_iq_psh_rm_scol_cnt); +int iSetSTF_WR_DI_CTRL_FIFO_STA_stf_wr_di_ctrl_fifo_sta(unsigned int ustf_wr_di_ctrl_fifo_sta); +int iSetSTF_WR_DI_CTRL_FIFO_STA_stf_ackstr_fifo_sta(unsigned int ustf_ackstr_fifo_sta); +int iSetSTF_FIFO_OV_ERR_0_stf_rd_req_fifo_ov(unsigned int ustf_rd_req_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_cmd_api_fifo_ov(unsigned int ustf_cmd_api_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_str_api_fifo_ov(unsigned int ustf_str_api_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_rd_di_fifo_ov(unsigned int ustf_rd_di_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_wr_di_fifo_ov(unsigned int ustf_wr_di_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_wr_di_ctrl_fifo_ov(unsigned int ustf_wr_di_ctrl_fifo_ov); +int iSetSTF_FIFO_OV_ERR_0_stf_ackstr_fifo_ov(unsigned int ustf_ackstr_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_hdr_fifo_ov(unsigned int ustf_rsp_api_hdr_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_dat_fifo_ov(unsigned int ustf_rsp_api_dat_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_cd_fifo_ov(unsigned int ustf_rsp_api_cd_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_crc_fifo_ov(unsigned int ustf_rsp_api_crc_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_cs_fifo_ov(unsigned int ustf_rsp_api_cs_fifo_ov); +int iSetSTF_FIFO_OV_ERR_1_stf_rsp_api_nptr_fifo_ov(unsigned int ustf_rsp_api_nptr_fifo_ov); +int iSetSTF_FIFO_UF_ERR_0_stf_rd_req_fifo_uf(unsigned int ustf_rd_req_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_cmd_api_fifo_uf(unsigned int ustf_cmd_api_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_str_api_fifo_uf(unsigned int ustf_str_api_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_rd_di_fifo_uf(unsigned int ustf_rd_di_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_wr_di_fifo_uf(unsigned int ustf_wr_di_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_wr_di_ctrl_fifo_uf(unsigned int ustf_wr_di_ctrl_fifo_uf); +int iSetSTF_FIFO_UF_ERR_0_stf_ackstr_fifo_uf(unsigned int ustf_ackstr_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_hdr_fifo_uf(unsigned int ustf_rsp_api_hdr_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_dat_fifo_uf(unsigned int ustf_rsp_api_dat_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_cd_fifo_uf(unsigned int ustf_rsp_api_cd_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_crc_fifo_uf(unsigned int ustf_rsp_api_crc_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_cs_fifo_uf(unsigned int ustf_rsp_api_cs_fifo_uf); +int iSetSTF_FIFO_UF_ERR_1_stf_rsp_api_nptr_fifo_uf(unsigned int ustf_rsp_api_nptr_fifo_uf); +int iSetCT_EXT_DEALC_FIFO_STA_ct_ext_dealc_rx_fifo_sta(unsigned int uct_ext_dealc_rx_fifo_sta); +int iSetCT_EXT_DEALC_FIFO_STA_ct_ext_dealc_tx_fifo_sta(unsigned int uct_ext_dealc_tx_fifo_sta); +int iSetSTF_PCOL_NUM_ERR_stf_pcol_num_err(unsigned int ustf_pcol_num_err); +int iSetSTFWR_FIFO_RAM_ERR_stfwr_fifo_mem_err_addr(unsigned int ustfwr_fifo_mem_err_addr); +int iSetSTFWR_FIFO_RAM_ERR_stfwr_fifo_mem_err_cerr(unsigned int ustfwr_fifo_mem_err_cerr); +int iSetSTFWR_FIFO_RAM_ERR_stfwr_fifo_mem_err_ucerr(unsigned int ustfwr_fifo_mem_err_ucerr); +int iSetSTFWR_FIFO_RAM_ERR_stfwr_fifo_mem_err_cnt(unsigned int ustfwr_fifo_mem_err_cnt); +int iSetSTFSTR_FIFO_RAM_ERR_stfstr_fifo_mem_err_addr(unsigned int ustfstr_fifo_mem_err_addr); +int iSetSTFSTR_FIFO_RAM_ERR_stfstr_fifo_mem_err_cerr(unsigned int ustfstr_fifo_mem_err_cerr); +int iSetSTFSTR_FIFO_RAM_ERR_stfstr_fifo_mem_err_ucerr(unsigned int ustfstr_fifo_mem_err_ucerr); +int iSetSTFSTR_FIFO_RAM_ERR_stfstr_fifo_mem_err_cnt(unsigned int ustfstr_fifo_mem_err_cnt); +int iSetSTFRSP_FIFO_RAM_ERR_stfrsp_fifo_mem_err_addr(unsigned int ustfrsp_fifo_mem_err_addr); +int iSetSTFRSP_FIFO_RAM_ERR_stfrsp_fifo_mem_err_cerr(unsigned int ustfrsp_fifo_mem_err_cerr); +int iSetSTFRSP_FIFO_RAM_ERR_stfrsp_fifo_mem_err_ucerr(unsigned int ustfrsp_fifo_mem_err_ucerr); +int iSetSTFRSP_FIFO_RAM_ERR_stfrsp_fifo_mem_err_cnt(unsigned int ustfrsp_fifo_mem_err_cnt); +int iSetSTFIQ_PKT_PSH_CNT_stfiq_pkt_psh_cnt(unsigned int ustfiq_pkt_psh_cnt); +int iSetSTFIQ_MSG_PSH_CNT_stfiq_msg_psh_cnt(unsigned int ustfiq_msg_psh_cnt); +int iSetSTFIQ_COL_PSH_CNT_stfiq_col_psh_cnt(unsigned int ustfiq_col_psh_cnt); +int iSetSTFIQ_LINK_REQ_CNT_stfiq_link_req_cnt(unsigned int ustfiq_link_req_cnt); +int iSetSTFIQ_PSH_FIFO_STA_stfiq_psh_fifo_sta(unsigned int ustfiq_psh_fifo_sta); +int iSetSTFIQ_LINK_FIFO_STA_stfiq_link_fifo_sta(unsigned int ustfiq_link_fifo_sta); +int iSetLINK_WR_FIFO_STA_link_wr_fifo_sta(unsigned int ulink_wr_fifo_sta); +int iSetCIQ_FIFO_OF_ERR_stliq_psh_fifo_of_err(unsigned int ustliq_psh_fifo_of_err); +int iSetCIQ_FIFO_OF_ERR_stfiq_psh_fifo_of_err(unsigned int ustfiq_psh_fifo_of_err); +int iSetCIQ_FIFO_OF_ERR_stfiq_link_fifo_of_err(unsigned int ustfiq_link_fifo_of_err); +int iSetCIQ_FIFO_OF_ERR_link_wr_fifo_of_err(unsigned int ulink_wr_fifo_of_err); +int iSetCIQ_FIFO_OF_ERR_rob_psh_fifo_of_err(unsigned int urob_psh_fifo_of_err); +int iSetCIQ_FIFO_UF_ERR_stliq_psh_fifo_uf_err(unsigned int ustliq_psh_fifo_uf_err); +int iSetCIQ_FIFO_UF_ERR_stfiq_psh_fifo_uf_err(unsigned int ustfiq_psh_fifo_uf_err); +int iSetCIQ_FIFO_UF_ERR_stfiq_link_fifo_uf_err(unsigned int ustfiq_link_fifo_uf_err); +int iSetCIQ_FIFO_UF_ERR_link_wr_fifo_uf_err(unsigned int ulink_wr_fifo_uf_err); +int iSetCIQ_FIFO_UF_ERR_rob_psh_fifo_uf_err(unsigned int urob_psh_fifo_uf_err); +int iSetCIQ_RAM_ERR_stfiq_psh_fifo_mem_err_addr(unsigned int ustfiq_psh_fifo_mem_err_addr); +int iSetCIQ_RAM_ERR_stfiq_psh_fifo_mem_cerr(unsigned int ustfiq_psh_fifo_mem_cerr); +int iSetCIQ_RAM_ERR_stfiq_psh_fifo_mem_ucerr(unsigned int ustfiq_psh_fifo_mem_ucerr); +int iSetCIQ_RAM_ERR_stfiq_psh_fifo_mem_err_cnt(unsigned int ustfiq_psh_fifo_mem_err_cnt); +int iSetCIQ_ERR_stfiq_col_psh_err(unsigned int ustfiq_col_psh_err); +int iSetDAT_RAM_ERR_dat_mem_err_addr(unsigned int udat_mem_err_addr); +int iSetDAT_RAM_ERR_dat_mem_err_cerr(unsigned int udat_mem_err_cerr); +int iSetDAT_RAM_ERR_dat_mem_err_ucerr(unsigned int udat_mem_err_ucerr); +int iSetDAT_RAM_ERR_dat_mem_err_cnt(unsigned int udat_mem_err_cnt); +int iSetCD_RAM_ERR_cd_mem_err_addr(unsigned int ucd_mem_err_addr); +int iSetCD_RAM_ERR_cd_mem_err_cerr(unsigned int ucd_mem_err_cerr); +int iSetCD_RAM_ERR_cd_mem_err_ucerr(unsigned int ucd_mem_err_ucerr); +int iSetCD_RAM_ERR_cd_mem_err_cnt(unsigned int ucd_mem_err_cnt); +int iSetNPTR_RAM_ERR_nptr_mem_err_addr(unsigned int unptr_mem_err_addr); +int iSetNPTR_RAM_ERR_nptr_mem_err_cerr(unsigned int unptr_mem_err_cerr); +int iSetNPTR_RAM_ERR_nptr_mem_err_ucerr(unsigned int unptr_mem_err_ucerr); +int iSetNPTR_RAM_ERR_nptr_mem_err_cnt(unsigned int unptr_mem_err_cnt); +int iSetTI_RAM_ERR_ti_mem_err_addr(unsigned int uti_mem_err_addr); +int iSetTI_RAM_ERR_ti_mem_err_cerr(unsigned int uti_mem_err_cerr); +int iSetTI_RAM_ERR_ti_mem_err_ucerr(unsigned int uti_mem_err_ucerr); +int iSetTI_RAM_ERR_ti_mem_err_cnt(unsigned int uti_mem_err_cnt); +int iSetBMP_RAM_ERR_bmp_mem_err_addr(unsigned int ubmp_mem_err_addr); +int iSetBMP_RAM_ERR_bmp_mem_err_cerr(unsigned int ubmp_mem_err_cerr); +int iSetBMP_RAM_ERR_bmp_mem_err_ucerr(unsigned int ubmp_mem_err_ucerr); +int iSetBMP_RAM_ERR_bmp_mem_err_cnt(unsigned int ubmp_mem_err_cnt); +int iSetAGE_RAM_ERR_age_mem_err_addr(unsigned int uage_mem_err_addr); +int iSetAGE_RAM_ERR_age_mem_err_cerr(unsigned int uage_mem_err_cerr); +int iSetAGE_RAM_ERR_age_mem_err_ucerr(unsigned int uage_mem_err_ucerr); +int iSetAGE_RAM_ERR_age_mem_err_cnt(unsigned int uage_mem_err_cnt); + +/* Define the union csr_cit_data_in_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_data_in_fifo_af_th : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_data_in_fifo_af_th_u; + +/* Define the union csr_cit_dealc_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_dealc_fifo_af_th : 5; /* [4:0] */ + u32 rsv_1 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_dealc_fifo_af_th_u; + +/* Define the union csr_cit_ec_ch_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_ec_ch0 : 5; /* [4:0] */ + u32 rsv_2 : 2; /* [6:5] */ + u32 cit_ec_ch0_vld : 1; /* [7] */ + u32 cit_ec_ch1 : 5; /* [12:8] */ + u32 rsv_3 : 2; /* [14:13] */ + u32 cit_ec_ch1_vld : 1; /* [15] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_ec_ch_u; + +/* Define the union csr_cpr_pro_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_wt_0 : 4; /* [3:0] */ + u32 cpr_pro_wt_1 : 4; /* [7:4] */ + u32 cpr_pro_wt_2 : 4; /* [11:8] */ + u32 cpr_pro_wt_3 : 4; /* [15:12] */ + u32 cpr_pro_wt_4 : 4; /* [19:16] */ + u32 rsv_5 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_wt_u; + +/* Define the union csr_cpr_fifo_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_fifo_crdt_init_dat : 6; /* [5:0] */ + u32 rsv_6 : 2; /* [7:6] */ + u32 cpr_fifo_crdt_init : 1; /* [8] */ + u32 rsv_7 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_fifo_crdt_init_u; + +/* Define the union csr_cpr_dealc_tx_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_dealc_tx_af_th : 7; /* [6:0] */ + u32 rsv_8 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_dealc_tx_af_th_u; + +/* Define the union csr_cpr_dealc_rx_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_dealc_rx_af_th : 7; /* [6:0] */ + u32 rsv_9 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_dealc_rx_af_th_u; + +/* Define the union csr_cpr_prls_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_prls_af_th : 7; /* [6:0] */ + u32 rsv_10 : 1; /* [7] */ + u32 cpr_pro_prls_fifo_af_th : 5; /* [12:8] */ + u32 rsv_11 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_prls_af_th_u; + +/* Define the union csr_cpr_col_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_deast_col_th : 7; /* [6:0] */ + u32 rsv_12 : 1; /* [7] */ + u32 cpr_ast_col_th : 7; /* [14:8] */ + u32 rsv_13 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_col_th_u; + +/* Define the union csr_cpr_pro_di_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_di_fifo_af_th : 5; /* [4:0] */ + u32 rsv_14 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_di_fifo_af_th_u; + +/* Define the union csr_cpr_pro_dealc_tx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_dealc_tx_fifo_af_th : 5; /* [4:0] */ + u32 rsv_15 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_dealc_tx_fifo_af_th_u; + +/* Define the union csr_cpr_pro_dealc_rx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_dealc_rx_fifo_af_th : 5; /* [4:0] */ + u32 rsv_16 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_dealc_rx_fifo_af_th_u; + +/* Define the union csr_cpr_pro_fifo_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_dat_fifo_crdt_init_dat : 5; /* [4:0] */ + u32 rsv_17 : 3; /* [7:5] */ + u32 cpr_pro_dat_fifo_crdt_init : 1; /* [8] */ + u32 rsv_18 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_fifo_crdt_init_u; + +/* Define the union csr_cpr_pro_dealc_rp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_dealc_rp_th : 7; /* [6:0] */ + u32 rsv_19 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_dealc_rp_th_u; + +/* Define the union csr_cpr_pro_rrdy_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_rrdy_fifo_af_th : 4; /* [3:0] */ + u32 rsv_20 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_rrdy_fifo_af_th_u; + +/* Define the union csr_cpr_out_err_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_perx_err_en : 1; /* [0] */ + u32 cpb_perx_ftso_err_en : 1; /* [1] */ + u32 rsv_21 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_out_err_en_u; + +/* Define the union csr_cit_dat_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_di_ctrl_fifo_sta : 11; /* [10:0] */ + u32 rsv_22 : 5; /* [15:11] */ + u32 cit_di_fifo_sta : 11; /* [26:16] */ + u32 rsv_23 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_dat_fifo_sta_u; + +/* Define the union csr_cit_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_dealc_fifo_sta : 11; /* [10:0] */ + u32 rsv_24 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_dealc_fifo_sta_u; + +/* Define the union csr_cit_in_pkt_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_in_pkt_sop_cnt : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_in_pkt_sop_cnt_u; + +/* Define the union csr_cit_in_pkt_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_in_pkt_eop_cnt : 16; /* [15:0] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_in_pkt_eop_cnt_u; + +/* Define the union csr_cit_in_chnl_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_in_chnl_pkt_cnt : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_in_chnl_pkt_cnt_u; + +/* Define the union csr_cit_rpt_iq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_rpt_iq_cnt : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_rpt_iq_cnt_u; + +/* Define the union csr_cit_iq_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_iq_bp_cnt : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_iq_bp_cnt_u; + +/* Define the union csr_cit_pal_less_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_pal_less_num : 16; /* [15:0] */ + u32 cit_pal_less_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_pal_less_sta_u; + +/* Define the union csr_cit_pal_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_pal_err : 1; /* [0] */ + u32 rsv_30 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_pal_err_u; + +/* Define the union csr_cit_schnl_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_schnl_err : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_schnl_err_u; + +/* Define the union csr_cit_fifo_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_di_fifo_uf : 1; /* [0] */ + u32 cit_di_ctrl_fifo_uf : 1; /* [1] */ + u32 cit_dealc_fifo_uf : 1; /* [2] */ + u32 rsv_32 : 13; /* [15:3] */ + u32 cit_di_fifo_ov : 1; /* [16] */ + u32 cit_di_ctrl_fifo_ov : 1; /* [17] */ + u32 cit_dealc_fifo_ov : 1; /* [18] */ + u32 rsv_33 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_fifo_err_u; + +/* Define the union csr_cit_ec_illegal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_ec_illegal : 1; /* [0] */ + u32 rsv_34 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_ec_illegal_u; + +/* Define the union csr_cit_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cit_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_35 : 7; /* [11:5] */ + u32 cit_fifo_mem_err_cerr : 1; /* [12] */ + u32 cit_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_36 : 2; /* [15:14] */ + u32 cit_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cit_fifo_ram_err_u; + +/* Define the union csr_cpr_pro_dat_in_rrdy_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_rrdy_fifo_sta : 11; /* [10:0] */ + u32 cpr_pro_di_fifo_sta : 11; /* [21:11] */ + u32 cpr_pro_prls_fifo_sta : 9; /* [30:22] */ + u32 rsv_37 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_dat_in_rrdy_fifo_sta_u; + +/* Define the union csr_cpr_pro_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_dealc_rx_fifo_sta : 11; /* [10:0] */ + u32 rsv_38 : 5; /* [15:11] */ + u32 cpr_pro_dealc_tx_fifo_sta : 11; /* [26:16] */ + u32 rsv_39 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_pro_dealc_fifo_sta_u; + +/* Define the union csr_cpr_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_dealc_rx_fifo_sta : 11; /* [10:0] */ + u32 rsv_40 : 5; /* [15:11] */ + u32 cpr_dealc_tx_fifo_sta : 11; /* [26:16] */ + u32 rsv_41 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_dealc_fifo_sta_u; + +/* Define the union csr_cpr_dat_out_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_dat_out_fifo_sta : 11; /* [10:0] */ + u32 rsv_42 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_dat_out_fifo_sta_u; + +/* Define the union csr_cpr_prls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_prls_fifo_sta : 11; /* [10:0] */ + u32 rsv_43 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_prls_fifo_sta_u; + +/* Define the union csr_cpr_out_pkt_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_out_pkt_sop_cnt : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_out_pkt_sop_cnt_u; + +/* Define the union csr_cpr_out_pkt_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_out_pkt_eop_cnt : 16; /* [15:0] */ + u32 rsv_45 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_out_pkt_eop_cnt_u; + +/* Define the union csr_cpr_rrdy_side_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_rrdy_side_err : 1; /* [0] */ + u32 rsv_46 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_rrdy_side_err_u; + +/* Define the union csr_cpr_out_chnl_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_out_chnl_pkt_cnt : 16; /* [15:0] */ + u32 rsv_47 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_out_chnl_pkt_cnt_u; + +/* Define the union csr_cpr_sof_msm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_sof_msm_info : 28; /* [27:0] */ + u32 rsv_48 : 3; /* [30:28] */ + u32 cpr_sof_msm : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_sof_msm_u; + +/* Define the union csr_cpr_eof_msm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_eof_msm_info : 28; /* [27:0] */ + u32 rsv_49 : 3; /* [30:28] */ + u32 cpr_eof_msm : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_eof_msm_u; + +/* Define the union csr_cpr_fifo_ov_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_di_fifo_ov : 5; /* [4:0] */ + u32 cpr_pro_rrdy_fifo_ov : 5; /* [9:5] */ + u32 cpr_pro_dealc_tx_fifo_ov : 5; /* [14:10] */ + u32 cpr_pro_dealc_rx_fifo_ov : 5; /* [19:15] */ + u32 cpr_pro_prls_fifo_ov : 5; /* [24:20] */ + u32 rsv_50 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_fifo_ov_err_u; + +/* Define the union csr_cpr_fifo_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_dat_out_fifo_uf : 5; /* [4:0] */ + u32 rsv_51 : 3; /* [7:5] */ + u32 cpr_dealc_tx_fifo_uf : 1; /* [8] */ + u32 cpr_dealc_rx_fifo_uf : 1; /* [9] */ + u32 cpr_prls_fifo_uf : 1; /* [10] */ + u32 rsv_52 : 5; /* [15:11] */ + u32 cpr_dat_out_fifo_ov : 5; /* [20:16] */ + u32 rsv_53 : 3; /* [23:21] */ + u32 cpr_dealc_tx_fifo_ov : 1; /* [24] */ + u32 cpr_dealc_rx_fifo_ov : 1; /* [25] */ + u32 cpr_prls_fifo_ov : 1; /* [26] */ + u32 rsv_54 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_fifo_err_u; + +/* Define the union csr_cpr_fifo_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_pro_di_fifo_uf : 5; /* [4:0] */ + u32 cpr_pro_rrdy_fifo_uf : 5; /* [9:5] */ + u32 cpr_pro_dealc_tx_fifo_uf : 5; /* [14:10] */ + u32 cpr_pro_dealc_rx_fifo_uf : 5; /* [19:15] */ + u32 cpr_pro_prls_fifo_uf : 5; /* [24:20] */ + u32 rsv_55 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_fifo_uf_err_u; + +/* Define the union csr_cpr_sge_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_zero_clr : 1; /* [0] */ + u32 rsv_56 : 3; /* [3:1] */ + u32 sge_crdt_err_pro : 2; /* [5:4] */ + u32 rsv_57 : 2; /* [7:6] */ + u32 sge_crdt_err_chnl : 5; /* [12:8] */ + u32 rsv_58 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_sge_crdt_err_u; + +/* Define the union csr_cpr_sge_crdt_err_dma_hed_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_err_crdt_err_dma_hed_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_sge_crdt_err_dma_hed_l_u; + +/* Define the union csr_cpr_sge_crdt_err_dma_hed_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_err_crdt_err_dma_hed_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_sge_crdt_err_dma_hed_h_u; + +/* Define the union csr_cpr_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_fifo_mem_err_addr : 4; /* [3:0] */ + u32 rsv_59 : 8; /* [11:4] */ + u32 cpr_fifo_mem_err_cerr : 1; /* [12] */ + u32 cpr_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_60 : 2; /* [15:14] */ + u32 cpr_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpr_fifo_ram_err_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cit_data_in_fifo_af_th_u cit_data_in_fifo_af_th; /* 500 */ + volatile csr_cit_dealc_fifo_af_th_u cit_dealc_fifo_af_th; /* 504 */ + volatile csr_cit_ec_ch_u cit_ec_ch; /* 508 */ + volatile csr_cpr_pro_wt_u cpr_pro_wt; /* 600 */ + volatile csr_cpr_fifo_crdt_init_u cpr_fifo_crdt_init; /* 604 */ + volatile csr_cpr_dealc_tx_af_th_u cpr_dealc_tx_af_th; /* 610 */ + volatile csr_cpr_dealc_rx_af_th_u cpr_dealc_rx_af_th; /* 614 */ + volatile csr_cpr_prls_af_th_u cpr_prls_af_th; /* 618 */ + volatile csr_cpr_col_th_u cpr_col_th; /* 61C */ + volatile csr_cpr_pro_di_fifo_af_th_u cpr_pro_di_fifo_af_th; /* 630 */ + volatile csr_cpr_pro_dealc_tx_fifo_af_th_u cpr_pro_dealc_tx_fifo_af_th; /* 634 */ + volatile csr_cpr_pro_dealc_rx_fifo_af_th_u cpr_pro_dealc_rx_fifo_af_th; /* 638 */ + volatile csr_cpr_pro_fifo_crdt_init_u cpr_pro_fifo_crdt_init; /* 63C */ + volatile csr_cpr_pro_dealc_rp_th_u cpr_pro_dealc_rp_th; /* 640 */ + volatile csr_cpr_pro_rrdy_fifo_af_th_u cpr_pro_rrdy_fifo_af_th; /* 644 */ + volatile csr_cpr_out_err_en_u cpr_out_err_en; /* 648 */ + volatile csr_cit_dat_fifo_sta_u cit_dat_fifo_sta; /* 1100 */ + volatile csr_cit_dealc_fifo_sta_u cit_dealc_fifo_sta; /* 1104 */ + volatile csr_cit_in_pkt_sop_cnt_u cit_in_pkt_sop_cnt; /* 1120 */ + volatile csr_cit_in_pkt_eop_cnt_u cit_in_pkt_eop_cnt; /* 1124 */ + volatile csr_cit_in_chnl_pkt_cnt_u cit_in_chnl_pkt_cnt[24]; /* 1130 */ + volatile csr_cit_rpt_iq_cnt_u cit_rpt_iq_cnt; /* 1190 */ + volatile csr_cit_iq_bp_cnt_u cit_iq_bp_cnt; /* 1194 */ + volatile csr_cit_pal_less_sta_u cit_pal_less_sta; /* 1198 */ + volatile csr_cit_pal_err_u cit_pal_err; /* 119C */ + volatile csr_cit_schnl_err_u cit_schnl_err; /* 11A0 */ + volatile csr_cit_fifo_err_u cit_fifo_err; /* 11A4 */ + volatile csr_cit_ec_illegal_u cit_ec_illegal; /* 11A8 */ + volatile csr_cit_fifo_ram_err_u cit_fifo_ram_err; /* 11B0 */ + volatile csr_cpr_pro_dat_in_rrdy_fifo_sta_u cpr_pro_dat_in_rrdy_fifo_sta[5]; /* 1200 */ + volatile csr_cpr_pro_dealc_fifo_sta_u cpr_pro_dealc_fifo_sta[5]; /* 1214 */ + volatile csr_cpr_dealc_fifo_sta_u cpr_dealc_fifo_sta; /* 1228 */ + volatile csr_cpr_dat_out_fifo_sta_u cpr_dat_out_fifo_sta[5]; /* 122C */ + volatile csr_cpr_prls_fifo_sta_u cpr_prls_fifo_sta; /* 1240 */ + volatile csr_cpr_out_pkt_sop_cnt_u cpr_out_pkt_sop_cnt; /* 1244 */ + volatile csr_cpr_out_pkt_eop_cnt_u cpr_out_pkt_eop_cnt; /* 1248 */ + volatile csr_cpr_rrdy_side_err_u cpr_rrdy_side_err; /* 124C */ + volatile csr_cpr_out_chnl_pkt_cnt_u cpr_out_chnl_pkt_cnt[23]; /* 1250 */ + volatile csr_cpr_sof_msm_u cpr_sof_msm[5]; /* 12AC */ + volatile csr_cpr_eof_msm_u cpr_eof_msm[5]; /* 12C0 */ + volatile csr_cpr_fifo_ov_err_u cpr_fifo_ov_err; /* 12D4 */ + volatile csr_cpr_fifo_err_u cpr_fifo_err; /* 12D8 */ + volatile csr_cpr_fifo_uf_err_u cpr_fifo_uf_err; /* 12DC */ + volatile csr_cpr_sge_crdt_err_u cpr_sge_crdt_err; /* 12E0 */ + volatile csr_cpr_sge_crdt_err_dma_hed_l_u cpr_sge_crdt_err_dma_hed_l; /* 12E4 */ + volatile csr_cpr_sge_crdt_err_dma_hed_h_u cpr_sge_crdt_err_dma_hed_h; /* 12E8 */ + volatile csr_cpr_fifo_ram_err_u cpr_fifo_ram_err[5]; /* 12EC */ +} S_cpb_csr_1_REGS_TYPE; + +/* Declare the struct pointor of the module cpb_csr_1 */ +extern volatile S_cpb_csr_1_REGS_TYPE *gopcpb_csr_1AllReg; + +/* Declare the functions that set the member value */ +int iSetCIT_DATA_IN_FIFO_AF_TH_cit_data_in_fifo_af_th(unsigned int ucit_data_in_fifo_af_th); +int iSetCIT_DEALC_FIFO_AF_TH_cit_dealc_fifo_af_th(unsigned int ucit_dealc_fifo_af_th); +int iSetCIT_EC_CH_cit_ec_ch0(unsigned int ucit_ec_ch0); +int iSetCIT_EC_CH_cit_ec_ch0_vld(unsigned int ucit_ec_ch0_vld); +int iSetCIT_EC_CH_cit_ec_ch1(unsigned int ucit_ec_ch1); +int iSetCIT_EC_CH_cit_ec_ch1_vld(unsigned int ucit_ec_ch1_vld); +int iSetCPR_PRO_WT_cpr_pro_wt_0(unsigned int ucpr_pro_wt_0); +int iSetCPR_PRO_WT_cpr_pro_wt_1(unsigned int ucpr_pro_wt_1); +int iSetCPR_PRO_WT_cpr_pro_wt_2(unsigned int ucpr_pro_wt_2); +int iSetCPR_PRO_WT_cpr_pro_wt_3(unsigned int ucpr_pro_wt_3); +int iSetCPR_PRO_WT_cpr_pro_wt_4(unsigned int ucpr_pro_wt_4); +int iSetCPR_FIFO_CRDT_INIT_cpr_fifo_crdt_init_dat(unsigned int ucpr_fifo_crdt_init_dat); +int iSetCPR_FIFO_CRDT_INIT_cpr_fifo_crdt_init(unsigned int ucpr_fifo_crdt_init); +int iSetCPR_DEALC_TX_AF_TH_cpr_dealc_tx_af_th(unsigned int ucpr_dealc_tx_af_th); +int iSetCPR_DEALC_RX_AF_TH_cpr_dealc_rx_af_th(unsigned int ucpr_dealc_rx_af_th); +int iSetCPR_PRLS_AF_TH_cpr_prls_af_th(unsigned int ucpr_prls_af_th); +int iSetCPR_PRLS_AF_TH_cpr_pro_prls_fifo_af_th(unsigned int ucpr_pro_prls_fifo_af_th); +int iSetCPR_COL_TH_cpr_deast_col_th(unsigned int ucpr_deast_col_th); +int iSetCPR_COL_TH_cpr_ast_col_th(unsigned int ucpr_ast_col_th); +int iSetCPR_PRO_DI_FIFO_AF_TH_cpr_pro_di_fifo_af_th(unsigned int ucpr_pro_di_fifo_af_th); +int iSetCPR_PRO_DEALC_TX_FIFO_AF_TH_cpr_pro_dealc_tx_fifo_af_th(unsigned int ucpr_pro_dealc_tx_fifo_af_th); +int iSetCPR_PRO_DEALC_RX_FIFO_AF_TH_cpr_pro_dealc_rx_fifo_af_th(unsigned int ucpr_pro_dealc_rx_fifo_af_th); +int iSetCPR_PRO_FIFO_CRDT_INIT_cpr_pro_dat_fifo_crdt_init_dat(unsigned int ucpr_pro_dat_fifo_crdt_init_dat); +int iSetCPR_PRO_FIFO_CRDT_INIT_cpr_pro_dat_fifo_crdt_init(unsigned int ucpr_pro_dat_fifo_crdt_init); +int iSetCPR_PRO_DEALC_RP_TH_cpr_pro_dealc_rp_th(unsigned int ucpr_pro_dealc_rp_th); +int iSetCPR_PRO_RRDY_FIFO_AF_TH_cpr_pro_rrdy_fifo_af_th(unsigned int ucpr_pro_rrdy_fifo_af_th); +int iSetCPR_OUT_ERR_EN_cpb_perx_err_en(unsigned int ucpb_perx_err_en); +int iSetCPR_OUT_ERR_EN_cpb_perx_ftso_err_en(unsigned int ucpb_perx_ftso_err_en); +int iSetCIT_DAT_FIFO_STA_cit_di_ctrl_fifo_sta(unsigned int ucit_di_ctrl_fifo_sta); +int iSetCIT_DAT_FIFO_STA_cit_di_fifo_sta(unsigned int ucit_di_fifo_sta); +int iSetCIT_DEALC_FIFO_STA_cit_dealc_fifo_sta(unsigned int ucit_dealc_fifo_sta); +int iSetCIT_IN_PKT_SOP_CNT_cit_in_pkt_sop_cnt(unsigned int ucit_in_pkt_sop_cnt); +int iSetCIT_IN_PKT_EOP_CNT_cit_in_pkt_eop_cnt(unsigned int ucit_in_pkt_eop_cnt); +int iSetCIT_IN_CHNL_PKT_CNT_cit_in_chnl_pkt_cnt(unsigned int ucit_in_chnl_pkt_cnt); +int iSetCIT_RPT_IQ_CNT_cit_rpt_iq_cnt(unsigned int ucit_rpt_iq_cnt); +int iSetCIT_IQ_BP_CNT_cit_iq_bp_cnt(unsigned int ucit_iq_bp_cnt); +int iSetCIT_PAL_LESS_STA_cit_pal_less_num(unsigned int ucit_pal_less_num); +int iSetCIT_PAL_LESS_STA_cit_pal_less_cnt(unsigned int ucit_pal_less_cnt); +int iSetCIT_PAL_ERR_cit_pal_err(unsigned int ucit_pal_err); +int iSetCIT_SCHNL_ERR_cit_schnl_err(unsigned int ucit_schnl_err); +int iSetCIT_FIFO_ERR_cit_di_fifo_uf(unsigned int ucit_di_fifo_uf); +int iSetCIT_FIFO_ERR_cit_di_ctrl_fifo_uf(unsigned int ucit_di_ctrl_fifo_uf); +int iSetCIT_FIFO_ERR_cit_dealc_fifo_uf(unsigned int ucit_dealc_fifo_uf); +int iSetCIT_FIFO_ERR_cit_di_fifo_ov(unsigned int ucit_di_fifo_ov); +int iSetCIT_FIFO_ERR_cit_di_ctrl_fifo_ov(unsigned int ucit_di_ctrl_fifo_ov); +int iSetCIT_FIFO_ERR_cit_dealc_fifo_ov(unsigned int ucit_dealc_fifo_ov); +int iSetCIT_EC_ILLEGAL_cit_ec_illegal(unsigned int ucit_ec_illegal); +int iSetCIT_FIFO_RAM_ERR_cit_fifo_mem_err_addr(unsigned int ucit_fifo_mem_err_addr); +int iSetCIT_FIFO_RAM_ERR_cit_fifo_mem_err_cerr(unsigned int ucit_fifo_mem_err_cerr); +int iSetCIT_FIFO_RAM_ERR_cit_fifo_mem_err_ucerr(unsigned int ucit_fifo_mem_err_ucerr); +int iSetCIT_FIFO_RAM_ERR_cit_fifo_mem_err_cnt(unsigned int ucit_fifo_mem_err_cnt); +int iSetCPR_PRO_DAT_IN_RRDY_FIFO_STA_cpr_pro_rrdy_fifo_sta(unsigned int ucpr_pro_rrdy_fifo_sta); +int iSetCPR_PRO_DAT_IN_RRDY_FIFO_STA_cpr_pro_di_fifo_sta(unsigned int ucpr_pro_di_fifo_sta); +int iSetCPR_PRO_DAT_IN_RRDY_FIFO_STA_cpr_pro_prls_fifo_sta(unsigned int ucpr_pro_prls_fifo_sta); +int iSetCPR_PRO_DEALC_FIFO_STA_cpr_pro_dealc_rx_fifo_sta(unsigned int ucpr_pro_dealc_rx_fifo_sta); +int iSetCPR_PRO_DEALC_FIFO_STA_cpr_pro_dealc_tx_fifo_sta(unsigned int ucpr_pro_dealc_tx_fifo_sta); +int iSetCPR_DEALC_FIFO_STA_cpr_dealc_rx_fifo_sta(unsigned int ucpr_dealc_rx_fifo_sta); +int iSetCPR_DEALC_FIFO_STA_cpr_dealc_tx_fifo_sta(unsigned int ucpr_dealc_tx_fifo_sta); +int iSetCPR_DAT_OUT_FIFO_STA_cpr_dat_out_fifo_sta(unsigned int ucpr_dat_out_fifo_sta); +int iSetCPR_PRLS_FIFO_STA_cpr_prls_fifo_sta(unsigned int ucpr_prls_fifo_sta); +int iSetCPR_OUT_PKT_SOP_CNT_cpr_out_pkt_sop_cnt(unsigned int ucpr_out_pkt_sop_cnt); +int iSetCPR_OUT_PKT_EOP_CNT_cpr_out_pkt_eop_cnt(unsigned int ucpr_out_pkt_eop_cnt); +int iSetCPR_RRDY_SIDE_ERR_cpr_rrdy_side_err(unsigned int ucpr_rrdy_side_err); +int iSetCPR_OUT_CHNL_PKT_CNT_cpr_out_chnl_pkt_cnt(unsigned int ucpr_out_chnl_pkt_cnt); +int iSetCPR_SOF_MSM_cpr_sof_msm_info(unsigned int ucpr_sof_msm_info); +int iSetCPR_SOF_MSM_cpr_sof_msm(unsigned int ucpr_sof_msm); +int iSetCPR_EOF_MSM_cpr_eof_msm_info(unsigned int ucpr_eof_msm_info); +int iSetCPR_EOF_MSM_cpr_eof_msm(unsigned int ucpr_eof_msm); +int iSetCPR_FIFO_OV_ERR_cpr_pro_di_fifo_ov(unsigned int ucpr_pro_di_fifo_ov); +int iSetCPR_FIFO_OV_ERR_cpr_pro_rrdy_fifo_ov(unsigned int ucpr_pro_rrdy_fifo_ov); +int iSetCPR_FIFO_OV_ERR_cpr_pro_dealc_tx_fifo_ov(unsigned int ucpr_pro_dealc_tx_fifo_ov); +int iSetCPR_FIFO_OV_ERR_cpr_pro_dealc_rx_fifo_ov(unsigned int ucpr_pro_dealc_rx_fifo_ov); +int iSetCPR_FIFO_OV_ERR_cpr_pro_prls_fifo_ov(unsigned int ucpr_pro_prls_fifo_ov); +int iSetCPR_FIFO_ERR_cpr_dat_out_fifo_uf(unsigned int ucpr_dat_out_fifo_uf); +int iSetCPR_FIFO_ERR_cpr_dealc_tx_fifo_uf(unsigned int ucpr_dealc_tx_fifo_uf); +int iSetCPR_FIFO_ERR_cpr_dealc_rx_fifo_uf(unsigned int ucpr_dealc_rx_fifo_uf); +int iSetCPR_FIFO_ERR_cpr_prls_fifo_uf(unsigned int ucpr_prls_fifo_uf); +int iSetCPR_FIFO_ERR_cpr_dat_out_fifo_ov(unsigned int ucpr_dat_out_fifo_ov); +int iSetCPR_FIFO_ERR_cpr_dealc_tx_fifo_ov(unsigned int ucpr_dealc_tx_fifo_ov); +int iSetCPR_FIFO_ERR_cpr_dealc_rx_fifo_ov(unsigned int ucpr_dealc_rx_fifo_ov); +int iSetCPR_FIFO_ERR_cpr_prls_fifo_ov(unsigned int ucpr_prls_fifo_ov); +int iSetCPR_FIFO_UF_ERR_cpr_pro_di_fifo_uf(unsigned int ucpr_pro_di_fifo_uf); +int iSetCPR_FIFO_UF_ERR_cpr_pro_rrdy_fifo_uf(unsigned int ucpr_pro_rrdy_fifo_uf); +int iSetCPR_FIFO_UF_ERR_cpr_pro_dealc_tx_fifo_uf(unsigned int ucpr_pro_dealc_tx_fifo_uf); +int iSetCPR_FIFO_UF_ERR_cpr_pro_dealc_rx_fifo_uf(unsigned int ucpr_pro_dealc_rx_fifo_uf); +int iSetCPR_FIFO_UF_ERR_cpr_pro_prls_fifo_uf(unsigned int ucpr_pro_prls_fifo_uf); +int iSetCPR_SGE_CRDT_ERR_sge_zero_clr(unsigned int usge_zero_clr); +int iSetCPR_SGE_CRDT_ERR_sge_crdt_err_pro(unsigned int usge_crdt_err_pro); +int iSetCPR_SGE_CRDT_ERR_sge_crdt_err_chnl(unsigned int usge_crdt_err_chnl); +int iSetCPR_SGE_CRDT_ERR_DMA_HED_L_sge_err_crdt_err_dma_hed_l(unsigned int usge_err_crdt_err_dma_hed_l); +int iSetCPR_SGE_CRDT_ERR_DMA_HED_H_sge_err_crdt_err_dma_hed_h(unsigned int usge_err_crdt_err_dma_hed_h); +int iSetCPR_FIFO_RAM_ERR_cpr_fifo_mem_err_addr(unsigned int ucpr_fifo_mem_err_addr); +int iSetCPR_FIFO_RAM_ERR_cpr_fifo_mem_err_cerr(unsigned int ucpr_fifo_mem_err_cerr); +int iSetCPR_FIFO_RAM_ERR_cpr_fifo_mem_err_ucerr(unsigned int ucpr_fifo_mem_err_ucerr); +int iSetCPR_FIFO_RAM_ERR_cpr_fifo_mem_err_cnt(unsigned int ucpr_fifo_mem_err_cnt); + +/* Define the union csr_stl_rsp_api_fifo_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_npt_fifo_crdt : 5; /* [4:0] */ + u32 rsv_0 : 3; /* [7:5] */ + u32 stl_rsp_dat_fifo_crdt : 6; /* [13:8] */ + u32 rsv_1 : 2; /* [15:14] */ + u32 stl_rsp_api_hdr_fifo_crdt : 4; /* [19:16] */ + u32 stl_rsp_crc_fifo_crdt : 4; /* [23:20] */ + u32 stl_rsp_api_fifo_crdt_init : 1; /* [24] */ + u32 rsv_2 : 3; /* [27:25] */ + u32 stl_str_rsp_hdr_crdt : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rsp_api_fifo_crdt_init_u; + +/* Define the union csr_stl_psh_cmd_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_cmd_req_wt : 4; /* [3:0] */ + u32 stl_psh_req_wt : 4; /* [7:4] */ + u32 rsv_3 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_psh_cmd_wt_u; + +/* Define the union csr_stl_rd_req_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rd_req_fifo_af_th : 4; /* [3:0] */ + u32 rsv_4 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rd_req_fifo_af_th_u; + +/* Define the union csr_stl_rd_ctrl_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rd_ctrl_fifo_af_th : 4; /* [3:0] */ + u32 rsv_5 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rd_ctrl_fifo_af_th_u; + +/* Define the union csr_cpb_stl_api_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_stl_api_crdt : 5; /* [4:0] */ + u32 rsv_6 : 3; /* [7:5] */ + u32 cpb_stl_api_crdt_init : 1; /* [8] */ + u32 rsv_7 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_stl_api_crdt_init_u; + +/* Define the union csr_stl_str_di_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_di_fifo_af_th : 6; /* [5:0] */ + u32 rsv_8 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_str_di_fifo_af_th_u; + +/* Define the union csr_stl_str_api_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_api_fifo_af_th : 6; /* [5:0] */ + u32 rsv_9 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_str_api_fifo_af_th_u; + +/* Define the union csr_stl_cmd_api_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_cmd_api_fifo_af_th : 4; /* [3:0] */ + u32 rsv_10 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_cmd_api_fifo_af_th_u; + +/* Define the union csr_stl_ackstr_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_ackstr_fifo_af_th : 3; /* [2:0] */ + u32 rsv_11 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_ackstr_fifo_af_th_u; + +/* Define the union csr_cdt_crdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cdt_crdt_cfg : 5; /* [4:0] */ + u32 rsv_12 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cdt_crdt_cfg_u; + +/* Define the union csr_cdt_psh_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cdt_psh_fifo_af_th : 5; /* [4:0] */ + u32 rsv_13 : 3; /* [7:5] */ + u32 cdt_psh_fifo_ae_th : 5; /* [12:8] */ + u32 rsv_14 : 3; /* [15:13] */ + u32 ct_para_ret_cell_num_err_en : 1; /* [16] */ + u32 rsv_15 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cdt_psh_fifo_cfg_u; + +/* Define the union csr_stliq_psh_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlpsh_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_16 : 2; /* [7:6] */ + u32 stlpsh_fifo_af_th : 6; /* [13:8] */ + u32 rsv_17 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_psh_fifo_cfg_u; + +/* Define the union csr_inner_chn_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 inner_cpi_chn_map_mode : 1; /* [0] */ + u32 rsv_18 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_inner_chn_map_u; + +/* Define the union csr_drp_ack_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_ack_th : 4; /* [3:0] */ + u32 rsv_19 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_ack_th_u; + +/* Define the union csr_oqrx_pd_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oqrxpd_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_20 : 1; /* [7] */ + u32 oqrxpd_fifo_af_th : 7; /* [14:8] */ + u32 rsv_21 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oqrx_pd_fifo_cfg_u; + +/* Define the union csr_oqtx_pd_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oqtxpd_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_22 : 1; /* [7] */ + u32 oqtxpd_fifo_af_th : 7; /* [14:8] */ + u32 rsv_23 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oqtx_pd_fifo_cfg_u; + +/* Define the union csr_drp_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_24 : 1; /* [7] */ + u32 drp_fifo_af_th : 7; /* [14:8] */ + u32 rsv_25 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_fifo_cfg_u; + +/* Define the union csr_drp_txrls_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_txrls_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_26 : 1; /* [7] */ + u32 drp_txrls_fifo_af_th : 7; /* [14:8] */ + u32 rsv_27 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_txrls_fifo_cfg_u; + +/* Define the union csr_drp_rxrls_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_rxrls_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_28 : 1; /* [7] */ + u32 drp_rxrls_fifo_af_th : 7; /* [14:8] */ + u32 rsv_29 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_rxrls_fifo_cfg_u; + +/* Define the union csr_fdrp_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fdrp_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_30 : 2; /* [7:6] */ + u32 fdrp_fifo_af_th : 6; /* [13:8] */ + u32 rsv_31 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fdrp_fifo_cfg_u; + +/* Define the union csr_rx_nor_chn_wt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cell_req_wt00 : 3; /* [2:0] */ + u32 rsv_32 : 1; /* [3] */ + u32 perx_cell_req_wt01 : 3; /* [6:4] */ + u32 rsv_33 : 1; /* [7] */ + u32 perx_cell_req_wt02 : 3; /* [10:8] */ + u32 rsv_34 : 1; /* [11] */ + u32 perx_cell_req_wt03 : 3; /* [14:12] */ + u32 rsv_35 : 1; /* [15] */ + u32 perx_cell_req_wt04 : 3; /* [18:16] */ + u32 rsv_36 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_nor_chn_wt0_u; + +/* Define the union csr_rx_nor_chn_wt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cell_req_wt10 : 3; /* [2:0] */ + u32 rsv_37 : 1; /* [3] */ + u32 perx_cell_req_wt11 : 3; /* [6:4] */ + u32 rsv_38 : 1; /* [7] */ + u32 perx_cell_req_wt12 : 3; /* [10:8] */ + u32 rsv_39 : 1; /* [11] */ + u32 perx_cell_req_wt13 : 3; /* [14:12] */ + u32 rsv_40 : 1; /* [15] */ + u32 perx_cell_req_wt14 : 3; /* [18:16] */ + u32 rsv_41 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_nor_chn_wt1_u; + +/* Define the union csr_rx_nor_chn_wt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cell_req_wt20 : 3; /* [2:0] */ + u32 rsv_42 : 1; /* [3] */ + u32 perx_cell_req_wt21 : 3; /* [6:4] */ + u32 rsv_43 : 1; /* [7] */ + u32 perx_cell_req_wt22 : 3; /* [10:8] */ + u32 rsv_44 : 1; /* [11] */ + u32 perx_cell_req_wt23 : 3; /* [14:12] */ + u32 rsv_45 : 1; /* [15] */ + u32 perx_cell_req_wt24 : 3; /* [18:16] */ + u32 rsv_46 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_nor_chn_wt2_u; + +/* Define the union csr_rx_nor_chn_wt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cell_req_wt30 : 3; /* [2:0] */ + u32 rsv_47 : 1; /* [3] */ + u32 perx_cell_req_wt31 : 3; /* [6:4] */ + u32 rsv_48 : 1; /* [7] */ + u32 perx_cell_req_wt32 : 3; /* [10:8] */ + u32 rsv_49 : 1; /* [11] */ + u32 perx_cell_req_wt33 : 3; /* [14:12] */ + u32 rsv_50 : 1; /* [15] */ + u32 perx_cell_req_wt34 : 3; /* [18:16] */ + u32 rsv_51 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_nor_chn_wt3_u; + +/* Define the union csr_rx_lb_chn_wt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cell_req_wt40 : 3; /* [2:0] */ + u32 rsv_52 : 1; /* [3] */ + u32 perx_cell_req_wt41 : 3; /* [6:4] */ + u32 rsv_53 : 1; /* [7] */ + u32 perx_cell_req_wt42 : 3; /* [10:8] */ + u32 rsv_54 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_lb_chn_wt3_u; + +/* Define the union csr_rxlb_port_wt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb0_port0_wt : 3; /* [2:0] */ + u32 rsv_55 : 1; /* [3] */ + u32 rxlb0_port1_wt : 3; /* [6:4] */ + u32 rsv_56 : 1; /* [7] */ + u32 rxlb0_port2_wt : 3; /* [10:8] */ + u32 rsv_57 : 1; /* [11] */ + u32 rxlb0_port3_wt : 3; /* [14:12] */ + u32 rsv_58 : 1; /* [15] */ + u32 rxlb0_port4_wt : 3; /* [18:16] */ + u32 rsv_59 : 1; /* [19] */ + u32 rxlb0_port5_wt : 3; /* [22:20] */ + u32 rsv_60 : 1; /* [23] */ + u32 rxlb0_port6_wt : 3; /* [26:24] */ + u32 rsv_61 : 1; /* [27] */ + u32 rxlb0_port7_wt : 3; /* [30:28] */ + u32 rsv_62 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_port_wt_0_u; + +/* Define the union csr_rxlb_port_wt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb1_port0_wt : 3; /* [2:0] */ + u32 rsv_63 : 1; /* [3] */ + u32 rxlb1_port1_wt : 3; /* [6:4] */ + u32 rsv_64 : 1; /* [7] */ + u32 rxlb1_port2_wt : 3; /* [10:8] */ + u32 rsv_65 : 1; /* [11] */ + u32 rxlb1_port3_wt : 3; /* [14:12] */ + u32 rsv_66 : 1; /* [15] */ + u32 rxlb1_port4_wt : 3; /* [18:16] */ + u32 rsv_67 : 1; /* [19] */ + u32 rxlb1_port5_wt : 3; /* [22:20] */ + u32 rsv_68 : 1; /* [23] */ + u32 rxlb1_port6_wt : 3; /* [26:24] */ + u32 rsv_69 : 1; /* [27] */ + u32 rxlb1_port7_wt : 3; /* [30:28] */ + u32 rsv_70 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_port_wt_1_u; + +/* Define the union csr_cos_chn_rxlb_cfg_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_chn_rxlb_cfg_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cos_chn_rxlb_cfg_0_u; + +/* Define the union csr_cos_chn_rxlb_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_chn_rxlb_cfg_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cos_chn_rxlb_cfg_1_u; + +/* Define the union csr_cpb_rx_crdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_prealc_crdt : 4; /* [3:0] */ + u32 rsv_71 : 4; /* [7:4] */ + u32 dat_prealc_crdt_w : 5; /* [12:8] */ + u32 rsv_72 : 3; /* [15:13] */ + u32 dat_prealc_crdt_o : 5; /* [20:16] */ + u32 rsv_73 : 3; /* [23:21] */ + u32 dat_prealc_crdt_lb : 3; /* [26:24] */ + u32 rsv_74 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_crdt_cfg_u; + +/* Define the union csr_cpb_rx_idx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_idx_crdt : 6; /* [5:0] */ + u32 rsv_75 : 2; /* [7:6] */ + u32 perx_idx_bp_gap : 4; /* [11:8] */ + u32 rsv_76 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_idx_cfg_u; + +/* Define the union csr_chn5_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th0 : 10; /* [9:0] */ + u32 rsv_77 : 2; /* [11:10] */ + u32 chn_sge_shr_th0 : 10; /* [21:12] */ + u32 rsv_78 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn5_sge_cfg_u; + +/* Define the union csr_chn6_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th1 : 10; /* [9:0] */ + u32 rsv_79 : 2; /* [11:10] */ + u32 chn_sge_shr_th1 : 10; /* [21:12] */ + u32 rsv_80 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn6_sge_cfg_u; + +/* Define the union csr_chn7_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th2 : 10; /* [9:0] */ + u32 rsv_81 : 2; /* [11:10] */ + u32 chn_sge_shr_th2 : 10; /* [21:12] */ + u32 rsv_82 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn7_sge_cfg_u; + +/* Define the union csr_chn8_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th3 : 10; /* [9:0] */ + u32 rsv_83 : 2; /* [11:10] */ + u32 chn_sge_shr_th3 : 10; /* [21:12] */ + u32 rsv_84 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn8_sge_cfg_u; + +/* Define the union csr_chn9_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th4 : 10; /* [9:0] */ + u32 rsv_85 : 2; /* [11:10] */ + u32 chn_sge_shr_th4 : 10; /* [21:12] */ + u32 rsv_86 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn9_sge_cfg_u; + +/* Define the union csr_chn10_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th5 : 10; /* [9:0] */ + u32 rsv_87 : 2; /* [11:10] */ + u32 chn_sge_shr_th5 : 10; /* [21:12] */ + u32 rsv_88 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn10_sge_cfg_u; + +/* Define the union csr_chn11_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th6 : 10; /* [9:0] */ + u32 rsv_89 : 2; /* [11:10] */ + u32 chn_sge_shr_th6 : 10; /* [21:12] */ + u32 rsv_90 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn11_sge_cfg_u; + +/* Define the union csr_chn12_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th7 : 10; /* [9:0] */ + u32 rsv_91 : 2; /* [11:10] */ + u32 chn_sge_shr_th7 : 10; /* [21:12] */ + u32 rsv_92 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn12_sge_cfg_u; + +/* Define the union csr_chn13_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th8 : 10; /* [9:0] */ + u32 rsv_93 : 2; /* [11:10] */ + u32 chn_sge_shr_th8 : 10; /* [21:12] */ + u32 rsv_94 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn13_sge_cfg_u; + +/* Define the union csr_chn14_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th9 : 10; /* [9:0] */ + u32 rsv_95 : 2; /* [11:10] */ + u32 chn_sge_shr_th9 : 10; /* [21:12] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn14_sge_cfg_u; + +/* Define the union csr_chn15_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th10 : 10; /* [9:0] */ + u32 rsv_97 : 2; /* [11:10] */ + u32 chn_sge_shr_th10 : 10; /* [21:12] */ + u32 rsv_98 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn15_sge_cfg_u; + +/* Define the union csr_chn16_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th11 : 10; /* [9:0] */ + u32 rsv_99 : 2; /* [11:10] */ + u32 chn_sge_shr_th11 : 10; /* [21:12] */ + u32 rsv_100 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn16_sge_cfg_u; + +/* Define the union csr_chn17_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th12 : 10; /* [9:0] */ + u32 rsv_101 : 2; /* [11:10] */ + u32 chn_sge_shr_th12 : 10; /* [21:12] */ + u32 rsv_102 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn17_sge_cfg_u; + +/* Define the union csr_chn18_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th13 : 10; /* [9:0] */ + u32 rsv_103 : 2; /* [11:10] */ + u32 chn_sge_shr_th13 : 10; /* [21:12] */ + u32 rsv_104 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn18_sge_cfg_u; + +/* Define the union csr_chn19_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th14 : 10; /* [9:0] */ + u32 rsv_105 : 2; /* [11:10] */ + u32 chn_sge_shr_th14 : 10; /* [21:12] */ + u32 rsv_106 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn19_sge_cfg_u; + +/* Define the union csr_chn20_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th15 : 10; /* [9:0] */ + u32 rsv_107 : 2; /* [11:10] */ + u32 chn_sge_shr_th15 : 10; /* [21:12] */ + u32 rsv_108 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn20_sge_cfg_u; + +/* Define the union csr_chn21_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th16 : 10; /* [9:0] */ + u32 rsv_109 : 2; /* [11:10] */ + u32 chn_sge_shr_th16 : 10; /* [21:12] */ + u32 rsv_110 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn21_sge_cfg_u; + +/* Define the union csr_chn22_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th17 : 10; /* [9:0] */ + u32 rsv_111 : 2; /* [11:10] */ + u32 chn_sge_shr_th17 : 10; /* [21:12] */ + u32 rsv_112 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn22_sge_cfg_u; + +/* Define the union csr_chn23_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th18 : 10; /* [9:0] */ + u32 rsv_113 : 2; /* [11:10] */ + u32 chn_sge_shr_th18 : 10; /* [21:12] */ + u32 rsv_114 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn23_sge_cfg_u; + +/* Define the union csr_chn24_sge_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_sge_rsv_th19 : 10; /* [9:0] */ + u32 rsv_115 : 2; /* [11:10] */ + u32 chn_sge_shr_th19 : 10; /* [21:12] */ + u32 rsv_116 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn24_sge_cfg_u; + +/* Define the union csr_host0_sge_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_sge_th0 : 10; /* [9:0] */ + u32 rsv_117 : 6; /* [15:10] */ + u32 host_sge_w_th0 : 10; /* [25:16] */ + u32 rsv_118 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host0_sge_th_u; + +/* Define the union csr_host1_sge_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_sge_th1 : 10; /* [9:0] */ + u32 rsv_119 : 6; /* [15:10] */ + u32 host_sge_w_th1 : 10; /* [25:16] */ + u32 rsv_120 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host1_sge_th_u; + +/* Define the union csr_host2_sge_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_sge_th2 : 10; /* [9:0] */ + u32 rsv_121 : 6; /* [15:10] */ + u32 host_sge_w_th2 : 10; /* [25:16] */ + u32 rsv_122 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host2_sge_th_u; + +/* Define the union csr_host3_sge_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_sge_th3 : 10; /* [9:0] */ + u32 rsv_123 : 6; /* [15:10] */ + u32 host_sge_w_th3 : 10; /* [25:16] */ + u32 rsv_124 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host3_sge_th_u; + +/* Define the union csr_host4_sge_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_sge_th4 : 10; /* [9:0] */ + u32 rsv_125 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host4_sge_th_u; + +/* Define the union csr_sge_shr_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_shr_bp_th : 10; /* [9:0] */ + u32 rsv_126 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sge_shr_bp_th_u; + +/* Define the union csr_sge_bp_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_bp_gap : 5; /* [4:0] */ + u32 rsv_127 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sge_bp_gap_u; + +/* Define the union csr_chn5_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th0 : 10; /* [9:0] */ + u32 rsv_128 : 2; /* [11:10] */ + u32 chn_dat_shr_th0 : 10; /* [21:12] */ + u32 rsv_129 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn5_dat_cfg_u; + +/* Define the union csr_chn6_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th1 : 10; /* [9:0] */ + u32 rsv_130 : 2; /* [11:10] */ + u32 chn_dat_shr_th1 : 10; /* [21:12] */ + u32 rsv_131 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn6_dat_cfg_u; + +/* Define the union csr_chn7_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th2 : 10; /* [9:0] */ + u32 rsv_132 : 2; /* [11:10] */ + u32 chn_dat_shr_th2 : 10; /* [21:12] */ + u32 rsv_133 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn7_dat_cfg_u; + +/* Define the union csr_chn8_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th3 : 10; /* [9:0] */ + u32 rsv_134 : 2; /* [11:10] */ + u32 chn_dat_shr_th3 : 10; /* [21:12] */ + u32 rsv_135 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn8_dat_cfg_u; + +/* Define the union csr_chn9_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th4 : 10; /* [9:0] */ + u32 rsv_136 : 2; /* [11:10] */ + u32 chn_dat_shr_th4 : 10; /* [21:12] */ + u32 rsv_137 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn9_dat_cfg_u; + +/* Define the union csr_chn10_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th5 : 10; /* [9:0] */ + u32 rsv_138 : 2; /* [11:10] */ + u32 chn_dat_shr_th5 : 10; /* [21:12] */ + u32 rsv_139 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn10_dat_cfg_u; + +/* Define the union csr_chn11_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th6 : 10; /* [9:0] */ + u32 rsv_140 : 2; /* [11:10] */ + u32 chn_dat_shr_th6 : 10; /* [21:12] */ + u32 rsv_141 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn11_dat_cfg_u; + +/* Define the union csr_chn12_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th7 : 10; /* [9:0] */ + u32 rsv_142 : 2; /* [11:10] */ + u32 chn_dat_shr_th7 : 10; /* [21:12] */ + u32 rsv_143 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn12_dat_cfg_u; + +/* Define the union csr_chn13_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th8 : 10; /* [9:0] */ + u32 rsv_144 : 2; /* [11:10] */ + u32 chn_dat_shr_th8 : 10; /* [21:12] */ + u32 rsv_145 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn13_dat_cfg_u; + +/* Define the union csr_chn14_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th9 : 10; /* [9:0] */ + u32 rsv_146 : 2; /* [11:10] */ + u32 chn_dat_shr_th9 : 10; /* [21:12] */ + u32 rsv_147 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn14_dat_cfg_u; + +/* Define the union csr_chn15_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th10 : 10; /* [9:0] */ + u32 rsv_148 : 2; /* [11:10] */ + u32 chn_dat_shr_th10 : 10; /* [21:12] */ + u32 rsv_149 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn15_dat_cfg_u; + +/* Define the union csr_chn16_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th11 : 10; /* [9:0] */ + u32 rsv_150 : 2; /* [11:10] */ + u32 chn_dat_shr_th11 : 10; /* [21:12] */ + u32 rsv_151 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn16_dat_cfg_u; + +/* Define the union csr_chn17_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th12 : 10; /* [9:0] */ + u32 rsv_152 : 2; /* [11:10] */ + u32 chn_dat_shr_th12 : 10; /* [21:12] */ + u32 rsv_153 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn17_dat_cfg_u; + +/* Define the union csr_chn18_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th13 : 10; /* [9:0] */ + u32 rsv_154 : 2; /* [11:10] */ + u32 chn_dat_shr_th13 : 10; /* [21:12] */ + u32 rsv_155 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn18_dat_cfg_u; + +/* Define the union csr_chn19_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th14 : 10; /* [9:0] */ + u32 rsv_156 : 2; /* [11:10] */ + u32 chn_dat_shr_th14 : 10; /* [21:12] */ + u32 rsv_157 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn19_dat_cfg_u; + +/* Define the union csr_chn20_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th15 : 10; /* [9:0] */ + u32 rsv_158 : 2; /* [11:10] */ + u32 chn_dat_shr_th15 : 10; /* [21:12] */ + u32 rsv_159 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn20_dat_cfg_u; + +/* Define the union csr_chn21_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th16 : 10; /* [9:0] */ + u32 rsv_160 : 2; /* [11:10] */ + u32 chn_dat_shr_th16 : 10; /* [21:12] */ + u32 rsv_161 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn21_dat_cfg_u; + +/* Define the union csr_chn22_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th17 : 10; /* [9:0] */ + u32 rsv_162 : 2; /* [11:10] */ + u32 chn_dat_shr_th17 : 10; /* [21:12] */ + u32 rsv_163 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn22_dat_cfg_u; + +/* Define the union csr_chn23_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th18 : 10; /* [9:0] */ + u32 rsv_164 : 2; /* [11:10] */ + u32 chn_dat_shr_th18 : 10; /* [21:12] */ + u32 rsv_165 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn23_dat_cfg_u; + +/* Define the union csr_chn24_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chn_dat_rsv_th19 : 10; /* [9:0] */ + u32 rsv_166 : 2; /* [11:10] */ + u32 chn_dat_shr_th19 : 10; /* [21:12] */ + u32 rsv_167 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_chn24_dat_cfg_u; + +/* Define the union csr_host0_dat_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_dat_th0 : 10; /* [9:0] */ + u32 rsv_168 : 6; /* [15:10] */ + u32 host_dat_w_th0 : 10; /* [25:16] */ + u32 rsv_169 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host0_dat_th_u; + +/* Define the union csr_host1_dat_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_dat_th1 : 10; /* [9:0] */ + u32 rsv_170 : 6; /* [15:10] */ + u32 host_dat_w_th1 : 10; /* [25:16] */ + u32 rsv_171 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host1_dat_th_u; + +/* Define the union csr_host2_dat_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_dat_th2 : 10; /* [9:0] */ + u32 rsv_172 : 6; /* [15:10] */ + u32 host_dat_w_th2 : 10; /* [25:16] */ + u32 rsv_173 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host2_dat_th_u; + +/* Define the union csr_host3_dat_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_dat_th3 : 10; /* [9:0] */ + u32 rsv_174 : 6; /* [15:10] */ + u32 host_dat_w_th3 : 10; /* [25:16] */ + u32 rsv_175 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host3_dat_th_u; + +/* Define the union csr_host4_dat_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_dat_th4 : 10; /* [9:0] */ + u32 rsv_176 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host4_dat_th_u; + +/* Define the union csr_dat_shr_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_shr_bp_th : 10; /* [9:0] */ + u32 rsv_177 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dat_shr_bp_th_u; + +/* Define the union csr_dat_bp_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_bp_gap : 5; /* [4:0] */ + u32 rsv_178 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dat_bp_gap_u; + +/* Define the union csr_rx_mpu_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_mpu_crdt_th : 7; /* [6:0] */ + u32 rsv_179 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_mpu_dat_cfg_u; + +/* Define the union csr_rx_lb0_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_lb_crdt_th0 : 7; /* [6:0] */ + u32 rsv_180 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_lb0_dat_cfg_u; + +/* Define the union csr_rx_lb1_dat_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_lb_crdt_th1 : 7; /* [6:0] */ + u32 rsv_181 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_lb1_dat_cfg_u; + +/* Define the union csr_rxlb_dat_bp_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb_dat_bp_gap : 4; /* [3:0] */ + u32 rsv_182 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_dat_bp_gap_u; + +/* Define the union csr_rxpd_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_183 : 2; /* [7:6] */ + u32 rxpd_fifo_af_th : 6; /* [13:8] */ + u32 rsv_184 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_cfg_u; + +/* Define the union csr_rxmpu_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxmpu_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_185 : 2; /* [7:6] */ + u32 rxmpu_fifo_af_th : 6; /* [13:8] */ + u32 rsv_186 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxmpu_fifo_cfg_u; + +/* Define the union csr_rxlb_cos_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb_cos_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_187 : 2; /* [7:6] */ + u32 rxlb_cos_fifo_af_th : 6; /* [13:8] */ + u32 rsv_188 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_cos_fifo_cfg_u; + +/* Define the union csr_rx_idx_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpr_idx_req_wt0 : 3; /* [2:0] */ + u32 rsv_189 : 1; /* [3] */ + u32 cpr_idx_req_wt1 : 3; /* [6:4] */ + u32 rsv_190 : 1; /* [7] */ + u32 cpr_idx_req_wt2 : 3; /* [10:8] */ + u32 rsv_191 : 1; /* [11] */ + u32 cpr_idx_req_wt3 : 3; /* [14:12] */ + u32 rsv_192 : 1; /* [15] */ + u32 cpr_idx_req_wt4 : 3; /* [18:16] */ + u32 rsv_193 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_idx_wt_u; + +/* Define the union csr_rx_host0_chn_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_chn_more_cfg : 1; /* [0] */ + u32 rsv_194 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_host0_chn_m_u; + +/* Define the union csr_rx_tso3_rls_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_tso3_rls_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_195 : 1; /* [7] */ + u32 rx_tso3_rls_fifo_af_th : 7; /* [14:8] */ + u32 rsv_196 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_tso3_rls_fifo_cfg_u; + +/* Define the union csr_stl_cmd_api_rd_req_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_cmd_api_fifo_sta : 11; /* [10:0] */ + u32 rsv_197 : 5; /* [15:11] */ + u32 stl_rd_req_fifo_sta : 11; /* [26:16] */ + u32 rsv_198 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_cmd_api_rd_req_fifo_sta_u; + +/* Define the union csr_stl_str_api_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_str_api_fifo_sta : 11; /* [10:0] */ + u32 rsv_199 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_str_api_fifo_sta_u; + +/* Define the union csr_stl_wr_rd_dat_in_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_wr_di_fifo_sta : 11; /* [10:0] */ + u32 rsv_200 : 5; /* [15:11] */ + u32 stl_rd_di_fifo_sta : 11; /* [26:16] */ + u32 rsv_201 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_wr_rd_dat_in_fifo_sta_u; + +/* Define the union csr_stl_rsp_api_hdr_dat_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_api_dat_fifo_sta : 11; /* [10:0] */ + u32 rsv_202 : 5; /* [15:11] */ + u32 stl_rsp_api_hdr_fifo_sta : 11; /* [26:16] */ + u32 rsv_203 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rsp_api_hdr_dat_fifo_sta_u; + +/* Define the union csr_stl_rsp_api_cd_crc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_api_crc_fifo_sta : 11; /* [10:0] */ + u32 rsv_204 : 5; /* [15:11] */ + u32 stl_rsp_api_cd_fifo_sta : 11; /* [26:16] */ + u32 rsv_205 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rsp_api_cd_crc_fifo_sta_u; + +/* Define the union csr_stl_rsp_api_cs_nptr_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_api_nptr_fifo_sta : 11; /* [10:0] */ + u32 rsv_206 : 5; /* [15:11] */ + u32 stl_rsp_api_cs_fifo_sta : 11; /* [26:16] */ + u32 rsv_207 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_rsp_api_cs_nptr_fifo_sta_u; + +/* Define the union csr_stl_str_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_cmd_cnt : 16; /* [15:0] */ + u32 stl_str_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_str_cmd_cnt_u; + +/* Define the union csr_stl_ack_rsp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_cnt : 16; /* [15:0] */ + u32 stl_ack_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_ack_rsp_cnt_u; + +/* Define the union csr_stl_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_psh_tl_cnt : 16; /* [15:0] */ + u32 stl_iq_psh_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_psh_cnt_u; + +/* Define the union csr_stl_cell_mdf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_cell_mdf_cnt : 16; /* [15:0] */ + u32 rsv_208 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_cell_mdf_cnt_u; + +/* Define the union csr_stl_wr_di_ctrl_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_wr_di_ctrl_fifo_sta : 11; /* [10:0] */ + u32 rsv_209 : 5; /* [15:11] */ + u32 stl_ackstr_fifo_sta : 11; /* [26:16] */ + u32 rsv_210 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_wr_di_ctrl_fifo_sta_u; + +/* Define the union csr_stl_fifo_ov_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rd_req_fifo_ov : 4; /* [3:0] */ + u32 stl_cmd_api_fifo_ov : 4; /* [7:4] */ + u32 stl_str_api_fifo_ov : 4; /* [11:8] */ + u32 stl_rd_di_fifo_ov : 2; /* [13:12] */ + u32 rsv_211 : 2; /* [15:14] */ + u32 stl_wr_di_fifo_ov : 2; /* [17:16] */ + u32 rsv_212 : 2; /* [19:18] */ + u32 stl_wr_di_ctrl_fifo_ov : 2; /* [21:20] */ + u32 rsv_213 : 2; /* [23:22] */ + u32 stl_ackstr_fifo_ov : 2; /* [25:24] */ + u32 rsv_214 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_fifo_ov_err_0_u; + +/* Define the union csr_stl_fifo_ov_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_api_hdr_fifo_ov : 4; /* [3:0] */ + u32 stl_rsp_api_dat_fifo_ov : 4; /* [7:4] */ + u32 stl_rsp_api_cd_fifo_ov : 4; /* [11:8] */ + u32 stl_rsp_api_crc_fifo_ov : 4; /* [15:12] */ + u32 stl_rsp_api_cs_fifo_ov : 4; /* [19:16] */ + u32 stl_rsp_api_nptr_fifo_ov : 4; /* [23:20] */ + u32 rsv_215 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_fifo_ov_err_1_u; + +/* Define the union csr_stl_fifo_uf_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rd_req_fifo_uf : 4; /* [3:0] */ + u32 stl_cmd_api_fifo_uf : 4; /* [7:4] */ + u32 stl_str_api_fifo_uf : 4; /* [11:8] */ + u32 stl_rd_di_fifo_uf : 2; /* [13:12] */ + u32 rsv_216 : 2; /* [15:14] */ + u32 stl_wr_di_fifo_uf : 2; /* [17:16] */ + u32 rsv_217 : 2; /* [19:18] */ + u32 stl_wr_di_ctrl_fifo_uf : 2; /* [21:20] */ + u32 rsv_218 : 2; /* [23:22] */ + u32 stl_ackstr_fifo_uf : 2; /* [25:24] */ + u32 rsv_219 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_fifo_uf_err_0_u; + +/* Define the union csr_stl_fifo_uf_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_rsp_api_hdr_fifo_uf : 4; /* [3:0] */ + u32 stl_rsp_api_dat_fifo_uf : 4; /* [7:4] */ + u32 stl_rsp_api_cd_fifo_uf : 4; /* [11:8] */ + u32 stl_rsp_api_crc_fifo_uf : 4; /* [15:12] */ + u32 stl_rsp_api_cs_fifo_uf : 4; /* [19:16] */ + u32 stl_rsp_api_nptr_fifo_uf : 4; /* [23:20] */ + u32 rsv_220 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stl_fifo_uf_err_1_u; + +/* Define the union csr_stlwr_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlwr_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_221 : 7; /* [11:5] */ + u32 stlwr_fifo_mem_err_cerr : 1; /* [12] */ + u32 stlwr_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_222 : 2; /* [15:14] */ + u32 stlwr_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stlwr_fifo_ram_err_u; + +/* Define the union csr_stlstr_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlstr_fifo_mem_err_addr : 6; /* [5:0] */ + u32 rsv_223 : 6; /* [11:6] */ + u32 stlstr_fifo_mem_err_cerr : 1; /* [12] */ + u32 stlstr_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_224 : 2; /* [15:14] */ + u32 stlstr_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stlstr_fifo_ram_err_u; + +/* Define the union csr_stlrsp_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlrsp_fifo_mem_err_addr : 5; /* [4:0] */ + u32 rsv_225 : 7; /* [11:5] */ + u32 stlrsp_fifo_mem_err_cerr : 1; /* [12] */ + u32 stlrsp_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_226 : 2; /* [15:14] */ + u32 stlrsp_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stlrsp_fifo_ram_err_u; + +/* Define the union csr_cdt_psh_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_227 : 9; /* [8:0] */ + u32 psh_ctrl_fifo1_sta : 9; /* [17:9] */ + u32 psh_dat_fifo1_sta : 9; /* [26:18] */ + u32 rsv_228 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cdt_psh_fifo_sta_u; + +/* Define the union csr_cdt_fifo_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cdt_psh_fifo_of_err : 3; /* [2:0] */ + u32 cdt_psh_fifo_uf_err : 3; /* [5:3] */ + u32 rsv_229 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cdt_fifo_err_u; + +/* Define the union csr_cdt_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cdt_crdt_cnt : 5; /* [4:0] */ + u32 rsv_230 : 3; /* [7:5] */ + u32 cdt_crdt_of_err : 1; /* [8] */ + u32 cdt_crdt_uf_err : 1; /* [9] */ + u32 geneve_flowpac_ofs_err : 1; /* [10] */ + u32 rsv_231 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cdt_crdt_sta_u; + +/* Define the union csr_stliq_pkt_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_pkt_psh_cnt : 16; /* [15:0] */ + u32 rsv_232 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_pkt_psh_cnt_u; + +/* Define the union csr_stliq_msg_psh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_msg_psh_cnt : 16; /* [15:0] */ + u32 rsv_233 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_msg_psh_cnt_u; + +/* Define the union csr_flowpac_psh_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flowpac_psh_req_cnt : 16; /* [15:0] */ + u32 rsv_234 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flowpac_psh_req_cnt_u; + +/* Define the union csr_nonflowpac_psh_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nonflowpac_psh_req_cnt : 16; /* [15:0] */ + u32 rsv_235 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nonflowpac_psh_req_cnt_u; + +/* Define the union csr_stliq_psh_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_psh_fifo_sta : 10; /* [9:0] */ + u32 rsv_236 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_stliq_psh_fifo_sta_u; + +/* Define the union csr_rob_psh_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rob_psh_fifo_sta : 10; /* [9:0] */ + u32 rsv_237 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rob_psh_fifo_sta_u; + +/* Define the union csr_rx_epd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_epd_cnt : 16; /* [15:0] */ + u32 rsv_238 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_epd_cnt_u; + +/* Define the union csr_rx_chn_epd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_epd_cnt : 16; /* [15:0] */ + u32 rsv_239 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_chn_epd_cnt_u; + +/* Define the union csr_tx_epd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epd_cnt : 16; /* [15:0] */ + u32 rsv_240 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_epd_cnt_u; + +/* Define the union csr_tx_chn_epd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_epd_cnt : 16; /* [15:0] */ + u32 rsv_241 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_epd_cnt_u; + +/* Define the union csr_txmac_chn_tso12_epd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txmac_chn_tso12_epd_cnt : 16; /* [15:0] */ + u32 rsv_242 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txmac_chn_tso12_epd_cnt_u; + +/* Define the union csr_drp_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_req_cnt : 16; /* [15:0] */ + u32 rsv_243 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_req_cnt_u; + +/* Define the union csr_rx_tso3_drp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_tso3_prls_cnt : 16; /* [15:0] */ + u32 rx_tso3_drp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_tso3_drp_cnt_u; + +/* Define the union csr_tx_tso3_drp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tso3_prls_cnt : 16; /* [15:0] */ + u32 tx_tso3_drp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_tso3_drp_cnt_u; + +/* Define the union csr_drp_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_eop_cnt : 16; /* [15:0] */ + u32 rsv_244 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_eop_cnt_u; + +/* Define the union csr_rx_epd_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_epd_fifo_sta : 11; /* [10:0] */ + u32 rsv_245 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_epd_fifo_sta_u; + +/* Define the union csr_tx_epd_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epd_fifo_sta : 11; /* [10:0] */ + u32 rsv_246 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_epd_fifo_sta_u; + +/* Define the union csr_ndrp_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ndrp_fifo_sta : 11; /* [10:0] */ + u32 rsv_247 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ndrp_fifo_sta_u; + +/* Define the union csr_drp_rxrls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_rxrls_fifo_sta : 11; /* [10:0] */ + u32 rsv_248 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_rxrls_fifo_sta_u; + +/* Define the union csr_drp_txrls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 drp_txrls_fifo_sta : 11; /* [10:0] */ + u32 rsv_249 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_drp_txrls_fifo_sta_u; + +/* Define the union csr_fdrp_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fdrp_fifo_sta : 11; /* [10:0] */ + u32 rsv_250 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fdrp_fifo_sta_u; + +/* Define the union csr_ftso_drp_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ftso_drp_req_cnt : 16; /* [15:0] */ + u32 rsv_251 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ftso_drp_req_cnt_u; + +/* Define the union csr_coq_fifo_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_epd_fifo_of_err : 1; /* [0] */ + u32 tx_epd_fifo_of_err : 1; /* [1] */ + u32 ndrp_fifo_of_err : 1; /* [2] */ + u32 drp_txrls_fifo_of_err : 1; /* [3] */ + u32 drp_rxrls_fifo_of_err : 1; /* [4] */ + u32 fdrp_fifo_of_err : 1; /* [5] */ + u32 rsv_252 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_coq_fifo_of_err_u; + +/* Define the union csr_coq_fifo_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_epd_fifo_uf_err : 1; /* [0] */ + u32 tx_epd_fifo_uf_err : 1; /* [1] */ + u32 ndrp_fifo_uf_err : 1; /* [2] */ + u32 drp_txrls_fifo_uf_err : 1; /* [3] */ + u32 drp_rxrls_fifo_uf_err : 1; /* [4] */ + u32 fdrp_fifo_uf_err : 1; /* [5] */ + u32 rsv_253 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_coq_fifo_uf_err_u; + +/* Define the union csr_coq_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_cpi_chn_err : 1; /* [0] */ + u32 rx_pkt_mode_err : 1; /* [1] */ + u32 rx_pcnum_srch_err : 1; /* [2] */ + u32 tx_lb_chn_err : 1; /* [3] */ + u32 tx_pkt_mode_err : 1; /* [4] */ + u32 tx_pcnum_srch_err : 1; /* [5] */ + u32 rsv_254 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_coq_err_u; + +/* Define the union csr_rx_cpi_chn_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_chnsge_crdt_cnt : 10; /* [9:0] */ + u32 rsv_255 : 2; /* [11:10] */ + u32 cpi_chnsge_crdt_af : 1; /* [12] */ + u32 rsv_256 : 3; /* [15:13] */ + u32 cpi_chndat_crdt_cnt : 10; /* [25:16] */ + u32 rsv_257 : 2; /* [27:26] */ + u32 cpi_chndat_crdt_af : 1; /* [28] */ + u32 rsv_258 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_cpi_chn_crdt_sta_u; + +/* Define the union csr_rx_cpi_host_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_hostsge_crdt_cnt : 10; /* [9:0] */ + u32 rsv_259 : 2; /* [11:10] */ + u32 cpi_hostsge_crdt_af : 1; /* [12] */ + u32 rsv_260 : 3; /* [15:13] */ + u32 cpi_hostdat_crdt_cnt : 10; /* [25:16] */ + u32 rsv_261 : 2; /* [27:26] */ + u32 cpi_hostdat_crdt_af : 1; /* [28] */ + u32 rsv_262 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_cpi_host_crdt_sta_u; + +/* Define the union csr_rx_cpi_shr_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_shrsge_crdt_cnt : 10; /* [9:0] */ + u32 rsv_263 : 2; /* [11:10] */ + u32 cpi_shrsge_crdt_af : 1; /* [12] */ + u32 rsv_264 : 3; /* [15:13] */ + u32 cpi_shrdat_crdt_cnt : 10; /* [25:16] */ + u32 rsv_265 : 2; /* [27:26] */ + u32 cpi_shrdat_crdt_af : 1; /* [28] */ + u32 rsv_266 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_cpi_shr_crdt_sta_u; + +/* Define the union csr_rx_cpi_host_wcrdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_host_wsge_crdt_cnt : 10; /* [9:0] */ + u32 rsv_267 : 2; /* [11:10] */ + u32 cpb_pqm_hostsge_crdt_bp : 1; /* [12] */ + u32 rsv_268 : 3; /* [15:13] */ + u32 cpi_host_wdat_crdt_cnt : 10; /* [25:16] */ + u32 rsv_269 : 2; /* [27:26] */ + u32 cpb_pqm_hostdat_crdt_bp : 1; /* [28] */ + u32 rsv_270 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_cpi_host_wcrdt_sta_u; + +/* Define the union csr_rxlb_chn_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb_chn_crdt_cnt : 7; /* [6:0] */ + u32 rsv_271 : 1; /* [7] */ + u32 rxlb_chn_crdt_af : 1; /* [8] */ + u32 rsv_272 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_chn_crdt_sta_u; + +/* Define the union csr_rx_idx_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_idx_crdt_cnt : 6; /* [5:0] */ + u32 rsv_273 : 2; /* [7:6] */ + u32 rx_idx_crdt_af : 1; /* [8] */ + u32 rsv_274 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_idx_crdt_sta_u; + +/* Define the union csr_rxlb_fp_bmp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb_fp_bmp_fill : 11; /* [10:0] */ + u32 rsv_275 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_fp_bmp_sta_u; + +/* Define the union csr_rxpd_fifo_empty_sta_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_empty_sta_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_empty_sta_0_u; + +/* Define the union csr_rxpd_fifo_empty_sta_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_empty_sta_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_empty_sta_1_u; + +/* Define the union csr_rxpd_fifo_empty_sta_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_empty_sta_2 : 21; /* [20:0] */ + u32 rsv_276 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_empty_sta_2_u; + +/* Define the union csr_rxpd_fifo_fill_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_fill_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_fill_sta_u; + +/* Define the union csr_rxpd_pro_fsm_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_pro_fsm_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_pro_fsm_sta_u; + +/* Define the union csr_rx_crdt_of_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_idx_crdt_of_err : 1; /* [0] */ + u32 rxlb_chn_crdt_of_err : 3; /* [3:1] */ + u32 cpi_chn_dat_crdt_of_err : 20; /* [23:4] */ + u32 rsv_277 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_crdt_of_err_0_u; + +/* Define the union csr_rx_crdt_of_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_chn_sge_crdt_of_err : 20; /* [19:0] */ + u32 rsv_278 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_crdt_of_err_1_u; + +/* Define the union csr_rx_crdt_uf_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_idx_crdt_uf_err : 1; /* [0] */ + u32 rxlb_chn_crdt_uf_err : 3; /* [3:1] */ + u32 cpi_chn_dat_crdt_uf_err : 20; /* [23:4] */ + u32 rsv_279 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_crdt_uf_err_0_u; + +/* Define the union csr_rx_crdt_uf_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_chn_sge_crdt_uf_err : 20; /* [19:0] */ + u32 rsv_280 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_crdt_uf_err_1_u; + +/* Define the union csr_rxpd_fifo_of_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_of_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_of_err_0_u; + +/* Define the union csr_rxpd_fifo_of_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_of_err_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_of_err_1_u; + +/* Define the union csr_rxpd_fifo_of_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_of_err_2 : 21; /* [20:0] */ + u32 rxlb_fp_fifo_of_err : 1; /* [21] */ + u32 rx_tso3_rls_fifo_of_err : 5; /* [26:22] */ + u32 rsv_281 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_of_err_2_u; + +/* Define the union csr_rxpd_fifo_uf_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_uf_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_uf_err_0_u; + +/* Define the union csr_rxpd_fifo_uf_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_uf_err_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_uf_err_1_u; + +/* Define the union csr_rxpd_fifo_uf_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxpd_fifo_uf_err_2 : 21; /* [20:0] */ + u32 rxlb_fp_fifo_uf_err : 1; /* [21] */ + u32 rx_tso3_rls_fifo_uf_err : 5; /* [26:22] */ + u32 rsv_282 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxpd_fifo_uf_err_2_u; + +/* Define the union csr_rxlb_pd_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxlb_pd_mem_err_addr : 10; /* [9:0] */ + u32 rsv_283 : 2; /* [11:10] */ + u32 rxlb_pd_mem_err_cerr : 1; /* [12] */ + u32 rxlb_pd_mem_err_ucerr : 1; /* [13] */ + u32 rsv_284 : 2; /* [15:14] */ + u32 rxlb_pd_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rxlb_pd_ram_err_u; + +/* Define the union csr_cpb_rx_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_pd_pptr_err : 23; /* [22:0] */ + u32 rsv_285 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_0_u; + +/* Define the union csr_cpb_rx_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_pd_pktmod_err : 23; /* [22:0] */ + u32 rsv_286 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_1_u; + +/* Define the union csr_cpb_rx_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_ret_pcnum_err : 23; /* [22:0] */ + u32 rsv_287 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_2_u; + +/* Define the union csr_cpb_rx_err_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_tso2_err : 23; /* [22:0] */ + u32 rx_chn_tso2_num_err : 1; /* [23] */ + u32 rx_chn_tso2_cmd_cnum_err0 : 1; /* [24] */ + u32 rx_chn_tso2_cmd_cnum_err1 : 1; /* [25] */ + u32 rx_chn_tso2_cmd_cnum_err2 : 1; /* [26] */ + u32 rsv_288 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_3_u; + +/* Define the union csr_cpb_rx_err_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_lro1_err : 23; /* [22:0] */ + u32 rx_chn_lro1_num_err : 1; /* [23] */ + u32 rx_chn_lro1_cmd_cnum_err : 1; /* [24] */ + u32 rsv_289 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_4_u; + +/* Define the union csr_cpb_rx_err_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_chn_lro2_err : 23; /* [22:0] */ + u32 rx_chn_lro2_num_err : 1; /* [23] */ + u32 rx_chn_lro2_cmd_cnum_err0 : 1; /* [24] */ + u32 rx_chn_lro2_cmd_cnum_err1 : 1; /* [25] */ + u32 rx_chn_lro2_cmd_cnum_err2 : 1; /* [26] */ + u32 rsv_290 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_rx_err_5_u; + +/* Define the union csr_rx_tso3_rls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_tso3_rls_fifo_sta : 11; /* [10:0] */ + u32 rsv_291 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_tso3_rls_fifo_sta_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_stl_rsp_api_fifo_crdt_init_u stl_rsp_api_fifo_crdt_init; /* 800 */ + volatile csr_stl_psh_cmd_wt_u stl_psh_cmd_wt; /* 804 */ + volatile csr_stl_rd_req_fifo_af_th_u stl_rd_req_fifo_af_th; /* 80C */ + volatile csr_stl_rd_ctrl_fifo_af_th_u stl_rd_ctrl_fifo_af_th; /* 810 */ + volatile csr_cpb_stl_api_crdt_init_u cpb_stl_api_crdt_init; /* 814 */ + volatile csr_stl_str_di_fifo_af_th_u stl_str_di_fifo_af_th; /* 818 */ + volatile csr_stl_str_api_fifo_af_th_u stl_str_api_fifo_af_th; /* 81C */ + volatile csr_stl_cmd_api_fifo_af_th_u stl_cmd_api_fifo_af_th; /* 820 */ + volatile csr_stl_ackstr_fifo_af_th_u stl_ackstr_fifo_af_th; /* 824 */ + volatile csr_cdt_crdt_cfg_u cdt_crdt_cfg; /* 8A0 */ + volatile csr_cdt_psh_fifo_cfg_u cdt_psh_fifo_cfg; /* 8B0 */ + volatile csr_stliq_psh_fifo_cfg_u stliq_psh_fifo_cfg; /* 900 */ + volatile csr_inner_chn_map_u inner_chn_map; /* 980 */ + volatile csr_drp_ack_th_u drp_ack_th; /* 984 */ + volatile csr_oqrx_pd_fifo_cfg_u oqrx_pd_fifo_cfg; /* 990 */ + volatile csr_oqtx_pd_fifo_cfg_u oqtx_pd_fifo_cfg; /* 994 */ + volatile csr_drp_fifo_cfg_u drp_fifo_cfg; /* 998 */ + volatile csr_drp_txrls_fifo_cfg_u drp_txrls_fifo_cfg; /* 99C */ + volatile csr_drp_rxrls_fifo_cfg_u drp_rxrls_fifo_cfg; /* 9A0 */ + volatile csr_fdrp_fifo_cfg_u fdrp_fifo_cfg; /* 9A4 */ + volatile csr_rx_nor_chn_wt0_u rx_nor_chn_wt0; /* A00 */ + volatile csr_rx_nor_chn_wt1_u rx_nor_chn_wt1; /* A04 */ + volatile csr_rx_nor_chn_wt2_u rx_nor_chn_wt2; /* A08 */ + volatile csr_rx_nor_chn_wt3_u rx_nor_chn_wt3; /* A0C */ + volatile csr_rx_lb_chn_wt3_u rx_lb_chn_wt3; /* A10 */ + volatile csr_rxlb_port_wt_0_u rxlb_port_wt_0; /* A14 */ + volatile csr_rxlb_port_wt_1_u rxlb_port_wt_1; /* A18 */ + volatile csr_cos_chn_rxlb_cfg_0_u cos_chn_rxlb_cfg_0; /* A1C */ + volatile csr_cos_chn_rxlb_cfg_1_u cos_chn_rxlb_cfg_1; /* A20 */ + volatile csr_cpb_rx_crdt_cfg_u cpb_rx_crdt_cfg; /* A30 */ + volatile csr_cpb_rx_idx_cfg_u cpb_rx_idx_cfg; /* A34 */ + volatile csr_chn5_sge_cfg_u chn5_sge_cfg; /* A40 */ + volatile csr_chn6_sge_cfg_u chn6_sge_cfg; /* A44 */ + volatile csr_chn7_sge_cfg_u chn7_sge_cfg; /* A48 */ + volatile csr_chn8_sge_cfg_u chn8_sge_cfg; /* A4C */ + volatile csr_chn9_sge_cfg_u chn9_sge_cfg; /* A50 */ + volatile csr_chn10_sge_cfg_u chn10_sge_cfg; /* A54 */ + volatile csr_chn11_sge_cfg_u chn11_sge_cfg; /* A58 */ + volatile csr_chn12_sge_cfg_u chn12_sge_cfg; /* A5C */ + volatile csr_chn13_sge_cfg_u chn13_sge_cfg; /* A60 */ + volatile csr_chn14_sge_cfg_u chn14_sge_cfg; /* A64 */ + volatile csr_chn15_sge_cfg_u chn15_sge_cfg; /* A68 */ + volatile csr_chn16_sge_cfg_u chn16_sge_cfg; /* A6C */ + volatile csr_chn17_sge_cfg_u chn17_sge_cfg; /* A70 */ + volatile csr_chn18_sge_cfg_u chn18_sge_cfg; /* A74 */ + volatile csr_chn19_sge_cfg_u chn19_sge_cfg; /* A78 */ + volatile csr_chn20_sge_cfg_u chn20_sge_cfg; /* A7C */ + volatile csr_chn21_sge_cfg_u chn21_sge_cfg; /* A80 */ + volatile csr_chn22_sge_cfg_u chn22_sge_cfg; /* A84 */ + volatile csr_chn23_sge_cfg_u chn23_sge_cfg; /* A88 */ + volatile csr_chn24_sge_cfg_u chn24_sge_cfg; /* A8C */ + volatile csr_host0_sge_th_u host0_sge_th; /* A90 */ + volatile csr_host1_sge_th_u host1_sge_th; /* A94 */ + volatile csr_host2_sge_th_u host2_sge_th; /* A98 */ + volatile csr_host3_sge_th_u host3_sge_th; /* A9C */ + volatile csr_host4_sge_th_u host4_sge_th; /* AA0 */ + volatile csr_sge_shr_bp_th_u sge_shr_bp_th; /* AA4 */ + volatile csr_sge_bp_gap_u sge_bp_gap; /* AA8 */ + volatile csr_chn5_dat_cfg_u chn5_dat_cfg; /* AB0 */ + volatile csr_chn6_dat_cfg_u chn6_dat_cfg; /* AB4 */ + volatile csr_chn7_dat_cfg_u chn7_dat_cfg; /* AB8 */ + volatile csr_chn8_dat_cfg_u chn8_dat_cfg; /* ABC */ + volatile csr_chn9_dat_cfg_u chn9_dat_cfg; /* AC0 */ + volatile csr_chn10_dat_cfg_u chn10_dat_cfg; /* AC4 */ + volatile csr_chn11_dat_cfg_u chn11_dat_cfg; /* AC8 */ + volatile csr_chn12_dat_cfg_u chn12_dat_cfg; /* ACC */ + volatile csr_chn13_dat_cfg_u chn13_dat_cfg; /* AD0 */ + volatile csr_chn14_dat_cfg_u chn14_dat_cfg; /* AD4 */ + volatile csr_chn15_dat_cfg_u chn15_dat_cfg; /* AD8 */ + volatile csr_chn16_dat_cfg_u chn16_dat_cfg; /* ADC */ + volatile csr_chn17_dat_cfg_u chn17_dat_cfg; /* AE0 */ + volatile csr_chn18_dat_cfg_u chn18_dat_cfg; /* AE4 */ + volatile csr_chn19_dat_cfg_u chn19_dat_cfg; /* AE8 */ + volatile csr_chn20_dat_cfg_u chn20_dat_cfg; /* AEC */ + volatile csr_chn21_dat_cfg_u chn21_dat_cfg; /* AF0 */ + volatile csr_chn22_dat_cfg_u chn22_dat_cfg; /* AF4 */ + volatile csr_chn23_dat_cfg_u chn23_dat_cfg; /* AF8 */ + volatile csr_chn24_dat_cfg_u chn24_dat_cfg; /* AFC */ + volatile csr_host0_dat_th_u host0_dat_th; /* B00 */ + volatile csr_host1_dat_th_u host1_dat_th; /* B04 */ + volatile csr_host2_dat_th_u host2_dat_th; /* B08 */ + volatile csr_host3_dat_th_u host3_dat_th; /* B0C */ + volatile csr_host4_dat_th_u host4_dat_th; /* B10 */ + volatile csr_dat_shr_bp_th_u dat_shr_bp_th; /* B14 */ + volatile csr_dat_bp_gap_u dat_bp_gap; /* B18 */ + volatile csr_rx_mpu_dat_cfg_u rx_mpu_dat_cfg; /* B20 */ + volatile csr_rx_lb0_dat_cfg_u rx_lb0_dat_cfg; /* B24 */ + volatile csr_rx_lb1_dat_cfg_u rx_lb1_dat_cfg; /* B28 */ + volatile csr_rxlb_dat_bp_gap_u rxlb_dat_bp_gap; /* B30 */ + volatile csr_rxpd_fifo_cfg_u rxpd_fifo_cfg; /* B40 */ + volatile csr_rxmpu_fifo_cfg_u rxmpu_fifo_cfg; /* B44 */ + volatile csr_rxlb_cos_fifo_cfg_u rxlb_cos_fifo_cfg; /* B48 */ + volatile csr_rx_idx_wt_u rx_idx_wt; /* B54 */ + volatile csr_rx_host0_chn_m_u rx_host0_chn_m; /* B58 */ + volatile csr_rx_tso3_rls_fifo_cfg_u rx_tso3_rls_fifo_cfg; /* B60 */ + volatile csr_stl_cmd_api_rd_req_fifo_sta_u stl_cmd_api_rd_req_fifo_sta[4]; /* 1400 */ + volatile csr_stl_str_api_fifo_sta_u stl_str_api_fifo_sta[4]; /* 1410 */ + volatile csr_stl_wr_rd_dat_in_fifo_sta_u stl_wr_rd_dat_in_fifo_sta[2]; /* 1420 */ + volatile csr_stl_rsp_api_hdr_dat_fifo_sta_u stl_rsp_api_hdr_dat_fifo_sta[4]; /* 1430 */ + volatile csr_stl_rsp_api_cd_crc_fifo_sta_u stl_rsp_api_cd_crc_fifo_sta[4]; /* 1440 */ + volatile csr_stl_rsp_api_cs_nptr_fifo_sta_u stl_rsp_api_cs_nptr_fifo_sta[4]; /* 1450 */ + volatile csr_stl_str_cmd_cnt_u stl_str_cmd_cnt[4]; /* 1460 */ + volatile csr_stl_ack_rsp_cnt_u stl_ack_rsp_cnt[4]; /* 1470 */ + volatile csr_stl_psh_cnt_u stl_psh_cnt[4]; /* 1480 */ + volatile csr_stl_cell_mdf_cnt_u stl_cell_mdf_cnt[4]; /* 1490 */ + volatile csr_stl_wr_di_ctrl_fifo_sta_u stl_wr_di_ctrl_fifo_sta[2]; /* 14A4 */ + volatile csr_stl_fifo_ov_err_0_u stl_fifo_ov_err_0; /* 14B0 */ + volatile csr_stl_fifo_ov_err_1_u stl_fifo_ov_err_1; /* 14B4 */ + volatile csr_stl_fifo_uf_err_0_u stl_fifo_uf_err_0; /* 14B8 */ + volatile csr_stl_fifo_uf_err_1_u stl_fifo_uf_err_1; /* 14BC */ + volatile csr_stlwr_fifo_ram_err_u stlwr_fifo_ram_err[2]; /* 14C0 */ + volatile csr_stlstr_fifo_ram_err_u stlstr_fifo_ram_err[4]; /* 14D0 */ + volatile csr_stlrsp_fifo_ram_err_u stlrsp_fifo_ram_err[4]; /* 14E0 */ + volatile csr_cdt_psh_fifo_sta_u cdt_psh_fifo_sta; /* 15C8 */ + volatile csr_cdt_fifo_err_u cdt_fifo_err; /* 15CC */ + volatile csr_cdt_crdt_sta_u cdt_crdt_sta; /* 15D0 */ + volatile csr_stliq_pkt_psh_cnt_u stliq_pkt_psh_cnt[4]; /* 1600 */ + volatile csr_stliq_msg_psh_cnt_u stliq_msg_psh_cnt[4]; /* 1610 */ + volatile csr_flowpac_psh_req_cnt_u flowpac_psh_req_cnt; /* 1660 */ + volatile csr_nonflowpac_psh_req_cnt_u nonflowpac_psh_req_cnt; /* 1664 */ + volatile csr_stliq_psh_fifo_sta_u stliq_psh_fifo_sta[4]; /* 1680 */ + volatile csr_rob_psh_fifo_sta_u rob_psh_fifo_sta; /* 16B4 */ + volatile csr_rx_epd_cnt_u rx_epd_cnt; /* 1700 */ + volatile csr_rx_chn_epd_cnt_u rx_chn_epd_cnt[23]; /* 1704 */ + volatile csr_tx_epd_cnt_u tx_epd_cnt; /* 1760 */ + volatile csr_tx_chn_epd_cnt_u tx_chn_epd_cnt[11]; /* 1764 */ + volatile csr_txmac_chn_tso12_epd_cnt_u txmac_chn_tso12_epd_cnt[8]; /* 1790 */ + volatile csr_drp_req_cnt_u drp_req_cnt; /* 17B0 */ + volatile csr_rx_tso3_drp_cnt_u rx_tso3_drp_cnt; /* 17B4 */ + volatile csr_tx_tso3_drp_cnt_u tx_tso3_drp_cnt; /* 17B8 */ + volatile csr_drp_eop_cnt_u drp_eop_cnt; /* 17BC */ + volatile csr_rx_epd_fifo_sta_u rx_epd_fifo_sta; /* 17D0 */ + volatile csr_tx_epd_fifo_sta_u tx_epd_fifo_sta; /* 17D4 */ + volatile csr_ndrp_fifo_sta_u ndrp_fifo_sta; /* 17D8 */ + volatile csr_drp_rxrls_fifo_sta_u drp_rxrls_fifo_sta; /* 17DC */ + volatile csr_drp_txrls_fifo_sta_u drp_txrls_fifo_sta; /* 17E0 */ + volatile csr_fdrp_fifo_sta_u fdrp_fifo_sta; /* 17E4 */ + volatile csr_ftso_drp_req_cnt_u ftso_drp_req_cnt; /* 17E8 */ + volatile csr_coq_fifo_of_err_u coq_fifo_of_err; /* 17F0 */ + volatile csr_coq_fifo_uf_err_u coq_fifo_uf_err; /* 17F4 */ + volatile csr_coq_err_u coq_err; /* 17F8 */ + volatile csr_rx_cpi_chn_crdt_sta_u rx_cpi_chn_crdt_sta[20]; /* 1800 */ + volatile csr_rx_cpi_host_crdt_sta_u rx_cpi_host_crdt_sta[5]; /* 1850 */ + volatile csr_rx_cpi_shr_crdt_sta_u rx_cpi_shr_crdt_sta; /* 1864 */ + volatile csr_rx_cpi_host_wcrdt_sta_u rx_cpi_host_wcrdt_sta[4]; /* 1870 */ + volatile csr_rxlb_chn_crdt_sta_u rxlb_chn_crdt_sta[3]; /* 1880 */ + volatile csr_rx_idx_crdt_sta_u rx_idx_crdt_sta; /* 188C */ + volatile csr_rxlb_fp_bmp_sta_u rxlb_fp_bmp_sta; /* 1890 */ + volatile csr_rxpd_fifo_empty_sta_0_u rxpd_fifo_empty_sta_0; /* 1894 */ + volatile csr_rxpd_fifo_empty_sta_1_u rxpd_fifo_empty_sta_1; /* 1898 */ + volatile csr_rxpd_fifo_empty_sta_2_u rxpd_fifo_empty_sta_2; /* 189C */ + volatile csr_rxpd_fifo_fill_sta_u rxpd_fifo_fill_sta[11]; /* 18A0 */ + volatile csr_rxpd_pro_fsm_sta_u rxpd_pro_fsm_sta[23]; /* 1900 */ + volatile csr_rx_crdt_of_err_0_u rx_crdt_of_err_0; /* 1990 */ + volatile csr_rx_crdt_of_err_1_u rx_crdt_of_err_1; /* 1994 */ + volatile csr_rx_crdt_uf_err_0_u rx_crdt_uf_err_0; /* 1998 */ + volatile csr_rx_crdt_uf_err_1_u rx_crdt_uf_err_1; /* 199C */ + volatile csr_rxpd_fifo_of_err_0_u rxpd_fifo_of_err_0; /* 19A0 */ + volatile csr_rxpd_fifo_of_err_1_u rxpd_fifo_of_err_1; /* 19A4 */ + volatile csr_rxpd_fifo_of_err_2_u rxpd_fifo_of_err_2; /* 19A8 */ + volatile csr_rxpd_fifo_uf_err_0_u rxpd_fifo_uf_err_0; /* 19B0 */ + volatile csr_rxpd_fifo_uf_err_1_u rxpd_fifo_uf_err_1; /* 19B4 */ + volatile csr_rxpd_fifo_uf_err_2_u rxpd_fifo_uf_err_2; /* 19B8 */ + volatile csr_rxlb_pd_ram_err_u rxlb_pd_ram_err; /* 19BC */ + volatile csr_cpb_rx_err_0_u cpb_rx_err_0; /* 19C0 */ + volatile csr_cpb_rx_err_1_u cpb_rx_err_1; /* 19C4 */ + volatile csr_cpb_rx_err_2_u cpb_rx_err_2; /* 19C8 */ + volatile csr_cpb_rx_err_3_u cpb_rx_err_3; /* 19CC */ + volatile csr_cpb_rx_err_4_u cpb_rx_err_4; /* 19D0 */ + volatile csr_cpb_rx_err_5_u cpb_rx_err_5; /* 19D4 */ + volatile csr_rx_tso3_rls_fifo_sta_u rx_tso3_rls_fifo_sta[5]; /* 19E0 */ +} S_cpb_csr_2_REGS_TYPE; + +/* Declare the struct pointor of the module cpb_csr_2 */ +extern volatile S_cpb_csr_2_REGS_TYPE *gopcpb_csr_2AllReg; + +/* Declare the functions that set the member value */ +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_rsp_npt_fifo_crdt(unsigned int ustl_rsp_npt_fifo_crdt); +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_rsp_dat_fifo_crdt(unsigned int ustl_rsp_dat_fifo_crdt); +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_rsp_api_hdr_fifo_crdt(unsigned int ustl_rsp_api_hdr_fifo_crdt); +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_rsp_crc_fifo_crdt(unsigned int ustl_rsp_crc_fifo_crdt); +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_rsp_api_fifo_crdt_init(unsigned int ustl_rsp_api_fifo_crdt_init); +int iSetSTL_RSP_API_FIFO_CRDT_INIT_stl_str_rsp_hdr_crdt(unsigned int ustl_str_rsp_hdr_crdt); +int iSetSTL_PSH_CMD_WT_stl_cmd_req_wt(unsigned int ustl_cmd_req_wt); +int iSetSTL_PSH_CMD_WT_stl_psh_req_wt(unsigned int ustl_psh_req_wt); +int iSetSTL_RD_REQ_FIFO_AF_TH_stl_rd_req_fifo_af_th(unsigned int ustl_rd_req_fifo_af_th); +int iSetSTL_RD_CTRL_FIFO_AF_TH_stl_rd_ctrl_fifo_af_th(unsigned int ustl_rd_ctrl_fifo_af_th); +int iSetCPB_STL_API_CRDT_INIT_cpb_stl_api_crdt(unsigned int ucpb_stl_api_crdt); +int iSetCPB_STL_API_CRDT_INIT_cpb_stl_api_crdt_init(unsigned int ucpb_stl_api_crdt_init); +int iSetSTL_STR_DI_FIFO_AF_TH_stl_str_di_fifo_af_th(unsigned int ustl_str_di_fifo_af_th); +int iSetSTL_STR_API_FIFO_AF_TH_stl_str_api_fifo_af_th(unsigned int ustl_str_api_fifo_af_th); +int iSetSTL_CMD_API_FIFO_AF_TH_stl_cmd_api_fifo_af_th(unsigned int ustl_cmd_api_fifo_af_th); +int iSetSTL_ACKSTR_FIFO_AF_TH_stl_ackstr_fifo_af_th(unsigned int ustl_ackstr_fifo_af_th); +int iSetCDT_CRDT_CFG_cdt_crdt_cfg(unsigned int ucdt_crdt_cfg); +int iSetCDT_PSH_FIFO_CFG_cdt_psh_fifo_af_th(unsigned int ucdt_psh_fifo_af_th); +int iSetCDT_PSH_FIFO_CFG_cdt_psh_fifo_ae_th(unsigned int ucdt_psh_fifo_ae_th); +int iSetCDT_PSH_FIFO_CFG_ct_para_ret_cell_num_err_en(unsigned int uct_para_ret_cell_num_err_en); +int iSetSTLIQ_PSH_FIFO_CFG_stlpsh_fifo_ae_th(unsigned int ustlpsh_fifo_ae_th); +int iSetSTLIQ_PSH_FIFO_CFG_stlpsh_fifo_af_th(unsigned int ustlpsh_fifo_af_th); +int iSetINNER_CHN_MAP_inner_cpi_chn_map_mode(unsigned int uinner_cpi_chn_map_mode); +int iSetDRP_ACK_TH_drp_ack_th(unsigned int udrp_ack_th); +int iSetOQRX_PD_FIFO_CFG_oqrxpd_fifo_ae_th(unsigned int uoqrxpd_fifo_ae_th); +int iSetOQRX_PD_FIFO_CFG_oqrxpd_fifo_af_th(unsigned int uoqrxpd_fifo_af_th); +int iSetOQTX_PD_FIFO_CFG_oqtxpd_fifo_ae_th(unsigned int uoqtxpd_fifo_ae_th); +int iSetOQTX_PD_FIFO_CFG_oqtxpd_fifo_af_th(unsigned int uoqtxpd_fifo_af_th); +int iSetDRP_FIFO_CFG_drp_fifo_ae_th(unsigned int udrp_fifo_ae_th); +int iSetDRP_FIFO_CFG_drp_fifo_af_th(unsigned int udrp_fifo_af_th); +int iSetDRP_TXRLS_FIFO_CFG_drp_txrls_fifo_ae_th(unsigned int udrp_txrls_fifo_ae_th); +int iSetDRP_TXRLS_FIFO_CFG_drp_txrls_fifo_af_th(unsigned int udrp_txrls_fifo_af_th); +int iSetDRP_RXRLS_FIFO_CFG_drp_rxrls_fifo_ae_th(unsigned int udrp_rxrls_fifo_ae_th); +int iSetDRP_RXRLS_FIFO_CFG_drp_rxrls_fifo_af_th(unsigned int udrp_rxrls_fifo_af_th); +int iSetFDRP_FIFO_CFG_fdrp_fifo_ae_th(unsigned int ufdrp_fifo_ae_th); +int iSetFDRP_FIFO_CFG_fdrp_fifo_af_th(unsigned int ufdrp_fifo_af_th); +int iSetRX_NOR_CHN_WT0_perx_cell_req_wt00(unsigned int uperx_cell_req_wt00); +int iSetRX_NOR_CHN_WT0_perx_cell_req_wt01(unsigned int uperx_cell_req_wt01); +int iSetRX_NOR_CHN_WT0_perx_cell_req_wt02(unsigned int uperx_cell_req_wt02); +int iSetRX_NOR_CHN_WT0_perx_cell_req_wt03(unsigned int uperx_cell_req_wt03); +int iSetRX_NOR_CHN_WT0_perx_cell_req_wt04(unsigned int uperx_cell_req_wt04); +int iSetRX_NOR_CHN_WT1_perx_cell_req_wt10(unsigned int uperx_cell_req_wt10); +int iSetRX_NOR_CHN_WT1_perx_cell_req_wt11(unsigned int uperx_cell_req_wt11); +int iSetRX_NOR_CHN_WT1_perx_cell_req_wt12(unsigned int uperx_cell_req_wt12); +int iSetRX_NOR_CHN_WT1_perx_cell_req_wt13(unsigned int uperx_cell_req_wt13); +int iSetRX_NOR_CHN_WT1_perx_cell_req_wt14(unsigned int uperx_cell_req_wt14); +int iSetRX_NOR_CHN_WT2_perx_cell_req_wt20(unsigned int uperx_cell_req_wt20); +int iSetRX_NOR_CHN_WT2_perx_cell_req_wt21(unsigned int uperx_cell_req_wt21); +int iSetRX_NOR_CHN_WT2_perx_cell_req_wt22(unsigned int uperx_cell_req_wt22); +int iSetRX_NOR_CHN_WT2_perx_cell_req_wt23(unsigned int uperx_cell_req_wt23); +int iSetRX_NOR_CHN_WT2_perx_cell_req_wt24(unsigned int uperx_cell_req_wt24); +int iSetRX_NOR_CHN_WT3_perx_cell_req_wt30(unsigned int uperx_cell_req_wt30); +int iSetRX_NOR_CHN_WT3_perx_cell_req_wt31(unsigned int uperx_cell_req_wt31); +int iSetRX_NOR_CHN_WT3_perx_cell_req_wt32(unsigned int uperx_cell_req_wt32); +int iSetRX_NOR_CHN_WT3_perx_cell_req_wt33(unsigned int uperx_cell_req_wt33); +int iSetRX_NOR_CHN_WT3_perx_cell_req_wt34(unsigned int uperx_cell_req_wt34); +int iSetRX_LB_CHN_WT3_perx_cell_req_wt40(unsigned int uperx_cell_req_wt40); +int iSetRX_LB_CHN_WT3_perx_cell_req_wt41(unsigned int uperx_cell_req_wt41); +int iSetRX_LB_CHN_WT3_perx_cell_req_wt42(unsigned int uperx_cell_req_wt42); +int iSetRXLB_PORT_WT_0_rxlb0_port0_wt(unsigned int urxlb0_port0_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port1_wt(unsigned int urxlb0_port1_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port2_wt(unsigned int urxlb0_port2_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port3_wt(unsigned int urxlb0_port3_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port4_wt(unsigned int urxlb0_port4_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port5_wt(unsigned int urxlb0_port5_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port6_wt(unsigned int urxlb0_port6_wt); +int iSetRXLB_PORT_WT_0_rxlb0_port7_wt(unsigned int urxlb0_port7_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port0_wt(unsigned int urxlb1_port0_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port1_wt(unsigned int urxlb1_port1_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port2_wt(unsigned int urxlb1_port2_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port3_wt(unsigned int urxlb1_port3_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port4_wt(unsigned int urxlb1_port4_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port5_wt(unsigned int urxlb1_port5_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port6_wt(unsigned int urxlb1_port6_wt); +int iSetRXLB_PORT_WT_1_rxlb1_port7_wt(unsigned int urxlb1_port7_wt); +int iSetCOS_CHN_RXLB_CFG_0_cos_chn_rxlb_cfg_0(unsigned int ucos_chn_rxlb_cfg_0); +int iSetCOS_CHN_RXLB_CFG_1_cos_chn_rxlb_cfg_1(unsigned int ucos_chn_rxlb_cfg_1); +int iSetCPB_RX_CRDT_CFG_sge_prealc_crdt(unsigned int usge_prealc_crdt); +int iSetCPB_RX_CRDT_CFG_dat_prealc_crdt_w(unsigned int udat_prealc_crdt_w); +int iSetCPB_RX_CRDT_CFG_dat_prealc_crdt_o(unsigned int udat_prealc_crdt_o); +int iSetCPB_RX_CRDT_CFG_dat_prealc_crdt_lb(unsigned int udat_prealc_crdt_lb); +int iSetCPB_RX_IDX_CFG_perx_idx_crdt(unsigned int uperx_idx_crdt); +int iSetCPB_RX_IDX_CFG_perx_idx_bp_gap(unsigned int uperx_idx_bp_gap); +int iSetCHN5_SGE_CFG_chn_sge_rsv_th0(unsigned int uchn_sge_rsv_th0); +int iSetCHN5_SGE_CFG_chn_sge_shr_th0(unsigned int uchn_sge_shr_th0); +int iSetCHN6_SGE_CFG_chn_sge_rsv_th1(unsigned int uchn_sge_rsv_th1); +int iSetCHN6_SGE_CFG_chn_sge_shr_th1(unsigned int uchn_sge_shr_th1); +int iSetCHN7_SGE_CFG_chn_sge_rsv_th2(unsigned int uchn_sge_rsv_th2); +int iSetCHN7_SGE_CFG_chn_sge_shr_th2(unsigned int uchn_sge_shr_th2); +int iSetCHN8_SGE_CFG_chn_sge_rsv_th3(unsigned int uchn_sge_rsv_th3); +int iSetCHN8_SGE_CFG_chn_sge_shr_th3(unsigned int uchn_sge_shr_th3); +int iSetCHN9_SGE_CFG_chn_sge_rsv_th4(unsigned int uchn_sge_rsv_th4); +int iSetCHN9_SGE_CFG_chn_sge_shr_th4(unsigned int uchn_sge_shr_th4); +int iSetCHN10_SGE_CFG_chn_sge_rsv_th5(unsigned int uchn_sge_rsv_th5); +int iSetCHN10_SGE_CFG_chn_sge_shr_th5(unsigned int uchn_sge_shr_th5); +int iSetCHN11_SGE_CFG_chn_sge_rsv_th6(unsigned int uchn_sge_rsv_th6); +int iSetCHN11_SGE_CFG_chn_sge_shr_th6(unsigned int uchn_sge_shr_th6); +int iSetCHN12_SGE_CFG_chn_sge_rsv_th7(unsigned int uchn_sge_rsv_th7); +int iSetCHN12_SGE_CFG_chn_sge_shr_th7(unsigned int uchn_sge_shr_th7); +int iSetCHN13_SGE_CFG_chn_sge_rsv_th8(unsigned int uchn_sge_rsv_th8); +int iSetCHN13_SGE_CFG_chn_sge_shr_th8(unsigned int uchn_sge_shr_th8); +int iSetCHN14_SGE_CFG_chn_sge_rsv_th9(unsigned int uchn_sge_rsv_th9); +int iSetCHN14_SGE_CFG_chn_sge_shr_th9(unsigned int uchn_sge_shr_th9); +int iSetCHN15_SGE_CFG_chn_sge_rsv_th10(unsigned int uchn_sge_rsv_th10); +int iSetCHN15_SGE_CFG_chn_sge_shr_th10(unsigned int uchn_sge_shr_th10); +int iSetCHN16_SGE_CFG_chn_sge_rsv_th11(unsigned int uchn_sge_rsv_th11); +int iSetCHN16_SGE_CFG_chn_sge_shr_th11(unsigned int uchn_sge_shr_th11); +int iSetCHN17_SGE_CFG_chn_sge_rsv_th12(unsigned int uchn_sge_rsv_th12); +int iSetCHN17_SGE_CFG_chn_sge_shr_th12(unsigned int uchn_sge_shr_th12); +int iSetCHN18_SGE_CFG_chn_sge_rsv_th13(unsigned int uchn_sge_rsv_th13); +int iSetCHN18_SGE_CFG_chn_sge_shr_th13(unsigned int uchn_sge_shr_th13); +int iSetCHN19_SGE_CFG_chn_sge_rsv_th14(unsigned int uchn_sge_rsv_th14); +int iSetCHN19_SGE_CFG_chn_sge_shr_th14(unsigned int uchn_sge_shr_th14); +int iSetCHN20_SGE_CFG_chn_sge_rsv_th15(unsigned int uchn_sge_rsv_th15); +int iSetCHN20_SGE_CFG_chn_sge_shr_th15(unsigned int uchn_sge_shr_th15); +int iSetCHN21_SGE_CFG_chn_sge_rsv_th16(unsigned int uchn_sge_rsv_th16); +int iSetCHN21_SGE_CFG_chn_sge_shr_th16(unsigned int uchn_sge_shr_th16); +int iSetCHN22_SGE_CFG_chn_sge_rsv_th17(unsigned int uchn_sge_rsv_th17); +int iSetCHN22_SGE_CFG_chn_sge_shr_th17(unsigned int uchn_sge_shr_th17); +int iSetCHN23_SGE_CFG_chn_sge_rsv_th18(unsigned int uchn_sge_rsv_th18); +int iSetCHN23_SGE_CFG_chn_sge_shr_th18(unsigned int uchn_sge_shr_th18); +int iSetCHN24_SGE_CFG_chn_sge_rsv_th19(unsigned int uchn_sge_rsv_th19); +int iSetCHN24_SGE_CFG_chn_sge_shr_th19(unsigned int uchn_sge_shr_th19); +int iSetHOST0_SGE_TH_host_sge_th0(unsigned int uhost_sge_th0); +int iSetHOST0_SGE_TH_host_sge_w_th0(unsigned int uhost_sge_w_th0); +int iSetHOST1_SGE_TH_host_sge_th1(unsigned int uhost_sge_th1); +int iSetHOST1_SGE_TH_host_sge_w_th1(unsigned int uhost_sge_w_th1); +int iSetHOST2_SGE_TH_host_sge_th2(unsigned int uhost_sge_th2); +int iSetHOST2_SGE_TH_host_sge_w_th2(unsigned int uhost_sge_w_th2); +int iSetHOST3_SGE_TH_host_sge_th3(unsigned int uhost_sge_th3); +int iSetHOST3_SGE_TH_host_sge_w_th3(unsigned int uhost_sge_w_th3); +int iSetHOST4_SGE_TH_host_sge_th4(unsigned int uhost_sge_th4); +int iSetSGE_SHR_BP_TH_sge_shr_bp_th(unsigned int usge_shr_bp_th); +int iSetSGE_BP_GAP_sge_bp_gap(unsigned int usge_bp_gap); +int iSetCHN5_DAT_CFG_chn_dat_rsv_th0(unsigned int uchn_dat_rsv_th0); +int iSetCHN5_DAT_CFG_chn_dat_shr_th0(unsigned int uchn_dat_shr_th0); +int iSetCHN6_DAT_CFG_chn_dat_rsv_th1(unsigned int uchn_dat_rsv_th1); +int iSetCHN6_DAT_CFG_chn_dat_shr_th1(unsigned int uchn_dat_shr_th1); +int iSetCHN7_DAT_CFG_chn_dat_rsv_th2(unsigned int uchn_dat_rsv_th2); +int iSetCHN7_DAT_CFG_chn_dat_shr_th2(unsigned int uchn_dat_shr_th2); +int iSetCHN8_DAT_CFG_chn_dat_rsv_th3(unsigned int uchn_dat_rsv_th3); +int iSetCHN8_DAT_CFG_chn_dat_shr_th3(unsigned int uchn_dat_shr_th3); +int iSetCHN9_DAT_CFG_chn_dat_rsv_th4(unsigned int uchn_dat_rsv_th4); +int iSetCHN9_DAT_CFG_chn_dat_shr_th4(unsigned int uchn_dat_shr_th4); +int iSetCHN10_DAT_CFG_chn_dat_rsv_th5(unsigned int uchn_dat_rsv_th5); +int iSetCHN10_DAT_CFG_chn_dat_shr_th5(unsigned int uchn_dat_shr_th5); +int iSetCHN11_DAT_CFG_chn_dat_rsv_th6(unsigned int uchn_dat_rsv_th6); +int iSetCHN11_DAT_CFG_chn_dat_shr_th6(unsigned int uchn_dat_shr_th6); +int iSetCHN12_DAT_CFG_chn_dat_rsv_th7(unsigned int uchn_dat_rsv_th7); +int iSetCHN12_DAT_CFG_chn_dat_shr_th7(unsigned int uchn_dat_shr_th7); +int iSetCHN13_DAT_CFG_chn_dat_rsv_th8(unsigned int uchn_dat_rsv_th8); +int iSetCHN13_DAT_CFG_chn_dat_shr_th8(unsigned int uchn_dat_shr_th8); +int iSetCHN14_DAT_CFG_chn_dat_rsv_th9(unsigned int uchn_dat_rsv_th9); +int iSetCHN14_DAT_CFG_chn_dat_shr_th9(unsigned int uchn_dat_shr_th9); +int iSetCHN15_DAT_CFG_chn_dat_rsv_th10(unsigned int uchn_dat_rsv_th10); +int iSetCHN15_DAT_CFG_chn_dat_shr_th10(unsigned int uchn_dat_shr_th10); +int iSetCHN16_DAT_CFG_chn_dat_rsv_th11(unsigned int uchn_dat_rsv_th11); +int iSetCHN16_DAT_CFG_chn_dat_shr_th11(unsigned int uchn_dat_shr_th11); +int iSetCHN17_DAT_CFG_chn_dat_rsv_th12(unsigned int uchn_dat_rsv_th12); +int iSetCHN17_DAT_CFG_chn_dat_shr_th12(unsigned int uchn_dat_shr_th12); +int iSetCHN18_DAT_CFG_chn_dat_rsv_th13(unsigned int uchn_dat_rsv_th13); +int iSetCHN18_DAT_CFG_chn_dat_shr_th13(unsigned int uchn_dat_shr_th13); +int iSetCHN19_DAT_CFG_chn_dat_rsv_th14(unsigned int uchn_dat_rsv_th14); +int iSetCHN19_DAT_CFG_chn_dat_shr_th14(unsigned int uchn_dat_shr_th14); +int iSetCHN20_DAT_CFG_chn_dat_rsv_th15(unsigned int uchn_dat_rsv_th15); +int iSetCHN20_DAT_CFG_chn_dat_shr_th15(unsigned int uchn_dat_shr_th15); +int iSetCHN21_DAT_CFG_chn_dat_rsv_th16(unsigned int uchn_dat_rsv_th16); +int iSetCHN21_DAT_CFG_chn_dat_shr_th16(unsigned int uchn_dat_shr_th16); +int iSetCHN22_DAT_CFG_chn_dat_rsv_th17(unsigned int uchn_dat_rsv_th17); +int iSetCHN22_DAT_CFG_chn_dat_shr_th17(unsigned int uchn_dat_shr_th17); +int iSetCHN23_DAT_CFG_chn_dat_rsv_th18(unsigned int uchn_dat_rsv_th18); +int iSetCHN23_DAT_CFG_chn_dat_shr_th18(unsigned int uchn_dat_shr_th18); +int iSetCHN24_DAT_CFG_chn_dat_rsv_th19(unsigned int uchn_dat_rsv_th19); +int iSetCHN24_DAT_CFG_chn_dat_shr_th19(unsigned int uchn_dat_shr_th19); +int iSetHOST0_DAT_TH_host_dat_th0(unsigned int uhost_dat_th0); +int iSetHOST0_DAT_TH_host_dat_w_th0(unsigned int uhost_dat_w_th0); +int iSetHOST1_DAT_TH_host_dat_th1(unsigned int uhost_dat_th1); +int iSetHOST1_DAT_TH_host_dat_w_th1(unsigned int uhost_dat_w_th1); +int iSetHOST2_DAT_TH_host_dat_th2(unsigned int uhost_dat_th2); +int iSetHOST2_DAT_TH_host_dat_w_th2(unsigned int uhost_dat_w_th2); +int iSetHOST3_DAT_TH_host_dat_th3(unsigned int uhost_dat_th3); +int iSetHOST3_DAT_TH_host_dat_w_th3(unsigned int uhost_dat_w_th3); +int iSetHOST4_DAT_TH_host_dat_th4(unsigned int uhost_dat_th4); +int iSetDAT_SHR_BP_TH_dat_shr_bp_th(unsigned int udat_shr_bp_th); +int iSetDAT_BP_GAP_dat_bp_gap(unsigned int udat_bp_gap); +int iSetRX_MPU_DAT_CFG_rx_mpu_crdt_th(unsigned int urx_mpu_crdt_th); +int iSetRX_LB0_DAT_CFG_rx_lb_crdt_th0(unsigned int urx_lb_crdt_th0); +int iSetRX_LB1_DAT_CFG_rx_lb_crdt_th1(unsigned int urx_lb_crdt_th1); +int iSetRXLB_DAT_BP_GAP_rxlb_dat_bp_gap(unsigned int urxlb_dat_bp_gap); +int iSetRXPD_FIFO_CFG_rxpd_fifo_ae_th(unsigned int urxpd_fifo_ae_th); +int iSetRXPD_FIFO_CFG_rxpd_fifo_af_th(unsigned int urxpd_fifo_af_th); +int iSetRXMPU_FIFO_CFG_rxmpu_fifo_ae_th(unsigned int urxmpu_fifo_ae_th); +int iSetRXMPU_FIFO_CFG_rxmpu_fifo_af_th(unsigned int urxmpu_fifo_af_th); +int iSetRXLB_COS_FIFO_CFG_rxlb_cos_fifo_ae_th(unsigned int urxlb_cos_fifo_ae_th); +int iSetRXLB_COS_FIFO_CFG_rxlb_cos_fifo_af_th(unsigned int urxlb_cos_fifo_af_th); +int iSetRX_IDX_WT_cpr_idx_req_wt0(unsigned int ucpr_idx_req_wt0); +int iSetRX_IDX_WT_cpr_idx_req_wt1(unsigned int ucpr_idx_req_wt1); +int iSetRX_IDX_WT_cpr_idx_req_wt2(unsigned int ucpr_idx_req_wt2); +int iSetRX_IDX_WT_cpr_idx_req_wt3(unsigned int ucpr_idx_req_wt3); +int iSetRX_IDX_WT_cpr_idx_req_wt4(unsigned int ucpr_idx_req_wt4); +int iSetRX_HOST0_CHN_M_host0_chn_more_cfg(unsigned int uhost0_chn_more_cfg); +int iSetRX_TSO3_RLS_FIFO_CFG_rx_tso3_rls_fifo_ae_th(unsigned int urx_tso3_rls_fifo_ae_th); +int iSetRX_TSO3_RLS_FIFO_CFG_rx_tso3_rls_fifo_af_th(unsigned int urx_tso3_rls_fifo_af_th); +int iSetSTL_CMD_API_RD_REQ_FIFO_STA_stl_cmd_api_fifo_sta(unsigned int ustl_cmd_api_fifo_sta); +int iSetSTL_CMD_API_RD_REQ_FIFO_STA_stl_rd_req_fifo_sta(unsigned int ustl_rd_req_fifo_sta); +int iSetSTL_STR_API_FIFO_STA_stl_str_api_fifo_sta(unsigned int ustl_str_api_fifo_sta); +int iSetSTL_WR_RD_DAT_IN_FIFO_STA_stl_wr_di_fifo_sta(unsigned int ustl_wr_di_fifo_sta); +int iSetSTL_WR_RD_DAT_IN_FIFO_STA_stl_rd_di_fifo_sta(unsigned int ustl_rd_di_fifo_sta); +int iSetSTL_RSP_API_HDR_DAT_FIFO_STA_stl_rsp_api_dat_fifo_sta(unsigned int ustl_rsp_api_dat_fifo_sta); +int iSetSTL_RSP_API_HDR_DAT_FIFO_STA_stl_rsp_api_hdr_fifo_sta(unsigned int ustl_rsp_api_hdr_fifo_sta); +int iSetSTL_RSP_API_CD_CRC_FIFO_STA_stl_rsp_api_crc_fifo_sta(unsigned int ustl_rsp_api_crc_fifo_sta); +int iSetSTL_RSP_API_CD_CRC_FIFO_STA_stl_rsp_api_cd_fifo_sta(unsigned int ustl_rsp_api_cd_fifo_sta); +int iSetSTL_RSP_API_CS_NPTR_FIFO_STA_stl_rsp_api_nptr_fifo_sta(unsigned int ustl_rsp_api_nptr_fifo_sta); +int iSetSTL_RSP_API_CS_NPTR_FIFO_STA_stl_rsp_api_cs_fifo_sta(unsigned int ustl_rsp_api_cs_fifo_sta); +int iSetSTL_STR_CMD_CNT_stl_cmd_cnt(unsigned int ustl_cmd_cnt); +int iSetSTL_STR_CMD_CNT_stl_str_cnt(unsigned int ustl_str_cnt); +int iSetSTL_ACK_RSP_CNT_stl_rsp_cnt(unsigned int ustl_rsp_cnt); +int iSetSTL_ACK_RSP_CNT_stl_ack_cnt(unsigned int ustl_ack_cnt); +int iSetSTL_PSH_CNT_stl_psh_tl_cnt(unsigned int ustl_psh_tl_cnt); +int iSetSTL_PSH_CNT_stl_iq_psh_cnt(unsigned int ustl_iq_psh_cnt); +int iSetSTL_CELL_MDF_CNT_stl_cell_mdf_cnt(unsigned int ustl_cell_mdf_cnt); +int iSetSTL_WR_DI_CTRL_FIFO_STA_stl_wr_di_ctrl_fifo_sta(unsigned int ustl_wr_di_ctrl_fifo_sta); +int iSetSTL_WR_DI_CTRL_FIFO_STA_stl_ackstr_fifo_sta(unsigned int ustl_ackstr_fifo_sta); +int iSetSTL_FIFO_OV_ERR_0_stl_rd_req_fifo_ov(unsigned int ustl_rd_req_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_cmd_api_fifo_ov(unsigned int ustl_cmd_api_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_str_api_fifo_ov(unsigned int ustl_str_api_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_rd_di_fifo_ov(unsigned int ustl_rd_di_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_wr_di_fifo_ov(unsigned int ustl_wr_di_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_wr_di_ctrl_fifo_ov(unsigned int ustl_wr_di_ctrl_fifo_ov); +int iSetSTL_FIFO_OV_ERR_0_stl_ackstr_fifo_ov(unsigned int ustl_ackstr_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_hdr_fifo_ov(unsigned int ustl_rsp_api_hdr_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_dat_fifo_ov(unsigned int ustl_rsp_api_dat_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_cd_fifo_ov(unsigned int ustl_rsp_api_cd_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_crc_fifo_ov(unsigned int ustl_rsp_api_crc_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_cs_fifo_ov(unsigned int ustl_rsp_api_cs_fifo_ov); +int iSetSTL_FIFO_OV_ERR_1_stl_rsp_api_nptr_fifo_ov(unsigned int ustl_rsp_api_nptr_fifo_ov); +int iSetSTL_FIFO_UF_ERR_0_stl_rd_req_fifo_uf(unsigned int ustl_rd_req_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_cmd_api_fifo_uf(unsigned int ustl_cmd_api_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_str_api_fifo_uf(unsigned int ustl_str_api_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_rd_di_fifo_uf(unsigned int ustl_rd_di_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_wr_di_fifo_uf(unsigned int ustl_wr_di_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_wr_di_ctrl_fifo_uf(unsigned int ustl_wr_di_ctrl_fifo_uf); +int iSetSTL_FIFO_UF_ERR_0_stl_ackstr_fifo_uf(unsigned int ustl_ackstr_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_hdr_fifo_uf(unsigned int ustl_rsp_api_hdr_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_dat_fifo_uf(unsigned int ustl_rsp_api_dat_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_cd_fifo_uf(unsigned int ustl_rsp_api_cd_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_crc_fifo_uf(unsigned int ustl_rsp_api_crc_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_cs_fifo_uf(unsigned int ustl_rsp_api_cs_fifo_uf); +int iSetSTL_FIFO_UF_ERR_1_stl_rsp_api_nptr_fifo_uf(unsigned int ustl_rsp_api_nptr_fifo_uf); +int iSetSTLWR_FIFO_RAM_ERR_stlwr_fifo_mem_err_addr(unsigned int ustlwr_fifo_mem_err_addr); +int iSetSTLWR_FIFO_RAM_ERR_stlwr_fifo_mem_err_cerr(unsigned int ustlwr_fifo_mem_err_cerr); +int iSetSTLWR_FIFO_RAM_ERR_stlwr_fifo_mem_err_ucerr(unsigned int ustlwr_fifo_mem_err_ucerr); +int iSetSTLWR_FIFO_RAM_ERR_stlwr_fifo_mem_err_cnt(unsigned int ustlwr_fifo_mem_err_cnt); +int iSetSTLSTR_FIFO_RAM_ERR_stlstr_fifo_mem_err_addr(unsigned int ustlstr_fifo_mem_err_addr); +int iSetSTLSTR_FIFO_RAM_ERR_stlstr_fifo_mem_err_cerr(unsigned int ustlstr_fifo_mem_err_cerr); +int iSetSTLSTR_FIFO_RAM_ERR_stlstr_fifo_mem_err_ucerr(unsigned int ustlstr_fifo_mem_err_ucerr); +int iSetSTLSTR_FIFO_RAM_ERR_stlstr_fifo_mem_err_cnt(unsigned int ustlstr_fifo_mem_err_cnt); +int iSetSTLRSP_FIFO_RAM_ERR_stlrsp_fifo_mem_err_addr(unsigned int ustlrsp_fifo_mem_err_addr); +int iSetSTLRSP_FIFO_RAM_ERR_stlrsp_fifo_mem_err_cerr(unsigned int ustlrsp_fifo_mem_err_cerr); +int iSetSTLRSP_FIFO_RAM_ERR_stlrsp_fifo_mem_err_ucerr(unsigned int ustlrsp_fifo_mem_err_ucerr); +int iSetSTLRSP_FIFO_RAM_ERR_stlrsp_fifo_mem_err_cnt(unsigned int ustlrsp_fifo_mem_err_cnt); +int iSetCDT_PSH_FIFO_STA_psh_ctrl_fifo1_sta(unsigned int upsh_ctrl_fifo1_sta); +int iSetCDT_PSH_FIFO_STA_psh_dat_fifo1_sta(unsigned int upsh_dat_fifo1_sta); +int iSetCDT_FIFO_ERR_cdt_psh_fifo_of_err(unsigned int ucdt_psh_fifo_of_err); +int iSetCDT_FIFO_ERR_cdt_psh_fifo_uf_err(unsigned int ucdt_psh_fifo_uf_err); +int iSetCDT_CRDT_STA_cdt_crdt_cnt(unsigned int ucdt_crdt_cnt); +int iSetCDT_CRDT_STA_cdt_crdt_of_err(unsigned int ucdt_crdt_of_err); +int iSetCDT_CRDT_STA_cdt_crdt_uf_err(unsigned int ucdt_crdt_uf_err); +int iSetCDT_CRDT_STA_geneve_flowpac_ofs_err(unsigned int ugeneve_flowpac_ofs_err); +int iSetSTLIQ_PKT_PSH_CNT_stliq_pkt_psh_cnt(unsigned int ustliq_pkt_psh_cnt); +int iSetSTLIQ_MSG_PSH_CNT_stliq_msg_psh_cnt(unsigned int ustliq_msg_psh_cnt); +int iSetFLOWPAC_PSH_REQ_CNT_flowpac_psh_req_cnt(unsigned int uflowpac_psh_req_cnt); +int iSetNONFLOWPAC_PSH_REQ_CNT_nonflowpac_psh_req_cnt(unsigned int unonflowpac_psh_req_cnt); +int iSetSTLIQ_PSH_FIFO_STA_stliq_psh_fifo_sta(unsigned int ustliq_psh_fifo_sta); +int iSetROB_PSH_FIFO_STA_rob_psh_fifo_sta(unsigned int urob_psh_fifo_sta); +int iSetRX_EPD_CNT_rx_epd_cnt(unsigned int urx_epd_cnt); +int iSetRX_CHN_EPD_CNT_rx_chn_epd_cnt(unsigned int urx_chn_epd_cnt); +int iSetTX_EPD_CNT_tx_epd_cnt(unsigned int utx_epd_cnt); +int iSetTX_CHN_EPD_CNT_tx_chn_epd_cnt(unsigned int utx_chn_epd_cnt); +int iSetTXMAC_CHN_TSO12_EPD_CNT_txmac_chn_tso12_epd_cnt(unsigned int utxmac_chn_tso12_epd_cnt); +int iSetDRP_REQ_CNT_drp_req_cnt(unsigned int udrp_req_cnt); +int iSetRX_TSO3_DRP_CNT_rx_tso3_prls_cnt(unsigned int urx_tso3_prls_cnt); +int iSetRX_TSO3_DRP_CNT_rx_tso3_drp_cnt(unsigned int urx_tso3_drp_cnt); +int iSetTX_TSO3_DRP_CNT_tx_tso3_prls_cnt(unsigned int utx_tso3_prls_cnt); +int iSetTX_TSO3_DRP_CNT_tx_tso3_drp_cnt(unsigned int utx_tso3_drp_cnt); +int iSetDRP_EOP_CNT_drp_eop_cnt(unsigned int udrp_eop_cnt); +int iSetRX_EPD_FIFO_STA_rx_epd_fifo_sta(unsigned int urx_epd_fifo_sta); +int iSetTX_EPD_FIFO_STA_tx_epd_fifo_sta(unsigned int utx_epd_fifo_sta); +int iSetNDRP_FIFO_STA_ndrp_fifo_sta(unsigned int undrp_fifo_sta); +int iSetDRP_RXRLS_FIFO_STA_drp_rxrls_fifo_sta(unsigned int udrp_rxrls_fifo_sta); +int iSetDRP_TXRLS_FIFO_STA_drp_txrls_fifo_sta(unsigned int udrp_txrls_fifo_sta); +int iSetFDRP_FIFO_STA_fdrp_fifo_sta(unsigned int ufdrp_fifo_sta); +int iSetFTSO_DRP_REQ_CNT_ftso_drp_req_cnt(unsigned int uftso_drp_req_cnt); +int iSetCOQ_FIFO_OF_ERR_rx_epd_fifo_of_err(unsigned int urx_epd_fifo_of_err); +int iSetCOQ_FIFO_OF_ERR_tx_epd_fifo_of_err(unsigned int utx_epd_fifo_of_err); +int iSetCOQ_FIFO_OF_ERR_ndrp_fifo_of_err(unsigned int undrp_fifo_of_err); +int iSetCOQ_FIFO_OF_ERR_drp_txrls_fifo_of_err(unsigned int udrp_txrls_fifo_of_err); +int iSetCOQ_FIFO_OF_ERR_drp_rxrls_fifo_of_err(unsigned int udrp_rxrls_fifo_of_err); +int iSetCOQ_FIFO_OF_ERR_fdrp_fifo_of_err(unsigned int ufdrp_fifo_of_err); +int iSetCOQ_FIFO_UF_ERR_rx_epd_fifo_uf_err(unsigned int urx_epd_fifo_uf_err); +int iSetCOQ_FIFO_UF_ERR_tx_epd_fifo_uf_err(unsigned int utx_epd_fifo_uf_err); +int iSetCOQ_FIFO_UF_ERR_ndrp_fifo_uf_err(unsigned int undrp_fifo_uf_err); +int iSetCOQ_FIFO_UF_ERR_drp_txrls_fifo_uf_err(unsigned int udrp_txrls_fifo_uf_err); +int iSetCOQ_FIFO_UF_ERR_drp_rxrls_fifo_uf_err(unsigned int udrp_rxrls_fifo_uf_err); +int iSetCOQ_FIFO_UF_ERR_fdrp_fifo_uf_err(unsigned int ufdrp_fifo_uf_err); +int iSetCOQ_ERR_rx_cpi_chn_err(unsigned int urx_cpi_chn_err); +int iSetCOQ_ERR_rx_pkt_mode_err(unsigned int urx_pkt_mode_err); +int iSetCOQ_ERR_rx_pcnum_srch_err(unsigned int urx_pcnum_srch_err); +int iSetCOQ_ERR_tx_lb_chn_err(unsigned int utx_lb_chn_err); +int iSetCOQ_ERR_tx_pkt_mode_err(unsigned int utx_pkt_mode_err); +int iSetCOQ_ERR_tx_pcnum_srch_err(unsigned int utx_pcnum_srch_err); +int iSetRX_CPI_CHN_CRDT_STA_cpi_chnsge_crdt_cnt(unsigned int ucpi_chnsge_crdt_cnt); +int iSetRX_CPI_CHN_CRDT_STA_cpi_chnsge_crdt_af(unsigned int ucpi_chnsge_crdt_af); +int iSetRX_CPI_CHN_CRDT_STA_cpi_chndat_crdt_cnt(unsigned int ucpi_chndat_crdt_cnt); +int iSetRX_CPI_CHN_CRDT_STA_cpi_chndat_crdt_af(unsigned int ucpi_chndat_crdt_af); +int iSetRX_CPI_HOST_CRDT_STA_cpi_hostsge_crdt_cnt(unsigned int ucpi_hostsge_crdt_cnt); +int iSetRX_CPI_HOST_CRDT_STA_cpi_hostsge_crdt_af(unsigned int ucpi_hostsge_crdt_af); +int iSetRX_CPI_HOST_CRDT_STA_cpi_hostdat_crdt_cnt(unsigned int ucpi_hostdat_crdt_cnt); +int iSetRX_CPI_HOST_CRDT_STA_cpi_hostdat_crdt_af(unsigned int ucpi_hostdat_crdt_af); +int iSetRX_CPI_SHR_CRDT_STA_cpi_shrsge_crdt_cnt(unsigned int ucpi_shrsge_crdt_cnt); +int iSetRX_CPI_SHR_CRDT_STA_cpi_shrsge_crdt_af(unsigned int ucpi_shrsge_crdt_af); +int iSetRX_CPI_SHR_CRDT_STA_cpi_shrdat_crdt_cnt(unsigned int ucpi_shrdat_crdt_cnt); +int iSetRX_CPI_SHR_CRDT_STA_cpi_shrdat_crdt_af(unsigned int ucpi_shrdat_crdt_af); +int iSetRX_CPI_HOST_WCRDT_STA_cpi_host_wsge_crdt_cnt(unsigned int ucpi_host_wsge_crdt_cnt); +int iSetRX_CPI_HOST_WCRDT_STA_cpb_pqm_hostsge_crdt_bp(unsigned int ucpb_pqm_hostsge_crdt_bp); +int iSetRX_CPI_HOST_WCRDT_STA_cpi_host_wdat_crdt_cnt(unsigned int ucpi_host_wdat_crdt_cnt); +int iSetRX_CPI_HOST_WCRDT_STA_cpb_pqm_hostdat_crdt_bp(unsigned int ucpb_pqm_hostdat_crdt_bp); +int iSetRXLB_CHN_CRDT_STA_rxlb_chn_crdt_cnt(unsigned int urxlb_chn_crdt_cnt); +int iSetRXLB_CHN_CRDT_STA_rxlb_chn_crdt_af(unsigned int urxlb_chn_crdt_af); +int iSetRX_IDX_CRDT_STA_rx_idx_crdt_cnt(unsigned int urx_idx_crdt_cnt); +int iSetRX_IDX_CRDT_STA_rx_idx_crdt_af(unsigned int urx_idx_crdt_af); +int iSetRXLB_FP_BMP_STA_rxlb_fp_bmp_fill(unsigned int urxlb_fp_bmp_fill); +int iSetRXPD_FIFO_EMPTY_STA_0_rxpd_fifo_empty_sta_0(unsigned int urxpd_fifo_empty_sta_0); +int iSetRXPD_FIFO_EMPTY_STA_1_rxpd_fifo_empty_sta_1(unsigned int urxpd_fifo_empty_sta_1); +int iSetRXPD_FIFO_EMPTY_STA_2_rxpd_fifo_empty_sta_2(unsigned int urxpd_fifo_empty_sta_2); +int iSetRXPD_FIFO_FILL_STA_rxpd_fifo_fill_sta(unsigned int urxpd_fifo_fill_sta); +int iSetRXPD_PRO_FSM_STA_rxpd_pro_fsm_sta(unsigned int urxpd_pro_fsm_sta); +int iSetRX_CRDT_OF_ERR_0_rx_idx_crdt_of_err(unsigned int urx_idx_crdt_of_err); +int iSetRX_CRDT_OF_ERR_0_rxlb_chn_crdt_of_err(unsigned int urxlb_chn_crdt_of_err); +int iSetRX_CRDT_OF_ERR_0_cpi_chn_dat_crdt_of_err(unsigned int ucpi_chn_dat_crdt_of_err); +int iSetRX_CRDT_OF_ERR_1_cpi_chn_sge_crdt_of_err(unsigned int ucpi_chn_sge_crdt_of_err); +int iSetRX_CRDT_UF_ERR_0_rx_idx_crdt_uf_err(unsigned int urx_idx_crdt_uf_err); +int iSetRX_CRDT_UF_ERR_0_rxlb_chn_crdt_uf_err(unsigned int urxlb_chn_crdt_uf_err); +int iSetRX_CRDT_UF_ERR_0_cpi_chn_dat_crdt_uf_err(unsigned int ucpi_chn_dat_crdt_uf_err); +int iSetRX_CRDT_UF_ERR_1_cpi_chn_sge_crdt_uf_err(unsigned int ucpi_chn_sge_crdt_uf_err); +int iSetRXPD_FIFO_OF_ERR_0_rxpd_fifo_of_err_0(unsigned int urxpd_fifo_of_err_0); +int iSetRXPD_FIFO_OF_ERR_1_rxpd_fifo_of_err_1(unsigned int urxpd_fifo_of_err_1); +int iSetRXPD_FIFO_OF_ERR_2_rxpd_fifo_of_err_2(unsigned int urxpd_fifo_of_err_2); +int iSetRXPD_FIFO_OF_ERR_2_rxlb_fp_fifo_of_err(unsigned int urxlb_fp_fifo_of_err); +int iSetRXPD_FIFO_OF_ERR_2_rx_tso3_rls_fifo_of_err(unsigned int urx_tso3_rls_fifo_of_err); +int iSetRXPD_FIFO_UF_ERR_0_rxpd_fifo_uf_err_0(unsigned int urxpd_fifo_uf_err_0); +int iSetRXPD_FIFO_UF_ERR_1_rxpd_fifo_uf_err_1(unsigned int urxpd_fifo_uf_err_1); +int iSetRXPD_FIFO_UF_ERR_2_rxpd_fifo_uf_err_2(unsigned int urxpd_fifo_uf_err_2); +int iSetRXPD_FIFO_UF_ERR_2_rxlb_fp_fifo_uf_err(unsigned int urxlb_fp_fifo_uf_err); +int iSetRXPD_FIFO_UF_ERR_2_rx_tso3_rls_fifo_uf_err(unsigned int urx_tso3_rls_fifo_uf_err); +int iSetRXLB_PD_RAM_ERR_rxlb_pd_mem_err_addr(unsigned int urxlb_pd_mem_err_addr); +int iSetRXLB_PD_RAM_ERR_rxlb_pd_mem_err_cerr(unsigned int urxlb_pd_mem_err_cerr); +int iSetRXLB_PD_RAM_ERR_rxlb_pd_mem_err_ucerr(unsigned int urxlb_pd_mem_err_ucerr); +int iSetRXLB_PD_RAM_ERR_rxlb_pd_mem_err_cnt(unsigned int urxlb_pd_mem_err_cnt); +int iSetCPB_RX_ERR_0_rx_chn_pd_pptr_err(unsigned int urx_chn_pd_pptr_err); +int iSetCPB_RX_ERR_1_rx_chn_pd_pktmod_err(unsigned int urx_chn_pd_pktmod_err); +int iSetCPB_RX_ERR_2_rx_chn_ret_pcnum_err(unsigned int urx_chn_ret_pcnum_err); +int iSetCPB_RX_ERR_3_rx_chn_tso2_err(unsigned int urx_chn_tso2_err); +int iSetCPB_RX_ERR_3_rx_chn_tso2_num_err(unsigned int urx_chn_tso2_num_err); +int iSetCPB_RX_ERR_3_rx_chn_tso2_cmd_cnum_err0(unsigned int urx_chn_tso2_cmd_cnum_err0); +int iSetCPB_RX_ERR_3_rx_chn_tso2_cmd_cnum_err1(unsigned int urx_chn_tso2_cmd_cnum_err1); +int iSetCPB_RX_ERR_3_rx_chn_tso2_cmd_cnum_err2(unsigned int urx_chn_tso2_cmd_cnum_err2); +int iSetCPB_RX_ERR_4_rx_chn_lro1_err(unsigned int urx_chn_lro1_err); +int iSetCPB_RX_ERR_4_rx_chn_lro1_num_err(unsigned int urx_chn_lro1_num_err); +int iSetCPB_RX_ERR_4_rx_chn_lro1_cmd_cnum_err(unsigned int urx_chn_lro1_cmd_cnum_err); +int iSetCPB_RX_ERR_5_rx_chn_lro2_err(unsigned int urx_chn_lro2_err); +int iSetCPB_RX_ERR_5_rx_chn_lro2_num_err(unsigned int urx_chn_lro2_num_err); +int iSetCPB_RX_ERR_5_rx_chn_lro2_cmd_cnum_err0(unsigned int urx_chn_lro2_cmd_cnum_err0); +int iSetCPB_RX_ERR_5_rx_chn_lro2_cmd_cnum_err1(unsigned int urx_chn_lro2_cmd_cnum_err1); +int iSetCPB_RX_ERR_5_rx_chn_lro2_cmd_cnum_err2(unsigned int urx_chn_lro2_cmd_cnum_err2); +int iSetRX_TSO3_RLS_FIFO_STA_rx_tso3_rls_fifo_sta(unsigned int urx_tso3_rls_fifo_sta); + +/* Define the union csr_cpb_indir_dat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_indir_dat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_indir_dat_u; + +/* Define the union csr_cir_alc_pro_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_pro_wt_0 : 4; /* [3:0] */ + u32 cir_alc_pro_wt_1 : 4; /* [7:4] */ + u32 cir_alc_pro_wt_2 : 4; /* [11:8] */ + u32 rsv_0 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_pro_wt_u; + +/* Define the union csr_cir_rpci_pro_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_rpci_pro_wt_0 : 4; /* [3:0] */ + u32 cir_rpci_pro_wt_1 : 4; /* [7:4] */ + u32 cir_rpci_pro_wt_2 : 4; /* [11:8] */ + u32 rsv_1 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_rpci_pro_wt_u; + +/* Define the union csr_cir_alc_mac_ncsi_port_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_mac_port_wt_4_0 : 4; /* [3:0] */ + u32 cir_alc_mac_port_wt_5_1 : 4; /* [7:4] */ + u32 cir_alc_mac_port_wt_6_2 : 4; /* [11:8] */ + u32 cir_alc_mac_port_wt_7_3 : 4; /* [15:12] */ + u32 cir_alc_ncsi_port_wt : 4; /* [19:16] */ + u32 rsv_2 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_mac_ncsi_port_wt_u; + +/* Define the union csr_cir_data_in_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_data_in_fifo_af_th_mac03 : 6; /* [5:0] */ + u32 rsv_3 : 2; /* [7:6] */ + u32 cir_data_in_fifo_af_th_mac47 : 6; /* [13:8] */ + u32 rsv_4 : 2; /* [15:14] */ + u32 cir_data_in_fifo_af_th_lprts : 6; /* [21:16] */ + u32 rsv_5 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_data_in_fifo_af_th_u; + +/* Define the union csr_cir_alc_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_fifo_af_th_mac03 : 5; /* [4:0] */ + u32 rsv_6 : 3; /* [7:5] */ + u32 cir_alc_fifo_af_th_mac47 : 5; /* [12:8] */ + u32 rsv_7 : 3; /* [15:13] */ + u32 cir_alc_fifo_af_th_lprts : 5; /* [20:16] */ + u32 rsv_8 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_fifo_af_th_u; + +/* Define the union csr_cir_rpci_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_rpci_fifo_af_th_mac03 : 5; /* [4:0] */ + u32 rsv_9 : 3; /* [7:5] */ + u32 cir_rpci_fifo_af_th_mac47 : 5; /* [12:8] */ + u32 rsv_10 : 3; /* [15:13] */ + u32 cir_rpci_fifo_af_th_lprts : 5; /* [20:16] */ + u32 rsv_11 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_rpci_fifo_af_th_u; + +/* Define the union csr_cir_alc_rp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_rp_th_mac03 : 7; /* [6:0] */ + u32 rsv_12 : 1; /* [7] */ + u32 cir_alc_rp_th_mac47 : 7; /* [14:8] */ + u32 rsv_13 : 1; /* [15] */ + u32 cir_alc_rp_th_lprts : 7; /* [22:16] */ + u32 rsv_14 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_rp_th_u; + +/* Define the union csr_cir_data_in_fifo_drop_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_data_in_fifo_drop_th_mac03 : 6; /* [5:0] */ + u32 rsv_15 : 2; /* [7:6] */ + u32 cir_data_in_fifo_drop_th_mac47 : 6; /* [13:8] */ + u32 rsv_16 : 2; /* [15:14] */ + u32 cir_data_in_fifo_drop_th_lprts : 6; /* [21:16] */ + u32 rsv_17 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_data_in_fifo_drop_th_u; + +/* Define the union csr_cir_ipsurx_bp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_ipsurx_bp_en : 1; /* [0] */ + u32 rsv_18 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_ipsurx_bp_en_u; + +/* Define the union csr_cir_alc_shp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_shp_en : 1; /* [0] */ + u32 rsv_19 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_shp_en_u; + +/* Define the union csr_cpt_mac03_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_mac03_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_mac03_ts_u; + +/* Define the union csr_cpt_mac47_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_mac47_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_mac47_ts_u; + +/* Define the union csr_cpt_maclb_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_maclb_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_maclb_ts_u; + +/* Define the union csr_cpt_ts_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_ts_len : 5; /* [4:0] */ + u32 rsv_20 : 3; /* [7:5] */ + u32 cpt_ts_cfg_done : 1; /* [8] */ + u32 rsv_21 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_ts_cfg_u; + +/* Define the union csr_cpt_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_fifo_crdt_init_dat : 6; /* [5:0] */ + u32 rsv_22 : 2; /* [7:6] */ + u32 cpt_fifo_crdt_init : 1; /* [8] */ + u32 rsv_23 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_crdt_init_u; + +/* Define the union csr_cpt_dealc_tx_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dealc_tx_af_th : 7; /* [6:0] */ + u32 rsv_24 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dealc_tx_af_th_u; + +/* Define the union csr_cpt_dealc_rx_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dealc_rx_af_th : 7; /* [6:0] */ + u32 rsv_25 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dealc_rx_af_th_u; + +/* Define the union csr_cpt_prls_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_prls_af_th : 7; /* [6:0] */ + u32 rsv_26 : 1; /* [7] */ + u32 cpt_pro_prls_fifo_af_th : 5; /* [12:8] */ + u32 rsv_27 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_prls_af_th_u; + +/* Define the union csr_cpt_col_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_deast_col_th : 7; /* [6:0] */ + u32 rsv_28 : 1; /* [7] */ + u32 cpt_ast_col_th : 7; /* [14:8] */ + u32 rsv_29 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_col_th_u; + +/* Define the union csr_cpt_pro_di_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_di_fifo_af_th : 5; /* [4:0] */ + u32 rsv_30 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_di_fifo_af_th_u; + +/* Define the union csr_cpt_pro_dealc_tx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_dealc_tx_fifo_af_th : 5; /* [4:0] */ + u32 rsv_31 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_dealc_tx_fifo_af_th_u; + +/* Define the union csr_cpt_pro_dealc_rx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_dealc_rx_fifo_af_th : 5; /* [4:0] */ + u32 rsv_32 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_dealc_rx_fifo_af_th_u; + +/* Define the union csr_cpt_pro_fifo_crdt_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_dat_fifo_crdt_init_dat : 5; /* [4:0] */ + u32 rsv_33 : 3; /* [7:5] */ + u32 cpt_pro_dat_fifo_crdt_init : 1; /* [8] */ + u32 rsv_34 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_fifo_crdt_init_u; + +/* Define the union csr_cpt_pro_dealc_rp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_dealc_rp_th : 7; /* [6:0] */ + u32 rsv_35 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_dealc_rp_th_u; + +/* Define the union csr_cpt_out_err_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_petx_err_en : 1; /* [0] */ + u32 cpb_petx_ftso_err_en : 1; /* [1] */ + u32 rsv_36 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_out_err_en_u; + +/* Define the union csr_cpt_txlb_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_txlb_en : 1; /* [0] */ + u32 rsv_37 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_txlb_en_u; + +/* Define the union csr_tx_crr0_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx0_crr_vld : 8; /* [7:0] */ + u32 cpbtx0_crr_len : 3; /* [10:8] */ + u32 rsv_38 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr0_en_u; + +/* Define the union csr_tx_crr0_pid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx0_crr_pid0 : 3; /* [2:0] */ + u32 rsv_39 : 1; /* [3] */ + u32 cpbtx0_crr_pid1 : 3; /* [6:4] */ + u32 rsv_40 : 1; /* [7] */ + u32 cpbtx0_crr_pid2 : 3; /* [10:8] */ + u32 rsv_41 : 1; /* [11] */ + u32 cpbtx0_crr_pid3 : 3; /* [14:12] */ + u32 rsv_42 : 1; /* [15] */ + u32 cpbtx0_crr_pid4 : 3; /* [18:16] */ + u32 rsv_43 : 1; /* [19] */ + u32 cpbtx0_crr_pid5 : 3; /* [22:20] */ + u32 rsv_44 : 1; /* [23] */ + u32 cpbtx0_crr_pid6 : 3; /* [26:24] */ + u32 rsv_45 : 1; /* [27] */ + u32 cpbtx0_crr_pid7 : 3; /* [30:28] */ + u32 rsv_46 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr0_pid_u; + +/* Define the union csr_tx_crr1_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx1_crr_vld : 8; /* [7:0] */ + u32 cpbtx1_crr_len : 3; /* [10:8] */ + u32 rsv_47 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr1_en_u; + +/* Define the union csr_tx_crr1_pid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx1_crr_pid0 : 3; /* [2:0] */ + u32 rsv_48 : 1; /* [3] */ + u32 cpbtx1_crr_pid1 : 3; /* [6:4] */ + u32 rsv_49 : 1; /* [7] */ + u32 cpbtx1_crr_pid2 : 3; /* [10:8] */ + u32 rsv_50 : 1; /* [11] */ + u32 cpbtx1_crr_pid3 : 3; /* [14:12] */ + u32 rsv_51 : 1; /* [15] */ + u32 cpbtx1_crr_pid4 : 3; /* [18:16] */ + u32 rsv_52 : 1; /* [19] */ + u32 cpbtx1_crr_pid5 : 3; /* [22:20] */ + u32 rsv_53 : 1; /* [23] */ + u32 cpbtx1_crr_pid6 : 3; /* [26:24] */ + u32 rsv_54 : 1; /* [27] */ + u32 cpbtx1_crr_pid7 : 3; /* [30:28] */ + u32 rsv_55 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr1_pid_u; + +/* Define the union csr_tx_crr2_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx2_crr_vld : 8; /* [7:0] */ + u32 cpbtx2_crr_len : 3; /* [10:8] */ + u32 rsv_56 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr2_en_u; + +/* Define the union csr_tx_crr2_pid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpbtx2_crr_pid0 : 2; /* [1:0] */ + u32 rsv_57 : 2; /* [3:2] */ + u32 cpbtx2_crr_pid1 : 2; /* [5:4] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 cpbtx2_crr_pid2 : 2; /* [9:8] */ + u32 rsv_59 : 2; /* [11:10] */ + u32 cpbtx2_crr_pid3 : 2; /* [13:12] */ + u32 rsv_60 : 2; /* [15:14] */ + u32 cpbtx2_crr_pid4 : 2; /* [17:16] */ + u32 rsv_61 : 2; /* [19:18] */ + u32 cpbtx2_crr_pid5 : 2; /* [21:20] */ + u32 rsv_62 : 2; /* [23:22] */ + u32 cpbtx2_crr_pid6 : 2; /* [25:24] */ + u32 rsv_63 : 2; /* [27:26] */ + u32 cpbtx2_crr_pid7 : 2; /* [29:28] */ + u32 rsv_64 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crr2_pid_u; + +/* Define the union csr_tx_chn_crdt_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_0 : 7; /* [6:0] */ + u32 rsv_65 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg0_u; + +/* Define the union csr_tx_chn_crdt_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_1 : 7; /* [6:0] */ + u32 rsv_66 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg1_u; + +/* Define the union csr_tx_chn_crdt_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_2 : 7; /* [6:0] */ + u32 rsv_67 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg2_u; + +/* Define the union csr_tx_chn_crdt_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_3 : 7; /* [6:0] */ + u32 rsv_68 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg3_u; + +/* Define the union csr_tx_chn_crdt_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_4 : 7; /* [6:0] */ + u32 rsv_69 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg4_u; + +/* Define the union csr_tx_chn_crdt_cfg5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_5 : 7; /* [6:0] */ + u32 rsv_70 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg5_u; + +/* Define the union csr_tx_chn_crdt_cfg6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_6 : 7; /* [6:0] */ + u32 rsv_71 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg6_u; + +/* Define the union csr_tx_chn_crdt_cfg7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_7 : 7; /* [6:0] */ + u32 rsv_72 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg7_u; + +/* Define the union csr_tx_chn_crdt_cfg8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_8 : 7; /* [6:0] */ + u32 rsv_73 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg8_u; + +/* Define the union csr_tx_chn_crdt_cfg9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_9 : 7; /* [6:0] */ + u32 rsv_74 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg9_u; + +/* Define the union csr_tx_chn_crdt_cfg10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_10 : 7; /* [6:0] */ + u32 rsv_75 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_cfg10_u; + +/* Define the union csr_cpb_tx_crdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_idx_crdt : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 tx_dat_prealc_crdt : 3; /* [10:8] */ + u32 rsv_77 : 5; /* [15:11] */ + u32 tx_crdt_bp_gap : 4; /* [19:16] */ + u32 rsv_78 : 4; /* [23:20] */ + u32 petx_idx_bp_gap : 4; /* [27:24] */ + u32 rsv_79 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_crdt_cfg_u; + +/* Define the union csr_txlb_pd_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txlp_pd_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_80 : 2; /* [7:6] */ + u32 txlp_pd_fifo_af_th : 6; /* [13:8] */ + u32 rsv_81 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txlb_pd_fifo_cfg_u; + +/* Define the union csr_tx_cos_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_cos_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_82 : 2; /* [7:6] */ + u32 tx_cos_fifo_af_th : 6; /* [13:8] */ + u32 rsv_83 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_cos_fifo_cfg_u; + +/* Define the union csr_ftso_rls_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ftso_rls_fifo_ae_th : 6; /* [5:0] */ + u32 rsv_84 : 2; /* [7:6] */ + u32 ftso_rls_fifo_af_th : 6; /* [13:8] */ + u32 rsv_85 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ftso_rls_fifo_cfg_u; + +/* Define the union csr_tx_idx_wt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_idx_req_wt0 : 3; /* [2:0] */ + u32 rsv_86 : 1; /* [3] */ + u32 cpt_idx_req_wt1 : 3; /* [6:4] */ + u32 rsv_87 : 1; /* [7] */ + u32 cpt_idx_req_wt2 : 3; /* [10:8] */ + u32 rsv_88 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_idx_wt_u; + +/* Define the union csr_mag_bp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cpb_bp_en : 1; /* [0] */ + u32 rsv_89 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_bp_en_u; + +/* Define the union csr_tx_tso3_rls_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tso3_rls_fifo_ae_th : 7; /* [6:0] */ + u32 rsv_90 : 1; /* [7] */ + u32 tx_tso3_rls_fifo_af_th : 7; /* [14:8] */ + u32 rsv_91 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_tso3_rls_fifo_cfg_u; + +/* Define the union csr_cir_dat_in_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_di_ctrl_fifo_sta : 11; /* [10:0] */ + u32 rsv_92 : 5; /* [15:11] */ + u32 cir_di_fifo_sta : 11; /* [26:16] */ + u32 rsv_93 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_dat_in_fifo_sta_u; + +/* Define the union csr_cir_rpt_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_fifo_sta : 11; /* [10:0] */ + u32 rsv_94 : 5; /* [15:11] */ + u32 cir_rpt_pci_sta : 11; /* [26:16] */ + u32 rsv_95 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_rpt_fifo_sta_u; + +/* Define the union csr_cir_in_pkt_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_in_pkt_sop_cnt : 16; /* [15:0] */ + u32 rsv_96 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_in_pkt_sop_cnt_u; + +/* Define the union csr_cir_in_pkt_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_in_pkt_eop_cnt : 16; /* [15:0] */ + u32 rsv_97 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_in_pkt_eop_cnt_u; + +/* Define the union csr_cir_in_port_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_in_port_pkt_cnt : 16; /* [15:0] */ + u32 rsv_98 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_in_port_pkt_cnt_u; + +/* Define the union csr_cir_drp_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_drp_pkt_cnt : 16; /* [15:0] */ + u32 rsv_99 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_drp_pkt_cnt_u; + +/* Define the union csr_cir_fifo_af_drp_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_fifo_af_drp_pkt_cnt : 16; /* [15:0] */ + u32 rsv_100 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_fifo_af_drp_pkt_cnt_u; + +/* Define the union csr_cir_bmu_af_drp_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_bmu_af_drp_pkt_cnt : 16; /* [15:0] */ + u32 rsv_101 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_bmu_af_drp_pkt_cnt_u; + +/* Define the union csr_cir_fifo_af_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_fifo_af_cnt : 16; /* [15:0] */ + u32 rsv_102 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_fifo_af_cnt_u; + +/* Define the union csr_cir_cut_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_cut_pkt_cnt : 16; /* [15:0] */ + u32 rsv_103 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_cut_pkt_cnt_u; + +/* Define the union csr_cir_rpt_iq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_rpt_iq_cnt : 16; /* [15:0] */ + u32 rsv_104 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_rpt_iq_cnt_u; + +/* Define the union csr_cir_iq_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_iq_bp_cnt : 16; /* [15:0] */ + u32 rsv_105 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_iq_bp_cnt_u; + +/* Define the union csr_cir_sport_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_sport_err : 1; /* [0] */ + u32 rsv_106 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_sport_err_u; + +/* Define the union csr_cir_alc_prm_cnum_full_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_alc_prm_cnum_full_err : 1; /* [0] */ + u32 rsv_107 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_alc_prm_cnum_full_err_u; + +/* Define the union csr_cir_fifo_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_di_fifo_uf : 3; /* [2:0] */ + u32 rsv_108 : 1; /* [3] */ + u32 cir_di_ctrl_fifo_uf : 3; /* [6:4] */ + u32 rsv_109 : 1; /* [7] */ + u32 cir_rpt_pci_uf : 3; /* [10:8] */ + u32 rsv_110 : 1; /* [11] */ + u32 cir_alc_fifo_uf : 3; /* [14:12] */ + u32 rsv_111 : 1; /* [15] */ + u32 cir_di_fifo_ov : 3; /* [18:16] */ + u32 rsv_112 : 1; /* [19] */ + u32 cir_di_ctrl_fifo_ov : 3; /* [22:20] */ + u32 rsv_113 : 1; /* [23] */ + u32 cir_rpt_pci_ov : 3; /* [26:24] */ + u32 rsv_114 : 1; /* [27] */ + u32 cir_alc_fifo_ov : 3; /* [30:28] */ + u32 rsv_115 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_fifo_err_u; + +/* Define the union csr_cir_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_fifo_mem_err_addr : 6; /* [5:0] */ + u32 rsv_116 : 6; /* [11:6] */ + u32 cir_fifo_mem_err_cerr : 1; /* [12] */ + u32 cir_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_117 : 2; /* [15:14] */ + u32 cir_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_fifo_ram_err_u; + +/* Define the union csr_cir_prm_bp_his_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_prm_bp_his_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_prm_bp_his_0_u; + +/* Define the union csr_cir_prm_bp_his_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_prm_bp_his_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_prm_bp_his_1_u; + +/* Define the union csr_cir_prm_bp_his_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_prm_bp_his_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_prm_bp_his_2_u; + +/* Define the union csr_cir_prm_bp_his_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_prm_bp_his_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_prm_bp_his_3_u; + +/* Define the union csr_cir_prm_bp_his_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cir_prm_bp_his_4 : 9; /* [8:0] */ + u32 rsv_118 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cir_prm_bp_his_4_u; + +/* Define the union csr_cpt_pro_dat_in_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_di_fifo_sta : 11; /* [10:0] */ + u32 rsv_119 : 5; /* [15:11] */ + u32 cpt_pro_prls_fifo_sta : 9; /* [24:16] */ + u32 rsv_120 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_dat_in_fifo_sta_u; + +/* Define the union csr_cpt_pro_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_dealc_rx_fifo_sta : 11; /* [10:0] */ + u32 rsv_121 : 5; /* [15:11] */ + u32 cpt_pro_dealc_tx_fifo_sta : 11; /* [26:16] */ + u32 rsv_122 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_pro_dealc_fifo_sta_u; + +/* Define the union csr_cpt_dealc_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dealc_rx_fifo_sta : 11; /* [10:0] */ + u32 rsv_123 : 5; /* [15:11] */ + u32 cpt_dealc_tx_fifo_sta : 11; /* [26:16] */ + u32 rsv_124 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dealc_fifo_sta_u; + +/* Define the union csr_cpt_prls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_prls_fifo_sta : 11; /* [10:0] */ + u32 rsv_125 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_prls_fifo_sta_u; + +/* Define the union csr_cpt_dat_out_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dat_out_fifo_sta : 11; /* [10:0] */ + u32 rsv_126 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dat_out_fifo_sta_u; + +/* Define the union csr_cpt_out_pkt_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_out_pkt_sop_cnt : 16; /* [15:0] */ + u32 rsv_127 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_out_pkt_sop_cnt_u; + +/* Define the union csr_cpt_out_pkt_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_out_pkt_eop_cnt : 16; /* [15:0] */ + u32 rsv_128 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_out_pkt_eop_cnt_u; + +/* Define the union csr_cpt_out_chnl_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_out_chnl_pkt_cnt : 16; /* [15:0] */ + u32 rsv_129 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_out_chnl_pkt_cnt_u; + +/* Define the union csr_cpt_sof_msm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_sof_msm_info : 28; /* [27:0] */ + u32 rsv_130 : 3; /* [30:28] */ + u32 cpt_sof_msm : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_sof_msm_u; + +/* Define the union csr_cpt_eof_msm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_eof_msm_info : 28; /* [27:0] */ + u32 rsv_131 : 3; /* [30:28] */ + u32 cpt_eof_msm : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_eof_msm_u; + +/* Define the union csr_cpt_dealc_tx_bp_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dealc_tx_bp_tm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dealc_tx_bp_tm_u; + +/* Define the union csr_cpt_dealc_rx_bp_tm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_dealc_rx_bp_tm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_dealc_rx_bp_tm_u; + +/* Define the union csr_cpt_ts_cfg_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_ts_cfg_err : 1; /* [0] */ + u32 rsv_132 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_ts_cfg_err_u; + +/* Define the union csr_cpt_fifo_ov_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_di_fifo_ov : 3; /* [2:0] */ + u32 rsv_133 : 1; /* [3] */ + u32 cpt_pro_dealc_tx_fifo_ov : 3; /* [6:4] */ + u32 rsv_134 : 1; /* [7] */ + u32 cpt_pro_dealc_rx_fifo_ov : 3; /* [10:8] */ + u32 rsv_135 : 1; /* [11] */ + u32 cpt_dat_out_fifo_ov : 3; /* [14:12] */ + u32 rsv_136 : 1; /* [15] */ + u32 cpt_dealc_tx_fifo_ov : 1; /* [16] */ + u32 cpt_dealc_rx_fifo_ov : 1; /* [17] */ + u32 cpt_prls_fifo_ov : 1; /* [18] */ + u32 cpt_pro_prls_fifo_ov : 3; /* [21:19] */ + u32 rsv_137 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_fifo_ov_err_u; + +/* Define the union csr_cpt_fifo_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_pro_di_fifo_uf : 3; /* [2:0] */ + u32 rsv_138 : 1; /* [3] */ + u32 cpt_pro_dealc_tx_fifo_uf : 3; /* [6:4] */ + u32 rsv_139 : 1; /* [7] */ + u32 cpt_pro_dealc_rx_fifo_uf : 3; /* [10:8] */ + u32 rsv_140 : 1; /* [11] */ + u32 cpt_dat_out_fifo_uf : 3; /* [14:12] */ + u32 rsv_141 : 1; /* [15] */ + u32 cpt_dealc_tx_fifo_uf : 1; /* [16] */ + u32 cpt_dealc_rx_fifo_uf : 1; /* [17] */ + u32 cpt_prls_fifo_uf : 1; /* [18] */ + u32 cpt_pro_prls_fifo_uf : 3; /* [21:19] */ + u32 rsv_142 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_fifo_uf_err_u; + +/* Define the union csr_cpt_fifo_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpt_fifo_mem_err_addr : 4; /* [3:0] */ + u32 rsv_143 : 8; /* [11:4] */ + u32 cpt_fifo_mem_err_cerr : 1; /* [12] */ + u32 cpt_fifo_mem_err_ucerr : 1; /* [13] */ + u32 rsv_144 : 2; /* [15:14] */ + u32 cpt_fifo_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpt_fifo_ram_err_u; + +/* Define the union csr_tx_chn_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_crdt_cnt : 7; /* [6:0] */ + u32 rsv_145 : 1; /* [7] */ + u32 tx_chn_crdt_af : 1; /* [8] */ + u32 rsv_146 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_chn_crdt_sta_u; + +/* Define the union csr_tx_idx_crdt_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_idx_crdt_cnt : 6; /* [5:0] */ + u32 rsv_147 : 2; /* [7:6] */ + u32 tx_idx_crdt_af : 1; /* [8] */ + u32 rsv_148 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_idx_crdt_sta_u; + +/* Define the union csr_tx_fp_bmp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fp_bmp_fill : 8; /* [7:0] */ + u32 rsv_149 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_fp_bmp_sta_u; + +/* Define the union csr_txpd_fifo_empty_sta_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_empty_sta_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_empty_sta_0_u; + +/* Define the union csr_txpd_fifo_empty_sta_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_empty_sta_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_empty_sta_1_u; + +/* Define the union csr_txpd_fifo_empty_sta_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_empty_sta_2 : 3; /* [2:0] */ + u32 rsv_150 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_empty_sta_2_u; + +/* Define the union csr_txpd_fifo_fill_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_fill_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_fill_sta_u; + +/* Define the union csr_txpd_pro_fsm_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_pro_fsm_sta : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_pro_fsm_sta_u; + +/* Define the union csr_mag_bp_sta_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cpb_bp_sta_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_bp_sta_0_u; + +/* Define the union csr_mag_bp_sta_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_cpb_bp_sta_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mag_bp_sta_1_u; + +/* Define the union csr_tx_ftso_rls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_ftsorls_fifo_sta_0 : 10; /* [9:0] */ + u32 rsv_151 : 6; /* [15:10] */ + u32 tx_ftsorls_fifo_sta_1 : 10; /* [25:16] */ + u32 rsv_152 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_ftso_rls_fifo_sta_u; + +/* Define the union csr_tx_tso3_rls_fifo_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tso3_rls_fifo_sta : 11; /* [10:0] */ + u32 rsv_153 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_tso3_rls_fifo_sta_u; + +/* Define the union csr_tx_crdt_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_idx_crdt_of_err : 1; /* [0] */ + u32 tx_chn_crdt_of_err : 11; /* [11:1] */ + u32 rsv_154 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crdt_of_err_u; + +/* Define the union csr_tx_crdt_uf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_idx_crdt_uf_err : 1; /* [0] */ + u32 tx_chn_crdt_uf_err : 11; /* [11:1] */ + u32 rsv_155 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_crdt_uf_err_u; + +/* Define the union csr_txpd_fifo_of_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_of_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_of_err_0_u; + +/* Define the union csr_txpd_fifo_of_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_of_err_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_of_err_1_u; + +/* Define the union csr_txpd_fifo_of_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_of_err_2 : 3; /* [2:0] */ + u32 tx_fp_fifo_of_err : 8; /* [10:3] */ + u32 tx_tso3_rls_fifo_of_err : 3; /* [13:11] */ + u32 rsv_156 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_of_err_2_u; + +/* Define the union csr_txpd_fifo_uf_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_uf_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_uf_err_0_u; + +/* Define the union csr_txpd_fifo_uf_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_uf_err_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_uf_err_1_u; + +/* Define the union csr_txpd_fifo_uf_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txpd_fifo_uf_err_2 : 3; /* [2:0] */ + u32 tx_fp_fifo_uf_err : 8; /* [10:3] */ + u32 tx_tso3_rls_fifo_uf_err : 3; /* [13:11] */ + u32 rsv_157 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_txpd_fifo_uf_err_2_u; + +/* Define the union csr_tx_ftso_rls_fifo_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_ftso_rls_fifo_uf_err : 2; /* [1:0] */ + u32 tx_ftso_rls_fifo_of_err : 2; /* [3:2] */ + u32 rsv_158 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_ftso_rls_fifo_err_u; + +/* Define the union csr_tso_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tso_mem_err_addr : 12; /* [11:0] */ + u32 tso_mem_err_cerr : 1; /* [12] */ + u32 tso_mem_err_ucerr : 1; /* [13] */ + u32 rsv_159 : 2; /* [15:14] */ + u32 tso_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tso_ram_err_u; + +/* Define the union csr_tx_pd_ram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_pd_mem_err_addr : 7; /* [6:0] */ + u32 rsv_160 : 5; /* [11:7] */ + u32 tx_pd_mem_err_cerr : 1; /* [12] */ + u32 tx_pd_mem_err_ucerr : 1; /* [13] */ + u32 rsv_161 : 2; /* [15:14] */ + u32 tx_pd_mem_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tx_pd_ram_err_u; + +/* Define the union csr_cpb_tx_err_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_pd_pptr_err : 11; /* [10:0] */ + u32 rsv_162 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_0_u; + +/* Define the union csr_cpb_tx_err_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_pd_pktmod_err : 11; /* [10:0] */ + u32 rsv_163 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_1_u; + +/* Define the union csr_cpb_tx_err_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_ret_pcnum_err : 11; /* [10:0] */ + u32 rsv_164 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_2_u; + +/* Define the union csr_cpb_tx_err_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_tso1_num_err : 11; /* [10:0] */ + u32 tx_chn_tso1_cmd_cnum_err : 11; /* [21:11] */ + u32 rsv_165 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_3_u; + +/* Define the union csr_cpb_tx_err_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_tso2_num_err : 11; /* [10:0] */ + u32 tx_chn_tso2_cmd_cnum_err : 11; /* [21:11] */ + u32 tx_chn_tso2_cmd_cnum_err0 : 1; /* [22] */ + u32 tx_chn_tso2_cmd_cnum_err1 : 1; /* [23] */ + u32 tx_chn_tso2_cmd_cnum_err2 : 1; /* [24] */ + u32 rsv_166 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_4_u; + +/* Define the union csr_cpb_tx_err_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_chn_lro2_num_err : 11; /* [10:0] */ + u32 tx_chn_lro2_cmd_cnum_err : 11; /* [21:11] */ + u32 tx_chn_lro2_cmd_cnum_err0 : 1; /* [22] */ + u32 tx_chn_lro2_cmd_cnum_err1 : 1; /* [23] */ + u32 tx_chn_lro2_cmd_cnum_err2 : 1; /* [24] */ + u32 rsv_167 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_tx_err_5_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cpb_indir_dat_u cpb_indir_dat[16]; /* 180 */ + volatile csr_cir_alc_pro_wt_u cir_alc_pro_wt; /* 400 */ + volatile csr_cir_rpci_pro_wt_u cir_rpci_pro_wt; /* 404 */ + volatile csr_cir_alc_mac_ncsi_port_wt_u cir_alc_mac_ncsi_port_wt; /* 408 */ + volatile csr_cir_data_in_fifo_af_th_u cir_data_in_fifo_af_th; /* 410 */ + volatile csr_cir_alc_fifo_af_th_u cir_alc_fifo_af_th; /* 414 */ + volatile csr_cir_rpci_fifo_af_th_u cir_rpci_fifo_af_th; /* 418 */ + volatile csr_cir_alc_rp_th_u cir_alc_rp_th; /* 41C */ + volatile csr_cir_data_in_fifo_drop_th_u cir_data_in_fifo_drop_th; /* 420 */ + volatile csr_cir_ipsurx_bp_en_u cir_ipsurx_bp_en; /* 424 */ + volatile csr_cir_alc_shp_en_u cir_alc_shp_en; /* 428 */ + volatile csr_cpt_mac03_ts_u cpt_mac03_ts; /* 700 */ + volatile csr_cpt_mac47_ts_u cpt_mac47_ts; /* 704 */ + volatile csr_cpt_maclb_ts_u cpt_maclb_ts; /* 708 */ + volatile csr_cpt_ts_cfg_u cpt_ts_cfg; /* 70C */ + volatile csr_cpt_crdt_init_u cpt_crdt_init; /* 710 */ + volatile csr_cpt_dealc_tx_af_th_u cpt_dealc_tx_af_th; /* 720 */ + volatile csr_cpt_dealc_rx_af_th_u cpt_dealc_rx_af_th; /* 724 */ + volatile csr_cpt_prls_af_th_u cpt_prls_af_th; /* 728 */ + volatile csr_cpt_col_th_u cpt_col_th; /* 72C */ + volatile csr_cpt_pro_di_fifo_af_th_u cpt_pro_di_fifo_af_th; /* 740 */ + volatile csr_cpt_pro_dealc_tx_fifo_af_th_u cpt_pro_dealc_tx_fifo_af_th; /* 744 */ + volatile csr_cpt_pro_dealc_rx_fifo_af_th_u cpt_pro_dealc_rx_fifo_af_th; /* 748 */ + volatile csr_cpt_pro_fifo_crdt_init_u cpt_pro_fifo_crdt_init; /* 74C */ + volatile csr_cpt_pro_dealc_rp_th_u cpt_pro_dealc_rp_th; /* 750 */ + volatile csr_cpt_out_err_en_u cpt_out_err_en; /* 754 */ + volatile csr_cpt_txlb_en_u cpt_txlb_en; /* 758 */ + volatile csr_tx_crr0_en_u tx_crr0_en; /* C00 */ + volatile csr_tx_crr0_pid_u tx_crr0_pid; /* C04 */ + volatile csr_tx_crr1_en_u tx_crr1_en; /* C08 */ + volatile csr_tx_crr1_pid_u tx_crr1_pid; /* C0C */ + volatile csr_tx_crr2_en_u tx_crr2_en; /* C10 */ + volatile csr_tx_crr2_pid_u tx_crr2_pid; /* C14 */ + volatile csr_tx_chn_crdt_cfg0_u tx_chn_crdt_cfg0; /* C20 */ + volatile csr_tx_chn_crdt_cfg1_u tx_chn_crdt_cfg1; /* C24 */ + volatile csr_tx_chn_crdt_cfg2_u tx_chn_crdt_cfg2; /* C28 */ + volatile csr_tx_chn_crdt_cfg3_u tx_chn_crdt_cfg3; /* C2C */ + volatile csr_tx_chn_crdt_cfg4_u tx_chn_crdt_cfg4; /* C30 */ + volatile csr_tx_chn_crdt_cfg5_u tx_chn_crdt_cfg5; /* C34 */ + volatile csr_tx_chn_crdt_cfg6_u tx_chn_crdt_cfg6; /* C38 */ + volatile csr_tx_chn_crdt_cfg7_u tx_chn_crdt_cfg7; /* C3C */ + volatile csr_tx_chn_crdt_cfg8_u tx_chn_crdt_cfg8; /* C40 */ + volatile csr_tx_chn_crdt_cfg9_u tx_chn_crdt_cfg9; /* C44 */ + volatile csr_tx_chn_crdt_cfg10_u tx_chn_crdt_cfg10; /* C48 */ + volatile csr_cpb_tx_crdt_cfg_u cpb_tx_crdt_cfg; /* C50 */ + volatile csr_txlb_pd_fifo_cfg_u txlb_pd_fifo_cfg; /* C60 */ + volatile csr_tx_cos_fifo_cfg_u tx_cos_fifo_cfg; /* C64 */ + volatile csr_ftso_rls_fifo_cfg_u ftso_rls_fifo_cfg; /* C68 */ + volatile csr_tx_idx_wt_u tx_idx_wt; /* C70 */ + volatile csr_mag_bp_en_u mag_bp_en; /* C74 */ + volatile csr_tx_tso3_rls_fifo_cfg_u tx_tso3_rls_fifo_cfg; /* C80 */ + volatile csr_cir_dat_in_fifo_sta_u cir_dat_in_fifo_sta[3]; /* 1000 */ + volatile csr_cir_rpt_fifo_sta_u cir_rpt_fifo_sta[3]; /* 1010 */ + volatile csr_cir_in_pkt_sop_cnt_u cir_in_pkt_sop_cnt; /* 1020 */ + volatile csr_cir_in_pkt_eop_cnt_u cir_in_pkt_eop_cnt; /* 1024 */ + volatile csr_cir_in_port_pkt_cnt_u cir_in_port_pkt_cnt[11]; /* 1030 */ + volatile csr_cir_drp_pkt_cnt_u cir_drp_pkt_cnt[3]; /* 1060 */ + volatile csr_cir_fifo_af_drp_pkt_cnt_u cir_fifo_af_drp_pkt_cnt[3]; /* 1070 */ + volatile csr_cir_bmu_af_drp_pkt_cnt_u cir_bmu_af_drp_pkt_cnt[3]; /* 1080 */ + volatile csr_cir_fifo_af_cnt_u cir_fifo_af_cnt[3]; /* 1090 */ + volatile csr_cir_cut_pkt_cnt_u cir_cut_pkt_cnt[3]; /* 10A0 */ + volatile csr_cir_rpt_iq_cnt_u cir_rpt_iq_cnt; /* 10B0 */ + volatile csr_cir_iq_bp_cnt_u cir_iq_bp_cnt; /* 10B4 */ + volatile csr_cir_sport_err_u cir_sport_err; /* 10B8 */ + volatile csr_cir_alc_prm_cnum_full_err_u cir_alc_prm_cnum_full_err; /* 10BC */ + volatile csr_cir_fifo_err_u cir_fifo_err; /* 10C0 */ + volatile csr_cir_fifo_ram_err_u cir_fifo_ram_err[3]; /* 10D0 */ + volatile csr_cir_prm_bp_his_0_u cir_prm_bp_his_0; /* 10E8 */ + volatile csr_cir_prm_bp_his_1_u cir_prm_bp_his_1; /* 10EC */ + volatile csr_cir_prm_bp_his_2_u cir_prm_bp_his_2; /* 10F0 */ + volatile csr_cir_prm_bp_his_3_u cir_prm_bp_his_3; /* 10F4 */ + volatile csr_cir_prm_bp_his_4_u cir_prm_bp_his_4; /* 10F8 */ + volatile csr_cpt_pro_dat_in_fifo_sta_u cpt_pro_dat_in_fifo_sta[3]; /* 1300 */ + volatile csr_cpt_pro_dealc_fifo_sta_u cpt_pro_dealc_fifo_sta[3]; /* 1310 */ + volatile csr_cpt_dealc_fifo_sta_u cpt_dealc_fifo_sta; /* 1320 */ + volatile csr_cpt_prls_fifo_sta_u cpt_prls_fifo_sta; /* 1324 */ + volatile csr_cpt_dat_out_fifo_sta_u cpt_dat_out_fifo_sta[3]; /* 1330 */ + volatile csr_cpt_out_pkt_sop_cnt_u cpt_out_pkt_sop_cnt; /* 1340 */ + volatile csr_cpt_out_pkt_eop_cnt_u cpt_out_pkt_eop_cnt; /* 1344 */ + volatile csr_cpt_out_chnl_pkt_cnt_u cpt_out_chnl_pkt_cnt[11]; /* 1350 */ + volatile csr_cpt_sof_msm_u cpt_sof_msm[3]; /* 1380 */ + volatile csr_cpt_eof_msm_u cpt_eof_msm[3]; /* 1390 */ + volatile csr_cpt_dealc_tx_bp_tm_u cpt_dealc_tx_bp_tm; /* 13A0 */ + volatile csr_cpt_dealc_rx_bp_tm_u cpt_dealc_rx_bp_tm; /* 13A4 */ + volatile csr_cpt_ts_cfg_err_u cpt_ts_cfg_err; /* 13A8 */ + volatile csr_cpt_fifo_ov_err_u cpt_fifo_ov_err; /* 13AC */ + volatile csr_cpt_fifo_uf_err_u cpt_fifo_uf_err; /* 13B0 */ + volatile csr_cpt_fifo_ram_err_u cpt_fifo_ram_err[3]; /* 13B4 */ + volatile csr_tx_chn_crdt_sta_u tx_chn_crdt_sta[11]; /* 1A00 */ + volatile csr_tx_idx_crdt_sta_u tx_idx_crdt_sta; /* 1A30 */ + volatile csr_tx_fp_bmp_sta_u tx_fp_bmp_sta[8]; /* 1A40 */ + volatile csr_txpd_fifo_empty_sta_0_u txpd_fifo_empty_sta_0; /* 1A60 */ + volatile csr_txpd_fifo_empty_sta_1_u txpd_fifo_empty_sta_1; /* 1A64 */ + volatile csr_txpd_fifo_empty_sta_2_u txpd_fifo_empty_sta_2; /* 1A68 */ + volatile csr_txpd_fifo_fill_sta_u txpd_fifo_fill_sta[9]; /* 1A70 */ + volatile csr_txpd_pro_fsm_sta_u txpd_pro_fsm_sta[11]; /* 1AA0 */ + volatile csr_mag_bp_sta_0_u mag_bp_sta_0; /* 1AD0 */ + volatile csr_mag_bp_sta_1_u mag_bp_sta_1; /* 1AD4 */ + volatile csr_tx_ftso_rls_fifo_sta_u tx_ftso_rls_fifo_sta; /* 1AE8 */ + volatile csr_tx_tso3_rls_fifo_sta_u tx_tso3_rls_fifo_sta[3]; /* 1AF0 */ + volatile csr_tx_crdt_of_err_u tx_crdt_of_err; /* 1B00 */ + volatile csr_tx_crdt_uf_err_u tx_crdt_uf_err; /* 1B04 */ + volatile csr_txpd_fifo_of_err_0_u txpd_fifo_of_err_0; /* 1B10 */ + volatile csr_txpd_fifo_of_err_1_u txpd_fifo_of_err_1; /* 1B14 */ + volatile csr_txpd_fifo_of_err_2_u txpd_fifo_of_err_2; /* 1B18 */ + volatile csr_txpd_fifo_uf_err_0_u txpd_fifo_uf_err_0; /* 1B20 */ + volatile csr_txpd_fifo_uf_err_1_u txpd_fifo_uf_err_1; /* 1B24 */ + volatile csr_txpd_fifo_uf_err_2_u txpd_fifo_uf_err_2; /* 1B28 */ + volatile csr_tx_ftso_rls_fifo_err_u tx_ftso_rls_fifo_err; /* 1B30 */ + volatile csr_tso_ram_err_u tso_ram_err; /* 1B34 */ + volatile csr_tx_pd_ram_err_u tx_pd_ram_err[8]; /* 1B40 */ + volatile csr_cpb_tx_err_0_u cpb_tx_err_0; /* 1B80 */ + volatile csr_cpb_tx_err_1_u cpb_tx_err_1; /* 1B84 */ + volatile csr_cpb_tx_err_2_u cpb_tx_err_2; /* 1B88 */ + volatile csr_cpb_tx_err_3_u cpb_tx_err_3; /* 1B8C */ + volatile csr_cpb_tx_err_4_u cpb_tx_err_4; /* 1B90 */ + volatile csr_cpb_tx_err_5_u cpb_tx_err_5; /* 1B94 */ +} S_cpb_csr_3_REGS_TYPE; + +/* Declare the struct pointor of the module cpb_csr_3 */ +extern volatile S_cpb_csr_3_REGS_TYPE *gopcpb_csr_3AllReg; + +/* Declare the functions that set the member value */ +int iSetCPB_INDIR_DAT_cpb_indir_dat(unsigned int ucpb_indir_dat); +int iSetCIR_ALC_PRO_WT_cir_alc_pro_wt_0(unsigned int ucir_alc_pro_wt_0); +int iSetCIR_ALC_PRO_WT_cir_alc_pro_wt_1(unsigned int ucir_alc_pro_wt_1); +int iSetCIR_ALC_PRO_WT_cir_alc_pro_wt_2(unsigned int ucir_alc_pro_wt_2); +int iSetCIR_RPCI_PRO_WT_cir_rpci_pro_wt_0(unsigned int ucir_rpci_pro_wt_0); +int iSetCIR_RPCI_PRO_WT_cir_rpci_pro_wt_1(unsigned int ucir_rpci_pro_wt_1); +int iSetCIR_RPCI_PRO_WT_cir_rpci_pro_wt_2(unsigned int ucir_rpci_pro_wt_2); +int iSetCIR_ALC_MAC_NCSI_PORT_WT_cir_alc_mac_port_wt_4_0(unsigned int ucir_alc_mac_port_wt_4_0); +int iSetCIR_ALC_MAC_NCSI_PORT_WT_cir_alc_mac_port_wt_5_1(unsigned int ucir_alc_mac_port_wt_5_1); +int iSetCIR_ALC_MAC_NCSI_PORT_WT_cir_alc_mac_port_wt_6_2(unsigned int ucir_alc_mac_port_wt_6_2); +int iSetCIR_ALC_MAC_NCSI_PORT_WT_cir_alc_mac_port_wt_7_3(unsigned int ucir_alc_mac_port_wt_7_3); +int iSetCIR_ALC_MAC_NCSI_PORT_WT_cir_alc_ncsi_port_wt(unsigned int ucir_alc_ncsi_port_wt); +int iSetCIR_DATA_IN_FIFO_AF_TH_cir_data_in_fifo_af_th_mac03(unsigned int ucir_data_in_fifo_af_th_mac03); +int iSetCIR_DATA_IN_FIFO_AF_TH_cir_data_in_fifo_af_th_mac47(unsigned int ucir_data_in_fifo_af_th_mac47); +int iSetCIR_DATA_IN_FIFO_AF_TH_cir_data_in_fifo_af_th_lprts(unsigned int ucir_data_in_fifo_af_th_lprts); +int iSetCIR_ALC_FIFO_AF_TH_cir_alc_fifo_af_th_mac03(unsigned int ucir_alc_fifo_af_th_mac03); +int iSetCIR_ALC_FIFO_AF_TH_cir_alc_fifo_af_th_mac47(unsigned int ucir_alc_fifo_af_th_mac47); +int iSetCIR_ALC_FIFO_AF_TH_cir_alc_fifo_af_th_lprts(unsigned int ucir_alc_fifo_af_th_lprts); +int iSetCIR_RPCI_FIFO_AF_TH_cir_rpci_fifo_af_th_mac03(unsigned int ucir_rpci_fifo_af_th_mac03); +int iSetCIR_RPCI_FIFO_AF_TH_cir_rpci_fifo_af_th_mac47(unsigned int ucir_rpci_fifo_af_th_mac47); +int iSetCIR_RPCI_FIFO_AF_TH_cir_rpci_fifo_af_th_lprts(unsigned int ucir_rpci_fifo_af_th_lprts); +int iSetCIR_ALC_RP_TH_cir_alc_rp_th_mac03(unsigned int ucir_alc_rp_th_mac03); +int iSetCIR_ALC_RP_TH_cir_alc_rp_th_mac47(unsigned int ucir_alc_rp_th_mac47); +int iSetCIR_ALC_RP_TH_cir_alc_rp_th_lprts(unsigned int ucir_alc_rp_th_lprts); +int iSetCIR_DATA_IN_FIFO_DROP_TH_cir_data_in_fifo_drop_th_mac03(unsigned int ucir_data_in_fifo_drop_th_mac03); +int iSetCIR_DATA_IN_FIFO_DROP_TH_cir_data_in_fifo_drop_th_mac47(unsigned int ucir_data_in_fifo_drop_th_mac47); +int iSetCIR_DATA_IN_FIFO_DROP_TH_cir_data_in_fifo_drop_th_lprts(unsigned int ucir_data_in_fifo_drop_th_lprts); +int iSetCIR_IPSURX_BP_EN_cir_ipsurx_bp_en(unsigned int ucir_ipsurx_bp_en); +int iSetCIR_ALC_SHP_EN_cir_alc_shp_en(unsigned int ucir_alc_shp_en); +int iSetCPT_MAC03_TS_cpt_mac03_ts(unsigned int ucpt_mac03_ts); +int iSetCPT_MAC47_TS_cpt_mac47_ts(unsigned int ucpt_mac47_ts); +int iSetCPT_MACLB_TS_cpt_maclb_ts(unsigned int ucpt_maclb_ts); +int iSetCPT_TS_CFG_cpt_ts_len(unsigned int ucpt_ts_len); +int iSetCPT_TS_CFG_cpt_ts_cfg_done(unsigned int ucpt_ts_cfg_done); +int iSetCPT_CRDT_INIT_cpt_fifo_crdt_init_dat(unsigned int ucpt_fifo_crdt_init_dat); +int iSetCPT_CRDT_INIT_cpt_fifo_crdt_init(unsigned int ucpt_fifo_crdt_init); +int iSetCPT_DEALC_TX_AF_TH_cpt_dealc_tx_af_th(unsigned int ucpt_dealc_tx_af_th); +int iSetCPT_DEALC_RX_AF_TH_cpt_dealc_rx_af_th(unsigned int ucpt_dealc_rx_af_th); +int iSetCPT_PRLS_AF_TH_cpt_prls_af_th(unsigned int ucpt_prls_af_th); +int iSetCPT_PRLS_AF_TH_cpt_pro_prls_fifo_af_th(unsigned int ucpt_pro_prls_fifo_af_th); +int iSetCPT_COL_TH_cpt_deast_col_th(unsigned int ucpt_deast_col_th); +int iSetCPT_COL_TH_cpt_ast_col_th(unsigned int ucpt_ast_col_th); +int iSetCPT_PRO_DI_FIFO_AF_TH_cpt_pro_di_fifo_af_th(unsigned int ucpt_pro_di_fifo_af_th); +int iSetCPT_PRO_DEALC_TX_FIFO_AF_TH_cpt_pro_dealc_tx_fifo_af_th(unsigned int ucpt_pro_dealc_tx_fifo_af_th); +int iSetCPT_PRO_DEALC_RX_FIFO_AF_TH_cpt_pro_dealc_rx_fifo_af_th(unsigned int ucpt_pro_dealc_rx_fifo_af_th); +int iSetCPT_PRO_FIFO_CRDT_INIT_cpt_pro_dat_fifo_crdt_init_dat(unsigned int ucpt_pro_dat_fifo_crdt_init_dat); +int iSetCPT_PRO_FIFO_CRDT_INIT_cpt_pro_dat_fifo_crdt_init(unsigned int ucpt_pro_dat_fifo_crdt_init); +int iSetCPT_PRO_DEALC_RP_TH_cpt_pro_dealc_rp_th(unsigned int ucpt_pro_dealc_rp_th); +int iSetCPT_OUT_ERR_EN_cpb_petx_err_en(unsigned int ucpb_petx_err_en); +int iSetCPT_OUT_ERR_EN_cpb_petx_ftso_err_en(unsigned int ucpb_petx_ftso_err_en); +int iSetCPT_TXLB_EN_cpt_txlb_en(unsigned int ucpt_txlb_en); +int iSetTX_CRR0_EN_cpbtx0_crr_vld(unsigned int ucpbtx0_crr_vld); +int iSetTX_CRR0_EN_cpbtx0_crr_len(unsigned int ucpbtx0_crr_len); +int iSetTX_CRR0_PID_cpbtx0_crr_pid0(unsigned int ucpbtx0_crr_pid0); +int iSetTX_CRR0_PID_cpbtx0_crr_pid1(unsigned int ucpbtx0_crr_pid1); +int iSetTX_CRR0_PID_cpbtx0_crr_pid2(unsigned int ucpbtx0_crr_pid2); +int iSetTX_CRR0_PID_cpbtx0_crr_pid3(unsigned int ucpbtx0_crr_pid3); +int iSetTX_CRR0_PID_cpbtx0_crr_pid4(unsigned int ucpbtx0_crr_pid4); +int iSetTX_CRR0_PID_cpbtx0_crr_pid5(unsigned int ucpbtx0_crr_pid5); +int iSetTX_CRR0_PID_cpbtx0_crr_pid6(unsigned int ucpbtx0_crr_pid6); +int iSetTX_CRR0_PID_cpbtx0_crr_pid7(unsigned int ucpbtx0_crr_pid7); +int iSetTX_CRR1_EN_cpbtx1_crr_vld(unsigned int ucpbtx1_crr_vld); +int iSetTX_CRR1_EN_cpbtx1_crr_len(unsigned int ucpbtx1_crr_len); +int iSetTX_CRR1_PID_cpbtx1_crr_pid0(unsigned int ucpbtx1_crr_pid0); +int iSetTX_CRR1_PID_cpbtx1_crr_pid1(unsigned int ucpbtx1_crr_pid1); +int iSetTX_CRR1_PID_cpbtx1_crr_pid2(unsigned int ucpbtx1_crr_pid2); +int iSetTX_CRR1_PID_cpbtx1_crr_pid3(unsigned int ucpbtx1_crr_pid3); +int iSetTX_CRR1_PID_cpbtx1_crr_pid4(unsigned int ucpbtx1_crr_pid4); +int iSetTX_CRR1_PID_cpbtx1_crr_pid5(unsigned int ucpbtx1_crr_pid5); +int iSetTX_CRR1_PID_cpbtx1_crr_pid6(unsigned int ucpbtx1_crr_pid6); +int iSetTX_CRR1_PID_cpbtx1_crr_pid7(unsigned int ucpbtx1_crr_pid7); +int iSetTX_CRR2_EN_cpbtx2_crr_vld(unsigned int ucpbtx2_crr_vld); +int iSetTX_CRR2_EN_cpbtx2_crr_len(unsigned int ucpbtx2_crr_len); +int iSetTX_CRR2_PID_cpbtx2_crr_pid0(unsigned int ucpbtx2_crr_pid0); +int iSetTX_CRR2_PID_cpbtx2_crr_pid1(unsigned int ucpbtx2_crr_pid1); +int iSetTX_CRR2_PID_cpbtx2_crr_pid2(unsigned int ucpbtx2_crr_pid2); +int iSetTX_CRR2_PID_cpbtx2_crr_pid3(unsigned int ucpbtx2_crr_pid3); +int iSetTX_CRR2_PID_cpbtx2_crr_pid4(unsigned int ucpbtx2_crr_pid4); +int iSetTX_CRR2_PID_cpbtx2_crr_pid5(unsigned int ucpbtx2_crr_pid5); +int iSetTX_CRR2_PID_cpbtx2_crr_pid6(unsigned int ucpbtx2_crr_pid6); +int iSetTX_CRR2_PID_cpbtx2_crr_pid7(unsigned int ucpbtx2_crr_pid7); +int iSetTX_CHN_CRDT_CFG0_tx_chn_crdt_0(unsigned int utx_chn_crdt_0); +int iSetTX_CHN_CRDT_CFG1_tx_chn_crdt_1(unsigned int utx_chn_crdt_1); +int iSetTX_CHN_CRDT_CFG2_tx_chn_crdt_2(unsigned int utx_chn_crdt_2); +int iSetTX_CHN_CRDT_CFG3_tx_chn_crdt_3(unsigned int utx_chn_crdt_3); +int iSetTX_CHN_CRDT_CFG4_tx_chn_crdt_4(unsigned int utx_chn_crdt_4); +int iSetTX_CHN_CRDT_CFG5_tx_chn_crdt_5(unsigned int utx_chn_crdt_5); +int iSetTX_CHN_CRDT_CFG6_tx_chn_crdt_6(unsigned int utx_chn_crdt_6); +int iSetTX_CHN_CRDT_CFG7_tx_chn_crdt_7(unsigned int utx_chn_crdt_7); +int iSetTX_CHN_CRDT_CFG8_tx_chn_crdt_8(unsigned int utx_chn_crdt_8); +int iSetTX_CHN_CRDT_CFG9_tx_chn_crdt_9(unsigned int utx_chn_crdt_9); +int iSetTX_CHN_CRDT_CFG10_tx_chn_crdt_10(unsigned int utx_chn_crdt_10); +int iSetCPB_TX_CRDT_CFG_petx_idx_crdt(unsigned int upetx_idx_crdt); +int iSetCPB_TX_CRDT_CFG_tx_dat_prealc_crdt(unsigned int utx_dat_prealc_crdt); +int iSetCPB_TX_CRDT_CFG_tx_crdt_bp_gap(unsigned int utx_crdt_bp_gap); +int iSetCPB_TX_CRDT_CFG_petx_idx_bp_gap(unsigned int upetx_idx_bp_gap); +int iSetTXLB_PD_FIFO_CFG_txlp_pd_fifo_ae_th(unsigned int utxlp_pd_fifo_ae_th); +int iSetTXLB_PD_FIFO_CFG_txlp_pd_fifo_af_th(unsigned int utxlp_pd_fifo_af_th); +int iSetTX_COS_FIFO_CFG_tx_cos_fifo_ae_th(unsigned int utx_cos_fifo_ae_th); +int iSetTX_COS_FIFO_CFG_tx_cos_fifo_af_th(unsigned int utx_cos_fifo_af_th); +int iSetFTSO_RLS_FIFO_CFG_ftso_rls_fifo_ae_th(unsigned int uftso_rls_fifo_ae_th); +int iSetFTSO_RLS_FIFO_CFG_ftso_rls_fifo_af_th(unsigned int uftso_rls_fifo_af_th); +int iSetTX_IDX_WT_cpt_idx_req_wt0(unsigned int ucpt_idx_req_wt0); +int iSetTX_IDX_WT_cpt_idx_req_wt1(unsigned int ucpt_idx_req_wt1); +int iSetTX_IDX_WT_cpt_idx_req_wt2(unsigned int ucpt_idx_req_wt2); +int iSetMAG_BP_EN_mag_cpb_bp_en(unsigned int umag_cpb_bp_en); +int iSetTX_TSO3_RLS_FIFO_CFG_tx_tso3_rls_fifo_ae_th(unsigned int utx_tso3_rls_fifo_ae_th); +int iSetTX_TSO3_RLS_FIFO_CFG_tx_tso3_rls_fifo_af_th(unsigned int utx_tso3_rls_fifo_af_th); +int iSetCIR_DAT_IN_FIFO_STA_cir_di_ctrl_fifo_sta(unsigned int ucir_di_ctrl_fifo_sta); +int iSetCIR_DAT_IN_FIFO_STA_cir_di_fifo_sta(unsigned int ucir_di_fifo_sta); +int iSetCIR_RPT_FIFO_STA_cir_alc_fifo_sta(unsigned int ucir_alc_fifo_sta); +int iSetCIR_RPT_FIFO_STA_cir_rpt_pci_sta(unsigned int ucir_rpt_pci_sta); +int iSetCIR_IN_PKT_SOP_CNT_cir_in_pkt_sop_cnt(unsigned int ucir_in_pkt_sop_cnt); +int iSetCIR_IN_PKT_EOP_CNT_cir_in_pkt_eop_cnt(unsigned int ucir_in_pkt_eop_cnt); +int iSetCIR_IN_PORT_PKT_CNT_cir_in_port_pkt_cnt(unsigned int ucir_in_port_pkt_cnt); +int iSetCIR_DRP_PKT_CNT_cir_drp_pkt_cnt(unsigned int ucir_drp_pkt_cnt); +int iSetCIR_FIFO_AF_DRP_PKT_CNT_cir_fifo_af_drp_pkt_cnt(unsigned int ucir_fifo_af_drp_pkt_cnt); +int iSetCIR_BMU_AF_DRP_PKT_CNT_cir_bmu_af_drp_pkt_cnt(unsigned int ucir_bmu_af_drp_pkt_cnt); +int iSetCIR_FIFO_AF_CNT_cir_fifo_af_cnt(unsigned int ucir_fifo_af_cnt); +int iSetCIR_CUT_PKT_CNT_cir_cut_pkt_cnt(unsigned int ucir_cut_pkt_cnt); +int iSetCIR_RPT_IQ_CNT_cir_rpt_iq_cnt(unsigned int ucir_rpt_iq_cnt); +int iSetCIR_IQ_BP_CNT_cir_iq_bp_cnt(unsigned int ucir_iq_bp_cnt); +int iSetCIR_SPORT_ERR_cir_sport_err(unsigned int ucir_sport_err); +int iSetCIR_ALC_PRM_CNUM_FULL_ERR_cir_alc_prm_cnum_full_err(unsigned int ucir_alc_prm_cnum_full_err); +int iSetCIR_FIFO_ERR_cir_di_fifo_uf(unsigned int ucir_di_fifo_uf); +int iSetCIR_FIFO_ERR_cir_di_ctrl_fifo_uf(unsigned int ucir_di_ctrl_fifo_uf); +int iSetCIR_FIFO_ERR_cir_rpt_pci_uf(unsigned int ucir_rpt_pci_uf); +int iSetCIR_FIFO_ERR_cir_alc_fifo_uf(unsigned int ucir_alc_fifo_uf); +int iSetCIR_FIFO_ERR_cir_di_fifo_ov(unsigned int ucir_di_fifo_ov); +int iSetCIR_FIFO_ERR_cir_di_ctrl_fifo_ov(unsigned int ucir_di_ctrl_fifo_ov); +int iSetCIR_FIFO_ERR_cir_rpt_pci_ov(unsigned int ucir_rpt_pci_ov); +int iSetCIR_FIFO_ERR_cir_alc_fifo_ov(unsigned int ucir_alc_fifo_ov); +int iSetCIR_FIFO_RAM_ERR_cir_fifo_mem_err_addr(unsigned int ucir_fifo_mem_err_addr); +int iSetCIR_FIFO_RAM_ERR_cir_fifo_mem_err_cerr(unsigned int ucir_fifo_mem_err_cerr); +int iSetCIR_FIFO_RAM_ERR_cir_fifo_mem_err_ucerr(unsigned int ucir_fifo_mem_err_ucerr); +int iSetCIR_FIFO_RAM_ERR_cir_fifo_mem_err_cnt(unsigned int ucir_fifo_mem_err_cnt); +int iSetCIR_PRM_BP_HIS_0_cir_prm_bp_his_0(unsigned int ucir_prm_bp_his_0); +int iSetCIR_PRM_BP_HIS_1_cir_prm_bp_his_1(unsigned int ucir_prm_bp_his_1); +int iSetCIR_PRM_BP_HIS_2_cir_prm_bp_his_2(unsigned int ucir_prm_bp_his_2); +int iSetCIR_PRM_BP_HIS_3_cir_prm_bp_his_3(unsigned int ucir_prm_bp_his_3); +int iSetCIR_PRM_BP_HIS_4_cir_prm_bp_his_4(unsigned int ucir_prm_bp_his_4); +int iSetCPT_PRO_DAT_IN_FIFO_STA_cpt_pro_di_fifo_sta(unsigned int ucpt_pro_di_fifo_sta); +int iSetCPT_PRO_DAT_IN_FIFO_STA_cpt_pro_prls_fifo_sta(unsigned int ucpt_pro_prls_fifo_sta); +int iSetCPT_PRO_DEALC_FIFO_STA_cpt_pro_dealc_rx_fifo_sta(unsigned int ucpt_pro_dealc_rx_fifo_sta); +int iSetCPT_PRO_DEALC_FIFO_STA_cpt_pro_dealc_tx_fifo_sta(unsigned int ucpt_pro_dealc_tx_fifo_sta); +int iSetCPT_DEALC_FIFO_STA_cpt_dealc_rx_fifo_sta(unsigned int ucpt_dealc_rx_fifo_sta); +int iSetCPT_DEALC_FIFO_STA_cpt_dealc_tx_fifo_sta(unsigned int ucpt_dealc_tx_fifo_sta); +int iSetCPT_PRLS_FIFO_STA_cpt_prls_fifo_sta(unsigned int ucpt_prls_fifo_sta); +int iSetCPT_DAT_OUT_FIFO_STA_cpt_dat_out_fifo_sta(unsigned int ucpt_dat_out_fifo_sta); +int iSetCPT_OUT_PKT_SOP_CNT_cpt_out_pkt_sop_cnt(unsigned int ucpt_out_pkt_sop_cnt); +int iSetCPT_OUT_PKT_EOP_CNT_cpt_out_pkt_eop_cnt(unsigned int ucpt_out_pkt_eop_cnt); +int iSetCPT_OUT_CHNL_PKT_CNT_cpt_out_chnl_pkt_cnt(unsigned int ucpt_out_chnl_pkt_cnt); +int iSetCPT_SOF_MSM_cpt_sof_msm_info(unsigned int ucpt_sof_msm_info); +int iSetCPT_SOF_MSM_cpt_sof_msm(unsigned int ucpt_sof_msm); +int iSetCPT_EOF_MSM_cpt_eof_msm_info(unsigned int ucpt_eof_msm_info); +int iSetCPT_EOF_MSM_cpt_eof_msm(unsigned int ucpt_eof_msm); +int iSetCPT_DEALC_TX_BP_TM_cpt_dealc_tx_bp_tm(unsigned int ucpt_dealc_tx_bp_tm); +int iSetCPT_DEALC_RX_BP_TM_cpt_dealc_rx_bp_tm(unsigned int ucpt_dealc_rx_bp_tm); +int iSetCPT_TS_CFG_ERR_cpt_ts_cfg_err(unsigned int ucpt_ts_cfg_err); +int iSetCPT_FIFO_OV_ERR_cpt_pro_di_fifo_ov(unsigned int ucpt_pro_di_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_pro_dealc_tx_fifo_ov(unsigned int ucpt_pro_dealc_tx_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_pro_dealc_rx_fifo_ov(unsigned int ucpt_pro_dealc_rx_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_dat_out_fifo_ov(unsigned int ucpt_dat_out_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_dealc_tx_fifo_ov(unsigned int ucpt_dealc_tx_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_dealc_rx_fifo_ov(unsigned int ucpt_dealc_rx_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_prls_fifo_ov(unsigned int ucpt_prls_fifo_ov); +int iSetCPT_FIFO_OV_ERR_cpt_pro_prls_fifo_ov(unsigned int ucpt_pro_prls_fifo_ov); +int iSetCPT_FIFO_UF_ERR_cpt_pro_di_fifo_uf(unsigned int ucpt_pro_di_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_pro_dealc_tx_fifo_uf(unsigned int ucpt_pro_dealc_tx_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_pro_dealc_rx_fifo_uf(unsigned int ucpt_pro_dealc_rx_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_dat_out_fifo_uf(unsigned int ucpt_dat_out_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_dealc_tx_fifo_uf(unsigned int ucpt_dealc_tx_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_dealc_rx_fifo_uf(unsigned int ucpt_dealc_rx_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_prls_fifo_uf(unsigned int ucpt_prls_fifo_uf); +int iSetCPT_FIFO_UF_ERR_cpt_pro_prls_fifo_uf(unsigned int ucpt_pro_prls_fifo_uf); +int iSetCPT_FIFO_RAM_ERR_cpt_fifo_mem_err_addr(unsigned int ucpt_fifo_mem_err_addr); +int iSetCPT_FIFO_RAM_ERR_cpt_fifo_mem_err_cerr(unsigned int ucpt_fifo_mem_err_cerr); +int iSetCPT_FIFO_RAM_ERR_cpt_fifo_mem_err_ucerr(unsigned int ucpt_fifo_mem_err_ucerr); +int iSetCPT_FIFO_RAM_ERR_cpt_fifo_mem_err_cnt(unsigned int ucpt_fifo_mem_err_cnt); +int iSetTX_CHN_CRDT_STA_tx_chn_crdt_cnt(unsigned int utx_chn_crdt_cnt); +int iSetTX_CHN_CRDT_STA_tx_chn_crdt_af(unsigned int utx_chn_crdt_af); +int iSetTX_IDX_CRDT_STA_tx_idx_crdt_cnt(unsigned int utx_idx_crdt_cnt); +int iSetTX_IDX_CRDT_STA_tx_idx_crdt_af(unsigned int utx_idx_crdt_af); +int iSetTX_FP_BMP_STA_tx_fp_bmp_fill(unsigned int utx_fp_bmp_fill); +int iSetTXPD_FIFO_EMPTY_STA_0_txpd_fifo_empty_sta_0(unsigned int utxpd_fifo_empty_sta_0); +int iSetTXPD_FIFO_EMPTY_STA_1_txpd_fifo_empty_sta_1(unsigned int utxpd_fifo_empty_sta_1); +int iSetTXPD_FIFO_EMPTY_STA_2_txpd_fifo_empty_sta_2(unsigned int utxpd_fifo_empty_sta_2); +int iSetTXPD_FIFO_FILL_STA_txpd_fifo_fill_sta(unsigned int utxpd_fifo_fill_sta); +int iSetTXPD_PRO_FSM_STA_txpd_pro_fsm_sta(unsigned int utxpd_pro_fsm_sta); +int iSetMAG_BP_STA_0_mag_cpb_bp_sta_0(unsigned int umag_cpb_bp_sta_0); +int iSetMAG_BP_STA_1_mag_cpb_bp_sta_1(unsigned int umag_cpb_bp_sta_1); +int iSetTX_FTSO_RLS_FIFO_STA_tx_ftsorls_fifo_sta_0(unsigned int utx_ftsorls_fifo_sta_0); +int iSetTX_FTSO_RLS_FIFO_STA_tx_ftsorls_fifo_sta_1(unsigned int utx_ftsorls_fifo_sta_1); +int iSetTX_TSO3_RLS_FIFO_STA_tx_tso3_rls_fifo_sta(unsigned int utx_tso3_rls_fifo_sta); +int iSetTX_CRDT_OF_ERR_tx_idx_crdt_of_err(unsigned int utx_idx_crdt_of_err); +int iSetTX_CRDT_OF_ERR_tx_chn_crdt_of_err(unsigned int utx_chn_crdt_of_err); +int iSetTX_CRDT_UF_ERR_tx_idx_crdt_uf_err(unsigned int utx_idx_crdt_uf_err); +int iSetTX_CRDT_UF_ERR_tx_chn_crdt_uf_err(unsigned int utx_chn_crdt_uf_err); +int iSetTXPD_FIFO_OF_ERR_0_txpd_fifo_of_err_0(unsigned int utxpd_fifo_of_err_0); +int iSetTXPD_FIFO_OF_ERR_1_txpd_fifo_of_err_1(unsigned int utxpd_fifo_of_err_1); +int iSetTXPD_FIFO_OF_ERR_2_txpd_fifo_of_err_2(unsigned int utxpd_fifo_of_err_2); +int iSetTXPD_FIFO_OF_ERR_2_tx_fp_fifo_of_err(unsigned int utx_fp_fifo_of_err); +int iSetTXPD_FIFO_OF_ERR_2_tx_tso3_rls_fifo_of_err(unsigned int utx_tso3_rls_fifo_of_err); +int iSetTXPD_FIFO_UF_ERR_0_txpd_fifo_uf_err_0(unsigned int utxpd_fifo_uf_err_0); +int iSetTXPD_FIFO_UF_ERR_1_txpd_fifo_uf_err_1(unsigned int utxpd_fifo_uf_err_1); +int iSetTXPD_FIFO_UF_ERR_2_txpd_fifo_uf_err_2(unsigned int utxpd_fifo_uf_err_2); +int iSetTXPD_FIFO_UF_ERR_2_tx_fp_fifo_uf_err(unsigned int utx_fp_fifo_uf_err); +int iSetTXPD_FIFO_UF_ERR_2_tx_tso3_rls_fifo_uf_err(unsigned int utx_tso3_rls_fifo_uf_err); +int iSetTX_FTSO_RLS_FIFO_ERR_tx_ftso_rls_fifo_uf_err(unsigned int utx_ftso_rls_fifo_uf_err); +int iSetTX_FTSO_RLS_FIFO_ERR_tx_ftso_rls_fifo_of_err(unsigned int utx_ftso_rls_fifo_of_err); +int iSetTSO_RAM_ERR_tso_mem_err_addr(unsigned int utso_mem_err_addr); +int iSetTSO_RAM_ERR_tso_mem_err_cerr(unsigned int utso_mem_err_cerr); +int iSetTSO_RAM_ERR_tso_mem_err_ucerr(unsigned int utso_mem_err_ucerr); +int iSetTSO_RAM_ERR_tso_mem_err_cnt(unsigned int utso_mem_err_cnt); +int iSetTX_PD_RAM_ERR_tx_pd_mem_err_addr(unsigned int utx_pd_mem_err_addr); +int iSetTX_PD_RAM_ERR_tx_pd_mem_err_cerr(unsigned int utx_pd_mem_err_cerr); +int iSetTX_PD_RAM_ERR_tx_pd_mem_err_ucerr(unsigned int utx_pd_mem_err_ucerr); +int iSetTX_PD_RAM_ERR_tx_pd_mem_err_cnt(unsigned int utx_pd_mem_err_cnt); +int iSetCPB_TX_ERR_0_tx_chn_pd_pptr_err(unsigned int utx_chn_pd_pptr_err); +int iSetCPB_TX_ERR_1_tx_chn_pd_pktmod_err(unsigned int utx_chn_pd_pktmod_err); +int iSetCPB_TX_ERR_2_tx_chn_ret_pcnum_err(unsigned int utx_chn_ret_pcnum_err); +int iSetCPB_TX_ERR_3_tx_chn_tso1_num_err(unsigned int utx_chn_tso1_num_err); +int iSetCPB_TX_ERR_3_tx_chn_tso1_cmd_cnum_err(unsigned int utx_chn_tso1_cmd_cnum_err); +int iSetCPB_TX_ERR_4_tx_chn_tso2_num_err(unsigned int utx_chn_tso2_num_err); +int iSetCPB_TX_ERR_4_tx_chn_tso2_cmd_cnum_err(unsigned int utx_chn_tso2_cmd_cnum_err); +int iSetCPB_TX_ERR_4_tx_chn_tso2_cmd_cnum_err0(unsigned int utx_chn_tso2_cmd_cnum_err0); +int iSetCPB_TX_ERR_4_tx_chn_tso2_cmd_cnum_err1(unsigned int utx_chn_tso2_cmd_cnum_err1); +int iSetCPB_TX_ERR_4_tx_chn_tso2_cmd_cnum_err2(unsigned int utx_chn_tso2_cmd_cnum_err2); +int iSetCPB_TX_ERR_5_tx_chn_lro2_num_err(unsigned int utx_chn_lro2_num_err); +int iSetCPB_TX_ERR_5_tx_chn_lro2_cmd_cnum_err(unsigned int utx_chn_lro2_cmd_cnum_err); +int iSetCPB_TX_ERR_5_tx_chn_lro2_cmd_cnum_err0(unsigned int utx_chn_lro2_cmd_cnum_err0); +int iSetCPB_TX_ERR_5_tx_chn_lro2_cmd_cnum_err1(unsigned int utx_chn_lro2_cmd_cnum_err1); +int iSetCPB_TX_ERR_5_tx_chn_lro2_cmd_cnum_err2(unsigned int utx_chn_lro2_cmd_cnum_err2); + +#endif // CPB_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_reg_offset.h new file mode 100644 index 000000000..e45d6eb4e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpb_reg_offset.h @@ -0,0 +1,1157 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cpb_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2020/3 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2020/03/24 21:10:00 Create file +// ****************************************************************************** + +#ifndef CPB_REG_OFFSET_H +#define CPB_REG_OFFSET_H + +/* CPB_CSR_0 Base address of Module's Register */ +#define CSR_CPB_CSR_0_BASE (0x2000) + +/* **************************************************************************** */ +/* CPB_CSR_0 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPB_CSR_CPB_FPGA_VER_REG (CSR_CPB_CSR_0_BASE + 0x0) /* CPB FPGA版本寄存器 */ +#define CSR_CPB_CSR_CPB_EMU_VER_REG (CSR_CPB_CSR_0_BASE + 0x4) /* CPB EMU版本寄存器 */ +#define CSR_CPB_CSR_CPB_BANK_ROW_EN_REG (CSR_CPB_CSR_0_BASE + 0xC) /* CPB BANK的各个ROW使能配置 */ +#define CSR_CPB_CSR_CPB_DAT_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x10) /* CPB DAT MEM初始化配置寄存器 */ +#define CSR_CPB_CSR_CPB_CD_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x14) /* CPB CD MEM初始化配置寄存器 */ +#define CSR_CPB_CSR_CPB_NPTR_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x18) /* CPB NPTR MEM初始化配置寄存器 */ +#define CSR_CPB_CSR_CPB_TI_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x1C) /* CPB TI MEM初始化配置寄存器 */ +#define CSR_CPB_CSR_CPB_DAT_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x20) /* CPB DAT MEM初始化完成状态寄存器 */ +#define CSR_CPB_CSR_CPB_CD_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x24) /* CPB CD MEM初始化完成状态寄存器 */ +#define CSR_CPB_CSR_CPB_NPTR_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x28) /* CPB NPTR MEM初始化完成状态寄存器 */ +#define CSR_CPB_CSR_CPB_TI_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x2C) /* CPB TI MEM初始化完成状态寄存器 */ +#define CSR_CPB_CSR_CPB_BMP_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x30) /* CPB Bitmap初始化配置寄存器 */ +#define CSR_CPB_CSR_CPB_BMP_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x34) /* CPB Bitmap初始化完成状态寄存器 */ +#define CSR_CPB_CSR_CPB_INIT_START_REG (CSR_CPB_CSR_0_BASE + 0x38) /* 配置表初始化使能寄存器 */ +#define CSR_CPB_CSR_CPB_INIT_DONE_REG (CSR_CPB_CSR_0_BASE + 0x3C) /* 配置表初始化状态寄存器 */ +#define CSR_CPB_CSR_CPB_INT_VECTOR_REG (CSR_CPB_CSR_0_BASE + 0x40) /* 中断向量寄存器 */ +#define CSR_CPB_CSR_CPB_INT_REG (CSR_CPB_CSR_0_BASE + 0x44) /* 中断状态寄存器 */ +#define CSR_CPB_CSR_CPB_INT_EN_REG (CSR_CPB_CSR_0_BASE + 0x48) /* 中断使能寄存器 */ +#define CSR_CPB_CSR_CPB_RAM_UCERR_REG (CSR_CPB_CSR_0_BASE + 0x4C) /* CPB RAM ECC不可纠错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_RAM_CERR_REG (CSR_CPB_CSR_0_BASE + 0x50) /* CPB RAM ECC可纠错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_FIFO_OF_ERR_REG (CSR_CPB_CSR_0_BASE + 0x54) /* CPB FIFO出现Overflow错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_FIFO_UF_ERR_REG (CSR_CPB_CSR_0_BASE + 0x58) /* CPB FIFO出现Underflow错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_RX_CRDT_ERR_REG (CSR_CPB_CSR_0_BASE + 0x5C) /* CPB RX方向Credit错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_TX_CRDT_ERR_REG (CSR_CPB_CSR_0_BASE + 0x60) /* CPB TX方向Credit错误中断寄存器 */ +#define CSR_CPB_CSR_TX_PREALC_CRDT_ERR_REG (CSR_CPB_CSR_0_BASE + 0x64) /* TX方向Cell预扣不足错误中断寄存器 */ +#define CSR_CPB_CSR_CPB_BP_DROP_ERR_REG (CSR_CPB_CSR_0_BASE + 0x68) /* CPB因反压丢包错误中断寄存器 */ +#define CSR_CPB_CSR_CIR_CIT_ABN_ERR_REG (CSR_CPB_CSR_0_BASE + 0x6C) /* CPB IPSURX/IPSUTX接口模块异常中断寄存器 */ +#define CSR_CPB_CSR_CPR_CPT_ABN_ERR_REG (CSR_CPB_CSR_0_BASE + 0x70) /* CPB PERX/PETX接口模块异常中断寄存器 */ +#define CSR_CPB_CSR_CT_ABN_ERR_REG (CSR_CPB_CSR_0_BASE + 0x74) /* CPB STL/STF Tile接口模块异常中断寄存器 */ +#define CSR_CPB_CSR_CQ_ABN_ERR_REG (CSR_CPB_CSR_0_BASE + 0x78) /* CPB QU IQ/OQ接口模块异常中断寄存器 */ +#define CSR_CPB_CSR_RX_TX_ABN_ERR_REG (CSR_CPB_CSR_0_BASE + 0x7C) /* CPB RX/TX处理模块异常中断寄存器 */ +#define CSR_CPB_CSR_CPB_BMU_RSC_ERR_REG (CSR_CPB_CSR_0_BASE + 0x80) /* CPB BMU Cell资源异常中断寄存器 */ +#define CSR_CPB_CSR_CPB_AGING_ERR_REG (CSR_CPB_CSR_0_BASE + 0x84) /* CPB发现有Cell被老化的异常中断寄存器 */ +#define CSR_CPB_CSR_CPB_FATAL_ERR_EN_REG (CSR_CPB_CSR_0_BASE + 0x90) /* CPB产生Fatal Err指示的使能配置 */ +#define CSR_CPB_CSR_CPB_FATAL_ERR_STA_REG (CSR_CPB_CSR_0_BASE + 0x94) /* CPB的Fatal Err的状态指示及清除寄存器 */ +#define CSR_CPB_CSR_CPB_ITF_BP_STA_REG (CSR_CPB_CSR_0_BASE + 0xA0) /* CPB周边接口反压状态指示寄存器 */ +#define CSR_CPB_CSR_CPB_ITF_BP_HIS_REG (CSR_CPB_CSR_0_BASE + 0xA4) /* CPB周边接口反压历史状态寄存器 */ +#define CSR_CPB_CSR_CPB_API_ERR_REG (CSR_CPB_CSR_0_BASE + 0xD0) /* CPB中API异常的汇聚，包含TL_REQ_INVLD、TL_STR_ERR */ +#define CSR_CPB_CSR_CPB_FIFO_ERR_COL_REG (CSR_CPB_CSR_0_BASE + 0xD4) /* CPB中各模块FIFO溢出汇聚寄存器 */ +#define CSR_CPB_CSR_TL_REQ_INVLD_REG (CSR_CPB_CSR_0_BASE + 0xD8) /* Tile下发API或IQ的push请求非法 */ +#define CSR_CPB_CSR_TL_STR_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0xDC) /* Tile下发的streamout API填充错误 */ +#define CSR_CPB_CSR_TL_STR_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0xE0) /* Tile下发的streamout API填充错误 */ +#define CSR_CPB_CSR_TL_STR_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0xE4) /* Tile下发的streamout API填充错误 */ +#define CSR_CPB_CSR_CPB_RAM_CTRL_BUS_0_REG (CSR_CPB_CSR_0_BASE + 0x100) /* CPB RAM CTRL控制寄存器0 */ +#define CSR_CPB_CSR_CPB_RAM_CTRL_BUS_1_REG (CSR_CPB_CSR_0_BASE + 0x104) /* CPB RAM CTRL控制寄存器1 */ +#define CSR_CPB_CSR_CPB_RAM_CTRL_BUS_2_REG (CSR_CPB_CSR_0_BASE + 0x108) /* CPB RAM CTRL控制寄存器2 */ +#define CSR_CPB_CSR_CPB_RAM_CTRL_BUS_3_REG (CSR_CPB_CSR_0_BASE + 0x10C) /* CPB RAM CTRL控制寄存器3 */ +#define CSR_CPB_CSR_CPB_RAM_CTRL_BUS_4_REG (CSR_CPB_CSR_0_BASE + 0x110) /* CPB RAM CTRL控制寄存器4 */ +#define CSR_CPB_CSR_CPB_RAM_ECC_BYPASS_REG (CSR_CPB_CSR_0_BASE + 0x114) /* CPB RAM ECC单bit纠错Bypass配置寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_CTRL_REG (CSR_CPB_CSR_0_BASE + 0x170) /* 间接访问控制寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_TO_TH_REG (CSR_CPB_CSR_0_BASE + 0x174) /* 间接访问Timeout配置寄存器 */ +#define CSR_CPB_CSR_BANK_WEAK_CFG_REG (CSR_CPB_CSR_0_BASE + 0x200) /* BMU Bank Weak配置寄存器 */ +#define CSR_CPB_CSR_BMU_ALT_BP_CFG_REG (CSR_CPB_CSR_0_BASE + 0x204) /* BMU告警反压配置寄存器 */ +#define CSR_CPB_CSR_BMU_FAT_BP_CFG_REG (CSR_CPB_CSR_0_BASE + 0x208) /* BMU致命反压配置寄存器 */ +#define CSR_CPB_CSR_BMU_AP_ACC_WT0_REG (CSR_CPB_CSR_0_BASE + 0x210) /* BMU指定地址访问端口的权重配置 */ +#define CSR_CPB_CSR_BMU_AP_ACC_WT1_REG (CSR_CPB_CSR_0_BASE + 0x214) /* BMU指定地址访问端口的权重配置 */ +#define CSR_CPB_CSR_TI_ACC_TO_TH_REG (CSR_CPB_CSR_0_BASE + 0x218) /* TI Mem非主Mem访问超时时间配置 */ +#define CSR_CPB_CSR_BMP_AM_TH_REG (CSR_CPB_CSR_0_BASE + 0x220) /* 每个ROW的Bitmap 快空门限配置 */ +#define CSR_CPB_CSR_BK_EXHT_TH_REG (CSR_CPB_CSR_0_BASE + 0x224) /* 每个BANK的Cell地址快耗完的门限配置 */ +#define CSR_CPB_CSR_CELL_RD_RLS_EN_REG (CSR_CPB_CSR_0_BASE + 0x228) /* Cell读释放使能配置 */ +#define CSR_CPB_CSR_CPB_AGE_CFG_REG (CSR_CPB_CSR_0_BASE + 0x258) /* CPB Cell老化公共配置寄存器 */ +#define CSR_CPB_CSR_CPB_AGE_TO_TH_REG (CSR_CPB_CSR_0_BASE + 0x25C) /* CPB Cell老化时间配置 */ +#define CSR_CPB_CSR_BK_AGE_CFG_0_REG (CSR_CPB_CSR_0_BASE + 0x260) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_1_REG (CSR_CPB_CSR_0_BASE + 0x264) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_2_REG (CSR_CPB_CSR_0_BASE + 0x268) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_3_REG (CSR_CPB_CSR_0_BASE + 0x26C) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_4_REG (CSR_CPB_CSR_0_BASE + 0x270) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_5_REG (CSR_CPB_CSR_0_BASE + 0x274) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_6_REG (CSR_CPB_CSR_0_BASE + 0x278) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_CFG_7_REG (CSR_CPB_CSR_0_BASE + 0x27C) /* CPB每个Bank Cell老化配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_0_REG (CSR_CPB_CSR_0_BASE + 0x280) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_1_REG (CSR_CPB_CSR_0_BASE + 0x284) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_2_REG (CSR_CPB_CSR_0_BASE + 0x288) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_3_REG (CSR_CPB_CSR_0_BASE + 0x28C) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_4_REG (CSR_CPB_CSR_0_BASE + 0x290) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_5_REG (CSR_CPB_CSR_0_BASE + 0x294) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_6_REG (CSR_CPB_CSR_0_BASE + 0x298) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_BMP_LINE_7_REG (CSR_CPB_CSR_0_BASE + 0x29C) /* 每个Bank老化的Bitmap Line */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_0_REG (CSR_CPB_CSR_0_BASE + 0x2A0) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_1_REG (CSR_CPB_CSR_0_BASE + 0x2A4) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_2_REG (CSR_CPB_CSR_0_BASE + 0x2A8) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_3_REG (CSR_CPB_CSR_0_BASE + 0x2AC) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_4_REG (CSR_CPB_CSR_0_BASE + 0x2B0) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_5_REG (CSR_CPB_CSR_0_BASE + 0x2B4) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_6_REG (CSR_CPB_CSR_0_BASE + 0x2B8) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_RLS_CFG_7_REG (CSR_CPB_CSR_0_BASE + 0x2BC) /* 每个Bank老化软件释放配置寄存器 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_0_REG (CSR_CPB_CSR_0_BASE + 0x2C0) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_1_REG (CSR_CPB_CSR_0_BASE + 0x2C4) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_2_REG (CSR_CPB_CSR_0_BASE + 0x2C8) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_3_REG (CSR_CPB_CSR_0_BASE + 0x2CC) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_4_REG (CSR_CPB_CSR_0_BASE + 0x2D0) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_5_REG (CSR_CPB_CSR_0_BASE + 0x2D4) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_6_REG (CSR_CPB_CSR_0_BASE + 0x2D8) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_AGE_FIND_NXT_7_REG (CSR_CPB_CSR_0_BASE + 0x2DC) /* 每个Bank查找下个老化Cell的配置 */ +#define CSR_CPB_CSR_BK_FREE_RSC_CNT0_REG (CSR_CPB_CSR_0_BASE + 0x300) /* BMU每个Bank当前可用地址数量指示 */ +#define CSR_CPB_CSR_BK_FREE_RSC_CNT1_REG (CSR_CPB_CSR_0_BASE + 0x304) /* BMU每个Bank当前可用地址数量指示 */ +#define CSR_CPB_CSR_BK_FREE_RSC_CNT2_REG (CSR_CPB_CSR_0_BASE + 0x308) /* BMU每个Bank当前可用地址数量指示 */ +#define CSR_CPB_CSR_BK_FREE_RSC_CNT3_REG (CSR_CPB_CSR_0_BASE + 0x30C) /* BMU每个Bank当前可用地址数量指示 */ +#define CSR_CPB_CSR_BK_MIN_RSC_HIS_CNT0_REG (CSR_CPB_CSR_0_BASE + 0x310) /* BMU每个Bank最小可用地址数量历史记录 */ +#define CSR_CPB_CSR_BK_MIN_RSC_HIS_CNT1_REG (CSR_CPB_CSR_0_BASE + 0x314) /* BMU每个Bank最小可用地址数量历史记录 */ +#define CSR_CPB_CSR_BK_MIN_RSC_HIS_CNT2_REG (CSR_CPB_CSR_0_BASE + 0x318) /* BMU每个Bank最小可用地址数量历史记录 */ +#define CSR_CPB_CSR_BK_MIN_RSC_HIS_CNT3_REG (CSR_CPB_CSR_0_BASE + 0x31C) /* BMU每个Bank最小可用地址数量历史记录 */ +#define CSR_CPB_CSR_CPB_MIN_RSC_HIS_CNT_REG (CSR_CPB_CSR_0_BASE + 0x320) /* CPB剩余最小资源的历史记录 */ +#define CSR_CPB_CSR_BMU_RSC_HIS_CNT_CLR_REG (CSR_CPB_CSR_0_BASE + 0x324) /* CPB BMU的资源历史记录清除配置 */ +#define CSR_CPB_CSR_BMU_BP_STA_REG (CSR_CPB_CSR_0_BASE + 0x328) /* CPB BMU的反压状态指示寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_0_REG (CSR_CPB_CSR_0_BASE + 0x330) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_1_REG (CSR_CPB_CSR_0_BASE + 0x334) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_2_REG (CSR_CPB_CSR_0_BASE + 0x338) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_3_REG (CSR_CPB_CSR_0_BASE + 0x33C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_4_REG (CSR_CPB_CSR_0_BASE + 0x340) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_5_REG (CSR_CPB_CSR_0_BASE + 0x344) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_6_REG (CSR_CPB_CSR_0_BASE + 0x348) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_7_REG (CSR_CPB_CSR_0_BASE + 0x34C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_8_REG (CSR_CPB_CSR_0_BASE + 0x350) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_9_REG (CSR_CPB_CSR_0_BASE + 0x354) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_10_REG (CSR_CPB_CSR_0_BASE + 0x358) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_11_REG (CSR_CPB_CSR_0_BASE + 0x35C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_12_REG (CSR_CPB_CSR_0_BASE + 0x360) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_13_REG (CSR_CPB_CSR_0_BASE + 0x364) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_14_REG (CSR_CPB_CSR_0_BASE + 0x368) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_15_REG (CSR_CPB_CSR_0_BASE + 0x36C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_16_REG (CSR_CPB_CSR_0_BASE + 0x370) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_17_REG (CSR_CPB_CSR_0_BASE + 0x374) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_18_REG (CSR_CPB_CSR_0_BASE + 0x378) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_19_REG (CSR_CPB_CSR_0_BASE + 0x37C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_20_REG (CSR_CPB_CSR_0_BASE + 0x380) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_21_REG (CSR_CPB_CSR_0_BASE + 0x384) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_22_REG (CSR_CPB_CSR_0_BASE + 0x388) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_23_REG (CSR_CPB_CSR_0_BASE + 0x38C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_24_REG (CSR_CPB_CSR_0_BASE + 0x390) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_25_REG (CSR_CPB_CSR_0_BASE + 0x394) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_26_REG (CSR_CPB_CSR_0_BASE + 0x398) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_27_REG (CSR_CPB_CSR_0_BASE + 0x39C) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_28_REG (CSR_CPB_CSR_0_BASE + 0x3A0) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_29_REG (CSR_CPB_CSR_0_BASE + 0x3A4) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_30_REG (CSR_CPB_CSR_0_BASE + 0x3A8) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_ROW_BMP_STA_31_REG (CSR_CPB_CSR_0_BASE + 0x3AC) /* BMU每个ROW的bitmap的状态寄存器 */ +#define CSR_CPB_CSR_AGE_RLS_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x3B0) /* BMU每个BNAK老化地址释放统计 */ +#define CSR_CPB_CSR_AGE_RLS_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x3B4) /* BMU每个BNAK老化地址释放统计 */ +#define CSR_CPB_CSR_AGE_RLS_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x3B8) /* BMU每个BNAK老化地址释放统计 */ +#define CSR_CPB_CSR_AGE_RLS_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x3BC) /* BMU每个BNAK老化地址释放统计 */ +#define CSR_CPB_CSR_STF_RSP_API_FIFO_CRDT_INIT_REG (CSR_CPB_CSR_0_BASE + 0x830) /* 内部存储reponse/push API实体的信用 \ + */ +#define CSR_CPB_CSR_STF_PSH_CMD_WT_REG (CSR_CPB_CSR_0_BASE + 0x834) +#define CSR_CPB_CSR_STF_COL_DEL_MD_HDR_EN_REG (CSR_CPB_CSR_0_BASE + 0x838) +#define CSR_CPB_CSR_STF_RD_REQ_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x83C) +#define CSR_CPB_CSR_STF_RD_CTRL_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x840) +#define CSR_CPB_CSR_CPB_STF_API_CRDT_INIT_REG (CSR_CPB_CSR_0_BASE + 0x844) +#define CSR_CPB_CSR_STF_STR_DI_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x848) +#define CSR_CPB_CSR_STF_STR_API_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x84C) +#define CSR_CPB_CSR_STF_CMD_API_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x850) +#define CSR_CPB_CSR_STF_ACKSTR_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x854) /* streamout ACK FQ FIFO的将满阈值 */ +#define CSR_CPB_CSR_STF_MSG_VFID_CTL_REG (CSR_CPB_CSR_0_BASE + 0x860) +#define CSR_CPB_CSR_CT_DMA_NRET_CFG_REG (CSR_CPB_CSR_0_BASE + 0x864) /* DMA normal return配置寄存器 */ +#define CSR_CPB_CSR_CT_COL_SRC_TAG_H_CFG_REG (CSR_CPB_CSR_0_BASE + 0x868) /* 聚合时src_tag_h步进控制寄存器 */ +#define CSR_CPB_CSR_CT_DEALC_FIFO_AF_TH_REG (CSR_CPB_CSR_0_BASE + 0x870) +#define CSR_CPB_CSR_STFIQ_PSH_FIFO_CFG_REG (CSR_CPB_CSR_0_BASE + 0x910) /* STF IQ Push请求FIFO配置 */ +#define CSR_CPB_CSR_STFIQ_LINK_FIFO_CFG_REG (CSR_CPB_CSR_0_BASE + 0x920) /* STF IQ Link请求FIFO配置 */ +#define CSR_CPB_CSR_LINK_WR_FIFO_CFG_REG (CSR_CPB_CSR_0_BASE + 0x924) /* Link WR请求FIFO配置 */ +#define CSR_CPB_CSR_STF_CMD_API_RD_REQ_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1500) /* statefull tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_CMD_API_RD_REQ_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1504) /* statefull tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_CMD_API_RD_REQ_FIFO_STA_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1508) /* statefull tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_CMD_API_RD_REQ_FIFO_STA_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x150C) /* statefull tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_STR_API_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1510) /* statefull tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_STR_API_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1514) /* statefull tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_STR_API_FIFO_STA_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1518) /* statefull tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_STR_API_FIFO_STA_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x151C) /* statefull tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_WR_RD_DAT_IN_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1520) /* statefull tile进行BMU读写的数据输入FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_WR_RD_DAT_IN_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1524) /* statefull tile进行BMU读写的数据输入FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_HDR_DAT_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1530) /* CPB发送给statefull tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_HDR_DAT_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1534) /* CPB发送给statefull tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_HDR_DAT_FIFO_STA_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1538) /* CPB发送给statefull tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_HDR_DAT_FIFO_STA_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x153C) /* CPB发送给statefull tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CD_CRC_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1540) /* CPB发送给statefull tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CD_CRC_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1544) /* CPB发送给statefull tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CD_CRC_FIFO_STA_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1548) /* CPB发送给statefull tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CD_CRC_FIFO_STA_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x154C) /* CPB发送给statefull tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CS_NPTR_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1550) /* CPB发送给statefull tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CS_NPTR_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1554) /* CPB发送给statefull tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CS_NPTR_FIFO_STA_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1558) /* CPB发送给statefull tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_RSP_API_CS_NPTR_FIFO_STA_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x155C) /* CPB发送给statefull tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_STR_CMD_CNT_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1560) /* statefull tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STF_STR_CMD_CNT_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1564) /* statefull tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STF_STR_CMD_CNT_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1568) /* statefull tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STF_STR_CMD_CNT_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x156C) /* statefull tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STF_ACK_RSP_CNT_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1570) /* CPB ACK statefull FQ及其statefull tile的次数统计 */ +#define CSR_CPB_CSR_STF_ACK_RSP_CNT_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1574) /* CPB ACK statefull FQ及其statefull tile的次数统计 */ +#define CSR_CPB_CSR_STF_ACK_RSP_CNT_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1578) /* CPB ACK statefull FQ及其statefull tile的次数统计 */ +#define CSR_CPB_CSR_STF_ACK_RSP_CNT_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x157C) /* CPB ACK statefull FQ及其statefull tile的次数统计 */ +#define CSR_CPB_CSR_STF_PSH_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x1580) /* statefull push请求次数统计 */ +#define CSR_CPB_CSR_STF_PSH_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x1584) /* statefull push请求次数统计 */ +#define CSR_CPB_CSR_STF_PSH_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x1588) /* statefull push请求次数统计 */ +#define CSR_CPB_CSR_STF_PSH_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x158C) /* statefull push请求次数统计 */ +#define CSR_CPB_CSR_STF_CELL_MDF_CNT_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x1590) /* statefull tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STF_CELL_MDF_CNT_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x1594) /* statefull tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STF_CELL_MDF_CNT_2_REG \ + (CSR_CPB_CSR_0_BASE + 0x1598) /* statefull tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STF_CELL_MDF_CNT_3_REG \ + (CSR_CPB_CSR_0_BASE + 0x159C) /* statefull tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STF_WR_DI_CTRL_FIFO_STA_0_REG \ + (CSR_CPB_CSR_0_BASE + 0x15A4) /* stateful tile进行BMU写的数据控制FIFO及其streamout ACK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_WR_DI_CTRL_FIFO_STA_1_REG \ + (CSR_CPB_CSR_0_BASE + 0x15A8) /* stateful tile进行BMU写的数据控制FIFO及其streamout ACK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_FIFO_OV_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x15B0) +#define CSR_CPB_CSR_STF_FIFO_OV_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x15B4) +#define CSR_CPB_CSR_STF_FIFO_UF_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x15B8) +#define CSR_CPB_CSR_STF_FIFO_UF_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x15BC) +#define CSR_CPB_CSR_CT_EXT_DEALC_FIFO_STA_REG \ + (CSR_CPB_CSR_0_BASE + 0x15C0) /* extend mode push时，extend cell释放FIFO状态寄存器 */ +#define CSR_CPB_CSR_STF_PCOL_NUM_ERR_REG \ + (CSR_CPB_CSR_0_BASE + 0x15C4) /* 弱聚合包数过多，导致发送给tile的src_tag_h错误 */ +#define CSR_CPB_CSR_STFWR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x15D8) /* STF WR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFWR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x15DC) /* STF WR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFSTR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x15E0) /* STF STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFSTR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x15E4) /* STF STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFSTR_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x15E8) /* STF STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFSTR_FIFO_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x15EC) /* STF STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFRSP_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x15F0) /* STF RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFRSP_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x15F4) /* STF RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFRSP_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x15F8) /* STF RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFRSP_FIFO_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x15FC) /* STF RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STFIQ_PKT_PSH_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x1620) /* STFIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_PKT_PSH_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x1624) /* STFIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_PKT_PSH_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x1628) /* STFIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_PKT_PSH_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x162C) /* STFIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_MSG_PSH_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x1630) /* STFIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_MSG_PSH_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x1634) /* STFIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_MSG_PSH_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x1638) /* STFIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_MSG_PSH_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x163C) /* STFIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STFIQ_COL_PSH_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x1640) /* STFIQ的聚合推送请求统计 */ +#define CSR_CPB_CSR_STFIQ_COL_PSH_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x1644) /* STFIQ的聚合推送请求统计 */ +#define CSR_CPB_CSR_STFIQ_COL_PSH_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x1648) /* STFIQ的聚合推送请求统计 */ +#define CSR_CPB_CSR_STFIQ_COL_PSH_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x164C) /* STFIQ的聚合推送请求统计 */ +#define CSR_CPB_CSR_STFIQ_LINK_REQ_CNT_0_REG (CSR_CPB_CSR_0_BASE + 0x1650) /* STFIQ的Link串链请求次数统计 */ +#define CSR_CPB_CSR_STFIQ_LINK_REQ_CNT_1_REG (CSR_CPB_CSR_0_BASE + 0x1654) /* STFIQ的Link串链请求次数统计 */ +#define CSR_CPB_CSR_STFIQ_LINK_REQ_CNT_2_REG (CSR_CPB_CSR_0_BASE + 0x1658) /* STFIQ的Link串链请求次数统计 */ +#define CSR_CPB_CSR_STFIQ_LINK_REQ_CNT_3_REG (CSR_CPB_CSR_0_BASE + 0x165C) /* STFIQ的Link串链请求次数统计 */ +#define CSR_CPB_CSR_STFIQ_PSH_FIFO_STA_0_REG (CSR_CPB_CSR_0_BASE + 0x1690) /* STFIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_PSH_FIFO_STA_1_REG (CSR_CPB_CSR_0_BASE + 0x1694) /* STFIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_PSH_FIFO_STA_2_REG (CSR_CPB_CSR_0_BASE + 0x1698) /* STFIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_PSH_FIFO_STA_3_REG (CSR_CPB_CSR_0_BASE + 0x169C) /* STFIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_LINK_FIFO_STA_0_REG (CSR_CPB_CSR_0_BASE + 0x16A0) /* STFIQ LINK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_LINK_FIFO_STA_1_REG (CSR_CPB_CSR_0_BASE + 0x16A4) /* STFIQ LINK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_LINK_FIFO_STA_2_REG (CSR_CPB_CSR_0_BASE + 0x16A8) /* STFIQ LINK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STFIQ_LINK_FIFO_STA_3_REG (CSR_CPB_CSR_0_BASE + 0x16AC) /* STFIQ LINK FIFO状态寄存器 */ +#define CSR_CPB_CSR_LINK_WR_FIFO_STA_REG (CSR_CPB_CSR_0_BASE + 0x16B0) /* LINK WR FIFO状态寄存器 */ +#define CSR_CPB_CSR_CIQ_FIFO_OF_ERR_REG (CSR_CPB_CSR_0_BASE + 0x16C0) /* CBP IQ接口模块FIFO Overflow状态记录 */ +#define CSR_CPB_CSR_CIQ_FIFO_UF_ERR_REG (CSR_CPB_CSR_0_BASE + 0x16C4) /* CBP IQ接口模块FIFO Underflow状态记录 */ +#define CSR_CPB_CSR_CIQ_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x16C8) /* CBP IQ接口模块RAM ECC ERR状态记录 */ +#define CSR_CPB_CSR_CIQ_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x16CC) /* CBP IQ接口模块RAM ECC ERR状态记录 */ +#define CSR_CPB_CSR_CIQ_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x16D0) /* CBP IQ接口模块RAM ECC ERR状态记录 */ +#define CSR_CPB_CSR_CIQ_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x16D4) /* CBP IQ接口模块RAM ECC ERR状态记录 */ +#define CSR_CPB_CSR_CIQ_ERR_REG (CSR_CPB_CSR_0_BASE + 0x16E0) /* CBP IQ接口模块错误状态记录 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1BA0) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1BA4) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1BA8) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1BAC) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1BB0) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1BB4) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1BB8) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_DAT_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1BBC) /* BMU DAT Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1BC0) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1BC4) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1BC8) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1BCC) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1BD0) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1BD4) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1BD8) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CD_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1BDC) /* BMU CD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1BE0) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1BE4) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1BE8) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1BEC) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1BF0) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1BF4) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1BF8) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_NPTR_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1BFC) /* BMU NPTR Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1C00) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1C04) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1C08) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1C0C) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1C10) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1C14) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1C18) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TI_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1C1C) /* BMU TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1C20) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1C24) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1C28) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1C2C) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1C30) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1C34) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1C38) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_BMP_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1C3C) /* BMP TI Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_0_REG (CSR_CPB_CSR_0_BASE + 0x1C40) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_1_REG (CSR_CPB_CSR_0_BASE + 0x1C44) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_2_REG (CSR_CPB_CSR_0_BASE + 0x1C48) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_3_REG (CSR_CPB_CSR_0_BASE + 0x1C4C) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_4_REG (CSR_CPB_CSR_0_BASE + 0x1C50) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_5_REG (CSR_CPB_CSR_0_BASE + 0x1C54) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_6_REG (CSR_CPB_CSR_0_BASE + 0x1C58) /* BMP AGE Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_AGE_RAM_ERR_7_REG (CSR_CPB_CSR_0_BASE + 0x1C5C) /* BMP AGE Mem错误历史记录寄存器 */ + +/* CPB_CSR_1 Base address of Module's Register */ +#define CSR_CPB_CSR_1_BASE (0x4000) + +/* **************************************************************************** */ +/* CPB_CSR_1 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPB_CSR_CIT_DATA_IN_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x500) +#define CSR_CPB_CSR_CIT_DEALC_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x504) +#define CSR_CPB_CSR_CIT_EC_CH_REG (CSR_CPB_CSR_1_BASE + 0x508) /* EC通道配置 */ +#define CSR_CPB_CSR_CPR_PRO_WT_REG (CSR_CPB_CSR_1_BASE + 0x600) +#define CSR_CPB_CSR_CPR_FIFO_CRDT_INIT_REG (CSR_CPB_CSR_1_BASE + 0x604) +#define CSR_CPB_CSR_CPR_DEALC_TX_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x610) +#define CSR_CPB_CSR_CPR_DEALC_RX_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x614) +#define CSR_CPB_CSR_CPR_PRLS_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x618) +#define CSR_CPB_CSR_CPR_COL_TH_REG (CSR_CPB_CSR_1_BASE + 0x61C) +#define CSR_CPB_CSR_CPR_PRO_DI_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x630) +#define CSR_CPB_CSR_CPR_PRO_DEALC_TX_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x634) +#define CSR_CPB_CSR_CPR_PRO_DEALC_RX_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x638) +#define CSR_CPB_CSR_CPR_PRO_FIFO_CRDT_INIT_REG (CSR_CPB_CSR_1_BASE + 0x63C) +#define CSR_CPB_CSR_CPR_PRO_DEALC_RP_TH_REG (CSR_CPB_CSR_1_BASE + 0x640) +#define CSR_CPB_CSR_CPR_PRO_RRDY_FIFO_AF_TH_REG (CSR_CPB_CSR_1_BASE + 0x644) +#define CSR_CPB_CSR_CPR_OUT_ERR_EN_REG (CSR_CPB_CSR_1_BASE + 0x648) /* CPB输出给PERX的err bit有效使能 */ +#define CSR_CPB_CSR_CIT_DAT_FIFO_STA_REG (CSR_CPB_CSR_1_BASE + 0x1100) /* IPSUTX_CPB接口数据FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CIT_DEALC_FIFO_STA_REG \ + (CSR_CPB_CSR_1_BASE + 0x1104) /* IPSUTX_CPB接口通告PCI及其PRM cell申请接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CIT_IN_PKT_SOP_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1120) /* CPB从IPSUTX接收到报文SOP数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_PKT_EOP_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1124) /* CPB从IPSUTX接收到报文EOP数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_0_REG (CSR_CPB_CSR_1_BASE + 0x1130) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_1_REG (CSR_CPB_CSR_1_BASE + 0x1134) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_2_REG (CSR_CPB_CSR_1_BASE + 0x1138) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_3_REG (CSR_CPB_CSR_1_BASE + 0x113C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_4_REG (CSR_CPB_CSR_1_BASE + 0x1140) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_5_REG (CSR_CPB_CSR_1_BASE + 0x1144) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_6_REG (CSR_CPB_CSR_1_BASE + 0x1148) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_7_REG (CSR_CPB_CSR_1_BASE + 0x114C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_8_REG (CSR_CPB_CSR_1_BASE + 0x1150) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_9_REG (CSR_CPB_CSR_1_BASE + 0x1154) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_10_REG (CSR_CPB_CSR_1_BASE + 0x1158) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_11_REG (CSR_CPB_CSR_1_BASE + 0x115C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_12_REG (CSR_CPB_CSR_1_BASE + 0x1160) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_13_REG (CSR_CPB_CSR_1_BASE + 0x1164) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_14_REG (CSR_CPB_CSR_1_BASE + 0x1168) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_15_REG (CSR_CPB_CSR_1_BASE + 0x116C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_16_REG (CSR_CPB_CSR_1_BASE + 0x1170) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_17_REG (CSR_CPB_CSR_1_BASE + 0x1174) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_18_REG (CSR_CPB_CSR_1_BASE + 0x1178) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_19_REG (CSR_CPB_CSR_1_BASE + 0x117C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_20_REG (CSR_CPB_CSR_1_BASE + 0x1180) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_21_REG (CSR_CPB_CSR_1_BASE + 0x1184) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_22_REG (CSR_CPB_CSR_1_BASE + 0x1188) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_IN_CHNL_PKT_CNT_23_REG (CSR_CPB_CSR_1_BASE + 0x118C) /* CPB从IPSUTX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIT_RPT_IQ_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1190) /* CPB向IQ通告PCI次数的统计每个报文仅统计一次 */ +#define CSR_CPB_CSR_CIT_IQ_BP_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1194) /* IQ反压CPB发送侧报文通告的次数 */ +#define CSR_CPB_CSR_CIT_PAL_LESS_STA_REG (CSR_CPB_CSR_1_BASE + 0x1198) /* 发送侧非UP（MCU）通道预扣状态寄存器 */ +#define CSR_CPB_CSR_CIT_PAL_ERR_REG (CSR_CPB_CSR_1_BASE + 0x119C) /* 发送侧非UP（MCU）通道预扣不足错误中断 */ +#define CSR_CPB_CSR_CIT_SCHNL_ERR_REG (CSR_CPB_CSR_1_BASE + 0x11A0) /* IPSUTX送给CPB报文对应的channel越界错误 */ +#define CSR_CPB_CSR_CIT_FIFO_ERR_REG (CSR_CPB_CSR_1_BASE + 0x11A4) /* IPSUTX_CPB接口FIFO溢出错误 */ +#define CSR_CPB_CSR_CIT_EC_ILLEGAL_REG (CSR_CPB_CSR_1_BASE + 0x11A8) /* IPSUTX送过来的EC channel配置非法 */ +#define CSR_CPB_CSR_CIT_FIFO_RAM_ERR_REG (CSR_CPB_CSR_1_BASE + 0x11B0) /* CIT FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DAT_IN_RRDY_FIFO_STA_0_REG \ + (CSR_CPB_CSR_1_BASE + 0x1200) /* CPB_RX送入的读取控制信息及其FC RRDY回复FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DAT_IN_RRDY_FIFO_STA_1_REG \ + (CSR_CPB_CSR_1_BASE + 0x1204) /* CPB_RX送入的读取控制信息及其FC RRDY回复FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DAT_IN_RRDY_FIFO_STA_2_REG \ + (CSR_CPB_CSR_1_BASE + 0x1208) /* CPB_RX送入的读取控制信息及其FC RRDY回复FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DAT_IN_RRDY_FIFO_STA_3_REG \ + (CSR_CPB_CSR_1_BASE + 0x120C) /* CPB_RX送入的读取控制信息及其FC RRDY回复FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DAT_IN_RRDY_FIFO_STA_4_REG \ + (CSR_CPB_CSR_1_BASE + 0x1210) /* CPB_RX送入的读取控制信息及其FC RRDY回复FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DEALC_FIFO_STA_0_REG \ + (CSR_CPB_CSR_1_BASE + 0x1214) /* CPB_PERX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DEALC_FIFO_STA_1_REG \ + (CSR_CPB_CSR_1_BASE + 0x1218) /* CPB_PERX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DEALC_FIFO_STA_2_REG \ + (CSR_CPB_CSR_1_BASE + 0x121C) /* CPB_PERX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DEALC_FIFO_STA_3_REG \ + (CSR_CPB_CSR_1_BASE + 0x1220) /* CPB_PERX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_PRO_DEALC_FIFO_STA_4_REG \ + (CSR_CPB_CSR_1_BASE + 0x1224) /* CPB_PERX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_DEALC_FIFO_STA_REG \ + (CSR_CPB_CSR_1_BASE + 0x1228) /* CPB_PERX模块通告PRM cell释放FIFO的状态寄存器（经调度送出） */ +#define CSR_CPB_CSR_CPR_DAT_OUT_FIFO_STA_0_REG \ + (CSR_CPB_CSR_1_BASE + 0x122C) /* CPB_PERX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPR_DAT_OUT_FIFO_STA_1_REG \ + (CSR_CPB_CSR_1_BASE + 0x1230) /* CPB_PERX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPR_DAT_OUT_FIFO_STA_2_REG \ + (CSR_CPB_CSR_1_BASE + 0x1234) /* CPB_PERX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPR_DAT_OUT_FIFO_STA_3_REG \ + (CSR_CPB_CSR_1_BASE + 0x1238) /* CPB_PERX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPR_DAT_OUT_FIFO_STA_4_REG \ + (CSR_CPB_CSR_1_BASE + 0x123C) /* CPB_PERX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPR_PRLS_FIFO_STA_REG (CSR_CPB_CSR_1_BASE + 0x1240) /* CPB_PERX接口PRLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPR_OUT_PKT_SOP_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1244) /* CPB输出给PERX报文SOP数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_PKT_EOP_CNT_REG (CSR_CPB_CSR_1_BASE + 0x1248) /* CPB输出给PERX报文EOP数量的统计 */ +#define CSR_CPB_CSR_CPR_RRDY_SIDE_ERR_REG (CSR_CPB_CSR_1_BASE + 0x124C) /* FC业务释放报文对应的源错误 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_0_REG (CSR_CPB_CSR_1_BASE + 0x1250) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_1_REG (CSR_CPB_CSR_1_BASE + 0x1254) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_2_REG (CSR_CPB_CSR_1_BASE + 0x1258) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_3_REG (CSR_CPB_CSR_1_BASE + 0x125C) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_4_REG (CSR_CPB_CSR_1_BASE + 0x1260) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_5_REG (CSR_CPB_CSR_1_BASE + 0x1264) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_6_REG (CSR_CPB_CSR_1_BASE + 0x1268) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_7_REG (CSR_CPB_CSR_1_BASE + 0x126C) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_8_REG (CSR_CPB_CSR_1_BASE + 0x1270) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_9_REG (CSR_CPB_CSR_1_BASE + 0x1274) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_10_REG (CSR_CPB_CSR_1_BASE + 0x1278) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_11_REG (CSR_CPB_CSR_1_BASE + 0x127C) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_12_REG (CSR_CPB_CSR_1_BASE + 0x1280) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_13_REG (CSR_CPB_CSR_1_BASE + 0x1284) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_14_REG (CSR_CPB_CSR_1_BASE + 0x1288) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_15_REG (CSR_CPB_CSR_1_BASE + 0x128C) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_16_REG (CSR_CPB_CSR_1_BASE + 0x1290) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_17_REG (CSR_CPB_CSR_1_BASE + 0x1294) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_18_REG (CSR_CPB_CSR_1_BASE + 0x1298) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_19_REG (CSR_CPB_CSR_1_BASE + 0x129C) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_20_REG (CSR_CPB_CSR_1_BASE + 0x12A0) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_21_REG (CSR_CPB_CSR_1_BASE + 0x12A4) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_OUT_CHNL_PKT_CNT_22_REG (CSR_CPB_CSR_1_BASE + 0x12A8) /* CPB输出给PERX报文数量的统计 */ +#define CSR_CPB_CSR_CPR_SOF_MSM_0_REG \ + (CSR_CPB_CSR_1_BASE + 0x12AC) /* CPB输出报文给PERX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPR_SOF_MSM_1_REG \ + (CSR_CPB_CSR_1_BASE + 0x12B0) /* CPB输出报文给PERX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPR_SOF_MSM_2_REG \ + (CSR_CPB_CSR_1_BASE + 0x12B4) /* CPB输出报文给PERX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPR_SOF_MSM_3_REG \ + (CSR_CPB_CSR_1_BASE + 0x12B8) /* CPB输出报文给PERX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPR_SOF_MSM_4_REG \ + (CSR_CPB_CSR_1_BASE + 0x12BC) /* CPB输出报文给PERX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPR_EOF_MSM_0_REG \ + (CSR_CPB_CSR_1_BASE + 0x12C0) /* CPB输出报文给PERX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPR_EOF_MSM_1_REG \ + (CSR_CPB_CSR_1_BASE + 0x12C4) /* CPB输出报文给PERX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPR_EOF_MSM_2_REG \ + (CSR_CPB_CSR_1_BASE + 0x12C8) /* CPB输出报文给PERX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPR_EOF_MSM_3_REG \ + (CSR_CPB_CSR_1_BASE + 0x12CC) /* CPB输出报文给PERX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPR_EOF_MSM_4_REG \ + (CSR_CPB_CSR_1_BASE + 0x12D0) /* CPB输出报文给PERX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPR_FIFO_OV_ERR_REG (CSR_CPB_CSR_1_BASE + 0x12D4) /* CPB_PERX_PRO中FIFO上溢错误 */ +#define CSR_CPB_CSR_CPR_FIFO_ERR_REG (CSR_CPB_CSR_1_BASE + 0x12D8) /* CPB_PERX_MISC接口模块FIFO溢出错误 */ +#define CSR_CPB_CSR_CPR_FIFO_UF_ERR_REG (CSR_CPB_CSR_1_BASE + 0x12DC) /* CPB_PERX_PRO模块FIFO下溢错误 */ +#define CSR_CPB_CSR_CPR_SGE_CRDT_ERR_REG (CSR_CPB_CSR_1_BASE + 0x12E0) /* 发送往CPI的sge信用值微码填充错误 */ +#define CSR_CPB_CSR_CPR_SGE_CRDT_ERR_DMA_HED_L_REG (CSR_CPB_CSR_1_BASE + 0x12E4) /* sge预扣错误时微码填充的B8yte数据 \ + */ +#define CSR_CPB_CSR_CPR_SGE_CRDT_ERR_DMA_HED_H_REG (CSR_CPB_CSR_1_BASE + 0x12E8) /* sge预扣错误时微码填充的B8yte数据 \ + */ +#define CSR_CPB_CSR_CPR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_1_BASE + 0x12EC) /* CPR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_1_BASE + 0x12F0) /* CPR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPR_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_1_BASE + 0x12F4) /* CPR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPR_FIFO_RAM_ERR_3_REG (CSR_CPB_CSR_1_BASE + 0x12F8) /* CPR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPR_FIFO_RAM_ERR_4_REG (CSR_CPB_CSR_1_BASE + 0x12FC) /* CPR FIFO Mem错误历史记录寄存器 */ + +/* CPB_CSR_2 Base address of Module's Register */ +#define CSR_CPB_CSR_2_BASE (0x6000) + +/* **************************************************************************** */ +/* CPB_CSR_2 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPB_CSR_STL_RSP_API_FIFO_CRDT_INIT_REG (CSR_CPB_CSR_2_BASE + 0x800) /* 内部存储reponse/push API实体的信用 \ + */ +#define CSR_CPB_CSR_STL_PSH_CMD_WT_REG (CSR_CPB_CSR_2_BASE + 0x804) +#define CSR_CPB_CSR_STL_RD_REQ_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x80C) +#define CSR_CPB_CSR_STL_RD_CTRL_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x810) +#define CSR_CPB_CSR_CPB_STL_API_CRDT_INIT_REG (CSR_CPB_CSR_2_BASE + 0x814) +#define CSR_CPB_CSR_STL_STR_DI_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x818) +#define CSR_CPB_CSR_STL_STR_API_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x81C) +#define CSR_CPB_CSR_STL_CMD_API_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x820) +#define CSR_CPB_CSR_STL_ACKSTR_FIFO_AF_TH_REG (CSR_CPB_CSR_2_BASE + 0x824) /* streamout ACK FQ FIFO的将满阈值 */ +#define CSR_CPB_CSR_CDT_CRDT_CFG_REG (CSR_CPB_CSR_2_BASE + 0x8A0) /* ROB与CPB间的入口FIFO的信用配置 */ +#define CSR_CPB_CSR_CDT_PSH_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x8B0) /* ROB Push FIFO的配置 */ +#define CSR_CPB_CSR_STLIQ_PSH_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x900) /* STL IQ Push请求FIFO配置 */ +#define CSR_CPB_CSR_INNER_CHN_MAP_REG (CSR_CPB_CSR_2_BASE + 0x980) /* RX CPI Channel在CPB内部的散列分配模式配置 */ +#define CSR_CPB_CSR_DRP_ACK_TH_REG (CSR_CPB_CSR_2_BASE + 0x984) /* 报文Drop释放的Cell通告门限配置 */ +#define CSR_CPB_CSR_OQRX_PD_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x990) /* OQ调往RX方向的PD FIFO配置 */ +#define CSR_CPB_CSR_OQTX_PD_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x994) /* OQ调往TX方向的PD FIFO配置 */ +#define CSR_CPB_CSR_DRP_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x998) /* 报文Drop 请求FIFO配置 */ +#define CSR_CPB_CSR_DRP_TXRLS_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x99C) /* TX方向报文Drop RRL FIFO配置 */ +#define CSR_CPB_CSR_DRP_RXRLS_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x9A0) /* RX方向报文Drop RRL FIFO配置 */ +#define CSR_CPB_CSR_FDRP_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0x9A4) /* FTSO报文Drop 请求FIFO配置 */ +#define CSR_CPB_CSR_RX_NOR_CHN_WT0_REG (CSR_CPB_CSR_2_BASE + 0xA00) /* CPB_RX_NOR_0内Chn间Cell权重配置 */ +#define CSR_CPB_CSR_RX_NOR_CHN_WT1_REG (CSR_CPB_CSR_2_BASE + 0xA04) /* CPB_RX_NOR_1内Chn间Cell权重配置 */ +#define CSR_CPB_CSR_RX_NOR_CHN_WT2_REG (CSR_CPB_CSR_2_BASE + 0xA08) /* CPB_RX_NOR_2内Chn间Cell权重配置 */ +#define CSR_CPB_CSR_RX_NOR_CHN_WT3_REG (CSR_CPB_CSR_2_BASE + 0xA0C) /* CPB_RX_NOR_3内Chn间Cell权重配置 */ +#define CSR_CPB_CSR_RX_LB_CHN_WT3_REG (CSR_CPB_CSR_2_BASE + 0xA10) /* CPB_RX_LB内Chn间Cell权重配置 */ +#define CSR_CPB_CSR_RXLB_PORT_WT_0_REG (CSR_CPB_CSR_2_BASE + 0xA14) /* RXLB0内部8个port的WRR权重配置 */ +#define CSR_CPB_CSR_RXLB_PORT_WT_1_REG (CSR_CPB_CSR_2_BASE + 0xA18) /* RXLB1内部8个port的WRR权重配置 */ +#define CSR_CPB_CSR_COS_CHN_RXLB_CFG_0_REG (CSR_CPB_CSR_2_BASE + 0xA1C) /* RXLB的64个Cos的划分配置0 */ +#define CSR_CPB_CSR_COS_CHN_RXLB_CFG_1_REG (CSR_CPB_CSR_2_BASE + 0xA20) /* RXLB的64个Cos的划分配置1 */ +#define CSR_CPB_CSR_CPB_RX_CRDT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA30) /* CPB_RX相关信用配置 */ +#define CSR_CPB_CSR_CPB_RX_IDX_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA34) /* CPB_RX IDX信用配置 */ +#define CSR_CPB_CSR_CHN5_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA40) /* CPI侧Chn5 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN6_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA44) /* CPI侧Chn6 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN7_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA48) /* CPI侧Chn7 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN8_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA4C) /* CPI侧Chn8 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN9_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA50) /* CPI侧Chn9 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN10_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA54) /* CPI侧Chn10 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN11_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA58) /* CPI侧Chn11 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN12_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA5C) /* CPI侧Chn12 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN13_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA60) /* CPI侧Chn13 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN14_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA64) /* CPI侧Chn14 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN15_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA68) /* CPI侧Chn15 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN16_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA6C) /* CPI侧Chn16 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN17_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA70) /* CPI侧Chn17 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN18_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA74) /* CPI侧Chn18 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN19_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA78) /* CPI侧Chn19 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN20_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA7C) /* CPI侧Chn20 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN21_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA80) /* CPI侧Chn21 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN22_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA84) /* CPI侧Chn22 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN23_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA88) /* CPI侧Chn23 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_CHN24_SGE_CFG_REG (CSR_CPB_CSR_2_BASE + 0xA8C) /* CPI侧Chn24 SGE信用配置寄存器 */ +#define CSR_CPB_CSR_HOST0_SGE_TH_REG (CSR_CPB_CSR_2_BASE + 0xA90) /* CPI侧Host0所有Chn的SGE空间反压门限配置 */ +#define CSR_CPB_CSR_HOST1_SGE_TH_REG (CSR_CPB_CSR_2_BASE + 0xA94) /* CPI侧Host1所有Chn的SGE空间反压门限配置 */ +#define CSR_CPB_CSR_HOST2_SGE_TH_REG (CSR_CPB_CSR_2_BASE + 0xA98) /* CPI侧Host2所有Chn的SGE空间反压门限配置 */ +#define CSR_CPB_CSR_HOST3_SGE_TH_REG (CSR_CPB_CSR_2_BASE + 0xA9C) /* CPI侧Host3所有Chn的SGE空间反压门限配置 */ +#define CSR_CPB_CSR_HOST4_SGE_TH_REG (CSR_CPB_CSR_2_BASE + 0xAA0) /* CPI侧Host4所有Chn的SGE空间反压门限配置 */ +#define CSR_CPB_CSR_SGE_SHR_BP_TH_REG (CSR_CPB_CSR_2_BASE + 0xAA4) /* CPI侧SGE Share空间反压门限配置 */ +#define CSR_CPB_CSR_SGE_BP_GAP_REG (CSR_CPB_CSR_2_BASE + 0xAA8) /* CPB内部的CPI侧每个Chn的SGE信用反压的Gap门限配置 */ +#define CSR_CPB_CSR_CHN5_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAB0) /* CPI侧Chn5 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN6_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAB4) /* CPI侧Chn6 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN7_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAB8) /* CPI侧Chn7 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN8_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xABC) /* CPI侧Chn8 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN9_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAC0) /* CPI侧Chn9 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN10_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAC4) /* CPI侧Chn10 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN11_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAC8) /* CPI侧Chn11 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN12_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xACC) /* CPI侧Chn12 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN13_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAD0) /* CPI侧Chn13 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN14_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAD4) /* CPI侧Chn14 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN15_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAD8) /* CPI侧Chn15 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN16_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xADC) /* CPI侧Chn16 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN17_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAE0) /* CPI侧Chn17 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN18_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAE4) /* CPI侧Chn18 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN19_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAE8) /* CPI侧Chn19 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN20_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAEC) /* CPI侧Chn20 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN21_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAF0) /* CPI侧Chn21 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN22_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAF4) /* CPI侧Chn22 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN23_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAF8) /* CPI侧Chn23 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_CHN24_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xAFC) /* CPI侧Chn24 DAT信用配置寄存器 */ +#define CSR_CPB_CSR_HOST0_DAT_TH_REG (CSR_CPB_CSR_2_BASE + 0xB00) /* CPI侧Host0所有Chn的DAT空间反压门限配置 */ +#define CSR_CPB_CSR_HOST1_DAT_TH_REG (CSR_CPB_CSR_2_BASE + 0xB04) /* CPI侧Host1所有Chn的DAT空间反压门限配置 */ +#define CSR_CPB_CSR_HOST2_DAT_TH_REG (CSR_CPB_CSR_2_BASE + 0xB08) /* CPI侧Host2所有Chn的DAT空间反压门限配置 */ +#define CSR_CPB_CSR_HOST3_DAT_TH_REG (CSR_CPB_CSR_2_BASE + 0xB0C) /* CPI侧Host3所有Chn的DAT空间反压门限配置 */ +#define CSR_CPB_CSR_HOST4_DAT_TH_REG (CSR_CPB_CSR_2_BASE + 0xB10) /* CPI侧Host4所有Chn的DAT空间反压门限配置 */ +#define CSR_CPB_CSR_DAT_SHR_BP_TH_REG (CSR_CPB_CSR_2_BASE + 0xB14) /* CPI侧DAT Share空间反压门限配置 */ +#define CSR_CPB_CSR_DAT_BP_GAP_REG (CSR_CPB_CSR_2_BASE + 0xB18) /* CPB内部的CPI侧每个Chn的DAT信用反压的Gap门限配置 */ +#define CSR_CPB_CSR_RX_MPU_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB20) /* RX MPU通道DAT信用配置寄存器 */ +#define CSR_CPB_CSR_RX_LB0_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB24) /* RX Loopback0通道DAT信用配置寄存器 */ +#define CSR_CPB_CSR_RX_LB1_DAT_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB28) /* RX Loopback1通道DAT信用配置寄存器 */ +#define CSR_CPB_CSR_RXLB_DAT_BP_GAP_REG (CSR_CPB_CSR_2_BASE + 0xB30) /* CPB内部的RXLB Chn的DAT信用反压的Gap门限配置 */ +#define CSR_CPB_CSR_RXPD_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB40) /* CPB_RX的PD请求FIFO配置 */ +#define CSR_CPB_CSR_RXMPU_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB44) /* CPB_RX的to MPU的PD请求FIFO配置 */ +#define CSR_CPB_CSR_RXLB_COS_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB48) /* RXLB COS PD请求FIFO配置 */ +#define CSR_CPB_CSR_RX_IDX_WT_REG (CSR_CPB_CSR_2_BASE + 0xB54) /* CPB_RX内部5个PRO间IDX信用申请权重配置 */ +#define CSR_CPB_CSR_RX_HOST0_CHN_M_REG (CSR_CPB_CSR_2_BASE + 0xB58) /* RX Host0 8 Chn的配置 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_CFG_REG (CSR_CPB_CSR_2_BASE + 0xB60) /* RX TSO3 RLS请求FIFO配置 */ +#define CSR_CPB_CSR_STL_CMD_API_RD_REQ_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1400) /* stateless tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_CMD_API_RD_REQ_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1404) /* stateless tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_CMD_API_RD_REQ_FIFO_STA_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1408) /* stateless tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_CMD_API_RD_REQ_FIFO_STA_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x140C) /* stateless tile送入的CMD API FIFO状态及其数据读取请求FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_STR_API_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1410) /* stateless tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_STR_API_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1414) /* stateless tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_STR_API_FIFO_STA_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1418) /* stateless tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_STR_API_FIFO_STA_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x141C) /* stateless tile送入的streamout API FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_WR_RD_DAT_IN_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1420) /* stateless tile进行BMU读写的数据输入FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_WR_RD_DAT_IN_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1424) /* stateless tile进行BMU读写的数据输入FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_HDR_DAT_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1430) /* CPB发送给stateless tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_HDR_DAT_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1434) /* CPB发送给stateless tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_HDR_DAT_FIFO_STA_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1438) /* CPB发送给stateless tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_HDR_DAT_FIFO_STA_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x143C) /* CPB发送给stateless tile的API header及其数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CD_CRC_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1440) /* CPB发送给stateless tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CD_CRC_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1444) /* CPB发送给stateless tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CD_CRC_FIFO_STA_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1448) /* CPB发送给stateless tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CD_CRC_FIFO_STA_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x144C) /* CPB发送给stateless tile的CD及其CRC数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CS_NPTR_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1450) /* CPB发送给stateless tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CS_NPTR_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1454) /* CPB发送给stateless tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CS_NPTR_FIFO_STA_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1458) /* CPB发送给stateless tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_RSP_API_CS_NPTR_FIFO_STA_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x145C) /* CPB发送给stateless tile的CKS及其NPTR数据FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_STR_CMD_CNT_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1460) /* stateless tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STL_STR_CMD_CNT_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1464) /* stateless tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STL_STR_CMD_CNT_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1468) /* stateless tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STL_STR_CMD_CNT_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x146C) /* stateless tile下发给CPB streamout、CMD的次数统计 */ +#define CSR_CPB_CSR_STL_ACK_RSP_CNT_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1470) /* CPB ACK stateless FQ及其stateless tile的次数统计 */ +#define CSR_CPB_CSR_STL_ACK_RSP_CNT_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1474) /* CPB ACK stateless FQ及其stateless tile的次数统计 */ +#define CSR_CPB_CSR_STL_ACK_RSP_CNT_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1478) /* CPB ACK stateless FQ及其stateless tile的次数统计 */ +#define CSR_CPB_CSR_STL_ACK_RSP_CNT_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x147C) /* CPB ACK stateless FQ及其stateless tile的次数统计 */ +#define CSR_CPB_CSR_STL_PSH_CNT_0_REG (CSR_CPB_CSR_2_BASE + 0x1480) /* stateless push请求次数统计 */ +#define CSR_CPB_CSR_STL_PSH_CNT_1_REG (CSR_CPB_CSR_2_BASE + 0x1484) /* stateless push请求次数统计 */ +#define CSR_CPB_CSR_STL_PSH_CNT_2_REG (CSR_CPB_CSR_2_BASE + 0x1488) /* stateless push请求次数统计 */ +#define CSR_CPB_CSR_STL_PSH_CNT_3_REG (CSR_CPB_CSR_2_BASE + 0x148C) /* stateless push请求次数统计 */ +#define CSR_CPB_CSR_STL_CELL_MDF_CNT_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1490) /* stateless tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STL_CELL_MDF_CNT_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1494) /* stateless tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STL_CELL_MDF_CNT_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1498) /* stateless tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STL_CELL_MDF_CNT_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x149C) /* stateless tile下发cell modify streamout次数统计 */ +#define CSR_CPB_CSR_STL_WR_DI_CTRL_FIFO_STA_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x14A4) /* stateless tile进行BMU写的数据控制FIFO及其streamout ACK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_WR_DI_CTRL_FIFO_STA_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x14A8) /* stateless tile进行BMU写的数据控制FIFO及其streamout ACK FIFO状态寄存器 */ +#define CSR_CPB_CSR_STL_FIFO_OV_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x14B0) +#define CSR_CPB_CSR_STL_FIFO_OV_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x14B4) +#define CSR_CPB_CSR_STL_FIFO_UF_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x14B8) +#define CSR_CPB_CSR_STL_FIFO_UF_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x14BC) +#define CSR_CPB_CSR_STLWR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x14C0) /* STL WR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLWR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x14C4) /* STL WR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLSTR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x14D0) /* STL STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLSTR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x14D4) /* STL STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLSTR_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_2_BASE + 0x14D8) /* STL STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLSTR_FIFO_RAM_ERR_3_REG (CSR_CPB_CSR_2_BASE + 0x14DC) /* STL STR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLRSP_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x14E0) /* STL RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLRSP_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x14E4) /* STL RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLRSP_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_2_BASE + 0x14E8) /* STL RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_STLRSP_FIFO_RAM_ERR_3_REG (CSR_CPB_CSR_2_BASE + 0x14EC) /* STL RSP FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CDT_PSH_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x15C8) /* CDT PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_CDT_FIFO_ERR_REG (CSR_CPB_CSR_2_BASE + 0x15CC) /* CDT FIFO 溢出状态记录 */ +#define CSR_CPB_CSR_CDT_CRDT_STA_REG (CSR_CPB_CSR_2_BASE + 0x15D0) /* CDT Credit状态指示 */ +#define CSR_CPB_CSR_STLIQ_PKT_PSH_CNT_0_REG (CSR_CPB_CSR_2_BASE + 0x1600) /* STLIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_PKT_PSH_CNT_1_REG (CSR_CPB_CSR_2_BASE + 0x1604) /* STLIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_PKT_PSH_CNT_2_REG (CSR_CPB_CSR_2_BASE + 0x1608) /* STLIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_PKT_PSH_CNT_3_REG (CSR_CPB_CSR_2_BASE + 0x160C) /* STLIQ的PKT Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_MSG_PSH_CNT_0_REG (CSR_CPB_CSR_2_BASE + 0x1610) /* STLIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_MSG_PSH_CNT_1_REG (CSR_CPB_CSR_2_BASE + 0x1614) /* STLIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_MSG_PSH_CNT_2_REG (CSR_CPB_CSR_2_BASE + 0x1618) /* STLIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_MSG_PSH_CNT_3_REG (CSR_CPB_CSR_2_BASE + 0x161C) /* STLIQ的MSG Push请求统计 */ +#define CSR_CPB_CSR_FLOWPAC_PSH_REQ_CNT_REG (CSR_CPB_CSR_2_BASE + 0x1660) /* STLIQ给ROB的Flowpac Push请求统计 */ +#define CSR_CPB_CSR_NONFLOWPAC_PSH_REQ_CNT_REG (CSR_CPB_CSR_2_BASE + 0x1664) /* STLIQ给ROB的nonflowpac Push请求统计 */ +#define CSR_CPB_CSR_STLIQ_PSH_FIFO_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1680) /* STLIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STLIQ_PSH_FIFO_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1684) /* STLIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STLIQ_PSH_FIFO_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1688) /* STLIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_STLIQ_PSH_FIFO_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x168C) /* STLIQ PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_ROB_PSH_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x16B4) /* ROB PSH FIFO状态寄存器 */ +#define CSR_CPB_CSR_RX_EPD_CNT_REG (CSR_CPB_CSR_2_BASE + 0x1700) /* QU OQ调往RX方向总的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_0_REG (CSR_CPB_CSR_2_BASE + 0x1704) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_1_REG (CSR_CPB_CSR_2_BASE + 0x1708) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_2_REG (CSR_CPB_CSR_2_BASE + 0x170C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_3_REG (CSR_CPB_CSR_2_BASE + 0x1710) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_4_REG (CSR_CPB_CSR_2_BASE + 0x1714) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_5_REG (CSR_CPB_CSR_2_BASE + 0x1718) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_6_REG (CSR_CPB_CSR_2_BASE + 0x171C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_7_REG (CSR_CPB_CSR_2_BASE + 0x1720) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_8_REG (CSR_CPB_CSR_2_BASE + 0x1724) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_9_REG (CSR_CPB_CSR_2_BASE + 0x1728) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_10_REG (CSR_CPB_CSR_2_BASE + 0x172C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_11_REG (CSR_CPB_CSR_2_BASE + 0x1730) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_12_REG (CSR_CPB_CSR_2_BASE + 0x1734) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_13_REG (CSR_CPB_CSR_2_BASE + 0x1738) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_14_REG (CSR_CPB_CSR_2_BASE + 0x173C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_15_REG (CSR_CPB_CSR_2_BASE + 0x1740) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_16_REG (CSR_CPB_CSR_2_BASE + 0x1744) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_17_REG (CSR_CPB_CSR_2_BASE + 0x1748) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_18_REG (CSR_CPB_CSR_2_BASE + 0x174C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_19_REG (CSR_CPB_CSR_2_BASE + 0x1750) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_20_REG (CSR_CPB_CSR_2_BASE + 0x1754) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_21_REG (CSR_CPB_CSR_2_BASE + 0x1758) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_RX_CHN_EPD_CNT_22_REG (CSR_CPB_CSR_2_BASE + 0x175C) /* QU OQ调往RX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_EPD_CNT_REG (CSR_CPB_CSR_2_BASE + 0x1760) /* QU OQ调往TX方向总的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_0_REG (CSR_CPB_CSR_2_BASE + 0x1764) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_1_REG (CSR_CPB_CSR_2_BASE + 0x1768) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_2_REG (CSR_CPB_CSR_2_BASE + 0x176C) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_3_REG (CSR_CPB_CSR_2_BASE + 0x1770) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_4_REG (CSR_CPB_CSR_2_BASE + 0x1774) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_5_REG (CSR_CPB_CSR_2_BASE + 0x1778) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_6_REG (CSR_CPB_CSR_2_BASE + 0x177C) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_7_REG (CSR_CPB_CSR_2_BASE + 0x1780) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_8_REG (CSR_CPB_CSR_2_BASE + 0x1784) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_9_REG (CSR_CPB_CSR_2_BASE + 0x1788) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TX_CHN_EPD_CNT_10_REG (CSR_CPB_CSR_2_BASE + 0x178C) /* QU OQ调往TX方向各个Chn的PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x1790) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x1794) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x1798) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_3_REG \ + (CSR_CPB_CSR_2_BASE + 0x179C) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_4_REG \ + (CSR_CPB_CSR_2_BASE + 0x17A0) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_5_REG \ + (CSR_CPB_CSR_2_BASE + 0x17A4) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_6_REG \ + (CSR_CPB_CSR_2_BASE + 0x17A8) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_TXMAC_CHN_TSO12_EPD_CNT_7_REG \ + (CSR_CPB_CSR_2_BASE + 0x17AC) /* QU OQ调往TX MAC各Chn的TSO1/2 PD数量统计 */ +#define CSR_CPB_CSR_DRP_REQ_CNT_REG (CSR_CPB_CSR_2_BASE + 0x17B0) /* QU OQ报文Drop请求次数统计 */ +#define CSR_CPB_CSR_RX_TSO3_DRP_CNT_REG (CSR_CPB_CSR_2_BASE + 0x17B4) /* RX方向TSO3报文丢弃数量统计 */ +#define CSR_CPB_CSR_TX_TSO3_DRP_CNT_REG (CSR_CPB_CSR_2_BASE + 0x17B8) /* TX方向TSO3报文丢弃数量统计 */ +#define CSR_CPB_CSR_DRP_EOP_CNT_REG (CSR_CPB_CSR_2_BASE + 0x17BC) /* CPB DROP接口丢弃报文量统计 */ +#define CSR_CPB_CSR_RX_EPD_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17D0) /* RX EPD FIFO状态寄存器 */ +#define CSR_CPB_CSR_TX_EPD_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17D4) /* TX EPD FIFO状态寄存器 */ +#define CSR_CPB_CSR_NDRP_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17D8) /* NDRP FIFO状态寄存器 */ +#define CSR_CPB_CSR_DRP_RXRLS_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17DC) /* DRP RXRLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_DRP_TXRLS_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17E0) /* DRP TXRLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_FDRP_FIFO_STA_REG (CSR_CPB_CSR_2_BASE + 0x17E4) /* FDRP FIFO状态寄存器 */ +#define CSR_CPB_CSR_FTSO_DRP_REQ_CNT_REG (CSR_CPB_CSR_2_BASE + 0x17E8) /* FAST TSO丢弃请求统计 */ +#define CSR_CPB_CSR_COQ_FIFO_OF_ERR_REG (CSR_CPB_CSR_2_BASE + 0x17F0) /* CBP OQ接口模块FIFO Overflow状态记录 */ +#define CSR_CPB_CSR_COQ_FIFO_UF_ERR_REG (CSR_CPB_CSR_2_BASE + 0x17F4) /* CBP OQ接口模块FIFO Uderflow状态记录 */ +#define CSR_CPB_CSR_COQ_ERR_REG (CSR_CPB_CSR_2_BASE + 0x17F8) /* CBP OQ接口模块错误状态记录 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1800) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1804) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1808) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x180C) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_4_REG (CSR_CPB_CSR_2_BASE + 0x1810) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_5_REG (CSR_CPB_CSR_2_BASE + 0x1814) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_6_REG (CSR_CPB_CSR_2_BASE + 0x1818) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_7_REG (CSR_CPB_CSR_2_BASE + 0x181C) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_8_REG (CSR_CPB_CSR_2_BASE + 0x1820) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_9_REG (CSR_CPB_CSR_2_BASE + 0x1824) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_10_REG (CSR_CPB_CSR_2_BASE + 0x1828) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_11_REG (CSR_CPB_CSR_2_BASE + 0x182C) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_12_REG (CSR_CPB_CSR_2_BASE + 0x1830) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_13_REG (CSR_CPB_CSR_2_BASE + 0x1834) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_14_REG (CSR_CPB_CSR_2_BASE + 0x1838) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_15_REG (CSR_CPB_CSR_2_BASE + 0x183C) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_16_REG (CSR_CPB_CSR_2_BASE + 0x1840) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_17_REG (CSR_CPB_CSR_2_BASE + 0x1844) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_18_REG (CSR_CPB_CSR_2_BASE + 0x1848) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_CHN_CRDT_STA_19_REG (CSR_CPB_CSR_2_BASE + 0x184C) /* RX方向CPI Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_CRDT_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1850) /* RX方向CPI HOST的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_CRDT_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1854) /* RX方向CPI HOST的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_CRDT_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1858) /* RX方向CPI HOST的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_CRDT_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x185C) /* RX方向CPI HOST的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_CRDT_STA_4_REG (CSR_CPB_CSR_2_BASE + 0x1860) /* RX方向CPI HOST的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_SHR_CRDT_STA_REG (CSR_CPB_CSR_2_BASE + 0x1864) /* RX方向CPI Share空间的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_WCRDT_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1870) /* RX方向CPI写属性信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_WCRDT_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1874) /* RX方向CPI写属性信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_WCRDT_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1878) /* RX方向CPI写属性信用状态寄存器 */ +#define CSR_CPB_CSR_RX_CPI_HOST_WCRDT_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x187C) /* RX方向CPI写属性信用状态寄存器 */ +#define CSR_CPB_CSR_RXLB_CHN_CRDT_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1880) /* RX方向MPU及RXLB Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RXLB_CHN_CRDT_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1884) /* RX方向MPU及RXLB Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RXLB_CHN_CRDT_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1888) /* RX方向MPU及RXLB Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_RX_IDX_CRDT_STA_REG (CSR_CPB_CSR_2_BASE + 0x188C) /* RX方向IDX的信用状态寄存器 */ +#define CSR_CPB_CSR_RXLB_FP_BMP_STA_REG (CSR_CPB_CSR_2_BASE + 0x1890) /* RXLB Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_EMPTY_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1894) /* RX方向PD FIFO empty状态寄存器0 */ +#define CSR_CPB_CSR_RXPD_FIFO_EMPTY_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1898) /* RX方向PD FIFO empty状态寄存器1 */ +#define CSR_CPB_CSR_RXPD_FIFO_EMPTY_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x189C) /* RX方向PD FIFO empty状态寄存器2 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x18A0) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x18A4) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x18A8) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x18AC) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_4_REG (CSR_CPB_CSR_2_BASE + 0x18B0) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_5_REG (CSR_CPB_CSR_2_BASE + 0x18B4) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_6_REG (CSR_CPB_CSR_2_BASE + 0x18B8) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_7_REG (CSR_CPB_CSR_2_BASE + 0x18BC) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_8_REG (CSR_CPB_CSR_2_BASE + 0x18C0) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_9_REG (CSR_CPB_CSR_2_BASE + 0x18C4) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_FIFO_FILL_STA_10_REG (CSR_CPB_CSR_2_BASE + 0x18C8) /* RX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x1900) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x1904) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x1908) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x190C) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_4_REG (CSR_CPB_CSR_2_BASE + 0x1910) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_5_REG (CSR_CPB_CSR_2_BASE + 0x1914) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_6_REG (CSR_CPB_CSR_2_BASE + 0x1918) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_7_REG (CSR_CPB_CSR_2_BASE + 0x191C) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_8_REG (CSR_CPB_CSR_2_BASE + 0x1920) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_9_REG (CSR_CPB_CSR_2_BASE + 0x1924) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_10_REG (CSR_CPB_CSR_2_BASE + 0x1928) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_11_REG (CSR_CPB_CSR_2_BASE + 0x192C) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_12_REG (CSR_CPB_CSR_2_BASE + 0x1930) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_13_REG (CSR_CPB_CSR_2_BASE + 0x1934) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_14_REG (CSR_CPB_CSR_2_BASE + 0x1938) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_15_REG (CSR_CPB_CSR_2_BASE + 0x193C) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_16_REG (CSR_CPB_CSR_2_BASE + 0x1940) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_17_REG (CSR_CPB_CSR_2_BASE + 0x1944) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_18_REG (CSR_CPB_CSR_2_BASE + 0x1948) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_19_REG (CSR_CPB_CSR_2_BASE + 0x194C) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_20_REG (CSR_CPB_CSR_2_BASE + 0x1950) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_21_REG (CSR_CPB_CSR_2_BASE + 0x1954) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RXPD_PRO_FSM_STA_22_REG (CSR_CPB_CSR_2_BASE + 0x1958) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_RX_CRDT_OF_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x1990) /* RX方向Credit Overflow Err历史记录寄存器0 */ +#define CSR_CPB_CSR_RX_CRDT_OF_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x1994) /* RX方向Credit Overflow Err历史记录寄存器1 */ +#define CSR_CPB_CSR_RX_CRDT_UF_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x1998) /* RX方向Credit Underflow Err历史记录寄存器0 */ +#define CSR_CPB_CSR_RX_CRDT_UF_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x199C) /* RX方向Credit Underflow Err历史记录寄存器1 */ +#define CSR_CPB_CSR_RXPD_FIFO_OF_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x19A0) /* RX方向PD FIFO Overflow Err历史记录寄存器0 \ + */ +#define CSR_CPB_CSR_RXPD_FIFO_OF_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x19A4) /* RX方向PD FIFO Overflow Err历史记录寄存器1 \ + */ +#define CSR_CPB_CSR_RXPD_FIFO_OF_ERR_2_REG (CSR_CPB_CSR_2_BASE + 0x19A8) /* RX方向PD FIFO Overflow Err历史记录寄存器2 \ + */ +#define CSR_CPB_CSR_RXPD_FIFO_UF_ERR_0_REG \ + (CSR_CPB_CSR_2_BASE + 0x19B0) /* RX方向PD FIFO Underflow Err历史记录寄存器0 */ +#define CSR_CPB_CSR_RXPD_FIFO_UF_ERR_1_REG \ + (CSR_CPB_CSR_2_BASE + 0x19B4) /* RX方向PD FIFO Underflow Err历史记录寄存器1 */ +#define CSR_CPB_CSR_RXPD_FIFO_UF_ERR_2_REG \ + (CSR_CPB_CSR_2_BASE + 0x19B8) /* RX方向PD FIFO Underflow Err历史记录寄存器2 */ +#define CSR_CPB_CSR_RXLB_PD_RAM_ERR_REG (CSR_CPB_CSR_2_BASE + 0x19BC) /* RXLB PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPB_RX_ERR_0_REG (CSR_CPB_CSR_2_BASE + 0x19C0) /* CPB RX处理错误历史记录寄存器0 */ +#define CSR_CPB_CSR_CPB_RX_ERR_1_REG (CSR_CPB_CSR_2_BASE + 0x19C4) /* CPB RX处理错误历史记录寄存器1 */ +#define CSR_CPB_CSR_CPB_RX_ERR_2_REG (CSR_CPB_CSR_2_BASE + 0x19C8) /* CPB RX处理错误历史记录寄存器2 */ +#define CSR_CPB_CSR_CPB_RX_ERR_3_REG (CSR_CPB_CSR_2_BASE + 0x19CC) /* CPB RX处理错误历史记录寄存器3 */ +#define CSR_CPB_CSR_CPB_RX_ERR_4_REG (CSR_CPB_CSR_2_BASE + 0x19D0) /* CPB RX处理错误历史记录寄存器4 */ +#define CSR_CPB_CSR_CPB_RX_ERR_5_REG (CSR_CPB_CSR_2_BASE + 0x19D4) /* CPB RX处理错误历史记录寄存器5 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_STA_0_REG (CSR_CPB_CSR_2_BASE + 0x19E0) /* RX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_STA_1_REG (CSR_CPB_CSR_2_BASE + 0x19E4) /* RX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_STA_2_REG (CSR_CPB_CSR_2_BASE + 0x19E8) /* RX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_STA_3_REG (CSR_CPB_CSR_2_BASE + 0x19EC) /* RX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_RX_TSO3_RLS_FIFO_STA_4_REG (CSR_CPB_CSR_2_BASE + 0x19F0) /* RX TSO3 RLS FIFO状态寄存器 */ + +/* CPB_CSR_3 Base address of Module's Register */ +#define CSR_CPB_CSR_3_BASE (0x8000) + +/* **************************************************************************** */ +/* CPB_CSR_3 Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPB_CSR_CPB_INDIR_DAT_0_REG (CSR_CPB_CSR_3_BASE + 0x180) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_1_REG (CSR_CPB_CSR_3_BASE + 0x184) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_2_REG (CSR_CPB_CSR_3_BASE + 0x188) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_3_REG (CSR_CPB_CSR_3_BASE + 0x18C) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_4_REG (CSR_CPB_CSR_3_BASE + 0x190) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_5_REG (CSR_CPB_CSR_3_BASE + 0x194) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_6_REG (CSR_CPB_CSR_3_BASE + 0x198) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_7_REG (CSR_CPB_CSR_3_BASE + 0x19C) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_8_REG (CSR_CPB_CSR_3_BASE + 0x1A0) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_9_REG (CSR_CPB_CSR_3_BASE + 0x1A4) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_10_REG (CSR_CPB_CSR_3_BASE + 0x1A8) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_11_REG (CSR_CPB_CSR_3_BASE + 0x1AC) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_12_REG (CSR_CPB_CSR_3_BASE + 0x1B0) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_13_REG (CSR_CPB_CSR_3_BASE + 0x1B4) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_14_REG (CSR_CPB_CSR_3_BASE + 0x1B8) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CPB_INDIR_DAT_15_REG (CSR_CPB_CSR_3_BASE + 0x1BC) /* 间接访问数据寄存器 */ +#define CSR_CPB_CSR_CIR_ALC_PRO_WT_REG (CSR_CPB_CSR_3_BASE + 0x400) +#define CSR_CPB_CSR_CIR_RPCI_PRO_WT_REG (CSR_CPB_CSR_3_BASE + 0x404) +#define CSR_CPB_CSR_CIR_ALC_MAC_NCSI_PORT_WT_REG (CSR_CPB_CSR_3_BASE + 0x408) +#define CSR_CPB_CSR_CIR_DATA_IN_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x410) +#define CSR_CPB_CSR_CIR_ALC_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x414) +#define CSR_CPB_CSR_CIR_RPCI_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x418) +#define CSR_CPB_CSR_CIR_ALC_RP_TH_REG (CSR_CPB_CSR_3_BASE + 0x41C) +#define CSR_CPB_CSR_CIR_DATA_IN_FIFO_DROP_TH_REG (CSR_CPB_CSR_3_BASE + 0x420) +#define CSR_CPB_CSR_CIR_IPSURX_BP_EN_REG (CSR_CPB_CSR_3_BASE + 0x424) +#define CSR_CPB_CSR_CIR_ALC_SHP_EN_REG (CSR_CPB_CSR_3_BASE + 0x428) /* CIR申请PRM限流300Mpps使能开关 */ +#define CSR_CPB_CSR_CPT_MAC03_TS_REG (CSR_CPB_CSR_3_BASE + 0x700) +#define CSR_CPB_CSR_CPT_MAC47_TS_REG (CSR_CPB_CSR_3_BASE + 0x704) +#define CSR_CPB_CSR_CPT_MACLB_TS_REG (CSR_CPB_CSR_3_BASE + 0x708) +#define CSR_CPB_CSR_CPT_TS_CFG_REG (CSR_CPB_CSR_3_BASE + 0x70C) +#define CSR_CPB_CSR_CPT_CRDT_INIT_REG (CSR_CPB_CSR_3_BASE + 0x710) +#define CSR_CPB_CSR_CPT_DEALC_TX_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x720) +#define CSR_CPB_CSR_CPT_DEALC_RX_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x724) +#define CSR_CPB_CSR_CPT_PRLS_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x728) +#define CSR_CPB_CSR_CPT_COL_TH_REG (CSR_CPB_CSR_3_BASE + 0x72C) +#define CSR_CPB_CSR_CPT_PRO_DI_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x740) +#define CSR_CPB_CSR_CPT_PRO_DEALC_TX_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x744) +#define CSR_CPB_CSR_CPT_PRO_DEALC_RX_FIFO_AF_TH_REG (CSR_CPB_CSR_3_BASE + 0x748) +#define CSR_CPB_CSR_CPT_PRO_FIFO_CRDT_INIT_REG (CSR_CPB_CSR_3_BASE + 0x74C) +#define CSR_CPB_CSR_CPT_PRO_DEALC_RP_TH_REG (CSR_CPB_CSR_3_BASE + 0x750) +#define CSR_CPB_CSR_CPT_OUT_ERR_EN_REG (CSR_CPB_CSR_3_BASE + 0x754) /* CPB输出给PETX的err bit有效使能 */ +#define CSR_CPB_CSR_CPT_TXLB_EN_REG (CSR_CPB_CSR_3_BASE + 0x758) /* TXLB通道使能配置 */ +#define CSR_CPB_CSR_TX_CRR0_EN_REG (CSR_CPB_CSR_3_BASE + 0xC00) /* CPB_TX_NOR0的CRR使能配置 */ +#define CSR_CPB_CSR_TX_CRR0_PID_REG (CSR_CPB_CSR_3_BASE + 0xC04) /* CPB_TX_NOR0的CRR时隙的端口配置 */ +#define CSR_CPB_CSR_TX_CRR1_EN_REG (CSR_CPB_CSR_3_BASE + 0xC08) /* CPB_TX_NOR1的CRR使能配置 */ +#define CSR_CPB_CSR_TX_CRR1_PID_REG (CSR_CPB_CSR_3_BASE + 0xC0C) /* CPB_TX_NOR1的CRR时隙的端口配置 */ +#define CSR_CPB_CSR_TX_CRR2_EN_REG (CSR_CPB_CSR_3_BASE + 0xC10) /* TXLB的CRR使能配置 */ +#define CSR_CPB_CSR_TX_CRR2_PID_REG (CSR_CPB_CSR_3_BASE + 0xC14) /* TXLB的CRR时隙的端口配置 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG0_REG (CSR_CPB_CSR_3_BASE + 0xC20) /* TX方向Chn0 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG1_REG (CSR_CPB_CSR_3_BASE + 0xC24) /* TX方向Chn1 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG2_REG (CSR_CPB_CSR_3_BASE + 0xC28) /* TX方向Chn2 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG3_REG (CSR_CPB_CSR_3_BASE + 0xC2C) /* TX方向Chn3 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG4_REG (CSR_CPB_CSR_3_BASE + 0xC30) /* TX方向Chn4 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG5_REG (CSR_CPB_CSR_3_BASE + 0xC34) /* TX方向Chn5 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG6_REG (CSR_CPB_CSR_3_BASE + 0xC38) /* TX方向Chn6 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG7_REG (CSR_CPB_CSR_3_BASE + 0xC3C) /* TX方向Chn7 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG8_REG (CSR_CPB_CSR_3_BASE + 0xC40) /* TX方向Chn8 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG9_REG (CSR_CPB_CSR_3_BASE + 0xC44) /* TX方向Chn9 Credit配置寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_CFG10_REG (CSR_CPB_CSR_3_BASE + 0xC48) /* TX方向Chn10 Credit配置寄存器 */ +#define CSR_CPB_CSR_CPB_TX_CRDT_CFG_REG (CSR_CPB_CSR_3_BASE + 0xC50) /* CPB_TX相关信用配置 */ +#define CSR_CPB_CSR_TXLB_PD_FIFO_CFG_REG (CSR_CPB_CSR_3_BASE + 0xC60) /* TXLB的PD请求FIFO配置 */ +#define CSR_CPB_CSR_TX_COS_FIFO_CFG_REG (CSR_CPB_CSR_3_BASE + 0xC64) /* TX COS PD请求FIFO配置 */ +#define CSR_CPB_CSR_FTSO_RLS_FIFO_CFG_REG (CSR_CPB_CSR_3_BASE + 0xC68) /* Fast TSO Pptr Rls请求FIFO配置 */ +#define CSR_CPB_CSR_TX_IDX_WT_REG (CSR_CPB_CSR_3_BASE + 0xC70) /* CPB_TX内部3个PRO间IDX信用申请权重配置 */ +#define CSR_CPB_CSR_MAG_BP_EN_REG (CSR_CPB_CSR_3_BASE + 0xC74) /* MAG的反压使能配置 */ +#define CSR_CPB_CSR_TX_TSO3_RLS_FIFO_CFG_REG (CSR_CPB_CSR_3_BASE + 0xC80) /* TX TSO3 RLS请求FIFO配置 */ +#define CSR_CPB_CSR_CIR_DAT_IN_FIFO_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1000) /* IPSURX_CPB接口数据FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CIR_DAT_IN_FIFO_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1004) /* IPSURX_CPB接口数据FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CIR_DAT_IN_FIFO_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1008) /* IPSURX_CPB接口数据FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CIR_RPT_FIFO_STA_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1010) /* IPSURX_CPB接口通告PCI及其PRM cell申请接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CIR_RPT_FIFO_STA_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1014) /* IPSURX_CPB接口通告PCI及其PRM cell申请接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CIR_RPT_FIFO_STA_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1018) /* IPSURX_CPB接口通告PCI及其PRM cell申请接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CIR_IN_PKT_SOP_CNT_REG (CSR_CPB_CSR_3_BASE + 0x1020) /* CPB从IPSURX接收到报文SOP数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PKT_EOP_CNT_REG (CSR_CPB_CSR_3_BASE + 0x1024) /* CPB从IPSURX接收到报文SOP数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_0_REG (CSR_CPB_CSR_3_BASE + 0x1030) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_1_REG (CSR_CPB_CSR_3_BASE + 0x1034) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_2_REG (CSR_CPB_CSR_3_BASE + 0x1038) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_3_REG (CSR_CPB_CSR_3_BASE + 0x103C) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_4_REG (CSR_CPB_CSR_3_BASE + 0x1040) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_5_REG (CSR_CPB_CSR_3_BASE + 0x1044) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_6_REG (CSR_CPB_CSR_3_BASE + 0x1048) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_7_REG (CSR_CPB_CSR_3_BASE + 0x104C) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_8_REG (CSR_CPB_CSR_3_BASE + 0x1050) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_9_REG (CSR_CPB_CSR_3_BASE + 0x1054) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_IN_PORT_PKT_CNT_10_REG (CSR_CPB_CSR_3_BASE + 0x1058) /* CPB从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_DRP_PKT_CNT_0_REG (CSR_CPB_CSR_3_BASE + 0x1060) /* CPB丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_DRP_PKT_CNT_1_REG (CSR_CPB_CSR_3_BASE + 0x1064) /* CPB丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_DRP_PKT_CNT_2_REG (CSR_CPB_CSR_3_BASE + 0x1068) /* CPB丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_DRP_PKT_CNT_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1070) /* CPB由于入口FIFO满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_DRP_PKT_CNT_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1074) /* CPB由于入口FIFO满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_DRP_PKT_CNT_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1078) /* CPB由于入口FIFO满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_BMU_AF_DRP_PKT_CNT_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1080) /* CPB由于BMU满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_BMU_AF_DRP_PKT_CNT_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1084) /* CPB由于BMU满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_BMU_AF_DRP_PKT_CNT_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1088) /* CPB由于BMU满丢弃从IPSURX接收到报文数量的统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_CNT_0_REG (CSR_CPB_CSR_3_BASE + 0x1090) /* IPSURX_CPB接口FIFO反压次数统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_CNT_1_REG (CSR_CPB_CSR_3_BASE + 0x1094) /* IPSURX_CPB接口FIFO反压次数统计 */ +#define CSR_CPB_CSR_CIR_FIFO_AF_CNT_2_REG (CSR_CPB_CSR_3_BASE + 0x1098) /* IPSURX_CPB接口FIFO反压次数统计 */ +#define CSR_CPB_CSR_CIR_CUT_PKT_CNT_0_REG (CSR_CPB_CSR_3_BASE + 0x10A0) /* CPB丢包时截断报文数量的统计 */ +#define CSR_CPB_CSR_CIR_CUT_PKT_CNT_1_REG (CSR_CPB_CSR_3_BASE + 0x10A4) /* CPB丢包时截断报文数量的统计 */ +#define CSR_CPB_CSR_CIR_CUT_PKT_CNT_2_REG (CSR_CPB_CSR_3_BASE + 0x10A8) /* CPB丢包时截断报文数量的统计 */ +#define CSR_CPB_CSR_CIR_RPT_IQ_CNT_REG (CSR_CPB_CSR_3_BASE + 0x10B0) /* CPB向IQ通告PCI次数的统计每个报文仅统计一次 */ +#define CSR_CPB_CSR_CIR_IQ_BP_CNT_REG (CSR_CPB_CSR_3_BASE + 0x10B4) /* IQ反压CPB接收侧报文通告的次数 */ +#define CSR_CPB_CSR_CIR_SPORT_ERR_REG (CSR_CPB_CSR_3_BASE + 0x10B8) /* IPSURX送给CPB的报文Sport超过有效范围 */ +#define CSR_CPB_CSR_CIR_ALC_PRM_CNUM_FULL_ERR_REG \ + (CSR_CPB_CSR_3_BASE + \ + 0x10BC) /* 由于受到PRM的反压，造成IPSURX_CPB内部申请PRM空间时根据COS汇聚，counter计满错误，counter最大值127 */ +#define CSR_CPB_CSR_CIR_FIFO_ERR_REG (CSR_CPB_CSR_3_BASE + 0x10C0) /* IPSURX_CPB模块FIFO溢出错误 */ +#define CSR_CPB_CSR_CIR_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_3_BASE + 0x10D0) /* CIR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CIR_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_3_BASE + 0x10D4) /* CIR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CIR_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_3_BASE + 0x10D8) /* CIR FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CIR_PRM_BP_HIS_0_REG (CSR_CPB_CSR_3_BASE + 0x10E8) /* PRM反压丢弃历史记录0 */ +#define CSR_CPB_CSR_CIR_PRM_BP_HIS_1_REG (CSR_CPB_CSR_3_BASE + 0x10EC) /* PRM反压丢弃历史记录1 */ +#define CSR_CPB_CSR_CIR_PRM_BP_HIS_2_REG (CSR_CPB_CSR_3_BASE + 0x10F0) /* PRM反压丢弃历史记录2 */ +#define CSR_CPB_CSR_CIR_PRM_BP_HIS_3_REG (CSR_CPB_CSR_3_BASE + 0x10F4) /* PRM反压丢弃历史记录3 */ +#define CSR_CPB_CSR_CIR_PRM_BP_HIS_4_REG (CSR_CPB_CSR_3_BASE + 0x10F8) /* PRM反压丢弃历史记录4 */ +#define CSR_CPB_CSR_CPT_PRO_DAT_IN_FIFO_STA_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1300) /* CPB_TX送入的读取控制信息FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPT_PRO_DAT_IN_FIFO_STA_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1304) /* CPB_TX送入的读取控制信息FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPT_PRO_DAT_IN_FIFO_STA_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1308) /* CPB_TX送入的读取控制信息FIFO的状态寄存器 */ +#define CSR_CPB_CSR_CPT_PRO_DEALC_FIFO_STA_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1310) /* CPB_PETX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPT_PRO_DEALC_FIFO_STA_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1314) /* CPB_PETX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPT_PRO_DEALC_FIFO_STA_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1318) /* CPB_PETX_PRO通告PRM cell释放接口FIFO状态寄存器 */ +#define CSR_CPB_CSR_CPT_DEALC_FIFO_STA_REG \ + (CSR_CPB_CSR_3_BASE + 0x1320) /* CPB_PETX模块通告PRM cell释放FIFO的状态寄存器（经调度送出） */ +#define CSR_CPB_CSR_CPT_PRLS_FIFO_STA_REG \ + (CSR_CPB_CSR_3_BASE + 0x1324) /* CPB_PETX模块通告packet release FIFO的状态寄存器（经调度送出） */ +#define CSR_CPB_CSR_CPT_DAT_OUT_FIFO_STA_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1330) /* CPB_PETX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPT_DAT_OUT_FIFO_STA_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1334) /* CPB_PETX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPT_DAT_OUT_FIFO_STA_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1338) /* CPB_PETX接口输出数据FIFO的状态寄存器（经调度送给PERX） */ +#define CSR_CPB_CSR_CPT_OUT_PKT_SOP_CNT_REG (CSR_CPB_CSR_3_BASE + 0x1340) /* CPB输出给PETX报文SOP数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_PKT_EOP_CNT_REG (CSR_CPB_CSR_3_BASE + 0x1344) /* CPB输出给PETX报文EOP数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_0_REG (CSR_CPB_CSR_3_BASE + 0x1350) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_1_REG (CSR_CPB_CSR_3_BASE + 0x1354) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_2_REG (CSR_CPB_CSR_3_BASE + 0x1358) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_3_REG (CSR_CPB_CSR_3_BASE + 0x135C) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_4_REG (CSR_CPB_CSR_3_BASE + 0x1360) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_5_REG (CSR_CPB_CSR_3_BASE + 0x1364) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_6_REG (CSR_CPB_CSR_3_BASE + 0x1368) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_7_REG (CSR_CPB_CSR_3_BASE + 0x136C) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_8_REG (CSR_CPB_CSR_3_BASE + 0x1370) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_9_REG (CSR_CPB_CSR_3_BASE + 0x1374) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_OUT_CHNL_PKT_CNT_10_REG (CSR_CPB_CSR_3_BASE + 0x1378) /* CPB输出给PETX报文数量的统计 */ +#define CSR_CPB_CSR_CPT_SOF_MSM_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1380) /* CPB输出报文给PETX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPT_SOF_MSM_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1384) /* CPB输出报文给PETX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPT_SOF_MSM_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1388) /* CPB输出报文给PETX时，请求SOF与CD INFO中的SOF不匹配 */ +#define CSR_CPB_CSR_CPT_EOF_MSM_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1390) /* CPB输出报文给PETX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPT_EOF_MSM_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1394) /* CPB输出报文给PETX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPT_EOF_MSM_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1398) /* CPB输出报文给PETX时，读取请求EOF与CD INFO中的EOF不匹配 */ +#define CSR_CPB_CSR_CPT_DEALC_TX_BP_TM_REG \ + (CSR_CPB_CSR_3_BASE + 0x13A0) /* CPB_PETX接口上PRM对DEALC_TX反压持续的最大时间 */ +#define CSR_CPB_CSR_CPT_DEALC_RX_BP_TM_REG \ + (CSR_CPB_CSR_3_BASE + 0x13A4) /* CPB_PETX接口上PRM对DEALC_RX反压持续的最大时间 */ +#define CSR_CPB_CSR_CPT_TS_CFG_ERR_REG (CSR_CPB_CSR_3_BASE + 0x13A8) /* CPB_PETX对应三个pro时隙配置错误 */ +#define CSR_CPB_CSR_CPT_FIFO_OV_ERR_REG (CSR_CPB_CSR_3_BASE + 0x13AC) /* CPB_PERX接口模块FIFO上溢错误 */ +#define CSR_CPB_CSR_CPT_FIFO_UF_ERR_REG (CSR_CPB_CSR_3_BASE + 0x13B0) /* CPB_PERX接口模块FIFO下溢错误 */ +#define CSR_CPB_CSR_CPT_FIFO_RAM_ERR_0_REG (CSR_CPB_CSR_3_BASE + 0x13B4) /* CPT FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPT_FIFO_RAM_ERR_1_REG (CSR_CPB_CSR_3_BASE + 0x13B8) /* CPT FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPT_FIFO_RAM_ERR_2_REG (CSR_CPB_CSR_3_BASE + 0x13BC) /* CPT FIFO Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1A00) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1A04) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1A08) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_3_REG (CSR_CPB_CSR_3_BASE + 0x1A0C) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_4_REG (CSR_CPB_CSR_3_BASE + 0x1A10) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_5_REG (CSR_CPB_CSR_3_BASE + 0x1A14) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_6_REG (CSR_CPB_CSR_3_BASE + 0x1A18) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_7_REG (CSR_CPB_CSR_3_BASE + 0x1A1C) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_8_REG (CSR_CPB_CSR_3_BASE + 0x1A20) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_9_REG (CSR_CPB_CSR_3_BASE + 0x1A24) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_CHN_CRDT_STA_10_REG (CSR_CPB_CSR_3_BASE + 0x1A28) /* TX方向每个Chn的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_IDX_CRDT_STA_REG (CSR_CPB_CSR_3_BASE + 0x1A30) /* TX方向IDX的信用状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1A40) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1A44) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1A48) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_3_REG (CSR_CPB_CSR_3_BASE + 0x1A4C) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_4_REG (CSR_CPB_CSR_3_BASE + 0x1A50) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_5_REG (CSR_CPB_CSR_3_BASE + 0x1A54) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_6_REG (CSR_CPB_CSR_3_BASE + 0x1A58) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TX_FP_BMP_STA_7_REG (CSR_CPB_CSR_3_BASE + 0x1A5C) /* TX方向PD Free Ptr Bitmap状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_EMPTY_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1A60) /* TX方向PD FIFO empty状态寄存器0 */ +#define CSR_CPB_CSR_TXPD_FIFO_EMPTY_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1A64) /* TX方向PD FIFO empty状态寄存器1 */ +#define CSR_CPB_CSR_TXPD_FIFO_EMPTY_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1A68) /* TX方向PD FIFO empty状态寄存器2 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1A70) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1A74) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1A78) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_3_REG (CSR_CPB_CSR_3_BASE + 0x1A7C) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_4_REG (CSR_CPB_CSR_3_BASE + 0x1A80) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_5_REG (CSR_CPB_CSR_3_BASE + 0x1A84) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_6_REG (CSR_CPB_CSR_3_BASE + 0x1A88) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_7_REG (CSR_CPB_CSR_3_BASE + 0x1A8C) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_FILL_STA_8_REG (CSR_CPB_CSR_3_BASE + 0x1A90) /* TX方向PD FIFO fill cnt状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1AA0) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1AA4) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1AA8) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_3_REG (CSR_CPB_CSR_3_BASE + 0x1AAC) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_4_REG (CSR_CPB_CSR_3_BASE + 0x1AB0) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_5_REG (CSR_CPB_CSR_3_BASE + 0x1AB4) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_6_REG (CSR_CPB_CSR_3_BASE + 0x1AB8) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_7_REG (CSR_CPB_CSR_3_BASE + 0x1ABC) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_8_REG (CSR_CPB_CSR_3_BASE + 0x1AC0) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_9_REG (CSR_CPB_CSR_3_BASE + 0x1AC4) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_TXPD_PRO_FSM_STA_10_REG (CSR_CPB_CSR_3_BASE + 0x1AC8) /* RX方向PD处理的FSM状态寄存器 */ +#define CSR_CPB_CSR_MAG_BP_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1AD0) /* MAG的反压状态指示0 */ +#define CSR_CPB_CSR_MAG_BP_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1AD4) /* MAG的反压状态指示1 */ +#define CSR_CPB_CSR_TX_FTSO_RLS_FIFO_STA_REG (CSR_CPB_CSR_3_BASE + 0x1AE8) /* TX FTSO Pptr Rls FIFO状态寄存器 */ +#define CSR_CPB_CSR_TX_TSO3_RLS_FIFO_STA_0_REG (CSR_CPB_CSR_3_BASE + 0x1AF0) /* TX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_TX_TSO3_RLS_FIFO_STA_1_REG (CSR_CPB_CSR_3_BASE + 0x1AF4) /* TX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_TX_TSO3_RLS_FIFO_STA_2_REG (CSR_CPB_CSR_3_BASE + 0x1AF8) /* TX TSO3 RLS FIFO状态寄存器 */ +#define CSR_CPB_CSR_TX_CRDT_OF_ERR_REG (CSR_CPB_CSR_3_BASE + 0x1B00) /* TX方向Credit Overflow Err历史记录寄存器 */ +#define CSR_CPB_CSR_TX_CRDT_UF_ERR_REG (CSR_CPB_CSR_3_BASE + 0x1B04) /* TX方向Credit Underflow Err历史记录寄存器 */ +#define CSR_CPB_CSR_TXPD_FIFO_OF_ERR_0_REG (CSR_CPB_CSR_3_BASE + 0x1B10) /* TX方向PD FIFO Overflow Err历史记录寄存器0 \ + */ +#define CSR_CPB_CSR_TXPD_FIFO_OF_ERR_1_REG (CSR_CPB_CSR_3_BASE + 0x1B14) /* TX方向PD FIFO Overflow Err历史记录寄存器1 \ + */ +#define CSR_CPB_CSR_TXPD_FIFO_OF_ERR_2_REG (CSR_CPB_CSR_3_BASE + 0x1B18) /* TX方向PD FIFO Overflow Err历史记录寄存器2 \ + */ +#define CSR_CPB_CSR_TXPD_FIFO_UF_ERR_0_REG \ + (CSR_CPB_CSR_3_BASE + 0x1B20) /* TX方向PD FIFO Underflow Err历史记录寄存器0 */ +#define CSR_CPB_CSR_TXPD_FIFO_UF_ERR_1_REG \ + (CSR_CPB_CSR_3_BASE + 0x1B24) /* TX方向PD FIFO Underflow Err历史记录寄存器1 */ +#define CSR_CPB_CSR_TXPD_FIFO_UF_ERR_2_REG \ + (CSR_CPB_CSR_3_BASE + 0x1B28) /* TX方向PD FIFO Underflow Err历史记录寄存器2 */ +#define CSR_CPB_CSR_TX_FTSO_RLS_FIFO_ERR_REG \ + (CSR_CPB_CSR_3_BASE + 0x1B30) /* TX FTSO Pptr Rls FIFO Underflow/Overflow Err历史记录寄存器 */ +#define CSR_CPB_CSR_TSO_RAM_ERR_REG (CSR_CPB_CSR_3_BASE + 0x1B34) /* TSO CTX Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_0_REG (CSR_CPB_CSR_3_BASE + 0x1B40) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_1_REG (CSR_CPB_CSR_3_BASE + 0x1B44) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_2_REG (CSR_CPB_CSR_3_BASE + 0x1B48) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_3_REG (CSR_CPB_CSR_3_BASE + 0x1B4C) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_4_REG (CSR_CPB_CSR_3_BASE + 0x1B50) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_5_REG (CSR_CPB_CSR_3_BASE + 0x1B54) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_6_REG (CSR_CPB_CSR_3_BASE + 0x1B58) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_TX_PD_RAM_ERR_7_REG (CSR_CPB_CSR_3_BASE + 0x1B5C) /* TX PD Mem错误历史记录寄存器 */ +#define CSR_CPB_CSR_CPB_TX_ERR_0_REG (CSR_CPB_CSR_3_BASE + 0x1B80) /* CPB TX处理错误历史记录寄存器0 */ +#define CSR_CPB_CSR_CPB_TX_ERR_1_REG (CSR_CPB_CSR_3_BASE + 0x1B84) /* CPB TX处理错误历史记录寄存器1 */ +#define CSR_CPB_CSR_CPB_TX_ERR_2_REG (CSR_CPB_CSR_3_BASE + 0x1B88) /* CPB TX处理错误历史记录寄存器2 */ +#define CSR_CPB_CSR_CPB_TX_ERR_3_REG (CSR_CPB_CSR_3_BASE + 0x1B8C) /* CPB TX处理错误历史记录寄存器3 */ +#define CSR_CPB_CSR_CPB_TX_ERR_4_REG (CSR_CPB_CSR_3_BASE + 0x1B90) /* CPB TX处理错误历史记录寄存器4 */ +#define CSR_CPB_CSR_CPB_TX_ERR_5_REG (CSR_CPB_CSR_3_BASE + 0x1B94) /* CPB TX处理错误历史记录寄存器5 */ + +#endif // CPB_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_c_union_define.h new file mode 100644 index 000000000..649f21cfa --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_c_union_define.h @@ -0,0 +1,23677 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cpi_c_union_define.h +// Project line : IT产品线 +// Department : 图灵ICT处理器开发部 +// Author : xxx +// Version : V100 +// Date : +// Description : Hi 1823 is a throughput of 100Gbps CNA chip. It provide large bandwith, low latency, scalability +// converged network solution, support network convergency, virtualization, protocol offload, and serves IT product and +// CT product. Others : Generated automatically by nManager V5.1 History : xxx 2020/07/27 20:37:29 Create +// file +// ****************************************************************************** + +#ifndef CPI_C_UNION_DEFINE_H +#define CPI_C_UNION_DEFINE_H + +/* Define the union csr_msi_cap_csr_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_enable : 1; /* [0] */ + u32 msi_mutiple_message_enable : 3; /* [3:1] */ + u32 msi_x_function_mask : 1; /* [4] */ + u32 msi_x_enable : 1; /* [5] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_cap_csr_dw0_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_msi_cap_csr_dw0_u msi_cap_csr_dw0[2]; /* 0 */ +} S_msi_cap_csr_REGS_TYPE; + +/* Declare the struct pointor of the module msi_cap_csr */ +extern volatile S_msi_cap_csr_REGS_TYPE *gopmsi_cap_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetMSI_CAP_CSR_DW0_msi_enable(unsigned int umsi_enable); +int iSetMSI_CAP_CSR_DW0_msi_mutiple_message_enable(unsigned int umsi_mutiple_message_enable); +int iSetMSI_CAP_CSR_DW0_msi_x_function_mask(unsigned int umsi_x_function_mask); +int iSetMSI_CAP_CSR_DW0_msi_x_enable(unsigned int umsi_x_enable); + +/* Define the union csr_up_pcie_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_pcie_link : 5; /* [4:0] */ + u32 rsv_0 : 26; /* [30:5] */ + u32 ucpu_ini_sts : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_pcie_status_u; + +/* Define the union csr_up_int_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_int_sts : 1; /* [0] */ + u32 ucpu_rx_api_int_sts : 1; /* [1] */ + u32 ucpu_mb_int_sts : 1; /* [2] */ + u32 ucpu_mctprx_int_sts : 4; /* [6:3] */ + u32 ucpu_mctptx_int_sts : 4; /* [10:7] */ + u32 ucpu_tlprx_int_sts : 1; /* [11] */ + u32 ucpu_tlptx_int_sts : 1; /* [12] */ + u32 ucpu_clprx_int_sts : 4; /* [16:13] */ + u32 ucpu_crt_err : 1; /* [17] */ + u32 ucpu_uncrt_err : 1; /* [18] */ + u32 axi_bus_err : 1; /* [19] */ + u32 cpi_fatal_err : 1; /* [20] */ + u32 cpi_nonfatal_err : 1; /* [21] */ + u32 cpi_table_ecc_serr : 1; /* [22] */ + u32 host_mpu_notify_int_sts : 5; /* [27:23] */ + u32 rsv_1 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_status_u; + +/* Define the union csr_up_int_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_int_en : 1; /* [0] */ + u32 ucpu_rx_api_int_en : 1; /* [1] */ + u32 ucpu_mb_int_en : 1; /* [2] */ + u32 ucpu_mctprx_int_en : 4; /* [6:3] */ + u32 ucpu_mctptx_int_en : 4; /* [10:7] */ + u32 ucpu_tlprx_int_en : 1; /* [11] */ + u32 ucpu_tlptx_int_en : 1; /* [12] */ + u32 ucpu_clprx_int_en : 4; /* [16:13] */ + u32 ucpu_crt_int_en : 1; /* [17] */ + u32 ucpu_uncrt_int_en : 1; /* [18] */ + u32 axi_bus_err_int_en : 1; /* [19] */ + u32 cpi_fatal_err_en : 1; /* [20] */ + u32 cpi_nonfatal_err_en : 1; /* [21] */ + u32 cpi_table_ecc_serr_en : 1; /* [22] */ + u32 host_mpu_notify_int_en : 5; /* [27:23] */ + u32 rsv_2 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_ctl_u; + +/* Define the union csr_up_direct_access_lock_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_dir_acc_lck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_direct_access_lock_u; + +/* Define the union csr_up_aeq_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_len : 21; /* [20:0] */ + u32 rsv_3 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_aeq_len_u; + +/* Define the union csr_up_aeq_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_ba : 26; /* [25:0] */ + u32 rsv_4 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_aeq_ba_u; + +/* Define the union csr_up_aeq_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_ci : 22; /* [21:0] */ + u32 rsv_5 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_aeq_ci_u; + +/* Define the union csr_up_aeq_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_aeq_pi : 22; /* [21:0] */ + u32 rsv_6 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_aeq_pi_u; + +/* Define the union csr_up_rx_api_buf_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_api_buf_len : 21; /* [20:0] */ + u32 rsv_7 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_api_buf_len_u; + +/* Define the union csr_up_rx_api_buf_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_api_buf_ba : 26; /* [25:0] */ + u32 rsv_8 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_api_buf_ba_u; + +/* Define the union csr_up_rx_api_buf_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_api_buf_ci : 22; /* [21:0] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_api_buf_ci_u; + +/* Define the union csr_up_rx_api_buf_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_api_buf_pi : 22; /* [21:0] */ + u32 rsv_10 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_api_buf_pi_u; + +/* Define the union csr_up_tx_api_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_tx_api_dest : 5; /* [4:0] */ + u32 ucpu_tx_api_code : 2; /* [6:5] */ + u32 op_type : 1; /* [7] */ + u32 ucpu_tx_api_len : 3; /* [10:8] */ + u32 rsv_11 : 1; /* [11] */ + u32 ucpu_api_rsp_len : 4; /* [15:12] */ + u32 src_tag_l : 12; /* [27:16] */ + u32 rsv_12 : 2; /* [29:28] */ + u32 status : 1; /* [30] */ + u32 ucpu_tx_api_issue : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tx_api_ctl_u; + +/* Define the union csr_up_tx_api_ctl_vio_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_tx_api_thread_id : 7; /* [6:0] */ + u32 up_tx_api_vio : 1; /* [7] */ + u32 up_tx_api_nvme : 1; /* [8] */ + u32 up_tx_rsvd_field : 6; /* [14:9] */ + u32 rsv_13 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tx_api_ctl_vio_u; + +/* Define the union csr_up_rb_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 up_aeq_timeout : 8; /* [7:0] */ + u32 rsv_14 : 8; /* [15:8] */ + u32 up_rb_timeout : 8; /* [23:16] */ + u32 up_mctp_timeout_off : 1; /* [24] */ + u32 up_mb_timeout_off : 1; /* [25] */ + u32 rsv_15 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rb_timeout_u; + +/* Define the union csr_up_xfer_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xcmd_otd : 4; /* [3:0] */ + u32 tlp_restart : 1; /* [4] */ + u32 apiram_init_start : 1; /* [5] */ + u32 apiram_init_done : 1; /* [6] */ + u32 rsv_16 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_xfer_ctrl_u; + +/* Define the union csr_up_tx_api_payload_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_tx_api_payload : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tx_api_payload_u; + +/* Define the union csr_up_int_coll_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_int_coll : 3; /* [2:0] */ + u32 rsv_17 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_coll_u; + +/* Define the union csr_up_int_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_18 : 16; /* [15:0] */ + u32 ucpu_int_timeout : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_timeout_u; + +/* Define the union csr_up_tlp_rx_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlprx_len : 21; /* [20:0] */ + u32 rsv_19 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_rx_len_u; + +/* Define the union csr_up_tlp_rx_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlprx_ba : 26; /* [25:0] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_rx_ba_u; + +/* Define the union csr_up_tlp_rx_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlprx_ci : 22; /* [21:0] */ + u32 rsv_21 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_rx_ci_u; + +/* Define the union csr_up_tlp_rx_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlprx_pi : 22; /* [21:0] */ + u32 rsv_22 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_rx_pi_u; + +/* Define the union csr_up_tlp_tx_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlptx_len : 21; /* [20:0] */ + u32 rsv_23 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_tx_len_u; + +/* Define the union csr_up_tlp_tx_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlptx_ba : 26; /* [25:0] */ + u32 rsv_24 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_tx_ba_u; + +/* Define the union csr_up_tlp_tx_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlptx_ci : 22; /* [21:0] */ + u32 rsv_25 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_tx_ci_u; + +/* Define the union csr_up_tlp_tx_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_tlptx_pi : 22; /* [21:0] */ + u32 rsv_26 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_tlp_tx_pi_u; + +/* Define the union csr_up_mctprx_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctprx_len : 21; /* [20:0] */ + u32 rsv_27 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctprx_len_u; + +/* Define the union csr_up_mctprx_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctprx_ba : 26; /* [25:0] */ + u32 rsv_28 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctprx_ba_u; + +/* Define the union csr_up_mctprx_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctprx_ci : 22; /* [21:0] */ + u32 rsv_29 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctprx_ci_u; + +/* Define the union csr_up_mctprx_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctprx_pi : 22; /* [21:0] */ + u32 rsv_30 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctprx_pi_u; + +/* Define the union csr_up_mctptx_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctptx_len : 21; /* [20:0] */ + u32 rsv_31 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctptx_len_u; + +/* Define the union csr_up_mctptx_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctptx_ba : 26; /* [25:0] */ + u32 rsv_32 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctptx_ba_u; + +/* Define the union csr_up_mctptx_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctptx_ci : 22; /* [21:0] */ + u32 rsv_33 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctptx_ci_u; + +/* Define the union csr_up_mctptx_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_port_mctptx_pi : 22; /* [21:0] */ + u32 rsv_34 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mctptx_pi_u; + +/* Define the union csr_up_csr_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_acc_csr_node_addr : 27; /* [26:0] */ + u32 ucpu_acc_csr_status : 1; /* [27] */ + u32 ucpu_acc_csr_op_code : 2; /* [29:28] */ + u32 ucpu_acc_csr_size : 1; /* [30] */ + u32 ucpu_acc_csr_issue : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_csr_ctl_u; + +/* Define the union csr_up_csr_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_acc_csr_wdat_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_csr_data0_u; + +/* Define the union csr_up_csr_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_acc_csr_wdat_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_csr_data1_u; + +/* Define the union csr_up_api_rdat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_api_rdat : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_api_rdat_u; + +/* Define the union csr_up_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 power_ctrl : 1; /* [0] */ + u32 spmem_tmod : 7; /* [7:1] */ + u32 tpmem_tmod : 8; /* [15:8] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_ctrl_u; + +/* Define the union csr_up_rb_dbgctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rb_dbg_sel : 5; /* [4:0] */ + u32 rsv_36 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rb_dbgctl_u; + +/* Define the union csr_up_rb_dbgdat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pi_ci_acc : 21; /* [20:0] */ + u32 rsv_37 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rb_dbgdat0_u; + +/* Define the union csr_up_rb_dbgdat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rb_cnt : 27; /* [26:0] */ + u32 rsv_38 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rb_dbgdat1_u; + +/* Define the union csr_up_fsm_dbg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxbuf_cur_st : 6; /* [5:0] */ + u32 aeq_cur_st : 6; /* [11:6] */ + u32 apirx_cur_st : 6; /* [17:12] */ + u32 apitx_cur_st : 3; /* [20:18] */ + u32 axi_bus_err : 2; /* [22:21] */ + u32 rsv_39 : 4; /* [26:23] */ + u32 tlp_xfer_err : 4; /* [30:27] */ + u32 rsv_40 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_fsm_dbg0_u; + +/* Define the union csr_up_fsm_dbg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 axixfer_cur_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_fsm_dbg1_u; + +/* Define the union csr_up_fsm_dbg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txbuf_cur_st : 20; /* [19:0] */ + u32 rsv_41 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_fsm_dbg2_u; + +/* Define the union csr_up_fsm_dbg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clp_cur_st : 4; /* [3:0] */ + u32 vpd_cur_st : 4; /* [7:4] */ + u32 mctprx_cur_st : 7; /* [14:8] */ + u32 rsv_42 : 1; /* [15] */ + u32 rxtlp_cur_st : 6; /* [21:16] */ + u32 txtlp_cur_st : 9; /* [30:22] */ + u32 rsv_43 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_fsm_dbg3_u; + +/* Define the union csr_up_mem_dbg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtlp_rama_errin : 2; /* [1:0] */ + u32 rxtlp_ramb_errin : 2; /* [3:2] */ + u32 upitf_rsp_ram_errin : 2; /* [5:4] */ + u32 prt0_rbdatfifo_ram_errin : 2; /* [7:6] */ + u32 prt1_rbdatfifo_ram_errin : 2; /* [9:8] */ + u32 prt2_rbdatfifo_ram_errin : 2; /* [11:10] */ + u32 prt3_rbdatfifo_ram_errin : 2; /* [13:12] */ + u32 prt0_txbuf_ram_errin : 2; /* [15:14] */ + u32 prt1_txbuf_ram_errin : 2; /* [17:16] */ + u32 prt2_txbuf_ram_errin : 2; /* [19:18] */ + u32 prt3_txbuf_ram_errin : 2; /* [21:20] */ + u32 axi_cnt_clr : 1; /* [22] */ + u32 rsv_44 : 1; /* [23] */ + u32 prt0_rxpctl_mb_ram_errin : 2; /* [25:24] */ + u32 prt1_rxpctl_mb_ram_errin : 2; /* [27:26] */ + u32 prt2_rxpctl_mb_ram_errin : 2; /* [29:28] */ + u32 prt3_rxpctl_mb_ram_errin : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_dbg0_u; + +/* Define the union csr_up_mem_dbg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rxtlp_rama_erraddr : 6; /* [5:0] */ + u32 rsv_45 : 2; /* [7:6] */ + u32 rxtlp_rama_err : 2; /* [9:8] */ + u32 rxtlp_ramb_erraddr : 6; /* [15:10] */ + u32 rsv_46 : 2; /* [17:16] */ + u32 rxtlp_ramb_err : 2; /* [19:18] */ + u32 upitf_rsp_ram_erraddr : 4; /* [23:20] */ + u32 upitf_rsp_ram_err : 2; /* [25:24] */ + u32 rsv_47 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_dbg1_u; + +/* Define the union csr_up_mem_dbg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_rbdatfifo_ram_erraddr : 5; /* [4:0] */ + u32 rsv_48 : 1; /* [5] */ + u32 prt0_rbdatfifo_ram_err : 2; /* [7:6] */ + u32 prt1_rbdatfifo_ram_erraddr : 5; /* [12:8] */ + u32 rsv_49 : 1; /* [13] */ + u32 prt1_rbdatfifo_ram_err : 2; /* [15:14] */ + u32 prt2_rbdatfifo_ram_erraddr : 5; /* [20:16] */ + u32 rsv_50 : 1; /* [21] */ + u32 prt2_rbdatfifo_ram_err : 2; /* [23:22] */ + u32 prt3_rbdatfifo_ram_erraddr : 5; /* [28:24] */ + u32 rsv_51 : 1; /* [29] */ + u32 prt3_rbdatfifo_ram_err : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_dbg2_u; + +/* Define the union csr_up_mem_dbg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_txbuf_erraddr : 4; /* [3:0] */ + u32 prt0_txbuf_err : 2; /* [5:4] */ + u32 rsv_52 : 2; /* [7:6] */ + u32 prt1_txbuf_erraddr : 4; /* [11:8] */ + u32 prt1_txbuf_err : 2; /* [13:12] */ + u32 rsv_53 : 2; /* [15:14] */ + u32 prt2_txbuf_erraddr : 4; /* [19:16] */ + u32 prt2_txbuf_err : 2; /* [21:20] */ + u32 rsv_54 : 2; /* [23:22] */ + u32 prt3_txbuf_erraddr : 4; /* [27:24] */ + u32 prt3_txbuf_err : 2; /* [29:28] */ + u32 rsv_55 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_dbg3_u; + +/* Define the union csr_up_dbg_st0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_fifo_st : 4; /* [3:0] */ + u32 prt1_fifo_st : 4; /* [7:4] */ + u32 prt2_fifo_st : 4; /* [11:8] */ + u32 prt3_fifo_st : 4; /* [15:12] */ + u32 wrcmd_otd : 4; /* [19:16] */ + u32 cnt_wr_acc : 4; /* [23:20] */ + u32 rdcmd_otd : 4; /* [27:24] */ + u32 cnt_rd_acc : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_st0_u; + +/* Define the union csr_up_dbg_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 wr_lat_avg : 8; /* [7:0] */ + u32 wr_lat_max : 8; /* [15:8] */ + u32 rd_lat_avg : 8; /* [23:16] */ + u32 rd_lat_max : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_st1_u; + +/* Define the union csr_up_dbg_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_rxpctl_fifo_cnt : 6; /* [5:0] */ + u32 prt1_rxpctl_fifo_cnt : 6; /* [11:6] */ + u32 prt2_rxpctl_fifo_cnt : 6; /* [17:12] */ + u32 prt3_rxpctl_fifo_cnt : 6; /* [23:18] */ + u32 rsv_56 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_st2_u; + +/* Define the union csr_up_dbg_st3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txbuf_fifo_cnt : 20; /* [19:0] */ + u32 rxbuf_fifo_cnt : 7; /* [26:20] */ + u32 rsv_57 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_st3_u; + +/* Define the union csr_up_mem_dbg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_rxpctl_mb_ram_erraddr : 4; /* [3:0] */ + u32 prt0_rxpctl_mb_ram_err : 2; /* [5:4] */ + u32 rsv_58 : 2; /* [7:6] */ + u32 prt1_rxpctl_mb_ram_erraddr : 4; /* [11:8] */ + u32 prt1_rxpctl_mb_ram_err : 2; /* [13:12] */ + u32 rsv_59 : 2; /* [15:14] */ + u32 prt2_rxpctl_mb_ram_erraddr : 4; /* [19:16] */ + u32 prt2_rxpctl_mb_ram_err : 2; /* [21:20] */ + u32 rsv_60 : 2; /* [23:22] */ + u32 prt3_rxpctl_mb_ram_erraddr : 4; /* [27:24] */ + u32 prt3_rxpctl_mb_ram_err : 2; /* [29:28] */ + u32 rsv_61 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_mem_dbg4_u; + +/* Define the union csr_up_dbg_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prt0_mctprx_dropcnt : 8; /* [7:0] */ + u32 prt1_mctprx_dropcnt : 8; /* [15:8] */ + u32 prt2_mctprx_dropcnt : 8; /* [23:16] */ + u32 prt3_mctprx_dropcnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_cnt0_u; + +/* Define the union csr_up_dbg_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 upitf_all_apb_cnt : 16; /* [15:0] */ + u32 upitf_csr_apb_cnt : 8; /* [23:16] */ + u32 upitf_cpi_apb_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_dbg_cnt1_u; + +/* Define the union csr_up_rx_mb_buf_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_mb_buf_len : 21; /* [20:0] */ + u32 rsv_62 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_mb_buf_len_u; + +/* Define the union csr_up_rx_mb_buf_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_mb_buf_ba : 26; /* [25:0] */ + u32 rsv_63 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_mb_buf_ba_u; + +/* Define the union csr_up_rx_mb_buf_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_mb_buf_ci : 22; /* [21:0] */ + u32 rsv_64 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_mb_buf_ci_u; + +/* Define the union csr_up_rx_mb_buf_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_rx_mb_buf_pi : 22; /* [21:0] */ + u32 rsv_65 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_rx_mb_buf_pi_u; + +/* Define the union csr_up_bar_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_bar_val : 3; /* [2:0] */ + u32 rsv_66 : 1; /* [3] */ + u32 msi_bar_val : 3; /* [6:4] */ + u32 rsv_67 : 1; /* [7] */ + u32 dbl_bar_val : 3; /* [10:8] */ + u32 rsv_68 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_bar_map_u; + +/* Define the union csr_up_acc_func_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_acc_func_idx : 12; /* [11:0] */ + u32 rsv_69 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_acc_func_idx_u; + +/* Define the union csr_up_int_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_pcie_int_sts : 5; /* [4:0] */ + u32 ucpu_aeq_drop_int_sts : 1; /* [5] */ + u32 octl_ecc_err_int_sts : 1; /* [6] */ + u32 octl_ecc_merr_int_sts : 1; /* [7] */ + u32 octl_nonfatal_err_int_sts : 1; /* [8] */ + u32 octl_fatal_err_int_sts : 1; /* [9] */ + u32 dma_ecc_err_int_sts : 1; /* [10] */ + u32 dma_ecc_merr_int_sts : 1; /* [11] */ + u32 dma_nonfatal_err_int_sts : 1; /* [12] */ + u32 dma_fatal_err_int_sts : 1; /* [13] */ + u32 rsv_70 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_status2_u; + +/* Define the union csr_up_int_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_pcie_int_en : 5; /* [4:0] */ + u32 ucpu_aeq_drop_int_en : 1; /* [5] */ + u32 octl_ecc_err_int_en : 1; /* [6] */ + u32 octl_ecc_merr_int_en : 1; /* [7] */ + u32 octl_nonfatal_err_int_en : 1; /* [8] */ + u32 octl_fatal_err_int_en : 1; /* [9] */ + u32 dma_ecc_err_int_en : 1; /* [10] */ + u32 dma_ecc_merr_int_en : 1; /* [11] */ + u32 dma_nonfatal_err_int_en : 1; /* [12] */ + u32 dma_fatal_err_int_en : 1; /* [13] */ + u32 rsv_71 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_int_ctl2_u; + +/* Define the union csr_up_vioaeq_otd_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_otd_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_otd_th_u; + +/* Define the union csr_up_vioaeq_otd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_otd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_otd_cnt_u; + +/* Define the union csr_up_vioaeq_otd_rec_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_otd_rec : 8; /* [7:0] */ + u32 rsv_72 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_otd_rec_u; + +/* Define the union csr_up_vioaeq_drop_rcd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_drop0_func : 12; /* [11:0] */ + u32 rsv_73 : 19; /* [30:12] */ + u32 ucpu_vioaeq_drop0_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_drop_rcd0_u; + +/* Define the union csr_up_vioaeq_drop_rcd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_drop1_func : 12; /* [11:0] */ + u32 rsv_74 : 19; /* [30:12] */ + u32 ucpu_vioaeq_drop1_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_drop_rcd1_u; + +/* Define the union csr_up_vioaeq_drop_rcd2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_drop2_func : 12; /* [11:0] */ + u32 rsv_75 : 19; /* [30:12] */ + u32 ucpu_vioaeq_drop2_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_drop_rcd2_u; + +/* Define the union csr_up_vioaeq_drop_rcd3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_vioaeq_drop3_func : 12; /* [11:0] */ + u32 rsv_76 : 19; /* [30:12] */ + u32 ucpu_vioaeq_drop3_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_vioaeq_drop_rcd3_u; + +/* Define the union csr_up_uncrt_err_dis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_uncrt_err_dis : 1; /* [0] */ + u32 rsv_77 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_up_uncrt_err_dis_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_up_pcie_status_u up_pcie_status; /* 0 */ + volatile csr_up_int_status_u up_int_status; /* 4 */ + volatile csr_up_int_ctl_u up_int_ctl; /* 8 */ + volatile csr_up_direct_access_lock_u up_direct_access_lock; /* C */ + volatile csr_up_aeq_len_u up_aeq_len; /* 10 */ + volatile csr_up_aeq_ba_u up_aeq_ba; /* 14 */ + volatile csr_up_aeq_ci_u up_aeq_ci; /* 18 */ + volatile csr_up_aeq_pi_u up_aeq_pi; /* 1C */ + volatile csr_up_rx_api_buf_len_u up_rx_api_buf_len; /* 20 */ + volatile csr_up_rx_api_buf_ba_u up_rx_api_buf_ba; /* 24 */ + volatile csr_up_rx_api_buf_ci_u up_rx_api_buf_ci; /* 28 */ + volatile csr_up_rx_api_buf_pi_u up_rx_api_buf_pi; /* 2C */ + volatile csr_up_tx_api_ctl_u up_tx_api_ctl; /* 30 */ + volatile csr_up_tx_api_ctl_vio_u up_tx_api_ctl_vio; /* 34 */ + volatile csr_up_rb_timeout_u up_rb_timeout; /* 38 */ + volatile csr_up_xfer_ctrl_u up_xfer_ctrl; /* 3C */ + volatile csr_up_tx_api_payload_u up_tx_api_payload[32]; /* 40 */ + volatile csr_up_int_coll_u up_int_coll; /* C8 */ + volatile csr_up_int_timeout_u up_int_timeout; /* CC */ + volatile csr_up_tlp_rx_len_u up_tlp_rx_len[4]; /* D0 */ + volatile csr_up_tlp_rx_ba_u up_tlp_rx_ba[4]; /* D4 */ + volatile csr_up_tlp_rx_ci_u up_tlp_rx_ci[4]; /* D8 */ + volatile csr_up_tlp_rx_pi_u up_tlp_rx_pi[4]; /* DC */ + volatile csr_up_tlp_tx_len_u up_tlp_tx_len[4]; /* E0 */ + volatile csr_up_tlp_tx_ba_u up_tlp_tx_ba[4]; /* E4 */ + volatile csr_up_tlp_tx_ci_u up_tlp_tx_ci[4]; /* E8 */ + volatile csr_up_tlp_tx_pi_u up_tlp_tx_pi[4]; /* EC */ + volatile csr_up_mctprx_len_u up_mctprx_len[4]; /* 150 */ + volatile csr_up_mctprx_ba_u up_mctprx_ba[4]; /* 154 */ + volatile csr_up_mctprx_ci_u up_mctprx_ci[4]; /* 158 */ + volatile csr_up_mctprx_pi_u up_mctprx_pi[4]; /* 15C */ + volatile csr_up_mctptx_len_u up_mctptx_len[4]; /* 160 */ + volatile csr_up_mctptx_ba_u up_mctptx_ba[4]; /* 164 */ + volatile csr_up_mctptx_ci_u up_mctptx_ci[4]; /* 168 */ + volatile csr_up_mctptx_pi_u up_mctptx_pi[4]; /* 16C */ + volatile csr_up_csr_ctl_u up_csr_ctl; /* 200 */ + volatile csr_up_csr_data0_u up_csr_data0; /* 204 */ + volatile csr_up_csr_data1_u up_csr_data1; /* 208 */ + volatile csr_up_api_rdat_u up_api_rdat[64]; /* 300 */ + volatile csr_up_mem_ctrl_u up_mem_ctrl; /* 400 */ + volatile csr_up_rb_dbgctl_u up_rb_dbgctl; /* 404 */ + volatile csr_up_rb_dbgdat0_u up_rb_dbgdat0; /* 408 */ + volatile csr_up_rb_dbgdat1_u up_rb_dbgdat1; /* 40C */ + volatile csr_up_fsm_dbg0_u up_fsm_dbg0; /* 410 */ + volatile csr_up_fsm_dbg1_u up_fsm_dbg1; /* 414 */ + volatile csr_up_fsm_dbg2_u up_fsm_dbg2; /* 418 */ + volatile csr_up_fsm_dbg3_u up_fsm_dbg3[4]; /* 420 */ + volatile csr_up_mem_dbg0_u up_mem_dbg0; /* 430 */ + volatile csr_up_mem_dbg1_u up_mem_dbg1; /* 434 */ + volatile csr_up_mem_dbg2_u up_mem_dbg2; /* 438 */ + volatile csr_up_mem_dbg3_u up_mem_dbg3; /* 43C */ + volatile csr_up_dbg_st0_u up_dbg_st0; /* 440 */ + volatile csr_up_dbg_st1_u up_dbg_st1; /* 444 */ + volatile csr_up_dbg_st2_u up_dbg_st2; /* 448 */ + volatile csr_up_dbg_st3_u up_dbg_st3; /* 44C */ + volatile csr_up_mem_dbg4_u up_mem_dbg4; /* 450 */ + volatile csr_up_dbg_cnt0_u up_dbg_cnt0; /* 460 */ + volatile csr_up_dbg_cnt1_u up_dbg_cnt1; /* 464 */ + volatile csr_up_rx_mb_buf_len_u up_rx_mb_buf_len; /* 470 */ + volatile csr_up_rx_mb_buf_ba_u up_rx_mb_buf_ba; /* 474 */ + volatile csr_up_rx_mb_buf_ci_u up_rx_mb_buf_ci; /* 478 */ + volatile csr_up_rx_mb_buf_pi_u up_rx_mb_buf_pi; /* 47C */ + volatile csr_up_bar_map_u up_bar_map; /* 480 */ + volatile csr_up_acc_func_idx_u up_acc_func_idx; /* 484 */ + volatile csr_up_int_status2_u up_int_status2; /* 490 */ + volatile csr_up_int_ctl2_u up_int_ctl2; /* 494 */ + volatile csr_up_vioaeq_otd_th_u up_vioaeq_otd_th; /* 4A0 */ + volatile csr_up_vioaeq_otd_cnt_u up_vioaeq_otd_cnt; /* 4A4 */ + volatile csr_up_vioaeq_otd_rec_u up_vioaeq_otd_rec; /* 4A8 */ + volatile csr_up_vioaeq_drop_rcd0_u up_vioaeq_drop_rcd0; /* 4B0 */ + volatile csr_up_vioaeq_drop_rcd1_u up_vioaeq_drop_rcd1; /* 4B4 */ + volatile csr_up_vioaeq_drop_rcd2_u up_vioaeq_drop_rcd2; /* 4B8 */ + volatile csr_up_vioaeq_drop_rcd3_u up_vioaeq_drop_rcd3; /* 4BC */ + volatile csr_up_uncrt_err_dis_u up_uncrt_err_dis; /* 4C0 */ +} S_up_itf_csr_REGS_TYPE; + +/* Declare the struct pointor of the module up_itf_csr */ +extern volatile S_up_itf_csr_REGS_TYPE *gopup_itf_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetUP_PCIE_STATUS_ucpu_pcie_link(unsigned int uucpu_pcie_link); +int iSetUP_PCIE_STATUS_ucpu_ini_sts(unsigned int uucpu_ini_sts); +int iSetUP_INT_STATUS_ucpu_aeq_int_sts(unsigned int uucpu_aeq_int_sts); +int iSetUP_INT_STATUS_ucpu_rx_api_int_sts(unsigned int uucpu_rx_api_int_sts); +int iSetUP_INT_STATUS_ucpu_mb_int_sts(unsigned int uucpu_mb_int_sts); +int iSetUP_INT_STATUS_ucpu_mctprx_int_sts(unsigned int uucpu_mctprx_int_sts); +int iSetUP_INT_STATUS_ucpu_mctptx_int_sts(unsigned int uucpu_mctptx_int_sts); +int iSetUP_INT_STATUS_ucpu_tlprx_int_sts(unsigned int uucpu_tlprx_int_sts); +int iSetUP_INT_STATUS_ucpu_tlptx_int_sts(unsigned int uucpu_tlptx_int_sts); +int iSetUP_INT_STATUS_ucpu_clprx_int_sts(unsigned int uucpu_clprx_int_sts); +int iSetUP_INT_STATUS_ucpu_crt_err(unsigned int uucpu_crt_err); +int iSetUP_INT_STATUS_ucpu_uncrt_err(unsigned int uucpu_uncrt_err); +int iSetUP_INT_STATUS_axi_bus_err(unsigned int uaxi_bus_err); +int iSetUP_INT_STATUS_cpi_fatal_err(unsigned int ucpi_fatal_err); +int iSetUP_INT_STATUS_cpi_nonfatal_err(unsigned int ucpi_nonfatal_err); +int iSetUP_INT_STATUS_cpi_table_ecc_serr(unsigned int ucpi_table_ecc_serr); +int iSetUP_INT_STATUS_host_mpu_notify_int_sts(unsigned int uhost_mpu_notify_int_sts); +int iSetUP_INT_CTL_ucpu_aeq_int_en(unsigned int uucpu_aeq_int_en); +int iSetUP_INT_CTL_ucpu_rx_api_int_en(unsigned int uucpu_rx_api_int_en); +int iSetUP_INT_CTL_ucpu_mb_int_en(unsigned int uucpu_mb_int_en); +int iSetUP_INT_CTL_ucpu_mctprx_int_en(unsigned int uucpu_mctprx_int_en); +int iSetUP_INT_CTL_ucpu_mctptx_int_en(unsigned int uucpu_mctptx_int_en); +int iSetUP_INT_CTL_ucpu_tlprx_int_en(unsigned int uucpu_tlprx_int_en); +int iSetUP_INT_CTL_ucpu_tlptx_int_en(unsigned int uucpu_tlptx_int_en); +int iSetUP_INT_CTL_ucpu_clprx_int_en(unsigned int uucpu_clprx_int_en); +int iSetUP_INT_CTL_ucpu_crt_int_en(unsigned int uucpu_crt_int_en); +int iSetUP_INT_CTL_ucpu_uncrt_int_en(unsigned int uucpu_uncrt_int_en); +int iSetUP_INT_CTL_axi_bus_err_int_en(unsigned int uaxi_bus_err_int_en); +int iSetUP_INT_CTL_cpi_fatal_err_en(unsigned int ucpi_fatal_err_en); +int iSetUP_INT_CTL_cpi_nonfatal_err_en(unsigned int ucpi_nonfatal_err_en); +int iSetUP_INT_CTL_cpi_table_ecc_serr_en(unsigned int ucpi_table_ecc_serr_en); +int iSetUP_INT_CTL_host_mpu_notify_int_en(unsigned int uhost_mpu_notify_int_en); +int iSetUP_DIRECT_ACCESS_LOCK_ucpu_dir_acc_lck(unsigned int uucpu_dir_acc_lck); +int iSetUP_AEQ_LEN_ucpu_aeq_len(unsigned int uucpu_aeq_len); +int iSetUP_AEQ_BA_ucpu_aeq_ba(unsigned int uucpu_aeq_ba); +int iSetUP_AEQ_CI_ucpu_aeq_ci(unsigned int uucpu_aeq_ci); +int iSetUP_AEQ_PI_ucpu_aeq_pi(unsigned int uucpu_aeq_pi); +int iSetUP_RX_API_BUF_LEN_ucpu_rx_api_buf_len(unsigned int uucpu_rx_api_buf_len); +int iSetUP_RX_API_BUF_BA_ucpu_rx_api_buf_ba(unsigned int uucpu_rx_api_buf_ba); +int iSetUP_RX_API_BUF_CI_ucpu_rx_api_buf_ci(unsigned int uucpu_rx_api_buf_ci); +int iSetUP_RX_API_BUF_PI_ucpu_rx_api_buf_pi(unsigned int uucpu_rx_api_buf_pi); +int iSetUP_TX_API_CTL_ucpu_tx_api_dest(unsigned int uucpu_tx_api_dest); +int iSetUP_TX_API_CTL_ucpu_tx_api_code(unsigned int uucpu_tx_api_code); +int iSetUP_TX_API_CTL_op_type(unsigned int uop_type); +int iSetUP_TX_API_CTL_ucpu_tx_api_len(unsigned int uucpu_tx_api_len); +int iSetUP_TX_API_CTL_ucpu_api_rsp_len(unsigned int uucpu_api_rsp_len); +int iSetUP_TX_API_CTL_src_tag_l(unsigned int usrc_tag_l); +int iSetUP_TX_API_CTL_status(unsigned int ustatus); +int iSetUP_TX_API_CTL_ucpu_tx_api_issue(unsigned int uucpu_tx_api_issue); +int iSetUP_TX_API_CTL_VIO_up_tx_api_thread_id(unsigned int uup_tx_api_thread_id); +int iSetUP_TX_API_CTL_VIO_up_tx_api_vio(unsigned int uup_tx_api_vio); +int iSetUP_TX_API_CTL_VIO_up_tx_api_nvme(unsigned int uup_tx_api_nvme); +int iSetUP_TX_API_CTL_VIO_up_tx_rsvd_field(unsigned int uup_tx_rsvd_field); +int iSetUP_RB_TIMEOUT_up_aeq_timeout(unsigned int uup_aeq_timeout); +int iSetUP_RB_TIMEOUT_up_rb_timeout(unsigned int uup_rb_timeout); +int iSetUP_RB_TIMEOUT_up_mctp_timeout_off(unsigned int uup_mctp_timeout_off); +int iSetUP_RB_TIMEOUT_up_mb_timeout_off(unsigned int uup_mb_timeout_off); +int iSetUP_XFER_CTRL_xcmd_otd(unsigned int uxcmd_otd); +int iSetUP_XFER_CTRL_tlp_restart(unsigned int utlp_restart); +int iSetUP_XFER_CTRL_apiram_init_start(unsigned int uapiram_init_start); +int iSetUP_XFER_CTRL_apiram_init_done(unsigned int uapiram_init_done); +int iSetUP_TX_API_PAYLOAD_ucpu_tx_api_payload(unsigned int uucpu_tx_api_payload); +int iSetUP_INT_COLL_ucpu_int_coll(unsigned int uucpu_int_coll); +int iSetUP_INT_TIMEOUT_ucpu_int_timeout(unsigned int uucpu_int_timeout); +int iSetUP_TLP_RX_LEN_ucpu_port_tlprx_len(unsigned int uucpu_port_tlprx_len); +int iSetUP_TLP_RX_BA_ucpu_port_tlprx_ba(unsigned int uucpu_port_tlprx_ba); +int iSetUP_TLP_RX_CI_ucpu_port_tlprx_ci(unsigned int uucpu_port_tlprx_ci); +int iSetUP_TLP_RX_PI_ucpu_port_tlprx_pi(unsigned int uucpu_port_tlprx_pi); +int iSetUP_TLP_TX_LEN_ucpu_port_tlptx_len(unsigned int uucpu_port_tlptx_len); +int iSetUP_TLP_TX_BA_ucpu_port_tlptx_ba(unsigned int uucpu_port_tlptx_ba); +int iSetUP_TLP_TX_CI_ucpu_port_tlptx_ci(unsigned int uucpu_port_tlptx_ci); +int iSetUP_TLP_TX_PI_ucpu_port_tlptx_pi(unsigned int uucpu_port_tlptx_pi); +int iSetUP_MCTPRX_LEN_ucpu_port_mctprx_len(unsigned int uucpu_port_mctprx_len); +int iSetUP_MCTPRX_BA_ucpu_port_mctprx_ba(unsigned int uucpu_port_mctprx_ba); +int iSetUP_MCTPRX_CI_ucpu_port_mctprx_ci(unsigned int uucpu_port_mctprx_ci); +int iSetUP_MCTPRX_PI_ucpu_port_mctprx_pi(unsigned int uucpu_port_mctprx_pi); +int iSetUP_MCTPTX_LEN_ucpu_port_mctptx_len(unsigned int uucpu_port_mctptx_len); +int iSetUP_MCTPTX_BA_ucpu_port_mctptx_ba(unsigned int uucpu_port_mctptx_ba); +int iSetUP_MCTPTX_CI_ucpu_port_mctptx_ci(unsigned int uucpu_port_mctptx_ci); +int iSetUP_MCTPTX_PI_ucpu_port_mctptx_pi(unsigned int uucpu_port_mctptx_pi); +int iSetUP_CSR_CTL_ucpu_acc_csr_node_addr(unsigned int uucpu_acc_csr_node_addr); +int iSetUP_CSR_CTL_ucpu_acc_csr_status(unsigned int uucpu_acc_csr_status); +int iSetUP_CSR_CTL_ucpu_acc_csr_op_code(unsigned int uucpu_acc_csr_op_code); +int iSetUP_CSR_CTL_ucpu_acc_csr_size(unsigned int uucpu_acc_csr_size); +int iSetUP_CSR_CTL_ucpu_acc_csr_issue(unsigned int uucpu_acc_csr_issue); +int iSetUP_CSR_DATA0_ucpu_acc_csr_wdat_h(unsigned int uucpu_acc_csr_wdat_h); +int iSetUP_CSR_DATA1_ucpu_acc_csr_wdat_l(unsigned int uucpu_acc_csr_wdat_l); +int iSetUP_API_RDAT_ucpu_api_rdat(unsigned int uucpu_api_rdat); +int iSetUP_MEM_CTRL_power_ctrl(unsigned int upower_ctrl); +int iSetUP_MEM_CTRL_spmem_tmod(unsigned int uspmem_tmod); +int iSetUP_MEM_CTRL_tpmem_tmod(unsigned int utpmem_tmod); +int iSetUP_RB_DBGCTL_rb_dbg_sel(unsigned int urb_dbg_sel); +int iSetUP_RB_DBGDAT0_pi_ci_acc(unsigned int upi_ci_acc); +int iSetUP_RB_DBGDAT1_rb_cnt(unsigned int urb_cnt); +int iSetUP_FSM_DBG0_rxbuf_cur_st(unsigned int urxbuf_cur_st); +int iSetUP_FSM_DBG0_aeq_cur_st(unsigned int uaeq_cur_st); +int iSetUP_FSM_DBG0_apirx_cur_st(unsigned int uapirx_cur_st); +int iSetUP_FSM_DBG0_apitx_cur_st(unsigned int uapitx_cur_st); +int iSetUP_FSM_DBG0_axi_bus_err(unsigned int uaxi_bus_err); +int iSetUP_FSM_DBG0_tlp_xfer_err(unsigned int utlp_xfer_err); +int iSetUP_FSM_DBG1_axixfer_cur_st(unsigned int uaxixfer_cur_st); +int iSetUP_FSM_DBG2_txbuf_cur_st(unsigned int utxbuf_cur_st); +int iSetUP_FSM_DBG3_clp_cur_st(unsigned int uclp_cur_st); +int iSetUP_FSM_DBG3_vpd_cur_st(unsigned int uvpd_cur_st); +int iSetUP_FSM_DBG3_mctprx_cur_st(unsigned int umctprx_cur_st); +int iSetUP_FSM_DBG3_rxtlp_cur_st(unsigned int urxtlp_cur_st); +int iSetUP_FSM_DBG3_txtlp_cur_st(unsigned int utxtlp_cur_st); +int iSetUP_MEM_DBG0_rxtlp_rama_errin(unsigned int urxtlp_rama_errin); +int iSetUP_MEM_DBG0_rxtlp_ramb_errin(unsigned int urxtlp_ramb_errin); +int iSetUP_MEM_DBG0_upitf_rsp_ram_errin(unsigned int uupitf_rsp_ram_errin); +int iSetUP_MEM_DBG0_prt0_rbdatfifo_ram_errin(unsigned int uprt0_rbdatfifo_ram_errin); +int iSetUP_MEM_DBG0_prt1_rbdatfifo_ram_errin(unsigned int uprt1_rbdatfifo_ram_errin); +int iSetUP_MEM_DBG0_prt2_rbdatfifo_ram_errin(unsigned int uprt2_rbdatfifo_ram_errin); +int iSetUP_MEM_DBG0_prt3_rbdatfifo_ram_errin(unsigned int uprt3_rbdatfifo_ram_errin); +int iSetUP_MEM_DBG0_prt0_txbuf_ram_errin(unsigned int uprt0_txbuf_ram_errin); +int iSetUP_MEM_DBG0_prt1_txbuf_ram_errin(unsigned int uprt1_txbuf_ram_errin); +int iSetUP_MEM_DBG0_prt2_txbuf_ram_errin(unsigned int uprt2_txbuf_ram_errin); +int iSetUP_MEM_DBG0_prt3_txbuf_ram_errin(unsigned int uprt3_txbuf_ram_errin); +int iSetUP_MEM_DBG0_axi_cnt_clr(unsigned int uaxi_cnt_clr); +int iSetUP_MEM_DBG0_prt0_rxpctl_mb_ram_errin(unsigned int uprt0_rxpctl_mb_ram_errin); +int iSetUP_MEM_DBG0_prt1_rxpctl_mb_ram_errin(unsigned int uprt1_rxpctl_mb_ram_errin); +int iSetUP_MEM_DBG0_prt2_rxpctl_mb_ram_errin(unsigned int uprt2_rxpctl_mb_ram_errin); +int iSetUP_MEM_DBG0_prt3_rxpctl_mb_ram_errin(unsigned int uprt3_rxpctl_mb_ram_errin); +int iSetUP_MEM_DBG1_rxtlp_rama_erraddr(unsigned int urxtlp_rama_erraddr); +int iSetUP_MEM_DBG1_rxtlp_rama_err(unsigned int urxtlp_rama_err); +int iSetUP_MEM_DBG1_rxtlp_ramb_erraddr(unsigned int urxtlp_ramb_erraddr); +int iSetUP_MEM_DBG1_rxtlp_ramb_err(unsigned int urxtlp_ramb_err); +int iSetUP_MEM_DBG1_upitf_rsp_ram_erraddr(unsigned int uupitf_rsp_ram_erraddr); +int iSetUP_MEM_DBG1_upitf_rsp_ram_err(unsigned int uupitf_rsp_ram_err); +int iSetUP_MEM_DBG2_prt0_rbdatfifo_ram_erraddr(unsigned int uprt0_rbdatfifo_ram_erraddr); +int iSetUP_MEM_DBG2_prt0_rbdatfifo_ram_err(unsigned int uprt0_rbdatfifo_ram_err); +int iSetUP_MEM_DBG2_prt1_rbdatfifo_ram_erraddr(unsigned int uprt1_rbdatfifo_ram_erraddr); +int iSetUP_MEM_DBG2_prt1_rbdatfifo_ram_err(unsigned int uprt1_rbdatfifo_ram_err); +int iSetUP_MEM_DBG2_prt2_rbdatfifo_ram_erraddr(unsigned int uprt2_rbdatfifo_ram_erraddr); +int iSetUP_MEM_DBG2_prt2_rbdatfifo_ram_err(unsigned int uprt2_rbdatfifo_ram_err); +int iSetUP_MEM_DBG2_prt3_rbdatfifo_ram_erraddr(unsigned int uprt3_rbdatfifo_ram_erraddr); +int iSetUP_MEM_DBG2_prt3_rbdatfifo_ram_err(unsigned int uprt3_rbdatfifo_ram_err); +int iSetUP_MEM_DBG3_prt0_txbuf_erraddr(unsigned int uprt0_txbuf_erraddr); +int iSetUP_MEM_DBG3_prt0_txbuf_err(unsigned int uprt0_txbuf_err); +int iSetUP_MEM_DBG3_prt1_txbuf_erraddr(unsigned int uprt1_txbuf_erraddr); +int iSetUP_MEM_DBG3_prt1_txbuf_err(unsigned int uprt1_txbuf_err); +int iSetUP_MEM_DBG3_prt2_txbuf_erraddr(unsigned int uprt2_txbuf_erraddr); +int iSetUP_MEM_DBG3_prt2_txbuf_err(unsigned int uprt2_txbuf_err); +int iSetUP_MEM_DBG3_prt3_txbuf_erraddr(unsigned int uprt3_txbuf_erraddr); +int iSetUP_MEM_DBG3_prt3_txbuf_err(unsigned int uprt3_txbuf_err); +int iSetUP_DBG_ST0_prt0_fifo_st(unsigned int uprt0_fifo_st); +int iSetUP_DBG_ST0_prt1_fifo_st(unsigned int uprt1_fifo_st); +int iSetUP_DBG_ST0_prt2_fifo_st(unsigned int uprt2_fifo_st); +int iSetUP_DBG_ST0_prt3_fifo_st(unsigned int uprt3_fifo_st); +int iSetUP_DBG_ST0_wrcmd_otd(unsigned int uwrcmd_otd); +int iSetUP_DBG_ST0_cnt_wr_acc(unsigned int ucnt_wr_acc); +int iSetUP_DBG_ST0_rdcmd_otd(unsigned int urdcmd_otd); +int iSetUP_DBG_ST0_cnt_rd_acc(unsigned int ucnt_rd_acc); +int iSetUP_DBG_ST1_wr_lat_avg(unsigned int uwr_lat_avg); +int iSetUP_DBG_ST1_wr_lat_max(unsigned int uwr_lat_max); +int iSetUP_DBG_ST1_rd_lat_avg(unsigned int urd_lat_avg); +int iSetUP_DBG_ST1_rd_lat_max(unsigned int urd_lat_max); +int iSetUP_DBG_ST2_prt0_rxpctl_fifo_cnt(unsigned int uprt0_rxpctl_fifo_cnt); +int iSetUP_DBG_ST2_prt1_rxpctl_fifo_cnt(unsigned int uprt1_rxpctl_fifo_cnt); +int iSetUP_DBG_ST2_prt2_rxpctl_fifo_cnt(unsigned int uprt2_rxpctl_fifo_cnt); +int iSetUP_DBG_ST2_prt3_rxpctl_fifo_cnt(unsigned int uprt3_rxpctl_fifo_cnt); +int iSetUP_DBG_ST3_txbuf_fifo_cnt(unsigned int utxbuf_fifo_cnt); +int iSetUP_DBG_ST3_rxbuf_fifo_cnt(unsigned int urxbuf_fifo_cnt); +int iSetUP_MEM_DBG4_prt0_rxpctl_mb_ram_erraddr(unsigned int uprt0_rxpctl_mb_ram_erraddr); +int iSetUP_MEM_DBG4_prt0_rxpctl_mb_ram_err(unsigned int uprt0_rxpctl_mb_ram_err); +int iSetUP_MEM_DBG4_prt1_rxpctl_mb_ram_erraddr(unsigned int uprt1_rxpctl_mb_ram_erraddr); +int iSetUP_MEM_DBG4_prt1_rxpctl_mb_ram_err(unsigned int uprt1_rxpctl_mb_ram_err); +int iSetUP_MEM_DBG4_prt2_rxpctl_mb_ram_erraddr(unsigned int uprt2_rxpctl_mb_ram_erraddr); +int iSetUP_MEM_DBG4_prt2_rxpctl_mb_ram_err(unsigned int uprt2_rxpctl_mb_ram_err); +int iSetUP_MEM_DBG4_prt3_rxpctl_mb_ram_erraddr(unsigned int uprt3_rxpctl_mb_ram_erraddr); +int iSetUP_MEM_DBG4_prt3_rxpctl_mb_ram_err(unsigned int uprt3_rxpctl_mb_ram_err); +int iSetUP_DBG_CNT0_prt0_mctprx_dropcnt(unsigned int uprt0_mctprx_dropcnt); +int iSetUP_DBG_CNT0_prt1_mctprx_dropcnt(unsigned int uprt1_mctprx_dropcnt); +int iSetUP_DBG_CNT0_prt2_mctprx_dropcnt(unsigned int uprt2_mctprx_dropcnt); +int iSetUP_DBG_CNT0_prt3_mctprx_dropcnt(unsigned int uprt3_mctprx_dropcnt); +int iSetUP_DBG_CNT1_upitf_all_apb_cnt(unsigned int uupitf_all_apb_cnt); +int iSetUP_DBG_CNT1_upitf_csr_apb_cnt(unsigned int uupitf_csr_apb_cnt); +int iSetUP_DBG_CNT1_upitf_cpi_apb_cnt(unsigned int uupitf_cpi_apb_cnt); +int iSetUP_RX_MB_BUF_LEN_ucpu_rx_mb_buf_len(unsigned int uucpu_rx_mb_buf_len); +int iSetUP_RX_MB_BUF_BA_ucpu_rx_mb_buf_ba(unsigned int uucpu_rx_mb_buf_ba); +int iSetUP_RX_MB_BUF_CI_ucpu_rx_mb_buf_ci(unsigned int uucpu_rx_mb_buf_ci); +int iSetUP_RX_MB_BUF_PI_ucpu_rx_mb_buf_pi(unsigned int uucpu_rx_mb_buf_pi); +int iSetUP_BAR_MAP_csr_bar_val(unsigned int ucsr_bar_val); +int iSetUP_BAR_MAP_msi_bar_val(unsigned int umsi_bar_val); +int iSetUP_BAR_MAP_dbl_bar_val(unsigned int udbl_bar_val); +int iSetUP_ACC_FUNC_IDX_ucpu_acc_func_idx(unsigned int uucpu_acc_func_idx); +int iSetUP_INT_STATUS2_ucpu_pcie_int_sts(unsigned int uucpu_pcie_int_sts); +int iSetUP_INT_STATUS2_ucpu_aeq_drop_int_sts(unsigned int uucpu_aeq_drop_int_sts); +int iSetUP_INT_STATUS2_octl_ecc_err_int_sts(unsigned int uoctl_ecc_err_int_sts); +int iSetUP_INT_STATUS2_octl_ecc_merr_int_sts(unsigned int uoctl_ecc_merr_int_sts); +int iSetUP_INT_STATUS2_octl_nonfatal_err_int_sts(unsigned int uoctl_nonfatal_err_int_sts); +int iSetUP_INT_STATUS2_octl_fatal_err_int_sts(unsigned int uoctl_fatal_err_int_sts); +int iSetUP_INT_STATUS2_dma_ecc_err_int_sts(unsigned int udma_ecc_err_int_sts); +int iSetUP_INT_STATUS2_dma_ecc_merr_int_sts(unsigned int udma_ecc_merr_int_sts); +int iSetUP_INT_STATUS2_dma_nonfatal_err_int_sts(unsigned int udma_nonfatal_err_int_sts); +int iSetUP_INT_STATUS2_dma_fatal_err_int_sts(unsigned int udma_fatal_err_int_sts); +int iSetUP_INT_CTL2_ucpu_pcie_int_en(unsigned int uucpu_pcie_int_en); +int iSetUP_INT_CTL2_ucpu_aeq_drop_int_en(unsigned int uucpu_aeq_drop_int_en); +int iSetUP_INT_CTL2_octl_ecc_err_int_en(unsigned int uoctl_ecc_err_int_en); +int iSetUP_INT_CTL2_octl_ecc_merr_int_en(unsigned int uoctl_ecc_merr_int_en); +int iSetUP_INT_CTL2_octl_nonfatal_err_int_en(unsigned int uoctl_nonfatal_err_int_en); +int iSetUP_INT_CTL2_octl_fatal_err_int_en(unsigned int uoctl_fatal_err_int_en); +int iSetUP_INT_CTL2_dma_ecc_err_int_en(unsigned int udma_ecc_err_int_en); +int iSetUP_INT_CTL2_dma_ecc_merr_int_en(unsigned int udma_ecc_merr_int_en); +int iSetUP_INT_CTL2_dma_nonfatal_err_int_en(unsigned int udma_nonfatal_err_int_en); +int iSetUP_INT_CTL2_dma_fatal_err_int_en(unsigned int udma_fatal_err_int_en); +int iSetUP_VIOAEQ_OTD_TH_ucpu_vioaeq_otd_th(unsigned int uucpu_vioaeq_otd_th); +int iSetUP_VIOAEQ_OTD_CNT_ucpu_vioaeq_otd_cnt(unsigned int uucpu_vioaeq_otd_cnt); +int iSetUP_VIOAEQ_OTD_REC_ucpu_vioaeq_otd_rec(unsigned int uucpu_vioaeq_otd_rec); +int iSetUP_VIOAEQ_DROP_RCD0_ucpu_vioaeq_drop0_func(unsigned int uucpu_vioaeq_drop0_func); +int iSetUP_VIOAEQ_DROP_RCD0_ucpu_vioaeq_drop0_vld(unsigned int uucpu_vioaeq_drop0_vld); +int iSetUP_VIOAEQ_DROP_RCD1_ucpu_vioaeq_drop1_func(unsigned int uucpu_vioaeq_drop1_func); +int iSetUP_VIOAEQ_DROP_RCD1_ucpu_vioaeq_drop1_vld(unsigned int uucpu_vioaeq_drop1_vld); +int iSetUP_VIOAEQ_DROP_RCD2_ucpu_vioaeq_drop2_func(unsigned int uucpu_vioaeq_drop2_func); +int iSetUP_VIOAEQ_DROP_RCD2_ucpu_vioaeq_drop2_vld(unsigned int uucpu_vioaeq_drop2_vld); +int iSetUP_VIOAEQ_DROP_RCD3_ucpu_vioaeq_drop3_func(unsigned int uucpu_vioaeq_drop3_func); +int iSetUP_VIOAEQ_DROP_RCD3_ucpu_vioaeq_drop3_vld(unsigned int uucpu_vioaeq_drop3_vld); +int iSetUP_UNCRT_ERR_DIS_ucpu_uncrt_err_dis(unsigned int uucpu_uncrt_err_dis); + +/* Define the union csr_function_attribute0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_glb_func_idx : 12; /* [11:0] */ + u32 af_assoc_pf_idx : 5; /* [16:12] */ + u32 af_itf_idx : 3; /* [19:17] */ + u32 af_vf_in_pf : 8; /* [27:20] */ + u32 af_pf_or_vf : 1; /* [28] */ + u32 rsv_0 : 2; /* [30:29] */ + u32 af_att_lrn : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute0_u; + +/* Define the union csr_function_attribute1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ppf_election : 6; /* [5:0] */ + u32 rsv_1 : 2; /* [7:6] */ + u32 af_aeq_per_func : 2; /* [9:8] */ + u32 rsv_2 : 20; /* [29:10] */ + u32 af_up_ini_sts : 1; /* [30] */ + u32 af_pf_rst_sts : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute1_u; + +/* Define the union csr_function_attribute2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ceq_per_func : 9; /* [8:0] */ + u32 af_dma_attr_per_func : 3; /* [11:9] */ + u32 rsv_3 : 4; /* [15:12] */ + u32 af_int_per_func : 11; /* [26:16] */ + u32 rsv_4 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute2_u; + +/* Define the union csr_function_attribute3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_vf_offset_for_nxt_pf : 12; /* [11:0] */ + u32 rsv_5 : 4; /* [15:12] */ + u32 af_vf_offset_for_cur_pf : 12; /* [27:16] */ + u32 rsv_6 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute3_u; + +/* Define the union csr_function_attribute4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_dbl_flush : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute4_u; + +/* Define the union csr_function_attribute5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_outbnd_flush : 1; /* [0] */ + u32 rsv_8 : 3; /* [3:1] */ + u32 ap_outbnd_flush : 5; /* [8:4] */ + u32 rsv_9 : 3; /* [11:9] */ + u32 af_round_bit : 1; /* [12] */ + u32 rsv_10 : 3; /* [15:13] */ + u32 cpi_rcv_chip_err : 1; /* [16] */ + u32 rsv_11 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute5_u; + +/* Define the union csr_function_attribute6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_status : 16; /* [15:0] */ + u32 rsvd : 6; /* [21:16] */ + u32 msix_flex_en : 1; /* [22] */ + u32 q_num : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_attribute6_u; + +/* Define the union csr_function_tsk0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_simple_mb_tsk0_csr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_tsk0_u; + +/* Define the union csr_function_tsk1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_simple_mb_tsk1_csr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_tsk1_u; + +/* Define the union csr_function_tsk2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_simple_mb_tsk2_csr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_tsk2_u; + +/* Define the union csr_function_tsk3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_simple_mb_tsk3_csr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_tsk3_u; + +/* Define the union csr_func_remap_table_entr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 20; /* [19:0] */ + u32 af_bme_bit : 1; /* [20] */ + u32 rsv_13 : 10; /* [30:21] */ + u32 af_vld_bit : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_remap_table_entr_u; + +/* Define the union csr_func_aeq_ci_indir_wr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_simple_indir_ci : 21; /* [20:0] */ + u32 aeq_simple_indir_armed : 1; /* [21] */ + u32 rsv_14 : 8; /* [29:22] */ + u32 aeq_simple_indir_idx : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_aeq_ci_indir_wr_u; + +/* Define the union csr_func_ceq_ci_indir_wr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_simple_indir_ci : 21; /* [20:0] */ + u32 ceq_simple_indir_armed : 1; /* [21] */ + u32 rsv_15 : 2; /* [23:22] */ + u32 ceq_simple_indir_idx : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ceq_ci_indir_wr_u; + +/* Define the union csr_func_msi_clr_indir_wr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_resend_timer_clr : 1; /* [0] */ + u32 msi_int_msk_set : 1; /* [1] */ + u32 msi_int_msk_clr : 1; /* [2] */ + u32 msi_auto_msk_set : 1; /* [3] */ + u32 msi_auto_msk_clr : 1; /* [4] */ + u32 rsv_16 : 17; /* [21:5] */ + u32 msi_simple_indir_idx : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_msi_clr_indir_wr_u; + +/* Define the union csr_func_ppf_elect_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port0_ppf_elect : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ppf_elect_port0_u; + +/* Define the union csr_func_ppf_elect_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port1_ppf_elect : 6; /* [5:0] */ + u32 rsv_18 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ppf_elect_port1_u; + +/* Define the union csr_func_ppf_elect_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port2_ppf_elect : 6; /* [5:0] */ + u32 rsv_19 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ppf_elect_port2_u; + +/* Define the union csr_func_ppf_elect_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port3_ppf_elect : 6; /* [5:0] */ + u32 rsv_20 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ppf_elect_port3_u; + +/* Define the union csr_func_ppf_elect_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port4_ppf_elect : 6; /* [5:0] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_func_ppf_elect_port4_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_function_attribute0_u function_attribute0[2]; /* 0 */ + volatile csr_function_attribute1_u function_attribute1[2]; /* 4 */ + volatile csr_function_attribute2_u function_attribute2[2]; /* 8 */ + volatile csr_function_attribute3_u function_attribute3[2]; /* C */ + volatile csr_function_attribute4_u function_attribute4[2]; /* 10 */ + volatile csr_function_attribute5_u function_attribute5[2]; /* 14 */ + volatile csr_function_attribute6_u function_attribute6[2]; /* 18 */ + volatile csr_function_tsk0_u function_tsk0[32]; /* 20 */ + volatile csr_function_tsk1_u function_tsk1[32]; /* 24 */ + volatile csr_function_tsk2_u function_tsk2[32]; /* 28 */ + volatile csr_function_tsk3_u function_tsk3[32]; /* 2C */ + volatile csr_func_remap_table_entr_u func_remap_table_entr[2]; /* 30 */ + volatile csr_func_aeq_ci_indir_wr_u func_aeq_ci_indir_wr; /* 50 */ + volatile csr_func_ceq_ci_indir_wr_u func_ceq_ci_indir_wr; /* 54 */ + volatile csr_func_msi_clr_indir_wr_u func_msi_clr_indir_wr; /* 58 */ + volatile csr_func_ppf_elect_port0_u func_ppf_elect_port0; /* 60 */ + volatile csr_func_ppf_elect_port1_u func_ppf_elect_port1; /* 64 */ + volatile csr_func_ppf_elect_port2_u func_ppf_elect_port2; /* 68 */ + volatile csr_func_ppf_elect_port3_u func_ppf_elect_port3; /* 6C */ + volatile csr_func_ppf_elect_port4_u func_ppf_elect_port4; /* 70 */ +} S_func_com_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_com_csr */ +extern volatile S_func_com_csr_REGS_TYPE *gopfunc_com_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetFUNCTION_ATTRIBUTE0_af_glb_func_idx(unsigned int uaf_glb_func_idx); +int iSetFUNCTION_ATTRIBUTE0_af_assoc_pf_idx(unsigned int uaf_assoc_pf_idx); +int iSetFUNCTION_ATTRIBUTE0_af_itf_idx(unsigned int uaf_itf_idx); +int iSetFUNCTION_ATTRIBUTE0_af_vf_in_pf(unsigned int uaf_vf_in_pf); +int iSetFUNCTION_ATTRIBUTE0_af_pf_or_vf(unsigned int uaf_pf_or_vf); +int iSetFUNCTION_ATTRIBUTE0_af_att_lrn(unsigned int uaf_att_lrn); +int iSetFUNCTION_ATTRIBUTE1_af_ppf_election(unsigned int uaf_ppf_election); +int iSetFUNCTION_ATTRIBUTE1_af_aeq_per_func(unsigned int uaf_aeq_per_func); +int iSetFUNCTION_ATTRIBUTE1_af_up_ini_sts(unsigned int uaf_up_ini_sts); +int iSetFUNCTION_ATTRIBUTE1_af_pf_rst_sts(unsigned int uaf_pf_rst_sts); +int iSetFUNCTION_ATTRIBUTE2_af_ceq_per_func(unsigned int uaf_ceq_per_func); +int iSetFUNCTION_ATTRIBUTE2_af_dma_attr_per_func(unsigned int uaf_dma_attr_per_func); +int iSetFUNCTION_ATTRIBUTE2_af_int_per_func(unsigned int uaf_int_per_func); +int iSetFUNCTION_ATTRIBUTE3_af_vf_offset_for_nxt_pf(unsigned int uaf_vf_offset_for_nxt_pf); +int iSetFUNCTION_ATTRIBUTE3_af_vf_offset_for_cur_pf(unsigned int uaf_vf_offset_for_cur_pf); +int iSetFUNCTION_ATTRIBUTE4_af_dbl_flush(unsigned int uaf_dbl_flush); +int iSetFUNCTION_ATTRIBUTE5_af_outbnd_flush(unsigned int uaf_outbnd_flush); +int iSetFUNCTION_ATTRIBUTE5_ap_outbnd_flush(unsigned int uap_outbnd_flush); +int iSetFUNCTION_ATTRIBUTE5_af_round_bit(unsigned int uaf_round_bit); +int iSetFUNCTION_ATTRIBUTE5_cpi_rcv_chip_err(unsigned int ucpi_rcv_chip_err); +int iSetFUNCTION_ATTRIBUTE6_af_simple_mb_tsk_csr(unsigned int uaf_simple_mb_tsk_csr); +int iSetFUNCTION_TSK0_pf_simple_mb_tsk0_csr(unsigned int upf_simple_mb_tsk0_csr); +int iSetFUNCTION_TSK1_pf_simple_mb_tsk1_csr(unsigned int upf_simple_mb_tsk1_csr); +int iSetFUNCTION_TSK2_pf_simple_mb_tsk2_csr(unsigned int upf_simple_mb_tsk2_csr); +int iSetFUNCTION_TSK3_pf_simple_mb_tsk3_csr(unsigned int upf_simple_mb_tsk3_csr); +int iSetFUNC_REMAP_TABLE_ENTR_af_bme_bit(unsigned int uaf_bme_bit); +int iSetFUNC_REMAP_TABLE_ENTR_af_vld_bit(unsigned int uaf_vld_bit); +int iSetFUNC_AEQ_CI_INDIR_WR_aeq_simple_indir_ci(unsigned int uaeq_simple_indir_ci); +int iSetFUNC_AEQ_CI_INDIR_WR_aeq_simple_indir_armed(unsigned int uaeq_simple_indir_armed); +int iSetFUNC_AEQ_CI_INDIR_WR_aeq_simple_indir_idx(unsigned int uaeq_simple_indir_idx); +int iSetFUNC_CEQ_CI_INDIR_WR_ceq_simple_indir_ci(unsigned int uceq_simple_indir_ci); +int iSetFUNC_CEQ_CI_INDIR_WR_ceq_simple_indir_armed(unsigned int uceq_simple_indir_armed); +int iSetFUNC_CEQ_CI_INDIR_WR_ceq_simple_indir_idx(unsigned int uceq_simple_indir_idx); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_resend_timer_clr(unsigned int umsi_resend_timer_clr); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_int_msk_set(unsigned int umsi_int_msk_set); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_int_msk_clr(unsigned int umsi_int_msk_clr); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_auto_msk_set(unsigned int umsi_auto_msk_set); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_auto_msk_clr(unsigned int umsi_auto_msk_clr); +int iSetFUNC_MSI_CLR_INDIR_WR_msi_simple_indir_idx(unsigned int umsi_simple_indir_idx); +int iSetFUNC_PPF_ELECT_PORT0_port0_ppf_elect(unsigned int uport0_ppf_elect); +int iSetFUNC_PPF_ELECT_PORT1_port1_ppf_elect(unsigned int uport1_ppf_elect); +int iSetFUNC_PPF_ELECT_PORT2_port2_ppf_elect(unsigned int uport2_ppf_elect); +int iSetFUNC_PPF_ELECT_PORT3_port3_ppf_elect(unsigned int uport3_ppf_elect); +int iSetFUNC_PPF_ELECT_PORT4_port4_ppf_elect(unsigned int uport4_ppf_elect); + +/* Define the union csr_mailbox_dat_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_0_u; + +/* Define the union csr_mailbox_dat_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_1_u; + +/* Define the union csr_mailbox_dat_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_2_u; + +/* Define the union csr_mailbox_dat_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_3_u; + +/* Define the union csr_mailbox_dat_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_4_u; + +/* Define the union csr_mailbox_dat_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_5_u; + +/* Define the union csr_mailbox_dat_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_6_u; + +/* Define the union csr_mailbox_dat_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_7_u; + +/* Define the union csr_mailbox_dat_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_8_u; + +/* Define the union csr_mailbox_dat_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_9_u; + +/* Define the union csr_mailbox_dat_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_10_u; + +/* Define the union csr_mailbox_dat_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_11_u; + +/* Define the union csr_mailbox_dat_12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_12_u; + +/* Define the union csr_mailbox_dat_13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_13_u; + +/* Define the union csr_mailbox_dat_14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_14_u; + +/* Define the union csr_mailbox_dat_15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_dat_15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_dat_15_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_mailbox_dat_0_u mailbox_dat_0[2]; /* 0 */ + volatile csr_mailbox_dat_1_u mailbox_dat_1[2]; /* 4 */ + volatile csr_mailbox_dat_2_u mailbox_dat_2[2]; /* 8 */ + volatile csr_mailbox_dat_3_u mailbox_dat_3[2]; /* C */ + volatile csr_mailbox_dat_4_u mailbox_dat_4[2]; /* 10 */ + volatile csr_mailbox_dat_5_u mailbox_dat_5[2]; /* 14 */ + volatile csr_mailbox_dat_6_u mailbox_dat_6[2]; /* 18 */ + volatile csr_mailbox_dat_7_u mailbox_dat_7[2]; /* 1C */ + volatile csr_mailbox_dat_8_u mailbox_dat_8[2]; /* 20 */ + volatile csr_mailbox_dat_9_u mailbox_dat_9[2]; /* 24 */ + volatile csr_mailbox_dat_10_u mailbox_dat_10[2]; /* 28 */ + volatile csr_mailbox_dat_11_u mailbox_dat_11[2]; /* 2C */ + volatile csr_mailbox_dat_12_u mailbox_dat_12[2]; /* 30 */ + volatile csr_mailbox_dat_13_u mailbox_dat_13[2]; /* 34 */ + volatile csr_mailbox_dat_14_u mailbox_dat_14[2]; /* 38 */ + volatile csr_mailbox_dat_15_u mailbox_dat_15[2]; /* 3C */ +} S_func_mb_dat_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_mb_dat_csr */ +extern volatile S_func_mb_dat_csr_REGS_TYPE *gopfunc_mb_dat_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetMAILBOX_DAT_0_af_mb_dat_0(unsigned int uaf_mb_dat_0); +int iSetMAILBOX_DAT_1_af_mb_dat_1(unsigned int uaf_mb_dat_1); +int iSetMAILBOX_DAT_2_af_mb_dat_2(unsigned int uaf_mb_dat_2); +int iSetMAILBOX_DAT_3_af_mb_dat_3(unsigned int uaf_mb_dat_3); +int iSetMAILBOX_DAT_4_af_mb_dat_4(unsigned int uaf_mb_dat_4); +int iSetMAILBOX_DAT_5_af_mb_dat_5(unsigned int uaf_mb_dat_5); +int iSetMAILBOX_DAT_6_af_mb_dat_6(unsigned int uaf_mb_dat_6); +int iSetMAILBOX_DAT_7_af_mb_dat_7(unsigned int uaf_mb_dat_7); +int iSetMAILBOX_DAT_8_af_mb_dat_8(unsigned int uaf_mb_dat_8); +int iSetMAILBOX_DAT_9_af_mb_dat_9(unsigned int uaf_mb_dat_9); +int iSetMAILBOX_DAT_10_af_mb_dat_10(unsigned int uaf_mb_dat_10); +int iSetMAILBOX_DAT_11_af_mb_dat_11(unsigned int uaf_mb_dat_11); +int iSetMAILBOX_DAT_12_af_mb_dat_12(unsigned int uaf_mb_dat_12); +int iSetMAILBOX_DAT_13_af_mb_dat_13(unsigned int uaf_mb_dat_13); +int iSetMAILBOX_DAT_14_af_mb_dat_14(unsigned int uaf_mb_dat_14); +int iSetMAILBOX_DAT_15_af_mb_dat_15(unsigned int uaf_mb_dat_15); + +/* Define the union csr_mailbox_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_trigger_aeqe : 1; /* [0] */ + u32 af_mb_tx_req : 1; /* [1] */ + u32 rsv_0 : 14; /* [15:2] */ + u32 af_mb_dest_func : 13; /* [28:16] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_control_u; + +/* Define the union csr_mailbox_int_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 10; /* [9:0] */ + u32 af_mb_dest_aeqn : 2; /* [11:10] */ + u32 af_mb_src_aeqn : 2; /* [13:12] */ + u32 af_mb_sts_dma_attr_offset : 6; /* [19:14] */ + u32 af_mb_tx_size : 5; /* [24:20] */ + u32 af_mb_sts_dma_so_ro : 2; /* [26:25] */ + u32 rsv_3 : 1; /* [27] */ + u32 af_mb_wr_sts_en : 1; /* [28] */ + u32 af_mb_tx_sts : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_int_offset_u; + +/* Define the union csr_mailbox_result_back_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_wr_sts_addrh : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_result_back_h_u; + +/* Define the union csr_mailbox_result_back_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_mb_wr_sts_addrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mailbox_result_back_l_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_mailbox_control_u mailbox_control[2]; /* 0 */ + volatile csr_mailbox_int_offset_u mailbox_int_offset[2]; /* 4 */ + volatile csr_mailbox_result_back_h_u mailbox_result_back_h[2]; /* 8 */ + volatile csr_mailbox_result_back_l_u mailbox_result_back_l[2]; /* C */ +} S_func_mb_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_mb_csr */ +extern volatile S_func_mb_csr_REGS_TYPE *gopfunc_mb_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetMAILBOX_CONTROL_af_mb_trigger_aeqe(unsigned int uaf_mb_trigger_aeqe); +int iSetMAILBOX_CONTROL_af_mb_tx_req(unsigned int uaf_mb_tx_req); +int iSetMAILBOX_CONTROL_af_mb_dest_func(unsigned int uaf_mb_dest_func); +int iSetMAILBOX_INT_OFFSET_af_mb_dest_aeqn(unsigned int uaf_mb_dest_aeqn); +int iSetMAILBOX_INT_OFFSET_af_mb_src_aeqn(unsigned int uaf_mb_src_aeqn); +int iSetMAILBOX_INT_OFFSET_af_mb_sts_dma_attr_offset(unsigned int uaf_mb_sts_dma_attr_offset); +int iSetMAILBOX_INT_OFFSET_af_mb_tx_size(unsigned int uaf_mb_tx_size); +int iSetMAILBOX_INT_OFFSET_af_mb_sts_dma_so_ro(unsigned int uaf_mb_sts_dma_so_ro); +int iSetMAILBOX_INT_OFFSET_af_mb_wr_sts_en(unsigned int uaf_mb_wr_sts_en); +int iSetMAILBOX_INT_OFFSET_af_mb_tx_sts(unsigned int uaf_mb_tx_sts); +int iSetMAILBOX_RESULT_BACK_H_af_mb_wr_sts_addrh(unsigned int uaf_mb_wr_sts_addrh); +int iSetMAILBOX_RESULT_BACK_L_af_mb_wr_sts_addrl(unsigned int uaf_mb_wr_sts_addrl); + +/* Define the union csr_aeq_ctl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_aeq_int_offset : 10; /* [9:0] */ + u32 rsv_0 : 2; /* [11:10] */ + u32 af_aeq_dma_attr_offset : 6; /* [17:12] */ + u32 af_aeq_dma_so : 2; /* [19:18] */ + u32 af_aeq_port : 3; /* [22:20] */ + u32 rsv_1 : 8; /* [30:23] */ + u32 af_aeq_int_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_ctl_0_u; + +/* Define the union csr_aeq_ctl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_aeq_length : 21; /* [20:0] */ + u32 rsv_2 : 3; /* [23:21] */ + u32 af_aeqe_size : 2; /* [25:24] */ + u32 rsv_3 : 2; /* [27:26] */ + u32 af_aeq_page : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_ctl_1_u; + +/* Define the union csr_aeq_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_aeq_ci : 21; /* [20:0] */ + u32 rsv_4 : 10; /* [30:21] */ + u32 af_aeq_int_armed : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_ci_u; + +/* Define the union csr_aeq_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_aeq_pi : 21; /* [20:0] */ + u32 rsv_5 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_pi_u; + +/* Define the union csr_aeq_indir_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_indir_idx : 10; /* [9:0] */ + u32 rsv_6 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_indir_idx_u; + +/* Define the union csr_function_aeq_mtt0_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_mtt0_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt0_h_u; + +/* Define the union csr_function_aeq_mtt0_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_7 : 12; /* [11:0] */ + u32 aeq_mtt0_addr_l : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt0_l_u; + +/* Define the union csr_function_aeq_mtt1_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_mtt1_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt1_h_u; + +/* Define the union csr_function_aeq_mtt1_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_8 : 12; /* [11:0] */ + u32 aeq_mtt1_addr_l : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt1_l_u; + +/* Define the union csr_function_aeq_mtt2_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_mtt2_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt2_h_u; + +/* Define the union csr_function_aeq_mtt2_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 12; /* [11:0] */ + u32 aeq_mtt2_addr_l : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt2_l_u; + +/* Define the union csr_function_aeq_mtt3_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_mtt3_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt3_h_u; + +/* Define the union csr_function_aeq_mtt3_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_10 : 12; /* [11:0] */ + u32 aeq_mtt3_addr_l : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_aeq_mtt3_l_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_aeq_ctl_0_u aeq_ctl_0[2]; /* 0 */ + volatile csr_aeq_ctl_1_u aeq_ctl_1[2]; /* 4 */ + volatile csr_aeq_ci_u aeq_ci[2]; /* 8 */ + volatile csr_aeq_pi_u aeq_pi[2]; /* C */ + volatile csr_aeq_indir_idx_u aeq_indir_idx[2]; /* 10 */ + volatile csr_function_aeq_mtt0_h_u function_aeq_mtt0_h[2]; /* 40 */ + volatile csr_function_aeq_mtt0_l_u function_aeq_mtt0_l[2]; /* 44 */ + volatile csr_function_aeq_mtt1_h_u function_aeq_mtt1_h[2]; /* 48 */ + volatile csr_function_aeq_mtt1_l_u function_aeq_mtt1_l[2]; /* 4C */ + volatile csr_function_aeq_mtt2_h_u function_aeq_mtt2_h[2]; /* 50 */ + volatile csr_function_aeq_mtt2_l_u function_aeq_mtt2_l[2]; /* 54 */ + volatile csr_function_aeq_mtt3_h_u function_aeq_mtt3_h[2]; /* 58 */ + volatile csr_function_aeq_mtt3_l_u function_aeq_mtt3_l[2]; /* 5C */ +} S_func_aeq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_aeq_csr */ +extern volatile S_func_aeq_csr_REGS_TYPE *gopfunc_aeq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetAEQ_CTL_0_af_aeq_int_offset(unsigned int uaf_aeq_int_offset); +int iSetAEQ_CTL_0_af_aeq_dma_attr_offset(unsigned int uaf_aeq_dma_attr_offset); +int iSetAEQ_CTL_0_af_aeq_dma_so(unsigned int uaf_aeq_dma_so); +int iSetAEQ_CTL_0_af_aeq_port(unsigned int uaf_aeq_port); +int iSetAEQ_CTL_0_af_aeq_int_mode(unsigned int uaf_aeq_int_mode); +int iSetAEQ_CTL_1_af_aeq_length(unsigned int uaf_aeq_length); +int iSetAEQ_CTL_1_af_aeqe_size(unsigned int uaf_aeqe_size); +int iSetAEQ_CTL_1_af_aeq_page(unsigned int uaf_aeq_page); +int iSetAEQ_CI_af_aeq_ci(unsigned int uaf_aeq_ci); +int iSetAEQ_CI_af_aeq_int_armed(unsigned int uaf_aeq_int_armed); +int iSetAEQ_PI_af_aeq_pi(unsigned int uaf_aeq_pi); +int iSetAEQ_INDIR_IDX_aeq_indir_idx(unsigned int uaeq_indir_idx); +int iSetFUNCTION_AEQ_MTT0_H_aeq_mtt0_addr_h(unsigned int uaeq_mtt0_addr_h); +int iSetFUNCTION_AEQ_MTT0_L_aeq_mtt0_addr_l(unsigned int uaeq_mtt0_addr_l); +int iSetFUNCTION_AEQ_MTT1_H_aeq_mtt1_addr_h(unsigned int uaeq_mtt1_addr_h); +int iSetFUNCTION_AEQ_MTT1_L_aeq_mtt1_addr_l(unsigned int uaeq_mtt1_addr_l); +int iSetFUNCTION_AEQ_MTT2_H_aeq_mtt2_addr_h(unsigned int uaeq_mtt2_addr_h); +int iSetFUNCTION_AEQ_MTT2_L_aeq_mtt2_addr_l(unsigned int uaeq_mtt2_addr_l); +int iSetFUNCTION_AEQ_MTT3_H_aeq_mtt3_addr_h(unsigned int uaeq_mtt3_addr_h); +int iSetFUNCTION_AEQ_MTT3_L_aeq_mtt3_addr_l(unsigned int uaeq_mtt3_addr_l); + +/* Define the union csr_ceq_ctl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ceq_int_offset : 10; /* [9:0] */ + u32 rsv_0 : 2; /* [11:10] */ + u32 af_ceq_dma_attr_offset : 6; /* [17:12] */ + u32 rsv_1 : 2; /* [19:18] */ + u32 af_ceqe_kickoff_lmt : 4; /* [23:20] */ + u32 af_ceq_pcie_port : 3; /* [26:24] */ + u32 af_ceq_page : 4; /* [30:27] */ + u32 af_ceq_int_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_ctl_0_u; + +/* Define the union csr_ceq_ctl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ceq_length : 20; /* [19:0] */ + u32 af_ceq_glb_func_idx : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_ctl_1_u; + +/* Define the union csr_ceq_ci_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ceq_ci : 21; /* [20:0] */ + u32 rsv_2 : 10; /* [30:21] */ + u32 af_ceq_int_armed : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_ci_u; + +/* Define the union csr_ceq_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 af_ceq_pi : 21; /* [20:0] */ + u32 rsv_3 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_pi_u; + +/* Define the union csr_ceq_indir_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_indir_idx : 10; /* [9:0] */ + u32 rsv_4 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_indir_idx_u; + +/* Define the union csr_function_ceq_mtt0_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt0_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt0_h_u; + +/* Define the union csr_function_ceq_mtt0_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt0_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt0_l_u; + +/* Define the union csr_function_ceq_mtt1_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt1_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt1_h_u; + +/* Define the union csr_function_ceq_mtt1_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt1_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt1_l_u; + +/* Define the union csr_function_ceq_mtt2_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt2_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt2_h_u; + +/* Define the union csr_function_ceq_mtt2_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt2_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt2_l_u; + +/* Define the union csr_function_ceq_mtt3_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt3_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt3_h_u; + +/* Define the union csr_function_ceq_mtt3_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt3_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt3_l_u; + +/* Define the union csr_function_ceq_mtt4_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt4_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt4_h_u; + +/* Define the union csr_function_ceq_mtt4_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt4_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt4_l_u; + +/* Define the union csr_function_ceq_mtt5_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt5_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt5_h_u; + +/* Define the union csr_function_ceq_mtt5_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt5_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt5_l_u; + +/* Define the union csr_function_ceq_mtt6_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt6_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt6_h_u; + +/* Define the union csr_function_ceq_mtt6_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt6_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt6_l_u; + +/* Define the union csr_function_ceq_mtt7_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt7_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt7_h_u; + +/* Define the union csr_function_ceq_mtt7_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt7_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_ceq_mtt7_l_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ceq_ctl_0_u ceq_ctl_0[2]; /* 0 */ + volatile csr_ceq_ctl_1_u ceq_ctl_1[2]; /* 4 */ + volatile csr_ceq_ci_u ceq_ci[2]; /* 8 */ + volatile csr_ceq_pi_u ceq_pi[2]; /* C */ + volatile csr_ceq_indir_idx_u ceq_indir_idx[2]; /* 10 */ + volatile csr_function_ceq_mtt0_h_u function_ceq_mtt0_h[2]; /* 40 */ + volatile csr_function_ceq_mtt0_l_u function_ceq_mtt0_l[2]; /* 44 */ + volatile csr_function_ceq_mtt1_h_u function_ceq_mtt1_h[2]; /* 48 */ + volatile csr_function_ceq_mtt1_l_u function_ceq_mtt1_l[2]; /* 4C */ + volatile csr_function_ceq_mtt2_h_u function_ceq_mtt2_h[2]; /* 50 */ + volatile csr_function_ceq_mtt2_l_u function_ceq_mtt2_l[2]; /* 54 */ + volatile csr_function_ceq_mtt3_h_u function_ceq_mtt3_h[2]; /* 58 */ + volatile csr_function_ceq_mtt3_l_u function_ceq_mtt3_l[2]; /* 5C */ + volatile csr_function_ceq_mtt4_h_u function_ceq_mtt4_h[2]; /* 60 */ + volatile csr_function_ceq_mtt4_l_u function_ceq_mtt4_l[2]; /* 64 */ + volatile csr_function_ceq_mtt5_h_u function_ceq_mtt5_h[2]; /* 68 */ + volatile csr_function_ceq_mtt5_l_u function_ceq_mtt5_l[2]; /* 6C */ + volatile csr_function_ceq_mtt6_h_u function_ceq_mtt6_h[2]; /* 70 */ + volatile csr_function_ceq_mtt6_l_u function_ceq_mtt6_l[2]; /* 74 */ + volatile csr_function_ceq_mtt7_h_u function_ceq_mtt7_h[2]; /* 78 */ + volatile csr_function_ceq_mtt7_l_u function_ceq_mtt7_l[2]; /* 7C */ +} S_func_ceq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_ceq_csr */ +extern volatile S_func_ceq_csr_REGS_TYPE *gopfunc_ceq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCEQ_CTL_0_af_ceq_int_offset(unsigned int uaf_ceq_int_offset); +int iSetCEQ_CTL_0_af_ceq_dma_attr_offset(unsigned int uaf_ceq_dma_attr_offset); +int iSetCEQ_CTL_0_af_ceqe_kickoff_lmt(unsigned int uaf_ceqe_kickoff_lmt); +int iSetCEQ_CTL_0_af_ceq_pcie_port(unsigned int uaf_ceq_pcie_port); +int iSetCEQ_CTL_0_af_ceq_page(unsigned int uaf_ceq_page); +int iSetCEQ_CTL_0_af_ceq_int_mode(unsigned int uaf_ceq_int_mode); +int iSetCEQ_CTL_1_af_ceq_length(unsigned int uaf_ceq_length); +int iSetCEQ_CTL_1_af_ceq_glb_func_idx(unsigned int uaf_ceq_glb_func_idx); +int iSetCEQ_CI_af_ceq_ci(unsigned int uaf_ceq_ci); +int iSetCEQ_CI_af_ceq_int_armed(unsigned int uaf_ceq_int_armed); +int iSetCEQ_PI_af_ceq_pi(unsigned int uaf_ceq_pi); +int iSetCEQ_INDIR_IDX_ceq_indir_idx(unsigned int uceq_indir_idx); +int iSetFUNCTION_CEQ_MTT0_H_ceq_mtt0_addr_h(unsigned int uceq_mtt0_addr_h); +int iSetFUNCTION_CEQ_MTT0_L_ceq_mtt0_addr_l(unsigned int uceq_mtt0_addr_l); +int iSetFUNCTION_CEQ_MTT1_H_ceq_mtt1_addr_h(unsigned int uceq_mtt1_addr_h); +int iSetFUNCTION_CEQ_MTT1_L_ceq_mtt1_addr_l(unsigned int uceq_mtt1_addr_l); +int iSetFUNCTION_CEQ_MTT2_H_ceq_mtt2_addr_h(unsigned int uceq_mtt2_addr_h); +int iSetFUNCTION_CEQ_MTT2_L_ceq_mtt2_addr_l(unsigned int uceq_mtt2_addr_l); +int iSetFUNCTION_CEQ_MTT3_H_ceq_mtt3_addr_h(unsigned int uceq_mtt3_addr_h); +int iSetFUNCTION_CEQ_MTT3_L_ceq_mtt3_addr_l(unsigned int uceq_mtt3_addr_l); +int iSetFUNCTION_CEQ_MTT4_H_ceq_mtt4_addr_h(unsigned int uceq_mtt4_addr_h); +int iSetFUNCTION_CEQ_MTT4_L_ceq_mtt4_addr_l(unsigned int uceq_mtt4_addr_l); +int iSetFUNCTION_CEQ_MTT5_H_ceq_mtt5_addr_h(unsigned int uceq_mtt5_addr_h); +int iSetFUNCTION_CEQ_MTT5_L_ceq_mtt5_addr_l(unsigned int uceq_mtt5_addr_l); +int iSetFUNCTION_CEQ_MTT6_H_ceq_mtt6_addr_h(unsigned int uceq_mtt6_addr_h); +int iSetFUNCTION_CEQ_MTT6_L_ceq_mtt6_addr_l(unsigned int uceq_mtt6_addr_l); +int iSetFUNCTION_CEQ_MTT7_H_ceq_mtt7_addr_h(unsigned int uceq_mtt7_addr_h); +int iSetFUNCTION_CEQ_MTT7_L_ceq_mtt7_addr_l(unsigned int uceq_mtt7_addr_l); + +/* Define the union csr_msi_control_csr_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pending_limt : 8; /* [7:0] */ + u32 coalesc_timer_cfg : 8; /* [15:8] */ + u32 lli_timer_cfg : 8; /* [23:16] */ + u32 lli_credit_limit : 5; /* [28:24] */ + u32 resend_timer_cfg : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_csr_0_u; + +/* Define the union csr_msi_control_csr_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lli_tmier_cnt : 8; /* [7:0] */ + u32 lli_credit_cnt : 8; /* [15:8] */ + u32 coalesct_timer_cnt : 8; /* [23:16] */ + u32 pengding_cnt : 5; /* [28:24] */ + u32 resend_timer_cnt : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_csr_1_u; + +/* Define the union csr_msi_control_csr_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 auto_msk_en : 1; /* [0] */ + u32 int_msk : 1; /* [1] */ + u32 rsv_0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_csr_2_u; + +/* Define the union csr_msi_control_csr_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_resend_timer_clr : 1; /* [0] */ + u32 msi_int_msk_set : 1; /* [1] */ + u32 msi_int_msk_clr : 1; /* [2] */ + u32 msi_auto_msk_set : 1; /* [3] */ + u32 msi_auto_msk_clr : 1; /* [4] */ + u32 rsv_1 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_csr_3_u; + +/* Define the union csr_msi_control_indir_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_ctl_indir_idx : 10; /* [9:0] */ + u32 rsv_2 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_indir_idx_u; + +/* Define the union csr_msi_control_csr_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_offset_in_func : 10; /* [9:0] */ + u32 rsv_3 : 6; /* [15:10] */ + u32 msi_glb_func_idx : 12; /* [27:16] */ + u32 rsv_4 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_control_csr_4_u; + +/* Define the union csr_function_dma_attr_entr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tlp_st : 8; /* [7:0] */ + u32 tlp_at : 2; /* [9:8] */ + u32 tlp_ph : 2; /* [11:10] */ + u32 tlp_no_snooping : 1; /* [12] */ + u32 tlp_en : 1; /* [13] */ + u32 rsv_5 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_function_dma_attr_entr_u; + +/* Define the union csr_dma_attr_indir_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_attr_indir_idx : 10; /* [9:0] */ + u32 rsv_6 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_attr_indir_idx_u; + +/* Define the union csr_pf_intx_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_mask_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_mask0_u; + +/* Define the union csr_pf_intx_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_mask_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_mask1_u; + +/* Define the union csr_pf_intx_mask2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_mask_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_mask2_u; + +/* Define the union csr_pf_intx_mask3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_mask_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_mask3_u; + +/* Define the union csr_pf_intx_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_status_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_status0_u; + +/* Define the union csr_pf_intx_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_status_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_status1_u; + +/* Define the union csr_pf_intx_status2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_status_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_status2_u; + +/* Define the union csr_pf_intx_status3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_intx_status_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_intx_status3_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_msi_control_csr_0_u msi_control_csr_0[2]; /* 0 */ + volatile csr_msi_control_csr_1_u msi_control_csr_1[2]; /* 4 */ + volatile csr_msi_control_csr_2_u msi_control_csr_2[2]; /* 8 */ + volatile csr_msi_control_csr_3_u msi_control_csr_3[2]; /* C */ + volatile csr_msi_control_indir_idx_u msi_control_indir_idx; /* 10 */ + volatile csr_msi_control_csr_4_u msi_control_csr_4[2]; /* 14 */ + volatile csr_function_dma_attr_entr_u function_dma_attr_entr[2]; /* 80000 */ + volatile csr_dma_attr_indir_idx_u dma_attr_indir_idx; /* 10 */ + volatile csr_pf_intx_mask0_u pf_intx_mask0[32]; /* A0000 */ + volatile csr_pf_intx_mask1_u pf_intx_mask1[32]; /* A0004 */ + volatile csr_pf_intx_mask2_u pf_intx_mask2[32]; /* A0008 */ + volatile csr_pf_intx_mask3_u pf_intx_mask3[32]; /* A000C */ + volatile csr_pf_intx_status0_u pf_intx_status0[32]; /* A0010 */ + volatile csr_pf_intx_status1_u pf_intx_status1[32]; /* A0014 */ + volatile csr_pf_intx_status2_u pf_intx_status2[32]; /* A0018 */ + volatile csr_pf_intx_status3_u pf_intx_status3[32]; /* A001C */ +} S_func_int_csr_REGS_TYPE; + +/* Declare the struct pointor of the module func_int_csr */ +extern volatile S_func_int_csr_REGS_TYPE *gopfunc_int_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetMSI_CONTROL_CSR_0_pending_limt(unsigned int upending_limt); +int iSetMSI_CONTROL_CSR_0_coalesc_timer_cfg(unsigned int ucoalesc_timer_cfg); +int iSetMSI_CONTROL_CSR_0_lli_timer_cfg(unsigned int ulli_timer_cfg); +int iSetMSI_CONTROL_CSR_0_lli_credit_limit(unsigned int ulli_credit_limit); +int iSetMSI_CONTROL_CSR_0_resend_timer_cfg(unsigned int uresend_timer_cfg); +int iSetMSI_CONTROL_CSR_1_lli_tmier_cnt(unsigned int ulli_tmier_cnt); +int iSetMSI_CONTROL_CSR_1_lli_credit_cnt(unsigned int ulli_credit_cnt); +int iSetMSI_CONTROL_CSR_1_coalesct_timer_cnt(unsigned int ucoalesct_timer_cnt); +int iSetMSI_CONTROL_CSR_1_pengding_cnt(unsigned int upengding_cnt); +int iSetMSI_CONTROL_CSR_1_resend_timer_cnt(unsigned int uresend_timer_cnt); +int iSetMSI_CONTROL_CSR_2_auto_msk_en(unsigned int uauto_msk_en); +int iSetMSI_CONTROL_CSR_2_int_msk(unsigned int uint_msk); +int iSetMSI_CONTROL_CSR_3_msi_resend_timer_clr(unsigned int umsi_resend_timer_clr); +int iSetMSI_CONTROL_CSR_3_msi_int_msk_set(unsigned int umsi_int_msk_set); +int iSetMSI_CONTROL_CSR_3_msi_int_msk_clr(unsigned int umsi_int_msk_clr); +int iSetMSI_CONTROL_CSR_3_msi_auto_msk_set(unsigned int umsi_auto_msk_set); +int iSetMSI_CONTROL_CSR_3_msi_auto_msk_clr(unsigned int umsi_auto_msk_clr); +int iSetMSI_CONTROL_INDIR_IDX_msi_ctl_indir_idx(unsigned int umsi_ctl_indir_idx); +int iSetMSI_CONTROL_CSR_4_msi_offset_in_func(unsigned int umsi_offset_in_func); +int iSetMSI_CONTROL_CSR_4_msi_glb_func_idx(unsigned int umsi_glb_func_idx); +int iSetFUNCTION_DMA_ATTR_ENTR_tlp_st(unsigned int utlp_st); +int iSetFUNCTION_DMA_ATTR_ENTR_tlp_at(unsigned int utlp_at); +int iSetFUNCTION_DMA_ATTR_ENTR_tlp_ph(unsigned int utlp_ph); +int iSetFUNCTION_DMA_ATTR_ENTR_tlp_no_snooping(unsigned int utlp_no_snooping); +int iSetFUNCTION_DMA_ATTR_ENTR_tlp_en(unsigned int utlp_en); +int iSetDMA_ATTR_INDIR_IDX_dma_attr_indir_idx(unsigned int udma_attr_indir_idx); +int iSetPF_INTX_MASK0_pf_intx_mask_127_96(unsigned int upf_intx_mask_127_96); +int iSetPF_INTX_MASK1_pf_intx_mask_95_64(unsigned int upf_intx_mask_95_64); +int iSetPF_INTX_MASK2_pf_intx_mask_63_32(unsigned int upf_intx_mask_63_32); +int iSetPF_INTX_MASK3_pf_intx_mask_31_0(unsigned int upf_intx_mask_31_0); +int iSetPF_INTX_STATUS0_pf_intx_status_127_96(unsigned int upf_intx_status_127_96); +int iSetPF_INTX_STATUS1_pf_intx_status_95_64(unsigned int upf_intx_status_95_64); +int iSetPF_INTX_STATUS2_pf_intx_status_63_32(unsigned int upf_intx_status_63_32); +int iSetPF_INTX_STATUS3_pf_intx_status_31_0(unsigned int upf_intx_status_31_0); + +/* Define the union csr_ppf_election_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_ppf_elect : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ppf_election_u; + +/* Define the union csr_mpf_election_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mpf_elect : 6; /* [5:0] */ + u32 rsv_1 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpf_election_u; + +/* Define the union csr_ucpu_clp_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_clp_req_size : 11; /* [10:0] */ + u32 rsv_2 : 5; /* [15:11] */ + u32 port_clp_rsp_size : 11; /* [26:16] */ + u32 rsv_3 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_clp_size_u; + +/* Define the union csr_ucpu_clp_reqbase_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_clp_req_base : 27; /* [26:0] */ + u32 rsv_4 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_clp_reqbase_u; + +/* Define the union csr_ucpu_clp_rspbase_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_clp_rsp_base : 27; /* [26:0] */ + u32 rsv_5 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_clp_rspbase_u; + +/* Define the union csr_ucpu_clp_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_clp_req_len : 11; /* [10:0] */ + u32 rsv_6 : 20; /* [30:11] */ + u32 port_clp_req_start : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_clp_req_u; + +/* Define the union csr_ucpu_clp_rsp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_clp_rsp_len : 11; /* [10:0] */ + u32 rsv_7 : 20; /* [30:11] */ + u32 port_clp_rsp_rdy : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_clp_rsp_u; + +/* Define the union csr_host_mpu_notify_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_mpu_pf_id : 5; /* [4:0] */ + u32 rsv_8 : 26; /* [30:5] */ + u32 host_mpu_notify : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_mpu_notify_ctl_u; + +/* Define the union csr_mpu_host_notify_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host_func_id : 12; /* [11:0] */ + u32 rsv_9 : 4; /* [15:12] */ + u32 mpu_host_vct_id : 10; /* [25:16] */ + u32 rsv_10 : 4; /* [29:26] */ + u32 mpu_host_int_en : 1; /* [30] */ + u32 mpu_host_notify : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host_notify_ctl_u; + +/* Define the union csr_host0_mpu_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_mpu_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host0_mpu_notify_data_u; + +/* Define the union csr_mpu_host0_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host0_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host0_notify_data_u; + +/* Define the union csr_host1_mpu_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host1_mpu_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host1_mpu_notify_data_u; + +/* Define the union csr_mpu_host1_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host1_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host1_notify_data_u; + +/* Define the union csr_host2_mpu_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_mpu_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host2_mpu_notify_data_u; + +/* Define the union csr_mpu_host2_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host2_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host2_notify_data_u; + +/* Define the union csr_host3_mpu_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host3_mpu_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host3_mpu_notify_data_u; + +/* Define the union csr_mpu_host3_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host3_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host3_notify_data_u; + +/* Define the union csr_host4_mpu_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host4_mpu_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host4_mpu_notify_data_u; + +/* Define the union csr_mpu_host4_notify_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_host4_notify_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mpu_host4_notify_data_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ppf_election_u ppf_election[5]; /* 0 */ + volatile csr_mpf_election_u mpf_election; /* 20 */ + volatile csr_ucpu_clp_size_u ucpu_clp_size[4]; /* 40 */ + volatile csr_ucpu_clp_reqbase_u ucpu_clp_reqbase[4]; /* 44 */ + volatile csr_ucpu_clp_rspbase_u ucpu_clp_rspbase[4]; /* 48 */ + volatile csr_ucpu_clp_req_u ucpu_clp_req[4]; /* 4C */ + volatile csr_ucpu_clp_rsp_u ucpu_clp_rsp[4]; /* 50 */ + volatile csr_host_mpu_notify_ctl_u host_mpu_notify_ctl[5]; /* C0 */ + volatile csr_mpu_host_notify_ctl_u mpu_host_notify_ctl[5]; /* C4 */ + volatile csr_host0_mpu_notify_data_u host0_mpu_notify_data[32]; /* 100 */ + volatile csr_mpu_host0_notify_data_u mpu_host0_notify_data[32]; /* 180 */ + volatile csr_host1_mpu_notify_data_u host1_mpu_notify_data[32]; /* 200 */ + volatile csr_mpu_host1_notify_data_u mpu_host1_notify_data[32]; /* 280 */ + volatile csr_host2_mpu_notify_data_u host2_mpu_notify_data[32]; /* 300 */ + volatile csr_mpu_host2_notify_data_u mpu_host2_notify_data[32]; /* 380 */ + volatile csr_host3_mpu_notify_data_u host3_mpu_notify_data[32]; /* 400 */ + volatile csr_mpu_host3_notify_data_u mpu_host3_notify_data[32]; /* 480 */ + volatile csr_host4_mpu_notify_data_u host4_mpu_notify_data[32]; /* 500 */ + volatile csr_mpu_host4_notify_data_u mpu_host4_notify_data[32]; /* 580 */ +} S_host_csr_REGS_TYPE; + +/* Declare the struct pointor of the module host_csr */ +extern volatile S_host_csr_REGS_TYPE *gophost_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetPPF_ELECTION_port_ppf_elect(unsigned int uport_ppf_elect); +int iSetMPF_ELECTION_glb_mpf_elect(unsigned int uglb_mpf_elect); +int iSetUCPU_CLP_SIZE_port_clp_req_size(unsigned int uport_clp_req_size); +int iSetUCPU_CLP_SIZE_port_clp_rsp_size(unsigned int uport_clp_rsp_size); +int iSetUCPU_CLP_REQBASE_port_clp_req_base(unsigned int uport_clp_req_base); +int iSetUCPU_CLP_RSPBASE_port_clp_rsp_base(unsigned int uport_clp_rsp_base); +int iSetUCPU_CLP_REQ_port_clp_req_len(unsigned int uport_clp_req_len); +int iSetUCPU_CLP_REQ_port_clp_req_start(unsigned int uport_clp_req_start); +int iSetUCPU_CLP_RSP_port_clp_rsp_len(unsigned int uport_clp_rsp_len); +int iSetUCPU_CLP_RSP_port_clp_rsp_rdy(unsigned int uport_clp_rsp_rdy); +int iSetHOST_MPU_NOTIFY_CTL_host_mpu_pf_id(unsigned int uhost_mpu_pf_id); +int iSetHOST_MPU_NOTIFY_CTL_host_mpu_notify(unsigned int uhost_mpu_notify); +int iSetMPU_HOST_NOTIFY_CTL_mpu_host_func_id(unsigned int umpu_host_func_id); +int iSetMPU_HOST_NOTIFY_CTL_mpu_host_vct_id(unsigned int umpu_host_vct_id); +int iSetMPU_HOST_NOTIFY_CTL_mpu_host_int_en(unsigned int umpu_host_int_en); +int iSetMPU_HOST_NOTIFY_CTL_mpu_host_notify(unsigned int umpu_host_notify); +int iSetHOST0_MPU_NOTIFY_DATA_host0_mpu_notify_data(unsigned int uhost0_mpu_notify_data); +int iSetMPU_HOST0_NOTIFY_DATA_mpu_host0_notify_data(unsigned int umpu_host0_notify_data); +int iSetHOST1_MPU_NOTIFY_DATA_host1_mpu_notify_data(unsigned int uhost1_mpu_notify_data); +int iSetMPU_HOST1_NOTIFY_DATA_mpu_host1_notify_data(unsigned int umpu_host1_notify_data); +int iSetHOST2_MPU_NOTIFY_DATA_host2_mpu_notify_data(unsigned int uhost2_mpu_notify_data); +int iSetMPU_HOST2_NOTIFY_DATA_mpu_host2_notify_data(unsigned int umpu_host2_notify_data); +int iSetHOST3_MPU_NOTIFY_DATA_host3_mpu_notify_data(unsigned int uhost3_mpu_notify_data); +int iSetMPU_HOST3_NOTIFY_DATA_mpu_host3_notify_data(unsigned int umpu_host3_notify_data); +int iSetHOST4_MPU_NOTIFY_DATA_host4_mpu_notify_data(unsigned int uhost4_mpu_notify_data); +int iSetMPU_HOST4_NOTIFY_DATA_mpu_host4_notify_data(unsigned int umpu_host4_notify_data); + +/* Define the union csr_glb_cpi_version_csr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_version_csr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_version_csr_u; + +/* Define the union csr_glb_x86_req_crd_flush_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_x86_req_crd_flush_max : 5; /* [4:0] */ + u32 rsv_0 : 3; /* [7:5] */ + u32 glb_x86_req_crd_flush_en : 1; /* [8] */ + u32 rsv_1 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_x86_req_crd_flush_ctl_u; + +/* Define the union csr_glb_x86_cpl_crd_flush_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_x86_cpl_crd_flush_max : 5; /* [4:0] */ + u32 rsv_2 : 3; /* [7:5] */ + u32 glb_x86_cpl_crd_flush_en : 1; /* [8] */ + u32 rsv_3 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_x86_cpl_crd_flush_ctl_u; + +/* Define the union csr_glb_spu_x86_acc_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_req_acc_weight_port : 8; /* [7:0] */ + u32 glb_cpl_acc_weight_port : 8; /* [15:8] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_spu_x86_acc_weight_u; + +/* Define the union csr_glb_port_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_port_mode_cfg : 2; /* [1:0] */ + u32 rsv_5 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port_mode_u; + +/* Define the union csr_glb_spu_req_crd_flush_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_spu_req_crd_flush_max : 5; /* [4:0] */ + u32 rsv_6 : 3; /* [7:5] */ + u32 glb_spu_req_crd_flush_en : 1; /* [8] */ + u32 rsv_7 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_spu_req_crd_flush_ctl_u; + +/* Define the union csr_glb_spu_cpl_crd_flush_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_spu_cpl_crd_flush_max : 5; /* [4:0] */ + u32 rsv_8 : 3; /* [7:5] */ + u32 glb_spu_cpl_crd_flush_en : 1; /* [8] */ + u32 rsv_9 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_spu_cpl_crd_flush_ctl_u; + +/* Define the union csr_glb_res_per_func_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_aeq_per_pf : 2; /* [1:0] */ + u32 glb_aeq_per_vf : 2; /* [3:2] */ + u32 rsv_10 : 4; /* [7:4] */ + u32 glb_api_per_pf : 4; /* [11:8] */ + u32 rsv_11 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_res_per_func_u; + +/* Define the union csr_api_gap_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_api_gap : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_gap_ctl_u; + +/* Define the union csr_dir_wqe_gap_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_gap : 16; /* [15:0] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dir_wqe_gap_ctl_u; + +/* Define the union csr_dir_wqe_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_aging_period : 20; /* [19:0] */ + u32 rsv_14 : 4; /* [23:20] */ + u32 glb_dwqe_tx_req_fifo_threshold : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dir_wqe_timeout_u; + +/* Define the union csr_glb_sw_srch_tcam_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_sw_srch_tcam_key : 26; /* [25:0] */ + u32 rsv_15 : 5; /* [30:26] */ + u32 glb_sw_srch_tcam_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_sw_srch_tcam_ctl_u; + +/* Define the union csr_glb_sw_srch_tcam_rslt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_sw_srch_tcam_data : 13; /* [12:0] */ + u32 rsv_16 : 18; /* [30:13] */ + u32 glb_sw_srch_tcam_hit : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_sw_srch_tcam_rslt_u; + +/* Define the union csr_glb_apb_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_apb_timer_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_apb_timer_cfg_u; + +/* Define the union csr_glb_srv_type_for_ddb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_srv_type_for_ddb0 : 5; /* [4:0] */ + u32 rsv_17 : 3; /* [7:5] */ + u32 glb_srv_type_for_ddb1 : 5; /* [12:8] */ + u32 rsv_18 : 3; /* [15:13] */ + u32 glb_srv_type_for_ddb2 : 5; /* [20:16] */ + u32 rsv_19 : 3; /* [23:21] */ + u32 glb_srv_type_for_ddb3 : 5; /* [28:24] */ + u32 rsv_20 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_srv_type_for_ddb_u; + +/* Define the union csr_glb_nl2n_inline_otd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_otd : 5; /* [4:0] */ + u32 rsv_21 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_nl2n_inline_otd_u; + +/* Define the union csr_glb_nl2n_inline_num_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_num_th : 6; /* [5:0] */ + u32 rsv_22 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_nl2n_inline_num_th_u; + +/* Define the union csr_glb_tilep_poll_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_indir_acc_poll_gap : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_tilep_poll_gap_u; + +/* Define the union csr_glb_mb_tx_legal_chk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_tx_legal_chk : 1; /* [0] */ + u32 rsv_24 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_tx_legal_chk_u; + +/* Define the union csr_glb_cpl_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpl_th_rsv : 1; /* [0] */ + u32 glb_cpl_data_rsv : 1; /* [1] */ + u32 glb_cpl_ur_st : 3; /* [4:2] */ + u32 rsv_25 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpl_ctrl_u; + +/* Define the union csr_ucpu_mb_tx_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_mb_dest_func : 13; /* [12:0] */ + u32 ucpu_mb_dest_port : 3; /* [15:13] */ + u32 ucpu_mb_dest_aeqn : 2; /* [17:16] */ + u32 ucpu_mb_tx_sts : 2; /* [19:18] */ + u32 ucpu_mb_tx_size : 5; /* [24:20] */ + u32 rsv_26 : 6; /* [30:25] */ + u32 ucpu_mb_tx_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_mb_tx_ctl_u; + +/* Define the union csr_ucpu_allow_vf_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_allow_vf_cfg : 1; /* [0] */ + u32 af_mb_tsk_csr_wr_right : 1; /* [1] */ + u32 pf_mb_tsk_csr_wr_right : 1; /* [2] */ + u32 rsv_27 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_allow_vf_cfg_u; + +/* Define the union csr_ucpu_mb_tx_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ucpu_mb_tx_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ucpu_mb_tx_data_u; + +/* Define the union csr_pf_eprom_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_eprom_offset : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_eprom_offset_u; + +/* Define the union csr_cpi_tbl_indir_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_tbl_indir_addr : 13; /* [12:0] */ + u32 rsv_28 : 11; /* [23:13] */ + u32 glb_tbl_indir_tab : 4; /* [27:24] */ + u32 glb_tbl_indir_stat : 2; /* [29:28] */ + u32 glb_tbl_indir_mode : 1; /* [30] */ + u32 glb_tbl_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tbl_indir_ctrl0_u; + +/* Define the union csr_cpi_tbl_indir_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_tbl_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tbl_indir_ctrl1_u; + +/* Define the union csr_cpi_tbl_indir_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_tbl_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tbl_indir_data_u; + +/* Define the union csr_cpi_indir_path_ring_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_indir_path_addr : 27; /* [26:0] */ + u32 pcie_indir_path_sts : 1; /* [27] */ + u32 pcie_indir_path_op : 1; /* [28] */ + u32 rsv_29 : 1; /* [29] */ + u32 pcie_indir_path_size : 1; /* [30] */ + u32 pcie_indir_path_issue : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_indir_path_ring_ctrl_u; + +/* Define the union csr_cpi_indir_path_ring_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_indir_path_dat0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_indir_path_ring_dat0_u; + +/* Define the union csr_cpi_indir_path_ring_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_indir_path_dat1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_indir_path_ring_dat1_u; + +/* Define the union csr_cpi_ram_init_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ram_ini_req : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_init_req_u; + +/* Define the union csr_cpi_ram_init_sts0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ram_ini_sts0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_init_sts0_u; + +/* Define the union csr_cpi_ram_init_sts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ram_ini_sts1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_init_sts1_u; + +/* Define the union csr_cpi_mb_tx_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_tx_gap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_mb_tx_gap_u; + +/* Define the union csr_glb_cpi_ram_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_30 : 31; /* [30:0] */ + u32 glb_cpi_ecc_bypass : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_ram_ecc_bypass_u; + +/* Define the union csr_glb_mb_shp_host0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_limit_for_pf_host0 : 6; /* [5:0] */ + u32 rsv_31 : 2; /* [7:6] */ + u32 mb_crdt_limit_for_vf_host0 : 6; /* [13:8] */ + u32 rsv_32 : 2; /* [15:14] */ + u32 mb_crdt_inc_timer_pf_host0 : 7; /* [22:16] */ + u32 rsv_33 : 1; /* [23] */ + u32 mb_crdt_inc_timer_vf_host0 : 7; /* [30:24] */ + u32 rsv_34 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_host0_u; + +/* Define the union csr_glb_mb_shp_host1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_limit_for_pf_host1 : 6; /* [5:0] */ + u32 rsv_35 : 2; /* [7:6] */ + u32 mb_crdt_limit_for_vf_host1 : 6; /* [13:8] */ + u32 rsv_36 : 2; /* [15:14] */ + u32 mb_crdt_inc_timer_pf_host1 : 7; /* [22:16] */ + u32 rsv_37 : 1; /* [23] */ + u32 mb_crdt_inc_timer_vf_host1 : 7; /* [30:24] */ + u32 rsv_38 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_host1_u; + +/* Define the union csr_glb_mb_shp_host2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_limit_for_pf_host2 : 6; /* [5:0] */ + u32 rsv_39 : 2; /* [7:6] */ + u32 mb_crdt_limit_for_vf_host2 : 6; /* [13:8] */ + u32 rsv_40 : 2; /* [15:14] */ + u32 mb_crdt_inc_timer_pf_host2 : 7; /* [22:16] */ + u32 rsv_41 : 1; /* [23] */ + u32 mb_crdt_inc_timer_vf_host2 : 7; /* [30:24] */ + u32 rsv_42 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_host2_u; + +/* Define the union csr_glb_mb_shp_host3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_limit_for_pf_host3 : 6; /* [5:0] */ + u32 rsv_43 : 2; /* [7:6] */ + u32 mb_crdt_limit_for_vf_host3 : 6; /* [13:8] */ + u32 rsv_44 : 2; /* [15:14] */ + u32 mb_crdt_inc_timer_pf_host3 : 7; /* [22:16] */ + u32 rsv_45 : 1; /* [23] */ + u32 mb_crdt_inc_timer_vf_host3 : 7; /* [30:24] */ + u32 rsv_46 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_host3_u; + +/* Define the union csr_glb_mb_shp_host4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_limit_for_pf_host4 : 6; /* [5:0] */ + u32 rsv_47 : 2; /* [7:6] */ + u32 mb_crdt_limit_for_vf_host4 : 6; /* [13:8] */ + u32 rsv_48 : 2; /* [15:14] */ + u32 mb_crdt_inc_timer_pf_host4 : 7; /* [22:16] */ + u32 rsv_49 : 1; /* [23] */ + u32 mb_crdt_inc_timer_vf_host4 : 7; /* [30:24] */ + u32 rsv_50 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_host4_u; + +/* Define the union csr_glb_mb_shp_unit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_crdt_inc_unit : 16; /* [15:0] */ + u32 rsv_51 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_shp_unit_u; + +/* Define the union csr_glb_mb_right_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mb_ppf_x86_to_spu_dis : 1; /* [0] */ + u32 mb_src_func_dis_mode : 1; /* [1] */ + u32 rsv_52 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_right_cfg_u; + +/* Define the union csr_glb_csr_acc_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_csr_acc_timeout : 16; /* [15:0] */ + u32 glb_dbl_acc_timeout : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_csr_acc_timeout_u; + +/* Define the union csr_glb_cpi_rs_nd_pe_crdit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_rs_nd_pe_crdt_sta : 10; /* [9:0] */ + u32 rsv_53 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_rs_nd_pe_crdit_u; + +/* Define the union csr_glb_np_ctx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_np_cpl_ur_st : 3; /* [2:0] */ + u32 rsv_54 : 5; /* [7:3] */ + u32 glb_np_cpl_data_rsv : 1; /* [8] */ + u32 rsv_55 : 7; /* [15:9] */ + u32 glb_np_ctx_aging_period : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_np_ctx_cfg_u; + +/* Define the union csr_glb_ipush_fifo_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_csr_fifo_bp_off : 7; /* [6:0] */ + u32 rsv_56 : 1; /* [7] */ + u32 glb_csr_fifo_bp_on : 7; /* [14:8] */ + u32 rsv_57 : 1; /* [15] */ + u32 glb_dbl_fifo_bp_off : 7; /* [22:16] */ + u32 rsv_58 : 1; /* [23] */ + u32 glb_dbl_fifo_bp_on : 7; /* [30:24] */ + u32 rsv_59 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ipush_fifo_bp_u; + +/* Define the union csr_glb_ipush_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ictl_ipush_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ipush_fifo_sts_u; + +/* Define the union csr_glb_cpath_int_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpath_int_bitmap : 16; /* [15:0] */ + u32 rsv_60 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpath_int_bitmap_u; + +/* Define the union csr_glb_dwqe_buf_vld_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_buf_vld_num : 7; /* [6:0] */ + u32 rsv_61 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dwqe_buf_vld_num_u; + +/* Define the union csr_dir_wqe_byte_order_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dirwqe_db_byte_order_switch_en : 1; /* [0] */ + u32 rsv_62 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dir_wqe_byte_order_en_u; + +/* Define the union csr_fake_vfid_cal_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fake_vfid_start_bit : 4; /* [3:0] */ + u32 fake_vfid_end_bit : 4; /* [7:4] */ + u32 fake_vfid_page_bit : 4; /* [11:8] */ + u32 rsv_63 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fake_vfid_cal_cfg_u; + +/* Define the union csr_fake_vfid_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fake_vfid_add_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_fake_vfid_enable_u; + +/* Define the union csr_dbl_fake_vfid_cbit_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbl_fake_vfid_cbit_en : 1; /* [0] */ + u32 rsv_64 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dbl_fake_vfid_cbit_en_u; + +/* Define the union csr_dbl_srv_type_illegal_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbl_srv_type_illegal : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dbl_srv_type_illegal_u; + +/* Define the union csr_glb_dwqe_lb_hash_acc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_dst_cid : 20; /* [19:0] */ + u32 rsv_65 : 11; /* [30:20] */ + u32 glb_dwqe_hash_based_ctxt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dwqe_lb_hash_acc_u; + +/* Define the union csr_glb_dwqe_lb_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_lbf_mode : 2; /* [1:0] */ + u32 rsv_66 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dwqe_lb_mod_u; + +/* Define the union csr_glb_dwqe_smf_pg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dwqe_smf_pg_cfg : 4; /* [3:0] */ + u32 rsv_67 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dwqe_smf_pg_u; + +/* Define the union csr_virtio_byte_order_dis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_byte_order_disable : 1; /* [0] */ + u32 rsv_68 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_byte_order_dis_u; + +/* Define the union csr_nvme_rsv_addr_range_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_rsv_start_addr : 12; /* [11:0] */ + u32 nvme_rsv_range_en : 1; /* [12] */ + u32 rsv_69 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_rsv_addr_range_u; + +/* Define the union csr_virtio_lb_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_lbf_mode : 2; /* [1:0] */ + u32 rsv_70 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_lb_mod_u; + +/* Define the union csr_virtio_otd_max_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_otd_max_th : 7; /* [6:0] */ + u32 rsv_71 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_otd_max_th_u; + +/* Define the union csr_glb_flxq_map_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_flxq_map_en : 1; /* [0] */ + u32 rsv_72 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_flxq_map_en_u; + +/* Define the union csr_glb_aeq_idx_for_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_aeq_idx_for_vf : 8; /* [7:0] */ + u32 rsv_73 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_aeq_idx_for_vf_u; + +/* Define the union csr_ptp_ts_updt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_ns_delta : 30; /* [29:0] */ + u32 rsv_74 : 1; /* [30] */ + u32 glb_ptp_ns_delta_op : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_updt_cfg_u; + +/* Define the union csr_ptp_ts_inc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_inc_frac : 16; /* [15:0] */ + u32 glb_ptp_inc_intg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_inc_cfg_u; + +/* Define the union csr_ptp_ts_calibration_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_calb_value : 16; /* [15:0] */ + u32 rsv_75 : 15; /* [30:16] */ + u32 glb_ptp_calb_sign : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_calibration_u; + +/* Define the union csr_ptp_ts_wr_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_wr_sec_h : 16; /* [15:0] */ + u32 rsv_76 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_wr_data0_u; + +/* Define the union csr_ptp_ts_wr_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_wr_sec_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_wr_data1_u; + +/* Define the union csr_ptp_ts_wr_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_wr_ns : 30; /* [29:0] */ + u32 rsv_77 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_wr_data2_u; + +/* Define the union csr_ptp_ts_rd_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_rd_sec_h : 16; /* [15:0] */ + u32 rsv_78 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_rd_data0_u; + +/* Define the union csr_ptp_ts_rd_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_rd_sec_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_rd_data1_u; + +/* Define the union csr_ptp_ts_rd_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_rd_ns : 30; /* [29:0] */ + u32 rsv_79 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_rd_data2_u; + +/* Define the union csr_ptp_ts_up_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_wr_up_en : 1; /* [0] */ + u32 glb_ptp_rd_up_en : 1; /* [1] */ + u32 glb_ptp_cfg_up_en : 1; /* [2] */ + u32 glb_ptp_delta_up_en : 1; /* [3] */ + u32 rsv_80 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_ts_up_en_u; + +/* Define the union csr_ptp_dstr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ptp_dstr_gap : 16; /* [15:0] */ + u32 rsv_81 : 15; /* [30:16] */ + u32 glb_ptp_dstr_cmp_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ptp_dstr_cfg_u; + +/* Define the union csr_non_ptp_ts_inc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_inc_frac : 16; /* [15:0] */ + u32 glb_non_ptp_inc_intg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_inc_cfg_u; + +/* Define the union csr_non_ptp_ts_calibration_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_calb_value : 16; /* [15:0] */ + u32 rsv_82 : 15; /* [30:16] */ + u32 glb_non_ptp_calb_sign : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_calibration_u; + +/* Define the union csr_non_ptp_ts_wr_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_wr_sec_h : 16; /* [15:0] */ + u32 rsv_83 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_wr_data0_u; + +/* Define the union csr_non_ptp_ts_wr_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_wr_sec_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_wr_data1_u; + +/* Define the union csr_non_ptp_ts_wr_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_wr_ns : 30; /* [29:0] */ + u32 rsv_84 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_wr_data2_u; + +/* Define the union csr_non_ptp_ts_rd_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_rd_sec_h : 16; /* [15:0] */ + u32 rsv_85 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_rd_data0_u; + +/* Define the union csr_non_ptp_ts_rd_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_rd_sec_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_rd_data1_u; + +/* Define the union csr_non_ptp_ts_rd_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_rd_ns : 30; /* [29:0] */ + u32 rsv_86 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_rd_data2_u; + +/* Define the union csr_non_ptp_ts_up_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_wr_up_en : 1; /* [0] */ + u32 glb_non_ptp_rd_up_en : 1; /* [1] */ + u32 glb_non_ptp_cfg_up_en : 1; /* [2] */ + u32 rsv_87 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_ts_up_en_u; + +/* Define the union csr_non_ptp_dstr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_ptp_dstr_gap : 16; /* [15:0] */ + u32 rsv_88 : 15; /* [30:16] */ + u32 glb_non_ptp_dstr_cmp_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_non_ptp_dstr_cfg_u; + +/* Define the union csr_glb_vf_offset_for_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_vf_offset_for_pf : 12; /* [11:0] */ + u32 rsv_89 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_vf_offset_for_pf_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_glb_cpi_version_csr_u glb_cpi_version_csr; /* 0 */ + volatile csr_glb_x86_req_crd_flush_ctl_u glb_x86_req_crd_flush_ctl; /* 4 */ + volatile csr_glb_x86_cpl_crd_flush_ctl_u glb_x86_cpl_crd_flush_ctl; /* 8 */ + volatile csr_glb_spu_x86_acc_weight_u glb_spu_x86_acc_weight; /* C */ + volatile csr_glb_port_mode_u glb_port_mode; /* 10 */ + volatile csr_glb_spu_req_crd_flush_ctl_u glb_spu_req_crd_flush_ctl; /* 14 */ + volatile csr_glb_spu_cpl_crd_flush_ctl_u glb_spu_cpl_crd_flush_ctl; /* 18 */ + volatile csr_glb_res_per_func_u glb_res_per_func; /* 50 */ + volatile csr_api_gap_ctl_u api_gap_ctl; /* 54 */ + volatile csr_dir_wqe_gap_ctl_u dir_wqe_gap_ctl; /* 58 */ + volatile csr_dir_wqe_timeout_u dir_wqe_timeout; /* 5C */ + volatile csr_glb_sw_srch_tcam_ctl_u glb_sw_srch_tcam_ctl; /* 80 */ + volatile csr_glb_sw_srch_tcam_rslt_u glb_sw_srch_tcam_rslt; /* 84 */ + volatile csr_glb_apb_timer_cfg_u glb_apb_timer_cfg; /* 88 */ + volatile csr_glb_srv_type_for_ddb_u glb_srv_type_for_ddb; /* 8C */ + volatile csr_glb_nl2n_inline_otd_u glb_nl2n_inline_otd; /* 90 */ + volatile csr_glb_nl2n_inline_num_th_u glb_nl2n_inline_num_th; /* 94 */ + volatile csr_glb_tilep_poll_gap_u glb_tilep_poll_gap; /* 98 */ + volatile csr_glb_mb_tx_legal_chk_u glb_mb_tx_legal_chk; /* A0 */ + volatile csr_glb_cpl_ctrl_u glb_cpl_ctrl; /* A8 */ + volatile csr_ucpu_mb_tx_ctl_u ucpu_mb_tx_ctl; /* B0 */ + volatile csr_ucpu_allow_vf_cfg_u ucpu_allow_vf_cfg; /* BC */ + volatile csr_ucpu_mb_tx_data_u ucpu_mb_tx_data[16]; /* C0 */ + volatile csr_pf_eprom_offset_u pf_eprom_offset[32]; /* 100 */ + volatile csr_cpi_tbl_indir_ctrl0_u cpi_tbl_indir_ctrl0; /* 200 */ + volatile csr_cpi_tbl_indir_ctrl1_u cpi_tbl_indir_ctrl1; /* 204 */ + volatile csr_cpi_tbl_indir_data_u cpi_tbl_indir_data[8]; /* 210 */ + volatile csr_cpi_indir_path_ring_ctrl_u cpi_indir_path_ring_ctrl; /* 230 */ + volatile csr_cpi_indir_path_ring_dat0_u cpi_indir_path_ring_dat0; /* 234 */ + volatile csr_cpi_indir_path_ring_dat1_u cpi_indir_path_ring_dat1; /* 238 */ + volatile csr_cpi_ram_init_req_u cpi_ram_init_req; /* 240 */ + volatile csr_cpi_ram_init_sts0_u cpi_ram_init_sts0; /* 250 */ + volatile csr_cpi_ram_init_sts1_u cpi_ram_init_sts1; /* 254 */ + volatile csr_cpi_mb_tx_gap_u cpi_mb_tx_gap; /* 260 */ + volatile csr_glb_cpi_ram_ecc_bypass_u glb_cpi_ram_ecc_bypass; /* 280 */ + volatile csr_glb_mb_shp_host0_u glb_mb_shp_host0; /* 290 */ + volatile csr_glb_mb_shp_host1_u glb_mb_shp_host1; /* 294 */ + volatile csr_glb_mb_shp_host2_u glb_mb_shp_host2; /* 298 */ + volatile csr_glb_mb_shp_host3_u glb_mb_shp_host3; /* 29C */ + volatile csr_glb_mb_shp_host4_u glb_mb_shp_host4; /* 2A0 */ + volatile csr_glb_mb_shp_unit_u glb_mb_shp_unit; /* 2A4 */ + volatile csr_glb_mb_right_cfg_u glb_mb_right_cfg; /* 2A8 */ + volatile csr_glb_csr_acc_timeout_u glb_csr_acc_timeout; /* 2B0 */ + volatile csr_glb_cpi_rs_nd_pe_crdit_u glb_cpi_rs_nd_pe_crdit; /* 2B8 */ + volatile csr_glb_np_ctx_cfg_u glb_np_ctx_cfg; /* 2F0 */ + volatile csr_glb_ipush_fifo_bp_u glb_ipush_fifo_bp; /* 318 */ + volatile csr_glb_ipush_fifo_sts_u glb_ipush_fifo_sts; /* 31C */ + volatile csr_glb_cpath_int_bitmap_u glb_cpath_int_bitmap; /* 340 */ + volatile csr_glb_dwqe_buf_vld_num_u glb_dwqe_buf_vld_num; /* 344 */ + volatile csr_dir_wqe_byte_order_en_u dir_wqe_byte_order_en; /* 354 */ + volatile csr_fake_vfid_cal_cfg_u fake_vfid_cal_cfg; /* 360 */ + volatile csr_fake_vfid_enable_u fake_vfid_enable; /* 364 */ + volatile csr_dbl_fake_vfid_cbit_en_u dbl_fake_vfid_cbit_en; /* 368 */ + volatile csr_dbl_srv_type_illegal_u dbl_srv_type_illegal; /* 36C */ + volatile csr_glb_dwqe_lb_hash_acc_u glb_dwqe_lb_hash_acc; /* 370 */ + volatile csr_glb_dwqe_lb_mod_u glb_dwqe_lb_mod; /* 374 */ + volatile csr_glb_dwqe_smf_pg_u glb_dwqe_smf_pg; /* 378 */ + volatile csr_virtio_byte_order_dis_u virtio_byte_order_dis; /* 380 */ + volatile csr_nvme_rsv_addr_range_u nvme_rsv_addr_range; /* 384 */ + volatile csr_virtio_lb_mod_u virtio_lb_mod; /* 388 */ + volatile csr_virtio_otd_max_th_u virtio_otd_max_th; /* 38C */ + volatile csr_glb_flxq_map_en_u glb_flxq_map_en; /* 390 */ + volatile csr_glb_aeq_idx_for_vf_u glb_aeq_idx_for_vf; /* 3A0 */ + volatile csr_ptp_ts_updt_cfg_u ptp_ts_updt_cfg; /* 3AC */ + volatile csr_ptp_ts_inc_cfg_u ptp_ts_inc_cfg; /* 3B0 */ + volatile csr_ptp_ts_calibration_u ptp_ts_calibration; /* 3B4 */ + volatile csr_ptp_ts_wr_data0_u ptp_ts_wr_data0; /* 3B8 */ + volatile csr_ptp_ts_wr_data1_u ptp_ts_wr_data1; /* 3BC */ + volatile csr_ptp_ts_wr_data2_u ptp_ts_wr_data2; /* 3C0 */ + volatile csr_ptp_ts_rd_data0_u ptp_ts_rd_data0; /* 3C4 */ + volatile csr_ptp_ts_rd_data1_u ptp_ts_rd_data1; /* 3C8 */ + volatile csr_ptp_ts_rd_data2_u ptp_ts_rd_data2; /* 3CC */ + volatile csr_ptp_ts_up_en_u ptp_ts_up_en; /* 3D0 */ + volatile csr_ptp_dstr_cfg_u ptp_dstr_cfg; /* 3D4 */ + volatile csr_non_ptp_ts_inc_cfg_u non_ptp_ts_inc_cfg; /* 3D8 */ + volatile csr_non_ptp_ts_calibration_u non_ptp_ts_calibration; /* 3DC */ + volatile csr_non_ptp_ts_wr_data0_u non_ptp_ts_wr_data0; /* 3E0 */ + volatile csr_non_ptp_ts_wr_data1_u non_ptp_ts_wr_data1; /* 3E4 */ + volatile csr_non_ptp_ts_wr_data2_u non_ptp_ts_wr_data2; /* 3E8 */ + volatile csr_non_ptp_ts_rd_data0_u non_ptp_ts_rd_data0; /* 3EC */ + volatile csr_non_ptp_ts_rd_data1_u non_ptp_ts_rd_data1; /* 3F0 */ + volatile csr_non_ptp_ts_rd_data2_u non_ptp_ts_rd_data2; /* 3F4 */ + volatile csr_non_ptp_ts_up_en_u non_ptp_ts_up_en; /* 3F8 */ + volatile csr_non_ptp_dstr_cfg_u non_ptp_dstr_cfg; /* 3FC */ + volatile csr_glb_vf_offset_for_pf_u glb_vf_offset_for_pf[33]; /* 400 */ +} S_glb_csr_REGS_TYPE; + +/* Declare the struct pointor of the module glb_csr */ +extern volatile S_glb_csr_REGS_TYPE *gopglb_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetGLB_CPI_VERSION_CSR_glb_cpi_version_csr(unsigned int uglb_cpi_version_csr); +int iSetGLB_X86_REQ_CRD_FLUSH_CTL_glb_x86_req_crd_flush_max(unsigned int uglb_x86_req_crd_flush_max); +int iSetGLB_X86_REQ_CRD_FLUSH_CTL_glb_x86_req_crd_flush_en(unsigned int uglb_x86_req_crd_flush_en); +int iSetGLB_X86_CPL_CRD_FLUSH_CTL_glb_x86_cpl_crd_flush_max(unsigned int uglb_x86_cpl_crd_flush_max); +int iSetGLB_X86_CPL_CRD_FLUSH_CTL_glb_x86_cpl_crd_flush_en(unsigned int uglb_x86_cpl_crd_flush_en); +int iSetGLB_SPU_X86_ACC_WEIGHT_glb_req_acc_weight_port(unsigned int uglb_req_acc_weight_port); +int iSetGLB_SPU_X86_ACC_WEIGHT_glb_cpl_acc_weight_port(unsigned int uglb_cpl_acc_weight_port); +int iSetGLB_PORT_MODE_glb_port_mode_cfg(unsigned int uglb_port_mode_cfg); +int iSetGLB_SPU_REQ_CRD_FLUSH_CTL_glb_spu_req_crd_flush_max(unsigned int uglb_spu_req_crd_flush_max); +int iSetGLB_SPU_REQ_CRD_FLUSH_CTL_glb_spu_req_crd_flush_en(unsigned int uglb_spu_req_crd_flush_en); +int iSetGLB_SPU_CPL_CRD_FLUSH_CTL_glb_spu_cpl_crd_flush_max(unsigned int uglb_spu_cpl_crd_flush_max); +int iSetGLB_SPU_CPL_CRD_FLUSH_CTL_glb_spu_cpl_crd_flush_en(unsigned int uglb_spu_cpl_crd_flush_en); +int iSetGLB_RES_PER_FUNC_glb_aeq_per_pf(unsigned int uglb_aeq_per_pf); +int iSetGLB_RES_PER_FUNC_glb_aeq_per_vf(unsigned int uglb_aeq_per_vf); +int iSetGLB_RES_PER_FUNC_glb_api_per_pf(unsigned int uglb_api_per_pf); +int iSetAPI_GAP_CTL_glb_api_gap(unsigned int uglb_api_gap); +int iSetDIR_WQE_GAP_CTL_glb_dwqe_gap(unsigned int uglb_dwqe_gap); +int iSetDIR_WQE_TIMEOUT_glb_dwqe_aging_period(unsigned int uglb_dwqe_aging_period); +int iSetDIR_WQE_TIMEOUT_glb_dwqe_tx_req_fifo_threshold(unsigned int uglb_dwqe_tx_req_fifo_threshold); +int iSetGLB_SW_SRCH_TCAM_CTL_glb_sw_srch_tcam_key(unsigned int uglb_sw_srch_tcam_key); +int iSetGLB_SW_SRCH_TCAM_CTL_glb_sw_srch_tcam_vld(unsigned int uglb_sw_srch_tcam_vld); +int iSetGLB_SW_SRCH_TCAM_RSLT_glb_sw_srch_tcam_data(unsigned int uglb_sw_srch_tcam_data); +int iSetGLB_SW_SRCH_TCAM_RSLT_glb_sw_srch_tcam_hit(unsigned int uglb_sw_srch_tcam_hit); +int iSetGLB_APB_TIMER_CFG_glb_apb_timer_cfg(unsigned int uglb_apb_timer_cfg); +int iSetGLB_SRV_TYPE_FOR_DDB_glb_srv_type_for_ddb0(unsigned int uglb_srv_type_for_ddb0); +int iSetGLB_SRV_TYPE_FOR_DDB_glb_srv_type_for_ddb1(unsigned int uglb_srv_type_for_ddb1); +int iSetGLB_SRV_TYPE_FOR_DDB_glb_srv_type_for_ddb2(unsigned int uglb_srv_type_for_ddb2); +int iSetGLB_SRV_TYPE_FOR_DDB_glb_srv_type_for_ddb3(unsigned int uglb_srv_type_for_ddb3); +int iSetGLB_NL2N_INLINE_OTD_nl2_otd(unsigned int unl2_otd); +int iSetGLB_NL2N_INLINE_NUM_TH_nl2_cmd_num_th(unsigned int unl2_cmd_num_th); +int iSetGLB_TILEP_POLL_GAP_tilep_indir_acc_poll_gap(unsigned int utilep_indir_acc_poll_gap); +int iSetGLB_MB_TX_LEGAL_CHK_glb_mb_tx_legal_chk(unsigned int uglb_mb_tx_legal_chk); +int iSetGLB_CPL_CTRL_glb_cpl_th_rsv(unsigned int uglb_cpl_th_rsv); +int iSetGLB_CPL_CTRL_glb_cpl_data_rsv(unsigned int uglb_cpl_data_rsv); +int iSetGLB_CPL_CTRL_glb_cpl_ur_st(unsigned int uglb_cpl_ur_st); +int iSetUCPU_MB_TX_CTL_ucpu_mb_dest_func(unsigned int uucpu_mb_dest_func); +int iSetUCPU_MB_TX_CTL_ucpu_mb_dest_port(unsigned int uucpu_mb_dest_port); +int iSetUCPU_MB_TX_CTL_ucpu_mb_dest_aeqn(unsigned int uucpu_mb_dest_aeqn); +int iSetUCPU_MB_TX_CTL_ucpu_mb_tx_sts(unsigned int uucpu_mb_tx_sts); +int iSetUCPU_MB_TX_CTL_ucpu_mb_tx_size(unsigned int uucpu_mb_tx_size); +int iSetUCPU_MB_TX_CTL_ucpu_mb_tx_req(unsigned int uucpu_mb_tx_req); +int iSetUCPU_ALLOW_VF_CFG_ucpu_allow_vf_cfg(unsigned int uucpu_allow_vf_cfg); +int iSetUCPU_ALLOW_VF_CFG_af_mb_tsk_csr_wr_right(unsigned int uaf_mb_tsk_csr_wr_right); +int iSetUCPU_ALLOW_VF_CFG_pf_mb_tsk_csr_wr_right(unsigned int upf_mb_tsk_csr_wr_right); +int iSetUCPU_MB_TX_DATA_ucpu_mb_tx_data(unsigned int uucpu_mb_tx_data); +int iSetPF_EPROM_OFFSET_pf_eprom_offset(unsigned int upf_eprom_offset); +int iSetCPI_TBL_INDIR_CTRL0_glb_tbl_indir_addr(unsigned int uglb_tbl_indir_addr); +int iSetCPI_TBL_INDIR_CTRL0_glb_tbl_indir_tab(unsigned int uglb_tbl_indir_tab); +int iSetCPI_TBL_INDIR_CTRL0_glb_tbl_indir_stat(unsigned int uglb_tbl_indir_stat); +int iSetCPI_TBL_INDIR_CTRL0_glb_tbl_indir_mode(unsigned int uglb_tbl_indir_mode); +int iSetCPI_TBL_INDIR_CTRL0_glb_tbl_indir_vld(unsigned int uglb_tbl_indir_vld); +int iSetCPI_TBL_INDIR_CTRL1_glb_tbl_indir_timeout(unsigned int uglb_tbl_indir_timeout); +int iSetCPI_TBL_INDIR_DATA_glb_tbl_indir_data(unsigned int uglb_tbl_indir_data); +int iSetCPI_INDIR_PATH_RING_CTRL_pcie_indir_path_addr(unsigned int upcie_indir_path_addr); +int iSetCPI_INDIR_PATH_RING_CTRL_pcie_indir_path_sts(unsigned int upcie_indir_path_sts); +int iSetCPI_INDIR_PATH_RING_CTRL_pcie_indir_path_op(unsigned int upcie_indir_path_op); +int iSetCPI_INDIR_PATH_RING_CTRL_pcie_indir_path_size(unsigned int upcie_indir_path_size); +int iSetCPI_INDIR_PATH_RING_CTRL_pcie_indir_path_issue(unsigned int upcie_indir_path_issue); +int iSetCPI_INDIR_PATH_RING_DAT0_pcie_indir_path_dat0(unsigned int upcie_indir_path_dat0); +int iSetCPI_INDIR_PATH_RING_DAT1_pcie_indir_path_dat1(unsigned int upcie_indir_path_dat1); +int iSetCPI_RAM_INIT_REQ_glb_cpi_ram_ini_req(unsigned int uglb_cpi_ram_ini_req); +int iSetCPI_RAM_INIT_STS0_glb_cpi_ram_ini_sts0(unsigned int uglb_cpi_ram_ini_sts0); +int iSetCPI_RAM_INIT_STS1_glb_cpi_ram_ini_sts1(unsigned int uglb_cpi_ram_ini_sts1); +int iSetCPI_MB_TX_GAP_glb_mb_tx_gap(unsigned int uglb_mb_tx_gap); +int iSetGLB_CPI_RAM_ECC_BYPASS_glb_cpi_ecc_bypass(unsigned int uglb_cpi_ecc_bypass); +int iSetGLB_MB_SHP_HOST0_mb_crdt_limit_for_pf_host0(unsigned int umb_crdt_limit_for_pf_host0); +int iSetGLB_MB_SHP_HOST0_mb_crdt_limit_for_vf_host0(unsigned int umb_crdt_limit_for_vf_host0); +int iSetGLB_MB_SHP_HOST0_mb_crdt_inc_timer_pf_host0(unsigned int umb_crdt_inc_timer_pf_host0); +int iSetGLB_MB_SHP_HOST0_mb_crdt_inc_timer_vf_host0(unsigned int umb_crdt_inc_timer_vf_host0); +int iSetGLB_MB_SHP_HOST1_mb_crdt_limit_for_pf_host1(unsigned int umb_crdt_limit_for_pf_host1); +int iSetGLB_MB_SHP_HOST1_mb_crdt_limit_for_vf_host1(unsigned int umb_crdt_limit_for_vf_host1); +int iSetGLB_MB_SHP_HOST1_mb_crdt_inc_timer_pf_host1(unsigned int umb_crdt_inc_timer_pf_host1); +int iSetGLB_MB_SHP_HOST1_mb_crdt_inc_timer_vf_host1(unsigned int umb_crdt_inc_timer_vf_host1); +int iSetGLB_MB_SHP_HOST2_mb_crdt_limit_for_pf_host2(unsigned int umb_crdt_limit_for_pf_host2); +int iSetGLB_MB_SHP_HOST2_mb_crdt_limit_for_vf_host2(unsigned int umb_crdt_limit_for_vf_host2); +int iSetGLB_MB_SHP_HOST2_mb_crdt_inc_timer_pf_host2(unsigned int umb_crdt_inc_timer_pf_host2); +int iSetGLB_MB_SHP_HOST2_mb_crdt_inc_timer_vf_host2(unsigned int umb_crdt_inc_timer_vf_host2); +int iSetGLB_MB_SHP_HOST3_mb_crdt_limit_for_pf_host3(unsigned int umb_crdt_limit_for_pf_host3); +int iSetGLB_MB_SHP_HOST3_mb_crdt_limit_for_vf_host3(unsigned int umb_crdt_limit_for_vf_host3); +int iSetGLB_MB_SHP_HOST3_mb_crdt_inc_timer_pf_host3(unsigned int umb_crdt_inc_timer_pf_host3); +int iSetGLB_MB_SHP_HOST3_mb_crdt_inc_timer_vf_host3(unsigned int umb_crdt_inc_timer_vf_host3); +int iSetGLB_MB_SHP_HOST4_mb_crdt_limit_for_pf_host4(unsigned int umb_crdt_limit_for_pf_host4); +int iSetGLB_MB_SHP_HOST4_mb_crdt_limit_for_vf_host4(unsigned int umb_crdt_limit_for_vf_host4); +int iSetGLB_MB_SHP_HOST4_mb_crdt_inc_timer_pf_host4(unsigned int umb_crdt_inc_timer_pf_host4); +int iSetGLB_MB_SHP_HOST4_mb_crdt_inc_timer_vf_host4(unsigned int umb_crdt_inc_timer_vf_host4); +int iSetGLB_MB_SHP_UNIT_mb_crdt_inc_unit(unsigned int umb_crdt_inc_unit); +int iSetGLB_MB_RIGHT_CFG_mb_ppf_x86_to_spu_dis(unsigned int umb_ppf_x86_to_spu_dis); +int iSetGLB_MB_RIGHT_CFG_mb_src_func_dis_mode(unsigned int umb_src_func_dis_mode); +int iSetGLB_CSR_ACC_TIMEOUT_glb_csr_acc_timeout(unsigned int uglb_csr_acc_timeout); +int iSetGLB_CSR_ACC_TIMEOUT_glb_dbl_acc_timeout(unsigned int uglb_dbl_acc_timeout); +int iSetGLB_CPI_RS_ND_PE_CRDIT_glb_cpi_rs_nd_pe_crdt_sta(unsigned int uglb_cpi_rs_nd_pe_crdt_sta); +int iSetGLB_NP_CTX_CFG_glb_np_cpl_ur_st(unsigned int uglb_np_cpl_ur_st); +int iSetGLB_NP_CTX_CFG_glb_np_cpl_data_rsv(unsigned int uglb_np_cpl_data_rsv); +int iSetGLB_NP_CTX_CFG_glb_np_ctx_aging_period(unsigned int uglb_np_ctx_aging_period); +int iSetGLB_IPUSH_FIFO_BP_glb_csr_fifo_bp_off(unsigned int uglb_csr_fifo_bp_off); +int iSetGLB_IPUSH_FIFO_BP_glb_csr_fifo_bp_on(unsigned int uglb_csr_fifo_bp_on); +int iSetGLB_IPUSH_FIFO_BP_glb_dbl_fifo_bp_off(unsigned int uglb_dbl_fifo_bp_off); +int iSetGLB_IPUSH_FIFO_BP_glb_dbl_fifo_bp_on(unsigned int uglb_dbl_fifo_bp_on); +int iSetGLB_IPUSH_FIFO_STS_glb_ictl_ipush_fifo_sts(unsigned int uglb_ictl_ipush_fifo_sts); +int iSetGLB_CPATH_INT_BITMAP_glb_cpath_int_bitmap(unsigned int uglb_cpath_int_bitmap); +int iSetGLB_DWQE_BUF_VLD_NUM_glb_dwqe_buf_vld_num(unsigned int uglb_dwqe_buf_vld_num); +int iSetDIR_WQE_BYTE_ORDER_EN_dirwqe_db_byte_order_switch_en(unsigned int udirwqe_db_byte_order_switch_en); +int iSetFAKE_VFID_CAL_CFG_fake_vfid_start_bit(unsigned int ufake_vfid_start_bit); +int iSetFAKE_VFID_CAL_CFG_fake_vfid_end_bit(unsigned int ufake_vfid_end_bit); +int iSetFAKE_VFID_CAL_CFG_fake_vfid_page_bit(unsigned int ufake_vfid_page_bit); +int iSetFAKE_VFID_ENABLE_fake_vfid_add_en(unsigned int ufake_vfid_add_en); +int iSetDBL_FAKE_VFID_CBIT_EN_dbl_fake_vfid_cbit_en(unsigned int udbl_fake_vfid_cbit_en); +int iSetDBL_SRV_TYPE_ILLEGAL_dbl_srv_type_illegal(unsigned int udbl_srv_type_illegal); +int iSetGLB_DWQE_LB_HASH_ACC_glb_dwqe_dst_cid(unsigned int uglb_dwqe_dst_cid); +int iSetGLB_DWQE_LB_HASH_ACC_glb_dwqe_hash_based_ctxt(unsigned int uglb_dwqe_hash_based_ctxt); +int iSetGLB_DWQE_LB_MOD_glb_dwqe_lbf_mode(unsigned int uglb_dwqe_lbf_mode); +int iSetGLB_DWQE_SMF_PG_glb_dwqe_smf_pg_cfg(unsigned int uglb_dwqe_smf_pg_cfg); +int iSetVIRTIO_BYTE_ORDER_DIS_virtio_byte_order_disable(unsigned int uvirtio_byte_order_disable); +int iSetNVME_RSV_ADDR_RANGE_nvme_rsv_start_addr(unsigned int unvme_rsv_start_addr); +int iSetNVME_RSV_ADDR_RANGE_nvme_rsv_range_en(unsigned int unvme_rsv_range_en); +int iSetVIRTIO_LB_MOD_virtio_lbf_mode(unsigned int uvirtio_lbf_mode); +int iSetVIRTIO_OTD_MAX_TH_virtio_otd_max_th(unsigned int uvirtio_otd_max_th); +int iSetGLB_FLXQ_MAP_EN_glb_flxq_map_en(unsigned int uglb_flxq_map_en); +int iSetGLB_AEQ_IDX_FOR_VF_glb_aeq_idx_for_vf(unsigned int uglb_aeq_idx_for_vf); +int iSetPTP_TS_UPDT_CFG_glb_ptp_ns_delta(unsigned int uglb_ptp_ns_delta); +int iSetPTP_TS_UPDT_CFG_glb_ptp_ns_delta_op(unsigned int uglb_ptp_ns_delta_op); +int iSetPTP_TS_INC_CFG_glb_ptp_inc_frac(unsigned int uglb_ptp_inc_frac); +int iSetPTP_TS_INC_CFG_glb_ptp_inc_intg(unsigned int uglb_ptp_inc_intg); +int iSetPTP_TS_CALIBRATION_glb_ptp_calb_value(unsigned int uglb_ptp_calb_value); +int iSetPTP_TS_CALIBRATION_glb_ptp_calb_sign(unsigned int uglb_ptp_calb_sign); +int iSetPTP_TS_WR_DATA0_glb_ptp_wr_sec_h(unsigned int uglb_ptp_wr_sec_h); +int iSetPTP_TS_WR_DATA1_glb_ptp_wr_sec_l(unsigned int uglb_ptp_wr_sec_l); +int iSetPTP_TS_WR_DATA2_glb_ptp_wr_ns(unsigned int uglb_ptp_wr_ns); +int iSetPTP_TS_RD_DATA0_glb_ptp_rd_sec_h(unsigned int uglb_ptp_rd_sec_h); +int iSetPTP_TS_RD_DATA1_glb_ptp_rd_sec_l(unsigned int uglb_ptp_rd_sec_l); +int iSetPTP_TS_RD_DATA2_glb_ptp_rd_ns(unsigned int uglb_ptp_rd_ns); +int iSetPTP_TS_UP_EN_glb_ptp_wr_up_en(unsigned int uglb_ptp_wr_up_en); +int iSetPTP_TS_UP_EN_glb_ptp_rd_up_en(unsigned int uglb_ptp_rd_up_en); +int iSetPTP_TS_UP_EN_glb_ptp_cfg_up_en(unsigned int uglb_ptp_cfg_up_en); +int iSetPTP_TS_UP_EN_glb_ptp_delta_up_en(unsigned int uglb_ptp_delta_up_en); +int iSetPTP_DSTR_CFG_glb_ptp_dstr_gap(unsigned int uglb_ptp_dstr_gap); +int iSetPTP_DSTR_CFG_glb_ptp_dstr_cmp_en(unsigned int uglb_ptp_dstr_cmp_en); +int iSetNON_PTP_TS_INC_CFG_glb_non_ptp_inc_frac(unsigned int uglb_non_ptp_inc_frac); +int iSetNON_PTP_TS_INC_CFG_glb_non_ptp_inc_intg(unsigned int uglb_non_ptp_inc_intg); +int iSetNON_PTP_TS_CALIBRATION_glb_non_ptp_calb_value(unsigned int uglb_non_ptp_calb_value); +int iSetNON_PTP_TS_CALIBRATION_glb_non_ptp_calb_sign(unsigned int uglb_non_ptp_calb_sign); +int iSetNON_PTP_TS_WR_DATA0_glb_non_ptp_wr_sec_h(unsigned int uglb_non_ptp_wr_sec_h); +int iSetNON_PTP_TS_WR_DATA1_glb_non_ptp_wr_sec_l(unsigned int uglb_non_ptp_wr_sec_l); +int iSetNON_PTP_TS_WR_DATA2_glb_non_ptp_wr_ns(unsigned int uglb_non_ptp_wr_ns); +int iSetNON_PTP_TS_RD_DATA0_glb_non_ptp_rd_sec_h(unsigned int uglb_non_ptp_rd_sec_h); +int iSetNON_PTP_TS_RD_DATA1_glb_non_ptp_rd_sec_l(unsigned int uglb_non_ptp_rd_sec_l); +int iSetNON_PTP_TS_RD_DATA2_glb_non_ptp_rd_ns(unsigned int uglb_non_ptp_rd_ns); +int iSetNON_PTP_TS_UP_EN_glb_non_ptp_wr_up_en(unsigned int uglb_non_ptp_wr_up_en); +int iSetNON_PTP_TS_UP_EN_glb_non_ptp_rd_up_en(unsigned int uglb_non_ptp_rd_up_en); +int iSetNON_PTP_TS_UP_EN_glb_non_ptp_cfg_up_en(unsigned int uglb_non_ptp_cfg_up_en); +int iSetNON_PTP_DSTR_CFG_glb_non_ptp_dstr_gap(unsigned int uglb_non_ptp_dstr_gap); +int iSetNON_PTP_DSTR_CFG_glb_non_ptp_dstr_cmp_en(unsigned int uglb_non_ptp_dstr_cmp_en); +int iSetGLB_VF_OFFSET_FOR_PF_glb_vf_offset_for_pf(unsigned int uglb_vf_offset_for_pf); + +/* Define the union csr_api_chain_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_addr_h_u; + +/* Define the union csr_api_chain_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_addr_l_u; + +/* Define the union csr_api_status_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_sts_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_status_addr_h_u; + +/* Define the union csr_api_status_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_sts_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_status_addr_l_u; + +/* Define the union csr_api_chain_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_len : 24; /* [23:0] */ + u32 rsv_0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_len_u; + +/* Define the union csr_api_chain_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_wb_after_susp : 1; /* [0] */ + u32 api_wb_after_restart : 1; /* [1] */ + u32 api_wb_after_xor_err : 1; /* [2] */ + u32 rsv_1 : 1; /* [3] */ + u32 api_wb_trigger_aeqe : 1; /* [4] */ + u32 ap_wb_after_cpld_err : 1; /* [5] */ + u32 rsv_2 : 2; /* [7:6] */ + u32 api_wb_aeq_num : 2; /* [9:8] */ + u32 rsv_3 : 18; /* [27:10] */ + u32 api_xor_chk_en : 2; /* [29:28] */ + u32 api_cell_unit : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_ctl_u; + +/* Define the union csr_api_chain_dma_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_wb_dma_attr_offset : 6; /* [5:0] */ + u32 rsv_4 : 2; /* [7:6] */ + u32 api_chain_rd_dma_attr_offset : 6; /* [13:8] */ + u32 rsv_5 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_dma_attr_u; + +/* Define the union csr_api_chain_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_pi : 24; /* [23:0] */ + u32 rsv_6 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_pi_u; + +/* Define the union csr_api_chain_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_susp_req : 1; /* [0] */ + u32 api_chain_restart_req : 1; /* [1] */ + u32 api_sts_rd_req : 1; /* [2] */ + u32 rsv_7 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_chain_req_u; + +/* Define the union csr_api_status_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_cur_ci : 24; /* [23:0] */ + u32 api_chain_cur_fsm : 4; /* [27:24] */ + u32 api_xor_chk_error : 2; /* [29:28] */ + u32 api_cpld_err : 1; /* [30] */ + u32 rsv_8 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_status_0_u; + +/* Define the union csr_api_status_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_cur_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_status_1_u; + +/* Define the union csr_api_status_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_chain_cur_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_api_status_2_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_api_chain_addr_h_u api_chain_addr_h[2]; /* 0 */ + volatile csr_api_chain_addr_l_u api_chain_addr_l[2]; /* 4 */ + volatile csr_api_status_addr_h_u api_status_addr_h[2]; /* 8 */ + volatile csr_api_status_addr_l_u api_status_addr_l[2]; /* C */ + volatile csr_api_chain_len_u api_chain_len[2]; /* 10 */ + volatile csr_api_chain_ctl_u api_chain_ctl[2]; /* 14 */ + volatile csr_api_chain_dma_attr_u api_chain_dma_attr[2]; /* 18 */ + volatile csr_api_chain_pi_u api_chain_pi[2]; /* 1C */ + volatile csr_api_chain_req_u api_chain_req[2]; /* 20 */ + volatile csr_api_status_0_u api_status_0[2]; /* 30 */ + volatile csr_api_status_1_u api_status_1[2]; /* 34 */ + volatile csr_api_status_2_u api_status_2[2]; /* 38 */ +} S_api_chn_csr_REGS_TYPE; + +/* Declare the struct pointor of the module api_chn_csr */ +extern volatile S_api_chn_csr_REGS_TYPE *gopapi_chn_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetAPI_CHAIN_ADDR_H_api_chain_addr_h(unsigned int uapi_chain_addr_h); +int iSetAPI_CHAIN_ADDR_L_api_chain_addr_l(unsigned int uapi_chain_addr_l); +int iSetAPI_STATUS_ADDR_H_api_sts_addr_h(unsigned int uapi_sts_addr_h); +int iSetAPI_STATUS_ADDR_L_api_sts_addr_l(unsigned int uapi_sts_addr_l); +int iSetAPI_CHAIN_LEN_api_chain_len(unsigned int uapi_chain_len); +int iSetAPI_CHAIN_CTL_api_wb_after_susp(unsigned int uapi_wb_after_susp); +int iSetAPI_CHAIN_CTL_api_wb_after_restart(unsigned int uapi_wb_after_restart); +int iSetAPI_CHAIN_CTL_api_wb_after_xor_err(unsigned int uapi_wb_after_xor_err); +int iSetAPI_CHAIN_CTL_api_wb_trigger_aeqe(unsigned int uapi_wb_trigger_aeqe); +int iSetAPI_CHAIN_CTL_ap_wb_after_cpld_err(unsigned int uap_wb_after_cpld_err); +int iSetAPI_CHAIN_CTL_api_wb_aeq_num(unsigned int uapi_wb_aeq_num); +int iSetAPI_CHAIN_CTL_api_xor_chk_en(unsigned int uapi_xor_chk_en); +int iSetAPI_CHAIN_CTL_api_cell_unit(unsigned int uapi_cell_unit); +int iSetAPI_CHAIN_DMA_ATTR_api_wb_dma_attr_offset(unsigned int uapi_wb_dma_attr_offset); +int iSetAPI_CHAIN_DMA_ATTR_api_chain_rd_dma_attr_offset(unsigned int uapi_chain_rd_dma_attr_offset); +int iSetAPI_CHAIN_PI_api_chain_pi(unsigned int uapi_chain_pi); +int iSetAPI_CHAIN_REQ_api_chain_susp_req(unsigned int uapi_chain_susp_req); +int iSetAPI_CHAIN_REQ_api_chain_restart_req(unsigned int uapi_chain_restart_req); +int iSetAPI_CHAIN_REQ_api_sts_rd_req(unsigned int uapi_sts_rd_req); +int iSetAPI_STATUS_0_api_chain_cur_ci(unsigned int uapi_chain_cur_ci); +int iSetAPI_STATUS_0_api_chain_cur_fsm(unsigned int uapi_chain_cur_fsm); +int iSetAPI_STATUS_0_api_xor_chk_error(unsigned int uapi_xor_chk_error); +int iSetAPI_STATUS_0_api_cpld_err(unsigned int uapi_cpld_err); +int iSetAPI_STATUS_1_api_chain_cur_addr_h(unsigned int uapi_chain_cur_addr_h); +int iSetAPI_STATUS_2_api_chain_cur_addr_l(unsigned int uapi_chain_cur_addr_l); + +/* Define the union csr_glb_debug_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbg_func_idx : 12; /* [11:0] */ + u32 rsv_0 : 4; /* [15:12] */ + u32 glb_dbg_bar_bitmap : 7; /* [22:16] */ + u32 rsv_1 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_debug_cfg_u; + +/* Define the union csr_glb_debug_rx_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbg_rx_mwr_tlp_cnt : 16; /* [15:0] */ + u32 glb_dbg_rx_mrd_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_debug_rx_tlp_cnt_u; + +/* Define the union csr_glb_debug_rx_dbl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbg_rx_dbl_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_debug_rx_dbl_cnt_u; + +/* Define the union csr_glb_debug_rx_dwqe_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbg_rx_dwqe_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_debug_rx_dwqe_cnt_u; + +/* Define the union csr_glb_port0_npcpl_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port0_tx_cpl_cnt : 16; /* [15:0] */ + u32 cpi_port0_rx_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port0_npcpl_tlp_cnt_u; + +/* Define the union csr_glb_port1_npcpl_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port1_tx_cpl_cnt : 16; /* [15:0] */ + u32 cpi_port1_rx_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port1_npcpl_tlp_cnt_u; + +/* Define the union csr_glb_port2_npcpl_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port2_tx_cpl_cnt : 16; /* [15:0] */ + u32 cpi_port2_rx_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port2_npcpl_tlp_cnt_u; + +/* Define the union csr_glb_port3_npcpl_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port3_tx_cpl_cnt : 16; /* [15:0] */ + u32 cpi_port3_rx_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port3_npcpl_tlp_cnt_u; + +/* Define the union csr_glb_port4_npcpl_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port4_tx_cpl_cnt : 16; /* [15:0] */ + u32 cpi_port4_rx_np_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_port4_npcpl_tlp_cnt_u; + +/* Define the union csr_dfx_ictl_rx_ok_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_sop_cnt : 16; /* [15:0] */ + u32 dfx_ictl_ok_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_rx_ok_cnt_u; + +/* Define the union csr_dfx_ictl_rx_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_vld_cnt : 16; /* [15:0] */ + u32 dfx_ictl_eop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_rx_eop_cnt_u; + +/* Define the union csr_dfx_ictl_sop_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_osch_tx_cpl_cnt : 16; /* [15:0] */ + u32 dfx_ictl_sop_eop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_sop_eop_cnt_u; + +/* Define the union csr_dfx_ictl_mpu_acc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_apb_rd_cnt : 16; /* [15:0] */ + u32 mpu_apb_wr_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_mpu_acc_cnt_u; + +/* Define the union csr_dfx_ictl_ipush_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_dwqe_tlp_cnt : 16; /* [15:0] */ + u32 ictl_ipush_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_ipush_tlp_cnt_u; + +/* Define the union csr_dfx_ictl_vio_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_rx_mem_cnt : 16; /* [15:0] */ + u32 ictl_vio_tlp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_vio_tlp_cnt_u; + +/* Define the union csr_dfx_ictl_rx_io_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_rx_rom_cnt : 16; /* [15:0] */ + u32 dfx_ictl_rx_io_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_rx_io_cnt_u; + +/* Define the union csr_dfx_ictl_rx_tlp_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_rx_uns_np_cnt : 16; /* [15:0] */ + u32 dfx_ictl_rx_tlp_drop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_rx_tlp_drop_cnt_u; + +/* Define the union csr_glb_cpi_port_bp_en_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_port_bp_en_cfg : 5; /* [4:0] */ + u32 rsv_2 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_port_bp_en_cfg_u; + +/* Define the union csr_dfx_ictl_fatal_msk0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_fatal_msk95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_fatal_msk0_u; + +/* Define the union csr_dfx_ictl_fatal_msk1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_fatal_msk63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_fatal_msk1_u; + +/* Define the union csr_dfx_ictl_fatal_msk2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_fatal_msk31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_fatal_msk2_u; + +/* Define the union csr_dfx_ictl_nonfatal_msk0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_nonfatal_msk95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_nonfatal_msk0_u; + +/* Define the union csr_dfx_ictl_nonfatal_msk1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_nonfatal_msk63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_nonfatal_msk1_u; + +/* Define the union csr_dfx_ictl_nonfatal_msk2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_nonfatal_msk31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_nonfatal_msk2_u; + +/* Define the union csr_dfx_ictl_err_pls0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_err_pls95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_err_pls0_u; + +/* Define the union csr_dfx_ictl_err_pls1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_err_pls63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_err_pls1_u; + +/* Define the union csr_dfx_ictl_err_pls2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ictl_err_pls31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ictl_err_pls2_u; + +/* Define the union csr_glb_cpi_bp_watch_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_bp_watch_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_bp_watch_sts_u; + +/* Define the union csr_glb_cpi_bp_watch_window_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_bp_watch_window : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_bp_watch_window_u; + +/* Define the union csr_glb_cpi_bp_watch_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_bp_watch_bitmap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_bp_watch_bitmap_u; + +/* Define the union csr_glb_cpi_bp_watch_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_bp_watch_start : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_bp_watch_start_u; + +/* Define the union csr_glb_cpi_bp_watch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_bp_watch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_bp_watch_cnt_u; + +/* Define the union csr_glb_csr_timeout_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_csr_timeout_cnt : 8; /* [7:0] */ + u32 glb_non_csr_timeout_cnt : 8; /* [15:8] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_csr_timeout_cnt_u; + +/* Define the union csr_dwqe_api_no_enough_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_api_no_enough_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_api_no_enough_data_u; + +/* Define the union csr_dwqe_dbl_no_enough_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dbl_no_enough_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dbl_no_enough_data_u; + +/* Define the union csr_norm_dbl_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 norm_dbl_illegal_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_norm_dbl_drop_cnt_u; + +/* Define the union csr_norm_dbl_tx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 norm_dbl_tx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_norm_dbl_tx_cnt_u; + +/* Define the union csr_dwqe_dbl_tx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dbl_tx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dbl_tx_cnt_u; + +/* Define the union csr_dwqe_api_tx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_api_tx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_api_tx_cnt_u; + +/* Define the union csr_dwqe_buf_bp_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_bp_sts : 4; /* [3:0] */ + u32 rsv_5 : 27; /* [30:4] */ + u32 dwqe_buf_bp_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_bp_msk_u; + +/* Define the union csr_dwqe_buf_cnt_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_cnt_port3 : 8; /* [7:0] */ + u32 dwqe_buf_cnt_port2 : 8; /* [15:8] */ + u32 dwqe_buf_cnt_port1 : 8; /* [23:16] */ + u32 dwqe_buf_cnt_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_cnt_port_u; + +/* Define the union csr_dwqe_buf_bp_on_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_bp_on_port3 : 8; /* [7:0] */ + u32 dwqe_buf_bp_on_port2 : 8; /* [15:8] */ + u32 dwqe_buf_bp_on_port1 : 8; /* [23:16] */ + u32 dwqe_buf_bp_on_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_bp_on_port_u; + +/* Define the union csr_dwqe_buf_bp_off_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_bp_off_port3 : 8; /* [7:0] */ + u32 dwqe_buf_bp_off_port2 : 8; /* [15:8] */ + u32 dwqe_buf_bp_off_port1 : 8; /* [23:16] */ + u32 dwqe_buf_bp_off_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_bp_off_port_u; + +/* Define the union csr_dwqe_req_buf_bgn_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_req_buf_bgn : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_req_buf_bgn_u; + +/* Define the union csr_dwqe_dropping_in_tx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dropping_in_tx : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dropping_in_tx_u; + +/* Define the union csr_dwqe_dropping_no_buf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dropping_no_buf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dropping_no_buf_u; + +/* Define the union csr_dwqe_dbl_without_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dbl_without_api : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dbl_without_api_u; + +/* Define the union csr_dwqe_tx_dbl_after_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_tx_dbl_after_api : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_tx_dbl_after_api_u; + +/* Define the union csr_dwqe_no_dbl_after_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_no_dbl_after_api : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_no_dbl_after_api_u; + +/* Define the union csr_dwqe_buf_overwrite_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_overwrite_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_overwrite_drop_cnt_u; + +/* Define the union csr_dwqe_buf_aging_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_aging_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_aging_drop_cnt_u; + +/* Define the union csr_dwqe_tx_req_fifo_push_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_tx_req_fifo_push_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_tx_req_fifo_push_cnt_u; + +/* Define the union csr_dwqe_tx_req_fifo_pop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_tx_req_fifo_pop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_tx_req_fifo_pop_cnt_u; + +/* Define the union csr_dwqe_tx_req_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_tx_req_fifo_sts : 3; /* [2:0] */ + u32 rsv_6 : 5; /* [7:3] */ + u32 dwqe_tx_req_fifo_overflow : 8; /* [15:8] */ + u32 dwqe_buf_alc_cnt : 8; /* [23:16] */ + u32 dwqe_tx_req_fifo_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_tx_req_fifo_sts_u; + +/* Define the union csr_dwqe_dropping_invld_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dropping_invld : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dropping_invld_u; + +/* Define the union csr_dwqe_sw_force_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_sw_force_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_sw_force_drop_u; + +/* Define the union csr_ictl_dbl_req_sop_null_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_dbl_req_sop_null : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_dbl_req_sop_null_u; + +/* Define the union csr_cpi_pcie_mb_aeqe_to_mpu_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_pcie_mb_aeqe_to_mpu_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pcie_mb_aeqe_to_mpu_cnt_u; + +/* Define the union csr_dfx_rx_dwqe_ddb_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_dwqe_ddb1_cnt : 16; /* [15:0] */ + u32 dfx_rx_dwqe_ddb0_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_rx_dwqe_ddb_cnt0_u; + +/* Define the union csr_dfx_rx_dwqe_ddb_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_dwqe_ddb3_cnt : 16; /* [15:0] */ + u32 dfx_rx_dwqe_ddb2_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_rx_dwqe_ddb_cnt1_u; + +/* Define the union csr_dfx_rx_dbl_srv_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_dbl_srv1_cnt : 16; /* [15:0] */ + u32 dfx_rx_dbl_srv0_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_rx_dbl_srv_cnt0_u; + +/* Define the union csr_dfx_rx_dbl_srv_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_rx_dbl_srv3_cnt : 16; /* [15:0] */ + u32 dfx_rx_dbl_srv2_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_rx_dbl_srv_cnt1_u; + +/* Define the union csr_glb_dfx_cfg_srv_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dfx_cfg0_srv_type : 5; /* [4:0] */ + u32 rsv_7 : 3; /* [7:5] */ + u32 glb_dfx_cfg1_srv_type : 5; /* [12:8] */ + u32 rsv_8 : 3; /* [15:13] */ + u32 glb_dfx_cfg2_srv_type : 5; /* [20:16] */ + u32 rsv_9 : 3; /* [23:21] */ + u32 glb_dfx_cfg3_srv_type : 5; /* [28:24] */ + u32 rsv_10 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dfx_cfg_srv_type_u; + +/* Define the union csr_aeq_ci_sw_wr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_ci_sw_wr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_ci_sw_wr_cnt_u; + +/* Define the union csr_aeq_tx_int_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_tx_int_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_tx_int_req_cnt_u; + +/* Define the union csr_cpi_ipush_csr_wr_pcie_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_wr_pcie_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_wr_pcie_cnt_u; + +/* Define the union csr_cpi_ipush_csr_wr_ucpu_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_wr_ucpu_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_wr_ucpu_cnt_u; + +/* Define the union csr_cpi_ipush_csr_rd_pcie_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_rd_pcie_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_rd_pcie_cnt_u; + +/* Define the union csr_cpi_ipush_csr_rd_ucpu_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_rd_ucpu_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_rd_ucpu_cnt_u; + +/* Define the union csr_cpi_ipush_osch_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_osch_cpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_osch_cpl_cnt_u; + +/* Define the union csr_cpi_ipush_ictl_cpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_ictl_cpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_ictl_cpl_cnt_u; + +/* Define the union csr_cpi_ipush_apictl_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_apictl_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_apictl_req_cnt_u; + +/* Define the union csr_cpi_pcie_mb_aeqe_to_dst_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_pcie_mb_aeqe_to_dst_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pcie_mb_aeqe_to_dst_cnt_u; + +/* Define the union csr_cpi_pcie_mb_aeqe_to_src_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_pcie_mb_aeqe_to_src_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pcie_mb_aeqe_to_src_cnt_u; + +/* Define the union csr_cpi_pcie_mb_stat_to_src_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_pcie_mb_stat_to_src_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pcie_mb_stat_to_src_cnt_u; + +/* Define the union csr_cpi_ucpu_mb_aeqe_to_dst_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ucpu_mb_aeqe_to_dst_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ucpu_mb_aeqe_to_dst_cnt_u; + +/* Define the union csr_cpi_ipush_csr_aeq_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_aeq_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_aeq_req_cnt_u; + +/* Define the union csr_cpi_ipush_csr_ceq_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_ceq_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_ceq_req_cnt_u; + +/* Define the union csr_cpi_ipush_csr_api_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_api_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_api_req_cnt_u; + +/* Define the union csr_cpi_ipush_csr_intctl_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_csr_intctl_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_csr_intctl_req_cnt_u; + +/* Define the union csr_cpi_ipush_upitf_clp_req_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ipush_upitf_clp_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ipush_upitf_clp_req_cnt_u; + +/* Define the union csr_cpi_ram_ecc_inj_err0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_inj_req0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_inj_err0_u; + +/* Define the union csr_cpi_ram_ecc_inj_err1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_inj_req1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_inj_err1_u; + +/* Define the union csr_cpi_ram_ecc_inj_err2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_inj_req2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_inj_err2_u; + +/* Define the union csr_cpi_ram_ecc_inj_err3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_inj_req3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_inj_err3_u; + +/* Define the union csr_cpi_ram_ecc_merr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_merr0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_merr0_u; + +/* Define the union csr_cpi_ram_ecc_merr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_merr1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_merr1_u; + +/* Define the union csr_cpi_ram_ecc_err0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err0_u; + +/* Define the union csr_cpi_ram_ecc_err1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err1_u; + +/* Define the union csr_cpi_ram_ecc_err_addr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err_addr0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err_addr0_u; + +/* Define the union csr_cpi_ram_ecc_err_addr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err_addr1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err_addr1_u; + +/* Define the union csr_cpi_ram_ecc_err_addr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err_addr2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err_addr2_u; + +/* Define the union csr_cpi_ram_ecc_err_addr3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ecc_err_addr3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_ram_ecc_err_addr3_u; + +/* Define the union csr_ipush_reserved0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_resved0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipush_reserved0_u; + +/* Define the union csr_ipush_reserved1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_resved1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipush_reserved1_u; + +/* Define the union csr_ipush_reserved2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_resved2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipush_reserved2_u; + +/* Define the union csr_ipush_reserved3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_resved3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipush_reserved3_u; + +/* Define the union csr_glb_cpi_uncrt_err_code0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_cmisc_uncrt_err_code : 4; /* [3:0] */ + u32 glb_cpi_cpath_dma_uncrt_err_code : 4; /* [7:4] */ + u32 glb_cpi_dtif_uncrt_err_code : 4; /* [11:8] */ + u32 glb_cpi_ictl_uncrt_err_code : 4; /* [15:12] */ + u32 glb_cpi_qmap_uncrt_err_code : 4; /* [19:16] */ + u32 glb_cpi_apictl_uncrt_err_code : 4; /* [23:20] */ + u32 glb_cpi_dpath_i_uncrt_err_code : 4; /* [27:24] */ + u32 glb_cpi_dpath_o_uncrt_err_code : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_uncrt_err_code0_u; + +/* Define the union csr_glb_cpi_uncrt_err_code1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ipush_uncrt_err_code : 4; /* [3:0] */ + u32 glb_cpi_cpath_uncrt_err_code : 4; /* [7:4] */ + u32 rsv_11 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_uncrt_err_code1_u; + +/* Define the union csr_glb_cpi_crt_err_code0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_cmisc_crt_err_code : 4; /* [3:0] */ + u32 glb_cpi_cpath_dma_crt_err_code : 4; /* [7:4] */ + u32 glb_cpi_dtif_crt_err_code : 4; /* [11:8] */ + u32 glb_cpi_ictl_crt_err_code : 4; /* [15:12] */ + u32 glb_cpi_qmap_crt_err_code : 4; /* [19:16] */ + u32 glb_cpi_apictl_crt_err_code : 4; /* [23:20] */ + u32 glb_cpi_dpath_i_crt_err_code : 4; /* [27:24] */ + u32 glb_cpi_dpath_o_crt_err_code : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_crt_err_code0_u; + +/* Define the union csr_glb_cpi_crt_err_code1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_ipush_crt_err_code : 4; /* [3:0] */ + u32 glb_cpi_cpath_crt_err_code : 4; /* [7:4] */ + u32 rsv_12 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpi_crt_err_code1_u; + +/* Define the union csr_dwqe_buf_dbg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_dbg_src_tag_l : 15; /* [14:0] */ + u32 rsv_13 : 1; /* [15] */ + u32 dwqe_buf_dbg_status : 2; /* [17:16] */ + u32 rsv_14 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_dbg0_u; + +/* Define the union csr_dwqe_buf_dbg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_dbg_exp_qw_num : 6; /* [5:0] */ + u32 rsv_15 : 2; /* [7:6] */ + u32 dwqe_buf_dbg_rx_qw_cnt : 6; /* [13:8] */ + u32 rsv_16 : 2; /* [15:14] */ + u32 dwqe_buf_dbg_no_dbl : 1; /* [16] */ + u32 dwqe_buf_dbg_aging_flag : 1; /* [17] */ + u32 rsv_17 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_dbg1_u; + +/* Define the union csr_dwqe_buf_dbg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_dbg_idx : 7; /* [6:0] */ + u32 rsv_18 : 1; /* [7] */ + u32 dwqe_buf_dbg_watch_en : 1; /* [8] */ + u32 dwqe_buf_dbg_force_ivld : 1; /* [9] */ + u32 rsv_19 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_buf_dbg2_u; + +/* Define the union csr_dwqe_bug_dbg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_buf_dbg_host_addr : 21; /* [20:0] */ + u32 rsv_20 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_bug_dbg3_u; + +/* Define the union csr_glb_mb_grp_tx_req_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_grp_tx_req_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_grp_tx_req_h_u; + +/* Define the union csr_glb_mb_grp_tx_req_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_grp_tx_req_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_grp_tx_req_l_u; + +/* Define the union csr_glb_mb_grp_grant_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_grp_grant_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_grp_grant_h_u; + +/* Define the union csr_glb_mb_grp_grant_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_grp_grant_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_grp_grant_l_u; + +/* Define the union csr_ictl_ipush_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_ipush_sop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_ipush_sop_cnt_u; + +/* Define the union csr_ictl_ipush_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_ipush_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_ipush_eop_cnt_u; + +/* Define the union csr_glb_mb_in_grp_tx_req_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_in_grp_tx_req_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_in_grp_tx_req_h_u; + +/* Define the union csr_glb_mb_in_grp_tx_req_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_in_grp_tx_req_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_in_grp_tx_req_l_u; + +/* Define the union csr_glb_mb_in_grp_grant_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_in_grp_grant_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_in_grp_grant_h_u; + +/* Define the union csr_glb_mb_in_grp_grant_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_in_grp_grant_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_in_grp_grant_l_u; + +/* Define the union csr_glb_mb_tx_start_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_tx_start_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_tx_start_cnt_u; + +/* Define the union csr_glb_mb_tx_illegal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_tx_illegal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_tx_illegal_cnt_u; + +/* Define the union csr_glb_mb_tx_illegal_code_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_tx_illegal_code : 6; /* [5:0] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_tx_illegal_code_u; + +/* Define the union csr_glb_mb_fsm_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_mb_buf_fsm_state : 3; /* [2:0] */ + u32 rsv_22 : 1; /* [3] */ + u32 glb_mb_csr_ram_fsm_state : 4; /* [7:4] */ + u32 glb_mb_tx_fsm_state : 3; /* [10:8] */ + u32 rsv_23 : 1; /* [11] */ + u32 glb_mb_rr_fsm_state : 3; /* [14:12] */ + u32 rsv_24 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_mb_fsm_state_u; + +/* Define the union csr_ictl_inbd_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_inbd_fifo_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_inbd_fifo_sts_u; + +/* Define the union csr_ictl_dbl_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_dbl_sop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_dbl_sop_cnt_u; + +/* Define the union csr_ictl_dbl_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ictl_dbl_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ictl_dbl_eop_cnt_u; + +/* Define the union csr_dwqe_drop_no_wr_buf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_drop_no_wr_buf_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_drop_no_wr_buf_cnt_u; + +/* Define the union csr_dwqe_wr_buf_complete_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_wr_buf_complete_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_wr_buf_complete_cnt_u; + +/* Define the union csr_norm_dbl_rx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 norm_dbl_rx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_norm_dbl_rx_cnt_u; + +/* Define the union csr_norm_dbl_force_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 norm_dbl_force_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_norm_dbl_force_drop_u; + +/* Define the union csr_dwqe_rx_buf_bgn_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_rx_buf_bgn : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_rx_buf_bgn_u; + +/* Define the union csr_dwqe_illegal_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_illegal_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_illegal_drop_cnt_u; + +/* Define the union csr_dwqe_dbl_force_drop_no_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dbl_force_drop_no_api : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dbl_force_drop_no_api_u; + +/* Define the union csr_dwqe_dbl_force_drop_aft_api_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_dbl_force_drop_aft_api : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_dbl_force_drop_aft_api_u; + +/* Define the union csr_aeq_fsm_dbg_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aeq_dbg_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_aeq_fsm_dbg_state_u; + +/* Define the union csr_glb_ucpu_msi_func_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ucpu_msi_func_idx : 10; /* [9:0] */ + u32 rsv_25 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ucpu_msi_func_idx_u; + +/* Define the union csr_glb_pcie_inbd_itf_wind_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_26 : 4; /* [3:0] */ + u32 pcie_inbd_itf_wind_16t : 16; /* [19:4] */ + u32 rsv_27 : 10; /* [29:20] */ + u32 pcie_inbd_itf_wind_mode : 1; /* [30] */ + u32 pcie_inbd_itf_wind_start : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_pcie_inbd_itf_wind_ctl_u; + +/* Define the union csr_glb_pcie_inbd_itf_wind_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_inbd_wind_detect_cnt : 20; /* [19:0] */ + u32 rsv_28 : 11; /* [30:20] */ + u32 pcie_inbd_wind_detect_done : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_pcie_inbd_itf_wind_cnt_u; + +/* Define the union csr_glb_pcie_inbd_itf_wind_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_inbd_wind_detect_tlp_cnt : 20; /* [19:0] */ + u32 rsv_29 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_pcie_inbd_itf_wind_tlp_cnt_u; + +/* Define the union csr_glb_dbg_cnt_dbl_grp_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbg_cnt_dbl_grp_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cnt_dbl_grp_en_u; + +/* Define the union csr_glb_dbl_crd_timer_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_timer_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_timer_cfg_u; + +/* Define the union csr_glb_dbl_crd_cfg_port01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cfg_port1 : 16; /* [15:0] */ + u32 glb_dbl_crd_cfg_port0 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cfg_port01_u; + +/* Define the union csr_glb_dbl_crd_cfg_port23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cfg_port3 : 16; /* [15:0] */ + u32 glb_dbl_crd_cfg_port2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cfg_port23_u; + +/* Define the union csr_glb_dbl_crd_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cnt_port0 : 26; /* [25:0] */ + u32 rsv_30 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cnt_port0_u; + +/* Define the union csr_glb_dbl_crd_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cnt_port1 : 26; /* [25:0] */ + u32 rsv_31 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cnt_port1_u; + +/* Define the union csr_glb_dbl_crd_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cnt_port2 : 26; /* [25:0] */ + u32 rsv_32 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cnt_port2_u; + +/* Define the union csr_glb_dbl_crd_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dbl_crd_cnt_port3 : 26; /* [25:0] */ + u32 rsv_33 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbl_crd_cnt_port3_u; + +/* Define the union csr_cpath_enj_a_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_enj_a_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_a_fatal_msk_u; + +/* Define the union csr_cpath_enj_a_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_enj_a_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_a_nonfatal_msk_u; + +/* Define the union csr_cpath_enj_fifo_aful_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_icpl_rdr_fifo_th : 4; /* [3:0] */ + u32 rsv_34 : 4; /* [7:4] */ + u32 oubd_pi_afifo_aful_gap_cpi : 5; /* [12:8] */ + u32 rsv_35 : 3; /* [15:13] */ + u32 oubd_pe_afifo_aful_gap_cpi : 5; /* [20:16] */ + u32 rsv_36 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_fifo_aful_th_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_tile_cnt : 16; /* [15:0] */ + u32 pure_ack_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt0_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_cnt : 16; /* [15:0] */ + u32 cpath_rsv_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt1_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api10_cnt : 16; /* [15:0] */ + u32 cpath_octl_api11_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt2_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api08_cnt : 16; /* [15:0] */ + u32 cpath_octl_api09_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt3_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api06_cnt : 16; /* [15:0] */ + u32 cpath_octl_api07_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt4_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api04_cnt : 16; /* [15:0] */ + u32 cpath_octl_api05_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt5_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api02_cnt : 16; /* [15:0] */ + u32 cpath_octl_api03_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt6_u; + +/* Define the union csr_glb_dbg_cpath_enj_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_octl_api00_cnt : 16; /* [15:0] */ + u32 cpath_octl_api01_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_cnt7_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_oubd_afifo_pe : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo0_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_oubd_sfifo_pe : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo1_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_oubd_sfifo_pi : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo2_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_oubd_sfifo_rsp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo3_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_0sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo4_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_1sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo5_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_2sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo6_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_3sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo7_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_tile : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo8_u; + +/* Define the union csr_glb_dbg_cpath_enj_fifo9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_sfifo_mqm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_enj_fifo9_u; + +/* Define the union csr_glb_dbg_cpath_ro0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro0_u; + +/* Define the union csr_glb_dbg_cpath_ro1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro1_u; + +/* Define the union csr_glb_dbg_cpath_ro2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro2_u; + +/* Define the union csr_glb_dbg_cpath_ro3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro3_u; + +/* Define the union csr_glb_dbg_cpath_ro4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro4_u; + +/* Define the union csr_glb_dbg_cpath_ro5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro5_u; + +/* Define the union csr_glb_dbg_cpath_ro6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro6_u; + +/* Define the union csr_glb_dbg_cpath_ro7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro7_u; + +/* Define the union csr_glb_dbg_cpath_ro8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_0sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro8_u; + +/* Define the union csr_glb_dbg_cpath_ro9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_1sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro9_u; + +/* Define the union csr_glb_dbg_cpath_ro10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_2sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro10_u; + +/* Define the union csr_glb_dbg_cpath_ro11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_3sm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro11_u; + +/* Define the union csr_glb_dbg_cpath_ro12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_tile : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro12_u; + +/* Define the union csr_glb_dbg_cpath_ro13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_mqm : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dbg_cpath_ro13_u; + +/* Define the union csr_cpath_enj_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_enj_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_pls_u; + +/* Define the union csr_ctrl_mem_ctrl_bus0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_mem_ctrl_bus133_128 : 6; /* [5:0] */ + u32 rsv_37 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_mem_ctrl_bus0_u; + +/* Define the union csr_ctrl_mem_ctrl_bus1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_mem_ctrl_bus127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_mem_ctrl_bus1_u; + +/* Define the union csr_ctrl_mem_ctrl_bus2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_mem_ctrl_bus95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_mem_ctrl_bus2_u; + +/* Define the union csr_ctrl_mem_ctrl_bus3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_mem_ctrl_bus63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_mem_ctrl_bus3_u; + +/* Define the union csr_ctrl_mem_ctrl_bus4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_mem_ctrl_bus31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_mem_ctrl_bus4_u; + +/* Define the union csr_ctrl_tcam_ctrl_bus0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_tcam_ctrl_bus9_0 : 10; /* [9:0] */ + u32 rsv_38 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_tcam_ctrl_bus0_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_glb_debug_cfg_u glb_debug_cfg[16]; /* 0 */ + volatile csr_glb_debug_rx_tlp_cnt_u glb_debug_rx_tlp_cnt[16]; /* 4 */ + volatile csr_glb_debug_rx_dbl_cnt_u glb_debug_rx_dbl_cnt[16]; /* 8 */ + volatile csr_glb_debug_rx_dwqe_cnt_u glb_debug_rx_dwqe_cnt[16]; /* C */ + volatile csr_glb_port0_npcpl_tlp_cnt_u glb_port0_npcpl_tlp_cnt; /* 100 */ + volatile csr_glb_port1_npcpl_tlp_cnt_u glb_port1_npcpl_tlp_cnt; /* 104 */ + volatile csr_glb_port2_npcpl_tlp_cnt_u glb_port2_npcpl_tlp_cnt; /* 108 */ + volatile csr_glb_port3_npcpl_tlp_cnt_u glb_port3_npcpl_tlp_cnt; /* 10C */ + volatile csr_glb_port4_npcpl_tlp_cnt_u glb_port4_npcpl_tlp_cnt; /* 110 */ + volatile csr_dfx_ictl_rx_ok_cnt_u dfx_ictl_rx_ok_cnt; /* 114 */ + volatile csr_dfx_ictl_rx_eop_cnt_u dfx_ictl_rx_eop_cnt; /* 118 */ + volatile csr_dfx_ictl_sop_eop_cnt_u dfx_ictl_sop_eop_cnt; /* 11C */ + volatile csr_dfx_ictl_mpu_acc_cnt_u dfx_ictl_mpu_acc_cnt; /* 120 */ + volatile csr_dfx_ictl_ipush_tlp_cnt_u dfx_ictl_ipush_tlp_cnt; /* 124 */ + volatile csr_dfx_ictl_vio_tlp_cnt_u dfx_ictl_vio_tlp_cnt; /* 128 */ + volatile csr_dfx_ictl_rx_io_cnt_u dfx_ictl_rx_io_cnt; /* 12C */ + volatile csr_dfx_ictl_rx_tlp_drop_cnt_u dfx_ictl_rx_tlp_drop_cnt; /* 130 */ + volatile csr_glb_cpi_port_bp_en_cfg_u glb_cpi_port_bp_en_cfg; /* 134 */ + volatile csr_dfx_ictl_fatal_msk0_u dfx_ictl_fatal_msk0; /* 140 */ + volatile csr_dfx_ictl_fatal_msk1_u dfx_ictl_fatal_msk1; /* 144 */ + volatile csr_dfx_ictl_fatal_msk2_u dfx_ictl_fatal_msk2; /* 148 */ + volatile csr_dfx_ictl_nonfatal_msk0_u dfx_ictl_nonfatal_msk0; /* 150 */ + volatile csr_dfx_ictl_nonfatal_msk1_u dfx_ictl_nonfatal_msk1; /* 154 */ + volatile csr_dfx_ictl_nonfatal_msk2_u dfx_ictl_nonfatal_msk2; /* 158 */ + volatile csr_dfx_ictl_err_pls0_u dfx_ictl_err_pls0; /* 160 */ + volatile csr_dfx_ictl_err_pls1_u dfx_ictl_err_pls1; /* 164 */ + volatile csr_dfx_ictl_err_pls2_u dfx_ictl_err_pls2; /* 168 */ + volatile csr_glb_cpi_bp_watch_sts_u glb_cpi_bp_watch_sts; /* 400 */ + volatile csr_glb_cpi_bp_watch_window_u glb_cpi_bp_watch_window; /* 404 */ + volatile csr_glb_cpi_bp_watch_bitmap_u glb_cpi_bp_watch_bitmap; /* 408 */ + volatile csr_glb_cpi_bp_watch_start_u glb_cpi_bp_watch_start; /* 40C */ + volatile csr_glb_cpi_bp_watch_cnt_u glb_cpi_bp_watch_cnt; /* 410 */ + volatile csr_glb_csr_timeout_cnt_u glb_csr_timeout_cnt; /* 414 */ + volatile csr_dwqe_api_no_enough_data_u dwqe_api_no_enough_data; /* 418 */ + volatile csr_dwqe_dbl_no_enough_data_u dwqe_dbl_no_enough_data; /* 41C */ + volatile csr_norm_dbl_drop_cnt_u norm_dbl_drop_cnt; /* 420 */ + volatile csr_norm_dbl_tx_cnt_u norm_dbl_tx_cnt; /* 424 */ + volatile csr_dwqe_dbl_tx_cnt_u dwqe_dbl_tx_cnt; /* 428 */ + volatile csr_dwqe_api_tx_cnt_u dwqe_api_tx_cnt; /* 42C */ + volatile csr_dwqe_buf_bp_msk_u dwqe_buf_bp_msk; /* 430 */ + volatile csr_dwqe_buf_cnt_port_u dwqe_buf_cnt_port; /* 434 */ + volatile csr_dwqe_buf_bp_on_port_u dwqe_buf_bp_on_port; /* 438 */ + volatile csr_dwqe_buf_bp_off_port_u dwqe_buf_bp_off_port; /* 43C */ + volatile csr_dwqe_req_buf_bgn_u dwqe_req_buf_bgn; /* 440 */ + volatile csr_dwqe_dropping_in_tx_u dwqe_dropping_in_tx; /* 444 */ + volatile csr_dwqe_dropping_no_buf_u dwqe_dropping_no_buf; /* 448 */ + volatile csr_dwqe_dbl_without_api_u dwqe_dbl_without_api; /* 44C */ + volatile csr_dwqe_tx_dbl_after_api_u dwqe_tx_dbl_after_api; /* 450 */ + volatile csr_dwqe_no_dbl_after_api_u dwqe_no_dbl_after_api; /* 454 */ + volatile csr_dwqe_buf_overwrite_drop_cnt_u dwqe_buf_overwrite_drop_cnt; /* 458 */ + volatile csr_dwqe_buf_aging_drop_cnt_u dwqe_buf_aging_drop_cnt; /* 45C */ + volatile csr_dwqe_tx_req_fifo_push_cnt_u dwqe_tx_req_fifo_push_cnt; /* 460 */ + volatile csr_dwqe_tx_req_fifo_pop_cnt_u dwqe_tx_req_fifo_pop_cnt; /* 464 */ + volatile csr_dwqe_tx_req_fifo_sts_u dwqe_tx_req_fifo_sts; /* 468 */ + volatile csr_dwqe_dropping_invld_u dwqe_dropping_invld; /* 474 */ + volatile csr_dwqe_sw_force_drop_u dwqe_sw_force_drop; /* 478 */ + volatile csr_ictl_dbl_req_sop_null_u ictl_dbl_req_sop_null; /* 47C */ + volatile csr_cpi_pcie_mb_aeqe_to_mpu_cnt_u cpi_pcie_mb_aeqe_to_mpu_cnt; /* 480 */ + volatile csr_dfx_rx_dwqe_ddb_cnt0_u dfx_rx_dwqe_ddb_cnt0; /* 4A0 */ + volatile csr_dfx_rx_dwqe_ddb_cnt1_u dfx_rx_dwqe_ddb_cnt1; /* 4A4 */ + volatile csr_dfx_rx_dbl_srv_cnt0_u dfx_rx_dbl_srv_cnt0; /* 4A8 */ + volatile csr_dfx_rx_dbl_srv_cnt1_u dfx_rx_dbl_srv_cnt1; /* 4AC */ + volatile csr_glb_dfx_cfg_srv_type_u glb_dfx_cfg_srv_type; /* 4B0 */ + volatile csr_aeq_ci_sw_wr_cnt_u aeq_ci_sw_wr_cnt; /* 4B4 */ + volatile csr_aeq_tx_int_req_cnt_u aeq_tx_int_req_cnt; /* 4BC */ + volatile csr_cpi_ipush_csr_wr_pcie_cnt_u cpi_ipush_csr_wr_pcie_cnt; /* 4C0 */ + volatile csr_cpi_ipush_csr_wr_ucpu_cnt_u cpi_ipush_csr_wr_ucpu_cnt; /* 4C4 */ + volatile csr_cpi_ipush_csr_rd_pcie_cnt_u cpi_ipush_csr_rd_pcie_cnt; /* 4C8 */ + volatile csr_cpi_ipush_csr_rd_ucpu_cnt_u cpi_ipush_csr_rd_ucpu_cnt; /* 4CC */ + volatile csr_cpi_ipush_osch_cpl_cnt_u cpi_ipush_osch_cpl_cnt; /* 4D0 */ + volatile csr_cpi_ipush_ictl_cpl_cnt_u cpi_ipush_ictl_cpl_cnt; /* 4D4 */ + volatile csr_cpi_ipush_apictl_req_cnt_u cpi_ipush_apictl_req_cnt; /* 4D8 */ + volatile csr_cpi_pcie_mb_aeqe_to_dst_cnt_u cpi_pcie_mb_aeqe_to_dst_cnt; /* 4DC */ + volatile csr_cpi_pcie_mb_aeqe_to_src_cnt_u cpi_pcie_mb_aeqe_to_src_cnt; /* 4E0 */ + volatile csr_cpi_pcie_mb_stat_to_src_cnt_u cpi_pcie_mb_stat_to_src_cnt; /* 4E4 */ + volatile csr_cpi_ucpu_mb_aeqe_to_dst_cnt_u cpi_ucpu_mb_aeqe_to_dst_cnt; /* 4E8 */ + volatile csr_cpi_ipush_csr_aeq_req_cnt_u cpi_ipush_csr_aeq_req_cnt; /* 4EC */ + volatile csr_cpi_ipush_csr_ceq_req_cnt_u cpi_ipush_csr_ceq_req_cnt; /* 4F0 */ + volatile csr_cpi_ipush_csr_api_req_cnt_u cpi_ipush_csr_api_req_cnt; /* 4F4 */ + volatile csr_cpi_ipush_csr_intctl_req_cnt_u cpi_ipush_csr_intctl_req_cnt; /* 4F8 */ + volatile csr_cpi_ipush_upitf_clp_req_cnt_u cpi_ipush_upitf_clp_req_cnt; /* 4FC */ + volatile csr_cpi_ram_ecc_inj_err0_u cpi_ram_ecc_inj_err0; /* 500 */ + volatile csr_cpi_ram_ecc_inj_err1_u cpi_ram_ecc_inj_err1; /* 504 */ + volatile csr_cpi_ram_ecc_inj_err2_u cpi_ram_ecc_inj_err2; /* 508 */ + volatile csr_cpi_ram_ecc_inj_err3_u cpi_ram_ecc_inj_err3; /* 50C */ + volatile csr_cpi_ram_ecc_merr0_u cpi_ram_ecc_merr0; /* 520 */ + volatile csr_cpi_ram_ecc_merr1_u cpi_ram_ecc_merr1; /* 524 */ + volatile csr_cpi_ram_ecc_err0_u cpi_ram_ecc_err0; /* 540 */ + volatile csr_cpi_ram_ecc_err1_u cpi_ram_ecc_err1; /* 544 */ + volatile csr_cpi_ram_ecc_err_addr0_u cpi_ram_ecc_err_addr0; /* 560 */ + volatile csr_cpi_ram_ecc_err_addr1_u cpi_ram_ecc_err_addr1; /* 564 */ + volatile csr_cpi_ram_ecc_err_addr2_u cpi_ram_ecc_err_addr2; /* 568 */ + volatile csr_cpi_ram_ecc_err_addr3_u cpi_ram_ecc_err_addr3; /* 56C */ + volatile csr_ipush_reserved0_u ipush_reserved0; /* 5C0 */ + volatile csr_ipush_reserved1_u ipush_reserved1; /* 5C4 */ + volatile csr_ipush_reserved2_u ipush_reserved2; /* 5C8 */ + volatile csr_ipush_reserved3_u ipush_reserved3; /* 5CC */ + volatile csr_glb_cpi_uncrt_err_code0_u glb_cpi_uncrt_err_code0; /* 5D0 */ + volatile csr_glb_cpi_uncrt_err_code1_u glb_cpi_uncrt_err_code1; /* 5D4 */ + volatile csr_glb_cpi_crt_err_code0_u glb_cpi_crt_err_code0; /* 5D8 */ + volatile csr_glb_cpi_crt_err_code1_u glb_cpi_crt_err_code1; /* 5DC */ + volatile csr_dwqe_buf_dbg0_u dwqe_buf_dbg0; /* 5E0 */ + volatile csr_dwqe_buf_dbg1_u dwqe_buf_dbg1; /* 5E4 */ + volatile csr_dwqe_buf_dbg2_u dwqe_buf_dbg2; /* 5E8 */ + volatile csr_dwqe_bug_dbg3_u dwqe_bug_dbg3; /* 5EC */ + volatile csr_glb_mb_grp_tx_req_h_u glb_mb_grp_tx_req_h; /* 5F0 */ + volatile csr_glb_mb_grp_tx_req_l_u glb_mb_grp_tx_req_l; /* 5F4 */ + volatile csr_glb_mb_grp_grant_h_u glb_mb_grp_grant_h; /* 5F8 */ + volatile csr_glb_mb_grp_grant_l_u glb_mb_grp_grant_l; /* 5FC */ + volatile csr_ictl_ipush_sop_cnt_u ictl_ipush_sop_cnt; /* 608 */ + volatile csr_ictl_ipush_eop_cnt_u ictl_ipush_eop_cnt; /* 60C */ + volatile csr_glb_mb_in_grp_tx_req_h_u glb_mb_in_grp_tx_req_h; /* 610 */ + volatile csr_glb_mb_in_grp_tx_req_l_u glb_mb_in_grp_tx_req_l; /* 614 */ + volatile csr_glb_mb_in_grp_grant_h_u glb_mb_in_grp_grant_h; /* 618 */ + volatile csr_glb_mb_in_grp_grant_l_u glb_mb_in_grp_grant_l; /* 61C */ + volatile csr_glb_mb_tx_start_cnt_u glb_mb_tx_start_cnt; /* 620 */ + volatile csr_glb_mb_tx_illegal_cnt_u glb_mb_tx_illegal_cnt; /* 624 */ + volatile csr_glb_mb_tx_illegal_code_u glb_mb_tx_illegal_code; /* 628 */ + volatile csr_glb_mb_fsm_state_u glb_mb_fsm_state; /* 62C */ + volatile csr_ictl_inbd_fifo_sts_u ictl_inbd_fifo_sts; /* 638 */ + volatile csr_ictl_dbl_sop_cnt_u ictl_dbl_sop_cnt; /* 640 */ + volatile csr_ictl_dbl_eop_cnt_u ictl_dbl_eop_cnt; /* 644 */ + volatile csr_dwqe_drop_no_wr_buf_cnt_u dwqe_drop_no_wr_buf_cnt; /* 648 */ + volatile csr_dwqe_wr_buf_complete_cnt_u dwqe_wr_buf_complete_cnt; /* 64C */ + volatile csr_norm_dbl_rx_cnt_u norm_dbl_rx_cnt; /* 690 */ + volatile csr_norm_dbl_force_drop_u norm_dbl_force_drop; /* 694 */ + volatile csr_dwqe_rx_buf_bgn_u dwqe_rx_buf_bgn; /* 698 */ + volatile csr_dwqe_illegal_drop_cnt_u dwqe_illegal_drop_cnt; /* 69C */ + volatile csr_dwqe_dbl_force_drop_no_api_u dwqe_dbl_force_drop_no_api; /* 6A0 */ + volatile csr_dwqe_dbl_force_drop_aft_api_u dwqe_dbl_force_drop_aft_api; /* 6A4 */ + volatile csr_aeq_fsm_dbg_state_u aeq_fsm_dbg_state; /* 6A8 */ + volatile csr_glb_ucpu_msi_func_idx_u glb_ucpu_msi_func_idx; /* 6B0 */ + volatile csr_glb_pcie_inbd_itf_wind_ctl_u glb_pcie_inbd_itf_wind_ctl; /* 6B4 */ + volatile csr_glb_pcie_inbd_itf_wind_cnt_u glb_pcie_inbd_itf_wind_cnt; /* 6B8 */ + volatile csr_glb_pcie_inbd_itf_wind_tlp_cnt_u glb_pcie_inbd_itf_wind_tlp_cnt; /* 6BC */ + volatile csr_glb_dbg_cnt_dbl_grp_en_u glb_dbg_cnt_dbl_grp_en; /* 6C0 */ + volatile csr_glb_dbl_crd_timer_cfg_u glb_dbl_crd_timer_cfg; /* 6C4 */ + volatile csr_glb_dbl_crd_cfg_port01_u glb_dbl_crd_cfg_port01; /* 6C8 */ + volatile csr_glb_dbl_crd_cfg_port23_u glb_dbl_crd_cfg_port23; /* 6CC */ + volatile csr_glb_dbl_crd_cnt_port0_u glb_dbl_crd_cnt_port0; /* 6D0 */ + volatile csr_glb_dbl_crd_cnt_port1_u glb_dbl_crd_cnt_port1; /* 6D4 */ + volatile csr_glb_dbl_crd_cnt_port2_u glb_dbl_crd_cnt_port2; /* 6D8 */ + volatile csr_glb_dbl_crd_cnt_port3_u glb_dbl_crd_cnt_port3; /* 6DC */ + volatile csr_cpath_enj_a_fatal_msk_u cpath_enj_a_fatal_msk; /* 700 */ + volatile csr_cpath_enj_a_nonfatal_msk_u cpath_enj_a_nonfatal_msk; /* 704 */ + volatile csr_cpath_enj_fifo_aful_th_u cpath_enj_fifo_aful_th; /* 708 */ + volatile csr_glb_dbg_cpath_enj_cnt0_u glb_dbg_cpath_enj_cnt0; /* 710 */ + volatile csr_glb_dbg_cpath_enj_cnt1_u glb_dbg_cpath_enj_cnt1; /* 714 */ + volatile csr_glb_dbg_cpath_enj_cnt2_u glb_dbg_cpath_enj_cnt2; /* 718 */ + volatile csr_glb_dbg_cpath_enj_cnt3_u glb_dbg_cpath_enj_cnt3; /* 71C */ + volatile csr_glb_dbg_cpath_enj_cnt4_u glb_dbg_cpath_enj_cnt4; /* 720 */ + volatile csr_glb_dbg_cpath_enj_cnt5_u glb_dbg_cpath_enj_cnt5; /* 724 */ + volatile csr_glb_dbg_cpath_enj_cnt6_u glb_dbg_cpath_enj_cnt6; /* 728 */ + volatile csr_glb_dbg_cpath_enj_cnt7_u glb_dbg_cpath_enj_cnt7; /* 72C */ + volatile csr_glb_dbg_cpath_enj_fifo0_u glb_dbg_cpath_enj_fifo0; /* 730 */ + volatile csr_glb_dbg_cpath_enj_fifo1_u glb_dbg_cpath_enj_fifo1; /* 734 */ + volatile csr_glb_dbg_cpath_enj_fifo2_u glb_dbg_cpath_enj_fifo2; /* 738 */ + volatile csr_glb_dbg_cpath_enj_fifo3_u glb_dbg_cpath_enj_fifo3; /* 73C */ + volatile csr_glb_dbg_cpath_enj_fifo4_u glb_dbg_cpath_enj_fifo4; /* 740 */ + volatile csr_glb_dbg_cpath_enj_fifo5_u glb_dbg_cpath_enj_fifo5; /* 744 */ + volatile csr_glb_dbg_cpath_enj_fifo6_u glb_dbg_cpath_enj_fifo6; /* 748 */ + volatile csr_glb_dbg_cpath_enj_fifo7_u glb_dbg_cpath_enj_fifo7; /* 74C */ + volatile csr_glb_dbg_cpath_enj_fifo8_u glb_dbg_cpath_enj_fifo8; /* 750 */ + volatile csr_glb_dbg_cpath_enj_fifo9_u glb_dbg_cpath_enj_fifo9; /* 754 */ + volatile csr_glb_dbg_cpath_ro0_u glb_dbg_cpath_ro0; /* 758 */ + volatile csr_glb_dbg_cpath_ro1_u glb_dbg_cpath_ro1; /* 75C */ + volatile csr_glb_dbg_cpath_ro2_u glb_dbg_cpath_ro2; /* 760 */ + volatile csr_glb_dbg_cpath_ro3_u glb_dbg_cpath_ro3; /* 764 */ + volatile csr_glb_dbg_cpath_ro4_u glb_dbg_cpath_ro4; /* 768 */ + volatile csr_glb_dbg_cpath_ro5_u glb_dbg_cpath_ro5; /* 76C */ + volatile csr_glb_dbg_cpath_ro6_u glb_dbg_cpath_ro6; /* 770 */ + volatile csr_glb_dbg_cpath_ro7_u glb_dbg_cpath_ro7; /* 774 */ + volatile csr_glb_dbg_cpath_ro8_u glb_dbg_cpath_ro8; /* 778 */ + volatile csr_glb_dbg_cpath_ro9_u glb_dbg_cpath_ro9; /* 77C */ + volatile csr_glb_dbg_cpath_ro10_u glb_dbg_cpath_ro10; /* 780 */ + volatile csr_glb_dbg_cpath_ro11_u glb_dbg_cpath_ro11; /* 784 */ + volatile csr_glb_dbg_cpath_ro12_u glb_dbg_cpath_ro12; /* 788 */ + volatile csr_glb_dbg_cpath_ro13_u glb_dbg_cpath_ro13; /* 78C */ + volatile csr_cpath_enj_pls_u cpath_enj_pls; /* 7A0 */ + volatile csr_ctrl_mem_ctrl_bus0_u ctrl_mem_ctrl_bus0; /* 7B0 */ + volatile csr_ctrl_mem_ctrl_bus1_u ctrl_mem_ctrl_bus1; /* 7B4 */ + volatile csr_ctrl_mem_ctrl_bus2_u ctrl_mem_ctrl_bus2; /* 7B8 */ + volatile csr_ctrl_mem_ctrl_bus3_u ctrl_mem_ctrl_bus3; /* 7BC */ + volatile csr_ctrl_mem_ctrl_bus4_u ctrl_mem_ctrl_bus4; /* 7C0 */ + volatile csr_ctrl_tcam_ctrl_bus0_u ctrl_tcam_ctrl_bus0; /* 7C4 */ +} S_dfx_glb_csr_REGS_TYPE; + +/* Declare the struct pointor of the module dfx_glb_csr */ +extern volatile S_dfx_glb_csr_REGS_TYPE *gopdfx_glb_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetGLB_DEBUG_CFG_glb_dbg_func_idx(unsigned int uglb_dbg_func_idx); +int iSetGLB_DEBUG_CFG_glb_dbg_bar_bitmap(unsigned int uglb_dbg_bar_bitmap); +int iSetGLB_DEBUG_RX_TLP_CNT_glb_dbg_rx_mwr_tlp_cnt(unsigned int uglb_dbg_rx_mwr_tlp_cnt); +int iSetGLB_DEBUG_RX_TLP_CNT_glb_dbg_rx_mrd_tlp_cnt(unsigned int uglb_dbg_rx_mrd_tlp_cnt); +int iSetGLB_DEBUG_RX_DBL_CNT_glb_dbg_rx_dbl_tlp_cnt(unsigned int uglb_dbg_rx_dbl_tlp_cnt); +int iSetGLB_DEBUG_RX_DWQE_CNT_glb_dbg_rx_dwqe_tlp_cnt(unsigned int uglb_dbg_rx_dwqe_tlp_cnt); +int iSetGLB_PORT0_NPCPL_TLP_CNT_cpi_port0_tx_cpl_cnt(unsigned int ucpi_port0_tx_cpl_cnt); +int iSetGLB_PORT0_NPCPL_TLP_CNT_cpi_port0_rx_np_cnt(unsigned int ucpi_port0_rx_np_cnt); +int iSetGLB_PORT1_NPCPL_TLP_CNT_cpi_port1_tx_cpl_cnt(unsigned int ucpi_port1_tx_cpl_cnt); +int iSetGLB_PORT1_NPCPL_TLP_CNT_cpi_port1_rx_np_cnt(unsigned int ucpi_port1_rx_np_cnt); +int iSetGLB_PORT2_NPCPL_TLP_CNT_cpi_port2_tx_cpl_cnt(unsigned int ucpi_port2_tx_cpl_cnt); +int iSetGLB_PORT2_NPCPL_TLP_CNT_cpi_port2_rx_np_cnt(unsigned int ucpi_port2_rx_np_cnt); +int iSetGLB_PORT3_NPCPL_TLP_CNT_cpi_port3_tx_cpl_cnt(unsigned int ucpi_port3_tx_cpl_cnt); +int iSetGLB_PORT3_NPCPL_TLP_CNT_cpi_port3_rx_np_cnt(unsigned int ucpi_port3_rx_np_cnt); +int iSetGLB_PORT4_NPCPL_TLP_CNT_cpi_port4_tx_cpl_cnt(unsigned int ucpi_port4_tx_cpl_cnt); +int iSetGLB_PORT4_NPCPL_TLP_CNT_cpi_port4_rx_np_cnt(unsigned int ucpi_port4_rx_np_cnt); +int iSetDFX_ICTL_RX_OK_CNT_dfx_ictl_sop_cnt(unsigned int udfx_ictl_sop_cnt); +int iSetDFX_ICTL_RX_OK_CNT_dfx_ictl_ok_cnt(unsigned int udfx_ictl_ok_cnt); +int iSetDFX_ICTL_RX_EOP_CNT_dfx_ictl_vld_cnt(unsigned int udfx_ictl_vld_cnt); +int iSetDFX_ICTL_RX_EOP_CNT_dfx_ictl_eop_cnt(unsigned int udfx_ictl_eop_cnt); +int iSetDFX_ICTL_SOP_EOP_CNT_ictl_osch_tx_cpl_cnt(unsigned int uictl_osch_tx_cpl_cnt); +int iSetDFX_ICTL_SOP_EOP_CNT_dfx_ictl_sop_eop_cnt(unsigned int udfx_ictl_sop_eop_cnt); +int iSetDFX_ICTL_MPU_ACC_CNT_mpu_apb_rd_cnt(unsigned int umpu_apb_rd_cnt); +int iSetDFX_ICTL_MPU_ACC_CNT_mpu_apb_wr_cnt(unsigned int umpu_apb_wr_cnt); +int iSetDFX_ICTL_IPUSH_TLP_CNT_ictl_dwqe_tlp_cnt(unsigned int uictl_dwqe_tlp_cnt); +int iSetDFX_ICTL_IPUSH_TLP_CNT_ictl_ipush_tlp_cnt(unsigned int uictl_ipush_tlp_cnt); +int iSetDFX_ICTL_VIO_TLP_CNT_dfx_ictl_rx_mem_cnt(unsigned int udfx_ictl_rx_mem_cnt); +int iSetDFX_ICTL_VIO_TLP_CNT_ictl_vio_tlp_cnt(unsigned int uictl_vio_tlp_cnt); +int iSetDFX_ICTL_RX_IO_CNT_dfx_ictl_rx_rom_cnt(unsigned int udfx_ictl_rx_rom_cnt); +int iSetDFX_ICTL_RX_IO_CNT_dfx_ictl_rx_io_cnt(unsigned int udfx_ictl_rx_io_cnt); +int iSetDFX_ICTL_RX_TLP_DROP_CNT_dfx_ictl_rx_uns_np_cnt(unsigned int udfx_ictl_rx_uns_np_cnt); +int iSetDFX_ICTL_RX_TLP_DROP_CNT_dfx_ictl_rx_tlp_drop_cnt(unsigned int udfx_ictl_rx_tlp_drop_cnt); +int iSetGLB_CPI_PORT_BP_EN_CFG_cpi_port_bp_en_cfg(unsigned int ucpi_port_bp_en_cfg); +int iSetDFX_ICTL_FATAL_MSK0_dfx_ictl_fatal_msk95_64(unsigned int udfx_ictl_fatal_msk95_64); +int iSetDFX_ICTL_FATAL_MSK1_dfx_ictl_fatal_msk63_32(unsigned int udfx_ictl_fatal_msk63_32); +int iSetDFX_ICTL_FATAL_MSK2_dfx_ictl_fatal_msk31_0(unsigned int udfx_ictl_fatal_msk31_0); +int iSetDFX_ICTL_NONFATAL_MSK0_dfx_ictl_nonfatal_msk95_64(unsigned int udfx_ictl_nonfatal_msk95_64); +int iSetDFX_ICTL_NONFATAL_MSK1_dfx_ictl_nonfatal_msk63_32(unsigned int udfx_ictl_nonfatal_msk63_32); +int iSetDFX_ICTL_NONFATAL_MSK2_dfx_ictl_nonfatal_msk31_0(unsigned int udfx_ictl_nonfatal_msk31_0); +int iSetDFX_ICTL_ERR_PLS0_dfx_ictl_err_pls95_64(unsigned int udfx_ictl_err_pls95_64); +int iSetDFX_ICTL_ERR_PLS1_dfx_ictl_err_pls63_32(unsigned int udfx_ictl_err_pls63_32); +int iSetDFX_ICTL_ERR_PLS2_dfx_ictl_err_pls31_0(unsigned int udfx_ictl_err_pls31_0); +int iSetGLB_CPI_BP_WATCH_STS_glb_cpi_bp_watch_sts(unsigned int uglb_cpi_bp_watch_sts); +int iSetGLB_CPI_BP_WATCH_WINDOW_glb_cpi_bp_watch_window(unsigned int uglb_cpi_bp_watch_window); +int iSetGLB_CPI_BP_WATCH_BITMAP_glb_cpi_bp_watch_bitmap(unsigned int uglb_cpi_bp_watch_bitmap); +int iSetGLB_CPI_BP_WATCH_START_glb_cpi_bp_watch_start(unsigned int uglb_cpi_bp_watch_start); +int iSetGLB_CPI_BP_WATCH_CNT_glb_cpi_bp_watch_cnt(unsigned int uglb_cpi_bp_watch_cnt); +int iSetGLB_CSR_TIMEOUT_CNT_glb_csr_timeout_cnt(unsigned int uglb_csr_timeout_cnt); +int iSetGLB_CSR_TIMEOUT_CNT_glb_non_csr_timeout_cnt(unsigned int uglb_non_csr_timeout_cnt); +int iSetDWQE_API_NO_ENOUGH_DATA_dwqe_api_no_enough_data(unsigned int udwqe_api_no_enough_data); +int iSetDWQE_DBL_NO_ENOUGH_DATA_dwqe_dbl_no_enough_data(unsigned int udwqe_dbl_no_enough_data); +int iSetNORM_DBL_DROP_CNT_norm_dbl_illegal_drop_cnt(unsigned int unorm_dbl_illegal_drop_cnt); +int iSetNORM_DBL_TX_CNT_norm_dbl_tx_cnt(unsigned int unorm_dbl_tx_cnt); +int iSetDWQE_DBL_TX_CNT_dwqe_dbl_tx_cnt(unsigned int udwqe_dbl_tx_cnt); +int iSetDWQE_API_TX_CNT_dwqe_api_tx_cnt(unsigned int udwqe_api_tx_cnt); +int iSetDWQE_BUF_BP_MSK_dwqe_buf_bp_sts(unsigned int udwqe_buf_bp_sts); +int iSetDWQE_BUF_BP_MSK_dwqe_buf_bp_en(unsigned int udwqe_buf_bp_en); +int iSetDWQE_BUF_CNT_PORT_dwqe_buf_cnt_port3(unsigned int udwqe_buf_cnt_port3); +int iSetDWQE_BUF_CNT_PORT_dwqe_buf_cnt_port2(unsigned int udwqe_buf_cnt_port2); +int iSetDWQE_BUF_CNT_PORT_dwqe_buf_cnt_port1(unsigned int udwqe_buf_cnt_port1); +int iSetDWQE_BUF_CNT_PORT_dwqe_buf_cnt_port0(unsigned int udwqe_buf_cnt_port0); +int iSetDWQE_BUF_BP_ON_PORT_dwqe_buf_bp_on_port3(unsigned int udwqe_buf_bp_on_port3); +int iSetDWQE_BUF_BP_ON_PORT_dwqe_buf_bp_on_port2(unsigned int udwqe_buf_bp_on_port2); +int iSetDWQE_BUF_BP_ON_PORT_dwqe_buf_bp_on_port1(unsigned int udwqe_buf_bp_on_port1); +int iSetDWQE_BUF_BP_ON_PORT_dwqe_buf_bp_on_port0(unsigned int udwqe_buf_bp_on_port0); +int iSetDWQE_BUF_BP_OFF_PORT_dwqe_buf_bp_off_port3(unsigned int udwqe_buf_bp_off_port3); +int iSetDWQE_BUF_BP_OFF_PORT_dwqe_buf_bp_off_port2(unsigned int udwqe_buf_bp_off_port2); +int iSetDWQE_BUF_BP_OFF_PORT_dwqe_buf_bp_off_port1(unsigned int udwqe_buf_bp_off_port1); +int iSetDWQE_BUF_BP_OFF_PORT_dwqe_buf_bp_off_port0(unsigned int udwqe_buf_bp_off_port0); +int iSetDWQE_REQ_BUF_BGN_dwqe_req_buf_bgn(unsigned int udwqe_req_buf_bgn); +int iSetDWQE_DROPPING_IN_TX_dwqe_dropping_in_tx(unsigned int udwqe_dropping_in_tx); +int iSetDWQE_DROPPING_NO_BUF_dwqe_dropping_no_buf(unsigned int udwqe_dropping_no_buf); +int iSetDWQE_DBL_WITHOUT_API_dwqe_dbl_without_api(unsigned int udwqe_dbl_without_api); +int iSetDWQE_TX_DBL_AFTER_API_dwqe_tx_dbl_after_api(unsigned int udwqe_tx_dbl_after_api); +int iSetDWQE_NO_DBL_AFTER_API_dwqe_no_dbl_after_api(unsigned int udwqe_no_dbl_after_api); +int iSetDWQE_BUF_OVERWRITE_DROP_CNT_dwqe_buf_overwrite_drop_cnt(unsigned int udwqe_buf_overwrite_drop_cnt); +int iSetDWQE_BUF_AGING_DROP_CNT_dwqe_buf_aging_drop_cnt(unsigned int udwqe_buf_aging_drop_cnt); +int iSetDWQE_TX_REQ_FIFO_PUSH_CNT_dwqe_tx_req_fifo_push_cnt(unsigned int udwqe_tx_req_fifo_push_cnt); +int iSetDWQE_TX_REQ_FIFO_POP_CNT_dwqe_tx_req_fifo_pop_cnt(unsigned int udwqe_tx_req_fifo_pop_cnt); +int iSetDWQE_TX_REQ_FIFO_STS_dwqe_tx_req_fifo_sts(unsigned int udwqe_tx_req_fifo_sts); +int iSetDWQE_TX_REQ_FIFO_STS_dwqe_tx_req_fifo_overflow(unsigned int udwqe_tx_req_fifo_overflow); +int iSetDWQE_TX_REQ_FIFO_STS_dwqe_buf_alc_cnt(unsigned int udwqe_buf_alc_cnt); +int iSetDWQE_TX_REQ_FIFO_STS_dwqe_tx_req_fifo_cnt(unsigned int udwqe_tx_req_fifo_cnt); +int iSetDWQE_DROPPING_INVLD_dwqe_dropping_invld(unsigned int udwqe_dropping_invld); +int iSetDWQE_SW_FORCE_DROP_dwqe_sw_force_drop(unsigned int udwqe_sw_force_drop); +int iSetICTL_DBL_REQ_SOP_NULL_ictl_dbl_req_sop_null(unsigned int uictl_dbl_req_sop_null); +int iSetCPI_PCIE_MB_AEQE_TO_MPU_CNT_glb_pcie_mb_aeqe_to_mpu_cnt(unsigned int uglb_pcie_mb_aeqe_to_mpu_cnt); +int iSetDFX_RX_DWQE_DDB_CNT0_dfx_rx_dwqe_ddb1_cnt(unsigned int udfx_rx_dwqe_ddb1_cnt); +int iSetDFX_RX_DWQE_DDB_CNT0_dfx_rx_dwqe_ddb0_cnt(unsigned int udfx_rx_dwqe_ddb0_cnt); +int iSetDFX_RX_DWQE_DDB_CNT1_dfx_rx_dwqe_ddb3_cnt(unsigned int udfx_rx_dwqe_ddb3_cnt); +int iSetDFX_RX_DWQE_DDB_CNT1_dfx_rx_dwqe_ddb2_cnt(unsigned int udfx_rx_dwqe_ddb2_cnt); +int iSetDFX_RX_DBL_SRV_CNT0_dfx_rx_dbl_srv1_cnt(unsigned int udfx_rx_dbl_srv1_cnt); +int iSetDFX_RX_DBL_SRV_CNT0_dfx_rx_dbl_srv0_cnt(unsigned int udfx_rx_dbl_srv0_cnt); +int iSetDFX_RX_DBL_SRV_CNT1_dfx_rx_dbl_srv3_cnt(unsigned int udfx_rx_dbl_srv3_cnt); +int iSetDFX_RX_DBL_SRV_CNT1_dfx_rx_dbl_srv2_cnt(unsigned int udfx_rx_dbl_srv2_cnt); +int iSetGLB_DFX_CFG_SRV_TYPE_glb_dfx_cfg0_srv_type(unsigned int uglb_dfx_cfg0_srv_type); +int iSetGLB_DFX_CFG_SRV_TYPE_glb_dfx_cfg1_srv_type(unsigned int uglb_dfx_cfg1_srv_type); +int iSetGLB_DFX_CFG_SRV_TYPE_glb_dfx_cfg2_srv_type(unsigned int uglb_dfx_cfg2_srv_type); +int iSetGLB_DFX_CFG_SRV_TYPE_glb_dfx_cfg3_srv_type(unsigned int uglb_dfx_cfg3_srv_type); +int iSetAEQ_CI_SW_WR_CNT_aeq_ci_sw_wr_cnt(unsigned int uaeq_ci_sw_wr_cnt); +int iSetAEQ_TX_INT_REQ_CNT_aeq_tx_int_req_cnt(unsigned int uaeq_tx_int_req_cnt); +int iSetCPI_IPUSH_CSR_WR_PCIE_CNT_glb_ipush_csr_wr_pcie_cnt(unsigned int uglb_ipush_csr_wr_pcie_cnt); +int iSetCPI_IPUSH_CSR_WR_UCPU_CNT_glb_ipush_csr_wr_ucpu_cnt(unsigned int uglb_ipush_csr_wr_ucpu_cnt); +int iSetCPI_IPUSH_CSR_RD_PCIE_CNT_glb_ipush_csr_rd_pcie_cnt(unsigned int uglb_ipush_csr_rd_pcie_cnt); +int iSetCPI_IPUSH_CSR_RD_UCPU_CNT_glb_ipush_csr_rd_ucpu_cnt(unsigned int uglb_ipush_csr_rd_ucpu_cnt); +int iSetCPI_IPUSH_OSCH_CPL_CNT_glb_ipush_osch_cpl_cnt(unsigned int uglb_ipush_osch_cpl_cnt); +int iSetCPI_IPUSH_ICTL_CPL_CNT_glb_ipush_ictl_cpl_cnt(unsigned int uglb_ipush_ictl_cpl_cnt); +int iSetCPI_IPUSH_APICTL_REQ_CNT_glb_ipush_apictl_req_cnt(unsigned int uglb_ipush_apictl_req_cnt); +int iSetCPI_PCIE_MB_AEQE_TO_DST_CNT_glb_pcie_mb_aeqe_to_dst_cnt(unsigned int uglb_pcie_mb_aeqe_to_dst_cnt); +int iSetCPI_PCIE_MB_AEQE_TO_SRC_CNT_glb_pcie_mb_aeqe_to_src_cnt(unsigned int uglb_pcie_mb_aeqe_to_src_cnt); +int iSetCPI_PCIE_MB_STAT_TO_SRC_CNT_glb_pcie_mb_stat_to_src_cnt(unsigned int uglb_pcie_mb_stat_to_src_cnt); +int iSetCPI_UCPU_MB_AEQE_TO_DST_CNT_glb_ucpu_mb_aeqe_to_dst_cnt(unsigned int uglb_ucpu_mb_aeqe_to_dst_cnt); +int iSetCPI_IPUSH_CSR_AEQ_REQ_CNT_glb_ipush_csr_aeq_req_cnt(unsigned int uglb_ipush_csr_aeq_req_cnt); +int iSetCPI_IPUSH_CSR_CEQ_REQ_CNT_glb_ipush_csr_ceq_req_cnt(unsigned int uglb_ipush_csr_ceq_req_cnt); +int iSetCPI_IPUSH_CSR_API_REQ_CNT_glb_ipush_csr_api_req_cnt(unsigned int uglb_ipush_csr_api_req_cnt); +int iSetCPI_IPUSH_CSR_INTCTL_REQ_CNT_glb_ipush_csr_intctl_req_cnt(unsigned int uglb_ipush_csr_intctl_req_cnt); +int iSetCPI_IPUSH_UPITF_CLP_REQ_CNT_glb_ipush_upitf_clp_req_cnt(unsigned int uglb_ipush_upitf_clp_req_cnt); +int iSetCPI_RAM_ECC_INJ_ERR0_glb_cpi_ecc_inj_req0(unsigned int uglb_cpi_ecc_inj_req0); +int iSetCPI_RAM_ECC_INJ_ERR1_glb_cpi_ecc_inj_req1(unsigned int uglb_cpi_ecc_inj_req1); +int iSetCPI_RAM_ECC_INJ_ERR2_glb_cpi_ecc_inj_req2(unsigned int uglb_cpi_ecc_inj_req2); +int iSetCPI_RAM_ECC_INJ_ERR3_glb_cpi_ecc_inj_req3(unsigned int uglb_cpi_ecc_inj_req3); +int iSetCPI_RAM_ECC_MERR0_glb_cpi_ecc_merr0(unsigned int uglb_cpi_ecc_merr0); +int iSetCPI_RAM_ECC_MERR1_glb_cpi_ecc_merr1(unsigned int uglb_cpi_ecc_merr1); +int iSetCPI_RAM_ECC_ERR0_glb_cpi_ecc_err0(unsigned int uglb_cpi_ecc_err0); +int iSetCPI_RAM_ECC_ERR1_glb_cpi_ecc_err1(unsigned int uglb_cpi_ecc_err1); +int iSetCPI_RAM_ECC_ERR_ADDR0_glb_cpi_ecc_err_addr0(unsigned int uglb_cpi_ecc_err_addr0); +int iSetCPI_RAM_ECC_ERR_ADDR1_glb_cpi_ecc_err_addr1(unsigned int uglb_cpi_ecc_err_addr1); +int iSetCPI_RAM_ECC_ERR_ADDR2_glb_cpi_ecc_err_addr2(unsigned int uglb_cpi_ecc_err_addr2); +int iSetCPI_RAM_ECC_ERR_ADDR3_glb_cpi_ecc_err_addr3(unsigned int uglb_cpi_ecc_err_addr3); +int iSetIPUSH_RESERVED0_ipush_resved0(unsigned int uipush_resved0); +int iSetIPUSH_RESERVED1_ipush_resved1(unsigned int uipush_resved1); +int iSetIPUSH_RESERVED2_ipush_resved2(unsigned int uipush_resved2); +int iSetIPUSH_RESERVED3_ipush_resved3(unsigned int uipush_resved3); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_cmisc_uncrt_err_code(unsigned int uglb_cpi_cmisc_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_cpath_dma_uncrt_err_code(unsigned int uglb_cpi_cpath_dma_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_dtif_uncrt_err_code(unsigned int uglb_cpi_dtif_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_ictl_uncrt_err_code(unsigned int uglb_cpi_ictl_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_qmap_uncrt_err_code(unsigned int uglb_cpi_qmap_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_apictl_uncrt_err_code(unsigned int uglb_cpi_apictl_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_dpath_i_uncrt_err_code(unsigned int uglb_cpi_dpath_i_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE0_glb_cpi_dpath_o_uncrt_err_code(unsigned int uglb_cpi_dpath_o_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE1_glb_cpi_ipush_uncrt_err_code(unsigned int uglb_cpi_ipush_uncrt_err_code); +int iSetGLB_CPI_UNCRT_ERR_CODE1_glb_cpi_cpath_uncrt_err_code(unsigned int uglb_cpi_cpath_uncrt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_cmisc_crt_err_code(unsigned int uglb_cpi_cmisc_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_cpath_dma_crt_err_code(unsigned int uglb_cpi_cpath_dma_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_dtif_crt_err_code(unsigned int uglb_cpi_dtif_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_ictl_crt_err_code(unsigned int uglb_cpi_ictl_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_qmap_crt_err_code(unsigned int uglb_cpi_qmap_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_apictl_crt_err_code(unsigned int uglb_cpi_apictl_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_dpath_i_crt_err_code(unsigned int uglb_cpi_dpath_i_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE0_glb_cpi_dpath_o_crt_err_code(unsigned int uglb_cpi_dpath_o_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE1_glb_cpi_ipush_crt_err_code(unsigned int uglb_cpi_ipush_crt_err_code); +int iSetGLB_CPI_CRT_ERR_CODE1_glb_cpi_cpath_crt_err_code(unsigned int uglb_cpi_cpath_crt_err_code); +int iSetDWQE_BUF_DBG0_dwqe_buf_dbg_src_tag_l(unsigned int udwqe_buf_dbg_src_tag_l); +int iSetDWQE_BUF_DBG0_dwqe_buf_dbg_status(unsigned int udwqe_buf_dbg_status); +int iSetDWQE_BUF_DBG1_dwqe_buf_dbg_exp_qw_num(unsigned int udwqe_buf_dbg_exp_qw_num); +int iSetDWQE_BUF_DBG1_dwqe_buf_dbg_rx_qw_cnt(unsigned int udwqe_buf_dbg_rx_qw_cnt); +int iSetDWQE_BUF_DBG1_dwqe_buf_dbg_no_dbl(unsigned int udwqe_buf_dbg_no_dbl); +int iSetDWQE_BUF_DBG1_dwqe_buf_dbg_aging_flag(unsigned int udwqe_buf_dbg_aging_flag); +int iSetDWQE_BUF_DBG2_dwqe_buf_dbg_idx(unsigned int udwqe_buf_dbg_idx); +int iSetDWQE_BUF_DBG2_dwqe_buf_dbg_watch_en(unsigned int udwqe_buf_dbg_watch_en); +int iSetDWQE_BUF_DBG2_dwqe_buf_dbg_force_ivld(unsigned int udwqe_buf_dbg_force_ivld); +int iSetDWQE_BUG_DBG3_dwqe_buf_dbg_host_addr(unsigned int udwqe_buf_dbg_host_addr); +int iSetGLB_MB_GRP_TX_REQ_H_glb_mb_grp_tx_req_h(unsigned int uglb_mb_grp_tx_req_h); +int iSetGLB_MB_GRP_TX_REQ_L_glb_mb_grp_tx_req_l(unsigned int uglb_mb_grp_tx_req_l); +int iSetGLB_MB_GRP_GRANT_H_glb_mb_grp_grant_h(unsigned int uglb_mb_grp_grant_h); +int iSetGLB_MB_GRP_GRANT_L_glb_mb_grp_grant_l(unsigned int uglb_mb_grp_grant_l); +int iSetICTL_IPUSH_SOP_CNT_ictl_ipush_sop_cnt(unsigned int uictl_ipush_sop_cnt); +int iSetICTL_IPUSH_EOP_CNT_ictl_ipush_eop_cnt(unsigned int uictl_ipush_eop_cnt); +int iSetGLB_MB_IN_GRP_TX_REQ_H_glb_mb_in_grp_tx_req_h(unsigned int uglb_mb_in_grp_tx_req_h); +int iSetGLB_MB_IN_GRP_TX_REQ_L_glb_mb_in_grp_tx_req_l(unsigned int uglb_mb_in_grp_tx_req_l); +int iSetGLB_MB_IN_GRP_GRANT_H_glb_mb_in_grp_grant_h(unsigned int uglb_mb_in_grp_grant_h); +int iSetGLB_MB_IN_GRP_GRANT_L_glb_mb_in_grp_grant_l(unsigned int uglb_mb_in_grp_grant_l); +int iSetGLB_MB_TX_START_CNT_glb_mb_tx_start_cnt(unsigned int uglb_mb_tx_start_cnt); +int iSetGLB_MB_TX_ILLEGAL_CNT_glb_mb_tx_illegal_cnt(unsigned int uglb_mb_tx_illegal_cnt); +int iSetGLB_MB_TX_ILLEGAL_CODE_glb_mb_tx_illegal_code(unsigned int uglb_mb_tx_illegal_code); +int iSetGLB_MB_FSM_STATE_glb_mb_buf_fsm_state(unsigned int uglb_mb_buf_fsm_state); +int iSetGLB_MB_FSM_STATE_glb_mb_csr_ram_fsm_state(unsigned int uglb_mb_csr_ram_fsm_state); +int iSetGLB_MB_FSM_STATE_glb_mb_tx_fsm_state(unsigned int uglb_mb_tx_fsm_state); +int iSetGLB_MB_FSM_STATE_glb_mb_rr_fsm_state(unsigned int uglb_mb_rr_fsm_state); +int iSetICTL_INBD_FIFO_STS_ictl_inbd_fifo_st(unsigned int uictl_inbd_fifo_st); +int iSetICTL_DBL_SOP_CNT_ictl_dbl_sop_cnt(unsigned int uictl_dbl_sop_cnt); +int iSetICTL_DBL_EOP_CNT_ictl_dbl_eop_cnt(unsigned int uictl_dbl_eop_cnt); +int iSetDWQE_DROP_NO_WR_BUF_CNT_dwqe_drop_no_wr_buf_cnt(unsigned int udwqe_drop_no_wr_buf_cnt); +int iSetDWQE_WR_BUF_COMPLETE_CNT_dwqe_wr_buf_complete_cnt(unsigned int udwqe_wr_buf_complete_cnt); +int iSetNORM_DBL_RX_CNT_norm_dbl_rx_cnt(unsigned int unorm_dbl_rx_cnt); +int iSetNORM_DBL_FORCE_DROP_norm_dbl_force_drop(unsigned int unorm_dbl_force_drop); +int iSetDWQE_RX_BUF_BGN_dwqe_rx_buf_bgn(unsigned int udwqe_rx_buf_bgn); +int iSetDWQE_ILLEGAL_DROP_CNT_dwqe_illegal_drop(unsigned int udwqe_illegal_drop); +int iSetDWQE_DBL_FORCE_DROP_NO_API_dwqe_dbl_force_drop_no_api(unsigned int udwqe_dbl_force_drop_no_api); +int iSetDWQE_DBL_FORCE_DROP_AFT_API_dwqe_dbl_force_drop_aft_api(unsigned int udwqe_dbl_force_drop_aft_api); +int iSetAEQ_FSM_DBG_STATE_aeq_dbg_status(unsigned int uaeq_dbg_status); +int iSetGLB_UCPU_MSI_FUNC_IDX_glb_ucpu_msi_func_idx(unsigned int uglb_ucpu_msi_func_idx); +int iSetGLB_PCIE_INBD_ITF_WIND_CTL_pcie_inbd_itf_wind_16t(unsigned int upcie_inbd_itf_wind_16t); +int iSetGLB_PCIE_INBD_ITF_WIND_CTL_pcie_inbd_itf_wind_mode(unsigned int upcie_inbd_itf_wind_mode); +int iSetGLB_PCIE_INBD_ITF_WIND_CTL_pcie_inbd_itf_wind_start(unsigned int upcie_inbd_itf_wind_start); +int iSetGLB_PCIE_INBD_ITF_WIND_CNT_pcie_inbd_wind_detect_cnt(unsigned int upcie_inbd_wind_detect_cnt); +int iSetGLB_PCIE_INBD_ITF_WIND_CNT_pcie_inbd_wind_detect_done(unsigned int upcie_inbd_wind_detect_done); +int iSetGLB_PCIE_INBD_ITF_WIND_TLP_CNT_pcie_inbd_wind_detect_tlp_cnt(unsigned int upcie_inbd_wind_detect_tlp_cnt); +int iSetGLB_DBG_CNT_DBL_GRP_EN_glb_dbg_cnt_dbl_grp_en(unsigned int uglb_dbg_cnt_dbl_grp_en); +int iSetGLB_DBL_CRD_TIMER_CFG_glb_dbl_crd_timer_cfg(unsigned int uglb_dbl_crd_timer_cfg); +int iSetGLB_DBL_CRD_CFG_PORT01_glb_dbl_crd_cfg_port1(unsigned int uglb_dbl_crd_cfg_port1); +int iSetGLB_DBL_CRD_CFG_PORT01_glb_dbl_crd_cfg_port0(unsigned int uglb_dbl_crd_cfg_port0); +int iSetGLB_DBL_CRD_CFG_PORT23_glb_dbl_crd_cfg_port3(unsigned int uglb_dbl_crd_cfg_port3); +int iSetGLB_DBL_CRD_CFG_PORT23_glb_dbl_crd_cfg_port2(unsigned int uglb_dbl_crd_cfg_port2); +int iSetGLB_DBL_CRD_CNT_PORT0_glb_dbl_crd_cnt_port0(unsigned int uglb_dbl_crd_cnt_port0); +int iSetGLB_DBL_CRD_CNT_PORT1_glb_dbl_crd_cnt_port1(unsigned int uglb_dbl_crd_cnt_port1); +int iSetGLB_DBL_CRD_CNT_PORT2_glb_dbl_crd_cnt_port2(unsigned int uglb_dbl_crd_cnt_port2); +int iSetGLB_DBL_CRD_CNT_PORT3_glb_dbl_crd_cnt_port3(unsigned int uglb_dbl_crd_cnt_port3); +int iSetCPATH_ENJ_A_FATAL_MSK_cpath_enj_a_fatal_msk(unsigned int ucpath_enj_a_fatal_msk); +int iSetCPATH_ENJ_A_NONFATAL_MSK_cpath_enj_a_nonfatal_msk(unsigned int ucpath_enj_a_nonfatal_msk); +int iSetCPATH_ENJ_FIFO_AFUL_TH_cfg_icpl_rdr_fifo_th(unsigned int ucfg_icpl_rdr_fifo_th); +int iSetCPATH_ENJ_FIFO_AFUL_TH_oubd_pi_afifo_aful_gap_cpi(unsigned int uoubd_pi_afifo_aful_gap_cpi); +int iSetCPATH_ENJ_FIFO_AFUL_TH_oubd_pe_afifo_aful_gap_cpi(unsigned int uoubd_pe_afifo_aful_gap_cpi); +int iSetGLB_DBG_CPATH_ENJ_CNT0_cpath_tile_cnt(unsigned int ucpath_tile_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT0_pure_ack_cnt(unsigned int upure_ack_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT1_cpath_octl_cnt(unsigned int ucpath_octl_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT1_cpath_rsv_cnt(unsigned int ucpath_rsv_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT2_cpath_octl_api10_cnt(unsigned int ucpath_octl_api10_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT2_cpath_octl_api11_cnt(unsigned int ucpath_octl_api11_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT3_cpath_octl_api08_cnt(unsigned int ucpath_octl_api08_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT3_cpath_octl_api09_cnt(unsigned int ucpath_octl_api09_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT4_cpath_octl_api06_cnt(unsigned int ucpath_octl_api06_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT4_cpath_octl_api07_cnt(unsigned int ucpath_octl_api07_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT5_cpath_octl_api04_cnt(unsigned int ucpath_octl_api04_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT5_cpath_octl_api05_cnt(unsigned int ucpath_octl_api05_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT6_cpath_octl_api02_cnt(unsigned int ucpath_octl_api02_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT6_cpath_octl_api03_cnt(unsigned int ucpath_octl_api03_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT7_cpath_octl_api00_cnt(unsigned int ucpath_octl_api00_cnt); +int iSetGLB_DBG_CPATH_ENJ_CNT7_cpath_octl_api01_cnt(unsigned int ucpath_octl_api01_cnt); +int iSetGLB_DBG_CPATH_ENJ_FIFO0_cpath_oubd_afifo_pe(unsigned int ucpath_oubd_afifo_pe); +int iSetGLB_DBG_CPATH_ENJ_FIFO1_cpath_oubd_sfifo_pe(unsigned int ucpath_oubd_sfifo_pe); +int iSetGLB_DBG_CPATH_ENJ_FIFO2_cpath_oubd_sfifo_pi(unsigned int ucpath_oubd_sfifo_pi); +int iSetGLB_DBG_CPATH_ENJ_FIFO3_cpath_oubd_sfifo_rsp(unsigned int ucpath_oubd_sfifo_rsp); +int iSetGLB_DBG_CPATH_ENJ_FIFO4_cpath_sfifo_0sm(unsigned int ucpath_sfifo_0sm); +int iSetGLB_DBG_CPATH_ENJ_FIFO5_cpath_sfifo_1sm(unsigned int ucpath_sfifo_1sm); +int iSetGLB_DBG_CPATH_ENJ_FIFO6_cpath_sfifo_2sm(unsigned int ucpath_sfifo_2sm); +int iSetGLB_DBG_CPATH_ENJ_FIFO7_cpath_sfifo_3sm(unsigned int ucpath_sfifo_3sm); +int iSetGLB_DBG_CPATH_ENJ_FIFO8_cpath_sfifo_tile(unsigned int ucpath_sfifo_tile); +int iSetGLB_DBG_CPATH_ENJ_FIFO9_cpath_sfifo_mqm(unsigned int ucpath_sfifo_mqm); +int iSetGLB_DBG_CPATH_RO0_cpath_out_a(unsigned int ucpath_out_a); +int iSetGLB_DBG_CPATH_RO1_cpath_out_b(unsigned int ucpath_out_b); +int iSetGLB_DBG_CPATH_RO2_cpath_out_c(unsigned int ucpath_out_c); +int iSetGLB_DBG_CPATH_RO3_cpath_out_d(unsigned int ucpath_out_d); +int iSetGLB_DBG_CPATH_RO4_cpath_out_e(unsigned int ucpath_out_e); +int iSetGLB_DBG_CPATH_RO5_cpath_out_f(unsigned int ucpath_out_f); +int iSetGLB_DBG_CPATH_RO6_cpath_out_g(unsigned int ucpath_out_g); +int iSetGLB_DBG_CPATH_RO7_cpath_out_h(unsigned int ucpath_out_h); +int iSetGLB_DBG_CPATH_RO8_cpath_out_0sm(unsigned int ucpath_out_0sm); +int iSetGLB_DBG_CPATH_RO9_cpath_out_1sm(unsigned int ucpath_out_1sm); +int iSetGLB_DBG_CPATH_RO10_cpath_out_2sm(unsigned int ucpath_out_2sm); +int iSetGLB_DBG_CPATH_RO11_cpath_out_3sm(unsigned int ucpath_out_3sm); +int iSetGLB_DBG_CPATH_RO12_cpath_out_tile(unsigned int ucpath_out_tile); +int iSetGLB_DBG_CPATH_RO13_cpath_out_mqm(unsigned int ucpath_out_mqm); +int iSetCPATH_ENJ_PLS_cpath_enj_pls(unsigned int ucpath_enj_pls); +int iSetCTRL_MEM_CTRL_BUS0_ctrl_mem_ctrl_bus133_128(unsigned int uctrl_mem_ctrl_bus133_128); +int iSetCTRL_MEM_CTRL_BUS1_ctrl_mem_ctrl_bus127_96(unsigned int uctrl_mem_ctrl_bus127_96); +int iSetCTRL_MEM_CTRL_BUS2_ctrl_mem_ctrl_bus95_64(unsigned int uctrl_mem_ctrl_bus95_64); +int iSetCTRL_MEM_CTRL_BUS3_ctrl_mem_ctrl_bus63_32(unsigned int uctrl_mem_ctrl_bus63_32); +int iSetCTRL_MEM_CTRL_BUS4_ctrl_mem_ctrl_bus31_0(unsigned int uctrl_mem_ctrl_bus31_0); +int iSetCTRL_TCAM_CTRL_BUS0_ctrl_tcam_ctrl_bus9_0(unsigned int uctrl_tcam_ctrl_bus9_0); + +/* Define the union csr_dtif_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_csr_acc_af_th : 4; /* [3:0] */ + u32 dtif_tx_tlp_af_th : 4; /* [7:4] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo_af_th_u; + +/* Define the union csr_dtif_dfx_arb_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_tx_gnt_ff : 14; /* [13:0] */ + u32 dtif_tx_gnt_vld : 1; /* [14] */ + u32 dtif_tx_is_busy : 1; /* [15] */ + u32 rsv_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_arb_ro_u; + +/* Define the union csr_dtif_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_csr_acc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_0_u; + +/* Define the union csr_dtif_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_arb_sel_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_1_u; + +/* Define the union csr_dtif_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_crdt_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_2_u; + +/* Define the union csr_dtif_dfx_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_crdt_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_3_u; + +/* Define the union csr_dtif_dfx_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_crdt_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_4_u; + +/* Define the union csr_dtif_dfx_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_crdt_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_5_u; + +/* Define the union csr_dtif_dfx_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_pkt_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_6_u; + +/* Define the union csr_dtif_dfx_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_pkt_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_7_u; + +/* Define the union csr_dtif_dfx_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_pkt_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_8_u; + +/* Define the union csr_dtif_dfx_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_pkt_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_9_u; + +/* Define the union csr_dtif_dfx_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_vld_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_10_u; + +/* Define the union csr_dtif_dfx_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_vld_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_11_u; + +/* Define the union csr_dtif_dfx_cnt_12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_vld_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_12_u; + +/* Define the union csr_dtif_dfx_cnt_13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_mpu2dtif_vld_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_13_u; + +/* Define the union csr_dtif_dfx_cnt_14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_dtif2ctif_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_14_u; + +/* Define the union csr_dtif_dfx_cnt_15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_tlp_dtif2ctif_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_15_u; + +/* Define the union csr_dtif_dfx_cnt_16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_rd_cmd_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_16_u; + +/* Define the union csr_dtif_dfx_cnt_17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_rd_cmd_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_17_u; + +/* Define the union csr_dtif_dfx_cnt_18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_rd_cmd_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_18_u; + +/* Define the union csr_dtif_dfx_cnt_19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_rd_cmd_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_19_u; + +/* Define the union csr_dtif_dfx_cnt_20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_rd_cmd_prt4_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_20_u; + +/* Define the union csr_dtif_dfx_cnt_21_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_wr_epath_cmd_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_21_u; + +/* Define the union csr_dtif_dfx_cnt_22_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_wr_epath_cmd_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_22_u; + +/* Define the union csr_dtif_dfx_cnt_23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_wr_epath_cmd_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_23_u; + +/* Define the union csr_dtif_dfx_cnt_24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_wr_epath_cmd_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_24_u; + +/* Define the union csr_dtif_dfx_cnt_25_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_wr_epath_cmd_prt4_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_25_u; + +/* Define the union csr_dtif_dfx_cnt_26_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_wr_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_26_u; + +/* Define the union csr_dtif_dfx_cnt_27_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_epath_wr_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_27_u; + +/* Define the union csr_dtif_dfx_cnt_28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_nl2_rsp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_28_u; + +/* Define the union csr_dtif_dfx_cnt_29_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_nl2_rsp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_29_u; + +/* Define the union csr_dtif_dfx_cnt_30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_mpu_tlp_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_30_u; + +/* Define the union csr_dtif_dfx_cnt_31_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_api_chn_tlp_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_31_u; + +/* Define the union csr_dtif_dfx_cnt_32_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_nl2_cmd_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_32_u; + +/* Define the union csr_dtif_dfx_cnt_33_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_mpu_csr_rsp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_33_u; + +/* Define the union csr_dtif_dfx_cnt_34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_api_chn_tlp_abrt_cnt : 16; /* [15:0] */ + u32 rx_mpu_tlp_abrt_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_dfx_cnt_34_u; + +/* Define the union csr_dfx_dtif_err_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_err_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dtif_err_pls_u; + +/* Define the union csr_dfx_dtif_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dtif_fatal_msk_u; + +/* Define the union csr_dfx_dtif_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dtif_nonfatal_msk_u; + +/* Define the union csr_dtif_fifo0_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_cpld_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo0_sts_u; + +/* Define the union csr_dtif_fifo1_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_csr_rsp_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo1_sts_u; + +/* Define the union csr_dtif_fifo2_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_nl2_cmd_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo2_sts_u; + +/* Define the union csr_dtif_fifo3_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_csr_acc_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo3_sts_u; + +/* Define the union csr_dtif_fifo4_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_tx_tlp_p0_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo4_sts_u; + +/* Define the union csr_dtif_fifo5_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_tx_tlp_p1_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo5_sts_u; + +/* Define the union csr_dtif_fifo6_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_tx_tlp_p2_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo6_sts_u; + +/* Define the union csr_dtif_fifo7_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dtif_tx_tlp_p3_fifo_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dtif_fifo7_sts_u; + +/* Define the union csr_db_arb_qmap_fifo_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_db_fifo_cnt : 5; /* [4:0] */ + u32 arb_dwqe_db_bp : 1; /* [5] */ + u32 dwqe_db_fifo_ept : 1; /* [6] */ + u32 rsv_2 : 1; /* [7] */ + u32 virtio_db_fifo_cnt : 5; /* [12:8] */ + u32 arb_virtio_db_bp : 1; /* [13] */ + u32 virtio_db_fifo_ept : 1; /* [14] */ + u32 rsv_3 : 1; /* [15] */ + u32 osch_db_fifo_cnt : 5; /* [20:16] */ + u32 arb_osch_db_bp : 1; /* [21] */ + u32 osch_db_fifo_ept : 1; /* [22] */ + u32 rsv_4 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_fifo_ro_u; + +/* Define the union csr_db_arb_qmap_arb_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 db_arb_schedule_en : 1; /* [0] */ + u32 tcam_srch_schedule_en : 1; /* [1] */ + u32 db_buf_empty : 1; /* [2] */ + u32 rsv_5 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_arb_ro_u; + +/* Define the union csr_db_arb_qmap_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_db_fifo_push_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_0_u; + +/* Define the union csr_db_arb_qmap_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_db_fifo_push_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_1_u; + +/* Define the union csr_db_arb_qmap_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_db_fifo_push_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_2_u; + +/* Define the union csr_db_arb_qmap_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 db_arb_gnt_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_3_u; + +/* Define the union csr_db_arb_qmap_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_mqm_tx_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_4_u; + +/* Define the union csr_db_arb_qmap_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_db_tx_req_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_5_u; + +/* Define the union csr_db_arb_qmap_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flxq_tcam_srch_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_6_u; + +/* Define the union csr_db_arb_qmap_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flxq_tcam_srch_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_7_u; + +/* Define the union csr_db_arb_qmap_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flxq_tcam_srch_miss_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_8_u; + +/* Define the union csr_db_arb_qmap_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tcam_srch_gnt_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_9_u; + +/* Define the union csr_db_arb_qmap_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vio_tcam_srch_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_10_u; + +/* Define the union csr_db_arb_qmap_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vio_tcam_srch_miss_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_qmap_cnt_11_u; + +/* Define the union csr_dfx_db_arb_qmap_err_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qmap_err_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_db_arb_qmap_err_pls_u; + +/* Define the union csr_dfx_db_arb_qmap_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qmap_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_db_arb_qmap_fatal_msk_u; + +/* Define the union csr_dfx_db_arb_qmap_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qmap_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_db_arb_qmap_nonfatal_msk_u; + +/* Define the union csr_ib_misc_dfx_ro_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 x86_req_fifo_cnt : 5; /* [4:0] */ + u32 rsv_6 : 3; /* [7:5] */ + u32 spu_req_fifo_cnt : 5; /* [12:8] */ + u32 rsv_7 : 3; /* [15:13] */ + u32 mctp_rx_fifo_cnt : 7; /* [22:16] */ + u32 rsv_8 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_ro_0_u; + +/* Define the union csr_ib_misc_dfx_ro_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_buf_dat_cnt : 2; /* [1:0] */ + u32 req_buf_reg_empty : 1; /* [2] */ + u32 rsv_9 : 1; /* [3] */ + u32 req_arb_gnted : 2; /* [5:4] */ + u32 req_arb_schedule_en : 1; /* [6] */ + u32 rsv_10 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_ro_1_u; + +/* Define the union csr_ib_misc_dfx_cnt_20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aer_uc_rpt_cnt : 16; /* [15:0] */ + u32 aer_ur_rpt_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_20_u; + +/* Define the union csr_ib_misc_dfx_cnt_21_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aer_all_rpt_cnt : 16; /* [15:0] */ + u32 aer_tout_rpt_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_21_u; + +/* Define the union csr_ib_misc_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 x86_req_fifo_overflow_cnt : 16; /* [15:0] */ + u32 spu_req_fifo_overflow_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_0_u; + +/* Define the union csr_ib_misc_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 abnormal_tlp_cnt : 16; /* [15:0] */ + u32 memio_tlp_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_1_u; + +/* Define the union csr_ib_misc_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_2_u; + +/* Define the union csr_ib_misc_dfx_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vdm1_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_3_u; + +/* Define the union csr_ib_misc_dfx_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 memio_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_4_u; + +/* Define the union csr_ib_misc_dfx_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 spu_req_fifo_wr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_5_u; + +/* Define the union csr_ib_misc_dfx_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hva_req_crd_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_6_u; + +/* Define the union csr_ib_misc_dfx_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 x86_req_fifo_wr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_7_u; + +/* Define the union csr_ib_misc_dfx_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_req_crd_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_8_u; + +/* Define the union csr_ib_misc_dfx_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_pkt_ok_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_9_u; + +/* Define the union csr_ib_misc_dfx_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_pkt_sop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_10_u; + +/* Define the union csr_ib_misc_dfx_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_pkt_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_11_u; + +/* Define the union csr_ib_misc_dfx_cnt_12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_pkt_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_12_u; + +/* Define the union csr_ib_misc_dfx_cnt_13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_pkt_sop_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_13_u; + +/* Define the union csr_ib_misc_dfx_cnt_14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_x86_pkt_ok_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_14_u; + +/* Define the union csr_ib_misc_dfx_cnt_15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_x86_pkt_sop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_15_u; + +/* Define the union csr_ib_misc_dfx_cnt_16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_x86_pkt_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_16_u; + +/* Define the union csr_ib_misc_dfx_cnt_17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_x86_pkt_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_17_u; + +/* Define the union csr_ib_misc_dfx_cnt_18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_x86_pkt_sop_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_18_u; + +/* Define the union csr_ib_misc_dfx_cnt_19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 req_spu_seop_err_cnt : 16; /* [15:0] */ + u32 req_x86_seop_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_dfx_cnt_19_u; + +/* Define the union csr_dfx_ctl_misc_err_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ctl_misc_err_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ctl_misc_err_pls_u; + +/* Define the union csr_dfx_ctl_misc_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ctl_misc_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ctl_misc_fatal_msk_u; + +/* Define the union csr_dfx_ctl_misc_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_ctl_misc_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_ctl_misc_nonfatal_msk_u; + +/* Define the union csr_virtio_itf_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_tlp_receive_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_0_u; + +/* Define the union csr_virtio_itf_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_msix_receive_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_1_u; + +/* Define the union csr_virtio_itf_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_2_u; + +/* Define the union csr_virtio_itf_dfx_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_tlp_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_3_u; + +/* Define the union csr_virtio_itf_dfx_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_msix_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_4_u; + +/* Define the union csr_virtio_itf_dfx_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_direct_cpld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_5_u; + +/* Define the union csr_virtio_itf_dfx_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_discard_tlp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_6_u; + +/* Define the union csr_virtio_itf_dfx_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_api_cpld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_7_u; + +/* Define the union csr_virtio_itf_dfx_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_send_api_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_8_u; + +/* Define the union csr_virtio_itf_dfx_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_api_rsp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_9_u; + +/* Define the union csr_virtio_itf_dfx_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_send_cpld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_10_u; + +/* Define the union csr_virtio_itf_dfx_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_itf_noapi_2dw_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cnt_11_u; + +/* Define the union csr_cpl_ctl_fifo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_ctl_fifo_ae_th_cfg : 6; /* [5:0] */ + u32 rsv_11 : 2; /* [7:6] */ + u32 cpl_ctl_fifo_af_th_cfg : 6; /* [13:8] */ + u32 rsv_12 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_fifo_cfg_u; + +/* Define the union csr_cpl_ctl_fifo_sts_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpl_ctl_fifo_cnt : 5; /* [4:0] */ + u32 rsv_13 : 11; /* [15:5] */ + u32 cpl_ctl_fifo_empty : 1; /* [16] */ + u32 cpl_ctl_fifo_pfull : 1; /* [17] */ + u32 rsv_14 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_fifo_sts_ro_u; + +/* Define the union csr_cpl_ctl_sts_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpl_ctl_sts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_sts_ro_u; + +/* Define the union csr_cpl_ctl_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpl_ictl_cnt : 16; /* [15:0] */ + u32 dfx_cpl_vio_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_dfx_cnt_0_u; + +/* Define the union csr_cpl_ctl_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpl_aeqcsr_cnt : 16; /* [15:0] */ + u32 dfx_cpl_ipush_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_dfx_cnt_1_u; + +/* Define the union csr_cpl_ctl_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpl_total_cnt : 16; /* [15:0] */ + u32 dfx_cpl_apictl_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_ctl_dfx_cnt_2_u; + +/* Define the union csr_db_arb_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_db_arb_weight : 4; /* [3:0] */ + u32 virtio_db_arb_weight : 4; /* [7:4] */ + u32 osch_db_arb_weight : 4; /* [11:8] */ + u32 rsv_15 : 4; /* [15:12] */ + u32 db_srch_tcam_arb_weight : 4; /* [19:16] */ + u32 vio_srch_tcam_arb_weight : 4; /* [23:20] */ + u32 sw_srch_tcam_arb_weight : 4; /* [27:24] */ + u32 rsv_16 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_arb_weight_cfg_u; + +/* Define the union csr_osch_db_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_db_fifo_af_th : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_db_fifo_af_th_u; + +/* Define the union csr_virtio_db_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_db_fifo_af_th : 6; /* [5:0] */ + u32 rsv_18 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_db_fifo_af_th_u; + +/* Define the union csr_dwqe_db_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwqe_db_fifo_af_th : 6; /* [5:0] */ + u32 rsv_19 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dwqe_db_fifo_af_th_u; + +/* Define the union csr_qmap_tcam_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tcam_top_msk_cfg : 26; /* [25:0] */ + u32 rsv_20 : 5; /* [30:26] */ + u32 tcam_top_valid_bit_mask_cfg : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qmap_tcam_rsvd_cfg_u; + +/* Define the union csr_nvme_db_cos_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nvme_db_cos_0 : 3; /* [2:0] */ + u32 rsv_21 : 1; /* [3] */ + u32 nvme_db_cos_1 : 3; /* [6:4] */ + u32 rsv_22 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nvme_db_cos_cfg_u; + +/* Define the union csr_virtio_db_cos_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_db_cos_rq : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 virtio_db_cos_sq : 3; /* [6:4] */ + u32 rsv_24 : 1; /* [7] */ + u32 virtio_db_cos_ctrlq : 3; /* [10:8] */ + u32 rsv_25 : 1; /* [11] */ + u32 virtio_db_cos_eventq : 3; /* [14:12] */ + u32 rsv_26 : 1; /* [15] */ + u32 virtio_db_cos_rqstq : 3; /* [18:16] */ + u32 rsv_27 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_db_cos_cfg_u; + +/* Define the union csr_virtio_itf_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_lb_only_smf0_en : 1; /* [0] */ + u32 virtio_err_rtn_cpl_en : 1; /* [1] */ + u32 rsv_28 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cfg_u; + +/* Define the union csr_virtio_itf_dfx_cfg_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_tlp_af_th : 10; /* [9:0] */ + u32 rsv_29 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_cfg_1_u; + +/* Define the union csr_virtio_itf_dfx_sts0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bitmap_exhauste : 1; /* [0] */ + u32 virtio_use_tag_cnt : 7; /* [7:1] */ + u32 o_free_addr_cnt : 7; /* [14:8] */ + u32 send_location_flag : 4; /* [18:15] */ + u32 sfifo_tlp_full : 1; /* [19] */ + u32 sfifo_msix_full : 1; /* [20] */ + u32 api_sfifo_full : 1; /* [21] */ + u32 direct_sfifo_full : 1; /* [22] */ + u32 sfifo_tlp_empty : 1; /* [23] */ + u32 sfifo_msix_empty : 1; /* [24] */ + u32 api_sfifo_empty : 1; /* [25] */ + u32 direct_sfifo_empty : 1; /* [26] */ + u32 rsv_30 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_itf_dfx_sts0_u; + +/* Define the union csr_vio_flr_dly_timer_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vio_flr_dly_timer_th : 16; /* [15:0] */ + u32 rsv_31 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vio_flr_dly_timer_th_u; + +/* Define the union csr_vio_flr_dly_timer_unit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vio_flr_dly_timer_unit : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vio_flr_dly_timer_unit_u; + +/* Define the union csr_vio_flr_enable_dly_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vio_flr_enable_dly : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vio_flr_enable_dly_u; + +/* Define the union csr_ib_misc_mctp_rx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mctp_rx_non_mctp_drop_en : 1; /* [0] */ + u32 mctp_rx_hed_byte_order_en : 1; /* [1] */ + u32 rsv_33 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_mctp_rx_cfg_u; + +/* Define the union csr_ib_misc_pcie_itf_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_pcie_rx_cpl_data_crd_vld : 1; /* [0] */ + u32 cpi_pcie_rx_req_data_crd_vld : 1; /* [1] */ + u32 cpi_pcie_rx_cpl_crd_active_en : 1; /* [2] */ + u32 cpi_pcie_rx_req_crd_active_en : 1; /* [3] */ + u32 pcie_cpi_rx_cpl_crd_active_en : 1; /* [4] */ + u32 pcie_cpi_rx_req_crd_active_en : 1; /* [5] */ + u32 rsv_34 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ib_misc_pcie_itf_cfg_u; + +/* Define the union csr_virtio_rsvd_q_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_rsvd0_q_index : 13; /* [12:0] */ + u32 virtio_rsvd0_q_type : 1; /* [13] */ + u32 rsv_35 : 2; /* [15:14] */ + u32 virtio_rsvd1_q_index : 13; /* [28:16] */ + u32 virtio_rsvd1_q_type : 1; /* [29] */ + u32 rsv_36 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_rsvd_q_cfg_u; + +/* Define the union csr_virtio_cos_sq_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cos_sq_cfg_typ0 : 3; /* [2:0] */ + u32 virtio_cos_sq_cfg_typ1 : 3; /* [5:3] */ + u32 virtio_cos_sq_cfg_typ2 : 3; /* [8:6] */ + u32 virtio_cos_sq_cfg_typ3 : 3; /* [11:9] */ + u32 virtio_cos_sq_cfg_typ4 : 3; /* [14:12] */ + u32 virtio_cos_sq_cfg_typ5 : 3; /* [17:15] */ + u32 virtio_cos_sq_cfg_typ6 : 3; /* [20:18] */ + u32 virtio_cos_sq_cfg_typ7 : 3; /* [23:21] */ + u32 rsv_37 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cos_sq_cfg0_u; + +/* Define the union csr_virtio_cos_sq_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cos_sq_cfg_typ8 : 3; /* [2:0] */ + u32 virtio_cos_sq_cfg_typ9 : 3; /* [5:3] */ + u32 virtio_cos_sq_cfg_typ10 : 3; /* [8:6] */ + u32 virtio_cos_sq_cfg_typ11 : 3; /* [11:9] */ + u32 virtio_cos_sq_cfg_typ12 : 3; /* [14:12] */ + u32 virtio_cos_sq_cfg_typ13 : 3; /* [17:15] */ + u32 virtio_cos_sq_cfg_typ14 : 3; /* [20:18] */ + u32 virtio_cos_sq_cfg_typ15 : 3; /* [23:21] */ + u32 rsv_38 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cos_sq_cfg1_u; + +/* Define the union csr_virtio_cos_sq_rp_en_all_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cos_rp_en : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_cos_sq_rp_en_all_u; + +/* Define the union csr_virtio_direct_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 direct_fifo_af_th : 4; /* [3:0] */ + u32 rsv_40 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_direct_fifo_af_th_u; + +/* Define the union csr_virtio_api_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_fifo_af_th : 6; /* [5:0] */ + u32 rsv_41 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_virtio_api_fifo_af_th_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_dtif_fifo_af_th_u dtif_fifo_af_th; /* 0 */ + volatile csr_dtif_dfx_arb_ro_u dtif_dfx_arb_ro; /* 8 */ + volatile csr_dtif_dfx_cnt_0_u dtif_dfx_cnt_0; /* C */ + volatile csr_dtif_dfx_cnt_1_u dtif_dfx_cnt_1; /* 10 */ + volatile csr_dtif_dfx_cnt_2_u dtif_dfx_cnt_2; /* 14 */ + volatile csr_dtif_dfx_cnt_3_u dtif_dfx_cnt_3; /* 18 */ + volatile csr_dtif_dfx_cnt_4_u dtif_dfx_cnt_4; /* 1C */ + volatile csr_dtif_dfx_cnt_5_u dtif_dfx_cnt_5; /* 20 */ + volatile csr_dtif_dfx_cnt_6_u dtif_dfx_cnt_6; /* 24 */ + volatile csr_dtif_dfx_cnt_7_u dtif_dfx_cnt_7; /* 28 */ + volatile csr_dtif_dfx_cnt_8_u dtif_dfx_cnt_8; /* 2C */ + volatile csr_dtif_dfx_cnt_9_u dtif_dfx_cnt_9; /* 30 */ + volatile csr_dtif_dfx_cnt_10_u dtif_dfx_cnt_10; /* 34 */ + volatile csr_dtif_dfx_cnt_11_u dtif_dfx_cnt_11; /* 38 */ + volatile csr_dtif_dfx_cnt_12_u dtif_dfx_cnt_12; /* 3C */ + volatile csr_dtif_dfx_cnt_13_u dtif_dfx_cnt_13; /* 40 */ + volatile csr_dtif_dfx_cnt_14_u dtif_dfx_cnt_14; /* 44 */ + volatile csr_dtif_dfx_cnt_15_u dtif_dfx_cnt_15; /* 48 */ + volatile csr_dtif_dfx_cnt_16_u dtif_dfx_cnt_16; /* 4C */ + volatile csr_dtif_dfx_cnt_17_u dtif_dfx_cnt_17; /* 50 */ + volatile csr_dtif_dfx_cnt_18_u dtif_dfx_cnt_18; /* 54 */ + volatile csr_dtif_dfx_cnt_19_u dtif_dfx_cnt_19; /* 58 */ + volatile csr_dtif_dfx_cnt_20_u dtif_dfx_cnt_20; /* 5C */ + volatile csr_dtif_dfx_cnt_21_u dtif_dfx_cnt_21; /* 60 */ + volatile csr_dtif_dfx_cnt_22_u dtif_dfx_cnt_22; /* 64 */ + volatile csr_dtif_dfx_cnt_23_u dtif_dfx_cnt_23; /* 68 */ + volatile csr_dtif_dfx_cnt_24_u dtif_dfx_cnt_24; /* 6C */ + volatile csr_dtif_dfx_cnt_25_u dtif_dfx_cnt_25; /* 70 */ + volatile csr_dtif_dfx_cnt_26_u dtif_dfx_cnt_26; /* 74 */ + volatile csr_dtif_dfx_cnt_27_u dtif_dfx_cnt_27; /* 78 */ + volatile csr_dtif_dfx_cnt_28_u dtif_dfx_cnt_28; /* 7C */ + volatile csr_dtif_dfx_cnt_29_u dtif_dfx_cnt_29; /* 80 */ + volatile csr_dtif_dfx_cnt_30_u dtif_dfx_cnt_30; /* 84 */ + volatile csr_dtif_dfx_cnt_31_u dtif_dfx_cnt_31; /* 88 */ + volatile csr_dtif_dfx_cnt_32_u dtif_dfx_cnt_32; /* 8C */ + volatile csr_dtif_dfx_cnt_33_u dtif_dfx_cnt_33; /* 90 */ + volatile csr_dtif_dfx_cnt_34_u dtif_dfx_cnt_34; /* 94 */ + volatile csr_dfx_dtif_err_pls_u dfx_dtif_err_pls; /* A0 */ + volatile csr_dfx_dtif_fatal_msk_u dfx_dtif_fatal_msk; /* A4 */ + volatile csr_dfx_dtif_nonfatal_msk_u dfx_dtif_nonfatal_msk; /* A8 */ + volatile csr_dtif_fifo0_sts_u dtif_fifo0_sts; /* B0 */ + volatile csr_dtif_fifo1_sts_u dtif_fifo1_sts; /* B4 */ + volatile csr_dtif_fifo2_sts_u dtif_fifo2_sts; /* B8 */ + volatile csr_dtif_fifo3_sts_u dtif_fifo3_sts; /* BC */ + volatile csr_dtif_fifo4_sts_u dtif_fifo4_sts; /* C0 */ + volatile csr_dtif_fifo5_sts_u dtif_fifo5_sts; /* C4 */ + volatile csr_dtif_fifo6_sts_u dtif_fifo6_sts; /* C8 */ + volatile csr_dtif_fifo7_sts_u dtif_fifo7_sts; /* CC */ + volatile csr_db_arb_qmap_fifo_ro_u db_arb_qmap_fifo_ro; /* 100 */ + volatile csr_db_arb_qmap_arb_ro_u db_arb_qmap_arb_ro; /* 108 */ + volatile csr_db_arb_qmap_cnt_0_u db_arb_qmap_cnt_0; /* 110 */ + volatile csr_db_arb_qmap_cnt_1_u db_arb_qmap_cnt_1; /* 114 */ + volatile csr_db_arb_qmap_cnt_2_u db_arb_qmap_cnt_2; /* 118 */ + volatile csr_db_arb_qmap_cnt_3_u db_arb_qmap_cnt_3; /* 11C */ + volatile csr_db_arb_qmap_cnt_4_u db_arb_qmap_cnt_4; /* 120 */ + volatile csr_db_arb_qmap_cnt_5_u db_arb_qmap_cnt_5; /* 124 */ + volatile csr_db_arb_qmap_cnt_6_u db_arb_qmap_cnt_6; /* 128 */ + volatile csr_db_arb_qmap_cnt_7_u db_arb_qmap_cnt_7; /* 12C */ + volatile csr_db_arb_qmap_cnt_8_u db_arb_qmap_cnt_8; /* 130 */ + volatile csr_db_arb_qmap_cnt_9_u db_arb_qmap_cnt_9; /* 134 */ + volatile csr_db_arb_qmap_cnt_10_u db_arb_qmap_cnt_10; /* 138 */ + volatile csr_db_arb_qmap_cnt_11_u db_arb_qmap_cnt_11; /* 13C */ + volatile csr_dfx_db_arb_qmap_err_pls_u dfx_db_arb_qmap_err_pls; /* 150 */ + volatile csr_dfx_db_arb_qmap_fatal_msk_u dfx_db_arb_qmap_fatal_msk; /* 154 */ + volatile csr_dfx_db_arb_qmap_nonfatal_msk_u dfx_db_arb_qmap_nonfatal_msk; /* 158 */ + volatile csr_ib_misc_dfx_ro_0_u ib_misc_dfx_ro_0; /* 180 */ + volatile csr_ib_misc_dfx_ro_1_u ib_misc_dfx_ro_1; /* 184 */ + volatile csr_ib_misc_dfx_cnt_20_u ib_misc_dfx_cnt_20; /* 198 */ + volatile csr_ib_misc_dfx_cnt_21_u ib_misc_dfx_cnt_21; /* 19C */ + volatile csr_ib_misc_dfx_cnt_0_u ib_misc_dfx_cnt_0; /* 1A0 */ + volatile csr_ib_misc_dfx_cnt_1_u ib_misc_dfx_cnt_1; /* 1A4 */ + volatile csr_ib_misc_dfx_cnt_2_u ib_misc_dfx_cnt_2; /* 1A8 */ + volatile csr_ib_misc_dfx_cnt_3_u ib_misc_dfx_cnt_3; /* 1AC */ + volatile csr_ib_misc_dfx_cnt_4_u ib_misc_dfx_cnt_4; /* 1B0 */ + volatile csr_ib_misc_dfx_cnt_5_u ib_misc_dfx_cnt_5; /* 1B4 */ + volatile csr_ib_misc_dfx_cnt_6_u ib_misc_dfx_cnt_6; /* 1B8 */ + volatile csr_ib_misc_dfx_cnt_7_u ib_misc_dfx_cnt_7; /* 1BC */ + volatile csr_ib_misc_dfx_cnt_8_u ib_misc_dfx_cnt_8; /* 1C0 */ + volatile csr_ib_misc_dfx_cnt_9_u ib_misc_dfx_cnt_9; /* 1C4 */ + volatile csr_ib_misc_dfx_cnt_10_u ib_misc_dfx_cnt_10; /* 1C8 */ + volatile csr_ib_misc_dfx_cnt_11_u ib_misc_dfx_cnt_11; /* 1CC */ + volatile csr_ib_misc_dfx_cnt_12_u ib_misc_dfx_cnt_12; /* 1D0 */ + volatile csr_ib_misc_dfx_cnt_13_u ib_misc_dfx_cnt_13; /* 1D4 */ + volatile csr_ib_misc_dfx_cnt_14_u ib_misc_dfx_cnt_14; /* 1D8 */ + volatile csr_ib_misc_dfx_cnt_15_u ib_misc_dfx_cnt_15; /* 1DC */ + volatile csr_ib_misc_dfx_cnt_16_u ib_misc_dfx_cnt_16; /* 1E0 */ + volatile csr_ib_misc_dfx_cnt_17_u ib_misc_dfx_cnt_17; /* 1E4 */ + volatile csr_ib_misc_dfx_cnt_18_u ib_misc_dfx_cnt_18; /* 1E8 */ + volatile csr_ib_misc_dfx_cnt_19_u ib_misc_dfx_cnt_19; /* 1EC */ + volatile csr_dfx_ctl_misc_err_pls_u dfx_ctl_misc_err_pls; /* 1F0 */ + volatile csr_dfx_ctl_misc_fatal_msk_u dfx_ctl_misc_fatal_msk; /* 1F4 */ + volatile csr_dfx_ctl_misc_nonfatal_msk_u dfx_ctl_misc_nonfatal_msk; /* 1F8 */ + volatile csr_virtio_itf_dfx_cnt_0_u virtio_itf_dfx_cnt_0; /* 200 */ + volatile csr_virtio_itf_dfx_cnt_1_u virtio_itf_dfx_cnt_1; /* 204 */ + volatile csr_virtio_itf_dfx_cnt_2_u virtio_itf_dfx_cnt_2; /* 208 */ + volatile csr_virtio_itf_dfx_cnt_3_u virtio_itf_dfx_cnt_3; /* 20C */ + volatile csr_virtio_itf_dfx_cnt_4_u virtio_itf_dfx_cnt_4; /* 210 */ + volatile csr_virtio_itf_dfx_cnt_5_u virtio_itf_dfx_cnt_5; /* 214 */ + volatile csr_virtio_itf_dfx_cnt_6_u virtio_itf_dfx_cnt_6; /* 218 */ + volatile csr_virtio_itf_dfx_cnt_7_u virtio_itf_dfx_cnt_7; /* 21C */ + volatile csr_virtio_itf_dfx_cnt_8_u virtio_itf_dfx_cnt_8; /* 220 */ + volatile csr_virtio_itf_dfx_cnt_9_u virtio_itf_dfx_cnt_9; /* 224 */ + volatile csr_virtio_itf_dfx_cnt_10_u virtio_itf_dfx_cnt_10; /* 228 */ + volatile csr_virtio_itf_dfx_cnt_11_u virtio_itf_dfx_cnt_11; /* 22C */ + volatile csr_cpl_ctl_fifo_cfg_u cpl_ctl_fifo_cfg; /* 280 */ + volatile csr_cpl_ctl_fifo_sts_ro_u cpl_ctl_fifo_sts_ro; /* 290 */ + volatile csr_cpl_ctl_sts_ro_u cpl_ctl_sts_ro; /* 294 */ + volatile csr_cpl_ctl_dfx_cnt_0_u cpl_ctl_dfx_cnt_0; /* 2A0 */ + volatile csr_cpl_ctl_dfx_cnt_1_u cpl_ctl_dfx_cnt_1; /* 2A4 */ + volatile csr_cpl_ctl_dfx_cnt_2_u cpl_ctl_dfx_cnt_2; /* 2A8 */ + volatile csr_db_arb_weight_cfg_u db_arb_weight_cfg; /* 400 */ + volatile csr_osch_db_fifo_af_th_u osch_db_fifo_af_th; /* 404 */ + volatile csr_virtio_db_fifo_af_th_u virtio_db_fifo_af_th; /* 408 */ + volatile csr_dwqe_db_fifo_af_th_u dwqe_db_fifo_af_th; /* 40C */ + volatile csr_qmap_tcam_rsvd_cfg_u qmap_tcam_rsvd_cfg; /* 410 */ + volatile csr_nvme_db_cos_cfg_u nvme_db_cos_cfg; /* 440 */ + volatile csr_virtio_db_cos_cfg_u virtio_db_cos_cfg; /* 444 */ + volatile csr_virtio_itf_dfx_cfg_u virtio_itf_dfx_cfg; /* 448 */ + volatile csr_virtio_itf_dfx_cfg_1_u virtio_itf_dfx_cfg_1; /* 44C */ + volatile csr_virtio_itf_dfx_sts0_u virtio_itf_dfx_sts0; /* 490 */ + volatile csr_vio_flr_dly_timer_th_u vio_flr_dly_timer_th; /* 498 */ + volatile csr_vio_flr_dly_timer_unit_u vio_flr_dly_timer_unit; /* 49C */ + volatile csr_vio_flr_enable_dly_u vio_flr_enable_dly; /* 4A0 */ + volatile csr_ib_misc_mctp_rx_cfg_u ib_misc_mctp_rx_cfg; /* 4B0 */ + volatile csr_ib_misc_pcie_itf_cfg_u ib_misc_pcie_itf_cfg; /* 4B4 */ + volatile csr_virtio_rsvd_q_cfg_u virtio_rsvd_q_cfg[2]; /* 500 */ + volatile csr_virtio_cos_sq_cfg0_u virtio_cos_sq_cfg0; /* 6A0 */ + volatile csr_virtio_cos_sq_cfg1_u virtio_cos_sq_cfg1; /* 6A4 */ + volatile csr_virtio_cos_sq_rp_en_all_u virtio_cos_sq_rp_en_all; /* 6A8 */ + volatile csr_virtio_direct_fifo_af_th_u virtio_direct_fifo_af_th; /* 6AC */ + volatile csr_virtio_api_fifo_af_th_u virtio_api_fifo_af_th; /* 6B0 */ +} S_dfx_ctrl_top_csr_REGS_TYPE; + +/* Declare the struct pointor of the module dfx_ctrl_top_csr */ +extern volatile S_dfx_ctrl_top_csr_REGS_TYPE *gopdfx_ctrl_top_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetDTIF_FIFO_AF_TH_dtif_csr_acc_af_th(unsigned int udtif_csr_acc_af_th); +int iSetDTIF_FIFO_AF_TH_dtif_tx_tlp_af_th(unsigned int udtif_tx_tlp_af_th); +int iSetDTIF_DFX_ARB_RO_dtif_tx_gnt_ff(unsigned int udtif_tx_gnt_ff); +int iSetDTIF_DFX_ARB_RO_dtif_tx_gnt_vld(unsigned int udtif_tx_gnt_vld); +int iSetDTIF_DFX_ARB_RO_dtif_tx_is_busy(unsigned int udtif_tx_is_busy); +int iSetDTIF_DFX_CNT_0_tx_csr_acc_cnt(unsigned int utx_csr_acc_cnt); +int iSetDTIF_DFX_CNT_1_tx_tlp_arb_sel_cnt(unsigned int utx_tlp_arb_sel_cnt); +int iSetDTIF_DFX_CNT_2_tx_tlp_crdt_prt0_cnt(unsigned int utx_tlp_crdt_prt0_cnt); +int iSetDTIF_DFX_CNT_3_tx_tlp_crdt_prt1_cnt(unsigned int utx_tlp_crdt_prt1_cnt); +int iSetDTIF_DFX_CNT_4_tx_tlp_crdt_prt2_cnt(unsigned int utx_tlp_crdt_prt2_cnt); +int iSetDTIF_DFX_CNT_5_tx_tlp_crdt_prt3_cnt(unsigned int utx_tlp_crdt_prt3_cnt); +int iSetDTIF_DFX_CNT_6_tx_tlp_mpu2dtif_pkt_prt0_cnt(unsigned int utx_tlp_mpu2dtif_pkt_prt0_cnt); +int iSetDTIF_DFX_CNT_7_tx_tlp_mpu2dtif_pkt_prt1_cnt(unsigned int utx_tlp_mpu2dtif_pkt_prt1_cnt); +int iSetDTIF_DFX_CNT_8_tx_tlp_mpu2dtif_pkt_prt2_cnt(unsigned int utx_tlp_mpu2dtif_pkt_prt2_cnt); +int iSetDTIF_DFX_CNT_9_tx_tlp_mpu2dtif_pkt_prt3_cnt(unsigned int utx_tlp_mpu2dtif_pkt_prt3_cnt); +int iSetDTIF_DFX_CNT_10_tx_tlp_mpu2dtif_vld_prt0_cnt(unsigned int utx_tlp_mpu2dtif_vld_prt0_cnt); +int iSetDTIF_DFX_CNT_11_tx_tlp_mpu2dtif_vld_prt1_cnt(unsigned int utx_tlp_mpu2dtif_vld_prt1_cnt); +int iSetDTIF_DFX_CNT_12_tx_tlp_mpu2dtif_vld_prt2_cnt(unsigned int utx_tlp_mpu2dtif_vld_prt2_cnt); +int iSetDTIF_DFX_CNT_13_tx_tlp_mpu2dtif_vld_prt3_cnt(unsigned int utx_tlp_mpu2dtif_vld_prt3_cnt); +int iSetDTIF_DFX_CNT_14_tx_tlp_dtif2ctif_pkt_cnt(unsigned int utx_tlp_dtif2ctif_pkt_cnt); +int iSetDTIF_DFX_CNT_15_tx_tlp_dtif2ctif_vld_cnt(unsigned int utx_tlp_dtif2ctif_vld_cnt); +int iSetDTIF_DFX_CNT_16_tx_epath_rd_cmd_prt0_cnt(unsigned int utx_epath_rd_cmd_prt0_cnt); +int iSetDTIF_DFX_CNT_17_tx_epath_rd_cmd_prt1_cnt(unsigned int utx_epath_rd_cmd_prt1_cnt); +int iSetDTIF_DFX_CNT_18_tx_epath_rd_cmd_prt2_cnt(unsigned int utx_epath_rd_cmd_prt2_cnt); +int iSetDTIF_DFX_CNT_19_tx_epath_rd_cmd_prt3_cnt(unsigned int utx_epath_rd_cmd_prt3_cnt); +int iSetDTIF_DFX_CNT_20_tx_epath_rd_cmd_prt4_cnt(unsigned int utx_epath_rd_cmd_prt4_cnt); +int iSetDTIF_DFX_CNT_21_tx_wr_epath_cmd_prt0_cnt(unsigned int utx_wr_epath_cmd_prt0_cnt); +int iSetDTIF_DFX_CNT_22_tx_wr_epath_cmd_prt1_cnt(unsigned int utx_wr_epath_cmd_prt1_cnt); +int iSetDTIF_DFX_CNT_23_tx_wr_epath_cmd_prt2_cnt(unsigned int utx_wr_epath_cmd_prt2_cnt); +int iSetDTIF_DFX_CNT_24_tx_wr_epath_cmd_prt3_cnt(unsigned int utx_wr_epath_cmd_prt3_cnt); +int iSetDTIF_DFX_CNT_25_tx_wr_epath_cmd_prt4_cnt(unsigned int utx_wr_epath_cmd_prt4_cnt); +int iSetDTIF_DFX_CNT_26_tx_epath_wr_pkt_cnt(unsigned int utx_epath_wr_pkt_cnt); +int iSetDTIF_DFX_CNT_27_tx_epath_wr_vld_cnt(unsigned int utx_epath_wr_vld_cnt); +int iSetDTIF_DFX_CNT_28_tx_nl2_rsp_cnt(unsigned int utx_nl2_rsp_cnt); +int iSetDTIF_DFX_CNT_29_tx_nl2_rsp_crdt_cnt(unsigned int utx_nl2_rsp_crdt_cnt); +int iSetDTIF_DFX_CNT_30_rx_mpu_tlp_eop_cnt(unsigned int urx_mpu_tlp_eop_cnt); +int iSetDTIF_DFX_CNT_31_rx_api_chn_tlp_eop_cnt(unsigned int urx_api_chn_tlp_eop_cnt); +int iSetDTIF_DFX_CNT_32_rx_nl2_cmd_req_cnt(unsigned int urx_nl2_cmd_req_cnt); +int iSetDTIF_DFX_CNT_33_rx_mpu_csr_rsp_cnt(unsigned int urx_mpu_csr_rsp_cnt); +int iSetDTIF_DFX_CNT_34_rx_api_chn_tlp_abrt_cnt(unsigned int urx_api_chn_tlp_abrt_cnt); +int iSetDTIF_DFX_CNT_34_rx_mpu_tlp_abrt_cnt(unsigned int urx_mpu_tlp_abrt_cnt); +int iSetDFX_DTIF_ERR_PLS_dtif_err_pls(unsigned int udtif_err_pls); +int iSetDFX_DTIF_FATAL_MSK_dtif_fatal_msk(unsigned int udtif_fatal_msk); +int iSetDFX_DTIF_NONFATAL_MSK_dtif_nonfatal_msk(unsigned int udtif_nonfatal_msk); +int iSetDTIF_FIFO0_STS_dtif_cpld_fifo_sts(unsigned int udtif_cpld_fifo_sts); +int iSetDTIF_FIFO1_STS_dtif_csr_rsp_fifo_sts(unsigned int udtif_csr_rsp_fifo_sts); +int iSetDTIF_FIFO2_STS_dtif_nl2_cmd_fifo_sts(unsigned int udtif_nl2_cmd_fifo_sts); +int iSetDTIF_FIFO3_STS_dtif_csr_acc_fifo_sts(unsigned int udtif_csr_acc_fifo_sts); +int iSetDTIF_FIFO4_STS_dtif_tx_tlp_p0_fifo_sts(unsigned int udtif_tx_tlp_p0_fifo_sts); +int iSetDTIF_FIFO5_STS_dtif_tx_tlp_p1_fifo_sts(unsigned int udtif_tx_tlp_p1_fifo_sts); +int iSetDTIF_FIFO6_STS_dtif_tx_tlp_p2_fifo_sts(unsigned int udtif_tx_tlp_p2_fifo_sts); +int iSetDTIF_FIFO7_STS_dtif_tx_tlp_p3_fifo_sts(unsigned int udtif_tx_tlp_p3_fifo_sts); +int iSetDB_ARB_QMAP_FIFO_RO_dwqe_db_fifo_cnt(unsigned int udwqe_db_fifo_cnt); +int iSetDB_ARB_QMAP_FIFO_RO_arb_dwqe_db_bp(unsigned int uarb_dwqe_db_bp); +int iSetDB_ARB_QMAP_FIFO_RO_dwqe_db_fifo_ept(unsigned int udwqe_db_fifo_ept); +int iSetDB_ARB_QMAP_FIFO_RO_virtio_db_fifo_cnt(unsigned int uvirtio_db_fifo_cnt); +int iSetDB_ARB_QMAP_FIFO_RO_arb_virtio_db_bp(unsigned int uarb_virtio_db_bp); +int iSetDB_ARB_QMAP_FIFO_RO_virtio_db_fifo_ept(unsigned int uvirtio_db_fifo_ept); +int iSetDB_ARB_QMAP_FIFO_RO_osch_db_fifo_cnt(unsigned int uosch_db_fifo_cnt); +int iSetDB_ARB_QMAP_FIFO_RO_arb_osch_db_bp(unsigned int uarb_osch_db_bp); +int iSetDB_ARB_QMAP_FIFO_RO_osch_db_fifo_ept(unsigned int uosch_db_fifo_ept); +int iSetDB_ARB_QMAP_ARB_RO_db_arb_schedule_en(unsigned int udb_arb_schedule_en); +int iSetDB_ARB_QMAP_ARB_RO_tcam_srch_schedule_en(unsigned int utcam_srch_schedule_en); +int iSetDB_ARB_QMAP_ARB_RO_db_buf_empty(unsigned int udb_buf_empty); +int iSetDB_ARB_QMAP_CNT_0_dwqe_db_fifo_push_cnt(unsigned int udwqe_db_fifo_push_cnt); +int iSetDB_ARB_QMAP_CNT_1_virtio_db_fifo_push_cnt(unsigned int uvirtio_db_fifo_push_cnt); +int iSetDB_ARB_QMAP_CNT_2_osch_db_fifo_push_cnt(unsigned int uosch_db_fifo_push_cnt); +int iSetDB_ARB_QMAP_CNT_3_db_arb_gnt_total_cnt(unsigned int udb_arb_gnt_total_cnt); +int iSetDB_ARB_QMAP_CNT_4_cpi_mqm_tx_db_cnt(unsigned int ucpi_mqm_tx_db_cnt); +int iSetDB_ARB_QMAP_CNT_5_cpi_db_tx_req_total_cnt(unsigned int ucpi_db_tx_req_total_cnt); +int iSetDB_ARB_QMAP_CNT_6_flxq_tcam_srch_total_cnt(unsigned int uflxq_tcam_srch_total_cnt); +int iSetDB_ARB_QMAP_CNT_7_flxq_tcam_srch_hit_cnt(unsigned int uflxq_tcam_srch_hit_cnt); +int iSetDB_ARB_QMAP_CNT_8_flxq_tcam_srch_miss_cnt(unsigned int uflxq_tcam_srch_miss_cnt); +int iSetDB_ARB_QMAP_CNT_9_tcam_srch_gnt_total_cnt(unsigned int utcam_srch_gnt_total_cnt); +int iSetDB_ARB_QMAP_CNT_10_vio_tcam_srch_hit_cnt(unsigned int uvio_tcam_srch_hit_cnt); +int iSetDB_ARB_QMAP_CNT_11_vio_tcam_srch_miss_cnt(unsigned int uvio_tcam_srch_miss_cnt); +int iSetDFX_DB_ARB_QMAP_ERR_PLS_qmap_err_pls(unsigned int uqmap_err_pls); +int iSetDFX_DB_ARB_QMAP_FATAL_MSK_qmap_fatal_msk(unsigned int uqmap_fatal_msk); +int iSetDFX_DB_ARB_QMAP_NONFATAL_MSK_qmap_nonfatal_msk(unsigned int uqmap_nonfatal_msk); +int iSetIB_MISC_DFX_RO_0_x86_req_fifo_cnt(unsigned int ux86_req_fifo_cnt); +int iSetIB_MISC_DFX_RO_0_spu_req_fifo_cnt(unsigned int uspu_req_fifo_cnt); +int iSetIB_MISC_DFX_RO_0_mctp_rx_fifo_cnt(unsigned int umctp_rx_fifo_cnt); +int iSetIB_MISC_DFX_RO_1_req_buf_dat_cnt(unsigned int ureq_buf_dat_cnt); +int iSetIB_MISC_DFX_RO_1_req_buf_reg_empty(unsigned int ureq_buf_reg_empty); +int iSetIB_MISC_DFX_RO_1_req_arb_gnted(unsigned int ureq_arb_gnted); +int iSetIB_MISC_DFX_RO_1_req_arb_schedule_en(unsigned int ureq_arb_schedule_en); +int iSetIB_MISC_DFX_CNT_20_aer_uc_rpt_cnt(unsigned int uaer_uc_rpt_cnt); +int iSetIB_MISC_DFX_CNT_20_aer_ur_rpt_cnt(unsigned int uaer_ur_rpt_cnt); +int iSetIB_MISC_DFX_CNT_21_aer_all_rpt_cnt(unsigned int uaer_all_rpt_cnt); +int iSetIB_MISC_DFX_CNT_21_aer_tout_rpt_cnt(unsigned int uaer_tout_rpt_cnt); +int iSetIB_MISC_DFX_CNT_0_x86_req_fifo_overflow_cnt(unsigned int ux86_req_fifo_overflow_cnt); +int iSetIB_MISC_DFX_CNT_0_spu_req_fifo_overflow_cnt(unsigned int uspu_req_fifo_overflow_cnt); +int iSetIB_MISC_DFX_CNT_1_abnormal_tlp_cnt(unsigned int uabnormal_tlp_cnt); +int iSetIB_MISC_DFX_CNT_1_memio_tlp_err_cnt(unsigned int umemio_tlp_err_cnt); +int iSetIB_MISC_DFX_CNT_2_mctp_tlp_cnt(unsigned int umctp_tlp_cnt); +int iSetIB_MISC_DFX_CNT_3_vdm1_tlp_cnt(unsigned int uvdm1_tlp_cnt); +int iSetIB_MISC_DFX_CNT_4_memio_tlp_cnt(unsigned int umemio_tlp_cnt); +int iSetIB_MISC_DFX_CNT_5_spu_req_fifo_wr_cnt(unsigned int uspu_req_fifo_wr_cnt); +int iSetIB_MISC_DFX_CNT_6_hva_req_crd_vld_cnt(unsigned int uhva_req_crd_vld_cnt); +int iSetIB_MISC_DFX_CNT_7_x86_req_fifo_wr_cnt(unsigned int ux86_req_fifo_wr_cnt); +int iSetIB_MISC_DFX_CNT_8_pcie_req_crd_vld_cnt(unsigned int upcie_req_crd_vld_cnt); +int iSetIB_MISC_DFX_CNT_9_req_spu_pkt_ok_cnt(unsigned int ureq_spu_pkt_ok_cnt); +int iSetIB_MISC_DFX_CNT_10_req_spu_pkt_sop_cnt(unsigned int ureq_spu_pkt_sop_cnt); +int iSetIB_MISC_DFX_CNT_11_req_spu_pkt_eop_cnt(unsigned int ureq_spu_pkt_eop_cnt); +int iSetIB_MISC_DFX_CNT_12_req_spu_pkt_vld_cnt(unsigned int ureq_spu_pkt_vld_cnt); +int iSetIB_MISC_DFX_CNT_13_req_spu_pkt_sop_eop_cnt(unsigned int ureq_spu_pkt_sop_eop_cnt); +int iSetIB_MISC_DFX_CNT_14_req_x86_pkt_ok_cnt(unsigned int ureq_x86_pkt_ok_cnt); +int iSetIB_MISC_DFX_CNT_15_req_x86_pkt_sop_cnt(unsigned int ureq_x86_pkt_sop_cnt); +int iSetIB_MISC_DFX_CNT_16_req_x86_pkt_eop_cnt(unsigned int ureq_x86_pkt_eop_cnt); +int iSetIB_MISC_DFX_CNT_17_req_x86_pkt_vld_cnt(unsigned int ureq_x86_pkt_vld_cnt); +int iSetIB_MISC_DFX_CNT_18_req_x86_pkt_sop_eop_cnt(unsigned int ureq_x86_pkt_sop_eop_cnt); +int iSetIB_MISC_DFX_CNT_19_req_spu_seop_err_cnt(unsigned int ureq_spu_seop_err_cnt); +int iSetIB_MISC_DFX_CNT_19_req_x86_seop_err_cnt(unsigned int ureq_x86_seop_err_cnt); +int iSetDFX_CTL_MISC_ERR_PLS_dfx_ctl_misc_err_pls(unsigned int udfx_ctl_misc_err_pls); +int iSetDFX_CTL_MISC_FATAL_MSK_dfx_ctl_misc_fatal_msk(unsigned int udfx_ctl_misc_fatal_msk); +int iSetDFX_CTL_MISC_NONFATAL_MSK_dfx_ctl_misc_nonfatal_msk(unsigned int udfx_ctl_misc_nonfatal_msk); +int iSetVIRTIO_ITF_DFX_CNT_0_virtio_tlp_receive_cnt(unsigned int uvirtio_tlp_receive_cnt); +int iSetVIRTIO_ITF_DFX_CNT_1_virtio_msix_receive_cnt(unsigned int uvirtio_msix_receive_cnt); +int iSetVIRTIO_ITF_DFX_CNT_2_virtio_itf_db_cnt(unsigned int uvirtio_itf_db_cnt); +int iSetVIRTIO_ITF_DFX_CNT_3_virtio_itf_tlp_api_cnt(unsigned int uvirtio_itf_tlp_api_cnt); +int iSetVIRTIO_ITF_DFX_CNT_4_virtio_itf_msix_api_cnt(unsigned int uvirtio_itf_msix_api_cnt); +int iSetVIRTIO_ITF_DFX_CNT_5_virtio_itf_direct_cpld_cnt(unsigned int uvirtio_itf_direct_cpld_cnt); +int iSetVIRTIO_ITF_DFX_CNT_6_virtio_itf_discard_tlp_cnt(unsigned int uvirtio_itf_discard_tlp_cnt); +int iSetVIRTIO_ITF_DFX_CNT_7_virtio_itf_api_cpld_cnt(unsigned int uvirtio_itf_api_cpld_cnt); +int iSetVIRTIO_ITF_DFX_CNT_8_virtio_itf_send_api_cnt(unsigned int uvirtio_itf_send_api_cnt); +int iSetVIRTIO_ITF_DFX_CNT_9_virtio_itf_api_rsp_cnt(unsigned int uvirtio_itf_api_rsp_cnt); +int iSetVIRTIO_ITF_DFX_CNT_10_virtio_itf_send_cpld_cnt(unsigned int uvirtio_itf_send_cpld_cnt); +int iSetVIRTIO_ITF_DFX_CNT_11_virtio_itf_noapi_2dw_cnt(unsigned int uvirtio_itf_noapi_2dw_cnt); +int iSetCPL_CTL_FIFO_CFG_cpl_ctl_fifo_ae_th_cfg(unsigned int ucpl_ctl_fifo_ae_th_cfg); +int iSetCPL_CTL_FIFO_CFG_cpl_ctl_fifo_af_th_cfg(unsigned int ucpl_ctl_fifo_af_th_cfg); +int iSetCPL_CTL_FIFO_STS_RO_cpl_ctl_fifo_cnt(unsigned int ucpl_ctl_fifo_cnt); +int iSetCPL_CTL_FIFO_STS_RO_cpl_ctl_fifo_empty(unsigned int ucpl_ctl_fifo_empty); +int iSetCPL_CTL_FIFO_STS_RO_cpl_ctl_fifo_pfull(unsigned int ucpl_ctl_fifo_pfull); +int iSetCPL_CTL_STS_RO_dfx_cpl_ctl_sts(unsigned int udfx_cpl_ctl_sts); +int iSetCPL_CTL_DFX_CNT_0_dfx_cpl_ictl_cnt(unsigned int udfx_cpl_ictl_cnt); +int iSetCPL_CTL_DFX_CNT_0_dfx_cpl_vio_cnt(unsigned int udfx_cpl_vio_cnt); +int iSetCPL_CTL_DFX_CNT_1_dfx_cpl_aeqcsr_cnt(unsigned int udfx_cpl_aeqcsr_cnt); +int iSetCPL_CTL_DFX_CNT_1_dfx_cpl_ipush_cnt(unsigned int udfx_cpl_ipush_cnt); +int iSetCPL_CTL_DFX_CNT_2_dfx_cpl_total_cnt(unsigned int udfx_cpl_total_cnt); +int iSetCPL_CTL_DFX_CNT_2_dfx_cpl_apictl_cnt(unsigned int udfx_cpl_apictl_cnt); +int iSetDB_ARB_WEIGHT_CFG_dwqe_db_arb_weight(unsigned int udwqe_db_arb_weight); +int iSetDB_ARB_WEIGHT_CFG_virtio_db_arb_weight(unsigned int uvirtio_db_arb_weight); +int iSetDB_ARB_WEIGHT_CFG_osch_db_arb_weight(unsigned int uosch_db_arb_weight); +int iSetDB_ARB_WEIGHT_CFG_db_srch_tcam_arb_weight(unsigned int udb_srch_tcam_arb_weight); +int iSetDB_ARB_WEIGHT_CFG_vio_srch_tcam_arb_weight(unsigned int uvio_srch_tcam_arb_weight); +int iSetDB_ARB_WEIGHT_CFG_sw_srch_tcam_arb_weight(unsigned int usw_srch_tcam_arb_weight); +int iSetOSCH_DB_FIFO_AF_TH_osch_db_fifo_af_th(unsigned int uosch_db_fifo_af_th); +int iSetVIRTIO_DB_FIFO_AF_TH_virtio_db_fifo_af_th(unsigned int uvirtio_db_fifo_af_th); +int iSetDWQE_DB_FIFO_AF_TH_dwqe_db_fifo_af_th(unsigned int udwqe_db_fifo_af_th); +int iSetQMAP_TCAM_RSVD_CFG_tcam_top_msk_cfg(unsigned int utcam_top_msk_cfg); +int iSetQMAP_TCAM_RSVD_CFG_tcam_top_valid_bit_mask_cfg(unsigned int utcam_top_valid_bit_mask_cfg); +int iSetNVME_DB_COS_CFG_nvme_db_cos_0(unsigned int unvme_db_cos_0); +int iSetNVME_DB_COS_CFG_nvme_db_cos_1(unsigned int unvme_db_cos_1); +int iSetVIRTIO_DB_COS_CFG_virtio_db_cos_rq(unsigned int uvirtio_db_cos_rq); +int iSetVIRTIO_DB_COS_CFG_virtio_db_cos_sq(unsigned int uvirtio_db_cos_sq); +int iSetVIRTIO_DB_COS_CFG_virtio_db_cos_ctrlq(unsigned int uvirtio_db_cos_ctrlq); +int iSetVIRTIO_DB_COS_CFG_virtio_db_cos_eventq(unsigned int uvirtio_db_cos_eventq); +int iSetVIRTIO_DB_COS_CFG_virtio_db_cos_rqstq(unsigned int uvirtio_db_cos_rqstq); +int iSetVIRTIO_ITF_DFX_CFG_virtio_lb_only_smf0_en(unsigned int uvirtio_lb_only_smf0_en); +int iSetVIRTIO_ITF_DFX_CFG_virtio_err_rtn_cpl_en(unsigned int uvirtio_err_rtn_cpl_en); +int iSetVIRTIO_ITF_DFX_CFG_1_sfifo_tlp_af_th(unsigned int usfifo_tlp_af_th); +int iSetVIRTIO_ITF_DFX_STS0_bitmap_exhauste(unsigned int ubitmap_exhauste); +int iSetVIRTIO_ITF_DFX_STS0_virtio_use_tag_cnt(unsigned int uvirtio_use_tag_cnt); +int iSetVIRTIO_ITF_DFX_STS0_o_free_addr_cnt(unsigned int uo_free_addr_cnt); +int iSetVIRTIO_ITF_DFX_STS0_send_location_flag(unsigned int usend_location_flag); +int iSetVIRTIO_ITF_DFX_STS0_sfifo_tlp_full(unsigned int usfifo_tlp_full); +int iSetVIRTIO_ITF_DFX_STS0_sfifo_msix_full(unsigned int usfifo_msix_full); +int iSetVIRTIO_ITF_DFX_STS0_api_sfifo_full(unsigned int uapi_sfifo_full); +int iSetVIRTIO_ITF_DFX_STS0_direct_sfifo_full(unsigned int udirect_sfifo_full); +int iSetVIRTIO_ITF_DFX_STS0_sfifo_tlp_empty(unsigned int usfifo_tlp_empty); +int iSetVIRTIO_ITF_DFX_STS0_sfifo_msix_empty(unsigned int usfifo_msix_empty); +int iSetVIRTIO_ITF_DFX_STS0_api_sfifo_empty(unsigned int uapi_sfifo_empty); +int iSetVIRTIO_ITF_DFX_STS0_direct_sfifo_empty(unsigned int udirect_sfifo_empty); +int iSetVIO_FLR_DLY_TIMER_TH_vio_flr_dly_timer_th(unsigned int uvio_flr_dly_timer_th); +int iSetVIO_FLR_DLY_TIMER_UNIT_vio_flr_dly_timer_unit(unsigned int uvio_flr_dly_timer_unit); +int iSetVIO_FLR_ENABLE_DLY_vio_flr_enable_dly(unsigned int uvio_flr_enable_dly); +int iSetIB_MISC_MCTP_RX_CFG_mctp_rx_non_mctp_drop_en(unsigned int umctp_rx_non_mctp_drop_en); +int iSetIB_MISC_MCTP_RX_CFG_mctp_rx_hed_byte_order_en(unsigned int umctp_rx_hed_byte_order_en); +int iSetIB_MISC_PCIE_ITF_CFG_cpi_pcie_rx_cpl_data_crd_vld(unsigned int ucpi_pcie_rx_cpl_data_crd_vld); +int iSetIB_MISC_PCIE_ITF_CFG_cpi_pcie_rx_req_data_crd_vld(unsigned int ucpi_pcie_rx_req_data_crd_vld); +int iSetIB_MISC_PCIE_ITF_CFG_cpi_pcie_rx_cpl_crd_active_en(unsigned int ucpi_pcie_rx_cpl_crd_active_en); +int iSetIB_MISC_PCIE_ITF_CFG_cpi_pcie_rx_req_crd_active_en(unsigned int ucpi_pcie_rx_req_crd_active_en); +int iSetIB_MISC_PCIE_ITF_CFG_pcie_cpi_rx_cpl_crd_active_en(unsigned int upcie_cpi_rx_cpl_crd_active_en); +int iSetIB_MISC_PCIE_ITF_CFG_pcie_cpi_rx_req_crd_active_en(unsigned int upcie_cpi_rx_req_crd_active_en); +int iSetVIRTIO_RSVD_Q_CFG_virtio_rsvd0_q_index(unsigned int uvirtio_rsvd0_q_index); +int iSetVIRTIO_RSVD_Q_CFG_virtio_rsvd0_q_type(unsigned int uvirtio_rsvd0_q_type); +int iSetVIRTIO_RSVD_Q_CFG_virtio_rsvd1_q_index(unsigned int uvirtio_rsvd1_q_index); +int iSetVIRTIO_RSVD_Q_CFG_virtio_rsvd1_q_type(unsigned int uvirtio_rsvd1_q_type); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ0(unsigned int uvirtio_cos_sq_cfg_typ0); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ1(unsigned int uvirtio_cos_sq_cfg_typ1); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ2(unsigned int uvirtio_cos_sq_cfg_typ2); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ3(unsigned int uvirtio_cos_sq_cfg_typ3); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ4(unsigned int uvirtio_cos_sq_cfg_typ4); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ5(unsigned int uvirtio_cos_sq_cfg_typ5); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ6(unsigned int uvirtio_cos_sq_cfg_typ6); +int iSetVIRTIO_COS_SQ_CFG0_virtio_cos_sq_cfg_typ7(unsigned int uvirtio_cos_sq_cfg_typ7); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ8(unsigned int uvirtio_cos_sq_cfg_typ8); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ9(unsigned int uvirtio_cos_sq_cfg_typ9); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ10(unsigned int uvirtio_cos_sq_cfg_typ10); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ11(unsigned int uvirtio_cos_sq_cfg_typ11); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ12(unsigned int uvirtio_cos_sq_cfg_typ12); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ13(unsigned int uvirtio_cos_sq_cfg_typ13); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ14(unsigned int uvirtio_cos_sq_cfg_typ14); +int iSetVIRTIO_COS_SQ_CFG1_virtio_cos_sq_cfg_typ15(unsigned int uvirtio_cos_sq_cfg_typ15); +int iSetVIRTIO_COS_SQ_RP_EN_ALL_virtio_cos_rp_en(unsigned int uvirtio_cos_rp_en); +int iSetVIRTIO_DIRECT_FIFO_AF_TH_direct_fifo_af_th(unsigned int udirect_fifo_af_th); +int iSetVIRTIO_API_FIFO_AF_TH_api_fifo_af_th(unsigned int uapi_fifo_af_th); + +/* Define the union csr_cpath_csr_inj_enj_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_csr_enj_cnt : 16; /* [15:0] */ + u32 cpath_csr_inj_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_csr_inj_enj_cnt_u; + +/* Define the union csr_cpath_inbd_inj_enj_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_enj_cnt : 16; /* [15:0] */ + u32 cpath_inbd_inj_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_inbd_inj_enj_cnt_u; + +/* Define the union csr_cpath_non_cpi_int_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_non_cpi_int_cnt_sf : 16; /* [15:0] */ + u32 cpath_non_cpi_int_cnt_hw : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_non_cpi_int_cnt_u; + +/* Define the union csr_cpath_enj_rsvd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_enj_rsvd_cnt : 16; /* [15:0] */ + u32 cpath_csr_enj_rsvd_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_rsvd_cnt_u; + +/* Define the union csr_cpath_enj_nml_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_enj_nml_cnt : 16; /* [15:0] */ + u32 cpath_csr_enj_nml_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_enj_nml_cnt_u; + +/* Define the union csr_cpath_inbd_oubd_cnt_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 2; /* [1:0] */ + u32 cpath_inbd_enj_cnt_type : 1; /* [2] */ + u32 cpath_inbd_inj_cnt_type : 1; /* [3] */ + u32 rsv_1 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_inbd_oubd_cnt_type_u; + +/* Define the union csr_cpath_fifo_aful_gap_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_csr_pe_fifo_aful_gap_cpi : 5; /* [4:0] */ + u32 rsv_2 : 3; /* [7:5] */ + u32 cpath_csr_pi_fifo_aful_gap_cpi : 5; /* [12:8] */ + u32 rsv_3 : 3; /* [15:13] */ + u32 cpath_inbd_pe_fifo_aful_gap_cpi : 6; /* [21:16] */ + u32 rsv_4 : 2; /* [23:22] */ + u32 cpath_inbd_pi_fifo_aful_gap_cpi : 5; /* [28:24] */ + u32 rsv_5 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_fifo_aful_gap_0_u; + +/* Define the union csr_cpath_reservd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsvd : 8; /* [7:0] */ + u32 smu_lastword : 1; /* [8] */ + u32 npu_lastwoed : 1; /* [9] */ + u32 mpu_wdog : 1; /* [10] */ + u32 mpu_lastword : 1; /* [11] */ + u32 wr_phy_timeout : 1; /* [12] */ + u32 wr_mem_timeout : 1; /* [13] */ + u32 wr_reg_timeout : 1; /* [14] */ + u32 sfp_high_temperature_port3 : 1; /* [15] */ + u32 sfp_high_temperature_port2 : 1; /* [16] */ + u32 sfp_high_temperature_port1 : 1; /* [17] */ + u32 sfp_high_temperature_port0 : 1; /* [18] */ + u32 chip_low_temperature : 1; /* [19] */ + u32 chip_high_temperature : 1; /* [20] */ + u32 logic_except : 1; /* [21] */ + u32 host0_heart : 1; /* [22] */ + u32 host1_heart : 1; /* [23] */ + u32 host2_heart : 1; /* [24] */ + u32 host3_heart : 1; /* [25] */ + u32 host4_heart : 1; /* [26] */ + u32 mpu_init_done : 2; /* [28:27] */ + u32 mpu_boot_cause : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_reservd_u; + +/* Define the union csr_cpath_itf_sts_out_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_itf_sts_out : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_itf_sts_out_u; + +/* Define the union csr_cpath_csr_sfifo_pe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_csr_sfifo_pe1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_csr_sfifo_pe1_u; + +/* Define the union csr_cpath_csr_sfifo_pe0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_csr_sfifo_pe0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_csr_sfifo_pe0_u; + +/* Define the union csr_cpath_csr_sfifo_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_csr_sfifo_pi : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_csr_sfifo_pi_u; + +/* Define the union csr_cpath_inbd_sfifo_pe1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_sfifo_pe1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_inbd_sfifo_pe1_u; + +/* Define the union csr_cpath_inbd_sfifo_pe0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_sfifo_pe0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_inbd_sfifo_pe0_u; + +/* Define the union csr_cpath_inbd_sfifo_pi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_inbd_sfifo_pi : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_inbd_sfifo_pi_u; + +/* Define the union csr_cpath_out_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_out_pls_u; + +/* Define the union csr_glb_ijt_node_id_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ijt_ring_node_id_bitmap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ijt_node_id_bitmap_u; + +/* Define the union csr_glb_ejt_node_id_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ejt_ring_node_id_bitmap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ejt_node_id_bitmap_u; + +/* Define the union csr_cpath_out_a_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_a_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_out_a_fatal_msk_u; + +/* Define the union csr_cpath_out_a_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_out_a_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpath_out_a_nonfatal_msk_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck0_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck1_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck2_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck3_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck4_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck5_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck6_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck7_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck8_u; + +/* Define the union csr_dfx_cpath_pe_rsp_lck9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cpath_pe_rsp_lck9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_cpath_pe_rsp_lck9_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cpath_csr_inj_enj_cnt_u cpath_csr_inj_enj_cnt; /* 10 */ + volatile csr_cpath_inbd_inj_enj_cnt_u cpath_inbd_inj_enj_cnt; /* 14 */ + volatile csr_cpath_non_cpi_int_cnt_u cpath_non_cpi_int_cnt; /* 1C */ + volatile csr_cpath_enj_rsvd_cnt_u cpath_enj_rsvd_cnt; /* 20 */ + volatile csr_cpath_enj_nml_cnt_u cpath_enj_nml_cnt; /* 24 */ + volatile csr_cpath_inbd_oubd_cnt_type_u cpath_inbd_oubd_cnt_type; /* 2C */ + volatile csr_cpath_fifo_aful_gap_0_u cpath_fifo_aful_gap_0; /* 30 */ + volatile csr_cpath_reservd_u cpath_reservd; /* 3C */ + volatile csr_cpath_itf_sts_out_u cpath_itf_sts_out; /* 44 */ + volatile csr_cpath_csr_sfifo_pe1_u cpath_csr_sfifo_pe1; /* 4C */ + volatile csr_cpath_csr_sfifo_pe0_u cpath_csr_sfifo_pe0; /* 50 */ + volatile csr_cpath_csr_sfifo_pi_u cpath_csr_sfifo_pi; /* 54 */ + volatile csr_cpath_inbd_sfifo_pe1_u cpath_inbd_sfifo_pe1; /* 58 */ + volatile csr_cpath_inbd_sfifo_pe0_u cpath_inbd_sfifo_pe0; /* 5C */ + volatile csr_cpath_inbd_sfifo_pi_u cpath_inbd_sfifo_pi; /* 60 */ + volatile csr_cpath_out_pls_u cpath_out_pls; /* 70 */ + volatile csr_glb_ijt_node_id_bitmap_u glb_ijt_node_id_bitmap; /* 80 */ + volatile csr_glb_ejt_node_id_bitmap_u glb_ejt_node_id_bitmap; /* 84 */ + volatile csr_cpath_out_a_fatal_msk_u cpath_out_a_fatal_msk; /* 100 */ + volatile csr_cpath_out_a_nonfatal_msk_u cpath_out_a_nonfatal_msk; /* 104 */ + volatile csr_dfx_cpath_pe_rsp_lck0_u dfx_cpath_pe_rsp_lck0; /* 110 */ + volatile csr_dfx_cpath_pe_rsp_lck1_u dfx_cpath_pe_rsp_lck1; /* 114 */ + volatile csr_dfx_cpath_pe_rsp_lck2_u dfx_cpath_pe_rsp_lck2; /* 118 */ + volatile csr_dfx_cpath_pe_rsp_lck3_u dfx_cpath_pe_rsp_lck3; /* 11C */ + volatile csr_dfx_cpath_pe_rsp_lck4_u dfx_cpath_pe_rsp_lck4; /* 120 */ + volatile csr_dfx_cpath_pe_rsp_lck5_u dfx_cpath_pe_rsp_lck5; /* 124 */ + volatile csr_dfx_cpath_pe_rsp_lck6_u dfx_cpath_pe_rsp_lck6; /* 128 */ + volatile csr_dfx_cpath_pe_rsp_lck7_u dfx_cpath_pe_rsp_lck7; /* 12C */ + volatile csr_dfx_cpath_pe_rsp_lck8_u dfx_cpath_pe_rsp_lck8; /* 130 */ + volatile csr_dfx_cpath_pe_rsp_lck9_u dfx_cpath_pe_rsp_lck9; /* 134 */ +} S_dfx_cpath_csr_REGS_TYPE; + +/* Declare the struct pointor of the module dfx_cpath_csr */ +extern volatile S_dfx_cpath_csr_REGS_TYPE *gopdfx_cpath_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCPATH_CSR_INJ_ENJ_CNT_cpath_csr_enj_cnt(unsigned int ucpath_csr_enj_cnt); +int iSetCPATH_CSR_INJ_ENJ_CNT_cpath_csr_inj_cnt(unsigned int ucpath_csr_inj_cnt); +int iSetCPATH_INBD_INJ_ENJ_CNT_cpath_inbd_enj_cnt(unsigned int ucpath_inbd_enj_cnt); +int iSetCPATH_INBD_INJ_ENJ_CNT_cpath_inbd_inj_cnt(unsigned int ucpath_inbd_inj_cnt); +int iSetCPATH_NON_CPI_INT_CNT_cpath_non_cpi_int_cnt_sf(unsigned int ucpath_non_cpi_int_cnt_sf); +int iSetCPATH_NON_CPI_INT_CNT_cpath_non_cpi_int_cnt_hw(unsigned int ucpath_non_cpi_int_cnt_hw); +int iSetCPATH_ENJ_RSVD_CNT_cpath_inbd_enj_rsvd_cnt(unsigned int ucpath_inbd_enj_rsvd_cnt); +int iSetCPATH_ENJ_RSVD_CNT_cpath_csr_enj_rsvd_cnt(unsigned int ucpath_csr_enj_rsvd_cnt); +int iSetCPATH_ENJ_NML_CNT_cpath_inbd_enj_nml_cnt(unsigned int ucpath_inbd_enj_nml_cnt); +int iSetCPATH_ENJ_NML_CNT_cpath_csr_enj_nml_cnt(unsigned int ucpath_csr_enj_nml_cnt); +int iSetCPATH_INBD_OUBD_CNT_TYPE_cpath_inbd_enj_cnt_type(unsigned int ucpath_inbd_enj_cnt_type); +int iSetCPATH_INBD_OUBD_CNT_TYPE_cpath_inbd_inj_cnt_type(unsigned int ucpath_inbd_inj_cnt_type); +int iSetCPATH_FIFO_AFUL_GAP_0_cpath_csr_pe_fifo_aful_gap_cpi(unsigned int ucpath_csr_pe_fifo_aful_gap_cpi); +int iSetCPATH_FIFO_AFUL_GAP_0_cpath_csr_pi_fifo_aful_gap_cpi(unsigned int ucpath_csr_pi_fifo_aful_gap_cpi); +int iSetCPATH_FIFO_AFUL_GAP_0_cpath_inbd_pe_fifo_aful_gap_cpi(unsigned int ucpath_inbd_pe_fifo_aful_gap_cpi); +int iSetCPATH_FIFO_AFUL_GAP_0_cpath_inbd_pi_fifo_aful_gap_cpi(unsigned int ucpath_inbd_pi_fifo_aful_gap_cpi); +int iSetCPATH_RESERVD_cpath_reserved(unsigned int ucpath_reserved); +int iSetCPATH_ITF_STS_OUT_cpath_itf_sts_out(unsigned int ucpath_itf_sts_out); +int iSetCPATH_CSR_SFIFO_PE1_cpath_csr_sfifo_pe1(unsigned int ucpath_csr_sfifo_pe1); +int iSetCPATH_CSR_SFIFO_PE0_cpath_csr_sfifo_pe0(unsigned int ucpath_csr_sfifo_pe0); +int iSetCPATH_CSR_SFIFO_PI_cpath_csr_sfifo_pi(unsigned int ucpath_csr_sfifo_pi); +int iSetCPATH_INBD_SFIFO_PE1_cpath_inbd_sfifo_pe1(unsigned int ucpath_inbd_sfifo_pe1); +int iSetCPATH_INBD_SFIFO_PE0_cpath_inbd_sfifo_pe0(unsigned int ucpath_inbd_sfifo_pe0); +int iSetCPATH_INBD_SFIFO_PI_cpath_inbd_sfifo_pi(unsigned int ucpath_inbd_sfifo_pi); +int iSetCPATH_OUT_PLS_cpath_out_pls(unsigned int ucpath_out_pls); +int iSetGLB_IJT_NODE_ID_BITMAP_glb_ijt_ring_node_id_bitmap(unsigned int uglb_ijt_ring_node_id_bitmap); +int iSetGLB_EJT_NODE_ID_BITMAP_glb_ejt_ring_node_id_bitmap(unsigned int uglb_ejt_ring_node_id_bitmap); +int iSetCPATH_OUT_A_FATAL_MSK_cpath_out_a_fatal_msk(unsigned int ucpath_out_a_fatal_msk); +int iSetCPATH_OUT_A_NONFATAL_MSK_cpath_out_a_nonfatal_msk(unsigned int ucpath_out_a_nonfatal_msk); +int iSetDFX_CPATH_PE_RSP_LCK0_dfx_cpath_pe_rsp_lck0(unsigned int udfx_cpath_pe_rsp_lck0); +int iSetDFX_CPATH_PE_RSP_LCK1_dfx_cpath_pe_rsp_lck1(unsigned int udfx_cpath_pe_rsp_lck1); +int iSetDFX_CPATH_PE_RSP_LCK2_dfx_cpath_pe_rsp_lck2(unsigned int udfx_cpath_pe_rsp_lck2); +int iSetDFX_CPATH_PE_RSP_LCK3_dfx_cpath_pe_rsp_lck3(unsigned int udfx_cpath_pe_rsp_lck3); +int iSetDFX_CPATH_PE_RSP_LCK4_dfx_cpath_pe_rsp_lck4(unsigned int udfx_cpath_pe_rsp_lck4); +int iSetDFX_CPATH_PE_RSP_LCK5_dfx_cpath_pe_rsp_lck5(unsigned int udfx_cpath_pe_rsp_lck5); +int iSetDFX_CPATH_PE_RSP_LCK6_dfx_cpath_pe_rsp_lck6(unsigned int udfx_cpath_pe_rsp_lck6); +int iSetDFX_CPATH_PE_RSP_LCK7_dfx_cpath_pe_rsp_lck7(unsigned int udfx_cpath_pe_rsp_lck7); +int iSetDFX_CPATH_PE_RSP_LCK8_dfx_cpath_pe_rsp_lck8(unsigned int udfx_cpath_pe_rsp_lck8); +int iSetDFX_CPATH_PE_RSP_LCK9_dfx_cpath_pe_rsp_lck9(unsigned int udfx_cpath_pe_rsp_lck9); + +/* Define the union csr_apictl_dbg_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_aeqe_drop_dis : 1; /* [0] */ + u32 rsv_0 : 3; /* [3:1] */ + u32 api_ctl_dbg_sel : 3; /* [6:4] */ + u32 rsv_1 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_sel_u; + +/* Define the union csr_apictl_af_th0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_2 : 16; /* [15:0] */ + u32 apiitf_dir_acc_af_th : 8; /* [23:16] */ + u32 apiitf_inbd_af_th : 5; /* [28:24] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_af_th0_u; + +/* Define the union csr_apictl_af_th1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apiitf_inline_wqe_af_th : 4; /* [3:0] */ + u32 rsv_4 : 4; /* [7:4] */ + u32 apiitf_resp_af_th : 5; /* [12:8] */ + u32 rsv_5 : 3; /* [15:13] */ + u32 api_ctl_upitf_af_th : 6; /* [21:16] */ + u32 rsv_6 : 2; /* [23:22] */ + u32 api_ctl_aeqe_data_af_th : 4; /* [27:24] */ + u32 rsv_7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_af_th1_u; + +/* Define the union csr_apictl_af_th2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_non_cpi_int_af_th : 9; /* [8:0] */ + u32 rsv_8 : 7; /* [15:9] */ + u32 apiitf_virtio_acc_af_th : 8; /* [23:16] */ + u32 rsv_9 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_af_th2_u; + +/* Define the union csr_apictl_af_th3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apichn_cpld_fifo_af_th : 5; /* [4:0] */ + u32 rsv_10 : 3; /* [7:5] */ + u32 apichn_rsp_fifo_af_th : 4; /* [11:8] */ + u32 api_ctl_nl2_fifo_af_th : 2; /* [13:12] */ + u32 rsv_11 : 2; /* [15:14] */ + u32 api_ctl_tile_acc_fifo_af_th : 10; /* [25:16] */ + u32 rsv_12 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_af_th3_u; + +/* Define the union csr_apictl_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_inbd_noncsr_cnt : 16; /* [15:0] */ + u32 api_ctl_inbd_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_cnt2_u; + +/* Define the union csr_apictl_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_inbd_csr_cnt : 16; /* [15:0] */ + u32 api_ctl_inbd_up_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_cnt3_u; + +/* Define the union csr_apictl_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dir_acc_cnt : 16; /* [15:0] */ + u32 api_ctl_inline_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_cnt4_u; + +/* Define the union csr_apictl_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_up_tx_cnt : 16; /* [15:0] */ + u32 api_ctl_resp_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_cnt5_u; + +/* Define the union csr_apictl_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_noncsr_tag : 16; /* [15:0] */ + u32 api_ctl_csr_tag : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_cnt6_u; + +/* Define the union csr_apictl_reservd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chip_type : 2; /* [1:0] */ + u32 chip_ver : 2; /* [3:2] */ + u32 spu_en : 1; /* [4] */ + u32 host_num : 3; /* [7:5] */ + u32 cfg_template_id : 4; /* [11:8] */ + u32 board_type : 8; /* [19:12] */ + u32 board_id : 4; /* [23:20] */ + u32 mpu_ver : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_reservd_u; + +/* Define the union csr_apictl_out_a_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_out_a_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_a_pls_u; + +/* Define the union csr_apictl_out_b_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_out_b_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_b_pls_u; + +/* Define the union csr_apictl_non_csr_timer_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_noncsr_timer_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_non_csr_timer_th_u; + +/* Define the union csr_apictl_csr_timer_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_csr_timer_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_csr_timer_th_u; + +/* Define the union csr_apictl_dbg_out_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_a_u; + +/* Define the union csr_apictl_dbg_out_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_b_u; + +/* Define the union csr_apictl_dbg_out_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_c_u; + +/* Define the union csr_apictl_dbg_out_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_d_u; + +/* Define the union csr_apictl_dbg_out_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_e_u; + +/* Define the union csr_apictl_dbg_out_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_f_u; + +/* Define the union csr_apictl_dbg_out_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_g_u; + +/* Define the union csr_apictl_dbg_out_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_h_u; + +/* Define the union csr_apictl_dbg_out_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_i_u; + +/* Define the union csr_apictl_dbg_out_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_j_u; + +/* Define the union csr_apictl_dbg_out_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_k_u; + +/* Define the union csr_apictl_dbg_out_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_l_u; + +/* Define the union csr_apictl_dbg_out_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_m_u; + +/* Define the union csr_apictl_dbg_out_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_n_u; + +/* Define the union csr_apictl_dbg_out_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_o_u; + +/* Define the union csr_apictl_dbg_out_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_p_u; + +/* Define the union csr_apictl_dbg_out_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_q_u; + +/* Define the union csr_apictl_dbg_out_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_r_u; + +/* Define the union csr_apictl_dbg_out_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_s_u; + +/* Define the union csr_apictl_dbg_out_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_t : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_t_u; + +/* Define the union csr_apictl_dbg_out_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_u_u; + +/* Define the union csr_apictl_dbg_out_v_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_v_u; + +/* Define the union csr_apictl_dbg_out_w_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_w : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_w_u; + +/* Define the union csr_apictl_dbg_out_x_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_x : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_x_u; + +/* Define the union csr_apictl_dbg_out_y_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_y : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_y_u; + +/* Define the union csr_apictl_dbg_out_z_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_out_z : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_out_z_u; + +/* Define the union csr_apictl_dbg_fifo_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_a_u; + +/* Define the union csr_apictl_dbg_fifo_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_b_u; + +/* Define the union csr_apictl_dbg_fifo_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_c_u; + +/* Define the union csr_apictl_dbg_fifo_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_d_u; + +/* Define the union csr_apictl_dbg_fifo_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_e_u; + +/* Define the union csr_apictl_dbg_fifo_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_f_u; + +/* Define the union csr_apictl_dbg_fifo_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_g_u; + +/* Define the union csr_apictl_dbg_fifo_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_h_u; + +/* Define the union csr_apictl_dbg_fifo_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_i_u; + +/* Define the union csr_apictl_dbg_fifo_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_j_u; + +/* Define the union csr_apictl_dbg_fifo_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_k_u; + +/* Define the union csr_apictl_dbg_fifo_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_l_u; + +/* Define the union csr_apictl_dbg_fifo_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_m_u; + +/* Define the union csr_apictl_dbg_fifo_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_n_u; + +/* Define the union csr_apictl_dbg_fifo_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_o_u; + +/* Define the union csr_apictl_dbg_fifo_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_p_u; + +/* Define the union csr_apictl_dbg_fifo_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_q_u; + +/* Define the union csr_apictl_dbg_fifo_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_r_u; + +/* Define the union csr_apictl_dbg_fifo_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_dbg_fifo_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_dbg_fifo_s_u; + +/* Define the union csr_inbd_ring_buf_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_inbd_ring_buf_crdt : 8; /* [7:0] */ + u32 rsv_13 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_inbd_ring_buf_crdt_u; + +/* Define the union csr_inbd_cmd_rd_so_ro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_inbd_cmd_rd_so_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_inbd_cmd_rd_so_ro_u; + +/* Define the union csr_tilep_dfx_ro_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_cur_st : 8; /* [7:0] */ + u32 tilep_fifo_cmd_cnt : 8; /* [15:8] */ + u32 tilep_indir_sts : 1; /* [16] */ + u32 apictl_tile_rsp_err_lock : 1; /* [17] */ + u32 tilep_e0_err : 1; /* [18] */ + u32 rsv_14 : 5; /* [23:19] */ + u32 tilep_err_code : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_ro_0_u; + +/* Define the union csr_tilep_dfx_ro_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_wr_dat_cnt : 5; /* [4:0] */ + u32 rsv_15 : 3; /* [7:5] */ + u32 tilep_indir_rd_tx_rsp_cnt : 5; /* [12:8] */ + u32 rsv_16 : 3; /* [15:13] */ + u32 tilep_rd_dat_cnt : 5; /* [20:16] */ + u32 rsv_17 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_ro_1_u; + +/* Define the union csr_tilep_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_cmd_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_0_u; + +/* Define the union csr_tilep_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_cmd_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_1_u; + +/* Define the union csr_tilep_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_cmd_ok_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_2_u; + +/* Define the union csr_tilep_dfx_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_csr_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_3_u; + +/* Define the union csr_tilep_dfx_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_indir_rd_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_4_u; + +/* Define the union csr_tilep_dfx_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_indir_wr_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_5_u; + +/* Define the union csr_tilep_dfx_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_tx_api_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_6_u; + +/* Define the union csr_tilep_dfx_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_tx_api_np_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_7_u; + +/* Define the union csr_tilep_dfx_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_rx_api_rsp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_8_u; + +/* Define the union csr_tilep_dfx_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_rx_api_rsp_e0_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_9_u; + +/* Define the union csr_tilep_dfx_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_rx_api_rsp_sts_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_10_u; + +/* Define the union csr_tilep_dfx_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_poll_req_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_11_u; + +/* Define the union csr_tilep_dfx_cnt_12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_rtn_rsp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_12_u; + +/* Define the union csr_tilep_dfx_cnt_13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_csr_no_ack_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_13_u; + +/* Define the union csr_tilep_dfx_cnt_14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tilep_indir_no_ack_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tilep_dfx_cnt_14_u; + +/* Define the union csr_nl2_dfx_ro_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_acc_cur_st : 3; /* [2:0] */ + u32 rsv_18 : 1; /* [3] */ + u32 nl2_finish_cur_st : 4; /* [7:4] */ + u32 nl2_acc_crdt_cnt : 5; /* [12:8] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 first_available_ctx_idx : 4; /* [19:16] */ + u32 cur_rsp_ctx_idx : 4; /* [23:20] */ + u32 rsv_20 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_ro_0_u; + +/* Define the union csr_nl2_dfx_ro_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_ctx_sm_miss : 16; /* [15:0] */ + u32 nl2_ctx_vld : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_ro_1_u; + +/* Define the union csr_nl2_dfx_cnt_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_0_u; + +/* Define the union csr_nl2_dfx_cnt_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_prt0_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_1_u; + +/* Define the union csr_nl2_dfx_cnt_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_prt1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_2_u; + +/* Define the union csr_nl2_dfx_cnt_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_prt2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_3_u; + +/* Define the union csr_nl2_dfx_cnt_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_prt3_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_4_u; + +/* Define the union csr_nl2_dfx_cnt_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_cmd_rev_prt4_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_5_u; + +/* Define the union csr_nl2_dfx_cnt_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_sub_cmd_tx_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_6_u; + +/* Define the union csr_nl2_dfx_cnt_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_sub_rsp_rx_total_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_7_u; + +/* Define the union csr_nl2_dfx_cnt_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_sub_rsp_rx_miss_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_8_u; + +/* Define the union csr_nl2_dfx_cnt_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_sub_rsp_rx_abort_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_9_u; + +/* Define the union csr_nl2_dfx_cnt_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_rtn_icpl_done_success_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_10_u; + +/* Define the union csr_nl2_dfx_cnt_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_rtn_icpl_done_fail_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_11_u; + +/* Define the union csr_nl2_dfx_cnt_12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_rtn_icpl_set_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_12_u; + +/* Define the union csr_nl2_dfx_cnt_13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nl2_rtn_icpl_set_rej_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nl2_dfx_cnt_13_u; + +/* Define the union csr_apictl_out_a_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apictl_out_a_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_a_fatal_msk_u; + +/* Define the union csr_apictl_out_b_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apictl_out_b_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_b_fatal_msk_u; + +/* Define the union csr_apictl_out_a_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apictl_out_a_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_a_nonfatal_msk_u; + +/* Define the union csr_apictl_out_b_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apictl_out_b_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_out_b_nonfatal_msk_u; + +/* Define the union csr_glb_api_chn_right_ctl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_api_chn_root_right : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_api_chn_right_ctl0_u; + +/* Define the union csr_glb_api_chn_right_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_api_chn_non_bypass_right : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_api_chn_right_ctl1_u; + +/* Define the union csr_glb_api_chn_right_ctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_api_chn_other_right : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_api_chn_right_ctl2_u; + +/* Define the union csr_apictl_tag_cmp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apictl_csr_tag_cmp_th : 6; /* [5:0] */ + u32 rsv_21 : 2; /* [7:6] */ + u32 apictl_noncsr_tag_cmp_th : 6; /* [13:8] */ + u32 rsv_22 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apictl_tag_cmp_th_u; + +/* Define the union csr_apiitf_dfx_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_virtio_cnt : 16; /* [15:0] */ + u32 api_ctl_tile_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apiitf_dfx_cnt0_u; + +/* Define the union csr_apiitf_dfx_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_csr_wr_dest_illg_cnt : 16; /* [15:0] */ + u32 api_ctl_csr_rd_dest_illg_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apiitf_dfx_cnt1_u; + +/* Define the union csr_apiitf_dfx_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_ctl_noncsr_wr_dest_illg_cnt : 16; /* [15:0] */ + u32 api_ctl_noncsr_rd_dest_illg_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apiitf_dfx_cnt2_u; + +/* Define the union csr_apiitf_ring_dest_illg_src_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 apiitf_ring_dest_illg_src : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_apiitf_ring_dest_illg_src_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_apictl_dbg_sel_u apictl_dbg_sel; /* 0 */ + volatile csr_apictl_af_th0_u apictl_af_th0; /* 4 */ + volatile csr_apictl_af_th1_u apictl_af_th1; /* 8 */ + volatile csr_apictl_af_th2_u apictl_af_th2; /* C */ + volatile csr_apictl_af_th3_u apictl_af_th3; /* 10 */ + volatile csr_apictl_cnt2_u apictl_cnt2; /* 18 */ + volatile csr_apictl_cnt3_u apictl_cnt3; /* 1C */ + volatile csr_apictl_cnt4_u apictl_cnt4; /* 20 */ + volatile csr_apictl_cnt5_u apictl_cnt5; /* 24 */ + volatile csr_apictl_cnt6_u apictl_cnt6; /* 28 */ + volatile csr_apictl_reservd_u apictl_reservd; /* 2C */ + volatile csr_apictl_out_a_pls_u apictl_out_a_pls; /* 30 */ + volatile csr_apictl_out_b_pls_u apictl_out_b_pls; /* 34 */ + volatile csr_apictl_non_csr_timer_th_u apictl_non_csr_timer_th; /* 38 */ + volatile csr_apictl_csr_timer_th_u apictl_csr_timer_th; /* 3C */ + volatile csr_apictl_dbg_out_a_u apictl_dbg_out_a; /* 40 */ + volatile csr_apictl_dbg_out_b_u apictl_dbg_out_b; /* 44 */ + volatile csr_apictl_dbg_out_c_u apictl_dbg_out_c; /* 48 */ + volatile csr_apictl_dbg_out_d_u apictl_dbg_out_d; /* 4C */ + volatile csr_apictl_dbg_out_e_u apictl_dbg_out_e; /* 50 */ + volatile csr_apictl_dbg_out_f_u apictl_dbg_out_f; /* 54 */ + volatile csr_apictl_dbg_out_g_u apictl_dbg_out_g; /* 58 */ + volatile csr_apictl_dbg_out_h_u apictl_dbg_out_h; /* 5C */ + volatile csr_apictl_dbg_out_i_u apictl_dbg_out_i; /* 60 */ + volatile csr_apictl_dbg_out_j_u apictl_dbg_out_j; /* 64 */ + volatile csr_apictl_dbg_out_k_u apictl_dbg_out_k; /* 68 */ + volatile csr_apictl_dbg_out_l_u apictl_dbg_out_l; /* 6C */ + volatile csr_apictl_dbg_out_m_u apictl_dbg_out_m; /* 70 */ + volatile csr_apictl_dbg_out_n_u apictl_dbg_out_n; /* 74 */ + volatile csr_apictl_dbg_out_o_u apictl_dbg_out_o; /* 78 */ + volatile csr_apictl_dbg_out_p_u apictl_dbg_out_p; /* 7C */ + volatile csr_apictl_dbg_out_q_u apictl_dbg_out_q; /* 80 */ + volatile csr_apictl_dbg_out_r_u apictl_dbg_out_r; /* 84 */ + volatile csr_apictl_dbg_out_s_u apictl_dbg_out_s; /* 88 */ + volatile csr_apictl_dbg_out_t_u apictl_dbg_out_t; /* 8C */ + volatile csr_apictl_dbg_out_u_u apictl_dbg_out_u; /* 90 */ + volatile csr_apictl_dbg_out_v_u apictl_dbg_out_v; /* 94 */ + volatile csr_apictl_dbg_out_w_u apictl_dbg_out_w; /* 98 */ + volatile csr_apictl_dbg_out_x_u apictl_dbg_out_x; /* 9C */ + volatile csr_apictl_dbg_out_y_u apictl_dbg_out_y; /* A0 */ + volatile csr_apictl_dbg_out_z_u apictl_dbg_out_z; /* A4 */ + volatile csr_apictl_dbg_fifo_a_u apictl_dbg_fifo_a; /* B0 */ + volatile csr_apictl_dbg_fifo_b_u apictl_dbg_fifo_b; /* B4 */ + volatile csr_apictl_dbg_fifo_c_u apictl_dbg_fifo_c; /* B8 */ + volatile csr_apictl_dbg_fifo_d_u apictl_dbg_fifo_d; /* BC */ + volatile csr_apictl_dbg_fifo_e_u apictl_dbg_fifo_e; /* C0 */ + volatile csr_apictl_dbg_fifo_f_u apictl_dbg_fifo_f; /* C4 */ + volatile csr_apictl_dbg_fifo_g_u apictl_dbg_fifo_g; /* C8 */ + volatile csr_apictl_dbg_fifo_h_u apictl_dbg_fifo_h; /* CC */ + volatile csr_apictl_dbg_fifo_i_u apictl_dbg_fifo_i; /* D0 */ + volatile csr_apictl_dbg_fifo_j_u apictl_dbg_fifo_j; /* D4 */ + volatile csr_apictl_dbg_fifo_k_u apictl_dbg_fifo_k; /* D8 */ + volatile csr_apictl_dbg_fifo_l_u apictl_dbg_fifo_l; /* DC */ + volatile csr_apictl_dbg_fifo_m_u apictl_dbg_fifo_m; /* E0 */ + volatile csr_apictl_dbg_fifo_n_u apictl_dbg_fifo_n; /* E4 */ + volatile csr_apictl_dbg_fifo_o_u apictl_dbg_fifo_o; /* E8 */ + volatile csr_apictl_dbg_fifo_p_u apictl_dbg_fifo_p; /* EC */ + volatile csr_apictl_dbg_fifo_q_u apictl_dbg_fifo_q; /* F0 */ + volatile csr_apictl_dbg_fifo_r_u apictl_dbg_fifo_r; /* F4 */ + volatile csr_apictl_dbg_fifo_s_u apictl_dbg_fifo_s; /* F8 */ + volatile csr_inbd_ring_buf_crdt_u inbd_ring_buf_crdt; /* 108 */ + volatile csr_inbd_cmd_rd_so_ro_u inbd_cmd_rd_so_ro; /* 10C */ + volatile csr_tilep_dfx_ro_0_u tilep_dfx_ro_0; /* 110 */ + volatile csr_tilep_dfx_ro_1_u tilep_dfx_ro_1; /* 114 */ + volatile csr_tilep_dfx_cnt_0_u tilep_dfx_cnt_0; /* 118 */ + volatile csr_tilep_dfx_cnt_1_u tilep_dfx_cnt_1; /* 11C */ + volatile csr_tilep_dfx_cnt_2_u tilep_dfx_cnt_2; /* 120 */ + volatile csr_tilep_dfx_cnt_3_u tilep_dfx_cnt_3; /* 124 */ + volatile csr_tilep_dfx_cnt_4_u tilep_dfx_cnt_4; /* 128 */ + volatile csr_tilep_dfx_cnt_5_u tilep_dfx_cnt_5; /* 12C */ + volatile csr_tilep_dfx_cnt_6_u tilep_dfx_cnt_6; /* 130 */ + volatile csr_tilep_dfx_cnt_7_u tilep_dfx_cnt_7; /* 134 */ + volatile csr_tilep_dfx_cnt_8_u tilep_dfx_cnt_8; /* 138 */ + volatile csr_tilep_dfx_cnt_9_u tilep_dfx_cnt_9; /* 13C */ + volatile csr_tilep_dfx_cnt_10_u tilep_dfx_cnt_10; /* 140 */ + volatile csr_tilep_dfx_cnt_11_u tilep_dfx_cnt_11; /* 144 */ + volatile csr_tilep_dfx_cnt_12_u tilep_dfx_cnt_12; /* 148 */ + volatile csr_tilep_dfx_cnt_13_u tilep_dfx_cnt_13; /* 14C */ + volatile csr_tilep_dfx_cnt_14_u tilep_dfx_cnt_14; /* 150 */ + volatile csr_nl2_dfx_ro_0_u nl2_dfx_ro_0; /* 180 */ + volatile csr_nl2_dfx_ro_1_u nl2_dfx_ro_1; /* 184 */ + volatile csr_nl2_dfx_cnt_0_u nl2_dfx_cnt_0; /* 188 */ + volatile csr_nl2_dfx_cnt_1_u nl2_dfx_cnt_1; /* 18C */ + volatile csr_nl2_dfx_cnt_2_u nl2_dfx_cnt_2; /* 190 */ + volatile csr_nl2_dfx_cnt_3_u nl2_dfx_cnt_3; /* 194 */ + volatile csr_nl2_dfx_cnt_4_u nl2_dfx_cnt_4; /* 198 */ + volatile csr_nl2_dfx_cnt_5_u nl2_dfx_cnt_5; /* 19C */ + volatile csr_nl2_dfx_cnt_6_u nl2_dfx_cnt_6; /* 1A0 */ + volatile csr_nl2_dfx_cnt_7_u nl2_dfx_cnt_7; /* 1A4 */ + volatile csr_nl2_dfx_cnt_8_u nl2_dfx_cnt_8; /* 1A8 */ + volatile csr_nl2_dfx_cnt_9_u nl2_dfx_cnt_9; /* 1AC */ + volatile csr_nl2_dfx_cnt_10_u nl2_dfx_cnt_10; /* 1B0 */ + volatile csr_nl2_dfx_cnt_11_u nl2_dfx_cnt_11; /* 1B4 */ + volatile csr_nl2_dfx_cnt_12_u nl2_dfx_cnt_12; /* 1B8 */ + volatile csr_nl2_dfx_cnt_13_u nl2_dfx_cnt_13; /* 1BC */ + volatile csr_apictl_out_a_fatal_msk_u apictl_out_a_fatal_msk; /* 200 */ + volatile csr_apictl_out_b_fatal_msk_u apictl_out_b_fatal_msk; /* 204 */ + volatile csr_apictl_out_a_nonfatal_msk_u apictl_out_a_nonfatal_msk; /* 210 */ + volatile csr_apictl_out_b_nonfatal_msk_u apictl_out_b_nonfatal_msk; /* 214 */ + volatile csr_glb_api_chn_right_ctl0_u glb_api_chn_right_ctl0; /* 220 */ + volatile csr_glb_api_chn_right_ctl1_u glb_api_chn_right_ctl1; /* 224 */ + volatile csr_glb_api_chn_right_ctl2_u glb_api_chn_right_ctl2; /* 228 */ + volatile csr_apictl_tag_cmp_th_u apictl_tag_cmp_th; /* 230 */ + volatile csr_apiitf_dfx_cnt0_u apiitf_dfx_cnt0; /* 240 */ + volatile csr_apiitf_dfx_cnt1_u apiitf_dfx_cnt1; /* 244 */ + volatile csr_apiitf_dfx_cnt2_u apiitf_dfx_cnt2; /* 248 */ + volatile csr_apiitf_ring_dest_illg_src_u apiitf_ring_dest_illg_src; /* 24C */ +} S_dfx_apictl_csr_REGS_TYPE; + +/* Declare the struct pointor of the module dfx_apictl_csr */ +extern volatile S_dfx_apictl_csr_REGS_TYPE *gopdfx_apictl_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetAPICTL_DBG_SEL_api_ctl_aeqe_drop_dis(unsigned int uapi_ctl_aeqe_drop_dis); +int iSetAPICTL_DBG_SEL_api_ctl_dbg_sel(unsigned int uapi_ctl_dbg_sel); +int iSetAPICTL_AF_TH0_apiitf_dir_acc_af_th(unsigned int uapiitf_dir_acc_af_th); +int iSetAPICTL_AF_TH0_apiitf_inbd_af_th(unsigned int uapiitf_inbd_af_th); +int iSetAPICTL_AF_TH1_apiitf_inline_wqe_af_th(unsigned int uapiitf_inline_wqe_af_th); +int iSetAPICTL_AF_TH1_apiitf_resp_af_th(unsigned int uapiitf_resp_af_th); +int iSetAPICTL_AF_TH1_api_ctl_upitf_af_th(unsigned int uapi_ctl_upitf_af_th); +int iSetAPICTL_AF_TH1_api_ctl_aeqe_data_af_th(unsigned int uapi_ctl_aeqe_data_af_th); +int iSetAPICTL_AF_TH2_api_ctl_non_cpi_int_af_th(unsigned int uapi_ctl_non_cpi_int_af_th); +int iSetAPICTL_AF_TH2_apiitf_virtio_acc_af_th(unsigned int uapiitf_virtio_acc_af_th); +int iSetAPICTL_AF_TH3_apichn_cpld_fifo_af_th(unsigned int uapichn_cpld_fifo_af_th); +int iSetAPICTL_AF_TH3_apichn_rsp_fifo_af_th(unsigned int uapichn_rsp_fifo_af_th); +int iSetAPICTL_AF_TH3_api_ctl_nl2_fifo_af_th(unsigned int uapi_ctl_nl2_fifo_af_th); +int iSetAPICTL_AF_TH3_api_ctl_tile_acc_fifo_af_th(unsigned int uapi_ctl_tile_acc_fifo_af_th); +int iSetAPICTL_CNT2_api_ctl_inbd_noncsr_cnt(unsigned int uapi_ctl_inbd_noncsr_cnt); +int iSetAPICTL_CNT2_api_ctl_inbd_cnt(unsigned int uapi_ctl_inbd_cnt); +int iSetAPICTL_CNT3_api_ctl_inbd_csr_cnt(unsigned int uapi_ctl_inbd_csr_cnt); +int iSetAPICTL_CNT3_api_ctl_inbd_up_cnt(unsigned int uapi_ctl_inbd_up_cnt); +int iSetAPICTL_CNT4_api_ctl_dir_acc_cnt(unsigned int uapi_ctl_dir_acc_cnt); +int iSetAPICTL_CNT4_api_ctl_inline_cnt(unsigned int uapi_ctl_inline_cnt); +int iSetAPICTL_CNT5_api_ctl_up_tx_cnt(unsigned int uapi_ctl_up_tx_cnt); +int iSetAPICTL_CNT5_api_ctl_resp_cnt(unsigned int uapi_ctl_resp_cnt); +int iSetAPICTL_CNT6_api_ctl_noncsr_tag(unsigned int uapi_ctl_noncsr_tag); +int iSetAPICTL_CNT6_api_ctl_csr_tag(unsigned int uapi_ctl_csr_tag); +int iSetAPICTL_RESERVD_apictl_reserved(unsigned int uapictl_reserved); +int iSetAPICTL_OUT_A_PLS_api_ctl_out_a_pls(unsigned int uapi_ctl_out_a_pls); +int iSetAPICTL_OUT_B_PLS_api_ctl_out_b_pls(unsigned int uapi_ctl_out_b_pls); +int iSetAPICTL_NON_CSR_TIMER_TH_api_ctl_noncsr_timer_th(unsigned int uapi_ctl_noncsr_timer_th); +int iSetAPICTL_CSR_TIMER_TH_api_ctl_csr_timer_th(unsigned int uapi_ctl_csr_timer_th); +int iSetAPICTL_DBG_OUT_A_api_ctl_dbg_out_a(unsigned int uapi_ctl_dbg_out_a); +int iSetAPICTL_DBG_OUT_B_api_ctl_dbg_out_b(unsigned int uapi_ctl_dbg_out_b); +int iSetAPICTL_DBG_OUT_C_api_ctl_dbg_out_c(unsigned int uapi_ctl_dbg_out_c); +int iSetAPICTL_DBG_OUT_D_api_ctl_dbg_out_d(unsigned int uapi_ctl_dbg_out_d); +int iSetAPICTL_DBG_OUT_E_api_ctl_dbg_out_e(unsigned int uapi_ctl_dbg_out_e); +int iSetAPICTL_DBG_OUT_F_api_ctl_dbg_out_f(unsigned int uapi_ctl_dbg_out_f); +int iSetAPICTL_DBG_OUT_G_api_ctl_dbg_out_g(unsigned int uapi_ctl_dbg_out_g); +int iSetAPICTL_DBG_OUT_H_api_ctl_dbg_out_h(unsigned int uapi_ctl_dbg_out_h); +int iSetAPICTL_DBG_OUT_I_api_ctl_dbg_out_i(unsigned int uapi_ctl_dbg_out_i); +int iSetAPICTL_DBG_OUT_J_api_ctl_dbg_out_j(unsigned int uapi_ctl_dbg_out_j); +int iSetAPICTL_DBG_OUT_K_api_ctl_dbg_out_k(unsigned int uapi_ctl_dbg_out_k); +int iSetAPICTL_DBG_OUT_L_api_ctl_dbg_out_l(unsigned int uapi_ctl_dbg_out_l); +int iSetAPICTL_DBG_OUT_M_api_ctl_dbg_out_m(unsigned int uapi_ctl_dbg_out_m); +int iSetAPICTL_DBG_OUT_N_api_ctl_dbg_out_n(unsigned int uapi_ctl_dbg_out_n); +int iSetAPICTL_DBG_OUT_O_api_ctl_dbg_out_o(unsigned int uapi_ctl_dbg_out_o); +int iSetAPICTL_DBG_OUT_P_api_ctl_dbg_out_p(unsigned int uapi_ctl_dbg_out_p); +int iSetAPICTL_DBG_OUT_Q_api_ctl_dbg_out_q(unsigned int uapi_ctl_dbg_out_q); +int iSetAPICTL_DBG_OUT_R_api_ctl_dbg_out_r(unsigned int uapi_ctl_dbg_out_r); +int iSetAPICTL_DBG_OUT_S_api_ctl_dbg_out_s(unsigned int uapi_ctl_dbg_out_s); +int iSetAPICTL_DBG_OUT_T_api_ctl_dbg_out_t(unsigned int uapi_ctl_dbg_out_t); +int iSetAPICTL_DBG_OUT_U_api_ctl_dbg_out_u(unsigned int uapi_ctl_dbg_out_u); +int iSetAPICTL_DBG_OUT_V_api_ctl_dbg_out_v(unsigned int uapi_ctl_dbg_out_v); +int iSetAPICTL_DBG_OUT_W_api_ctl_dbg_out_w(unsigned int uapi_ctl_dbg_out_w); +int iSetAPICTL_DBG_OUT_X_api_ctl_dbg_out_x(unsigned int uapi_ctl_dbg_out_x); +int iSetAPICTL_DBG_OUT_Y_api_ctl_dbg_out_y(unsigned int uapi_ctl_dbg_out_y); +int iSetAPICTL_DBG_OUT_Z_api_ctl_dbg_out_z(unsigned int uapi_ctl_dbg_out_z); +int iSetAPICTL_DBG_FIFO_A_api_ctl_dbg_fifo_a(unsigned int uapi_ctl_dbg_fifo_a); +int iSetAPICTL_DBG_FIFO_B_api_ctl_dbg_fifo_b(unsigned int uapi_ctl_dbg_fifo_b); +int iSetAPICTL_DBG_FIFO_C_api_ctl_dbg_fifo_c(unsigned int uapi_ctl_dbg_fifo_c); +int iSetAPICTL_DBG_FIFO_D_api_ctl_dbg_fifo_d(unsigned int uapi_ctl_dbg_fifo_d); +int iSetAPICTL_DBG_FIFO_E_api_ctl_dbg_fifo_e(unsigned int uapi_ctl_dbg_fifo_e); +int iSetAPICTL_DBG_FIFO_F_api_ctl_dbg_fifo_f(unsigned int uapi_ctl_dbg_fifo_f); +int iSetAPICTL_DBG_FIFO_G_api_ctl_dbg_fifo_g(unsigned int uapi_ctl_dbg_fifo_g); +int iSetAPICTL_DBG_FIFO_H_api_ctl_dbg_fifo_h(unsigned int uapi_ctl_dbg_fifo_h); +int iSetAPICTL_DBG_FIFO_I_api_ctl_dbg_fifo_i(unsigned int uapi_ctl_dbg_fifo_i); +int iSetAPICTL_DBG_FIFO_J_api_ctl_dbg_fifo_j(unsigned int uapi_ctl_dbg_fifo_j); +int iSetAPICTL_DBG_FIFO_K_api_ctl_dbg_fifo_k(unsigned int uapi_ctl_dbg_fifo_k); +int iSetAPICTL_DBG_FIFO_L_api_ctl_dbg_fifo_l(unsigned int uapi_ctl_dbg_fifo_l); +int iSetAPICTL_DBG_FIFO_M_api_ctl_dbg_fifo_m(unsigned int uapi_ctl_dbg_fifo_m); +int iSetAPICTL_DBG_FIFO_N_api_ctl_dbg_fifo_n(unsigned int uapi_ctl_dbg_fifo_n); +int iSetAPICTL_DBG_FIFO_O_api_ctl_dbg_fifo_o(unsigned int uapi_ctl_dbg_fifo_o); +int iSetAPICTL_DBG_FIFO_P_api_ctl_dbg_fifo_p(unsigned int uapi_ctl_dbg_fifo_p); +int iSetAPICTL_DBG_FIFO_Q_api_ctl_dbg_fifo_q(unsigned int uapi_ctl_dbg_fifo_q); +int iSetAPICTL_DBG_FIFO_R_api_ctl_dbg_fifo_r(unsigned int uapi_ctl_dbg_fifo_r); +int iSetAPICTL_DBG_FIFO_S_api_ctl_dbg_fifo_s(unsigned int uapi_ctl_dbg_fifo_s); +int iSetINBD_RING_BUF_CRDT_api_inbd_ring_buf_crdt(unsigned int uapi_inbd_ring_buf_crdt); +int iSetINBD_CMD_RD_SO_RO_api_inbd_cmd_rd_so_ro(unsigned int uapi_inbd_cmd_rd_so_ro); +int iSetTILEP_DFX_RO_0_tilep_cur_st(unsigned int utilep_cur_st); +int iSetTILEP_DFX_RO_0_tilep_fifo_cmd_cnt(unsigned int utilep_fifo_cmd_cnt); +int iSetTILEP_DFX_RO_0_tilep_indir_sts(unsigned int utilep_indir_sts); +int iSetTILEP_DFX_RO_0_apictl_tile_rsp_err_lock(unsigned int uapictl_tile_rsp_err_lock); +int iSetTILEP_DFX_RO_0_tilep_e0_err(unsigned int utilep_e0_err); +int iSetTILEP_DFX_RO_0_tilep_err_code(unsigned int utilep_err_code); +int iSetTILEP_DFX_RO_1_tilep_wr_dat_cnt(unsigned int utilep_wr_dat_cnt); +int iSetTILEP_DFX_RO_1_tilep_indir_rd_tx_rsp_cnt(unsigned int utilep_indir_rd_tx_rsp_cnt); +int iSetTILEP_DFX_RO_1_tilep_rd_dat_cnt(unsigned int utilep_rd_dat_cnt); +int iSetTILEP_DFX_CNT_0_tilep_cmd_total_cnt(unsigned int utilep_cmd_total_cnt); +int iSetTILEP_DFX_CNT_1_tilep_cmd_err_cnt(unsigned int utilep_cmd_err_cnt); +int iSetTILEP_DFX_CNT_2_tilep_cmd_ok_cnt(unsigned int utilep_cmd_ok_cnt); +int iSetTILEP_DFX_CNT_3_tilep_csr_cmd_cnt(unsigned int utilep_csr_cmd_cnt); +int iSetTILEP_DFX_CNT_4_tilep_indir_rd_cmd_cnt(unsigned int utilep_indir_rd_cmd_cnt); +int iSetTILEP_DFX_CNT_5_tilep_indir_wr_cmd_cnt(unsigned int utilep_indir_wr_cmd_cnt); +int iSetTILEP_DFX_CNT_6_tilep_tx_api_req_cnt(unsigned int utilep_tx_api_req_cnt); +int iSetTILEP_DFX_CNT_7_tilep_tx_api_np_req_cnt(unsigned int utilep_tx_api_np_req_cnt); +int iSetTILEP_DFX_CNT_8_tilep_rx_api_rsp_cnt(unsigned int utilep_rx_api_rsp_cnt); +int iSetTILEP_DFX_CNT_9_tilep_rx_api_rsp_e0_err_cnt(unsigned int utilep_rx_api_rsp_e0_err_cnt); +int iSetTILEP_DFX_CNT_10_tilep_rx_api_rsp_sts_err_cnt(unsigned int utilep_rx_api_rsp_sts_err_cnt); +int iSetTILEP_DFX_CNT_11_tilep_poll_req_cnt(unsigned int utilep_poll_req_cnt); +int iSetTILEP_DFX_CNT_12_tilep_rtn_rsp_cnt(unsigned int utilep_rtn_rsp_cnt); +int iSetTILEP_DFX_CNT_13_tilep_csr_no_ack_cnt(unsigned int utilep_csr_no_ack_cnt); +int iSetTILEP_DFX_CNT_14_tilep_indir_no_ack_cnt(unsigned int utilep_indir_no_ack_cnt); +int iSetNL2_DFX_RO_0_nl2_acc_cur_st(unsigned int unl2_acc_cur_st); +int iSetNL2_DFX_RO_0_nl2_finish_cur_st(unsigned int unl2_finish_cur_st); +int iSetNL2_DFX_RO_0_nl2_acc_crdt_cnt(unsigned int unl2_acc_crdt_cnt); +int iSetNL2_DFX_RO_0_first_available_ctx_idx(unsigned int ufirst_available_ctx_idx); +int iSetNL2_DFX_RO_0_cur_rsp_ctx_idx(unsigned int ucur_rsp_ctx_idx); +int iSetNL2_DFX_RO_1_nl2_ctx_sm_miss(unsigned int unl2_ctx_sm_miss); +int iSetNL2_DFX_RO_1_nl2_ctx_vld(unsigned int unl2_ctx_vld); +int iSetNL2_DFX_CNT_0_nl2_cmd_rev_total_cnt(unsigned int unl2_cmd_rev_total_cnt); +int iSetNL2_DFX_CNT_1_nl2_cmd_rev_prt0_cnt(unsigned int unl2_cmd_rev_prt0_cnt); +int iSetNL2_DFX_CNT_2_nl2_cmd_rev_prt1_cnt(unsigned int unl2_cmd_rev_prt1_cnt); +int iSetNL2_DFX_CNT_3_nl2_cmd_rev_prt2_cnt(unsigned int unl2_cmd_rev_prt2_cnt); +int iSetNL2_DFX_CNT_4_nl2_cmd_rev_prt3_cnt(unsigned int unl2_cmd_rev_prt3_cnt); +int iSetNL2_DFX_CNT_5_nl2_cmd_rev_prt4_cnt(unsigned int unl2_cmd_rev_prt4_cnt); +int iSetNL2_DFX_CNT_6_nl2_sub_cmd_tx_total_cnt(unsigned int unl2_sub_cmd_tx_total_cnt); +int iSetNL2_DFX_CNT_7_nl2_sub_rsp_rx_total_cnt(unsigned int unl2_sub_rsp_rx_total_cnt); +int iSetNL2_DFX_CNT_8_nl2_sub_rsp_rx_miss_cnt(unsigned int unl2_sub_rsp_rx_miss_cnt); +int iSetNL2_DFX_CNT_9_nl2_sub_rsp_rx_abort_cnt(unsigned int unl2_sub_rsp_rx_abort_cnt); +int iSetNL2_DFX_CNT_10_nl2_rtn_icpl_done_success_cnt(unsigned int unl2_rtn_icpl_done_success_cnt); +int iSetNL2_DFX_CNT_11_nl2_rtn_icpl_done_fail_cnt(unsigned int unl2_rtn_icpl_done_fail_cnt); +int iSetNL2_DFX_CNT_12_nl2_rtn_icpl_set_vld_cnt(unsigned int unl2_rtn_icpl_set_vld_cnt); +int iSetNL2_DFX_CNT_13_nl2_rtn_icpl_set_rej_cnt(unsigned int unl2_rtn_icpl_set_rej_cnt); +int iSetAPICTL_OUT_A_FATAL_MSK_apictl_out_a_fatal_msk(unsigned int uapictl_out_a_fatal_msk); +int iSetAPICTL_OUT_B_FATAL_MSK_apictl_out_b_fatal_msk(unsigned int uapictl_out_b_fatal_msk); +int iSetAPICTL_OUT_A_NONFATAL_MSK_apictl_out_a_nonfatal_msk(unsigned int uapictl_out_a_nonfatal_msk); +int iSetAPICTL_OUT_B_NONFATAL_MSK_apictl_out_b_nonfatal_msk(unsigned int uapictl_out_b_nonfatal_msk); +int iSetGLB_API_CHN_RIGHT_CTL0_glb_api_chn_root_right(unsigned int uglb_api_chn_root_right); +int iSetGLB_API_CHN_RIGHT_CTL1_glb_api_chn_non_bypass_right(unsigned int uglb_api_chn_non_bypass_right); +int iSetGLB_API_CHN_RIGHT_CTL2_glb_api_chn_other_right(unsigned int uglb_api_chn_other_right); +int iSetAPICTL_TAG_CMP_TH_apictl_csr_tag_cmp_th(unsigned int uapictl_csr_tag_cmp_th); +int iSetAPICTL_TAG_CMP_TH_apictl_noncsr_tag_cmp_th(unsigned int uapictl_noncsr_tag_cmp_th); +int iSetAPIITF_DFX_CNT0_api_ctl_virtio_cnt(unsigned int uapi_ctl_virtio_cnt); +int iSetAPIITF_DFX_CNT0_api_ctl_tile_cnt(unsigned int uapi_ctl_tile_cnt); +int iSetAPIITF_DFX_CNT1_api_ctl_csr_wr_dest_illg_cnt(unsigned int uapi_ctl_csr_wr_dest_illg_cnt); +int iSetAPIITF_DFX_CNT1_api_ctl_csr_rd_dest_illg_cnt(unsigned int uapi_ctl_csr_rd_dest_illg_cnt); +int iSetAPIITF_DFX_CNT2_api_ctl_noncsr_wr_dest_illg_cnt(unsigned int uapi_ctl_noncsr_wr_dest_illg_cnt); +int iSetAPIITF_DFX_CNT2_api_ctl_noncsr_rd_dest_illg_cnt(unsigned int uapi_ctl_noncsr_rd_dest_illg_cnt); +int iSetAPIITF_RING_DEST_ILLG_SRC_apiitf_ring_dest_illg_src(unsigned int uapiitf_ring_dest_illg_src); + +/* Define the union csr_dma_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_indrect_addr : 16; /* [15:0] */ + u32 rsv_0 : 8; /* [23:16] */ + u32 dma_indrect_tab : 4; /* [27:24] */ + u32 dma_indrect_status : 2; /* [29:28] */ + u32 dma_indrect_mode : 1; /* [30] */ + u32 dma_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_indrect_ctrl_u; + +/* Define the union csr_dma_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_indrect_timeout_u; + +/* Define the union csr_dma_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_indrect_data_u; + +/* Define the union csr_cpi_dma_ram_tmode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpi_tp_ram_tmode : 8; /* [7:0] */ + u32 glb_cpi_sp_ram_tmode : 7; /* [14:8] */ + u32 rsv_1 : 1; /* [15] */ + u32 glb_cpi_mem_power_mode : 6; /* [21:16] */ + u32 rsv_2 : 9; /* [30:22] */ + u32 glb_cpi_ecc_bypass : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_dma_ram_tmode_u; + +/* Define the union csr_msi_bar_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_pba_offset : 15; /* [14:0] */ + u32 rsv_3 : 1; /* [15] */ + u32 glb_cpl_data_rsv : 1; /* [16] */ + u32 rsv_4 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msi_bar_offset_u; + +/* Define the union csr_pf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_func_idx_l : 5; /* [4:0] */ + u32 rsv_5 : 11; /* [15:5] */ + u32 pf_func_idx_h : 5; /* [20:16] */ + u32 rsv_6 : 10; /* [30:21] */ + u32 pf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pf_range_port_u; + +/* Define the union csr_vf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_func_idx_l : 12; /* [11:0] */ + u32 rsv_7 : 4; /* [15:12] */ + u32 vf_func_idx_h : 12; /* [27:16] */ + u32 rsv_8 : 3; /* [30:28] */ + u32 vf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_range_port_u; + +/* Define the union csr_lvf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lvf_func_idx_l : 12; /* [11:0] */ + u32 rsv_9 : 4; /* [15:12] */ + u32 lvf_func_idx_h : 12; /* [27:16] */ + u32 rsv_10 : 3; /* [30:28] */ + u32 lvf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lvf_range_port_u; + +/* Define the union csr_ceq_num_acc_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_num_acc_weight : 12; /* [11:0] */ + u32 rsv_11 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_num_acc_weight_u; + +/* Define the union csr_copy_ep_2_cos_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 copy_ep2cos_4_spu_en : 1; /* [0] */ + u32 modify_src_4_spu_en : 1; /* [1] */ + u32 rsv_12 : 2; /* [3:2] */ + u32 modify_src_idx : 3; /* [6:4] */ + u32 rsv_13 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_copy_ep_2_cos_en_u; + +/* Define the union csr_dma_attr_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dma_attr_per_func : 3; /* [2:0] */ + u32 rsv_14 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_attr_num_u; + +/* Define the union csr_dma_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flxq_mode_en : 1; /* [0] */ + u32 pcie_cpi_tag_modify_chk_en : 1; /* [1] */ + u32 rdr_buf_cfg_chk_en : 1; /* [2] */ + u32 cfg_bme_clr_no_flush : 1; /* [3] */ + u32 cfg_osch_drp_no_flush : 1; /* [4] */ + u32 cfg_bme_int_mode : 1; /* [5] */ + u32 rsv_15 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_0_u; + +/* Define the union csr_dma_ram_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_csr_ceq_ram_ini : 1; /* [0] */ + u32 ceq_num_init_start : 1; /* [1] */ + u32 dma_attr_ram_ini_req : 1; /* [2] */ + u32 func_idx_remap_ram_ini_req : 1; /* [3] */ + u32 rsv_16 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ram_init_u; + +/* Define the union csr_dma_ram_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_mtt_tab_ram_ini_sts : 1; /* [0] */ + u32 ceq_attr_csr_ram_ini_sts : 1; /* [1] */ + u32 ceq_num_init_done : 1; /* [2] */ + u32 dma_attr_ram_ini_sts : 1; /* [3] */ + u32 func_idx_remap_ram_ini_sts : 1; /* [4] */ + u32 rsv_17 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ram_status_u; + +/* Define the union csr_pcie_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_time_out_treshold : 10; /* [9:0] */ + u32 rsv_18 : 6; /* [15:10] */ + u32 oubd_tag_time_out_unit_16us : 8; /* [23:16] */ + u32 rsv_19 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_timeout_u; + +/* Define the union csr_pcie_tag_force_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_force_clr_func : 12; /* [11:0] */ + u32 rsv_20 : 4; /* [15:12] */ + u32 mpu_force_clr : 1; /* [16] */ + u32 rsv_21 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_tag_force_u; + +/* Define the union csr_pcie_tag_force_itf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mpu_port_force_clr_idx : 3; /* [2:0] */ + u32 rsv_22 : 13; /* [15:3] */ + u32 mpu_port_force_clr : 1; /* [16] */ + u32 rsv_23 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_tag_force_itf_u; + +/* Define the union csr_timeout_dly_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 timeout_itf_dly_th : 16; /* [15:0] */ + u32 timeout_itf_unit : 8; /* [23:16] */ + u32 rsv_24 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_timeout_dly_cfg_u; + +/* Define the union csr_pcie_cfg_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mrrs_used_mode : 1; /* [0] */ + u32 rsv_25 : 3; /* [3:1] */ + u32 timeout_set_used_mode : 1; /* [4] */ + u32 rsv_26 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cfg_mod_u; + +/* Define the union csr_pcie_cfg_loc_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_local_mrrs : 12; /* [11:0] */ + u32 cfg_local_timeout_val : 16; /* [27:12] */ + u32 cfg_local_timeout_dis : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cfg_loc_set_u; + +/* Define the union csr_spu_cfg_loc_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_spu_local_mrrs : 3; /* [2:0] */ + u32 rsv_27 : 9; /* [11:3] */ + u32 cfg_spu_local_timeout_val : 4; /* [15:12] */ + u32 rsv_28 : 12; /* [27:16] */ + u32 cfg_spu_local_timeout_dis : 1; /* [28] */ + u32 rsv_29 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_spu_cfg_loc_set_u; + +/* Define the union csr_dma_top_eco0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfqu_uncrt_err : 1; /* [0] */ + u32 pqm_uncrt_err : 1; /* [1] */ + u32 mqm_uncrt_err : 1; /* [2] */ + u32 stlqu_uncrt_err : 1; /* [3] */ + u32 smf0_uncrt_err : 1; /* [4] */ + u32 smf1_uncrt_err : 1; /* [5] */ + u32 smf2_uncrt_err : 1; /* [6] */ + u32 smf3_uncrt_err : 1; /* [7] */ + u32 sml0_uncrt_err : 1; /* [8] */ + u32 sml1_uncrt_err : 1; /* [9] */ + u32 sml2_uncrt_err : 1; /* [10] */ + u32 sml3_uncrt_err : 1; /* [11] */ + u32 stftile0_uncrt_err : 1; /* [12] */ + u32 stftile1_uncrt_err : 1; /* [13] */ + u32 stftile2_uncrt_err : 1; /* [14] */ + u32 stftile3_uncrt_err : 1; /* [15] */ + u32 stltile0_uncrt_err : 1; /* [16] */ + u32 stltile1_uncrt_err : 1; /* [17] */ + u32 stltile2_uncrt_err : 1; /* [18] */ + u32 stltile3_uncrt_err : 1; /* [19] */ + u32 mpu_uncrt_err : 1; /* [20] */ + u32 cpi_uncrt_err : 1; /* [21] */ + u32 lcam_uncrt_err : 1; /* [22] */ + u32 ipsutx_uncrt_err : 1; /* [23] */ + u32 perx_uncrt_err : 1; /* [24] */ + u32 ipsurx_uncrt_err : 1; /* [25] */ + u32 petx_uncrt_err : 1; /* [26] */ + u32 cpb_uncrt_err : 1; /* [27] */ + u32 ckd_err_int0 : 1; /* [28] */ + u32 ckd_err_int1 : 1; /* [29] */ + u32 pcie_uncrt_err : 1; /* [30] */ + u32 cryptorx_uncrt_err : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_top_eco0_u; + +/* Define the union csr_dma_top_eco1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptotx_uncrt_err : 1; /* [0] */ + u32 ts_uncrt_err : 1; /* [1] */ + u32 mag_uncrt_err : 1; /* [2] */ + u32 fc_uncrt_err : 1; /* [3] */ + u32 hva_uncrt_err : 1; /* [4] */ + u32 rsvd : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_top_eco1_u; + +/* Define the union csr_dma_top_eco2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_top_eco2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_top_eco2_u; + +/* Define the union csr_dma_top_eco3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_top_eco3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_top_eco3_u; + +/* Define the union csr_dma_top_eco4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_top_eco4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_top_eco4_u; + +/* Define the union csr_cpl_timeout_value0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_0set : 10; /* [9:0] */ + u32 rsv_30 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_0set : 8; /* [23:16] */ + u32 rsv_31 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value0_u; + +/* Define the union csr_cpl_timeout_value1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_1set : 10; /* [9:0] */ + u32 rsv_32 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_1set : 8; /* [23:16] */ + u32 rsv_33 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value1_u; + +/* Define the union csr_cpl_timeout_value2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_2set : 10; /* [9:0] */ + u32 rsv_34 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_2set : 8; /* [23:16] */ + u32 rsv_35 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value2_u; + +/* Define the union csr_cpl_timeout_value5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_5set : 10; /* [9:0] */ + u32 rsv_36 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_5set : 8; /* [23:16] */ + u32 rsv_37 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value5_u; + +/* Define the union csr_cpl_timeout_value6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_6set : 10; /* [9:0] */ + u32 rsv_38 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_6set : 8; /* [23:16] */ + u32 rsv_39 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value6_u; + +/* Define the union csr_cpl_timeout_value9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_9set : 10; /* [9:0] */ + u32 rsv_40 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_9set : 8; /* [23:16] */ + u32 rsv_41 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value9_u; + +/* Define the union csr_cpl_timeout_valuea_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_aset : 10; /* [9:0] */ + u32 rsv_42 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_aset : 8; /* [23:16] */ + u32 rsv_43 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_valuea_u; + +/* Define the union csr_cpl_timeout_value_dis_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oubd_tag_treshold_dis_set : 10; /* [9:0] */ + u32 rsv_44 : 6; /* [15:10] */ + u32 oubd_tag_unit_16us_dis_set : 8; /* [23:16] */ + u32 rsv_45 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpl_timeout_value_dis_u; + +/* Define the union csr_pdi_tag_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_pcie_ur_cpl_req_cnt : 16; /* [15:0] */ + u32 dbg_pending_tag_req_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt0_u; + +/* Define the union csr_pdi_tag_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_timeout_req_cnt : 16; /* [15:0] */ + u32 dbg_osch_quick_back_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt1_u; + +/* Define the union csr_pdi_tag_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_aer_uc_cnt : 16; /* [15:0] */ + u32 dbg_mpu_force_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt2_u; + +/* Define the union csr_pdi_tag_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_pcie_ictl_sop_cnt : 16; /* [15:0] */ + u32 dbg_10bit_err_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt3_u; + +/* Define the union csr_pdi_tag_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_icpl_ep_cnt : 16; /* [15:0] */ + u32 dbg_pcie_ictl_eop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt4_u; + +/* Define the union csr_pdi_tag_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_icpl_unsucc_cnt : 16; /* [15:0] */ + u32 dbg_icpl_null_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt5_u; + +/* Define the union csr_pdi_tag_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_46 : 16; /* [15:0] */ + u32 dbg_osch_spu_quick_back_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt6_u; + +/* Define the union csr_pdi_tag_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_timeout3_req_cnt : 16; /* [15:0] */ + u32 dbg_timeout4_req_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt7_u; + +/* Define the union csr_pdi_tag_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_timeout1_req_cnt : 16; /* [15:0] */ + u32 dbg_timeout2_req_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt8_u; + +/* Define the union csr_pdi_tag_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_47 : 16; /* [15:0] */ + u32 dbg_mpu_port_force_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt9_u; + +/* Define the union csr_pdi_tag_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_cpld_spu_pkt_cnt : 16; /* [15:0] */ + u32 cpi_cpld_x86_pkt_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pdi_tag_cnt10_u; + +/* Define the union csr_ceq_blk_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_ceq_tx_int_req_cnt : 16; /* [15:0] */ + u32 dbg_ceq_ci_sw_wr_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_blk_cnt_u; + +/* Define the union csr_ceq_csr_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbg_ceq_state : 12; /* [11:0] */ + u32 rsv_48 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_csr_st_u; + +/* Define the union csr_flr_rcv_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_rcv_pcie1_flr_cnt : 16; /* [15:0] */ + u32 cpi_rcv_pcie0_flr_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flr_rcv_cnt0_u; + +/* Define the union csr_flr_rcv_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_rcv_pcie3_flr_cnt : 16; /* [15:0] */ + u32 cpi_rcv_pcie2_flr_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flr_rcv_cnt1_u; + +/* Define the union csr_flr_rcv_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_49 : 16; /* [15:0] */ + u32 cpi_rcv_pcie4_flr_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_flr_rcv_cnt2_u; + +/* Define the union csr_dma_ctrl_bus0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ctrl_bus4 : 6; /* [5:0] */ + u32 rsv_50 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_bus0_u; + +/* Define the union csr_dma_ctrl_bus1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ctrl_bus3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_bus1_u; + +/* Define the union csr_dma_ctrl_bus2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ctrl_bus2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_bus2_u; + +/* Define the union csr_dma_ctrl_bus3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ctrl_bus1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_bus3_u; + +/* Define the union csr_dma_ctrl_bus4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_ctrl_bus0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_ctrl_bus4_u; + +/* Define the union csr_dma_pcie_inbd_itf_wind_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_51 : 4; /* [3:0] */ + u32 itf_wind_16t : 16; /* [19:4] */ + u32 rsv_52 : 10; /* [29:20] */ + u32 itf_wind_mode : 1; /* [30] */ + u32 itf_wind_start : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_pcie_inbd_itf_wind_ctl_u; + +/* Define the union csr_dma_pcie_inbd_itf_wind_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 itf_wind_detect_mode_cnt : 20; /* [19:0] */ + u32 rsv_53 : 11; /* [30:20] */ + u32 itf_wind_detect_done : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_pcie_inbd_itf_wind_cnt_u; + +/* Define the union csr_dma_pcie_inbd_itf_wind_tlp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 itf_wind_detect_tlp_cnt : 20; /* [19:0] */ + u32 rsv_54 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_pcie_inbd_itf_wind_tlp_cnt_u; + +/* Define the union csr_cpi_rcv_bme_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_rcv_bme_clear_func_idx : 12; /* [11:0] */ + u32 cpi_rcv_bme_clear_lat_en : 1; /* [12] */ + u32 rsv_55 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_rcv_bme_sts_u; + +/* Define the union csr_cpi_tag_timeout_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_tag_timeout_sel : 7; /* [6:0] */ + u32 rsv_56 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tag_timeout_sel_u; + +/* Define the union csr_cpi_tag_timeout_clear_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_tag_timeout_clr_pulse : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tag_timeout_clear_u; + +/* Define the union csr_cpi_tag_timeout_st_out_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_tag_timeout_func_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tag_timeout_st_out_u; + +/* Define the union csr_cpi_tag_timeout_group_st_out_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_tag_timeout_func_group_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_tag_timeout_group_st_out_u; + +/* Define the union csr_cpi_pdi_a_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_a_fatal_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_a_fatal_msk_u; + +/* Define the union csr_cpi_pdi_a_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_a_nonfatal_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_a_nonfatal_msk_u; + +/* Define the union csr_cpi_pdi_a_int_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_a_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_a_int_pls_u; + +/* Define the union csr_cpi_pdi_b_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_b_fatal_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_b_fatal_msk_u; + +/* Define the union csr_cpi_pdi_b_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_b_nonfatal_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_b_nonfatal_msk_u; + +/* Define the union csr_cpi_pdi_b_int_pls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_dfx_b_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_pdi_b_int_pls_u; + +/* Define the union csr_cpi_virtio_cap_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_en : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_en_u; + +/* Define the union csr_cpi_virtio_cap_00value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_00value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_00value_pf_u; + +/* Define the union csr_cpi_virtio_cap_01value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_01value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_01value_pf_u; + +/* Define the union csr_cpi_virtio_cap_02value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_02value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_02value_pf_u; + +/* Define the union csr_cpi_virtio_cap_03value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_03value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_03value_pf_u; + +/* Define the union csr_cpi_virtio_cap_04value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_04value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_04value_pf_u; + +/* Define the union csr_cpi_virtio_cap_05value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_05value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_05value_pf_u; + +/* Define the union csr_cpi_virtio_cap_06value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_06value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_06value_pf_u; + +/* Define the union csr_cpi_virtio_cap_07value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_07value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_07value_pf_u; + +/* Define the union csr_cpi_virtio_cap_08value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_08value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_08value_pf_u; + +/* Define the union csr_cpi_virtio_cap_09value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_09value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_09value_pf_u; + +/* Define the union csr_cpi_virtio_cap_10value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_10value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_10value_pf_u; + +/* Define the union csr_cpi_virtio_cap_11value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_11value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_11value_pf_u; + +/* Define the union csr_cpi_virtio_cap_12value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_12value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_12value_pf_u; + +/* Define the union csr_cpi_virtio_cap_13value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_13value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_13value_pf_u; + +/* Define the union csr_cpi_virtio_cap_14value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_14value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_14value_pf_u; + +/* Define the union csr_cpi_virtio_cap_15value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_15value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_15value_pf_u; + +/* Define the union csr_cpi_virtio_cap_16value_pf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_16value_pf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_16value_pf_u; + +/* Define the union csr_cpi_virtio_cap_00value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_00value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_00value_vf_u; + +/* Define the union csr_cpi_virtio_cap_01value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_01value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_01value_vf_u; + +/* Define the union csr_cpi_virtio_cap_02value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_02value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_02value_vf_u; + +/* Define the union csr_cpi_virtio_cap_03value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_03value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_03value_vf_u; + +/* Define the union csr_cpi_virtio_cap_04value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_04value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_04value_vf_u; + +/* Define the union csr_cpi_virtio_cap_05value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_05value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_05value_vf_u; + +/* Define the union csr_cpi_virtio_cap_06value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_06value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_06value_vf_u; + +/* Define the union csr_cpi_virtio_cap_07value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_07value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_07value_vf_u; + +/* Define the union csr_cpi_virtio_cap_08value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_08value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_08value_vf_u; + +/* Define the union csr_cpi_virtio_cap_09value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_09value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_09value_vf_u; + +/* Define the union csr_cpi_virtio_cap_10value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_10value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_10value_vf_u; + +/* Define the union csr_cpi_virtio_cap_11value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_11value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_11value_vf_u; + +/* Define the union csr_cpi_virtio_cap_12value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_12value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_12value_vf_u; + +/* Define the union csr_cpi_virtio_cap_13value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_13value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_13value_vf_u; + +/* Define the union csr_cpi_virtio_cap_14value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_14value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_14value_vf_u; + +/* Define the union csr_cpi_virtio_cap_15value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_15value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_15value_vf_u; + +/* Define the union csr_cpi_virtio_cap_16value_vf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 virtio_cap_16value_vf : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_virtio_cap_16value_vf_u; + +/* Define the union csr_dfx_dmatop_ram_ecc_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmatop_ecc_cerr : 11; /* [10:0] */ + u32 rsv_57 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dmatop_ram_ecc_cerr_u; + +/* Define the union csr_dfx_dmatop_ram_ecc_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmatop_ecc_ucerr : 11; /* [10:0] */ + u32 rsv_58 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dmatop_ram_ecc_ucerr_u; + +/* Define the union csr_dfx_dmatop_ram_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmatop_ecc_err_addr : 24; /* [23:0] */ + u32 rsv_59 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_dmatop_ram_err_addr_u; + +/* Define the union csr_dmatop_ecc_inj_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmatop_ecc_inj_req : 22; /* [21:0] */ + u32 rsv_60 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_ecc_inj_req_u; + +/* Define the union csr_dmatop_dbg_fifo_st_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_a_u; + +/* Define the union csr_dmatop_dbg_fifo_st_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_b_u; + +/* Define the union csr_dmatop_dbg_fifo_st_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_c_u; + +/* Define the union csr_dmatop_dbg_fifo_st_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_d_u; + +/* Define the union csr_dmatop_dbg_fifo_st_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_e_u; + +/* Define the union csr_dmatop_dbg_fifo_st_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_f_u; + +/* Define the union csr_dmatop_dbg_fifo_st_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_g_u; + +/* Define the union csr_dmatop_dbg_fifo_st_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_h_u; + +/* Define the union csr_dmatop_dbg_fifo_st_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_i_u; + +/* Define the union csr_dmatop_dbg_fifo_st_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_j_u; + +/* Define the union csr_dmatop_dbg_fifo_st_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_k_u; + +/* Define the union csr_dmatop_dbg_fifo_st_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_l_u; + +/* Define the union csr_dmatop_dbg_fifo_st_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_m_u; + +/* Define the union csr_dmatop_dbg_fifo_st_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_n_u; + +/* Define the union csr_dmatop_dbg_fifo_st_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_o_u; + +/* Define the union csr_dmatop_dbg_fifo_st_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_p_u; + +/* Define the union csr_dmatop_dbg_fifo_st_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_q_u; + +/* Define the union csr_dmatop_dbg_fifo_st_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_r_u; + +/* Define the union csr_dmatop_dbg_fifo_st_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_s_u; + +/* Define the union csr_dmatop_dbg_fifo_st_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_t : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_t_u; + +/* Define the union csr_dmatop_dbg_fifo_st_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_fifo_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_fifo_st_u_u; + +/* Define the union csr_dmatop_dbg_out_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_out_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_out_a_u; + +/* Define the union csr_dmatop_dbg_out_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_out_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_out_b_u; + +/* Define the union csr_dmatop_dbg_out_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pdi_out_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dmatop_dbg_out_c_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_dma_indrect_ctrl_u dma_indrect_ctrl; /* 0 */ + volatile csr_dma_indrect_timeout_u dma_indrect_timeout; /* 4 */ + volatile csr_dma_indrect_data_u dma_indrect_data[8]; /* 8 */ + volatile csr_cpi_dma_ram_tmode_u cpi_dma_ram_tmode; /* 40 */ + volatile csr_msi_bar_offset_u msi_bar_offset; /* 44 */ + volatile csr_pf_range_port_u pf_range_port[5]; /* 50 */ + volatile csr_vf_range_port_u vf_range_port[5]; /* 54 */ + volatile csr_lvf_range_port_u lvf_range_port[5]; /* 58 */ + volatile csr_ceq_num_acc_weight_u ceq_num_acc_weight; /* B0 */ + volatile csr_copy_ep_2_cos_en_u copy_ep_2_cos_en; /* B4 */ + volatile csr_dma_attr_num_u dma_attr_num; /* B8 */ + volatile csr_dma_ctrl_0_u dma_ctrl_0; /* BC */ + volatile csr_dma_ram_init_u dma_ram_init; /* C0 */ + volatile csr_dma_ram_status_u dma_ram_status; /* C4 */ + volatile csr_pcie_timeout_u pcie_timeout; /* D0 */ + volatile csr_pcie_tag_force_u pcie_tag_force; /* D4 */ + volatile csr_pcie_tag_force_itf_u pcie_tag_force_itf; /* D8 */ + volatile csr_timeout_dly_cfg_u timeout_dly_cfg; /* DC */ + volatile csr_pcie_cfg_mod_u pcie_cfg_mod; /* E0 */ + volatile csr_pcie_cfg_loc_set_u pcie_cfg_loc_set; /* E4 */ + volatile csr_spu_cfg_loc_set_u spu_cfg_loc_set; /* E8 */ + volatile csr_dma_top_eco0_u dma_top_eco0; /* EC */ + volatile csr_dma_top_eco1_u dma_top_eco1; /* F0 */ + volatile csr_dma_top_eco2_u dma_top_eco2; /* F4 */ + volatile csr_dma_top_eco3_u dma_top_eco3; /* F8 */ + volatile csr_dma_top_eco4_u dma_top_eco4; /* FC */ + volatile csr_cpl_timeout_value0_u cpl_timeout_value0[5]; /* 100 */ + volatile csr_cpl_timeout_value1_u cpl_timeout_value1[5]; /* 104 */ + volatile csr_cpl_timeout_value2_u cpl_timeout_value2[5]; /* 108 */ + volatile csr_cpl_timeout_value5_u cpl_timeout_value5[5]; /* 10C */ + volatile csr_cpl_timeout_value6_u cpl_timeout_value6[5]; /* 110 */ + volatile csr_cpl_timeout_value9_u cpl_timeout_value9[5]; /* 114 */ + volatile csr_cpl_timeout_valuea_u cpl_timeout_valuea[5]; /* 118 */ + volatile csr_cpl_timeout_value_dis_u cpl_timeout_value_dis[5]; /* 11C */ + volatile csr_pdi_tag_cnt0_u pdi_tag_cnt0; /* 240 */ + volatile csr_pdi_tag_cnt1_u pdi_tag_cnt1; /* 244 */ + volatile csr_pdi_tag_cnt2_u pdi_tag_cnt2; /* 248 */ + volatile csr_pdi_tag_cnt3_u pdi_tag_cnt3; /* 24C */ + volatile csr_pdi_tag_cnt4_u pdi_tag_cnt4; /* 250 */ + volatile csr_pdi_tag_cnt5_u pdi_tag_cnt5; /* 254 */ + volatile csr_pdi_tag_cnt6_u pdi_tag_cnt6; /* 258 */ + volatile csr_pdi_tag_cnt7_u pdi_tag_cnt7; /* 25C */ + volatile csr_pdi_tag_cnt8_u pdi_tag_cnt8; /* 260 */ + volatile csr_pdi_tag_cnt9_u pdi_tag_cnt9; /* 264 */ + volatile csr_pdi_tag_cnt10_u pdi_tag_cnt10; /* 268 */ + volatile csr_ceq_blk_cnt_u ceq_blk_cnt; /* 2A0 */ + volatile csr_ceq_csr_st_u ceq_csr_st; /* 2A4 */ + volatile csr_flr_rcv_cnt0_u flr_rcv_cnt0; /* 2B0 */ + volatile csr_flr_rcv_cnt1_u flr_rcv_cnt1; /* 2B4 */ + volatile csr_flr_rcv_cnt2_u flr_rcv_cnt2; /* 2B8 */ + volatile csr_dma_ctrl_bus0_u dma_ctrl_bus0; /* 2E0 */ + volatile csr_dma_ctrl_bus1_u dma_ctrl_bus1; /* 2E4 */ + volatile csr_dma_ctrl_bus2_u dma_ctrl_bus2; /* 2E8 */ + volatile csr_dma_ctrl_bus3_u dma_ctrl_bus3; /* 2EC */ + volatile csr_dma_ctrl_bus4_u dma_ctrl_bus4; /* 2F0 */ + volatile csr_dma_pcie_inbd_itf_wind_ctl_u dma_pcie_inbd_itf_wind_ctl; /* 300 */ + volatile csr_dma_pcie_inbd_itf_wind_cnt_u dma_pcie_inbd_itf_wind_cnt; /* 304 */ + volatile csr_dma_pcie_inbd_itf_wind_tlp_cnt_u dma_pcie_inbd_itf_wind_tlp_cnt; /* 308 */ + volatile csr_cpi_rcv_bme_sts_u cpi_rcv_bme_sts[16]; /* 340 */ + volatile csr_cpi_tag_timeout_sel_u cpi_tag_timeout_sel; /* 380 */ + volatile csr_cpi_tag_timeout_clear_u cpi_tag_timeout_clear; /* 384 */ + volatile csr_cpi_tag_timeout_st_out_u cpi_tag_timeout_st_out; /* 388 */ + volatile csr_cpi_tag_timeout_group_st_out_u cpi_tag_timeout_group_st_out; /* 38C */ + volatile csr_cpi_pdi_a_fatal_msk_u cpi_pdi_a_fatal_msk; /* 3E0 */ + volatile csr_cpi_pdi_a_nonfatal_msk_u cpi_pdi_a_nonfatal_msk; /* 3E4 */ + volatile csr_cpi_pdi_a_int_pls_u cpi_pdi_a_int_pls; /* 3E8 */ + volatile csr_cpi_pdi_b_fatal_msk_u cpi_pdi_b_fatal_msk; /* 3F0 */ + volatile csr_cpi_pdi_b_nonfatal_msk_u cpi_pdi_b_nonfatal_msk; /* 3F4 */ + volatile csr_cpi_pdi_b_int_pls_u cpi_pdi_b_int_pls; /* 3F8 */ + volatile csr_cpi_virtio_cap_en_u cpi_virtio_cap_en[2]; /* 400 */ + volatile csr_cpi_virtio_cap_00value_pf_u cpi_virtio_cap_00value_pf; /* 600 */ + volatile csr_cpi_virtio_cap_01value_pf_u cpi_virtio_cap_01value_pf; /* 604 */ + volatile csr_cpi_virtio_cap_02value_pf_u cpi_virtio_cap_02value_pf; /* 608 */ + volatile csr_cpi_virtio_cap_03value_pf_u cpi_virtio_cap_03value_pf; /* 60C */ + volatile csr_cpi_virtio_cap_04value_pf_u cpi_virtio_cap_04value_pf; /* 610 */ + volatile csr_cpi_virtio_cap_05value_pf_u cpi_virtio_cap_05value_pf; /* 614 */ + volatile csr_cpi_virtio_cap_06value_pf_u cpi_virtio_cap_06value_pf; /* 618 */ + volatile csr_cpi_virtio_cap_07value_pf_u cpi_virtio_cap_07value_pf; /* 61C */ + volatile csr_cpi_virtio_cap_08value_pf_u cpi_virtio_cap_08value_pf; /* 620 */ + volatile csr_cpi_virtio_cap_09value_pf_u cpi_virtio_cap_09value_pf; /* 630 */ + volatile csr_cpi_virtio_cap_10value_pf_u cpi_virtio_cap_10value_pf; /* 634 */ + volatile csr_cpi_virtio_cap_11value_pf_u cpi_virtio_cap_11value_pf; /* 638 */ + volatile csr_cpi_virtio_cap_12value_pf_u cpi_virtio_cap_12value_pf; /* 63C */ + volatile csr_cpi_virtio_cap_13value_pf_u cpi_virtio_cap_13value_pf; /* 640 */ + volatile csr_cpi_virtio_cap_14value_pf_u cpi_virtio_cap_14value_pf; /* 644 */ + volatile csr_cpi_virtio_cap_15value_pf_u cpi_virtio_cap_15value_pf; /* 648 */ + volatile csr_cpi_virtio_cap_16value_pf_u cpi_virtio_cap_16value_pf; /* 64C */ + volatile csr_cpi_virtio_cap_00value_vf_u cpi_virtio_cap_00value_vf; /* 680 */ + volatile csr_cpi_virtio_cap_01value_vf_u cpi_virtio_cap_01value_vf; /* 684 */ + volatile csr_cpi_virtio_cap_02value_vf_u cpi_virtio_cap_02value_vf; /* 688 */ + volatile csr_cpi_virtio_cap_03value_vf_u cpi_virtio_cap_03value_vf; /* 68C */ + volatile csr_cpi_virtio_cap_04value_vf_u cpi_virtio_cap_04value_vf; /* 690 */ + volatile csr_cpi_virtio_cap_05value_vf_u cpi_virtio_cap_05value_vf; /* 694 */ + volatile csr_cpi_virtio_cap_06value_vf_u cpi_virtio_cap_06value_vf; /* 698 */ + volatile csr_cpi_virtio_cap_07value_vf_u cpi_virtio_cap_07value_vf; /* 69C */ + volatile csr_cpi_virtio_cap_08value_vf_u cpi_virtio_cap_08value_vf; /* 6A0 */ + volatile csr_cpi_virtio_cap_09value_vf_u cpi_virtio_cap_09value_vf; /* 6B0 */ + volatile csr_cpi_virtio_cap_10value_vf_u cpi_virtio_cap_10value_vf; /* 6B4 */ + volatile csr_cpi_virtio_cap_11value_vf_u cpi_virtio_cap_11value_vf; /* 6B8 */ + volatile csr_cpi_virtio_cap_12value_vf_u cpi_virtio_cap_12value_vf; /* 6BC */ + volatile csr_cpi_virtio_cap_13value_vf_u cpi_virtio_cap_13value_vf; /* 6C0 */ + volatile csr_cpi_virtio_cap_14value_vf_u cpi_virtio_cap_14value_vf; /* 6C4 */ + volatile csr_cpi_virtio_cap_15value_vf_u cpi_virtio_cap_15value_vf; /* 6C8 */ + volatile csr_cpi_virtio_cap_16value_vf_u cpi_virtio_cap_16value_vf; /* 6CC */ + volatile csr_dfx_dmatop_ram_ecc_cerr_u dfx_dmatop_ram_ecc_cerr; /* 700 */ + volatile csr_dfx_dmatop_ram_ecc_ucerr_u dfx_dmatop_ram_ecc_ucerr; /* 704 */ + volatile csr_dfx_dmatop_ram_err_addr_u dfx_dmatop_ram_err_addr; /* 708 */ + volatile csr_dmatop_ecc_inj_req_u dmatop_ecc_inj_req; /* 710 */ + volatile csr_dmatop_dbg_fifo_st_a_u dmatop_dbg_fifo_st_a; /* 720 */ + volatile csr_dmatop_dbg_fifo_st_b_u dmatop_dbg_fifo_st_b; /* 724 */ + volatile csr_dmatop_dbg_fifo_st_c_u dmatop_dbg_fifo_st_c; /* 728 */ + volatile csr_dmatop_dbg_fifo_st_d_u dmatop_dbg_fifo_st_d; /* 72C */ + volatile csr_dmatop_dbg_fifo_st_e_u dmatop_dbg_fifo_st_e; /* 730 */ + volatile csr_dmatop_dbg_fifo_st_f_u dmatop_dbg_fifo_st_f; /* 734 */ + volatile csr_dmatop_dbg_fifo_st_g_u dmatop_dbg_fifo_st_g; /* 738 */ + volatile csr_dmatop_dbg_fifo_st_h_u dmatop_dbg_fifo_st_h; /* 73C */ + volatile csr_dmatop_dbg_fifo_st_i_u dmatop_dbg_fifo_st_i; /* 740 */ + volatile csr_dmatop_dbg_fifo_st_j_u dmatop_dbg_fifo_st_j; /* 744 */ + volatile csr_dmatop_dbg_fifo_st_k_u dmatop_dbg_fifo_st_k; /* 748 */ + volatile csr_dmatop_dbg_fifo_st_l_u dmatop_dbg_fifo_st_l; /* 74C */ + volatile csr_dmatop_dbg_fifo_st_m_u dmatop_dbg_fifo_st_m; /* 750 */ + volatile csr_dmatop_dbg_fifo_st_n_u dmatop_dbg_fifo_st_n; /* 754 */ + volatile csr_dmatop_dbg_fifo_st_o_u dmatop_dbg_fifo_st_o; /* 758 */ + volatile csr_dmatop_dbg_fifo_st_p_u dmatop_dbg_fifo_st_p; /* 75C */ + volatile csr_dmatop_dbg_fifo_st_q_u dmatop_dbg_fifo_st_q; /* 760 */ + volatile csr_dmatop_dbg_fifo_st_r_u dmatop_dbg_fifo_st_r; /* 764 */ + volatile csr_dmatop_dbg_fifo_st_s_u dmatop_dbg_fifo_st_s; /* 768 */ + volatile csr_dmatop_dbg_fifo_st_t_u dmatop_dbg_fifo_st_t; /* 76C */ + volatile csr_dmatop_dbg_fifo_st_u_u dmatop_dbg_fifo_st_u; /* 770 */ + volatile csr_dmatop_dbg_out_a_u dmatop_dbg_out_a; /* 780 */ + volatile csr_dmatop_dbg_out_b_u dmatop_dbg_out_b; /* 784 */ + volatile csr_dmatop_dbg_out_c_u dmatop_dbg_out_c; /* 788 */ +} S_cpi_dma_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cpi_dma_csr */ +extern volatile S_cpi_dma_csr_REGS_TYPE *gopcpi_dma_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetDMA_INDRECT_CTRL_dma_indrect_addr(unsigned int udma_indrect_addr); +int iSetDMA_INDRECT_CTRL_dma_indrect_tab(unsigned int udma_indrect_tab); +int iSetDMA_INDRECT_CTRL_dma_indrect_status(unsigned int udma_indrect_status); +int iSetDMA_INDRECT_CTRL_dma_indrect_mode(unsigned int udma_indrect_mode); +int iSetDMA_INDRECT_CTRL_dma_indrect_vld(unsigned int udma_indrect_vld); +int iSetDMA_INDRECT_TIMEOUT_dma_indrect_timeout(unsigned int udma_indrect_timeout); +int iSetDMA_INDRECT_DATA_dma_indrect_data(unsigned int udma_indrect_data); +int iSetCPI_DMA_RAM_TMODE_glb_cpi_tp_ram_tmode(unsigned int uglb_cpi_tp_ram_tmode); +int iSetCPI_DMA_RAM_TMODE_glb_cpi_sp_ram_tmode(unsigned int uglb_cpi_sp_ram_tmode); +int iSetCPI_DMA_RAM_TMODE_glb_cpi_mem_power_mode(unsigned int uglb_cpi_mem_power_mode); +int iSetCPI_DMA_RAM_TMODE_glb_cpi_ecc_bypass(unsigned int uglb_cpi_ecc_bypass); +int iSetMSI_BAR_OFFSET_glb_pba_offset(unsigned int uglb_pba_offset); +int iSetMSI_BAR_OFFSET_glb_cpl_data_rsv(unsigned int uglb_cpl_data_rsv); +int iSetPF_RANGE_PORT_pf_func_idx_l(unsigned int upf_func_idx_l); +int iSetPF_RANGE_PORT_pf_func_idx_h(unsigned int upf_func_idx_h); +int iSetPF_RANGE_PORT_pf_func_idx_v(unsigned int upf_func_idx_v); +int iSetVF_RANGE_PORT_vf_func_idx_l(unsigned int uvf_func_idx_l); +int iSetVF_RANGE_PORT_vf_func_idx_h(unsigned int uvf_func_idx_h); +int iSetVF_RANGE_PORT_vf_func_idx_v(unsigned int uvf_func_idx_v); +int iSetLVF_RANGE_PORT_lvf_func_idx_l(unsigned int ulvf_func_idx_l); +int iSetLVF_RANGE_PORT_lvf_func_idx_h(unsigned int ulvf_func_idx_h); +int iSetLVF_RANGE_PORT_lvf_func_idx_v(unsigned int ulvf_func_idx_v); +int iSetCEQ_NUM_ACC_WEIGHT_ceq_num_acc_weight(unsigned int uceq_num_acc_weight); +int iSetCOPY_EP_2_COS_EN_copy_ep2cos_4_spu_en(unsigned int ucopy_ep2cos_4_spu_en); +int iSetCOPY_EP_2_COS_EN_modify_src_4_spu_en(unsigned int umodify_src_4_spu_en); +int iSetCOPY_EP_2_COS_EN_modify_src_idx(unsigned int umodify_src_idx); +int iSetDMA_ATTR_NUM_glb_dma_attr_per_func(unsigned int uglb_dma_attr_per_func); +int iSetDMA_CTRL_0_flxq_mode_en(unsigned int uflxq_mode_en); +int iSetDMA_CTRL_0_pcie_cpi_tag_modify_chk_en(unsigned int upcie_cpi_tag_modify_chk_en); +int iSetDMA_CTRL_0_rdr_buf_cfg_chk_en(unsigned int urdr_buf_cfg_chk_en); +int iSetDMA_CTRL_0_cfg_bme_clr_no_flush(unsigned int ucfg_bme_clr_no_flush); +int iSetDMA_CTRL_0_cfg_osch_drp_no_flush(unsigned int ucfg_osch_drp_no_flush); +int iSetDMA_CTRL_0_cfg_bme_int_mode(unsigned int ucfg_bme_int_mode); +int iSetDMA_RAM_INIT_ipush_csr_ceq_ram_ini(unsigned int uipush_csr_ceq_ram_ini); +int iSetDMA_RAM_INIT_ceq_num_init_start(unsigned int uceq_num_init_start); +int iSetDMA_RAM_INIT_dma_attr_ram_ini_req(unsigned int udma_attr_ram_ini_req); +int iSetDMA_RAM_INIT_func_idx_remap_ram_ini_req(unsigned int ufunc_idx_remap_ram_ini_req); +int iSetDMA_RAM_STATUS_ceq_mtt_tab_ram_ini_sts(unsigned int uceq_mtt_tab_ram_ini_sts); +int iSetDMA_RAM_STATUS_ceq_attr_csr_ram_ini_sts(unsigned int uceq_attr_csr_ram_ini_sts); +int iSetDMA_RAM_STATUS_ceq_num_init_done(unsigned int uceq_num_init_done); +int iSetDMA_RAM_STATUS_dma_attr_ram_ini_sts(unsigned int udma_attr_ram_ini_sts); +int iSetDMA_RAM_STATUS_func_idx_remap_ram_ini_sts(unsigned int ufunc_idx_remap_ram_ini_sts); +int iSetPCIE_TIMEOUT_oubd_tag_time_out_treshold(unsigned int uoubd_tag_time_out_treshold); +int iSetPCIE_TIMEOUT_oubd_tag_time_out_unit_16us(unsigned int uoubd_tag_time_out_unit_16us); +int iSetPCIE_TAG_FORCE_mpu_force_clr_func(unsigned int umpu_force_clr_func); +int iSetPCIE_TAG_FORCE_mpu_force_clr(unsigned int umpu_force_clr); +int iSetPCIE_TAG_FORCE_ITF_mpu_port_force_clr_idx(unsigned int umpu_port_force_clr_idx); +int iSetPCIE_TAG_FORCE_ITF_mpu_port_force_clr(unsigned int umpu_port_force_clr); +int iSetTIMEOUT_DLY_CFG_timeout_itf_dly_th(unsigned int utimeout_itf_dly_th); +int iSetTIMEOUT_DLY_CFG_timeout_itf_unit(unsigned int utimeout_itf_unit); +int iSetPCIE_CFG_MOD_mrrs_used_mode(unsigned int umrrs_used_mode); +int iSetPCIE_CFG_MOD_timeout_set_used_mode(unsigned int utimeout_set_used_mode); +int iSetPCIE_CFG_LOC_SET_cfg_local_mrrs(unsigned int ucfg_local_mrrs); +int iSetPCIE_CFG_LOC_SET_cfg_local_timeout_val(unsigned int ucfg_local_timeout_val); +int iSetPCIE_CFG_LOC_SET_cfg_local_timeout_dis(unsigned int ucfg_local_timeout_dis); +int iSetSPU_CFG_LOC_SET_cfg_spu_local_mrrs(unsigned int ucfg_spu_local_mrrs); +int iSetSPU_CFG_LOC_SET_cfg_spu_local_timeout_val(unsigned int ucfg_spu_local_timeout_val); +int iSetSPU_CFG_LOC_SET_cfg_spu_local_timeout_dis(unsigned int ucfg_spu_local_timeout_dis); +int iSetDMA_TOP_ECO0_dma_top_eco0(unsigned int udma_top_eco0); +int iSetDMA_TOP_ECO1_dma_top_eco1(unsigned int udma_top_eco1); +int iSetDMA_TOP_ECO2_dma_top_eco2(unsigned int udma_top_eco2); +int iSetDMA_TOP_ECO3_dma_top_eco3(unsigned int udma_top_eco3); +int iSetDMA_TOP_ECO4_dma_top_eco4(unsigned int udma_top_eco4); +int iSetCPL_TIMEOUT_VALUE0_oubd_tag_treshold_0set(unsigned int uoubd_tag_treshold_0set); +int iSetCPL_TIMEOUT_VALUE0_oubd_tag_unit_16us_0set(unsigned int uoubd_tag_unit_16us_0set); +int iSetCPL_TIMEOUT_VALUE1_oubd_tag_treshold_1set(unsigned int uoubd_tag_treshold_1set); +int iSetCPL_TIMEOUT_VALUE1_oubd_tag_unit_16us_1set(unsigned int uoubd_tag_unit_16us_1set); +int iSetCPL_TIMEOUT_VALUE2_oubd_tag_treshold_2set(unsigned int uoubd_tag_treshold_2set); +int iSetCPL_TIMEOUT_VALUE2_oubd_tag_unit_16us_2set(unsigned int uoubd_tag_unit_16us_2set); +int iSetCPL_TIMEOUT_VALUE5_oubd_tag_treshold_5set(unsigned int uoubd_tag_treshold_5set); +int iSetCPL_TIMEOUT_VALUE5_oubd_tag_unit_16us_5set(unsigned int uoubd_tag_unit_16us_5set); +int iSetCPL_TIMEOUT_VALUE6_oubd_tag_treshold_6set(unsigned int uoubd_tag_treshold_6set); +int iSetCPL_TIMEOUT_VALUE6_oubd_tag_unit_16us_6set(unsigned int uoubd_tag_unit_16us_6set); +int iSetCPL_TIMEOUT_VALUE9_oubd_tag_treshold_9set(unsigned int uoubd_tag_treshold_9set); +int iSetCPL_TIMEOUT_VALUE9_oubd_tag_unit_16us_9set(unsigned int uoubd_tag_unit_16us_9set); +int iSetCPL_TIMEOUT_VALUEA_oubd_tag_treshold_aset(unsigned int uoubd_tag_treshold_aset); +int iSetCPL_TIMEOUT_VALUEA_oubd_tag_unit_16us_aset(unsigned int uoubd_tag_unit_16us_aset); +int iSetCPL_TIMEOUT_VALUE_DIS_oubd_tag_treshold_dis_set(unsigned int uoubd_tag_treshold_dis_set); +int iSetCPL_TIMEOUT_VALUE_DIS_oubd_tag_unit_16us_dis_set(unsigned int uoubd_tag_unit_16us_dis_set); +int iSetPDI_TAG_CNT0_dbg_pcie_ur_cpl_req_cnt(unsigned int udbg_pcie_ur_cpl_req_cnt); +int iSetPDI_TAG_CNT0_dbg_pending_tag_req_cnt(unsigned int udbg_pending_tag_req_cnt); +int iSetPDI_TAG_CNT1_dbg_timeout_req_cnt(unsigned int udbg_timeout_req_cnt); +int iSetPDI_TAG_CNT1_dbg_osch_quick_back_cnt(unsigned int udbg_osch_quick_back_cnt); +int iSetPDI_TAG_CNT2_dbg_aer_uc_cnt(unsigned int udbg_aer_uc_cnt); +int iSetPDI_TAG_CNT2_dbg_mpu_force_cnt(unsigned int udbg_mpu_force_cnt); +int iSetPDI_TAG_CNT3_dbg_pcie_ictl_sop_cnt(unsigned int udbg_pcie_ictl_sop_cnt); +int iSetPDI_TAG_CNT3_dbg_10bit_err_cnt(unsigned int udbg_10bit_err_cnt); +int iSetPDI_TAG_CNT4_dbg_icpl_ep_cnt(unsigned int udbg_icpl_ep_cnt); +int iSetPDI_TAG_CNT4_dbg_pcie_ictl_eop_cnt(unsigned int udbg_pcie_ictl_eop_cnt); +int iSetPDI_TAG_CNT5_dbg_icpl_unsucc_cnt(unsigned int udbg_icpl_unsucc_cnt); +int iSetPDI_TAG_CNT5_dbg_icpl_null_cnt(unsigned int udbg_icpl_null_cnt); +int iSetPDI_TAG_CNT6_dbg_osch_spu_quick_back_cnt(unsigned int udbg_osch_spu_quick_back_cnt); +int iSetPDI_TAG_CNT7_dbg_timeout3_req_cnt(unsigned int udbg_timeout3_req_cnt); +int iSetPDI_TAG_CNT7_dbg_timeout4_req_cnt(unsigned int udbg_timeout4_req_cnt); +int iSetPDI_TAG_CNT8_dbg_timeout1_req_cnt(unsigned int udbg_timeout1_req_cnt); +int iSetPDI_TAG_CNT8_dbg_timeout2_req_cnt(unsigned int udbg_timeout2_req_cnt); +int iSetPDI_TAG_CNT9_dbg_mpu_port_force_cnt(unsigned int udbg_mpu_port_force_cnt); +int iSetPDI_TAG_CNT10_cpi_cpld_spu_pkt_cnt(unsigned int ucpi_cpld_spu_pkt_cnt); +int iSetPDI_TAG_CNT10_cpi_cpld_x86_pkt_cnt(unsigned int ucpi_cpld_x86_pkt_cnt); +int iSetCEQ_BLK_CNT_dbg_ceq_tx_int_req_cnt(unsigned int udbg_ceq_tx_int_req_cnt); +int iSetCEQ_BLK_CNT_dbg_ceq_ci_sw_wr_cnt(unsigned int udbg_ceq_ci_sw_wr_cnt); +int iSetCEQ_CSR_ST_dbg_ceq_state(unsigned int udbg_ceq_state); +int iSetFLR_RCV_CNT0_cpi_rcv_pcie1_flr_cnt(unsigned int ucpi_rcv_pcie1_flr_cnt); +int iSetFLR_RCV_CNT0_cpi_rcv_pcie0_flr_cnt(unsigned int ucpi_rcv_pcie0_flr_cnt); +int iSetFLR_RCV_CNT1_cpi_rcv_pcie3_flr_cnt(unsigned int ucpi_rcv_pcie3_flr_cnt); +int iSetFLR_RCV_CNT1_cpi_rcv_pcie2_flr_cnt(unsigned int ucpi_rcv_pcie2_flr_cnt); +int iSetFLR_RCV_CNT2_cpi_rcv_pcie4_flr_cnt(unsigned int ucpi_rcv_pcie4_flr_cnt); +int iSetDMA_CTRL_BUS0_dma_ctrl_bus4(unsigned int udma_ctrl_bus4); +int iSetDMA_CTRL_BUS1_dma_ctrl_bus3(unsigned int udma_ctrl_bus3); +int iSetDMA_CTRL_BUS2_dma_ctrl_bus2(unsigned int udma_ctrl_bus2); +int iSetDMA_CTRL_BUS3_dma_ctrl_bus1(unsigned int udma_ctrl_bus1); +int iSetDMA_CTRL_BUS4_dma_ctrl_bus0(unsigned int udma_ctrl_bus0); +int iSetDMA_PCIE_INBD_ITF_WIND_CTL_itf_wind_16t(unsigned int uitf_wind_16t); +int iSetDMA_PCIE_INBD_ITF_WIND_CTL_itf_wind_mode(unsigned int uitf_wind_mode); +int iSetDMA_PCIE_INBD_ITF_WIND_CTL_itf_wind_start(unsigned int uitf_wind_start); +int iSetDMA_PCIE_INBD_ITF_WIND_CNT_itf_wind_detect_mode_cnt(unsigned int uitf_wind_detect_mode_cnt); +int iSetDMA_PCIE_INBD_ITF_WIND_CNT_itf_wind_detect_done(unsigned int uitf_wind_detect_done); +int iSetDMA_PCIE_INBD_ITF_WIND_TLP_CNT_itf_wind_detect_tlp_cnt(unsigned int uitf_wind_detect_tlp_cnt); +int iSetCPI_RCV_BME_STS_cpi_rcv_bme_clear_func_idx(unsigned int ucpi_rcv_bme_clear_func_idx); +int iSetCPI_RCV_BME_STS_cpi_rcv_bme_clear_lat_en(unsigned int ucpi_rcv_bme_clear_lat_en); +int iSetCPI_TAG_TIMEOUT_SEL_cpi_tag_timeout_sel(unsigned int ucpi_tag_timeout_sel); +int iSetCPI_TAG_TIMEOUT_CLEAR_cpi_tag_timeout_clr_pulse(unsigned int ucpi_tag_timeout_clr_pulse); +int iSetCPI_TAG_TIMEOUT_ST_OUT_cpi_tag_timeout_func_ro(unsigned int ucpi_tag_timeout_func_ro); +int iSetCPI_TAG_TIMEOUT_GROUP_ST_OUT_cpi_tag_timeout_func_group_ro(unsigned int ucpi_tag_timeout_func_group_ro); +int iSetCPI_PDI_A_FATAL_MSK_pdi_dfx_a_fatal_mask(unsigned int updi_dfx_a_fatal_mask); +int iSetCPI_PDI_A_NONFATAL_MSK_pdi_dfx_a_nonfatal_mask(unsigned int updi_dfx_a_nonfatal_mask); +int iSetCPI_PDI_A_INT_PLS_pdi_dfx_a_pls(unsigned int updi_dfx_a_pls); +int iSetCPI_PDI_B_FATAL_MSK_pdi_dfx_b_fatal_mask(unsigned int updi_dfx_b_fatal_mask); +int iSetCPI_PDI_B_NONFATAL_MSK_pdi_dfx_b_nonfatal_mask(unsigned int updi_dfx_b_nonfatal_mask); +int iSetCPI_PDI_B_INT_PLS_pdi_dfx_b_pls(unsigned int updi_dfx_b_pls); +int iSetCPI_VIRTIO_CAP_EN_virtio_cap_en(unsigned int uvirtio_cap_en); +int iSetCPI_VIRTIO_CAP_00VALUE_PF_virtio_cap_00value_pf(unsigned int uvirtio_cap_00value_pf); +int iSetCPI_VIRTIO_CAP_01VALUE_PF_virtio_cap_01value_pf(unsigned int uvirtio_cap_01value_pf); +int iSetCPI_VIRTIO_CAP_02VALUE_PF_virtio_cap_02value_pf(unsigned int uvirtio_cap_02value_pf); +int iSetCPI_VIRTIO_CAP_03VALUE_PF_virtio_cap_03value_pf(unsigned int uvirtio_cap_03value_pf); +int iSetCPI_VIRTIO_CAP_04VALUE_PF_virtio_cap_04value_pf(unsigned int uvirtio_cap_04value_pf); +int iSetCPI_VIRTIO_CAP_05VALUE_PF_virtio_cap_05value_pf(unsigned int uvirtio_cap_05value_pf); +int iSetCPI_VIRTIO_CAP_06VALUE_PF_virtio_cap_06value_pf(unsigned int uvirtio_cap_06value_pf); +int iSetCPI_VIRTIO_CAP_07VALUE_PF_virtio_cap_07value_pf(unsigned int uvirtio_cap_07value_pf); +int iSetCPI_VIRTIO_CAP_08VALUE_PF_virtio_cap_08value_pf(unsigned int uvirtio_cap_08value_pf); +int iSetCPI_VIRTIO_CAP_09VALUE_PF_virtio_cap_09value_pf(unsigned int uvirtio_cap_09value_pf); +int iSetCPI_VIRTIO_CAP_10VALUE_PF_virtio_cap_10value_pf(unsigned int uvirtio_cap_10value_pf); +int iSetCPI_VIRTIO_CAP_11VALUE_PF_virtio_cap_11value_pf(unsigned int uvirtio_cap_11value_pf); +int iSetCPI_VIRTIO_CAP_12VALUE_PF_virtio_cap_12value_pf(unsigned int uvirtio_cap_12value_pf); +int iSetCPI_VIRTIO_CAP_13VALUE_PF_virtio_cap_13value_pf(unsigned int uvirtio_cap_13value_pf); +int iSetCPI_VIRTIO_CAP_14VALUE_PF_virtio_cap_14value_pf(unsigned int uvirtio_cap_14value_pf); +int iSetCPI_VIRTIO_CAP_15VALUE_PF_virtio_cap_15value_pf(unsigned int uvirtio_cap_15value_pf); +int iSetCPI_VIRTIO_CAP_16VALUE_PF_virtio_cap_16value_pf(unsigned int uvirtio_cap_16value_pf); +int iSetCPI_VIRTIO_CAP_00VALUE_VF_virtio_cap_00value_vf(unsigned int uvirtio_cap_00value_vf); +int iSetCPI_VIRTIO_CAP_01VALUE_VF_virtio_cap_01value_vf(unsigned int uvirtio_cap_01value_vf); +int iSetCPI_VIRTIO_CAP_02VALUE_VF_virtio_cap_02value_vf(unsigned int uvirtio_cap_02value_vf); +int iSetCPI_VIRTIO_CAP_03VALUE_VF_virtio_cap_03value_vf(unsigned int uvirtio_cap_03value_vf); +int iSetCPI_VIRTIO_CAP_04VALUE_VF_virtio_cap_04value_vf(unsigned int uvirtio_cap_04value_vf); +int iSetCPI_VIRTIO_CAP_05VALUE_VF_virtio_cap_05value_vf(unsigned int uvirtio_cap_05value_vf); +int iSetCPI_VIRTIO_CAP_06VALUE_VF_virtio_cap_06value_vf(unsigned int uvirtio_cap_06value_vf); +int iSetCPI_VIRTIO_CAP_07VALUE_VF_virtio_cap_07value_vf(unsigned int uvirtio_cap_07value_vf); +int iSetCPI_VIRTIO_CAP_08VALUE_VF_virtio_cap_08value_vf(unsigned int uvirtio_cap_08value_vf); +int iSetCPI_VIRTIO_CAP_09VALUE_VF_virtio_cap_09value_vf(unsigned int uvirtio_cap_09value_vf); +int iSetCPI_VIRTIO_CAP_10VALUE_VF_virtio_cap_10value_vf(unsigned int uvirtio_cap_10value_vf); +int iSetCPI_VIRTIO_CAP_11VALUE_VF_virtio_cap_11value_vf(unsigned int uvirtio_cap_11value_vf); +int iSetCPI_VIRTIO_CAP_12VALUE_VF_virtio_cap_12value_vf(unsigned int uvirtio_cap_12value_vf); +int iSetCPI_VIRTIO_CAP_13VALUE_VF_virtio_cap_13value_vf(unsigned int uvirtio_cap_13value_vf); +int iSetCPI_VIRTIO_CAP_14VALUE_VF_virtio_cap_14value_vf(unsigned int uvirtio_cap_14value_vf); +int iSetCPI_VIRTIO_CAP_15VALUE_VF_virtio_cap_15value_vf(unsigned int uvirtio_cap_15value_vf); +int iSetCPI_VIRTIO_CAP_16VALUE_VF_virtio_cap_16value_vf(unsigned int uvirtio_cap_16value_vf); +int iSetDFX_DMATOP_RAM_ECC_CERR_dmatop_ecc_cerr(unsigned int udmatop_ecc_cerr); +int iSetDFX_DMATOP_RAM_ECC_UCERR_dmatop_ecc_ucerr(unsigned int udmatop_ecc_ucerr); +int iSetDFX_DMATOP_RAM_ERR_ADDR_dmatop_ecc_err_addr(unsigned int udmatop_ecc_err_addr); +int iSetDMATOP_ECC_INJ_REQ_dmatop_ecc_inj_req(unsigned int udmatop_ecc_inj_req); +int iSetDMATOP_DBG_FIFO_ST_A_pdi_fifo_a(unsigned int updi_fifo_a); +int iSetDMATOP_DBG_FIFO_ST_B_pdi_fifo_b(unsigned int updi_fifo_b); +int iSetDMATOP_DBG_FIFO_ST_C_pdi_fifo_c(unsigned int updi_fifo_c); +int iSetDMATOP_DBG_FIFO_ST_D_pdi_fifo_d(unsigned int updi_fifo_d); +int iSetDMATOP_DBG_FIFO_ST_E_pdi_fifo_e(unsigned int updi_fifo_e); +int iSetDMATOP_DBG_FIFO_ST_F_pdi_fifo_f(unsigned int updi_fifo_f); +int iSetDMATOP_DBG_FIFO_ST_G_pdi_fifo_g(unsigned int updi_fifo_g); +int iSetDMATOP_DBG_FIFO_ST_H_pdi_fifo_h(unsigned int updi_fifo_h); +int iSetDMATOP_DBG_FIFO_ST_I_pdi_fifo_i(unsigned int updi_fifo_i); +int iSetDMATOP_DBG_FIFO_ST_J_pdi_fifo_j(unsigned int updi_fifo_j); +int iSetDMATOP_DBG_FIFO_ST_K_pdi_fifo_k(unsigned int updi_fifo_k); +int iSetDMATOP_DBG_FIFO_ST_L_pdi_fifo_l(unsigned int updi_fifo_l); +int iSetDMATOP_DBG_FIFO_ST_M_pdi_fifo_m(unsigned int updi_fifo_m); +int iSetDMATOP_DBG_FIFO_ST_N_pdi_fifo_n(unsigned int updi_fifo_n); +int iSetDMATOP_DBG_FIFO_ST_O_pdi_fifo_o(unsigned int updi_fifo_o); +int iSetDMATOP_DBG_FIFO_ST_P_pdi_fifo_p(unsigned int updi_fifo_p); +int iSetDMATOP_DBG_FIFO_ST_Q_pdi_fifo_q(unsigned int updi_fifo_q); +int iSetDMATOP_DBG_FIFO_ST_R_pdi_fifo_r(unsigned int updi_fifo_r); +int iSetDMATOP_DBG_FIFO_ST_S_pdi_fifo_s(unsigned int updi_fifo_s); +int iSetDMATOP_DBG_FIFO_ST_T_pdi_fifo_t(unsigned int updi_fifo_t); +int iSetDMATOP_DBG_FIFO_ST_U_pdi_fifo_u(unsigned int updi_fifo_u); +int iSetDMATOP_DBG_OUT_A_pdi_out_a(unsigned int updi_out_a); +int iSetDMATOP_DBG_OUT_B_pdi_out_b(unsigned int updi_out_b); +int iSetDMATOP_DBG_OUT_C_pdi_out_c(unsigned int updi_out_c); + +/* Define the union csr_dp_normal_chl_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pipe_chl_act_en : 20; /* [19:0] */ + u32 rsv_0 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dp_normal_chl_en_u; + +/* Define the union csr_icpl_ram_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reorder_buf_init_start : 1; /* [0] */ + u32 icpl_bitmap_init_start : 5; /* [5:1] */ + u32 pre_fifo_cfg : 1; /* [6] */ + u32 icpl_cmd_info_init_start : 1; /* [7] */ + u32 icpl_res_init_start : 1; /* [8] */ + u32 rsv_1 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_ram_init_u; + +/* Define the union csr_icpl_ram_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reorder_buf_init_done : 1; /* [0] */ + u32 icpl_tag_bitmap_init_done : 5; /* [5:1] */ + u32 icpl_cmd_bitmap_init_done : 5; /* [10:6] */ + u32 icpl_cmd_info_init_done : 1; /* [11] */ + u32 rsv_2 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_ram_status_u; + +/* Define the union csr_icpl_fifo_aful_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cpld_fifo_af_cmd_th : 4; /* [3:0] */ + u32 cfg_cpld_fifo_af_dat_th : 4; /* [7:4] */ + u32 cfg_cpld_rdr_af_th : 3; /* [10:8] */ + u32 rsv_3 : 1; /* [11] */ + u32 cfg_cpld_tag_rls_af_th : 2; /* [13:12] */ + u32 rsv_4 : 2; /* [15:14] */ + u32 cfg_rdr_buf_pre_fifo_af_th : 3; /* [18:16] */ + u32 rsv_5 : 1; /* [19] */ + u32 cfg_rdr_buf_nonl2_af_th : 3; /* [22:20] */ + u32 rsv_6 : 1; /* [23] */ + u32 out_fifo_crdt_emp_gap : 4; /* [27:24] */ + u32 rsv_7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_fifo_aful_ctl_u; + +/* Define the union csr_icpl_fifo_aful_ctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 out_fifo_af_th : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_fifo_aful_ctl1_u; + +/* Define the union csr_icpl_res_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bp_dpath_tag_div4 : 8; /* [7:0] */ + u32 bp_cpath_tag_div4 : 8; /* [15:8] */ + u32 bp_tag_num_div4 : 8; /* [23:16] */ + u32 pcie_tag_type : 1; /* [24] */ + u32 rsv_8 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_res_cfg_u; + +/* Define the union csr_icpl_tag_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_tag_cnt : 10; /* [9:0] */ + u32 rsv_9 : 6; /* [15:10] */ + u32 dpath_tag_cnt : 10; /* [25:16] */ + u32 rsv_10 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_tag_cnt_u; + +/* Define the union csr_icpl_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_pkt_cnt : 10; /* [9:0] */ + u32 rsv_11 : 6; /* [15:10] */ + u32 dpath_pkt_cnt : 10; /* [25:16] */ + u32 rsv_12 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_pkt_cnt_u; + +/* Define the union csr_icpl_tag_base_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 max_tag_num_div4 : 8; /* [7:0] */ + u32 rsv_13 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_tag_base_u; + +/* Define the union csr_icpl_rdr_buf0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 non_pkt_buf_num : 11; /* [10:0] */ + u32 rsv_14 : 5; /* [15:11] */ + u32 pkt_buf_num : 11; /* [26:16] */ + u32 rsv_15 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rdr_buf0_u; + +/* Define the union csr_icpl_rdr_buf1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 type1_buf_num : 11; /* [10:0] */ + u32 rsv_16 : 5; /* [15:11] */ + u32 type0_buf_num : 11; /* [26:16] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rdr_buf1_u; + +/* Define the union csr_icpl_arb_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_reodr_acc_weight_port : 12; /* [11:0] */ + u32 rsv_18 : 4; /* [15:12] */ + u32 icpl_reodr_pre_weight_port : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_arb_weight0_u; + +/* Define the union csr_icpl_arb_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 16; /* [15:0] */ + u32 icpl_pre_fifo_weight_port : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_arb_weight1_u; + +/* Define the union csr_icpl_arb_weight2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_20 : 8; /* [7:0] */ + u32 info_wrr_weight : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_arb_weight2_u; + +/* Define the union csr_icpl_ctrl_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_tag_use_mode : 1; /* [0] */ + u32 rsv_21 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_ctrl_mod_u; + +/* Define the union csr_icpl_dbg_out_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_dbg_out_sel : 2; /* [1:0] */ + u32 rsv_22 : 2; /* [3:2] */ + u32 icpl_reodr_buf_vld_sel : 6; /* [9:4] */ + u32 icpl_dfx_cnt_en : 1; /* [10] */ + u32 rsv_23 : 1; /* [11] */ + u32 icpl_reodr_buf_rd_st_sel : 5; /* [16:12] */ + u32 rsv_24 : 7; /* [23:17] */ + u32 dfx_icpl_tag_round_trip_en : 1; /* [24] */ + u32 icpl_pkt_err_send_ceq_en : 1; /* [25] */ + u32 icpl_tag_round_type : 1; /* [26] */ + u32 icpl_atomic_soro_cfg : 2; /* [28:27] */ + u32 icpl_atomic_endian : 1; /* [29] */ + u32 icpl_atomic_64b_swap_mode : 1; /* [30] */ + u32 rsv_25 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_sel_u; + +/* Define the union csr_icpl_rtt_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_rtt_unit : 8; /* [7:0] */ + u32 rsv_26 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_ctl_u; + +/* Define the union csr_icpl_rtt_tag_idx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_idx_b : 10; /* [9:0] */ + u32 rsv_27 : 6; /* [15:10] */ + u32 dfx_icpl_tag_idx_a : 10; /* [25:16] */ + u32 rsv_28 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_tag_idx0_u; + +/* Define the union csr_icpl_rtt_tag_idx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_idx_d : 10; /* [9:0] */ + u32 rsv_29 : 6; /* [15:10] */ + u32 dfx_icpl_tag_idx_c : 10; /* [25:16] */ + u32 rsv_30 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_tag_idx1_u; + +/* Define the union csr_icpl_rtt_tag_idx2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_idx_e : 10; /* [9:0] */ + u32 rsv_31 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_tag_idx2_u; + +/* Define the union csr_icpl_rtt_rang_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_snap : 1; /* [0] */ + u32 rsv_32 : 27; /* [27:1] */ + u32 dfx_icpl_tag_range_port : 3; /* [30:28] */ + u32 rsv_33 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_rang_ctl_u; + +/* Define the union csr_icpl_rtt_rang1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_range_a : 24; /* [23:0] */ + u32 rsv_34 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_rang1_u; + +/* Define the union csr_icpl_rtt_rang2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_range_b : 24; /* [23:0] */ + u32 rsv_35 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_rang2_u; + +/* Define the union csr_icpl_rtt_rang3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_range_c : 24; /* [23:0] */ + u32 rsv_36 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_rang3_u; + +/* Define the union csr_icpl_rtt_rang4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_range_d : 24; /* [23:0] */ + u32 rsv_37 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_rang4_u; + +/* Define the union csr_icpl_rtt_cur_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_tag_rtt_cur : 24; /* [23:0] */ + u32 rsv_38 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_rtt_cur_u; + +/* Define the union csr_icpl_dbg_out_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_a_u; + +/* Define the union csr_icpl_dbg_out_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_b_u; + +/* Define the union csr_icpl_dbg_out_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_c_u; + +/* Define the union csr_icpl_dbg_out_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_d_u; + +/* Define the union csr_icpl_dbg_out_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_e_u; + +/* Define the union csr_icpl_dbg_out_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_f_u; + +/* Define the union csr_icpl_dbg_out_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_g_u; + +/* Define the union csr_icpl_dbg_out_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_h_u; + +/* Define the union csr_icpl_dbg_out_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_i_u; + +/* Define the union csr_icpl_dbg_out_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_j_u; + +/* Define the union csr_icpl_dbg_out_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_k_u; + +/* Define the union csr_icpl_dbg_out_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_l_u; + +/* Define the union csr_icpl_dbg_out_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_m_u; + +/* Define the union csr_icpl_dbg_out_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_n_u; + +/* Define the union csr_icpl_dbg_out_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_o_u; + +/* Define the union csr_icpl_dbg_out_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_p_u; + +/* Define the union csr_icpl_dbg_out_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_q_u; + +/* Define the union csr_icpl_dbg_out_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_r_u; + +/* Define the union csr_icpl_dbg_out_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_s_u; + +/* Define the union csr_icpl_dbg_out_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_t : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_t_u; + +/* Define the union csr_icpl_dbg_out_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_u_u; + +/* Define the union csr_icpl_dbg_out_v_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_v_u; + +/* Define the union csr_icpl_dbg_out_w_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_w : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_w_u; + +/* Define the union csr_icpl_dbg_out_x_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_x : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_x_u; + +/* Define the union csr_icpl_dbg_out_y_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_y : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_y_u; + +/* Define the union csr_icpl_dbg_out_z_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_out_z : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_out_z_u; + +/* Define the union csr_icpl_db_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_chl_idx_sel : 5; /* [4:0] */ + u32 rsv_39 : 2; /* [6:5] */ + u32 icpl_chl_idx_sel_for_cdpath : 1; /* [7] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_db_sel_u; + +/* Define the union csr_icpl_dbg_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_chl_eop_cnt : 16; /* [15:0] */ + u32 icpl_chl_sop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt0_u; + +/* Define the union csr_icpl_dbg_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_chl_eor_cnt : 16; /* [15:0] */ + u32 icpl_chl_sor_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt1_u; + +/* Define the union csr_icpl_dbg_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_inl_bak_miss_cnt : 16; /* [15:0] */ + u32 icpl_inl_bak_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt2_u; + +/* Define the union csr_icpl_dbg_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_inl_2osch_cnt : 16; /* [15:0] */ + u32 icpl_inl_2osch_miss_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt3_u; + +/* Define the union csr_icpl_dbg_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_aad_bak_cnt : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt4_u; + +/* Define the union csr_icpl_dbg_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_aad_bak_eop_cnt : 16; /* [15:0] */ + u32 icpl_aad_bak_sop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_cnt5_u; + +/* Define the union csr_icpl_chl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_chl_pkt_eop_cnt : 16; /* [15:0] */ + u32 icpl_chl_pkt_sop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_chl_cnt_u; + +/* Define the union csr_icpl_dbg_fifo_st_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_a_u; + +/* Define the union csr_icpl_dbg_fifo_st_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_b_u; + +/* Define the union csr_icpl_dbg_fifo_st_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_c_u; + +/* Define the union csr_icpl_dbg_fifo_st_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_d_u; + +/* Define the union csr_icpl_dbg_fifo_st_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_e_u; + +/* Define the union csr_icpl_dbg_fifo_st_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_f_u; + +/* Define the union csr_icpl_dbg_fifo_st_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_g_u; + +/* Define the union csr_icpl_dbg_fifo_st_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_h_u; + +/* Define the union csr_icpl_dbg_fifo_st_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_i_u; + +/* Define the union csr_icpl_dbg_fifo_st_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_j_u; + +/* Define the union csr_icpl_dbg_fifo_st_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_k_u; + +/* Define the union csr_icpl_dbg_fifo_st_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_l_u; + +/* Define the union csr_icpl_dbg_fifo_st_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_m_u; + +/* Define the union csr_icpl_dbg_fifo_st_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_n_u; + +/* Define the union csr_icpl_dbg_fifo_st_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_o_u; + +/* Define the union csr_icpl_dbg_fifo_st_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_p_u; + +/* Define the union csr_icpl_dbg_fifo_st_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_q_u; + +/* Define the union csr_icpl_dbg_fifo_st_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_r_u; + +/* Define the union csr_icpl_dbg_fifo_st_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_s_u; + +/* Define the union csr_icpl_dbg_fifo_st_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_t : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_t_u; + +/* Define the union csr_icpl_dbg_fifo_st_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_u_u; + +/* Define the union csr_icpl_dbg_fifo_st_v_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_v_u; + +/* Define the union csr_icpl_dbg_fifo_st_w_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_w : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_w_u; + +/* Define the union csr_icpl_dbg_fifo_st_x_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_x : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_x_u; + +/* Define the union csr_icpl_dbg_fifo_st_y_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_fifo_y : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_dbg_fifo_st_y_u; + +/* Define the union csr_icpl_plsa_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsa_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsa_fatal_msk_u; + +/* Define the union csr_icpl_plsa_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsa_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsa_nonfatal_msk_u; + +/* Define the union csr_icpl_plsa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsa : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsa_u; + +/* Define the union csr_icpl_plsb_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsb_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsb_fatal_msk_u; + +/* Define the union csr_icpl_plsb_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsb_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsb_nonfatal_msk_u; + +/* Define the union csr_icpl_plsb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_icpl_plsb : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_plsb_u; + +/* Define the union csr_dfx_icpl_ram_ecc_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_ecc_cerr : 13; /* [12:0] */ + u32 rsv_42 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_icpl_ram_ecc_cerr_u; + +/* Define the union csr_dfx_icpl_ram_ecc_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_ecc_ucerr : 13; /* [12:0] */ + u32 rsv_43 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_icpl_ram_ecc_ucerr_u; + +/* Define the union csr_dfx_icpl_ram_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_ecc_err_addr : 24; /* [23:0] */ + u32 rsv_44 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_icpl_ram_err_addr_u; + +/* Define the union csr_icpl_ecc_inj_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_ecc_inj_req : 26; /* [25:0] */ + u32 rsv_45 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icpl_ecc_inj_req_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_dp_normal_chl_en_u dp_normal_chl_en; /* 0 */ + volatile csr_icpl_ram_init_u icpl_ram_init; /* 44 */ + volatile csr_icpl_ram_status_u icpl_ram_status; /* 48 */ + volatile csr_icpl_fifo_aful_ctl_u icpl_fifo_aful_ctl; /* 50 */ + volatile csr_icpl_fifo_aful_ctl1_u icpl_fifo_aful_ctl1; /* 54 */ + volatile csr_icpl_res_cfg_u icpl_res_cfg[5]; /* 100 */ + volatile csr_icpl_tag_cnt_u icpl_tag_cnt[5]; /* 104 */ + volatile csr_icpl_pkt_cnt_u icpl_pkt_cnt[5]; /* 108 */ + volatile csr_icpl_tag_base_u icpl_tag_base[5]; /* 10C */ + volatile csr_icpl_rdr_buf0_u icpl_rdr_buf0[5]; /* 110 */ + volatile csr_icpl_rdr_buf1_u icpl_rdr_buf1[5]; /* 114 */ + volatile csr_icpl_arb_weight0_u icpl_arb_weight0; /* 1A0 */ + volatile csr_icpl_arb_weight1_u icpl_arb_weight1; /* 1A4 */ + volatile csr_icpl_arb_weight2_u icpl_arb_weight2; /* 1A8 */ + volatile csr_icpl_ctrl_mod_u icpl_ctrl_mod; /* 1AC */ + volatile csr_icpl_dbg_out_sel_u icpl_dbg_out_sel; /* 300 */ + volatile csr_icpl_rtt_ctl_u icpl_rtt_ctl; /* 304 */ + volatile csr_icpl_rtt_tag_idx0_u icpl_rtt_tag_idx0; /* 308 */ + volatile csr_icpl_rtt_tag_idx1_u icpl_rtt_tag_idx1; /* 30C */ + volatile csr_icpl_rtt_tag_idx2_u icpl_rtt_tag_idx2; /* 310 */ + volatile csr_icpl_rtt_rang_ctl_u icpl_rtt_rang_ctl; /* 314 */ + volatile csr_icpl_rtt_rang1_u icpl_rtt_rang1; /* 318 */ + volatile csr_icpl_rtt_rang2_u icpl_rtt_rang2; /* 31C */ + volatile csr_icpl_rtt_rang3_u icpl_rtt_rang3; /* 320 */ + volatile csr_icpl_rtt_rang4_u icpl_rtt_rang4; /* 324 */ + volatile csr_icpl_rtt_cur_u icpl_rtt_cur; /* 328 */ + volatile csr_icpl_dbg_out_a_u icpl_dbg_out_a; /* 360 */ + volatile csr_icpl_dbg_out_b_u icpl_dbg_out_b; /* 364 */ + volatile csr_icpl_dbg_out_c_u icpl_dbg_out_c; /* 368 */ + volatile csr_icpl_dbg_out_d_u icpl_dbg_out_d; /* 36C */ + volatile csr_icpl_dbg_out_e_u icpl_dbg_out_e; /* 370 */ + volatile csr_icpl_dbg_out_f_u icpl_dbg_out_f; /* 374 */ + volatile csr_icpl_dbg_out_g_u icpl_dbg_out_g; /* 378 */ + volatile csr_icpl_dbg_out_h_u icpl_dbg_out_h; /* 37C */ + volatile csr_icpl_dbg_out_i_u icpl_dbg_out_i; /* 380 */ + volatile csr_icpl_dbg_out_j_u icpl_dbg_out_j; /* 384 */ + volatile csr_icpl_dbg_out_k_u icpl_dbg_out_k; /* 388 */ + volatile csr_icpl_dbg_out_l_u icpl_dbg_out_l; /* 38C */ + volatile csr_icpl_dbg_out_m_u icpl_dbg_out_m; /* 390 */ + volatile csr_icpl_dbg_out_n_u icpl_dbg_out_n; /* 394 */ + volatile csr_icpl_dbg_out_o_u icpl_dbg_out_o; /* 398 */ + volatile csr_icpl_dbg_out_p_u icpl_dbg_out_p; /* 39C */ + volatile csr_icpl_dbg_out_q_u icpl_dbg_out_q; /* 3A0 */ + volatile csr_icpl_dbg_out_r_u icpl_dbg_out_r; /* 3A4 */ + volatile csr_icpl_dbg_out_s_u icpl_dbg_out_s; /* 3A8 */ + volatile csr_icpl_dbg_out_t_u icpl_dbg_out_t; /* 3AC */ + volatile csr_icpl_dbg_out_u_u icpl_dbg_out_u; /* 3B0 */ + volatile csr_icpl_dbg_out_v_u icpl_dbg_out_v; /* 3B4 */ + volatile csr_icpl_dbg_out_w_u icpl_dbg_out_w; /* 3B8 */ + volatile csr_icpl_dbg_out_x_u icpl_dbg_out_x; /* 3BC */ + volatile csr_icpl_dbg_out_y_u icpl_dbg_out_y; /* 3C0 */ + volatile csr_icpl_dbg_out_z_u icpl_dbg_out_z; /* 3C4 */ + volatile csr_icpl_db_sel_u icpl_db_sel[8]; /* 400 */ + volatile csr_icpl_dbg_cnt0_u icpl_dbg_cnt0[8]; /* 408 */ + volatile csr_icpl_dbg_cnt1_u icpl_dbg_cnt1[8]; /* 40C */ + volatile csr_icpl_dbg_cnt2_u icpl_dbg_cnt2; /* 480 */ + volatile csr_icpl_dbg_cnt3_u icpl_dbg_cnt3; /* 484 */ + volatile csr_icpl_dbg_cnt4_u icpl_dbg_cnt4; /* 488 */ + volatile csr_icpl_dbg_cnt5_u icpl_dbg_cnt5; /* 48C */ + volatile csr_icpl_chl_cnt_u icpl_chl_cnt[20]; /* 490 */ + volatile csr_icpl_dbg_fifo_st_a_u icpl_dbg_fifo_st_a; /* 500 */ + volatile csr_icpl_dbg_fifo_st_b_u icpl_dbg_fifo_st_b; /* 504 */ + volatile csr_icpl_dbg_fifo_st_c_u icpl_dbg_fifo_st_c; /* 508 */ + volatile csr_icpl_dbg_fifo_st_d_u icpl_dbg_fifo_st_d; /* 50C */ + volatile csr_icpl_dbg_fifo_st_e_u icpl_dbg_fifo_st_e; /* 510 */ + volatile csr_icpl_dbg_fifo_st_f_u icpl_dbg_fifo_st_f; /* 514 */ + volatile csr_icpl_dbg_fifo_st_g_u icpl_dbg_fifo_st_g; /* 518 */ + volatile csr_icpl_dbg_fifo_st_h_u icpl_dbg_fifo_st_h; /* 51C */ + volatile csr_icpl_dbg_fifo_st_i_u icpl_dbg_fifo_st_i; /* 520 */ + volatile csr_icpl_dbg_fifo_st_j_u icpl_dbg_fifo_st_j; /* 524 */ + volatile csr_icpl_dbg_fifo_st_k_u icpl_dbg_fifo_st_k; /* 528 */ + volatile csr_icpl_dbg_fifo_st_l_u icpl_dbg_fifo_st_l; /* 52C */ + volatile csr_icpl_dbg_fifo_st_m_u icpl_dbg_fifo_st_m; /* 530 */ + volatile csr_icpl_dbg_fifo_st_n_u icpl_dbg_fifo_st_n; /* 534 */ + volatile csr_icpl_dbg_fifo_st_o_u icpl_dbg_fifo_st_o; /* 538 */ + volatile csr_icpl_dbg_fifo_st_p_u icpl_dbg_fifo_st_p; /* 53C */ + volatile csr_icpl_dbg_fifo_st_q_u icpl_dbg_fifo_st_q; /* 540 */ + volatile csr_icpl_dbg_fifo_st_r_u icpl_dbg_fifo_st_r; /* 544 */ + volatile csr_icpl_dbg_fifo_st_s_u icpl_dbg_fifo_st_s; /* 548 */ + volatile csr_icpl_dbg_fifo_st_t_u icpl_dbg_fifo_st_t; /* 54C */ + volatile csr_icpl_dbg_fifo_st_u_u icpl_dbg_fifo_st_u; /* 550 */ + volatile csr_icpl_dbg_fifo_st_v_u icpl_dbg_fifo_st_v; /* 554 */ + volatile csr_icpl_dbg_fifo_st_w_u icpl_dbg_fifo_st_w; /* 558 */ + volatile csr_icpl_dbg_fifo_st_x_u icpl_dbg_fifo_st_x; /* 55C */ + volatile csr_icpl_dbg_fifo_st_y_u icpl_dbg_fifo_st_y; /* 560 */ + volatile csr_icpl_plsa_fatal_msk_u icpl_plsa_fatal_msk; /* 5E0 */ + volatile csr_icpl_plsa_nonfatal_msk_u icpl_plsa_nonfatal_msk; /* 5E4 */ + volatile csr_icpl_plsa_u icpl_plsa; /* 5E8 */ + volatile csr_icpl_plsb_fatal_msk_u icpl_plsb_fatal_msk; /* 5F0 */ + volatile csr_icpl_plsb_nonfatal_msk_u icpl_plsb_nonfatal_msk; /* 5F4 */ + volatile csr_icpl_plsb_u icpl_plsb; /* 5F8 */ + volatile csr_dfx_icpl_ram_ecc_cerr_u dfx_icpl_ram_ecc_cerr; /* 600 */ + volatile csr_dfx_icpl_ram_ecc_ucerr_u dfx_icpl_ram_ecc_ucerr; /* 604 */ + volatile csr_dfx_icpl_ram_err_addr_u dfx_icpl_ram_err_addr; /* 608 */ + volatile csr_icpl_ecc_inj_req_u icpl_ecc_inj_req; /* 610 */ +} S_cpi_icpl_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cpi_icpl_csr */ +extern volatile S_cpi_icpl_csr_REGS_TYPE *gopcpi_icpl_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetDP_NORMAL_CHL_EN_pipe_chl_act_en(unsigned int upipe_chl_act_en); +int iSetICPL_RAM_INIT_reorder_buf_init_start(unsigned int ureorder_buf_init_start); +int iSetICPL_RAM_INIT_icpl_bitmap_init_start(unsigned int uicpl_bitmap_init_start); +int iSetICPL_RAM_INIT_pre_fifo_cfg(unsigned int upre_fifo_cfg); +int iSetICPL_RAM_INIT_icpl_cmd_info_init_start(unsigned int uicpl_cmd_info_init_start); +int iSetICPL_RAM_INIT_icpl_res_init_start(unsigned int uicpl_res_init_start); +int iSetICPL_RAM_STATUS_reorder_buf_init_done(unsigned int ureorder_buf_init_done); +int iSetICPL_RAM_STATUS_icpl_tag_bitmap_init_done(unsigned int uicpl_tag_bitmap_init_done); +int iSetICPL_RAM_STATUS_icpl_cmd_bitmap_init_done(unsigned int uicpl_cmd_bitmap_init_done); +int iSetICPL_RAM_STATUS_icpl_cmd_info_init_done(unsigned int uicpl_cmd_info_init_done); +int iSetICPL_FIFO_AFUL_CTL_cfg_cpld_fifo_af_cmd_th(unsigned int ucfg_cpld_fifo_af_cmd_th); +int iSetICPL_FIFO_AFUL_CTL_cfg_cpld_fifo_af_dat_th(unsigned int ucfg_cpld_fifo_af_dat_th); +int iSetICPL_FIFO_AFUL_CTL_cfg_cpld_rdr_af_th(unsigned int ucfg_cpld_rdr_af_th); +int iSetICPL_FIFO_AFUL_CTL_cfg_cpld_tag_rls_af_th(unsigned int ucfg_cpld_tag_rls_af_th); +int iSetICPL_FIFO_AFUL_CTL_cfg_rdr_buf_pre_fifo_af_th(unsigned int ucfg_rdr_buf_pre_fifo_af_th); +int iSetICPL_FIFO_AFUL_CTL_cfg_rdr_buf_nonl2_af_th(unsigned int ucfg_rdr_buf_nonl2_af_th); +int iSetICPL_FIFO_AFUL_CTL_out_fifo_crdt_emp_gap(unsigned int uout_fifo_crdt_emp_gap); +int iSetICPL_FIFO_AFUL_CTL1_out_fifo_af_th(unsigned int uout_fifo_af_th); +int iSetICPL_RES_CFG_bp_dpath_tag_div4(unsigned int ubp_dpath_tag_div4); +int iSetICPL_RES_CFG_bp_cpath_tag_div4(unsigned int ubp_cpath_tag_div4); +int iSetICPL_RES_CFG_bp_tag_num_div4(unsigned int ubp_tag_num_div4); +int iSetICPL_RES_CFG_pcie_tag_type(unsigned int upcie_tag_type); +int iSetICPL_TAG_CNT_cpath_tag_cnt(unsigned int ucpath_tag_cnt); +int iSetICPL_TAG_CNT_dpath_tag_cnt(unsigned int udpath_tag_cnt); +int iSetICPL_PKT_CNT_cpath_pkt_cnt(unsigned int ucpath_pkt_cnt); +int iSetICPL_PKT_CNT_dpath_pkt_cnt(unsigned int udpath_pkt_cnt); +int iSetICPL_TAG_BASE_max_tag_num_div4(unsigned int umax_tag_num_div4); +int iSetICPL_RDR_BUF0_non_pkt_buf_num(unsigned int unon_pkt_buf_num); +int iSetICPL_RDR_BUF0_pkt_buf_num(unsigned int upkt_buf_num); +int iSetICPL_RDR_BUF1_type1_buf_num(unsigned int utype1_buf_num); +int iSetICPL_RDR_BUF1_type0_buf_num(unsigned int utype0_buf_num); +int iSetICPL_ARB_WEIGHT0_icpl_reodr_acc_weight_port(unsigned int uicpl_reodr_acc_weight_port); +int iSetICPL_ARB_WEIGHT0_icpl_reodr_pre_weight_port(unsigned int uicpl_reodr_pre_weight_port); +int iSetICPL_ARB_WEIGHT1_icpl_pre_fifo_weight_port(unsigned int uicpl_pre_fifo_weight_port); +int iSetICPL_ARB_WEIGHT2_info_wrr_weight(unsigned int uinfo_wrr_weight); +int iSetICPL_CTRL_MOD_icpl_tag_use_mode(unsigned int uicpl_tag_use_mode); +int iSetICPL_DBG_OUT_SEL_icpl_dbg_out_sel(unsigned int uicpl_dbg_out_sel); +int iSetICPL_DBG_OUT_SEL_icpl_reodr_buf_vld_sel(unsigned int uicpl_reodr_buf_vld_sel); +int iSetICPL_DBG_OUT_SEL_icpl_dfx_cnt_en(unsigned int uicpl_dfx_cnt_en); +int iSetICPL_DBG_OUT_SEL_icpl_reodr_buf_rd_st_sel(unsigned int uicpl_reodr_buf_rd_st_sel); +int iSetICPL_DBG_OUT_SEL_dfx_icpl_tag_round_trip_en(unsigned int udfx_icpl_tag_round_trip_en); +int iSetICPL_DBG_OUT_SEL_icpl_pkt_err_send_ceq_en(unsigned int uicpl_pkt_err_send_ceq_en); +int iSetICPL_DBG_OUT_SEL_icpl_tag_round_type(unsigned int uicpl_tag_round_type); +int iSetICPL_DBG_OUT_SEL_icpl_atomic_soro_cfg(unsigned int uicpl_atomic_soro_cfg); +int iSetICPL_DBG_OUT_SEL_icpl_atomic_endian(unsigned int uicpl_atomic_endian); +int iSetICPL_DBG_OUT_SEL_icpl_atomic_64b_swap_mode(unsigned int uicpl_atomic_64b_swap_mode); +int iSetICPL_RTT_CTL_dfx_icpl_tag_rtt_unit(unsigned int udfx_icpl_tag_rtt_unit); +int iSetICPL_RTT_TAG_IDX0_dfx_icpl_tag_idx_b(unsigned int udfx_icpl_tag_idx_b); +int iSetICPL_RTT_TAG_IDX0_dfx_icpl_tag_idx_a(unsigned int udfx_icpl_tag_idx_a); +int iSetICPL_RTT_TAG_IDX1_dfx_icpl_tag_idx_d(unsigned int udfx_icpl_tag_idx_d); +int iSetICPL_RTT_TAG_IDX1_dfx_icpl_tag_idx_c(unsigned int udfx_icpl_tag_idx_c); +int iSetICPL_RTT_TAG_IDX2_dfx_icpl_tag_idx_e(unsigned int udfx_icpl_tag_idx_e); +int iSetICPL_RTT_RANG_CTL_dfx_icpl_tag_snap(unsigned int udfx_icpl_tag_snap); +int iSetICPL_RTT_RANG_CTL_dfx_icpl_tag_range_port(unsigned int udfx_icpl_tag_range_port); +int iSetICPL_RTT_RANG1_dfx_icpl_tag_range_a(unsigned int udfx_icpl_tag_range_a); +int iSetICPL_RTT_RANG2_dfx_icpl_tag_range_b(unsigned int udfx_icpl_tag_range_b); +int iSetICPL_RTT_RANG3_dfx_icpl_tag_range_c(unsigned int udfx_icpl_tag_range_c); +int iSetICPL_RTT_RANG4_dfx_icpl_tag_range_d(unsigned int udfx_icpl_tag_range_d); +int iSetICPL_RTT_CUR_dfx_icpl_tag_rtt_cur(unsigned int udfx_icpl_tag_rtt_cur); +int iSetICPL_DBG_OUT_A_dfx_icpl_out_a(unsigned int udfx_icpl_out_a); +int iSetICPL_DBG_OUT_B_dfx_icpl_out_b(unsigned int udfx_icpl_out_b); +int iSetICPL_DBG_OUT_C_dfx_icpl_out_c(unsigned int udfx_icpl_out_c); +int iSetICPL_DBG_OUT_D_dfx_icpl_out_d(unsigned int udfx_icpl_out_d); +int iSetICPL_DBG_OUT_E_dfx_icpl_out_e(unsigned int udfx_icpl_out_e); +int iSetICPL_DBG_OUT_F_dfx_icpl_out_f(unsigned int udfx_icpl_out_f); +int iSetICPL_DBG_OUT_G_dfx_icpl_out_g(unsigned int udfx_icpl_out_g); +int iSetICPL_DBG_OUT_H_dfx_icpl_out_h(unsigned int udfx_icpl_out_h); +int iSetICPL_DBG_OUT_I_dfx_icpl_out_i(unsigned int udfx_icpl_out_i); +int iSetICPL_DBG_OUT_J_dfx_icpl_out_j(unsigned int udfx_icpl_out_j); +int iSetICPL_DBG_OUT_K_dfx_icpl_out_k(unsigned int udfx_icpl_out_k); +int iSetICPL_DBG_OUT_L_dfx_icpl_out_l(unsigned int udfx_icpl_out_l); +int iSetICPL_DBG_OUT_M_dfx_icpl_out_m(unsigned int udfx_icpl_out_m); +int iSetICPL_DBG_OUT_N_dfx_icpl_out_n(unsigned int udfx_icpl_out_n); +int iSetICPL_DBG_OUT_O_dfx_icpl_out_o(unsigned int udfx_icpl_out_o); +int iSetICPL_DBG_OUT_P_dfx_icpl_out_p(unsigned int udfx_icpl_out_p); +int iSetICPL_DBG_OUT_Q_dfx_icpl_out_q(unsigned int udfx_icpl_out_q); +int iSetICPL_DBG_OUT_R_dfx_icpl_out_r(unsigned int udfx_icpl_out_r); +int iSetICPL_DBG_OUT_S_dfx_icpl_out_s(unsigned int udfx_icpl_out_s); +int iSetICPL_DBG_OUT_T_dfx_icpl_out_t(unsigned int udfx_icpl_out_t); +int iSetICPL_DBG_OUT_U_dfx_icpl_out_u(unsigned int udfx_icpl_out_u); +int iSetICPL_DBG_OUT_V_dfx_icpl_out_v(unsigned int udfx_icpl_out_v); +int iSetICPL_DBG_OUT_W_dfx_icpl_out_w(unsigned int udfx_icpl_out_w); +int iSetICPL_DBG_OUT_X_dfx_icpl_out_x(unsigned int udfx_icpl_out_x); +int iSetICPL_DBG_OUT_Y_dfx_icpl_out_y(unsigned int udfx_icpl_out_y); +int iSetICPL_DBG_OUT_Z_dfx_icpl_out_z(unsigned int udfx_icpl_out_z); +int iSetICPL_DB_SEL_icpl_chl_idx_sel(unsigned int uicpl_chl_idx_sel); +int iSetICPL_DB_SEL_icpl_chl_idx_sel_for_cdpath(unsigned int uicpl_chl_idx_sel_for_cdpath); +int iSetICPL_DBG_CNT0_icpl_chl_eop_cnt(unsigned int uicpl_chl_eop_cnt); +int iSetICPL_DBG_CNT0_icpl_chl_sop_cnt(unsigned int uicpl_chl_sop_cnt); +int iSetICPL_DBG_CNT1_icpl_chl_eor_cnt(unsigned int uicpl_chl_eor_cnt); +int iSetICPL_DBG_CNT1_icpl_chl_sor_cnt(unsigned int uicpl_chl_sor_cnt); +int iSetICPL_DBG_CNT2_icpl_inl_bak_miss_cnt(unsigned int uicpl_inl_bak_miss_cnt); +int iSetICPL_DBG_CNT2_icpl_inl_bak_cnt(unsigned int uicpl_inl_bak_cnt); +int iSetICPL_DBG_CNT3_icpl_inl_2osch_cnt(unsigned int uicpl_inl_2osch_cnt); +int iSetICPL_DBG_CNT3_icpl_inl_2osch_miss_cnt(unsigned int uicpl_inl_2osch_miss_cnt); +int iSetICPL_DBG_CNT4_icpl_aad_bak_cnt(unsigned int uicpl_aad_bak_cnt); +int iSetICPL_DBG_CNT5_icpl_aad_bak_eop_cnt(unsigned int uicpl_aad_bak_eop_cnt); +int iSetICPL_DBG_CNT5_icpl_aad_bak_sop_cnt(unsigned int uicpl_aad_bak_sop_cnt); +int iSetICPL_CHL_CNT_icpl_chl_pkt_eop_cnt(unsigned int uicpl_chl_pkt_eop_cnt); +int iSetICPL_CHL_CNT_icpl_chl_pkt_sop_cnt(unsigned int uicpl_chl_pkt_sop_cnt); +int iSetICPL_DBG_FIFO_ST_A_dfx_icpl_fifo_a(unsigned int udfx_icpl_fifo_a); +int iSetICPL_DBG_FIFO_ST_B_dfx_icpl_fifo_b(unsigned int udfx_icpl_fifo_b); +int iSetICPL_DBG_FIFO_ST_C_dfx_icpl_fifo_c(unsigned int udfx_icpl_fifo_c); +int iSetICPL_DBG_FIFO_ST_D_dfx_icpl_fifo_d(unsigned int udfx_icpl_fifo_d); +int iSetICPL_DBG_FIFO_ST_E_dfx_icpl_fifo_e(unsigned int udfx_icpl_fifo_e); +int iSetICPL_DBG_FIFO_ST_F_dfx_icpl_fifo_f(unsigned int udfx_icpl_fifo_f); +int iSetICPL_DBG_FIFO_ST_G_dfx_icpl_fifo_g(unsigned int udfx_icpl_fifo_g); +int iSetICPL_DBG_FIFO_ST_H_dfx_icpl_fifo_h(unsigned int udfx_icpl_fifo_h); +int iSetICPL_DBG_FIFO_ST_I_dfx_icpl_fifo_i(unsigned int udfx_icpl_fifo_i); +int iSetICPL_DBG_FIFO_ST_J_dfx_icpl_fifo_j(unsigned int udfx_icpl_fifo_j); +int iSetICPL_DBG_FIFO_ST_K_dfx_icpl_fifo_k(unsigned int udfx_icpl_fifo_k); +int iSetICPL_DBG_FIFO_ST_L_dfx_icpl_fifo_l(unsigned int udfx_icpl_fifo_l); +int iSetICPL_DBG_FIFO_ST_M_dfx_icpl_fifo_m(unsigned int udfx_icpl_fifo_m); +int iSetICPL_DBG_FIFO_ST_N_dfx_icpl_fifo_n(unsigned int udfx_icpl_fifo_n); +int iSetICPL_DBG_FIFO_ST_O_dfx_icpl_fifo_o(unsigned int udfx_icpl_fifo_o); +int iSetICPL_DBG_FIFO_ST_P_dfx_icpl_fifo_p(unsigned int udfx_icpl_fifo_p); +int iSetICPL_DBG_FIFO_ST_Q_dfx_icpl_fifo_q(unsigned int udfx_icpl_fifo_q); +int iSetICPL_DBG_FIFO_ST_R_dfx_icpl_fifo_r(unsigned int udfx_icpl_fifo_r); +int iSetICPL_DBG_FIFO_ST_S_dfx_icpl_fifo_s(unsigned int udfx_icpl_fifo_s); +int iSetICPL_DBG_FIFO_ST_T_dfx_icpl_fifo_t(unsigned int udfx_icpl_fifo_t); +int iSetICPL_DBG_FIFO_ST_U_dfx_icpl_fifo_u(unsigned int udfx_icpl_fifo_u); +int iSetICPL_DBG_FIFO_ST_V_dfx_icpl_fifo_v(unsigned int udfx_icpl_fifo_v); +int iSetICPL_DBG_FIFO_ST_W_dfx_icpl_fifo_w(unsigned int udfx_icpl_fifo_w); +int iSetICPL_DBG_FIFO_ST_X_dfx_icpl_fifo_x(unsigned int udfx_icpl_fifo_x); +int iSetICPL_DBG_FIFO_ST_Y_dfx_icpl_fifo_y(unsigned int udfx_icpl_fifo_y); +int iSetICPL_PLSA_FATAL_MSK_dfx_icpl_plsa_fatal_msk(unsigned int udfx_icpl_plsa_fatal_msk); +int iSetICPL_PLSA_NONFATAL_MSK_dfx_icpl_plsa_nonfatal_msk(unsigned int udfx_icpl_plsa_nonfatal_msk); +int iSetICPL_PLSA_dfx_icpl_plsa(unsigned int udfx_icpl_plsa); +int iSetICPL_PLSB_FATAL_MSK_dfx_icpl_plsb_fatal_msk(unsigned int udfx_icpl_plsb_fatal_msk); +int iSetICPL_PLSB_NONFATAL_MSK_dfx_icpl_plsb_nonfatal_msk(unsigned int udfx_icpl_plsb_nonfatal_msk); +int iSetICPL_PLSB_dfx_icpl_plsb(unsigned int udfx_icpl_plsb); +int iSetDFX_ICPL_RAM_ECC_CERR_icpl_ecc_cerr(unsigned int uicpl_ecc_cerr); +int iSetDFX_ICPL_RAM_ECC_UCERR_icpl_ecc_ucerr(unsigned int uicpl_ecc_ucerr); +int iSetDFX_ICPL_RAM_ERR_ADDR_icpl_ecc_err_addr(unsigned int uicpl_ecc_err_addr); +int iSetICPL_ECC_INJ_REQ_icpl_ecc_inj_req(unsigned int uicpl_ecc_inj_req); + +/* Define the union csr_intctl_int_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intctl_int_msk_af_th : 8; /* [7:0] */ + u32 intctl_int_trig_af_th : 8; /* [15:8] */ + u32 dfx_intctl_flr_vct_sel : 7; /* [22:16] */ + u32 rsv_0 : 1; /* [23] */ + u32 intctl_dbg_sel : 1; /* [24] */ + u32 rsv_1 : 3; /* [27:25] */ + u32 cfg_for_bp_set : 1; /* [28] */ + u32 cfg_msi_data_add : 1; /* [29] */ + u32 cfg_acc_mme_notchk : 1; /* [30] */ + u32 rsv_2 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_int_ctl_u; + +/* Define the union csr_intctl_dbg_func_idx_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_bitmap__b : 8; /* [7:0] */ + u32 dfx_func_idx_bitmap__a : 8; /* [15:8] */ + u32 rsv_3 : 15; /* [30:16] */ + u32 dfx_func_idx_bitmap_start : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_bitmap_u; + +/* Define the union csr_intctl_dbg_func_idx_bitmap_wndw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_bitmap__win : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_bitmap_wndw_u; + +/* Define the union csr_intctl_dbg_func_idx_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_b : 12; /* [11:0] */ + u32 rsv_4 : 4; /* [15:12] */ + u32 dfx_func_idx_a : 12; /* [27:16] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_ab_u; + +/* Define the union csr_intctl_dbg_func_idx_cd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_d : 12; /* [11:0] */ + u32 rsv_6 : 4; /* [15:12] */ + u32 dfx_func_idx_c : 12; /* [27:16] */ + u32 rsv_7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_cd_u; + +/* Define the union csr_intctl_dbg_func_idx_ef_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_f : 12; /* [11:0] */ + u32 rsv_8 : 4; /* [15:12] */ + u32 dfx_func_idx_e : 12; /* [27:16] */ + u32 rsv_9 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_ef_u; + +/* Define the union csr_intctl_dbg_func_idx_gh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_h : 12; /* [11:0] */ + u32 rsv_10 : 4; /* [15:12] */ + u32 dfx_func_idx_g : 12; /* [27:16] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_gh_u; + +/* Define the union csr_intctl_dbg_func_idx_ab_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_b_cnt : 16; /* [15:0] */ + u32 dfx_func_idx_a_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_ab_cnt_u; + +/* Define the union csr_intctl_dbg_func_idx_cd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_d_cnt : 16; /* [15:0] */ + u32 dfx_func_idx_c_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_cd_cnt_u; + +/* Define the union csr_intctl_dbg_func_idx_ef_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_f_cnt : 16; /* [15:0] */ + u32 dfx_func_idx_e_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_ef_cnt_u; + +/* Define the union csr_intctl_dbg_func_idx_gh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_func_idx_h_cnt : 16; /* [15:0] */ + u32 dfx_func_idx_g_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_func_idx_gh_cnt_u; + +/* Define the union csr_intctl_dbg_ipush_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_ipush_cpl_cnt : 16; /* [15:0] */ + u32 dfx_intctl_ipush_req_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_ipush_cnt_u; + +/* Define the union csr_intctl_dbg_cfg_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cfg_ack_rw_cnt : 16; /* [15:0] */ + u32 dfx_cfg_req_rw_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_cfg_cnt_u; + +/* Define the union csr_intctl_dbg_msk_trig_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_fun_msk_trig_cnt : 16; /* [15:0] */ + u32 dfx_per_msk_trig_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_msk_trig_cnt_u; + +/* Define the union csr_intctl_dbg_coal_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_coal_lli_in_cnt : 16; /* [15:0] */ + u32 dfx_coal_num_int_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_coal_cnt0_u; + +/* Define the union csr_intctl_dbg_coal_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_coal_time_int_cnt : 16; /* [15:0] */ + u32 dfx_coal_normal_in_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_coal_cnt1_u; + +/* Define the union csr_intctl_dbg_msi_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_msi_int_cnt : 16; /* [15:0] */ + u32 dfx_coal_num_drop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_msi_cnt_u; + +/* Define the union csr_intctl_dbg_msix_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_pba_int_cnt : 16; /* [15:0] */ + u32 dfx_msix_int_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_msix_cnt_u; + +/* Define the union csr_intctl_dbg_vct_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_trig_vct_cnt : 16; /* [15:0] */ + u32 dfx_normal_vct_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_vct_cnt_u; + +/* Define the union csr_intctl_dbg_intx_assert_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intx_ab_cnt : 16; /* [15:0] */ + u32 dfx_intx_aa_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_intx_assert_cnt0_u; + +/* Define the union csr_intctl_dbg_intx_assert_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intx_ad_cnt : 16; /* [15:0] */ + u32 dfx_intx_ac_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_intx_assert_cnt1_u; + +/* Define the union csr_intctl_dbg_intx_deassert_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intx_db_cnt : 16; /* [15:0] */ + u32 dfx_intx_da_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_intx_deassert_cnt0_u; + +/* Define the union csr_intctl_dbg_intx_deassert_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intx_dd_cnt : 16; /* [15:0] */ + u32 dfx_intx_dc_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_intx_deassert_cnt1_u; + +/* Define the union csr_intctl_dbg_out_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_a_u; + +/* Define the union csr_intctl_dbg_out_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_b_u; + +/* Define the union csr_intctl_dbg_out_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_c_u; + +/* Define the union csr_intctl_dbg_out_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_d_u; + +/* Define the union csr_intctl_dbg_out_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_e_u; + +/* Define the union csr_intctl_dbg_out_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_f_u; + +/* Define the union csr_intctl_dbg_out_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_g : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_g_u; + +/* Define the union csr_intctl_dbg_out_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_h_u; + +/* Define the union csr_intctl_dbg_out_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_i_u; + +/* Define the union csr_intctl_dbg_out_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_j : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_j_u; + +/* Define the union csr_intctl_dbg_out_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_k : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_k_u; + +/* Define the union csr_intctl_dbg_out_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_l_u; + +/* Define the union csr_intctl_dbg_out_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_m : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_m_u; + +/* Define the union csr_intctl_dbg_out_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_n : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_n_u; + +/* Define the union csr_intctl_dbg_out_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_o_u; + +/* Define the union csr_intctl_dbg_out_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_p : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_p_u; + +/* Define the union csr_intctl_dbg_out_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_q : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_q_u; + +/* Define the union csr_intctl_dbg_out_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_r : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_r_u; + +/* Define the union csr_intctl_dbg_out_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_s : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_s_u; + +/* Define the union csr_intctl_dbg_out_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_t : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_t_u; + +/* Define the union csr_intctl_dbg_out_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_u_u; + +/* Define the union csr_intctl_dbg_out_v_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_v_u; + +/* Define the union csr_intctl_dbg_out_w_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_w : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_w_u; + +/* Define the union csr_intctl_dbg_out_x_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_x : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_x_u; + +/* Define the union csr_intctl_dbg_out_y_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_y : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_y_u; + +/* Define the union csr_intctl_dbg_out_z_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_z : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_z_u; + +/* Define the union csr_intctl_dbg_fifo_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_a_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_a_u; + +/* Define the union csr_intctl_dbg_fifo_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_b_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_b_u; + +/* Define the union csr_intctl_dbg_fifo_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_c_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_c_u; + +/* Define the union csr_intctl_dbg_fifo_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_d_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_d_u; + +/* Define the union csr_intctl_dbg_fifo_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_e_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_e_u; + +/* Define the union csr_intctl_dbg_fifo_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_f_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_f_u; + +/* Define the union csr_intctl_dbg_fifo_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_g_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_g_u; + +/* Define the union csr_intctl_dbg_fifo_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_h_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_h_u; + +/* Define the union csr_intctl_dbg_fifo_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_i_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_i_u; + +/* Define the union csr_intctl_dbg_fifo_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_j_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_j_u; + +/* Define the union csr_intctl_dbg_fifo_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_k_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_k_u; + +/* Define the union csr_intctl_dbg_fifo_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_l_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_l_u; + +/* Define the union csr_intctl_dbg_fifo_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_m_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_m_u; + +/* Define the union csr_intctl_dbg_fifo_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_n_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_n_u; + +/* Define the union csr_intctl_dbg_fifo_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_o_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_o_u; + +/* Define the union csr_intctl_dbg_fifo_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_p_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_p_u; + +/* Define the union csr_intctl_dbg_fifo_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_q_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_q_u; + +/* Define the union csr_intctl_dbg_fifo_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_fifo_r_ro : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_fifo_r_u; + +/* Define the union csr_intctl_dbg_drop_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_per_msk_drop_cnt : 16; /* [15:0] */ + u32 dfx_fm_msk_drop_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_drop_msk_u; + +/* Define the union csr_intctl_msi_bp_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_msi_bp_timeout_1st : 16; /* [15:0] */ + u32 dfx_intctl_msi_bp_timeout4_2nd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_msi_bp_timeout_u; + +/* Define the union csr_intctl_msi_bp_timeout_2nd_01p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_msi_bp_timeout1_2nd : 16; /* [15:0] */ + u32 dfx_intctl_msi_bp_timeout0_2nd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_msi_bp_timeout_2nd_01p_u; + +/* Define the union csr_intctl_msi_bp_timeout_2nd_23p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_msi_bp_timeout3_2nd : 16; /* [15:0] */ + u32 dfx_intctl_msi_bp_timeout2_2nd : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_msi_bp_timeout_2nd_23p_u; + +/* Define the union csr_intctl_flr_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_int_flr_limit : 10; /* [9:0] */ + u32 rsv_12 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_flr_limit_u; + +/* Define the union csr_intctl_reservd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsvd : 29; /* [28:0] */ + u32 mpu_write_log_to_flash : 1; /* [29] */ + u32 npu_hot_update_active : 1; /* [30] */ + u32 mpu_hot_update_active : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_reservd_u; + +/* Define the union csr_intctl_out_a_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_a_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_out_a_fatal_msk_u; + +/* Define the union csr_intctl_out_a_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_a_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_out_a_nonfatal_msk_u; + +/* Define the union csr_intctl_dbg_out_a_plus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_a_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_a_plus_u; + +/* Define the union csr_intctl_out_b_fatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_b_fatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_out_b_fatal_msk_u; + +/* Define the union csr_intctl_out_b_nonfatal_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_b_nonfatal_msk : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_out_b_nonfatal_msk_u; + +/* Define the union csr_intctl_dbg_out_b_plus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_out_b_pls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_dbg_out_b_plus_u; + +/* Define the union csr_intctl_ram_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcnt_ram_init_start : 1; /* [0] */ + u32 attr_ram_init_start : 1; /* [1] */ + u32 cap_ram_ini_start : 1; /* [2] */ + u32 pba_ram_init_start : 1; /* [3] */ + u32 msk_ram_init_start : 1; /* [4] */ + u32 tb_ram_init_start : 1; /* [5] */ + u32 int_num_init_start : 1; /* [6] */ + u32 msi_ram_ini_start : 1; /* [7] */ + u32 rsv_13 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_ram_init_u; + +/* Define the union csr_intctl_ram_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcnt_ram_init_done : 1; /* [0] */ + u32 attr_ram_init_done : 1; /* [1] */ + u32 cap_ram_ini_done : 1; /* [2] */ + u32 pba_ram_init_done : 1; /* [3] */ + u32 msk_ram_init_done : 1; /* [4] */ + u32 tb_ram_init_done : 1; /* [5] */ + u32 int_num_init_done : 1; /* [6] */ + u32 msi_ram_ini_done : 1; /* [7] */ + u32 rsv_14 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_ram_status_u; + +/* Define the union csr_intctl_ctl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipush_intctl_allow_vf_cfg : 1; /* [0] */ + u32 cfg_msk_without_trig : 1; /* [1] */ + u32 rsv_15 : 1; /* [2] */ + u32 int_flr_no_clr_tab : 1; /* [3] */ + u32 intctl_coal_dbg_sel : 4; /* [7:4] */ + u32 cfg_msi_data_4byte_en : 5; /* [12:8] */ + u32 rsv_16 : 3; /* [15:13] */ + u32 cfg_msi_tlp_soro_nosnoop : 15; /* [30:16] */ + u32 rsv_17 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_ctl_u; + +/* Define the union csr_intctl_res_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_per_pf : 4; /* [3:0] */ + u32 int_per_vf : 4; /* [7:4] */ + u32 rsv_18 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_res_u; + +/* Define the union csr_intctl_csr_acc_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intctl_csr_acc_weight_port : 8; /* [7:0] */ + u32 int_num_acc_weight : 12; /* [19:8] */ + u32 rsv_19 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_csr_acc_weight_u; + +/* Define the union csr_intctl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msi_nxt_ptr : 8; /* [7:0] */ + u32 msix_nxt_ptr_pf : 8; /* [15:8] */ + u32 msix_nxt_ptr_vf : 8; /* [23:16] */ + u32 ipush_intctl_allow_pf_cfg : 1; /* [24] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl1_u; + +/* Define the union csr_intctl2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msien_crdt_gap : 6; /* [5:0] */ + u32 rsv_21 : 2; /* [7:6] */ + u32 msien_snap_2_virtio_en : 1; /* [8] */ + u32 rsv_22 : 3; /* [11:9] */ + u32 cfg_int_msk_aful_th : 3; /* [14:12] */ + u32 rsv_23 : 1; /* [15] */ + u32 cfg_intctl_csr_in_th : 2; /* [17:16] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl2_u; + +/* Define the union csr_intctl3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msix_nxt_ptr_vf_with_vio : 8; /* [7:0] */ + u32 msix_at_cfg : 10; /* [17:8] */ + u32 rsv_25 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl3_u; + +/* Define the union csr_dfx_intctl_ram_ecc_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_ram_ecc_cerr : 12; /* [11:0] */ + u32 rsv_26 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_intctl_ram_ecc_cerr_u; + +/* Define the union csr_dfx_intctl_ram_ecc_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_ram_ecc_ucerr : 12; /* [11:0] */ + u32 rsv_27 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_intctl_ram_ecc_ucerr_u; + +/* Define the union csr_dfx_intctl_ram_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_ram_err_addr : 24; /* [23:0] */ + u32 rsv_28 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_intctl_ram_err_addr_u; + +/* Define the union csr_dfx_intctl_ram_multi_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_intctl_ram_multi_err_addr : 24; /* [23:0] */ + u32 rsv_29 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dfx_intctl_ram_multi_err_addr_u; + +/* Define the union csr_intctl_ecc_inj_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 intctl_ecc_inj_req : 24; /* [23:0] */ + u32 rsv_30 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_intctl_ecc_inj_req_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_intctl_int_ctl_u intctl_int_ctl; /* 0 */ + volatile csr_intctl_dbg_func_idx_bitmap_u intctl_dbg_func_idx_bitmap; /* 8 */ + volatile csr_intctl_dbg_func_idx_bitmap_wndw_u intctl_dbg_func_idx_bitmap_wndw; /* C */ + volatile csr_intctl_dbg_func_idx_ab_u intctl_dbg_func_idx_ab; /* 10 */ + volatile csr_intctl_dbg_func_idx_cd_u intctl_dbg_func_idx_cd; /* 14 */ + volatile csr_intctl_dbg_func_idx_ef_u intctl_dbg_func_idx_ef; /* 18 */ + volatile csr_intctl_dbg_func_idx_gh_u intctl_dbg_func_idx_gh; /* 1C */ + volatile csr_intctl_dbg_func_idx_ab_cnt_u intctl_dbg_func_idx_ab_cnt; /* 20 */ + volatile csr_intctl_dbg_func_idx_cd_cnt_u intctl_dbg_func_idx_cd_cnt; /* 24 */ + volatile csr_intctl_dbg_func_idx_ef_cnt_u intctl_dbg_func_idx_ef_cnt; /* 28 */ + volatile csr_intctl_dbg_func_idx_gh_cnt_u intctl_dbg_func_idx_gh_cnt; /* 2C */ + volatile csr_intctl_dbg_ipush_cnt_u intctl_dbg_ipush_cnt; /* 30 */ + volatile csr_intctl_dbg_cfg_cnt_u intctl_dbg_cfg_cnt; /* 34 */ + volatile csr_intctl_dbg_msk_trig_cnt_u intctl_dbg_msk_trig_cnt; /* 38 */ + volatile csr_intctl_dbg_coal_cnt0_u intctl_dbg_coal_cnt0; /* 3C */ + volatile csr_intctl_dbg_coal_cnt1_u intctl_dbg_coal_cnt1; /* 40 */ + volatile csr_intctl_dbg_msi_cnt_u intctl_dbg_msi_cnt; /* 44 */ + volatile csr_intctl_dbg_msix_cnt_u intctl_dbg_msix_cnt; /* 48 */ + volatile csr_intctl_dbg_vct_cnt_u intctl_dbg_vct_cnt; /* 4C */ + volatile csr_intctl_dbg_intx_assert_cnt0_u intctl_dbg_intx_assert_cnt0; /* 50 */ + volatile csr_intctl_dbg_intx_assert_cnt1_u intctl_dbg_intx_assert_cnt1; /* 54 */ + volatile csr_intctl_dbg_intx_deassert_cnt0_u intctl_dbg_intx_deassert_cnt0; /* 58 */ + volatile csr_intctl_dbg_intx_deassert_cnt1_u intctl_dbg_intx_deassert_cnt1; /* 5C */ + volatile csr_intctl_dbg_out_a_u intctl_dbg_out_a; /* 60 */ + volatile csr_intctl_dbg_out_b_u intctl_dbg_out_b; /* 64 */ + volatile csr_intctl_dbg_out_c_u intctl_dbg_out_c; /* 68 */ + volatile csr_intctl_dbg_out_d_u intctl_dbg_out_d; /* 6C */ + volatile csr_intctl_dbg_out_e_u intctl_dbg_out_e; /* 70 */ + volatile csr_intctl_dbg_out_f_u intctl_dbg_out_f; /* 74 */ + volatile csr_intctl_dbg_out_g_u intctl_dbg_out_g; /* 78 */ + volatile csr_intctl_dbg_out_h_u intctl_dbg_out_h; /* 7C */ + volatile csr_intctl_dbg_out_i_u intctl_dbg_out_i; /* 80 */ + volatile csr_intctl_dbg_out_j_u intctl_dbg_out_j; /* 84 */ + volatile csr_intctl_dbg_out_k_u intctl_dbg_out_k; /* 88 */ + volatile csr_intctl_dbg_out_l_u intctl_dbg_out_l; /* 8C */ + volatile csr_intctl_dbg_out_m_u intctl_dbg_out_m; /* 90 */ + volatile csr_intctl_dbg_out_n_u intctl_dbg_out_n; /* 94 */ + volatile csr_intctl_dbg_out_o_u intctl_dbg_out_o; /* 98 */ + volatile csr_intctl_dbg_out_p_u intctl_dbg_out_p; /* 9C */ + volatile csr_intctl_dbg_out_q_u intctl_dbg_out_q; /* A0 */ + volatile csr_intctl_dbg_out_r_u intctl_dbg_out_r; /* A4 */ + volatile csr_intctl_dbg_out_s_u intctl_dbg_out_s; /* A8 */ + volatile csr_intctl_dbg_out_t_u intctl_dbg_out_t; /* AC */ + volatile csr_intctl_dbg_out_u_u intctl_dbg_out_u; /* B0 */ + volatile csr_intctl_dbg_out_v_u intctl_dbg_out_v; /* B4 */ + volatile csr_intctl_dbg_out_w_u intctl_dbg_out_w; /* B8 */ + volatile csr_intctl_dbg_out_x_u intctl_dbg_out_x; /* BC */ + volatile csr_intctl_dbg_out_y_u intctl_dbg_out_y; /* C0 */ + volatile csr_intctl_dbg_out_z_u intctl_dbg_out_z; /* C4 */ + volatile csr_intctl_dbg_fifo_a_u intctl_dbg_fifo_a; /* D0 */ + volatile csr_intctl_dbg_fifo_b_u intctl_dbg_fifo_b; /* D4 */ + volatile csr_intctl_dbg_fifo_c_u intctl_dbg_fifo_c; /* D8 */ + volatile csr_intctl_dbg_fifo_d_u intctl_dbg_fifo_d; /* DC */ + volatile csr_intctl_dbg_fifo_e_u intctl_dbg_fifo_e; /* E0 */ + volatile csr_intctl_dbg_fifo_f_u intctl_dbg_fifo_f; /* E4 */ + volatile csr_intctl_dbg_fifo_g_u intctl_dbg_fifo_g; /* E8 */ + volatile csr_intctl_dbg_fifo_h_u intctl_dbg_fifo_h; /* EC */ + volatile csr_intctl_dbg_fifo_i_u intctl_dbg_fifo_i; /* F0 */ + volatile csr_intctl_dbg_fifo_j_u intctl_dbg_fifo_j; /* F4 */ + volatile csr_intctl_dbg_fifo_k_u intctl_dbg_fifo_k; /* F8 */ + volatile csr_intctl_dbg_fifo_l_u intctl_dbg_fifo_l; /* FC */ + volatile csr_intctl_dbg_fifo_m_u intctl_dbg_fifo_m; /* 100 */ + volatile csr_intctl_dbg_fifo_n_u intctl_dbg_fifo_n; /* 104 */ + volatile csr_intctl_dbg_fifo_o_u intctl_dbg_fifo_o; /* 108 */ + volatile csr_intctl_dbg_fifo_p_u intctl_dbg_fifo_p; /* 10C */ + volatile csr_intctl_dbg_fifo_q_u intctl_dbg_fifo_q; /* 110 */ + volatile csr_intctl_dbg_fifo_r_u intctl_dbg_fifo_r; /* 114 */ + volatile csr_intctl_dbg_drop_msk_u intctl_dbg_drop_msk; /* 120 */ + volatile csr_intctl_msi_bp_timeout_u intctl_msi_bp_timeout; /* 200 */ + volatile csr_intctl_msi_bp_timeout_2nd_01p_u intctl_msi_bp_timeout_2nd_01p; /* 204 */ + volatile csr_intctl_msi_bp_timeout_2nd_23p_u intctl_msi_bp_timeout_2nd_23p; /* 208 */ + volatile csr_intctl_flr_limit_u intctl_flr_limit; /* 220 */ + volatile csr_intctl_reservd_u intctl_reservd; /* 230 */ + volatile csr_intctl_out_a_fatal_msk_u intctl_out_a_fatal_msk; /* 2E0 */ + volatile csr_intctl_out_a_nonfatal_msk_u intctl_out_a_nonfatal_msk; /* 2E4 */ + volatile csr_intctl_dbg_out_a_plus_u intctl_dbg_out_a_plus; /* 2E8 */ + volatile csr_intctl_out_b_fatal_msk_u intctl_out_b_fatal_msk; /* 2F0 */ + volatile csr_intctl_out_b_nonfatal_msk_u intctl_out_b_nonfatal_msk; /* 2F4 */ + volatile csr_intctl_dbg_out_b_plus_u intctl_dbg_out_b_plus; /* 2F8 */ + volatile csr_intctl_ram_init_u intctl_ram_init; /* 310 */ + volatile csr_intctl_ram_status_u intctl_ram_status; /* 314 */ + volatile csr_intctl_ctl_u intctl_ctl; /* 318 */ + volatile csr_intctl_res_u intctl_res; /* 31C */ + volatile csr_intctl_csr_acc_weight_u intctl_csr_acc_weight; /* 320 */ + volatile csr_intctl1_u intctl1; /* 324 */ + volatile csr_intctl2_u intctl2; /* 328 */ + volatile csr_intctl3_u intctl3; /* 32C */ + volatile csr_dfx_intctl_ram_ecc_cerr_u dfx_intctl_ram_ecc_cerr; /* 400 */ + volatile csr_dfx_intctl_ram_ecc_ucerr_u dfx_intctl_ram_ecc_ucerr; /* 404 */ + volatile csr_dfx_intctl_ram_err_addr_u dfx_intctl_ram_err_addr; /* 408 */ + volatile csr_dfx_intctl_ram_multi_err_addr_u dfx_intctl_ram_multi_err_addr; /* 40C */ + volatile csr_intctl_ecc_inj_req_u intctl_ecc_inj_req; /* 410 */ +} S_cpi_intctl_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cpi_intctl_csr */ +extern volatile S_cpi_intctl_csr_REGS_TYPE *gopcpi_intctl_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetINTCTL_INT_CTL_intctl_int_msk_af_th(unsigned int uintctl_int_msk_af_th); +int iSetINTCTL_INT_CTL_intctl_int_trig_af_th(unsigned int uintctl_int_trig_af_th); +int iSetINTCTL_INT_CTL_dfx_intctl_flr_vct_sel(unsigned int udfx_intctl_flr_vct_sel); +int iSetINTCTL_INT_CTL_intctl_dbg_sel(unsigned int uintctl_dbg_sel); +int iSetINTCTL_INT_CTL_cfg_for_bp_set(unsigned int ucfg_for_bp_set); +int iSetINTCTL_INT_CTL_cfg_msi_data_add(unsigned int ucfg_msi_data_add); +int iSetINTCTL_INT_CTL_cfg_acc_mme_notchk(unsigned int ucfg_acc_mme_notchk); +int iSetINTCTL_DBG_FUNC_IDX_BITMAP_dfx_func_idx_bitmap__b(unsigned int udfx_func_idx_bitmap__b); +int iSetINTCTL_DBG_FUNC_IDX_BITMAP_dfx_func_idx_bitmap__a(unsigned int udfx_func_idx_bitmap__a); +int iSetINTCTL_DBG_FUNC_IDX_BITMAP_dfx_func_idx_bitmap_start(unsigned int udfx_func_idx_bitmap_start); +int iSetINTCTL_DBG_FUNC_IDX_BITMAP_WNDW_dfx_func_idx_bitmap__win(unsigned int udfx_func_idx_bitmap__win); +int iSetINTCTL_DBG_FUNC_IDX_AB_dfx_func_idx_b(unsigned int udfx_func_idx_b); +int iSetINTCTL_DBG_FUNC_IDX_AB_dfx_func_idx_a(unsigned int udfx_func_idx_a); +int iSetINTCTL_DBG_FUNC_IDX_CD_dfx_func_idx_d(unsigned int udfx_func_idx_d); +int iSetINTCTL_DBG_FUNC_IDX_CD_dfx_func_idx_c(unsigned int udfx_func_idx_c); +int iSetINTCTL_DBG_FUNC_IDX_EF_dfx_func_idx_f(unsigned int udfx_func_idx_f); +int iSetINTCTL_DBG_FUNC_IDX_EF_dfx_func_idx_e(unsigned int udfx_func_idx_e); +int iSetINTCTL_DBG_FUNC_IDX_GH_dfx_func_idx_h(unsigned int udfx_func_idx_h); +int iSetINTCTL_DBG_FUNC_IDX_GH_dfx_func_idx_g(unsigned int udfx_func_idx_g); +int iSetINTCTL_DBG_FUNC_IDX_AB_CNT_dfx_func_idx_b_cnt(unsigned int udfx_func_idx_b_cnt); +int iSetINTCTL_DBG_FUNC_IDX_AB_CNT_dfx_func_idx_a_cnt(unsigned int udfx_func_idx_a_cnt); +int iSetINTCTL_DBG_FUNC_IDX_CD_CNT_dfx_func_idx_d_cnt(unsigned int udfx_func_idx_d_cnt); +int iSetINTCTL_DBG_FUNC_IDX_CD_CNT_dfx_func_idx_c_cnt(unsigned int udfx_func_idx_c_cnt); +int iSetINTCTL_DBG_FUNC_IDX_EF_CNT_dfx_func_idx_f_cnt(unsigned int udfx_func_idx_f_cnt); +int iSetINTCTL_DBG_FUNC_IDX_EF_CNT_dfx_func_idx_e_cnt(unsigned int udfx_func_idx_e_cnt); +int iSetINTCTL_DBG_FUNC_IDX_GH_CNT_dfx_func_idx_h_cnt(unsigned int udfx_func_idx_h_cnt); +int iSetINTCTL_DBG_FUNC_IDX_GH_CNT_dfx_func_idx_g_cnt(unsigned int udfx_func_idx_g_cnt); +int iSetINTCTL_DBG_IPUSH_CNT_dfx_intctl_ipush_cpl_cnt(unsigned int udfx_intctl_ipush_cpl_cnt); +int iSetINTCTL_DBG_IPUSH_CNT_dfx_intctl_ipush_req_cnt(unsigned int udfx_intctl_ipush_req_cnt); +int iSetINTCTL_DBG_CFG_CNT_dfx_cfg_ack_rw_cnt(unsigned int udfx_cfg_ack_rw_cnt); +int iSetINTCTL_DBG_CFG_CNT_dfx_cfg_req_rw_cnt(unsigned int udfx_cfg_req_rw_cnt); +int iSetINTCTL_DBG_MSK_TRIG_CNT_dfx_fun_msk_trig_cnt(unsigned int udfx_fun_msk_trig_cnt); +int iSetINTCTL_DBG_MSK_TRIG_CNT_dfx_per_msk_trig_cnt(unsigned int udfx_per_msk_trig_cnt); +int iSetINTCTL_DBG_COAL_CNT0_dfx_coal_lli_in_cnt(unsigned int udfx_coal_lli_in_cnt); +int iSetINTCTL_DBG_COAL_CNT0_dfx_coal_num_int_cnt(unsigned int udfx_coal_num_int_cnt); +int iSetINTCTL_DBG_COAL_CNT1_dfx_coal_time_int_cnt(unsigned int udfx_coal_time_int_cnt); +int iSetINTCTL_DBG_COAL_CNT1_dfx_coal_normal_in_cnt(unsigned int udfx_coal_normal_in_cnt); +int iSetINTCTL_DBG_MSI_CNT_dfx_msi_int_cnt(unsigned int udfx_msi_int_cnt); +int iSetINTCTL_DBG_MSI_CNT_dfx_coal_num_drop_cnt(unsigned int udfx_coal_num_drop_cnt); +int iSetINTCTL_DBG_MSIX_CNT_dfx_pba_int_cnt(unsigned int udfx_pba_int_cnt); +int iSetINTCTL_DBG_MSIX_CNT_dfx_msix_int_cnt(unsigned int udfx_msix_int_cnt); +int iSetINTCTL_DBG_VCT_CNT_dfx_trig_vct_cnt(unsigned int udfx_trig_vct_cnt); +int iSetINTCTL_DBG_VCT_CNT_dfx_normal_vct_cnt(unsigned int udfx_normal_vct_cnt); +int iSetINTCTL_DBG_INTX_ASSERT_CNT0_dfx_intx_ab_cnt(unsigned int udfx_intx_ab_cnt); +int iSetINTCTL_DBG_INTX_ASSERT_CNT0_dfx_intx_aa_cnt(unsigned int udfx_intx_aa_cnt); +int iSetINTCTL_DBG_INTX_ASSERT_CNT1_dfx_intx_ad_cnt(unsigned int udfx_intx_ad_cnt); +int iSetINTCTL_DBG_INTX_ASSERT_CNT1_dfx_intx_ac_cnt(unsigned int udfx_intx_ac_cnt); +int iSetINTCTL_DBG_INTX_DEASSERT_CNT0_dfx_intx_db_cnt(unsigned int udfx_intx_db_cnt); +int iSetINTCTL_DBG_INTX_DEASSERT_CNT0_dfx_intx_da_cnt(unsigned int udfx_intx_da_cnt); +int iSetINTCTL_DBG_INTX_DEASSERT_CNT1_dfx_intx_dd_cnt(unsigned int udfx_intx_dd_cnt); +int iSetINTCTL_DBG_INTX_DEASSERT_CNT1_dfx_intx_dc_cnt(unsigned int udfx_intx_dc_cnt); +int iSetINTCTL_DBG_OUT_A_dfx_intctl_out_a(unsigned int udfx_intctl_out_a); +int iSetINTCTL_DBG_OUT_B_dfx_intctl_out_b(unsigned int udfx_intctl_out_b); +int iSetINTCTL_DBG_OUT_C_dfx_intctl_out_c(unsigned int udfx_intctl_out_c); +int iSetINTCTL_DBG_OUT_D_dfx_intctl_out_d(unsigned int udfx_intctl_out_d); +int iSetINTCTL_DBG_OUT_E_dfx_intctl_out_e(unsigned int udfx_intctl_out_e); +int iSetINTCTL_DBG_OUT_F_dfx_intctl_out_f(unsigned int udfx_intctl_out_f); +int iSetINTCTL_DBG_OUT_G_dfx_intctl_out_g(unsigned int udfx_intctl_out_g); +int iSetINTCTL_DBG_OUT_H_dfx_intctl_out_h(unsigned int udfx_intctl_out_h); +int iSetINTCTL_DBG_OUT_I_dfx_intctl_out_i(unsigned int udfx_intctl_out_i); +int iSetINTCTL_DBG_OUT_J_dfx_intctl_out_j(unsigned int udfx_intctl_out_j); +int iSetINTCTL_DBG_OUT_K_dfx_intctl_out_k(unsigned int udfx_intctl_out_k); +int iSetINTCTL_DBG_OUT_L_dfx_intctl_out_l(unsigned int udfx_intctl_out_l); +int iSetINTCTL_DBG_OUT_M_dfx_intctl_out_m(unsigned int udfx_intctl_out_m); +int iSetINTCTL_DBG_OUT_N_dfx_intctl_out_n(unsigned int udfx_intctl_out_n); +int iSetINTCTL_DBG_OUT_O_dfx_intctl_out_o(unsigned int udfx_intctl_out_o); +int iSetINTCTL_DBG_OUT_P_dfx_intctl_out_p(unsigned int udfx_intctl_out_p); +int iSetINTCTL_DBG_OUT_Q_dfx_intctl_out_q(unsigned int udfx_intctl_out_q); +int iSetINTCTL_DBG_OUT_R_dfx_intctl_out_r(unsigned int udfx_intctl_out_r); +int iSetINTCTL_DBG_OUT_S_dfx_intctl_out_s(unsigned int udfx_intctl_out_s); +int iSetINTCTL_DBG_OUT_T_dfx_intctl_out_t(unsigned int udfx_intctl_out_t); +int iSetINTCTL_DBG_OUT_U_dfx_intctl_out_u(unsigned int udfx_intctl_out_u); +int iSetINTCTL_DBG_OUT_V_dfx_intctl_out_v(unsigned int udfx_intctl_out_v); +int iSetINTCTL_DBG_OUT_W_dfx_intctl_out_w(unsigned int udfx_intctl_out_w); +int iSetINTCTL_DBG_OUT_X_dfx_intctl_out_x(unsigned int udfx_intctl_out_x); +int iSetINTCTL_DBG_OUT_Y_dfx_intctl_out_y(unsigned int udfx_intctl_out_y); +int iSetINTCTL_DBG_OUT_Z_dfx_intctl_out_z(unsigned int udfx_intctl_out_z); +int iSetINTCTL_DBG_FIFO_A_dfx_intctl_fifo_a_ro(unsigned int udfx_intctl_fifo_a_ro); +int iSetINTCTL_DBG_FIFO_B_dfx_intctl_fifo_b_ro(unsigned int udfx_intctl_fifo_b_ro); +int iSetINTCTL_DBG_FIFO_C_dfx_intctl_fifo_c_ro(unsigned int udfx_intctl_fifo_c_ro); +int iSetINTCTL_DBG_FIFO_D_dfx_intctl_fifo_d_ro(unsigned int udfx_intctl_fifo_d_ro); +int iSetINTCTL_DBG_FIFO_E_dfx_intctl_fifo_e_ro(unsigned int udfx_intctl_fifo_e_ro); +int iSetINTCTL_DBG_FIFO_F_dfx_intctl_fifo_f_ro(unsigned int udfx_intctl_fifo_f_ro); +int iSetINTCTL_DBG_FIFO_G_dfx_intctl_fifo_g_ro(unsigned int udfx_intctl_fifo_g_ro); +int iSetINTCTL_DBG_FIFO_H_dfx_intctl_fifo_h_ro(unsigned int udfx_intctl_fifo_h_ro); +int iSetINTCTL_DBG_FIFO_I_dfx_intctl_fifo_i_ro(unsigned int udfx_intctl_fifo_i_ro); +int iSetINTCTL_DBG_FIFO_J_dfx_intctl_fifo_j_ro(unsigned int udfx_intctl_fifo_j_ro); +int iSetINTCTL_DBG_FIFO_K_dfx_intctl_fifo_k_ro(unsigned int udfx_intctl_fifo_k_ro); +int iSetINTCTL_DBG_FIFO_L_dfx_intctl_fifo_l_ro(unsigned int udfx_intctl_fifo_l_ro); +int iSetINTCTL_DBG_FIFO_M_dfx_intctl_fifo_m_ro(unsigned int udfx_intctl_fifo_m_ro); +int iSetINTCTL_DBG_FIFO_N_dfx_intctl_fifo_n_ro(unsigned int udfx_intctl_fifo_n_ro); +int iSetINTCTL_DBG_FIFO_O_dfx_intctl_fifo_o_ro(unsigned int udfx_intctl_fifo_o_ro); +int iSetINTCTL_DBG_FIFO_P_dfx_intctl_fifo_p_ro(unsigned int udfx_intctl_fifo_p_ro); +int iSetINTCTL_DBG_FIFO_Q_dfx_intctl_fifo_q_ro(unsigned int udfx_intctl_fifo_q_ro); +int iSetINTCTL_DBG_FIFO_R_dfx_intctl_fifo_r_ro(unsigned int udfx_intctl_fifo_r_ro); +int iSetINTCTL_DBG_DROP_MSK_dfx_per_msk_drop_cnt(unsigned int udfx_per_msk_drop_cnt); +int iSetINTCTL_DBG_DROP_MSK_dfx_fm_msk_drop_cnt(unsigned int udfx_fm_msk_drop_cnt); +int iSetINTCTL_MSI_BP_TIMEOUT_dfx_intctl_msi_bp_timeout_1st(unsigned int udfx_intctl_msi_bp_timeout_1st); +int iSetINTCTL_MSI_BP_TIMEOUT_dfx_intctl_msi_bp_timeout4_2nd(unsigned int udfx_intctl_msi_bp_timeout4_2nd); +int iSetINTCTL_MSI_BP_TIMEOUT_2ND_01P_dfx_intctl_msi_bp_timeout1_2nd(unsigned int udfx_intctl_msi_bp_timeout1_2nd); +int iSetINTCTL_MSI_BP_TIMEOUT_2ND_01P_dfx_intctl_msi_bp_timeout0_2nd(unsigned int udfx_intctl_msi_bp_timeout0_2nd); +int iSetINTCTL_MSI_BP_TIMEOUT_2ND_23P_dfx_intctl_msi_bp_timeout3_2nd(unsigned int udfx_intctl_msi_bp_timeout3_2nd); +int iSetINTCTL_MSI_BP_TIMEOUT_2ND_23P_dfx_intctl_msi_bp_timeout2_2nd(unsigned int udfx_intctl_msi_bp_timeout2_2nd); +int iSetINTCTL_FLR_LIMIT_glb_int_flr_limit(unsigned int uglb_int_flr_limit); +int iSetINTCTL_RESERVD_intctl_reserved(unsigned int uintctl_reserved); +int iSetINTCTL_OUT_A_FATAL_MSK_dfx_intctl_out_a_fatal_msk(unsigned int udfx_intctl_out_a_fatal_msk); +int iSetINTCTL_OUT_A_NONFATAL_MSK_dfx_intctl_out_a_nonfatal_msk(unsigned int udfx_intctl_out_a_nonfatal_msk); +int iSetINTCTL_DBG_OUT_A_PLUS_dfx_intctl_out_a_pls(unsigned int udfx_intctl_out_a_pls); +int iSetINTCTL_OUT_B_FATAL_MSK_dfx_intctl_out_b_fatal_msk(unsigned int udfx_intctl_out_b_fatal_msk); +int iSetINTCTL_OUT_B_NONFATAL_MSK_dfx_intctl_out_b_nonfatal_msk(unsigned int udfx_intctl_out_b_nonfatal_msk); +int iSetINTCTL_DBG_OUT_B_PLUS_dfx_intctl_out_b_pls(unsigned int udfx_intctl_out_b_pls); +int iSetINTCTL_RAM_INIT_pcnt_ram_init_start(unsigned int upcnt_ram_init_start); +int iSetINTCTL_RAM_INIT_attr_ram_init_start(unsigned int uattr_ram_init_start); +int iSetINTCTL_RAM_INIT_cap_ram_ini_start(unsigned int ucap_ram_ini_start); +int iSetINTCTL_RAM_INIT_pba_ram_init_start(unsigned int upba_ram_init_start); +int iSetINTCTL_RAM_INIT_msk_ram_init_start(unsigned int umsk_ram_init_start); +int iSetINTCTL_RAM_INIT_tb_ram_init_start(unsigned int utb_ram_init_start); +int iSetINTCTL_RAM_INIT_int_num_init_start(unsigned int uint_num_init_start); +int iSetINTCTL_RAM_INIT_msi_ram_ini_start(unsigned int umsi_ram_ini_start); +int iSetINTCTL_RAM_STATUS_pcnt_ram_init_done(unsigned int upcnt_ram_init_done); +int iSetINTCTL_RAM_STATUS_attr_ram_init_done(unsigned int uattr_ram_init_done); +int iSetINTCTL_RAM_STATUS_cap_ram_ini_done(unsigned int ucap_ram_ini_done); +int iSetINTCTL_RAM_STATUS_pba_ram_init_done(unsigned int upba_ram_init_done); +int iSetINTCTL_RAM_STATUS_msk_ram_init_done(unsigned int umsk_ram_init_done); +int iSetINTCTL_RAM_STATUS_tb_ram_init_done(unsigned int utb_ram_init_done); +int iSetINTCTL_RAM_STATUS_int_num_init_done(unsigned int uint_num_init_done); +int iSetINTCTL_RAM_STATUS_msi_ram_ini_done(unsigned int umsi_ram_ini_done); +int iSetINTCTL_CTL_ipush_intctl_allow_vf_cfg(unsigned int uipush_intctl_allow_vf_cfg); +int iSetINTCTL_CTL_cfg_msk_without_trig(unsigned int ucfg_msk_without_trig); +int iSetINTCTL_CTL_int_flr_no_clr_tab(unsigned int uint_flr_no_clr_tab); +int iSetINTCTL_CTL_intctl_coal_dbg_sel(unsigned int uintctl_coal_dbg_sel); +int iSetINTCTL_CTL_cfg_msi_data_4byte_en(unsigned int ucfg_msi_data_4byte_en); +int iSetINTCTL_CTL_cfg_msi_tlp_soro_nosnoop(unsigned int ucfg_msi_tlp_soro_nosnoop); +int iSetINTCTL_RES_int_per_pf(unsigned int uint_per_pf); +int iSetINTCTL_RES_int_per_vf(unsigned int uint_per_vf); +int iSetINTCTL_CSR_ACC_WEIGHT_intctl_csr_acc_weight_port(unsigned int uintctl_csr_acc_weight_port); +int iSetINTCTL_CSR_ACC_WEIGHT_int_num_acc_weight(unsigned int uint_num_acc_weight); +int iSetINTCTL1_msi_nxt_ptr(unsigned int umsi_nxt_ptr); +int iSetINTCTL1_msix_nxt_ptr_pf(unsigned int umsix_nxt_ptr_pf); +int iSetINTCTL1_msix_nxt_ptr_vf(unsigned int umsix_nxt_ptr_vf); +int iSetINTCTL1_ipush_intctl_allow_pf_cfg(unsigned int uipush_intctl_allow_pf_cfg); +int iSetINTCTL2_msien_crdt_gap(unsigned int umsien_crdt_gap); +int iSetINTCTL2_msien_snap_2_virtio_en(unsigned int umsien_snap_2_virtio_en); +int iSetINTCTL2_cfg_int_msk_aful_th(unsigned int ucfg_int_msk_aful_th); +int iSetINTCTL2_cfg_intctl_csr_in_th(unsigned int ucfg_intctl_csr_in_th); +int iSetINTCTL3_msix_nxt_ptr_vf_with_vio(unsigned int umsix_nxt_ptr_vf_with_vio); +int iSetINTCTL3_msix_at_cfg(unsigned int umsix_at_cfg); +int iSetDFX_INTCTL_RAM_ECC_CERR_dfx_intctl_ram_ecc_cerr(unsigned int udfx_intctl_ram_ecc_cerr); +int iSetDFX_INTCTL_RAM_ECC_UCERR_dfx_intctl_ram_ecc_ucerr(unsigned int udfx_intctl_ram_ecc_ucerr); +int iSetDFX_INTCTL_RAM_ERR_ADDR_dfx_intctl_ram_err_addr(unsigned int udfx_intctl_ram_err_addr); +int iSetDFX_INTCTL_RAM_MULTI_ERR_ADDR_dfx_intctl_ram_multi_err_addr(unsigned int udfx_intctl_ram_multi_err_addr); +int iSetINTCTL_ECC_INJ_REQ_intctl_ecc_inj_req(unsigned int uintctl_ecc_inj_req); + +/* Define the union csr_octl_tbl_indir_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_tbl_indir_addr : 14; /* [13:0] */ + u32 rsv_0 : 10; /* [23:14] */ + u32 octl_tbl_indir_tab : 4; /* [27:24] */ + u32 octl_tbl_indir_stat : 2; /* [29:28] */ + u32 octl_tbl_indir_mode : 1; /* [30] */ + u32 octl_tbl_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_tbl_indir_ctrl0_u; + +/* Define the union csr_octl_tbl_indir_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_tbl_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_tbl_indir_ctrl1_u; + +/* Define the union csr_octl_tbl_indir_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_tbl_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_tbl_indir_data_u; + +/* Define the union csr_octl_ram_init_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ram_ini_req : 13; /* [12:0] */ + u32 rsv_1 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_init_req_u; + +/* Define the union csr_octl_ram_init_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ram_ini_sts : 13; /* [12:0] */ + u32 rsv_2 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_init_sts_u; + +/* Define the union csr_pre_sub_dat_crd_cpb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_presub_data_crdt : 8; /* [7:0] */ + u32 rsv_3 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pre_sub_dat_crd_cpb_u; + +/* Define the union csr_l2nic_ci_wr_chl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l2nic_ci_wr_chl_port0 : 5; /* [4:0] */ + u32 l2nic_ci_wr_chl_port1 : 5; /* [9:5] */ + u32 l2nic_ci_wr_chl_port2 : 5; /* [14:10] */ + u32 l2nic_ci_wr_chl_port3 : 5; /* [19:15] */ + u32 l2nic_ci_wr_chl_port4 : 5; /* [24:20] */ + u32 rsv_4 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_l2nic_ci_wr_chl_cfg_u; + +/* Define the union csr_cqe_wr_chl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqe_wr_chl_port0 : 5; /* [4:0] */ + u32 cqe_wr_chl_port1 : 5; /* [9:5] */ + u32 cqe_wr_chl_port2 : 5; /* [14:10] */ + u32 cqe_wr_chl_port3 : 5; /* [19:15] */ + u32 cqe_wr_chl_port4 : 5; /* [24:20] */ + u32 rsv_5 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cqe_wr_chl_cfg_u; + +/* Define the union csr_pcie_port_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_port_cfg : 5; /* [4:0] */ + u32 rsv_6 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_port_cfg_u; + +/* Define the union csr_dma_pe_yyy_fifo_depth_port012_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port0_dma_pe_yyy_fifo_depth_cfg : 10; /* [9:0] */ + u32 port1_dma_pe_yyy_fifo_depth_cfg : 10; /* [19:10] */ + u32 port2_dma_pe_yyy_fifo_depth_cfg : 10; /* [29:20] */ + u32 rsv_7 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_pe_yyy_fifo_depth_port012_u; + +/* Define the union csr_dma_pe_yyy_fifo_depth_port34_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port3_dma_pe_yyy_fifo_depth_cfg : 10; /* [9:0] */ + u32 port4_dma_pe_yyy_fifo_depth_cfg : 10; /* [19:10] */ + u32 rsv_8 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_dma_pe_yyy_fifo_depth_port34_u; + +/* Define the union csr_cpi_prealloc_cpb_buf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_cell_prealloc_cfg : 10; /* [9:0] */ + u32 rsv_9 : 2; /* [11:10] */ + u32 cpb_cell_prealloc_adj : 4; /* [15:12] */ + u32 cpb_cell_prealloc_thd : 10; /* [25:16] */ + u32 rsv_10 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_prealloc_cpb_buf_u; + +/* Define the union csr_cpi_sm_chl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_sm_chl_cfg0 : 5; /* [4:0] */ + u32 rsv_11 : 3; /* [7:5] */ + u32 cpi_sm_chl_cfg1 : 5; /* [12:8] */ + u32 rsv_12 : 3; /* [15:13] */ + u32 cpi_sm_chl_cfg2 : 5; /* [20:16] */ + u32 rsv_13 : 3; /* [23:21] */ + u32 cpi_sm_chl_cfg3 : 5; /* [28:24] */ + u32 rsv_14 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_sm_chl_cfg_u; + +/* Define the union csr_octl_cut_thr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_pe_wdat_cut_through : 4; /* [3:0] */ + u32 cpath_wdat_cut_through : 4; /* [7:4] */ + u32 rsv_15 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cut_thr_cfg_u; + +/* Define the union csr_octl_in_cmd_chnl_src_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_mem_err_addr_sel : 6; /* [5:0] */ + u32 perx_cmd_cnt_chnl_sel : 5; /* [10:6] */ + u32 perx_cmd_cnt_out_grain_cfg : 1; /* [11] */ + u32 perx_cmd_cnt_in_or_out_cfg : 1; /* [12] */ + u32 l2nic_cmd_cnt_chnl_sel : 6; /* [18:13] */ + u32 l2nic_cmd_cnt_out_grain_cfg : 1; /* [19] */ + u32 l2nic_cmd_cnt_in_or_out_cfg : 1; /* [20] */ + u32 sm_cp_cmd_src_sel : 5; /* [25:21] */ + u32 cpath_cmd_cnt_in_or_out_cfg : 1; /* [26] */ + u32 sm_cp_proc_cmd_src_sel : 3; /* [29:27] */ + u32 rsv_16 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_cmd_chnl_src_sel_u; + +/* Define the union csr_octl_err_detect_reg_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_octl_fatal_err : 1; /* [0] */ + u32 cpi_octl_nonfatal_err : 1; /* [1] */ + u32 octl_mem_ecc_merr_all : 1; /* [2] */ + u32 octl_mem_ecc_err_all : 1; /* [3] */ + u32 proc_cpath_data_err : 1; /* [4] */ + u32 sm_cpath_data_err : 1; /* [5] */ + u32 sm_l2nic_data_err : 1; /* [6] */ + u32 rde_octl_data_err : 1; /* [7] */ + u32 octl_mul_dif_cfg_chnl_err : 1; /* [8] */ + u32 octl_mul_dif_cfg_en_err : 1; /* [9] */ + u32 octl_ec_chnl_cfg_chnl_err_1 : 1; /* [10] */ + u32 octl_ec_chnl_cfg_chnl_err_0 : 1; /* [11] */ + u32 octl_ec_chnl_cfg_en_err : 1; /* [12] */ + u32 octl_cpb_num_deficit_err : 1; /* [13] */ + u32 octl_sge0_len_err_less : 1; /* [14] */ + u32 octl_sge0_len_err_more : 1; /* [15] */ + u32 octl_sge0_len_err : 1; /* [16] */ + u32 perx_unknown_cmd_err : 1; /* [17] */ + u32 perxin_unknown_cmd_err : 1; /* [18] */ + u32 cpi_dpath_rel_non_vld_err_all : 1; /* [19] */ + u32 cpi_dpath_rel_loss_eop_err_all : 1; /* [20] */ + u32 cpi_dpath_rel_loss_sop_err_all : 1; /* [21] */ + u32 cpi_dpath_o_non_vld_err_all : 1; /* [22] */ + u32 cpi_dpath_o_loss_eop_err_all : 1; /* [23] */ + u32 cpi_dpath_o_loss_sop_err_all : 1; /* [24] */ + u32 octl_fifo_underflow_all : 1; /* [25] */ + u32 octl_fifo_overflow_all : 1; /* [26] */ + u32 rsv_17 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_reg_a_u; + +/* Define the union csr_octl_err_detect_reg_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 proc_cpath_non_vld_err_all : 1; /* [0] */ + u32 proc_cpath_loss_eop_err_all : 1; /* [1] */ + u32 proc_cpath_loss_sop_err_all : 1; /* [2] */ + u32 sm_cpath_non_vld_err_all : 1; /* [3] */ + u32 sm_cpath_loss_eop_err_all : 1; /* [4] */ + u32 sm_cpath_loss_sop_err_all : 1; /* [5] */ + u32 sm_l2nic_non_vld_err_all : 1; /* [6] */ + u32 sm_l2nic_loss_eop_err_all : 1; /* [7] */ + u32 sm_l2nic_loss_sop_err_all : 1; /* [8] */ + u32 octl_sm_parser_data_err : 1; /* [9] */ + u32 octl_perx_hd_dif_err : 1; /* [10] */ + u32 octl_perx_hd_wdat_err : 1; /* [11] */ + u32 octl_dpath_o_sop_err : 1; /* [12] */ + u32 rsv_18 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_reg_b_u; + +/* Define the union csr_octl_err_detect_ro_reg_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cpi_bp_all : 1; /* [0] */ + u32 osch_octl_cpath_bp_all : 1; /* [1] */ + u32 osch_octl_dpath_sm_bp_all : 1; /* [2] */ + u32 osch_octl_dpath_pe_bp_all : 1; /* [3] */ + u32 prm_cpi_src_bp_all : 1; /* [4] */ + u32 prm_cpi_bp_all : 1; /* [5] */ + u32 octl_all_fifo_no_empty : 1; /* [6] */ + u32 octl_cpath_loop_swallow_packet : 1; /* [7] */ + u32 octl_l2nic_loop_swallow_packet : 1; /* [8] */ + u32 octl_pe_loop_swallow_packet : 1; /* [9] */ + u32 dma_pre_alc_num_cur : 10; /* [19:10] */ + u32 glb_cpb_cell_num_cnt : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_ro_reg_a_u; + +/* Define the union csr_octl_err_detect_ro_reg_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cp_proc_osch_host_crd_cnt_0 : 8; /* [7:0] */ + u32 cp_proc_icpl_sm_crd_cnt : 9; /* [16:8] */ + u32 cp_proc_icpl_vio_crd_cnt : 10; /* [26:17] */ + u32 rsv_19 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_ro_reg_b_u; + +/* Define the union csr_octl_err_detect_ro_reg_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cp_proc_osch_host_crd_cnt_4 : 8; /* [7:0] */ + u32 cp_proc_osch_host_crd_cnt_3 : 8; /* [15:8] */ + u32 cp_proc_osch_host_crd_cnt_2 : 8; /* [23:16] */ + u32 cp_proc_osch_host_crd_cnt_1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_ro_reg_c_u; + +/* Define the union csr_octl_err_detect_ro_reg_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_mem_err_addr : 15; /* [14:0] */ + u32 rsv_20 : 1; /* [15] */ + u32 ci_cqe_tbl_indir_op_done : 1; /* [16] */ + u32 rsv_21 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_detect_ro_reg_d_u; + +/* Define the union csr_octl_cmd_cnt_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_a_u; + +/* Define the union csr_octl_cmd_cnt_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_b_u; + +/* Define the union csr_octl_cmd_cnt_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_rel_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_c_u; + +/* Define the union csr_octl_cmd_cnt_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_rel_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_d_u; + +/* Define the union csr_octl_cmd_cnt_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_in_chnl_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_e_u; + +/* Define the union csr_octl_cmd_cnt_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_in_chnl_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_f_u; + +/* Define the union csr_octl_cmd_cnt_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_rel_chnl_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_g_u; + +/* Define the union csr_octl_cmd_cnt_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_rel_chnl_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_h_u; + +/* Define the union csr_octl_cmd_cnt_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_rd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_i_u; + +/* Define the union csr_octl_cmd_cnt_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_rd_cqe_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_j_u; + +/* Define the union csr_octl_cmd_cnt_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_atomic_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_k_u; + +/* Define the union csr_octl_cmd_cnt_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_non_l2nic_il_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_l_u; + +/* Define the union csr_octl_cmd_cnt_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_non_l2nic_il_cqe_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_m_u; + +/* Define the union csr_octl_cmd_cnt_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_wr_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_n_u; + +/* Define the union csr_octl_cmd_cnt_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_wr_cqe_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_o_u; + +/* Define the union csr_octl_cmd_cnt_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_cqe_only_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_p_u; + +/* Define the union csr_octl_cmd_cnt_q_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ceqe_only : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_q_u; + +/* Define the union csr_octl_cmd_cnt_r_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_db_wr_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_r_u; + +/* Define the union csr_octl_cmd_cnt_s_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_mul_dif_rd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_s_u; + +/* Define the union csr_octl_cmd_cnt_t_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ec_rd_1st_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_t_u; + +/* Define the union csr_octl_cmd_cnt_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ec_rd_2nd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_u_u; + +/* Define the union csr_octl_cmd_cnt_v_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ec_cqe_rd_1st_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_v_u; + +/* Define the union csr_octl_cmd_cnt_w_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_ec_cqe_rd_2nd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_w_u; + +/* Define the union csr_octl_cmd_cnt_x_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_rd_by_aad_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_x_u; + +/* Define the union csr_octl_cmd_cnt_y_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_cqe_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_y_u; + +/* Define the union csr_octl_cmd_cnt_z_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_ci_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_z_u; + +/* Define the union csr_octl_cmd_cnt_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_cqe_only_ceqe_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_aa_u; + +/* Define the union csr_octl_cmd_cnt_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_head_obd_0_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ab_u; + +/* Define the union csr_octl_cmd_cnt_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_head_obd_1_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ac_u; + +/* Define the union csr_octl_cmd_cnt_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_head_obd_2_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ad_u; + +/* Define the union csr_octl_cmd_cnt_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_head_obd_3_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ae_u; + +/* Define the union csr_octl_cmd_cnt_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_head_obd_4_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_af_u; + +/* Define the union csr_octl_cmd_cnt_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_parser_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ag_u; + +/* Define the union csr_octl_cmd_cnt_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_parser_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ah_u; + +/* Define the union csr_octl_cmd_cnt_ai_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ai_u; + +/* Define the union csr_octl_cmd_cnt_aj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_aj_u; + +/* Define the union csr_octl_cmd_cnt_ak_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_chnl_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ak_u; + +/* Define the union csr_octl_cmd_cnt_al_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_chnl_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_al_u; + +/* Define the union csr_octl_cmd_cnt_am_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_read_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_am_u; + +/* Define the union csr_octl_cmd_cnt_an_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_ceqe_only_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_an_u; + +/* Define the union csr_octl_cmd_cnt_ao_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_il_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ao_u; + +/* Define the union csr_octl_cmd_cnt_ap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_read_ci_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ap_u; + +/* Define the union csr_octl_cmd_cnt_aq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_l2nic_il_ci_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_aq_u; + +/* Define the union csr_octl_cmd_cnt_ar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cpath_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ar_u; + +/* Define the union csr_octl_cmd_cnt_as_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cpath_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_as_u; + +/* Define the union csr_octl_cmd_cnt_at_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cpath_rd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_at_u; + +/* Define the union csr_octl_cmd_cnt_au_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cpath_wr_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_au_u; + +/* Define the union csr_octl_cmd_cnt_av_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_in_src_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_av_u; + +/* Define the union csr_octl_cmd_cnt_aw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_in_src_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_aw_u; + +/* Define the union csr_octl_cmd_cnt_ax_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_proc_src_sop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ax_u; + +/* Define the union csr_octl_cmd_cnt_ay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_proc_src_eop_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ay_u; + +/* Define the union csr_octl_cmd_cnt_az_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_proc_rd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_az_u; + +/* Define the union csr_octl_cmd_cnt_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_proc_wr_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_ba_u; + +/* Define the union csr_octl_cmd_cnt_bb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_osch_cp_rd_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bb_u; + +/* Define the union csr_octl_cmd_cnt_bc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_osch_cp_wr_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bc_u; + +/* Define the union csr_octl_cmd_port_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_rd_cqe_inc : 16; /* [15:0] */ + u32 port_octl_rd_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_aa_u; + +/* Define the union csr_octl_cmd_port_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_non_l2nic_il_inc : 16; /* [15:0] */ + u32 port_octl_atomic_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ab_u; + +/* Define the union csr_octl_cmd_port_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_wr_inc : 16; /* [15:0] */ + u32 port_octl_non_l2nic_il_cqe_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ac_u; + +/* Define the union csr_octl_cmd_port_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_cqe_only_inc : 16; /* [15:0] */ + u32 port_octl_wr_cqe_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ad_u; + +/* Define the union csr_octl_cmd_port_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_db_wr_inc : 16; /* [15:0] */ + u32 port_octl_ceqe_only_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ae_u; + +/* Define the union csr_octl_cmd_port_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_ec_rd_1st_inc : 16; /* [15:0] */ + u32 port_octl_mul_dif_rd_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_af_u; + +/* Define the union csr_octl_cmd_port_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_ec_cqe_rd_1st_inc : 16; /* [15:0] */ + u32 port_octl_ec_rd_2nd_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ag_u; + +/* Define the union csr_octl_cmd_port_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_octl_rd_by_aad_inc : 16; /* [15:0] */ + u32 port_octl_ec_cqe_rd_2nd_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ah_u; + +/* Define the union csr_octl_cmd_port_ai_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_icpl_cqe_only_ceqe_inc : 16; /* [15:0] */ + u32 port_icpl_cqe_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ai_u; + +/* Define the union csr_octl_cmd_port_aj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_pe_cmd_port_inc : 16; /* [15:0] */ + u32 port_icpl_ci_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_aj_u; + +/* Define the union csr_octl_cmd_port_ak_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_sm_l2nic_ceqe_only_inc : 16; /* [15:0] */ + u32 port_sm_l2nic_read_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_ak_u; + +/* Define the union csr_octl_cmd_port_al_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_sm_l2nic_read_ci_inc : 16; /* [15:0] */ + u32 port_sm_l2nic_il_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_al_u; + +/* Define the union csr_octl_cmd_port_am_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_port_cp_inc : 16; /* [15:0] */ + u32 port_sm_l2nic_il_ci_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_am_u; + +/* Define the union csr_octl_cmd_port_an_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_port_cp_wr_inc : 16; /* [15:0] */ + u32 octl_port_cp_rd_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_port_an_u; + +/* Define the union csr_octl_cmd_cnt_bd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_parser_cpath_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bd_u; + +/* Define the union csr_octl_cmd_cnt_be_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_parser_l2nic_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_be_u; + +/* Define the union csr_octl_cmd_cnt_bf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_parser_ceqe_only_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bf_u; + +/* Define the union csr_octl_cmd_cnt_bg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 proc_cpath_eop_inc : 16; /* [15:0] */ + u32 proc_cpath_sop_inc : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bg_u; + +/* Define the union csr_octl_cmd_cnt_bh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_drop_zero_sge_len_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_cmd_cnt_bh_u; + +/* Define the union csr_octl_dpath_o_err_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_o_chnl_sop_err : 20; /* [19:0] */ + u32 rsv_22 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_dpath_o_err_dfx_u; + +/* Define the union csr_octl_sub_err_cfg_bk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_18 : 20; /* [19:0] */ + u32 rsv_23 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bk_u; + +/* Define the union csr_octl_sub_err_cfg_bl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_18 : 20; /* [19:0] */ + u32 rsv_24 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bl_u; + +/* Define the union csr_octl_sub_err_cfg_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_0 : 22; /* [21:0] */ + u32 rsv_25 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_aa_u; + +/* Define the union csr_octl_sub_err_cfg_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_0 : 22; /* [21:0] */ + u32 rsv_26 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ab_u; + +/* Define the union csr_octl_sub_err_cfg_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_1 : 22; /* [21:0] */ + u32 rsv_27 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ac_u; + +/* Define the union csr_octl_sub_err_cfg_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_1 : 22; /* [21:0] */ + u32 rsv_28 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ad_u; + +/* Define the union csr_octl_sub_err_cfg_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_2 : 20; /* [19:0] */ + u32 rsv_29 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ae_u; + +/* Define the union csr_octl_sub_err_cfg_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_2 : 20; /* [19:0] */ + u32 rsv_30 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_af_u; + +/* Define the union csr_octl_sub_err_cfg_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_3 : 20; /* [19:0] */ + u32 rsv_31 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ag_u; + +/* Define the union csr_octl_sub_err_cfg_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_3 : 20; /* [19:0] */ + u32 rsv_32 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ah_u; + +/* Define the union csr_octl_sub_err_cfg_ai_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_4 : 20; /* [19:0] */ + u32 rsv_33 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ai_u; + +/* Define the union csr_octl_sub_err_cfg_aj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_4 : 20; /* [19:0] */ + u32 rsv_34 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_aj_u; + +/* Define the union csr_octl_sub_err_cfg_ak_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_5 : 20; /* [19:0] */ + u32 rsv_35 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ak_u; + +/* Define the union csr_octl_sub_err_cfg_al_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_5 : 20; /* [19:0] */ + u32 rsv_36 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_al_u; + +/* Define the union csr_octl_sub_err_cfg_am_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_6 : 20; /* [19:0] */ + u32 rsv_37 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_am_u; + +/* Define the union csr_octl_sub_err_cfg_an_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_6 : 20; /* [19:0] */ + u32 rsv_38 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_an_u; + +/* Define the union csr_octl_sub_err_cfg_ao_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_7 : 20; /* [19:0] */ + u32 rsv_39 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ao_u; + +/* Define the union csr_octl_sub_err_cfg_ap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_7 : 20; /* [19:0] */ + u32 rsv_40 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ap_u; + +/* Define the union csr_octl_sub_err_cfg_aq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_aq_u; + +/* Define the union csr_octl_sub_err_cfg_ar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ar_u; + +/* Define the union csr_octl_sub_err_cfg_as_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_9 : 24; /* [23:0] */ + u32 rsv_41 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_as_u; + +/* Define the union csr_octl_sub_err_cfg_at_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_9 : 24; /* [23:0] */ + u32 rsv_42 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_at_u; + +/* Define the union csr_octl_sub_err_cfg_au_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_au_u; + +/* Define the union csr_octl_sub_err_cfg_av_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_av_u; + +/* Define the union csr_octl_sub_err_cfg_aw_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_11 : 24; /* [23:0] */ + u32 rsv_43 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_aw_u; + +/* Define the union csr_octl_sub_err_cfg_ax_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_11 : 24; /* [23:0] */ + u32 rsv_44 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ax_u; + +/* Define the union csr_octl_sub_err_cfg_ay_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ay_u; + +/* Define the union csr_octl_sub_err_cfg_az_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_az_u; + +/* Define the union csr_octl_sub_err_cfg_ba_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_13 : 24; /* [23:0] */ + u32 rsv_45 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_ba_u; + +/* Define the union csr_octl_sub_err_cfg_bb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_13 : 24; /* [23:0] */ + u32 rsv_46 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bb_u; + +/* Define the union csr_octl_sub_err_cfg_bc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bc_u; + +/* Define the union csr_octl_sub_err_cfg_bd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bd_u; + +/* Define the union csr_octl_sub_err_cfg_be_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_be_u; + +/* Define the union csr_octl_sub_err_cfg_bf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bf_u; + +/* Define the union csr_octl_sub_err_cfg_bg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bg_u; + +/* Define the union csr_octl_sub_err_cfg_bh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bh_u; + +/* Define the union csr_octl_sub_err_cfg_bi_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_fatal_mask_17 : 18; /* [17:0] */ + u32 rsv_47 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bi_u; + +/* Define the union csr_octl_sub_err_cfg_bj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_err_nonfatal_mask_17 : 18; /* [17:0] */ + u32 rsv_48 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sub_err_cfg_bj_u; + +/* Define the union csr_octl_ram_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_bypass : 1; /* [0] */ + u32 rsv_49 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_bypass_u; + +/* Define the union csr_octl_ram_ecc_inj_req_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_inj_req_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_inj_req_a_u; + +/* Define the union csr_octl_ram_ecc_inj_req_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_inj_req_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_inj_req_b_u; + +/* Define the union csr_octl_ram_ecc_inj_req_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_inj_req_2 : 2; /* [1:0] */ + u32 rsv_50 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_inj_req_c_u; + +/* Define the union csr_octl_ram_ecc_err_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_err_a_u; + +/* Define the union csr_octl_ram_ecc_err_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_err_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_err_b_u; + +/* Define the union csr_octl_ram_ecc_err_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_err_2 : 2; /* [1:0] */ + u32 rsv_51 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_ecc_err_c_u; + +/* Define the union csr_octl_ram_link_list_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cbuf_ram_head_empty : 20; /* [19:0] */ + u32 rsv_52 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_aa_u; + +/* Define the union csr_octl_ram_link_list_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cbuf_ram_sge_empty : 20; /* [19:0] */ + u32 rsv_53 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ab_u; + +/* Define the union csr_octl_ram_link_list_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cbuf_ram_app0_empty : 20; /* [19:0] */ + u32 rsv_54 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ac_u; + +/* Define the union csr_octl_ram_link_list_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cbuf_ram_app1_empty : 20; /* [19:0] */ + u32 rsv_55 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ad_u; + +/* Define the union csr_octl_ram_link_list_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_head_empty_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ae_u; + +/* Define the union csr_octl_ram_link_list_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_head_empty_1 : 24; /* [23:0] */ + u32 rsv_56 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_af_u; + +/* Define the union csr_octl_ram_link_list_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_sge_empty_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ag_u; + +/* Define the union csr_octl_ram_link_list_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_sge_empty_1 : 24; /* [23:0] */ + u32 rsv_57 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ah_u; + +/* Define the union csr_octl_ram_link_list_ai_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_app0_empty_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ai_u; + +/* Define the union csr_octl_ram_link_list_aj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_1st_app0_empty_1 : 24; /* [23:0] */ + u32 rsv_58 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_aj_u; + +/* Define the union csr_octl_ram_link_list_ak_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_2nd_app0_empty : 5; /* [4:0] */ + u32 rsv_59 : 3; /* [7:5] */ + u32 sm_cbuf_ram_2nd_sge_empty : 5; /* [12:8] */ + u32 rsv_60 : 3; /* [15:13] */ + u32 sm_cbuf_ram_2nd_head_empty : 5; /* [20:16] */ + u32 rsv_61 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ak_u; + +/* Define the union csr_octl_ram_link_list_al_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cmd_2nd_ec_ram_empty : 15; /* [14:0] */ + u32 pe_cmd_1st_ec_ram_empty : 15; /* [29:15] */ + u32 rsv_62 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_al_u; + +/* Define the union csr_octl_ram_link_list_am_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_proc_ram_empty : 10; /* [9:0] */ + u32 rsv_63 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_am_u; + +/* Define the union csr_octl_ram_link_list_an_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cbuf_ram_app0_free_cell_cnt : 10; /* [9:0] */ + u32 pe_cbuf_ram_sge_free_cell_cnt : 10; /* [19:10] */ + u32 pe_cbuf_ram_head_free_cell_cnt : 10; /* [29:20] */ + u32 rsv_64 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_an_u; + +/* Define the union csr_octl_ram_link_list_ao_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_dbuf_ram_bk1_free_cell_cnt : 10; /* [9:0] */ + u32 pe_dbuf_ram_bk0_free_cell_cnt : 10; /* [19:10] */ + u32 pe_cbuf_ram_app1_free_cell_cnt : 10; /* [29:20] */ + u32 rsv_65 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ao_u; + +/* Define the union csr_octl_ram_link_list_ap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_ram_sge_free_cell_cnt : 11; /* [10:0] */ + u32 sm_cbuf_ram_head_free_cell_cnt : 11; /* [21:11] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ap_u; + +/* Define the union csr_octl_ram_link_list_aq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_dbuf_ram_bk1_free_cell_cnt : 10; /* [9:0] */ + u32 sm_dbuf_ram_bk0_free_cell_cnt : 10; /* [19:10] */ + u32 sm_cbuf_ram_app0_free_cell_cnt : 11; /* [30:20] */ + u32 rsv_67 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_aq_u; + +/* Define the union csr_octl_ram_link_list_ar_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_proc_free_cell_cnt : 11; /* [10:0] */ + u32 pe_cmd_2nd_ec_free_cell_cnt : 7; /* [17:11] */ + u32 pe_cmd_1st_ec_free_cell_cnt : 7; /* [24:18] */ + u32 rsv_68 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ram_link_list_ar_u; + +/* Define the union csr_octl_in_bp_sig_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_cpi_src_bp_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_a_u; + +/* Define the union csr_octl_in_bp_sig_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_cpi_src_bp_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_b_u; + +/* Define the union csr_octl_in_bp_sig_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_cpi_src_bp_2 : 24; /* [23:0] */ + u32 rsv_69 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_c_u; + +/* Define the union csr_octl_in_bp_sig_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_octl_dpath_pe_bp : 20; /* [19:0] */ + u32 rsv_70 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_d_u; + +/* Define the union csr_octl_in_bp_sig_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_octl_cpath_bp : 5; /* [4:0] */ + u32 osch_octl_dpath_sm_bp : 5; /* [9:5] */ + u32 rsv_71 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_e_u; + +/* Define the union csr_octl_in_bp_sig_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cpi_dat_inc_bp : 1; /* [0] */ + u32 mqm_cpi_host_sge_inc_bp : 1; /* [1] */ + u32 mqm_cpi_ep_sge_inc_bp : 1; /* [2] */ + u32 prm_cpi_bp : 1; /* [3] */ + u32 octl_rde_sm_parser_bp : 1; /* [4] */ + u32 octl_cpi_perx_bp : 1; /* [5] */ + u32 rsv_72 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_in_bp_sig_f_u; + +/* Define the union csr_octl_fifo_st_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_fifo_overflow : 22; /* [21:0] */ + u32 rsv_73 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_st_a_u; + +/* Define the union csr_octl_fifo_st_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_fifo_underflow : 22; /* [21:0] */ + u32 rsv_74 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_st_b_u; + +/* Define the union csr_octl_fifo_st_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_fifo_empty : 25; /* [24:0] */ + u32 rsv_75 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_st_c_u; + +/* Define the union csr_octl_fifo_st_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_fifo_full : 25; /* [24:0] */ + u32 rsv_76 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_st_d_u; + +/* Define the union csr_octl_fifo_st_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqe_cmd_fifo_done_port : 5; /* [4:0] */ + u32 cp_l2nic_cqe_en_cmd_pful : 1; /* [5] */ + u32 rsv_77 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_st_e_u; + +/* Define the union csr_octl_fifo_afon_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbuf_pe_app1_afon_th : 4; /* [3:0] */ + u32 dbuf_pe_app0_afon_th : 4; /* [7:4] */ + u32 cp_l2nic_cqe_en_cmd_afon_th : 5; /* [12:8] */ + u32 smvio_fifo_afon_th : 3; /* [15:13] */ + u32 dpath_o_sfifo_afon_th : 7; /* [22:16] */ + u32 rsv_78 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_afon_a_u; + +/* Define the union csr_octl_fifo_afon_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dbuf_sm_app0_afon_th : 4; /* [3:0] */ + u32 cpb_bk1_fifo_afon_th : 6; /* [9:4] */ + u32 cpb_bk0_fifo_afon_th : 6; /* [15:10] */ + u32 cpb_adj_fifo_afon_th : 5; /* [20:16] */ + u32 pe_parser_dbuf_fifo_afon_th : 3; /* [23:21] */ + u32 pe_parser_sge_fifo_afon_th : 3; /* [26:24] */ + u32 pe_parser_head_fifo_afon_th : 3; /* [29:27] */ + u32 rsv_79 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_afon_b_u; + +/* Define the union csr_octl_fifo_afon_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge_crdt_fifo_afon_th : 6; /* [5:0] */ + u32 aad_rd_fifo_afon_th : 4; /* [9:6] */ + u32 tlp_rd_fifo_afon_th : 3; /* [12:10] */ + u32 rde_octl_fifo_afon_th : 5; /* [17:13] */ + u32 sm_parser_dbuf_fifo_afon_th : 3; /* [20:18] */ + u32 sm_parser_sge_fifo_afon_th : 3; /* [23:21] */ + u32 sm_parser_head_fifo_afon_th : 3; /* [26:24] */ + u32 dbuf_sm_app1_afon_th : 4; /* [30:27] */ + u32 rsv_80 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fifo_afon_c_u; + +/* Define the union csr_octl_err_sig_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_perx_data_err : 1; /* [0] */ + u32 rsv_81 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_aa_u; + +/* Define the union csr_octl_err_sig_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_o_loss_sop_err : 20; /* [19:0] */ + u32 rsv_82 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ab_u; + +/* Define the union csr_octl_err_sig_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_o_loss_eop_err : 20; /* [19:0] */ + u32 rsv_83 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ac_u; + +/* Define the union csr_octl_err_sig_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_o_non_vld_err : 20; /* [19:0] */ + u32 rsv_84 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ad_u; + +/* Define the union csr_octl_err_sig_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_rel_loss_sop_err : 20; /* [19:0] */ + u32 rsv_85 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ae_u; + +/* Define the union csr_octl_err_sig_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_rel_loss_eop_err : 20; /* [19:0] */ + u32 rsv_86 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_af_u; + +/* Define the union csr_octl_err_sig_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_dpath_rel_non_vld_err : 20; /* [19:0] */ + u32 rsv_87 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ag_u; + +/* Define the union csr_octl_err_sig_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_loss_sop_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ah_u; + +/* Define the union csr_octl_err_sig_ai_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_loss_sop_err_1 : 24; /* [23:0] */ + u32 rsv_88 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ai_u; + +/* Define the union csr_octl_err_sig_aj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_loss_eop_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_aj_u; + +/* Define the union csr_octl_err_sig_ak_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_loss_eop_err_1 : 24; /* [23:0] */ + u32 rsv_89 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ak_u; + +/* Define the union csr_octl_err_sig_al_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_non_vld_err_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_al_u; + +/* Define the union csr_octl_err_sig_am_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_l2nic_non_vld_err_1 : 24; /* [23:0] */ + u32 rsv_90 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_am_u; + +/* Define the union csr_octl_ec_soro_attr_tbl_first_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_vf_so_ro_0_first : 2; /* [1:0] */ + u32 octl_vf_dma_attr_offset_0_first : 6; /* [7:2] */ + u32 rsv_91 : 2; /* [9:8] */ + u32 octl_vf_so_ro_1_first : 2; /* [11:10] */ + u32 octl_vf_dma_attr_offset_1_first : 6; /* [17:12] */ + u32 rsv_92 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ec_soro_attr_tbl_first_u; + +/* Define the union csr_octl_ec_soro_attr_tbl_second_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_vf_so_ro_0_second : 2; /* [1:0] */ + u32 octl_vf_dma_attr_offset_0_second : 6; /* [7:2] */ + u32 rsv_93 : 2; /* [9:8] */ + u32 octl_vf_so_ro_1_second : 2; /* [11:10] */ + u32 octl_vf_dma_attr_offset_1_second : 6; /* [17:12] */ + u32 rsv_94 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ec_soro_attr_tbl_second_u; + +/* Define the union csr_octl_ec_channel_enable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_octl_ec_chnl_first : 5; /* [4:0] */ + u32 cpi_octl_ec_chnl_first_en : 1; /* [5] */ + u32 rsv_95 : 4; /* [9:6] */ + u32 cpi_octl_ec_chnl_second : 5; /* [14:10] */ + u32 cpi_octl_ec_chnl_second_en : 1; /* [15] */ + u32 rsv_96 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_ec_channel_enable_u; + +/* Define the union csr_octl_sm_cbuf_i_ready_chnl_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_i_ready_chnl_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sm_cbuf_i_ready_chnl_a_u; + +/* Define the union csr_octl_sm_cbuf_i_ready_chnl_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cbuf_i_ready_chnl_b : 24; /* [23:0] */ + u32 rsv_97 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_sm_cbuf_i_ready_chnl_b_u; + +/* Define the union csr_octl_mul_host_dif_rd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_mul_dif_dma_attr_offset_1 : 6; /* [5:0] */ + u32 octl_mul_dif_so_ro_1 : 2; /* [7:6] */ + u32 rsv_98 : 2; /* [9:8] */ + u32 octl_mul_dif_dma_attr_offset_0 : 6; /* [15:10] */ + u32 octl_mul_dif_so_ro_0 : 2; /* [17:16] */ + u32 cpi_octl_mul_dif_rd_chnl : 5; /* [22:18] */ + u32 cpi_octl_mul_dif_rd_chnl_en : 1; /* [23] */ + u32 rsv_99 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_mul_host_dif_rd_cfg_u; + +/* Define the union csr_octl_db_wr_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_db_wr_sge_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_db_wr_addr_l_u; + +/* Define the union csr_octl_db_wr_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_db_wr_sge_addr_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_db_wr_addr_h_u; + +/* Define the union csr_octl_endian_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_octl_ci_endian_cfg : 1; /* [0] */ + u32 cpi_octl_cqe_endian_cfg : 1; /* [1] */ + u32 rsv_100 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_endian_cfg_u; + +/* Define the union csr_octl_fsm_st_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_cur_st_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_a_u; + +/* Define the union csr_octl_fsm_st_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_cur_st_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_b_u; + +/* Define the union csr_octl_fsm_st_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_cur_st_c : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_c_u; + +/* Define the union csr_octl_fsm_st_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_cur_st_d : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_d_u; + +/* Define the union csr_octl_fsm_st_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_dpath_o_cur_st_e : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_e_u; + +/* Define the union csr_octl_fsm_st_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_ci_data_tbl_st : 12; /* [11:0] */ + u32 cur_ci_attr_tbl_st : 12; /* [23:12] */ + u32 rsv_101 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_fsm_st_f_u; + +/* Define the union csr_octl_head_storage_dfx_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_unknown_cmd_head_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_a_u; + +/* Define the union csr_octl_head_storage_dfx_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_unknown_cmd_head_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_b_u; + +/* Define the union csr_octl_head_storage_dfx_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_unknown_cmd_head_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_c_u; + +/* Define the union csr_octl_head_storage_dfx_d_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_unknown_cmd_head_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_d_u; + +/* Define the union csr_octl_head_storage_dfx_e_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_num_deficit_err_head_0 : 30; /* [29:0] */ + u32 rsv_102 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_e_u; + +/* Define the union csr_octl_head_storage_dfx_f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_num_deficit_err_head_1 : 13; /* [12:0] */ + u32 rsv_103 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_f_u; + +/* Define the union csr_octl_head_storage_dfx_g_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge0_len_err_head_0 : 30; /* [29:0] */ + u32 rsv_104 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_g_u; + +/* Define the union csr_octl_head_storage_dfx_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sge0_len_err_head_1 : 13; /* [12:0] */ + u32 rsv_105 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_h_u; + +/* Define the union csr_octl_err_sig_an_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_cpath_loss_sop_err : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_an_u; + +/* Define the union csr_octl_err_sig_ao_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_cpath_loss_eop_err : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ao_u; + +/* Define the union csr_octl_err_sig_ap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_cpath_non_vld_err : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_ap_u; + +/* Define the union csr_octl_err_sig_aq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_proc_non_vld_err : 6; /* [5:0] */ + u32 octl_proc_cpath_loss_eop_err : 6; /* [11:6] */ + u32 octl_proc_cpath_loss_sop_err : 6; /* [17:12] */ + u32 rsv_106 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_err_sig_aq_u; + +/* Define the union csr_octl_head_storage_dfx_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cmd_last_known_head_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_i_u; + +/* Define the union csr_octl_head_storage_dfx_j_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cmd_last_known_head_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_j_u; + +/* Define the union csr_octl_head_storage_dfx_k_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cmd_last_known_head_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_k_u; + +/* Define the union csr_octl_head_storage_dfx_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_cmd_last_known_head_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_l_u; + +/* Define the union csr_octl_pe_parser_cfg_1st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_num_deficit_err_en : 1; /* [0] */ + u32 sge0_len_err_en : 1; /* [1] */ + u32 pe_unknown_cmd_err_en : 1; /* [2] */ + u32 sge_len_null_en : 1; /* [3] */ + u32 cpi_octl_cqe_ci_cmd_drop_en : 1; /* [4] */ + u32 rsv_107 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_pe_parser_cfg_1st_u; + +/* Define the union csr_octl_loop_st_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pe_loop_has_packet : 1; /* [0] */ + u32 sm_l2nic_loop_has_packet : 1; /* [1] */ + u32 cpath_loop_has_packet : 1; /* [2] */ + u32 rsv_108 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_loop_st_a_u; + +/* Define the union csr_octl_loop_st_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_proc_has_packet : 1; /* [0] */ + u32 cpath_has_packet : 1; /* [1] */ + u32 sm_cmd_ctl_has_packet : 1; /* [2] */ + u32 sm_dbuf_has_packet : 1; /* [3] */ + u32 sm_cbuf_has_packet : 1; /* [4] */ + u32 sm_parser_has_packet : 1; /* [5] */ + u32 pe_cmd_ctl_has_packet : 1; /* [6] */ + u32 pe_cqe_ctl_has_packet : 1; /* [7] */ + u32 pe_dbuf_has_packet : 1; /* [8] */ + u32 pe_cbuf_has_packet : 1; /* [9] */ + u32 pe_parser_has_cpb_crdt : 1; /* [10] */ + u32 pe_parser_has_packet : 1; /* [11] */ + u32 octl_tlp_ctl_has_packet : 1; /* [12] */ + u32 octl_aad_ctl_has_packet : 1; /* [13] */ + u32 octl_dpath_o_has_packet : 1; /* [14] */ + u32 rsv_109 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_loop_st_b_u; + +/* Define the union csr_octl_dfx_sig_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_perx_max_bp_cnt : 12; /* [11:0] */ + u32 rsv_110 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_dfx_sig_a_u; + +/* Define the union csr_octl_pf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_func_idx_l : 5; /* [4:0] */ + u32 rsv_111 : 11; /* [15:5] */ + u32 pf_func_idx_h : 5; /* [20:16] */ + u32 rsv_112 : 10; /* [30:21] */ + u32 pf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_pf_range_port_u; + +/* Define the union csr_octl_vf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_func_idx_l : 12; /* [11:0] */ + u32 rsv_113 : 4; /* [15:12] */ + u32 vf_func_idx_h : 12; /* [27:16] */ + u32 rsv_114 : 3; /* [30:28] */ + u32 vf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vf_range_port_u; + +/* Define the union csr_octl_lvf_range_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lvf_func_idx_l : 12; /* [11:0] */ + u32 rsv_115 : 4; /* [15:12] */ + u32 lvf_func_idx_h : 12; /* [27:16] */ + u32 rsv_116 : 3; /* [30:28] */ + u32 lvf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_lvf_range_port_u; + +/* Define the union csr_octl_vld_sig_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_aa_u; + +/* Define the union csr_octl_vld_sig_ab_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ab_u; + +/* Define the union csr_octl_vld_sig_ac_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ac_u; + +/* Define the union csr_octl_vld_sig_ad_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ad_u; + +/* Define the union csr_octl_vld_sig_ae_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ae_u; + +/* Define the union csr_octl_vld_sig_af_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_af_u; + +/* Define the union csr_octl_vld_sig_ag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ag_u; + +/* Define the union csr_octl_vld_sig_ah_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_inside_data_vld_7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_vld_sig_ah_u; + +/* Define the union csr_cpi_octl_cpath_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icpl_sm_crdt_num : 9; /* [8:0] */ + u32 rsv_117 : 1; /* [9] */ + u32 icpl_vio_crdt_num : 10; /* [19:10] */ + u32 osch_host_crdt_num : 8; /* [27:20] */ + u32 cpi_cpath_proc_bypass : 1; /* [28] */ + u32 rsv_118 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_octl_cpath_crdt_u; + +/* Define the union csr_ctrl_bus_cfg_one_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_bus_one : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_bus_cfg_one_u; + +/* Define the union csr_ctrl_bus_cfg_two_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_bus_two : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_bus_cfg_two_u; + +/* Define the union csr_ctrl_bus_cfg_three_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_bus_three : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_bus_cfg_three_u; + +/* Define the union csr_ctrl_bus_cfg_four_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_bus_four : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_bus_cfg_four_u; + +/* Define the union csr_ctrl_bus_cfg_five_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_bus_five : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctrl_bus_cfg_five_u; + +/* Define the union csr_bak_for_eco_aa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bak_for_eco_b : 16; /* [15:0] */ + u32 bak_for_eco_a : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bak_for_eco_aa_u; + +/* Define the union csr_bak_for_eco_bb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bak_for_eco_d : 16; /* [15:0] */ + u32 bak_for_eco_c : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bak_for_eco_bb_u; + +/* Define the union csr_octl_head_storage_dfx_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perxin_unknown_cmd_head_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_m_u; + +/* Define the union csr_octl_head_storage_dfx_n_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perxin_unknown_cmd_head_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_n_u; + +/* Define the union csr_octl_head_storage_dfx_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perxin_unknown_cmd_head_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_o_u; + +/* Define the union csr_octl_head_storage_dfx_p_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perxin_unknown_cmd_head_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_octl_head_storage_dfx_p_u; + +/* Define the union csr_bak_for_eco_cc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bak_for_eco_f : 16; /* [15:0] */ + u32 bak_for_eco_e : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bak_for_eco_cc_u; + +/* Define the union csr_bak_for_eco_dd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bak_for_eco_h : 16; /* [15:0] */ + u32 bak_for_eco_g : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bak_for_eco_dd_u; + +/* Define the union csr_bak_for_eco_ee_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bak_for_eco_j : 16; /* [15:0] */ + u32 bak_for_eco_i : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_bak_for_eco_ee_u; + +/* Define the union csr_cpi_sm_chl_cfg_en_a_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_sm_chl_cfg_en_a : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_sm_chl_cfg_en_a_u; + +/* Define the union csr_cpi_sm_chl_cfg_en_b_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_sm_chl_cfg_en_b : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_sm_chl_cfg_en_b_u; + +/* Define the union csr_cpi_octl_mul_wr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 octl_mul_wr_dma_attr_offset : 6; /* [5:0] */ + u32 rsv_119 : 2; /* [7:6] */ + u32 octl_mul_wr_so_ro : 2; /* [9:8] */ + u32 rsv_120 : 2; /* [11:10] */ + u32 octl_mul_wr_soro_attr_en : 1; /* [12] */ + u32 rsv_121 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_octl_mul_wr_cfg_u; + +/* Define the union csr_cpi_octl_cqe_ctl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cqe_cmd_fifo_alfull_gap : 11; /* [10:0] */ + u32 rsv_122 : 1; /* [11] */ + u32 l2nic_ci_force_update : 1; /* [12] */ + u32 rsv_123 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_octl_cqe_ctl_cfg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_octl_tbl_indir_ctrl0_u octl_tbl_indir_ctrl0; /* 0 */ + volatile csr_octl_tbl_indir_ctrl1_u octl_tbl_indir_ctrl1; /* 4 */ + volatile csr_octl_tbl_indir_data_u octl_tbl_indir_data[8]; /* 8 */ + volatile csr_octl_ram_init_req_u octl_ram_init_req; /* 28 */ + volatile csr_octl_ram_init_sts_u octl_ram_init_sts; /* 2C */ + volatile csr_pre_sub_dat_crd_cpb_u pre_sub_dat_crd_cpb; /* 30 */ + volatile csr_l2nic_ci_wr_chl_cfg_u l2nic_ci_wr_chl_cfg; /* 34 */ + volatile csr_cqe_wr_chl_cfg_u cqe_wr_chl_cfg; /* 38 */ + volatile csr_pcie_port_cfg_u pcie_port_cfg; /* 3C */ + volatile csr_dma_pe_yyy_fifo_depth_port012_u dma_pe_yyy_fifo_depth_port012; /* 40 */ + volatile csr_dma_pe_yyy_fifo_depth_port34_u dma_pe_yyy_fifo_depth_port34; /* 44 */ + volatile csr_cpi_prealloc_cpb_buf_u cpi_prealloc_cpb_buf; /* 48 */ + volatile csr_cpi_sm_chl_cfg_u cpi_sm_chl_cfg[16]; /* 4C */ + volatile csr_octl_cut_thr_cfg_u octl_cut_thr_cfg; /* 8C */ + volatile csr_octl_in_cmd_chnl_src_sel_u octl_in_cmd_chnl_src_sel; /* 94 */ + volatile csr_octl_err_detect_reg_a_u octl_err_detect_reg_a; /* 98 */ + volatile csr_octl_err_detect_reg_b_u octl_err_detect_reg_b; /* 9C */ + volatile csr_octl_err_detect_ro_reg_a_u octl_err_detect_ro_reg_a; /* A0 */ + volatile csr_octl_err_detect_ro_reg_b_u octl_err_detect_ro_reg_b; /* A4 */ + volatile csr_octl_err_detect_ro_reg_c_u octl_err_detect_ro_reg_c; /* A8 */ + volatile csr_octl_err_detect_ro_reg_d_u octl_err_detect_ro_reg_d; /* AC */ + volatile csr_octl_cmd_cnt_a_u octl_cmd_cnt_a; /* B0 */ + volatile csr_octl_cmd_cnt_b_u octl_cmd_cnt_b; /* B4 */ + volatile csr_octl_cmd_cnt_c_u octl_cmd_cnt_c; /* B8 */ + volatile csr_octl_cmd_cnt_d_u octl_cmd_cnt_d; /* BC */ + volatile csr_octl_cmd_cnt_e_u octl_cmd_cnt_e; /* C0 */ + volatile csr_octl_cmd_cnt_f_u octl_cmd_cnt_f; /* C4 */ + volatile csr_octl_cmd_cnt_g_u octl_cmd_cnt_g; /* C8 */ + volatile csr_octl_cmd_cnt_h_u octl_cmd_cnt_h; /* CC */ + volatile csr_octl_cmd_cnt_i_u octl_cmd_cnt_i; /* D0 */ + volatile csr_octl_cmd_cnt_j_u octl_cmd_cnt_j; /* D4 */ + volatile csr_octl_cmd_cnt_k_u octl_cmd_cnt_k; /* D8 */ + volatile csr_octl_cmd_cnt_l_u octl_cmd_cnt_l; /* DC */ + volatile csr_octl_cmd_cnt_m_u octl_cmd_cnt_m; /* E0 */ + volatile csr_octl_cmd_cnt_n_u octl_cmd_cnt_n; /* E4 */ + volatile csr_octl_cmd_cnt_o_u octl_cmd_cnt_o; /* E8 */ + volatile csr_octl_cmd_cnt_p_u octl_cmd_cnt_p; /* EC */ + volatile csr_octl_cmd_cnt_q_u octl_cmd_cnt_q; /* F0 */ + volatile csr_octl_cmd_cnt_r_u octl_cmd_cnt_r; /* F4 */ + volatile csr_octl_cmd_cnt_s_u octl_cmd_cnt_s; /* F8 */ + volatile csr_octl_cmd_cnt_t_u octl_cmd_cnt_t; /* FC */ + volatile csr_octl_cmd_cnt_u_u octl_cmd_cnt_u; /* 100 */ + volatile csr_octl_cmd_cnt_v_u octl_cmd_cnt_v; /* 104 */ + volatile csr_octl_cmd_cnt_w_u octl_cmd_cnt_w; /* 108 */ + volatile csr_octl_cmd_cnt_x_u octl_cmd_cnt_x; /* 10C */ + volatile csr_octl_cmd_cnt_y_u octl_cmd_cnt_y; /* 110 */ + volatile csr_octl_cmd_cnt_z_u octl_cmd_cnt_z; /* 114 */ + volatile csr_octl_cmd_cnt_aa_u octl_cmd_cnt_aa; /* 118 */ + volatile csr_octl_cmd_cnt_ab_u octl_cmd_cnt_ab; /* 11C */ + volatile csr_octl_cmd_cnt_ac_u octl_cmd_cnt_ac; /* 120 */ + volatile csr_octl_cmd_cnt_ad_u octl_cmd_cnt_ad; /* 124 */ + volatile csr_octl_cmd_cnt_ae_u octl_cmd_cnt_ae; /* 128 */ + volatile csr_octl_cmd_cnt_af_u octl_cmd_cnt_af; /* 12C */ + volatile csr_octl_cmd_cnt_ag_u octl_cmd_cnt_ag; /* 130 */ + volatile csr_octl_cmd_cnt_ah_u octl_cmd_cnt_ah; /* 134 */ + volatile csr_octl_cmd_cnt_ai_u octl_cmd_cnt_ai; /* 138 */ + volatile csr_octl_cmd_cnt_aj_u octl_cmd_cnt_aj; /* 13C */ + volatile csr_octl_cmd_cnt_ak_u octl_cmd_cnt_ak; /* 140 */ + volatile csr_octl_cmd_cnt_al_u octl_cmd_cnt_al; /* 144 */ + volatile csr_octl_cmd_cnt_am_u octl_cmd_cnt_am; /* 148 */ + volatile csr_octl_cmd_cnt_an_u octl_cmd_cnt_an; /* 14C */ + volatile csr_octl_cmd_cnt_ao_u octl_cmd_cnt_ao; /* 150 */ + volatile csr_octl_cmd_cnt_ap_u octl_cmd_cnt_ap; /* 154 */ + volatile csr_octl_cmd_cnt_aq_u octl_cmd_cnt_aq; /* 158 */ + volatile csr_octl_cmd_cnt_ar_u octl_cmd_cnt_ar; /* 15C */ + volatile csr_octl_cmd_cnt_as_u octl_cmd_cnt_as; /* 160 */ + volatile csr_octl_cmd_cnt_at_u octl_cmd_cnt_at; /* 164 */ + volatile csr_octl_cmd_cnt_au_u octl_cmd_cnt_au; /* 168 */ + volatile csr_octl_cmd_cnt_av_u octl_cmd_cnt_av; /* 16C */ + volatile csr_octl_cmd_cnt_aw_u octl_cmd_cnt_aw; /* 170 */ + volatile csr_octl_cmd_cnt_ax_u octl_cmd_cnt_ax; /* 174 */ + volatile csr_octl_cmd_cnt_ay_u octl_cmd_cnt_ay; /* 178 */ + volatile csr_octl_cmd_cnt_az_u octl_cmd_cnt_az; /* 17C */ + volatile csr_octl_cmd_cnt_ba_u octl_cmd_cnt_ba; /* 180 */ + volatile csr_octl_cmd_cnt_bb_u octl_cmd_cnt_bb; /* 184 */ + volatile csr_octl_cmd_cnt_bc_u octl_cmd_cnt_bc; /* 188 */ + volatile csr_octl_cmd_port_aa_u octl_cmd_port_aa[5]; /* 1A0 */ + volatile csr_octl_cmd_port_ab_u octl_cmd_port_ab[5]; /* 1A4 */ + volatile csr_octl_cmd_port_ac_u octl_cmd_port_ac[5]; /* 1A8 */ + volatile csr_octl_cmd_port_ad_u octl_cmd_port_ad[5]; /* 1AC */ + volatile csr_octl_cmd_port_ae_u octl_cmd_port_ae[5]; /* 1B0 */ + volatile csr_octl_cmd_port_af_u octl_cmd_port_af[5]; /* 1B4 */ + volatile csr_octl_cmd_port_ag_u octl_cmd_port_ag[5]; /* 1B8 */ + volatile csr_octl_cmd_port_ah_u octl_cmd_port_ah[5]; /* 1BC */ + volatile csr_octl_cmd_port_ai_u octl_cmd_port_ai[5]; /* 1C0 */ + volatile csr_octl_cmd_port_aj_u octl_cmd_port_aj[5]; /* 1C4 */ + volatile csr_octl_cmd_port_ak_u octl_cmd_port_ak[5]; /* 1C8 */ + volatile csr_octl_cmd_port_al_u octl_cmd_port_al[5]; /* 1CC */ + volatile csr_octl_cmd_port_am_u octl_cmd_port_am[5]; /* 1D0 */ + volatile csr_octl_cmd_port_an_u octl_cmd_port_an[5]; /* 1D4 */ + volatile csr_octl_cmd_cnt_bd_u octl_cmd_cnt_bd; /* 300 */ + volatile csr_octl_cmd_cnt_be_u octl_cmd_cnt_be; /* 304 */ + volatile csr_octl_cmd_cnt_bf_u octl_cmd_cnt_bf; /* 308 */ + volatile csr_octl_cmd_cnt_bg_u octl_cmd_cnt_bg; /* 30C */ + volatile csr_octl_cmd_cnt_bh_u octl_cmd_cnt_bh; /* 310 */ + volatile csr_octl_dpath_o_err_dfx_u octl_dpath_o_err_dfx; /* 340 */ + volatile csr_octl_sub_err_cfg_bk_u octl_sub_err_cfg_bk; /* 350 */ + volatile csr_octl_sub_err_cfg_bl_u octl_sub_err_cfg_bl; /* 354 */ + volatile csr_octl_sub_err_cfg_aa_u octl_sub_err_cfg_aa; /* 358 */ + volatile csr_octl_sub_err_cfg_ab_u octl_sub_err_cfg_ab; /* 35C */ + volatile csr_octl_sub_err_cfg_ac_u octl_sub_err_cfg_ac; /* 360 */ + volatile csr_octl_sub_err_cfg_ad_u octl_sub_err_cfg_ad; /* 364 */ + volatile csr_octl_sub_err_cfg_ae_u octl_sub_err_cfg_ae; /* 368 */ + volatile csr_octl_sub_err_cfg_af_u octl_sub_err_cfg_af; /* 36C */ + volatile csr_octl_sub_err_cfg_ag_u octl_sub_err_cfg_ag; /* 370 */ + volatile csr_octl_sub_err_cfg_ah_u octl_sub_err_cfg_ah; /* 374 */ + volatile csr_octl_sub_err_cfg_ai_u octl_sub_err_cfg_ai; /* 378 */ + volatile csr_octl_sub_err_cfg_aj_u octl_sub_err_cfg_aj; /* 37C */ + volatile csr_octl_sub_err_cfg_ak_u octl_sub_err_cfg_ak; /* 380 */ + volatile csr_octl_sub_err_cfg_al_u octl_sub_err_cfg_al; /* 384 */ + volatile csr_octl_sub_err_cfg_am_u octl_sub_err_cfg_am; /* 388 */ + volatile csr_octl_sub_err_cfg_an_u octl_sub_err_cfg_an; /* 38C */ + volatile csr_octl_sub_err_cfg_ao_u octl_sub_err_cfg_ao; /* 390 */ + volatile csr_octl_sub_err_cfg_ap_u octl_sub_err_cfg_ap; /* 394 */ + volatile csr_octl_sub_err_cfg_aq_u octl_sub_err_cfg_aq; /* 398 */ + volatile csr_octl_sub_err_cfg_ar_u octl_sub_err_cfg_ar; /* 39C */ + volatile csr_octl_sub_err_cfg_as_u octl_sub_err_cfg_as; /* 3A0 */ + volatile csr_octl_sub_err_cfg_at_u octl_sub_err_cfg_at; /* 3A4 */ + volatile csr_octl_sub_err_cfg_au_u octl_sub_err_cfg_au; /* 3A8 */ + volatile csr_octl_sub_err_cfg_av_u octl_sub_err_cfg_av; /* 3AC */ + volatile csr_octl_sub_err_cfg_aw_u octl_sub_err_cfg_aw; /* 3B0 */ + volatile csr_octl_sub_err_cfg_ax_u octl_sub_err_cfg_ax; /* 3B4 */ + volatile csr_octl_sub_err_cfg_ay_u octl_sub_err_cfg_ay; /* 3B8 */ + volatile csr_octl_sub_err_cfg_az_u octl_sub_err_cfg_az; /* 3BC */ + volatile csr_octl_sub_err_cfg_ba_u octl_sub_err_cfg_ba; /* 3C0 */ + volatile csr_octl_sub_err_cfg_bb_u octl_sub_err_cfg_bb; /* 3C4 */ + volatile csr_octl_sub_err_cfg_bc_u octl_sub_err_cfg_bc; /* 3C8 */ + volatile csr_octl_sub_err_cfg_bd_u octl_sub_err_cfg_bd; /* 3CC */ + volatile csr_octl_sub_err_cfg_be_u octl_sub_err_cfg_be; /* 3D0 */ + volatile csr_octl_sub_err_cfg_bf_u octl_sub_err_cfg_bf; /* 3D4 */ + volatile csr_octl_sub_err_cfg_bg_u octl_sub_err_cfg_bg; /* 3D8 */ + volatile csr_octl_sub_err_cfg_bh_u octl_sub_err_cfg_bh; /* 3DC */ + volatile csr_octl_sub_err_cfg_bi_u octl_sub_err_cfg_bi; /* 3E0 */ + volatile csr_octl_sub_err_cfg_bj_u octl_sub_err_cfg_bj; /* 3E4 */ + volatile csr_octl_ram_ecc_bypass_u octl_ram_ecc_bypass; /* 3F8 */ + volatile csr_octl_ram_ecc_inj_req_a_u octl_ram_ecc_inj_req_a; /* 3FC */ + volatile csr_octl_ram_ecc_inj_req_b_u octl_ram_ecc_inj_req_b; /* 400 */ + volatile csr_octl_ram_ecc_inj_req_c_u octl_ram_ecc_inj_req_c; /* 404 */ + volatile csr_octl_ram_ecc_err_a_u octl_ram_ecc_err_a; /* 408 */ + volatile csr_octl_ram_ecc_err_b_u octl_ram_ecc_err_b; /* 40C */ + volatile csr_octl_ram_ecc_err_c_u octl_ram_ecc_err_c; /* 410 */ + volatile csr_octl_ram_link_list_aa_u octl_ram_link_list_aa; /* 414 */ + volatile csr_octl_ram_link_list_ab_u octl_ram_link_list_ab; /* 418 */ + volatile csr_octl_ram_link_list_ac_u octl_ram_link_list_ac; /* 41C */ + volatile csr_octl_ram_link_list_ad_u octl_ram_link_list_ad; /* 420 */ + volatile csr_octl_ram_link_list_ae_u octl_ram_link_list_ae; /* 424 */ + volatile csr_octl_ram_link_list_af_u octl_ram_link_list_af; /* 428 */ + volatile csr_octl_ram_link_list_ag_u octl_ram_link_list_ag; /* 42C */ + volatile csr_octl_ram_link_list_ah_u octl_ram_link_list_ah; /* 430 */ + volatile csr_octl_ram_link_list_ai_u octl_ram_link_list_ai; /* 434 */ + volatile csr_octl_ram_link_list_aj_u octl_ram_link_list_aj; /* 438 */ + volatile csr_octl_ram_link_list_ak_u octl_ram_link_list_ak; /* 43C */ + volatile csr_octl_ram_link_list_al_u octl_ram_link_list_al; /* 440 */ + volatile csr_octl_ram_link_list_am_u octl_ram_link_list_am; /* 444 */ + volatile csr_octl_ram_link_list_an_u octl_ram_link_list_an; /* 448 */ + volatile csr_octl_ram_link_list_ao_u octl_ram_link_list_ao; /* 44C */ + volatile csr_octl_ram_link_list_ap_u octl_ram_link_list_ap; /* 450 */ + volatile csr_octl_ram_link_list_aq_u octl_ram_link_list_aq; /* 454 */ + volatile csr_octl_ram_link_list_ar_u octl_ram_link_list_ar; /* 458 */ + volatile csr_octl_in_bp_sig_a_u octl_in_bp_sig_a; /* 45C */ + volatile csr_octl_in_bp_sig_b_u octl_in_bp_sig_b; /* 460 */ + volatile csr_octl_in_bp_sig_c_u octl_in_bp_sig_c; /* 464 */ + volatile csr_octl_in_bp_sig_d_u octl_in_bp_sig_d; /* 468 */ + volatile csr_octl_in_bp_sig_e_u octl_in_bp_sig_e; /* 46C */ + volatile csr_octl_in_bp_sig_f_u octl_in_bp_sig_f; /* 470 */ + volatile csr_octl_fifo_st_a_u octl_fifo_st_a; /* 474 */ + volatile csr_octl_fifo_st_b_u octl_fifo_st_b; /* 478 */ + volatile csr_octl_fifo_st_c_u octl_fifo_st_c; /* 47C */ + volatile csr_octl_fifo_st_d_u octl_fifo_st_d; /* 480 */ + volatile csr_octl_fifo_st_e_u octl_fifo_st_e; /* 484 */ + volatile csr_octl_fifo_afon_a_u octl_fifo_afon_a; /* 488 */ + volatile csr_octl_fifo_afon_b_u octl_fifo_afon_b; /* 48C */ + volatile csr_octl_fifo_afon_c_u octl_fifo_afon_c; /* 490 */ + volatile csr_octl_err_sig_aa_u octl_err_sig_aa; /* 4A0 */ + volatile csr_octl_err_sig_ab_u octl_err_sig_ab; /* 4A4 */ + volatile csr_octl_err_sig_ac_u octl_err_sig_ac; /* 4A8 */ + volatile csr_octl_err_sig_ad_u octl_err_sig_ad; /* 4AC */ + volatile csr_octl_err_sig_ae_u octl_err_sig_ae; /* 4B0 */ + volatile csr_octl_err_sig_af_u octl_err_sig_af; /* 4B4 */ + volatile csr_octl_err_sig_ag_u octl_err_sig_ag; /* 4B8 */ + volatile csr_octl_err_sig_ah_u octl_err_sig_ah; /* 4BC */ + volatile csr_octl_err_sig_ai_u octl_err_sig_ai; /* 4C0 */ + volatile csr_octl_err_sig_aj_u octl_err_sig_aj; /* 4C4 */ + volatile csr_octl_err_sig_ak_u octl_err_sig_ak; /* 4C8 */ + volatile csr_octl_err_sig_al_u octl_err_sig_al; /* 4CC */ + volatile csr_octl_err_sig_am_u octl_err_sig_am; /* 4D0 */ + volatile csr_octl_ec_soro_attr_tbl_first_u octl_ec_soro_attr_tbl_first; /* 4E4 */ + volatile csr_octl_ec_soro_attr_tbl_second_u octl_ec_soro_attr_tbl_second; /* 4E8 */ + volatile csr_octl_ec_channel_enable_u octl_ec_channel_enable; /* 4EC */ + volatile csr_octl_sm_cbuf_i_ready_chnl_a_u octl_sm_cbuf_i_ready_chnl_a; /* 4F0 */ + volatile csr_octl_sm_cbuf_i_ready_chnl_b_u octl_sm_cbuf_i_ready_chnl_b; /* 4F4 */ + volatile csr_octl_mul_host_dif_rd_cfg_u octl_mul_host_dif_rd_cfg; /* 4F8 */ + volatile csr_octl_db_wr_addr_l_u octl_db_wr_addr_l; /* 4FC */ + volatile csr_octl_db_wr_addr_h_u octl_db_wr_addr_h; /* 500 */ + volatile csr_octl_endian_cfg_u octl_endian_cfg; /* 504 */ + volatile csr_octl_fsm_st_a_u octl_fsm_st_a; /* 560 */ + volatile csr_octl_fsm_st_b_u octl_fsm_st_b; /* 564 */ + volatile csr_octl_fsm_st_c_u octl_fsm_st_c; /* 568 */ + volatile csr_octl_fsm_st_d_u octl_fsm_st_d; /* 56C */ + volatile csr_octl_fsm_st_e_u octl_fsm_st_e; /* 570 */ + volatile csr_octl_fsm_st_f_u octl_fsm_st_f; /* 574 */ + volatile csr_octl_head_storage_dfx_a_u octl_head_storage_dfx_a; /* 578 */ + volatile csr_octl_head_storage_dfx_b_u octl_head_storage_dfx_b; /* 57C */ + volatile csr_octl_head_storage_dfx_c_u octl_head_storage_dfx_c; /* 580 */ + volatile csr_octl_head_storage_dfx_d_u octl_head_storage_dfx_d; /* 584 */ + volatile csr_octl_head_storage_dfx_e_u octl_head_storage_dfx_e; /* 588 */ + volatile csr_octl_head_storage_dfx_f_u octl_head_storage_dfx_f; /* 58C */ + volatile csr_octl_head_storage_dfx_g_u octl_head_storage_dfx_g; /* 590 */ + volatile csr_octl_head_storage_dfx_h_u octl_head_storage_dfx_h; /* 594 */ + volatile csr_octl_err_sig_an_u octl_err_sig_an; /* 598 */ + volatile csr_octl_err_sig_ao_u octl_err_sig_ao; /* 59C */ + volatile csr_octl_err_sig_ap_u octl_err_sig_ap; /* 5A0 */ + volatile csr_octl_err_sig_aq_u octl_err_sig_aq; /* 5A4 */ + volatile csr_octl_head_storage_dfx_i_u octl_head_storage_dfx_i; /* 5A8 */ + volatile csr_octl_head_storage_dfx_j_u octl_head_storage_dfx_j; /* 5AC */ + volatile csr_octl_head_storage_dfx_k_u octl_head_storage_dfx_k; /* 5B0 */ + volatile csr_octl_head_storage_dfx_l_u octl_head_storage_dfx_l; /* 5B4 */ + volatile csr_octl_pe_parser_cfg_1st_u octl_pe_parser_cfg_1st; /* 650 */ + volatile csr_octl_loop_st_a_u octl_loop_st_a; /* 654 */ + volatile csr_octl_loop_st_b_u octl_loop_st_b; /* 658 */ + volatile csr_octl_dfx_sig_a_u octl_dfx_sig_a; /* 65C */ + volatile csr_octl_pf_range_port_u octl_pf_range_port[5]; /* 674 */ + volatile csr_octl_vf_range_port_u octl_vf_range_port[5]; /* 678 */ + volatile csr_octl_lvf_range_port_u octl_lvf_range_port[5]; /* 67C */ + volatile csr_octl_vld_sig_aa_u octl_vld_sig_aa; /* 6C0 */ + volatile csr_octl_vld_sig_ab_u octl_vld_sig_ab; /* 6C4 */ + volatile csr_octl_vld_sig_ac_u octl_vld_sig_ac; /* 6C8 */ + volatile csr_octl_vld_sig_ad_u octl_vld_sig_ad; /* 6CC */ + volatile csr_octl_vld_sig_ae_u octl_vld_sig_ae; /* 6D0 */ + volatile csr_octl_vld_sig_af_u octl_vld_sig_af; /* 6D4 */ + volatile csr_octl_vld_sig_ag_u octl_vld_sig_ag; /* 6D8 */ + volatile csr_octl_vld_sig_ah_u octl_vld_sig_ah; /* 6DC */ + volatile csr_cpi_octl_cpath_crdt_u cpi_octl_cpath_crdt; /* 718 */ + volatile csr_ctrl_bus_cfg_one_u ctrl_bus_cfg_one; /* 71C */ + volatile csr_ctrl_bus_cfg_two_u ctrl_bus_cfg_two; /* 720 */ + volatile csr_ctrl_bus_cfg_three_u ctrl_bus_cfg_three; /* 724 */ + volatile csr_ctrl_bus_cfg_four_u ctrl_bus_cfg_four; /* 728 */ + volatile csr_ctrl_bus_cfg_five_u ctrl_bus_cfg_five; /* 72C */ + volatile csr_bak_for_eco_aa_u bak_for_eco_aa; /* 730 */ + volatile csr_bak_for_eco_bb_u bak_for_eco_bb; /* 734 */ + volatile csr_octl_head_storage_dfx_m_u octl_head_storage_dfx_m; /* 738 */ + volatile csr_octl_head_storage_dfx_n_u octl_head_storage_dfx_n; /* 73C */ + volatile csr_octl_head_storage_dfx_o_u octl_head_storage_dfx_o; /* 740 */ + volatile csr_octl_head_storage_dfx_p_u octl_head_storage_dfx_p; /* 744 */ + volatile csr_bak_for_eco_cc_u bak_for_eco_cc; /* 748 */ + volatile csr_bak_for_eco_dd_u bak_for_eco_dd; /* 74C */ + volatile csr_bak_for_eco_ee_u bak_for_eco_ee; /* 750 */ + volatile csr_cpi_sm_chl_cfg_en_a_u cpi_sm_chl_cfg_en_a; /* 754 */ + volatile csr_cpi_sm_chl_cfg_en_b_u cpi_sm_chl_cfg_en_b; /* 758 */ + volatile csr_cpi_octl_mul_wr_cfg_u cpi_octl_mul_wr_cfg; /* 75C */ + volatile csr_cpi_octl_cqe_ctl_cfg_u cpi_octl_cqe_ctl_cfg; /* 760 */ +} S_cpi_octl_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cpi_octl_csr */ +extern volatile S_cpi_octl_csr_REGS_TYPE *gopcpi_octl_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetOCTL_TBL_INDIR_CTRL0_octl_tbl_indir_addr(unsigned int uoctl_tbl_indir_addr); +int iSetOCTL_TBL_INDIR_CTRL0_octl_tbl_indir_tab(unsigned int uoctl_tbl_indir_tab); +int iSetOCTL_TBL_INDIR_CTRL0_octl_tbl_indir_stat(unsigned int uoctl_tbl_indir_stat); +int iSetOCTL_TBL_INDIR_CTRL0_octl_tbl_indir_mode(unsigned int uoctl_tbl_indir_mode); +int iSetOCTL_TBL_INDIR_CTRL0_octl_tbl_indir_vld(unsigned int uoctl_tbl_indir_vld); +int iSetOCTL_TBL_INDIR_CTRL1_octl_tbl_indir_timeout(unsigned int uoctl_tbl_indir_timeout); +int iSetOCTL_TBL_INDIR_DATA_octl_tbl_indir_data(unsigned int uoctl_tbl_indir_data); +int iSetOCTL_RAM_INIT_REQ_octl_ram_ini_req(unsigned int uoctl_ram_ini_req); +int iSetOCTL_RAM_INIT_STS_octl_ram_ini_sts(unsigned int uoctl_ram_ini_sts); +int iSetPRE_SUB_DAT_CRD_CPB_cpb_presub_data_crdt(unsigned int ucpb_presub_data_crdt); +int iSetL2NIC_CI_WR_CHL_CFG_l2nic_ci_wr_chl_port0(unsigned int ul2nic_ci_wr_chl_port0); +int iSetL2NIC_CI_WR_CHL_CFG_l2nic_ci_wr_chl_port1(unsigned int ul2nic_ci_wr_chl_port1); +int iSetL2NIC_CI_WR_CHL_CFG_l2nic_ci_wr_chl_port2(unsigned int ul2nic_ci_wr_chl_port2); +int iSetL2NIC_CI_WR_CHL_CFG_l2nic_ci_wr_chl_port3(unsigned int ul2nic_ci_wr_chl_port3); +int iSetL2NIC_CI_WR_CHL_CFG_l2nic_ci_wr_chl_port4(unsigned int ul2nic_ci_wr_chl_port4); +int iSetCQE_WR_CHL_CFG_cqe_wr_chl_port0(unsigned int ucqe_wr_chl_port0); +int iSetCQE_WR_CHL_CFG_cqe_wr_chl_port1(unsigned int ucqe_wr_chl_port1); +int iSetCQE_WR_CHL_CFG_cqe_wr_chl_port2(unsigned int ucqe_wr_chl_port2); +int iSetCQE_WR_CHL_CFG_cqe_wr_chl_port3(unsigned int ucqe_wr_chl_port3); +int iSetCQE_WR_CHL_CFG_cqe_wr_chl_port4(unsigned int ucqe_wr_chl_port4); +int iSetPCIE_PORT_CFG_pcie_port_cfg(unsigned int upcie_port_cfg); +int iSetDMA_PE_YYY_FIFO_DEPTH_PORT012_port0_dma_pe_yyy_fifo_depth_cfg(unsigned int uport0_dma_pe_yyy_fifo_depth_cfg); +int iSetDMA_PE_YYY_FIFO_DEPTH_PORT012_port1_dma_pe_yyy_fifo_depth_cfg(unsigned int uport1_dma_pe_yyy_fifo_depth_cfg); +int iSetDMA_PE_YYY_FIFO_DEPTH_PORT012_port2_dma_pe_yyy_fifo_depth_cfg(unsigned int uport2_dma_pe_yyy_fifo_depth_cfg); +int iSetDMA_PE_YYY_FIFO_DEPTH_PORT34_port3_dma_pe_yyy_fifo_depth_cfg(unsigned int uport3_dma_pe_yyy_fifo_depth_cfg); +int iSetDMA_PE_YYY_FIFO_DEPTH_PORT34_port4_dma_pe_yyy_fifo_depth_cfg(unsigned int uport4_dma_pe_yyy_fifo_depth_cfg); +int iSetCPI_PREALLOC_CPB_BUF_cpb_cell_prealloc_cfg(unsigned int ucpb_cell_prealloc_cfg); +int iSetCPI_PREALLOC_CPB_BUF_cpb_cell_prealloc_adj(unsigned int ucpb_cell_prealloc_adj); +int iSetCPI_PREALLOC_CPB_BUF_cpb_cell_prealloc_thd(unsigned int ucpb_cell_prealloc_thd); +int iSetCPI_SM_CHL_CFG_cpi_sm_chl_cfg0(unsigned int ucpi_sm_chl_cfg0); +int iSetCPI_SM_CHL_CFG_cpi_sm_chl_cfg1(unsigned int ucpi_sm_chl_cfg1); +int iSetCPI_SM_CHL_CFG_cpi_sm_chl_cfg2(unsigned int ucpi_sm_chl_cfg2); +int iSetCPI_SM_CHL_CFG_cpi_sm_chl_cfg3(unsigned int ucpi_sm_chl_cfg3); +int iSetOCTL_CUT_THR_CFG_dma_pe_wdat_cut_through(unsigned int udma_pe_wdat_cut_through); +int iSetOCTL_CUT_THR_CFG_cpath_wdat_cut_through(unsigned int ucpath_wdat_cut_through); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_octl_mem_err_addr_sel(unsigned int uoctl_mem_err_addr_sel); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_perx_cmd_cnt_chnl_sel(unsigned int uperx_cmd_cnt_chnl_sel); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_perx_cmd_cnt_out_grain_cfg(unsigned int uperx_cmd_cnt_out_grain_cfg); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_perx_cmd_cnt_in_or_out_cfg(unsigned int uperx_cmd_cnt_in_or_out_cfg); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_l2nic_cmd_cnt_chnl_sel(unsigned int ul2nic_cmd_cnt_chnl_sel); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_l2nic_cmd_cnt_out_grain_cfg(unsigned int ul2nic_cmd_cnt_out_grain_cfg); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_l2nic_cmd_cnt_in_or_out_cfg(unsigned int ul2nic_cmd_cnt_in_or_out_cfg); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_sm_cp_cmd_src_sel(unsigned int usm_cp_cmd_src_sel); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_cpath_cmd_cnt_in_or_out_cfg(unsigned int ucpath_cmd_cnt_in_or_out_cfg); +int iSetOCTL_IN_CMD_CHNL_SRC_SEL_sm_cp_proc_cmd_src_sel(unsigned int usm_cp_proc_cmd_src_sel); +int iSetOCTL_ERR_DETECT_REG_A_cpi_octl_fatal_err(unsigned int ucpi_octl_fatal_err); +int iSetOCTL_ERR_DETECT_REG_A_cpi_octl_nonfatal_err(unsigned int ucpi_octl_nonfatal_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_mem_ecc_merr_all(unsigned int uoctl_mem_ecc_merr_all); +int iSetOCTL_ERR_DETECT_REG_A_octl_mem_ecc_err_all(unsigned int uoctl_mem_ecc_err_all); +int iSetOCTL_ERR_DETECT_REG_A_proc_cpath_data_err(unsigned int uproc_cpath_data_err); +int iSetOCTL_ERR_DETECT_REG_A_sm_cpath_data_err(unsigned int usm_cpath_data_err); +int iSetOCTL_ERR_DETECT_REG_A_sm_l2nic_data_err(unsigned int usm_l2nic_data_err); +int iSetOCTL_ERR_DETECT_REG_A_rde_octl_data_err(unsigned int urde_octl_data_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_mul_dif_cfg_chnl_err(unsigned int uoctl_mul_dif_cfg_chnl_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_mul_dif_cfg_en_err(unsigned int uoctl_mul_dif_cfg_en_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_ec_chnl_cfg_chnl_err_1(unsigned int uoctl_ec_chnl_cfg_chnl_err_1); +int iSetOCTL_ERR_DETECT_REG_A_octl_ec_chnl_cfg_chnl_err_0(unsigned int uoctl_ec_chnl_cfg_chnl_err_0); +int iSetOCTL_ERR_DETECT_REG_A_octl_ec_chnl_cfg_en_err(unsigned int uoctl_ec_chnl_cfg_en_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_cpb_num_deficit_err(unsigned int uoctl_cpb_num_deficit_err); +int iSetOCTL_ERR_DETECT_REG_A_octl_sge0_len_err_less(unsigned int uoctl_sge0_len_err_less); +int iSetOCTL_ERR_DETECT_REG_A_octl_sge0_len_err_more(unsigned int uoctl_sge0_len_err_more); +int iSetOCTL_ERR_DETECT_REG_A_octl_sge0_len_err(unsigned int uoctl_sge0_len_err); +int iSetOCTL_ERR_DETECT_REG_A_perx_unknown_cmd_err(unsigned int uperx_unknown_cmd_err); +int iSetOCTL_ERR_DETECT_REG_A_perxin_unknown_cmd_err(unsigned int uperxin_unknown_cmd_err); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_rel_non_vld_err_all(unsigned int ucpi_dpath_rel_non_vld_err_all); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_rel_loss_eop_err_all(unsigned int ucpi_dpath_rel_loss_eop_err_all); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_rel_loss_sop_err_all(unsigned int ucpi_dpath_rel_loss_sop_err_all); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_o_non_vld_err_all(unsigned int ucpi_dpath_o_non_vld_err_all); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_o_loss_eop_err_all(unsigned int ucpi_dpath_o_loss_eop_err_all); +int iSetOCTL_ERR_DETECT_REG_A_cpi_dpath_o_loss_sop_err_all(unsigned int ucpi_dpath_o_loss_sop_err_all); +int iSetOCTL_ERR_DETECT_REG_A_octl_fifo_underflow_all(unsigned int uoctl_fifo_underflow_all); +int iSetOCTL_ERR_DETECT_REG_A_octl_fifo_overflow_all(unsigned int uoctl_fifo_overflow_all); +int iSetOCTL_ERR_DETECT_REG_B_proc_cpath_non_vld_err_all(unsigned int uproc_cpath_non_vld_err_all); +int iSetOCTL_ERR_DETECT_REG_B_proc_cpath_loss_eop_err_all(unsigned int uproc_cpath_loss_eop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_proc_cpath_loss_sop_err_all(unsigned int uproc_cpath_loss_sop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_cpath_non_vld_err_all(unsigned int usm_cpath_non_vld_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_cpath_loss_eop_err_all(unsigned int usm_cpath_loss_eop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_cpath_loss_sop_err_all(unsigned int usm_cpath_loss_sop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_l2nic_non_vld_err_all(unsigned int usm_l2nic_non_vld_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_l2nic_loss_eop_err_all(unsigned int usm_l2nic_loss_eop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_sm_l2nic_loss_sop_err_all(unsigned int usm_l2nic_loss_sop_err_all); +int iSetOCTL_ERR_DETECT_REG_B_octl_sm_parser_data_err(unsigned int uoctl_sm_parser_data_err); +int iSetOCTL_ERR_DETECT_REG_B_octl_perx_hd_dif_err(unsigned int uoctl_perx_hd_dif_err); +int iSetOCTL_ERR_DETECT_REG_B_octl_perx_hd_wdat_err(unsigned int uoctl_perx_hd_wdat_err); +int iSetOCTL_ERR_DETECT_REG_B_octl_dpath_o_sop_err(unsigned int uoctl_dpath_o_sop_err); +int iSetOCTL_ERR_DETECT_RO_REG_A_mqm_cpi_bp_all(unsigned int umqm_cpi_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_osch_octl_cpath_bp_all(unsigned int uosch_octl_cpath_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_osch_octl_dpath_sm_bp_all(unsigned int uosch_octl_dpath_sm_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_osch_octl_dpath_pe_bp_all(unsigned int uosch_octl_dpath_pe_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_prm_cpi_src_bp_all(unsigned int uprm_cpi_src_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_prm_cpi_bp_all(unsigned int uprm_cpi_bp_all); +int iSetOCTL_ERR_DETECT_RO_REG_A_octl_all_fifo_no_empty(unsigned int uoctl_all_fifo_no_empty); +int iSetOCTL_ERR_DETECT_RO_REG_A_octl_cpath_loop_swallow_packet(unsigned int uoctl_cpath_loop_swallow_packet); +int iSetOCTL_ERR_DETECT_RO_REG_A_octl_l2nic_loop_swallow_packet(unsigned int uoctl_l2nic_loop_swallow_packet); +int iSetOCTL_ERR_DETECT_RO_REG_A_octl_pe_loop_swallow_packet(unsigned int uoctl_pe_loop_swallow_packet); +int iSetOCTL_ERR_DETECT_RO_REG_A_dma_pre_alc_num_cur(unsigned int udma_pre_alc_num_cur); +int iSetOCTL_ERR_DETECT_RO_REG_A_glb_cpb_cell_num_cnt(unsigned int uglb_cpb_cell_num_cnt); +int iSetOCTL_ERR_DETECT_RO_REG_B_cp_proc_osch_host_crd_cnt_0(unsigned int ucp_proc_osch_host_crd_cnt_0); +int iSetOCTL_ERR_DETECT_RO_REG_B_cp_proc_icpl_sm_crd_cnt(unsigned int ucp_proc_icpl_sm_crd_cnt); +int iSetOCTL_ERR_DETECT_RO_REG_B_cp_proc_icpl_vio_crd_cnt(unsigned int ucp_proc_icpl_vio_crd_cnt); +int iSetOCTL_ERR_DETECT_RO_REG_C_cp_proc_osch_host_crd_cnt_4(unsigned int ucp_proc_osch_host_crd_cnt_4); +int iSetOCTL_ERR_DETECT_RO_REG_C_cp_proc_osch_host_crd_cnt_3(unsigned int ucp_proc_osch_host_crd_cnt_3); +int iSetOCTL_ERR_DETECT_RO_REG_C_cp_proc_osch_host_crd_cnt_2(unsigned int ucp_proc_osch_host_crd_cnt_2); +int iSetOCTL_ERR_DETECT_RO_REG_C_cp_proc_osch_host_crd_cnt_1(unsigned int ucp_proc_osch_host_crd_cnt_1); +int iSetOCTL_ERR_DETECT_RO_REG_D_octl_mem_err_addr(unsigned int uoctl_mem_err_addr); +int iSetOCTL_ERR_DETECT_RO_REG_D_ci_cqe_tbl_indir_op_done(unsigned int uci_cqe_tbl_indir_op_done); +int iSetOCTL_CMD_CNT_A_cpi_dpath_o_sop_inc(unsigned int ucpi_dpath_o_sop_inc); +int iSetOCTL_CMD_CNT_B_cpi_dpath_o_eop_inc(unsigned int ucpi_dpath_o_eop_inc); +int iSetOCTL_CMD_CNT_C_cpi_dpath_rel_sop_inc(unsigned int ucpi_dpath_rel_sop_inc); +int iSetOCTL_CMD_CNT_D_cpi_dpath_rel_eop_inc(unsigned int ucpi_dpath_rel_eop_inc); +int iSetOCTL_CMD_CNT_E_cpi_dpath_in_chnl_sop_inc(unsigned int ucpi_dpath_in_chnl_sop_inc); +int iSetOCTL_CMD_CNT_F_cpi_dpath_in_chnl_eop_inc(unsigned int ucpi_dpath_in_chnl_eop_inc); +int iSetOCTL_CMD_CNT_G_cpi_dpath_rel_chnl_sop_inc(unsigned int ucpi_dpath_rel_chnl_sop_inc); +int iSetOCTL_CMD_CNT_H_cpi_dpath_rel_chnl_eop_inc(unsigned int ucpi_dpath_rel_chnl_eop_inc); +int iSetOCTL_CMD_CNT_I_octl_rd_inc(unsigned int uoctl_rd_inc); +int iSetOCTL_CMD_CNT_J_octl_rd_cqe_inc(unsigned int uoctl_rd_cqe_inc); +int iSetOCTL_CMD_CNT_K_octl_atomic_inc(unsigned int uoctl_atomic_inc); +int iSetOCTL_CMD_CNT_L_octl_non_l2nic_il_inc(unsigned int uoctl_non_l2nic_il_inc); +int iSetOCTL_CMD_CNT_M_octl_non_l2nic_il_cqe_inc(unsigned int uoctl_non_l2nic_il_cqe_inc); +int iSetOCTL_CMD_CNT_N_octl_wr_inc(unsigned int uoctl_wr_inc); +int iSetOCTL_CMD_CNT_O_octl_wr_cqe_inc(unsigned int uoctl_wr_cqe_inc); +int iSetOCTL_CMD_CNT_P_octl_cqe_only_inc(unsigned int uoctl_cqe_only_inc); +int iSetOCTL_CMD_CNT_Q_octl_ceqe_only(unsigned int uoctl_ceqe_only); +int iSetOCTL_CMD_CNT_R_octl_db_wr_inc(unsigned int uoctl_db_wr_inc); +int iSetOCTL_CMD_CNT_S_octl_mul_dif_rd_inc(unsigned int uoctl_mul_dif_rd_inc); +int iSetOCTL_CMD_CNT_T_octl_ec_rd_1st_inc(unsigned int uoctl_ec_rd_1st_inc); +int iSetOCTL_CMD_CNT_U_octl_ec_rd_2nd_inc(unsigned int uoctl_ec_rd_2nd_inc); +int iSetOCTL_CMD_CNT_V_octl_ec_cqe_rd_1st_inc(unsigned int uoctl_ec_cqe_rd_1st_inc); +int iSetOCTL_CMD_CNT_W_octl_ec_cqe_rd_2nd_inc(unsigned int uoctl_ec_cqe_rd_2nd_inc); +int iSetOCTL_CMD_CNT_X_octl_rd_by_aad_inc(unsigned int uoctl_rd_by_aad_inc); +int iSetOCTL_CMD_CNT_Y_icpl_cqe_inc(unsigned int uicpl_cqe_inc); +int iSetOCTL_CMD_CNT_Z_icpl_ci_inc(unsigned int uicpl_ci_inc); +int iSetOCTL_CMD_CNT_AA_icpl_cqe_only_ceqe_inc(unsigned int uicpl_cqe_only_ceqe_inc); +int iSetOCTL_CMD_CNT_AB_sm_cbuf_head_obd_0_inc(unsigned int usm_cbuf_head_obd_0_inc); +int iSetOCTL_CMD_CNT_AC_sm_cbuf_head_obd_1_inc(unsigned int usm_cbuf_head_obd_1_inc); +int iSetOCTL_CMD_CNT_AD_sm_cbuf_head_obd_2_inc(unsigned int usm_cbuf_head_obd_2_inc); +int iSetOCTL_CMD_CNT_AE_sm_cbuf_head_obd_3_inc(unsigned int usm_cbuf_head_obd_3_inc); +int iSetOCTL_CMD_CNT_AF_sm_cbuf_head_obd_4_inc(unsigned int usm_cbuf_head_obd_4_inc); +int iSetOCTL_CMD_CNT_AG_sm_parser_sop_inc(unsigned int usm_parser_sop_inc); +int iSetOCTL_CMD_CNT_AH_sm_parser_eop_inc(unsigned int usm_parser_eop_inc); +int iSetOCTL_CMD_CNT_AI_sm_l2nic_sop_inc(unsigned int usm_l2nic_sop_inc); +int iSetOCTL_CMD_CNT_AJ_sm_l2nic_eop_inc(unsigned int usm_l2nic_eop_inc); +int iSetOCTL_CMD_CNT_AK_sm_l2nic_chnl_sop_inc(unsigned int usm_l2nic_chnl_sop_inc); +int iSetOCTL_CMD_CNT_AL_sm_l2nic_chnl_eop_inc(unsigned int usm_l2nic_chnl_eop_inc); +int iSetOCTL_CMD_CNT_AM_sm_l2nic_read_inc(unsigned int usm_l2nic_read_inc); +int iSetOCTL_CMD_CNT_AN_sm_l2nic_ceqe_only_inc(unsigned int usm_l2nic_ceqe_only_inc); +int iSetOCTL_CMD_CNT_AO_sm_l2nic_il_inc(unsigned int usm_l2nic_il_inc); +int iSetOCTL_CMD_CNT_AP_sm_l2nic_read_ci_inc(unsigned int usm_l2nic_read_ci_inc); +int iSetOCTL_CMD_CNT_AQ_sm_l2nic_il_ci_inc(unsigned int usm_l2nic_il_ci_inc); +int iSetOCTL_CMD_CNT_AR_sm_cpath_sop_inc(unsigned int usm_cpath_sop_inc); +int iSetOCTL_CMD_CNT_AS_sm_cpath_eop_inc(unsigned int usm_cpath_eop_inc); +int iSetOCTL_CMD_CNT_AT_sm_cpath_rd_inc(unsigned int usm_cpath_rd_inc); +int iSetOCTL_CMD_CNT_AU_sm_cpath_wr_inc(unsigned int usm_cpath_wr_inc); +int iSetOCTL_CMD_CNT_AV_sm_cp_in_src_sop_inc(unsigned int usm_cp_in_src_sop_inc); +int iSetOCTL_CMD_CNT_AW_sm_cp_in_src_eop_inc(unsigned int usm_cp_in_src_eop_inc); +int iSetOCTL_CMD_CNT_AX_sm_cp_proc_src_sop_inc(unsigned int usm_cp_proc_src_sop_inc); +int iSetOCTL_CMD_CNT_AY_sm_cp_proc_src_eop_inc(unsigned int usm_cp_proc_src_eop_inc); +int iSetOCTL_CMD_CNT_AZ_sm_cp_proc_rd_inc(unsigned int usm_cp_proc_rd_inc); +int iSetOCTL_CMD_CNT_BA_sm_cp_proc_wr_inc(unsigned int usm_cp_proc_wr_inc); +int iSetOCTL_CMD_CNT_BB_octl_osch_cp_rd_inc(unsigned int uoctl_osch_cp_rd_inc); +int iSetOCTL_CMD_CNT_BC_octl_osch_cp_wr_inc(unsigned int uoctl_osch_cp_wr_inc); +int iSetOCTL_CMD_PORT_AA_port_octl_rd_cqe_inc(unsigned int uport_octl_rd_cqe_inc); +int iSetOCTL_CMD_PORT_AA_port_octl_rd_inc(unsigned int uport_octl_rd_inc); +int iSetOCTL_CMD_PORT_AB_port_octl_non_l2nic_il_inc(unsigned int uport_octl_non_l2nic_il_inc); +int iSetOCTL_CMD_PORT_AB_port_octl_atomic_inc(unsigned int uport_octl_atomic_inc); +int iSetOCTL_CMD_PORT_AC_port_octl_wr_inc(unsigned int uport_octl_wr_inc); +int iSetOCTL_CMD_PORT_AC_port_octl_non_l2nic_il_cqe_inc(unsigned int uport_octl_non_l2nic_il_cqe_inc); +int iSetOCTL_CMD_PORT_AD_port_octl_cqe_only_inc(unsigned int uport_octl_cqe_only_inc); +int iSetOCTL_CMD_PORT_AD_port_octl_wr_cqe_inc(unsigned int uport_octl_wr_cqe_inc); +int iSetOCTL_CMD_PORT_AE_port_octl_db_wr_inc(unsigned int uport_octl_db_wr_inc); +int iSetOCTL_CMD_PORT_AE_port_octl_ceqe_only_inc(unsigned int uport_octl_ceqe_only_inc); +int iSetOCTL_CMD_PORT_AF_port_octl_ec_rd_1st_inc(unsigned int uport_octl_ec_rd_1st_inc); +int iSetOCTL_CMD_PORT_AF_port_octl_mul_dif_rd_inc(unsigned int uport_octl_mul_dif_rd_inc); +int iSetOCTL_CMD_PORT_AG_port_octl_ec_cqe_rd_1st_inc(unsigned int uport_octl_ec_cqe_rd_1st_inc); +int iSetOCTL_CMD_PORT_AG_port_octl_ec_rd_2nd_inc(unsigned int uport_octl_ec_rd_2nd_inc); +int iSetOCTL_CMD_PORT_AH_port_octl_rd_by_aad_inc(unsigned int uport_octl_rd_by_aad_inc); +int iSetOCTL_CMD_PORT_AH_port_octl_ec_cqe_rd_2nd_inc(unsigned int uport_octl_ec_cqe_rd_2nd_inc); +int iSetOCTL_CMD_PORT_AI_port_icpl_cqe_only_ceqe_inc(unsigned int uport_icpl_cqe_only_ceqe_inc); +int iSetOCTL_CMD_PORT_AI_port_icpl_cqe_inc(unsigned int uport_icpl_cqe_inc); +int iSetOCTL_CMD_PORT_AJ_octl_pe_cmd_port_inc(unsigned int uoctl_pe_cmd_port_inc); +int iSetOCTL_CMD_PORT_AJ_port_icpl_ci_inc(unsigned int uport_icpl_ci_inc); +int iSetOCTL_CMD_PORT_AK_port_sm_l2nic_ceqe_only_inc(unsigned int uport_sm_l2nic_ceqe_only_inc); +int iSetOCTL_CMD_PORT_AK_port_sm_l2nic_read_inc(unsigned int uport_sm_l2nic_read_inc); +int iSetOCTL_CMD_PORT_AL_port_sm_l2nic_read_ci_inc(unsigned int uport_sm_l2nic_read_ci_inc); +int iSetOCTL_CMD_PORT_AL_port_sm_l2nic_il_inc(unsigned int uport_sm_l2nic_il_inc); +int iSetOCTL_CMD_PORT_AM_octl_port_cp_inc(unsigned int uoctl_port_cp_inc); +int iSetOCTL_CMD_PORT_AM_port_sm_l2nic_il_ci_inc(unsigned int uport_sm_l2nic_il_ci_inc); +int iSetOCTL_CMD_PORT_AN_octl_port_cp_wr_inc(unsigned int uoctl_port_cp_wr_inc); +int iSetOCTL_CMD_PORT_AN_octl_port_cp_rd_inc(unsigned int uoctl_port_cp_rd_inc); +int iSetOCTL_CMD_CNT_BD_sm_parser_cpath_inc(unsigned int usm_parser_cpath_inc); +int iSetOCTL_CMD_CNT_BE_sm_parser_l2nic_inc(unsigned int usm_parser_l2nic_inc); +int iSetOCTL_CMD_CNT_BF_sm_parser_ceqe_only_inc(unsigned int usm_parser_ceqe_only_inc); +int iSetOCTL_CMD_CNT_BG_proc_cpath_eop_inc(unsigned int uproc_cpath_eop_inc); +int iSetOCTL_CMD_CNT_BG_proc_cpath_sop_inc(unsigned int uproc_cpath_sop_inc); +int iSetOCTL_CMD_CNT_BH_octl_drop_zero_sge_len_inc(unsigned int uoctl_drop_zero_sge_len_inc); +int iSetOCTL_DPATH_O_ERR_DFX_octl_dpath_o_chnl_sop_err(unsigned int uoctl_dpath_o_chnl_sop_err); +int iSetOCTL_SUB_ERR_CFG_BK_octl_err_fatal_mask_18(unsigned int uoctl_err_fatal_mask_18); +int iSetOCTL_SUB_ERR_CFG_BL_octl_err_nonfatal_mask_18(unsigned int uoctl_err_nonfatal_mask_18); +int iSetOCTL_SUB_ERR_CFG_AA_octl_err_fatal_mask_0(unsigned int uoctl_err_fatal_mask_0); +int iSetOCTL_SUB_ERR_CFG_AB_octl_err_nonfatal_mask_0(unsigned int uoctl_err_nonfatal_mask_0); +int iSetOCTL_SUB_ERR_CFG_AC_octl_err_fatal_mask_1(unsigned int uoctl_err_fatal_mask_1); +int iSetOCTL_SUB_ERR_CFG_AD_octl_err_nonfatal_mask_1(unsigned int uoctl_err_nonfatal_mask_1); +int iSetOCTL_SUB_ERR_CFG_AE_octl_err_fatal_mask_2(unsigned int uoctl_err_fatal_mask_2); +int iSetOCTL_SUB_ERR_CFG_AF_octl_err_nonfatal_mask_2(unsigned int uoctl_err_nonfatal_mask_2); +int iSetOCTL_SUB_ERR_CFG_AG_octl_err_fatal_mask_3(unsigned int uoctl_err_fatal_mask_3); +int iSetOCTL_SUB_ERR_CFG_AH_octl_err_nonfatal_mask_3(unsigned int uoctl_err_nonfatal_mask_3); +int iSetOCTL_SUB_ERR_CFG_AI_octl_err_fatal_mask_4(unsigned int uoctl_err_fatal_mask_4); +int iSetOCTL_SUB_ERR_CFG_AJ_octl_err_nonfatal_mask_4(unsigned int uoctl_err_nonfatal_mask_4); +int iSetOCTL_SUB_ERR_CFG_AK_octl_err_fatal_mask_5(unsigned int uoctl_err_fatal_mask_5); +int iSetOCTL_SUB_ERR_CFG_AL_octl_err_nonfatal_mask_5(unsigned int uoctl_err_nonfatal_mask_5); +int iSetOCTL_SUB_ERR_CFG_AM_octl_err_fatal_mask_6(unsigned int uoctl_err_fatal_mask_6); +int iSetOCTL_SUB_ERR_CFG_AN_octl_err_nonfatal_mask_6(unsigned int uoctl_err_nonfatal_mask_6); +int iSetOCTL_SUB_ERR_CFG_AO_octl_err_fatal_mask_7(unsigned int uoctl_err_fatal_mask_7); +int iSetOCTL_SUB_ERR_CFG_AP_octl_err_nonfatal_mask_7(unsigned int uoctl_err_nonfatal_mask_7); +int iSetOCTL_SUB_ERR_CFG_AQ_octl_err_fatal_mask_8(unsigned int uoctl_err_fatal_mask_8); +int iSetOCTL_SUB_ERR_CFG_AR_octl_err_nonfatal_mask_8(unsigned int uoctl_err_nonfatal_mask_8); +int iSetOCTL_SUB_ERR_CFG_AS_octl_err_fatal_mask_9(unsigned int uoctl_err_fatal_mask_9); +int iSetOCTL_SUB_ERR_CFG_AT_octl_err_nonfatal_mask_9(unsigned int uoctl_err_nonfatal_mask_9); +int iSetOCTL_SUB_ERR_CFG_AU_octl_err_fatal_mask_10(unsigned int uoctl_err_fatal_mask_10); +int iSetOCTL_SUB_ERR_CFG_AV_octl_err_nonfatal_mask_10(unsigned int uoctl_err_nonfatal_mask_10); +int iSetOCTL_SUB_ERR_CFG_AW_octl_err_fatal_mask_11(unsigned int uoctl_err_fatal_mask_11); +int iSetOCTL_SUB_ERR_CFG_AX_octl_err_nonfatal_mask_11(unsigned int uoctl_err_nonfatal_mask_11); +int iSetOCTL_SUB_ERR_CFG_AY_octl_err_fatal_mask_12(unsigned int uoctl_err_fatal_mask_12); +int iSetOCTL_SUB_ERR_CFG_AZ_octl_err_nonfatal_mask_12(unsigned int uoctl_err_nonfatal_mask_12); +int iSetOCTL_SUB_ERR_CFG_BA_octl_err_fatal_mask_13(unsigned int uoctl_err_fatal_mask_13); +int iSetOCTL_SUB_ERR_CFG_BB_octl_err_nonfatal_mask_13(unsigned int uoctl_err_nonfatal_mask_13); +int iSetOCTL_SUB_ERR_CFG_BC_octl_err_fatal_mask_14(unsigned int uoctl_err_fatal_mask_14); +int iSetOCTL_SUB_ERR_CFG_BD_octl_err_nonfatal_mask_14(unsigned int uoctl_err_nonfatal_mask_14); +int iSetOCTL_SUB_ERR_CFG_BE_octl_err_fatal_mask_15(unsigned int uoctl_err_fatal_mask_15); +int iSetOCTL_SUB_ERR_CFG_BF_octl_err_nonfatal_mask_15(unsigned int uoctl_err_nonfatal_mask_15); +int iSetOCTL_SUB_ERR_CFG_BG_octl_err_fatal_mask_16(unsigned int uoctl_err_fatal_mask_16); +int iSetOCTL_SUB_ERR_CFG_BH_octl_err_nonfatal_mask_16(unsigned int uoctl_err_nonfatal_mask_16); +int iSetOCTL_SUB_ERR_CFG_BI_octl_err_fatal_mask_17(unsigned int uoctl_err_fatal_mask_17); +int iSetOCTL_SUB_ERR_CFG_BJ_octl_err_nonfatal_mask_17(unsigned int uoctl_err_nonfatal_mask_17); +int iSetOCTL_RAM_ECC_BYPASS_mem_ecc_bypass(unsigned int umem_ecc_bypass); +int iSetOCTL_RAM_ECC_INJ_REQ_A_mem_ecc_inj_req_0(unsigned int umem_ecc_inj_req_0); +int iSetOCTL_RAM_ECC_INJ_REQ_B_mem_ecc_inj_req_1(unsigned int umem_ecc_inj_req_1); +int iSetOCTL_RAM_ECC_INJ_REQ_C_mem_ecc_inj_req_2(unsigned int umem_ecc_inj_req_2); +int iSetOCTL_RAM_ECC_ERR_A_mem_ecc_err_0(unsigned int umem_ecc_err_0); +int iSetOCTL_RAM_ECC_ERR_B_mem_ecc_err_1(unsigned int umem_ecc_err_1); +int iSetOCTL_RAM_ECC_ERR_C_mem_ecc_err_2(unsigned int umem_ecc_err_2); +int iSetOCTL_RAM_LINK_LIST_AA_pe_cbuf_ram_head_empty(unsigned int upe_cbuf_ram_head_empty); +int iSetOCTL_RAM_LINK_LIST_AB_pe_cbuf_ram_sge_empty(unsigned int upe_cbuf_ram_sge_empty); +int iSetOCTL_RAM_LINK_LIST_AC_pe_cbuf_ram_app0_empty(unsigned int upe_cbuf_ram_app0_empty); +int iSetOCTL_RAM_LINK_LIST_AD_pe_cbuf_ram_app1_empty(unsigned int upe_cbuf_ram_app1_empty); +int iSetOCTL_RAM_LINK_LIST_AE_sm_cbuf_ram_1st_head_empty_0(unsigned int usm_cbuf_ram_1st_head_empty_0); +int iSetOCTL_RAM_LINK_LIST_AF_sm_cbuf_ram_1st_head_empty_1(unsigned int usm_cbuf_ram_1st_head_empty_1); +int iSetOCTL_RAM_LINK_LIST_AG_sm_cbuf_ram_1st_sge_empty_0(unsigned int usm_cbuf_ram_1st_sge_empty_0); +int iSetOCTL_RAM_LINK_LIST_AH_sm_cbuf_ram_1st_sge_empty_1(unsigned int usm_cbuf_ram_1st_sge_empty_1); +int iSetOCTL_RAM_LINK_LIST_AI_sm_cbuf_ram_1st_app0_empty_0(unsigned int usm_cbuf_ram_1st_app0_empty_0); +int iSetOCTL_RAM_LINK_LIST_AJ_sm_cbuf_ram_1st_app0_empty_1(unsigned int usm_cbuf_ram_1st_app0_empty_1); +int iSetOCTL_RAM_LINK_LIST_AK_sm_cbuf_ram_2nd_app0_empty(unsigned int usm_cbuf_ram_2nd_app0_empty); +int iSetOCTL_RAM_LINK_LIST_AK_sm_cbuf_ram_2nd_sge_empty(unsigned int usm_cbuf_ram_2nd_sge_empty); +int iSetOCTL_RAM_LINK_LIST_AK_sm_cbuf_ram_2nd_head_empty(unsigned int usm_cbuf_ram_2nd_head_empty); +int iSetOCTL_RAM_LINK_LIST_AL_pe_cmd_2nd_ec_ram_empty(unsigned int upe_cmd_2nd_ec_ram_empty); +int iSetOCTL_RAM_LINK_LIST_AL_pe_cmd_1st_ec_ram_empty(unsigned int upe_cmd_1st_ec_ram_empty); +int iSetOCTL_RAM_LINK_LIST_AM_cpath_proc_ram_empty(unsigned int ucpath_proc_ram_empty); +int iSetOCTL_RAM_LINK_LIST_AN_pe_cbuf_ram_app0_free_cell_cnt(unsigned int upe_cbuf_ram_app0_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AN_pe_cbuf_ram_sge_free_cell_cnt(unsigned int upe_cbuf_ram_sge_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AN_pe_cbuf_ram_head_free_cell_cnt(unsigned int upe_cbuf_ram_head_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AO_pe_dbuf_ram_bk1_free_cell_cnt(unsigned int upe_dbuf_ram_bk1_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AO_pe_dbuf_ram_bk0_free_cell_cnt(unsigned int upe_dbuf_ram_bk0_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AO_pe_cbuf_ram_app1_free_cell_cnt(unsigned int upe_cbuf_ram_app1_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AP_sm_cbuf_ram_sge_free_cell_cnt(unsigned int usm_cbuf_ram_sge_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AP_sm_cbuf_ram_head_free_cell_cnt(unsigned int usm_cbuf_ram_head_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AQ_sm_dbuf_ram_bk1_free_cell_cnt(unsigned int usm_dbuf_ram_bk1_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AQ_sm_dbuf_ram_bk0_free_cell_cnt(unsigned int usm_dbuf_ram_bk0_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AQ_sm_cbuf_ram_app0_free_cell_cnt(unsigned int usm_cbuf_ram_app0_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AR_cpath_proc_free_cell_cnt(unsigned int ucpath_proc_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AR_pe_cmd_2nd_ec_free_cell_cnt(unsigned int upe_cmd_2nd_ec_free_cell_cnt); +int iSetOCTL_RAM_LINK_LIST_AR_pe_cmd_1st_ec_free_cell_cnt(unsigned int upe_cmd_1st_ec_free_cell_cnt); +int iSetOCTL_IN_BP_SIG_A_prm_cpi_src_bp_0(unsigned int uprm_cpi_src_bp_0); +int iSetOCTL_IN_BP_SIG_B_prm_cpi_src_bp_1(unsigned int uprm_cpi_src_bp_1); +int iSetOCTL_IN_BP_SIG_C_prm_cpi_src_bp_2(unsigned int uprm_cpi_src_bp_2); +int iSetOCTL_IN_BP_SIG_D_osch_octl_dpath_pe_bp(unsigned int uosch_octl_dpath_pe_bp); +int iSetOCTL_IN_BP_SIG_E_osch_octl_cpath_bp(unsigned int uosch_octl_cpath_bp); +int iSetOCTL_IN_BP_SIG_E_osch_octl_dpath_sm_bp(unsigned int uosch_octl_dpath_sm_bp); +int iSetOCTL_IN_BP_SIG_F_mqm_cpi_dat_inc_bp(unsigned int umqm_cpi_dat_inc_bp); +int iSetOCTL_IN_BP_SIG_F_mqm_cpi_host_sge_inc_bp(unsigned int umqm_cpi_host_sge_inc_bp); +int iSetOCTL_IN_BP_SIG_F_mqm_cpi_ep_sge_inc_bp(unsigned int umqm_cpi_ep_sge_inc_bp); +int iSetOCTL_IN_BP_SIG_F_prm_cpi_bp(unsigned int uprm_cpi_bp); +int iSetOCTL_IN_BP_SIG_F_octl_rde_sm_parser_bp(unsigned int uoctl_rde_sm_parser_bp); +int iSetOCTL_IN_BP_SIG_F_octl_cpi_perx_bp(unsigned int uoctl_cpi_perx_bp); +int iSetOCTL_FIFO_ST_A_octl_fifo_overflow(unsigned int uoctl_fifo_overflow); +int iSetOCTL_FIFO_ST_B_octl_fifo_underflow(unsigned int uoctl_fifo_underflow); +int iSetOCTL_FIFO_ST_C_octl_fifo_empty(unsigned int uoctl_fifo_empty); +int iSetOCTL_FIFO_ST_D_octl_fifo_full(unsigned int uoctl_fifo_full); +int iSetOCTL_FIFO_ST_E_cqe_cmd_fifo_done_port(unsigned int ucqe_cmd_fifo_done_port); +int iSetOCTL_FIFO_ST_E_cp_l2nic_cqe_en_cmd_pful(unsigned int ucp_l2nic_cqe_en_cmd_pful); +int iSetOCTL_FIFO_AFON_A_dbuf_pe_app1_afon_th(unsigned int udbuf_pe_app1_afon_th); +int iSetOCTL_FIFO_AFON_A_dbuf_pe_app0_afon_th(unsigned int udbuf_pe_app0_afon_th); +int iSetOCTL_FIFO_AFON_A_cp_l2nic_cqe_en_cmd_afon_th(unsigned int ucp_l2nic_cqe_en_cmd_afon_th); +int iSetOCTL_FIFO_AFON_A_smvio_fifo_afon_th(unsigned int usmvio_fifo_afon_th); +int iSetOCTL_FIFO_AFON_A_dpath_o_sfifo_afon_th(unsigned int udpath_o_sfifo_afon_th); +int iSetOCTL_FIFO_AFON_B_dbuf_sm_app0_afon_th(unsigned int udbuf_sm_app0_afon_th); +int iSetOCTL_FIFO_AFON_B_cpb_bk1_fifo_afon_th(unsigned int ucpb_bk1_fifo_afon_th); +int iSetOCTL_FIFO_AFON_B_cpb_bk0_fifo_afon_th(unsigned int ucpb_bk0_fifo_afon_th); +int iSetOCTL_FIFO_AFON_B_cpb_adj_fifo_afon_th(unsigned int ucpb_adj_fifo_afon_th); +int iSetOCTL_FIFO_AFON_B_pe_parser_dbuf_fifo_afon_th(unsigned int upe_parser_dbuf_fifo_afon_th); +int iSetOCTL_FIFO_AFON_B_pe_parser_sge_fifo_afon_th(unsigned int upe_parser_sge_fifo_afon_th); +int iSetOCTL_FIFO_AFON_B_pe_parser_head_fifo_afon_th(unsigned int upe_parser_head_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_sge_crdt_fifo_afon_th(unsigned int usge_crdt_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_aad_rd_fifo_afon_th(unsigned int uaad_rd_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_tlp_rd_fifo_afon_th(unsigned int utlp_rd_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_rde_octl_fifo_afon_th(unsigned int urde_octl_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_sm_parser_dbuf_fifo_afon_th(unsigned int usm_parser_dbuf_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_sm_parser_sge_fifo_afon_th(unsigned int usm_parser_sge_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_sm_parser_head_fifo_afon_th(unsigned int usm_parser_head_fifo_afon_th); +int iSetOCTL_FIFO_AFON_C_dbuf_sm_app1_afon_th(unsigned int udbuf_sm_app1_afon_th); +int iSetOCTL_ERR_SIG_AA_octl_perx_data_err(unsigned int uoctl_perx_data_err); +int iSetOCTL_ERR_SIG_AB_octl_dpath_o_loss_sop_err(unsigned int uoctl_dpath_o_loss_sop_err); +int iSetOCTL_ERR_SIG_AC_octl_dpath_o_loss_eop_err(unsigned int uoctl_dpath_o_loss_eop_err); +int iSetOCTL_ERR_SIG_AD_octl_dpath_o_non_vld_err(unsigned int uoctl_dpath_o_non_vld_err); +int iSetOCTL_ERR_SIG_AE_octl_dpath_rel_loss_sop_err(unsigned int uoctl_dpath_rel_loss_sop_err); +int iSetOCTL_ERR_SIG_AF_octl_dpath_rel_loss_eop_err(unsigned int uoctl_dpath_rel_loss_eop_err); +int iSetOCTL_ERR_SIG_AG_octl_dpath_rel_non_vld_err(unsigned int uoctl_dpath_rel_non_vld_err); +int iSetOCTL_ERR_SIG_AH_octl_l2nic_loss_sop_err_0(unsigned int uoctl_l2nic_loss_sop_err_0); +int iSetOCTL_ERR_SIG_AI_octl_l2nic_loss_sop_err_1(unsigned int uoctl_l2nic_loss_sop_err_1); +int iSetOCTL_ERR_SIG_AJ_octl_l2nic_loss_eop_err_0(unsigned int uoctl_l2nic_loss_eop_err_0); +int iSetOCTL_ERR_SIG_AK_octl_l2nic_loss_eop_err_1(unsigned int uoctl_l2nic_loss_eop_err_1); +int iSetOCTL_ERR_SIG_AL_octl_l2nic_non_vld_err_0(unsigned int uoctl_l2nic_non_vld_err_0); +int iSetOCTL_ERR_SIG_AM_octl_l2nic_non_vld_err_1(unsigned int uoctl_l2nic_non_vld_err_1); +int iSetOCTL_EC_SORO_ATTR_TBL_FIRST_octl_vf_so_ro_0_first(unsigned int uoctl_vf_so_ro_0_first); +int iSetOCTL_EC_SORO_ATTR_TBL_FIRST_octl_vf_dma_attr_offset_0_first(unsigned int uoctl_vf_dma_attr_offset_0_first); +int iSetOCTL_EC_SORO_ATTR_TBL_FIRST_octl_vf_so_ro_1_first(unsigned int uoctl_vf_so_ro_1_first); +int iSetOCTL_EC_SORO_ATTR_TBL_FIRST_octl_vf_dma_attr_offset_1_first(unsigned int uoctl_vf_dma_attr_offset_1_first); +int iSetOCTL_EC_SORO_ATTR_TBL_SECOND_octl_vf_so_ro_0_second(unsigned int uoctl_vf_so_ro_0_second); +int iSetOCTL_EC_SORO_ATTR_TBL_SECOND_octl_vf_dma_attr_offset_0_second(unsigned int uoctl_vf_dma_attr_offset_0_second); +int iSetOCTL_EC_SORO_ATTR_TBL_SECOND_octl_vf_so_ro_1_second(unsigned int uoctl_vf_so_ro_1_second); +int iSetOCTL_EC_SORO_ATTR_TBL_SECOND_octl_vf_dma_attr_offset_1_second(unsigned int uoctl_vf_dma_attr_offset_1_second); +int iSetOCTL_EC_CHANNEL_ENABLE_cpi_octl_ec_chnl_first(unsigned int ucpi_octl_ec_chnl_first); +int iSetOCTL_EC_CHANNEL_ENABLE_cpi_octl_ec_chnl_first_en(unsigned int ucpi_octl_ec_chnl_first_en); +int iSetOCTL_EC_CHANNEL_ENABLE_cpi_octl_ec_chnl_second(unsigned int ucpi_octl_ec_chnl_second); +int iSetOCTL_EC_CHANNEL_ENABLE_cpi_octl_ec_chnl_second_en(unsigned int ucpi_octl_ec_chnl_second_en); +int iSetOCTL_SM_CBUF_I_READY_CHNL_A_sm_cbuf_i_ready_chnl_a(unsigned int usm_cbuf_i_ready_chnl_a); +int iSetOCTL_SM_CBUF_I_READY_CHNL_B_sm_cbuf_i_ready_chnl_b(unsigned int usm_cbuf_i_ready_chnl_b); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_octl_mul_dif_dma_attr_offset_1(unsigned int uoctl_mul_dif_dma_attr_offset_1); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_octl_mul_dif_so_ro_1(unsigned int uoctl_mul_dif_so_ro_1); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_octl_mul_dif_dma_attr_offset_0(unsigned int uoctl_mul_dif_dma_attr_offset_0); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_octl_mul_dif_so_ro_0(unsigned int uoctl_mul_dif_so_ro_0); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_cpi_octl_mul_dif_rd_chnl(unsigned int ucpi_octl_mul_dif_rd_chnl); +int iSetOCTL_MUL_HOST_DIF_RD_CFG_cpi_octl_mul_dif_rd_chnl_en(unsigned int ucpi_octl_mul_dif_rd_chnl_en); +int iSetOCTL_DB_WR_ADDR_L_octl_db_wr_sge_addr_l(unsigned int uoctl_db_wr_sge_addr_l); +int iSetOCTL_DB_WR_ADDR_H_octl_db_wr_sge_addr_h(unsigned int uoctl_db_wr_sge_addr_h); +int iSetOCTL_ENDIAN_CFG_cpi_octl_ci_endian_cfg(unsigned int ucpi_octl_ci_endian_cfg); +int iSetOCTL_ENDIAN_CFG_cpi_octl_cqe_endian_cfg(unsigned int ucpi_octl_cqe_endian_cfg); +int iSetOCTL_FSM_ST_A_cpi_dpath_o_cur_st_a(unsigned int ucpi_dpath_o_cur_st_a); +int iSetOCTL_FSM_ST_B_cpi_dpath_o_cur_st_b(unsigned int ucpi_dpath_o_cur_st_b); +int iSetOCTL_FSM_ST_C_cpi_dpath_o_cur_st_c(unsigned int ucpi_dpath_o_cur_st_c); +int iSetOCTL_FSM_ST_D_cpi_dpath_o_cur_st_d(unsigned int ucpi_dpath_o_cur_st_d); +int iSetOCTL_FSM_ST_E_cpi_dpath_o_cur_st_e(unsigned int ucpi_dpath_o_cur_st_e); +int iSetOCTL_FSM_ST_F_cur_ci_data_tbl_st(unsigned int ucur_ci_data_tbl_st); +int iSetOCTL_FSM_ST_F_cur_ci_attr_tbl_st(unsigned int ucur_ci_attr_tbl_st); +int iSetOCTL_HEAD_STORAGE_DFX_A_pe_unknown_cmd_head_0(unsigned int upe_unknown_cmd_head_0); +int iSetOCTL_HEAD_STORAGE_DFX_B_pe_unknown_cmd_head_1(unsigned int upe_unknown_cmd_head_1); +int iSetOCTL_HEAD_STORAGE_DFX_C_pe_unknown_cmd_head_2(unsigned int upe_unknown_cmd_head_2); +int iSetOCTL_HEAD_STORAGE_DFX_D_pe_unknown_cmd_head_3(unsigned int upe_unknown_cmd_head_3); +int iSetOCTL_HEAD_STORAGE_DFX_E_cpb_num_deficit_err_head_0(unsigned int ucpb_num_deficit_err_head_0); +int iSetOCTL_HEAD_STORAGE_DFX_F_cpb_num_deficit_err_head_1(unsigned int ucpb_num_deficit_err_head_1); +int iSetOCTL_HEAD_STORAGE_DFX_G_sge0_len_err_head_0(unsigned int usge0_len_err_head_0); +int iSetOCTL_HEAD_STORAGE_DFX_H_sge0_len_err_head_1(unsigned int usge0_len_err_head_1); +int iSetOCTL_ERR_SIG_AN_octl_cpath_loss_sop_err(unsigned int uoctl_cpath_loss_sop_err); +int iSetOCTL_ERR_SIG_AO_octl_cpath_loss_eop_err(unsigned int uoctl_cpath_loss_eop_err); +int iSetOCTL_ERR_SIG_AP_octl_cpath_non_vld_err(unsigned int uoctl_cpath_non_vld_err); +int iSetOCTL_ERR_SIG_AQ_octl_proc_non_vld_err(unsigned int uoctl_proc_non_vld_err); +int iSetOCTL_ERR_SIG_AQ_octl_proc_cpath_loss_eop_err(unsigned int uoctl_proc_cpath_loss_eop_err); +int iSetOCTL_ERR_SIG_AQ_octl_proc_cpath_loss_sop_err(unsigned int uoctl_proc_cpath_loss_sop_err); +int iSetOCTL_HEAD_STORAGE_DFX_I_pe_cmd_last_known_head_0(unsigned int upe_cmd_last_known_head_0); +int iSetOCTL_HEAD_STORAGE_DFX_J_pe_cmd_last_known_head_1(unsigned int upe_cmd_last_known_head_1); +int iSetOCTL_HEAD_STORAGE_DFX_K_pe_cmd_last_known_head_2(unsigned int upe_cmd_last_known_head_2); +int iSetOCTL_HEAD_STORAGE_DFX_L_pe_cmd_last_known_head_3(unsigned int upe_cmd_last_known_head_3); +int iSetOCTL_PE_PARSER_CFG_1ST_cpb_num_deficit_err_en(unsigned int ucpb_num_deficit_err_en); +int iSetOCTL_PE_PARSER_CFG_1ST_sge0_len_err_en(unsigned int usge0_len_err_en); +int iSetOCTL_PE_PARSER_CFG_1ST_pe_unknown_cmd_err_en(unsigned int upe_unknown_cmd_err_en); +int iSetOCTL_PE_PARSER_CFG_1ST_sge_len_null_en(unsigned int usge_len_null_en); +int iSetOCTL_PE_PARSER_CFG_1ST_cpi_octl_cqe_ci_cmd_drop_en(unsigned int ucpi_octl_cqe_ci_cmd_drop_en); +int iSetOCTL_LOOP_ST_A_pe_loop_has_packet(unsigned int upe_loop_has_packet); +int iSetOCTL_LOOP_ST_A_sm_l2nic_loop_has_packet(unsigned int usm_l2nic_loop_has_packet); +int iSetOCTL_LOOP_ST_A_cpath_loop_has_packet(unsigned int ucpath_loop_has_packet); +int iSetOCTL_LOOP_ST_B_cpath_proc_has_packet(unsigned int ucpath_proc_has_packet); +int iSetOCTL_LOOP_ST_B_cpath_has_packet(unsigned int ucpath_has_packet); +int iSetOCTL_LOOP_ST_B_sm_cmd_ctl_has_packet(unsigned int usm_cmd_ctl_has_packet); +int iSetOCTL_LOOP_ST_B_sm_dbuf_has_packet(unsigned int usm_dbuf_has_packet); +int iSetOCTL_LOOP_ST_B_sm_cbuf_has_packet(unsigned int usm_cbuf_has_packet); +int iSetOCTL_LOOP_ST_B_sm_parser_has_packet(unsigned int usm_parser_has_packet); +int iSetOCTL_LOOP_ST_B_pe_cmd_ctl_has_packet(unsigned int upe_cmd_ctl_has_packet); +int iSetOCTL_LOOP_ST_B_pe_cqe_ctl_has_packet(unsigned int upe_cqe_ctl_has_packet); +int iSetOCTL_LOOP_ST_B_pe_dbuf_has_packet(unsigned int upe_dbuf_has_packet); +int iSetOCTL_LOOP_ST_B_pe_cbuf_has_packet(unsigned int upe_cbuf_has_packet); +int iSetOCTL_LOOP_ST_B_pe_parser_has_cpb_crdt(unsigned int upe_parser_has_cpb_crdt); +int iSetOCTL_LOOP_ST_B_pe_parser_has_packet(unsigned int upe_parser_has_packet); +int iSetOCTL_LOOP_ST_B_octl_tlp_ctl_has_packet(unsigned int uoctl_tlp_ctl_has_packet); +int iSetOCTL_LOOP_ST_B_octl_aad_ctl_has_packet(unsigned int uoctl_aad_ctl_has_packet); +int iSetOCTL_LOOP_ST_B_octl_dpath_o_has_packet(unsigned int uoctl_dpath_o_has_packet); +int iSetOCTL_DFX_SIG_A_cpi_perx_max_bp_cnt(unsigned int ucpi_perx_max_bp_cnt); +int iSetOCTL_PF_RANGE_PORT_pf_func_idx_l(unsigned int upf_func_idx_l); +int iSetOCTL_PF_RANGE_PORT_pf_func_idx_h(unsigned int upf_func_idx_h); +int iSetOCTL_PF_RANGE_PORT_pf_func_idx_v(unsigned int upf_func_idx_v); +int iSetOCTL_VF_RANGE_PORT_vf_func_idx_l(unsigned int uvf_func_idx_l); +int iSetOCTL_VF_RANGE_PORT_vf_func_idx_h(unsigned int uvf_func_idx_h); +int iSetOCTL_VF_RANGE_PORT_vf_func_idx_v(unsigned int uvf_func_idx_v); +int iSetOCTL_LVF_RANGE_PORT_lvf_func_idx_l(unsigned int ulvf_func_idx_l); +int iSetOCTL_LVF_RANGE_PORT_lvf_func_idx_h(unsigned int ulvf_func_idx_h); +int iSetOCTL_LVF_RANGE_PORT_lvf_func_idx_v(unsigned int ulvf_func_idx_v); +int iSetOCTL_VLD_SIG_AA_octl_inside_data_vld_0(unsigned int uoctl_inside_data_vld_0); +int iSetOCTL_VLD_SIG_AB_octl_inside_data_vld_1(unsigned int uoctl_inside_data_vld_1); +int iSetOCTL_VLD_SIG_AC_octl_inside_data_vld_2(unsigned int uoctl_inside_data_vld_2); +int iSetOCTL_VLD_SIG_AD_octl_inside_data_vld_3(unsigned int uoctl_inside_data_vld_3); +int iSetOCTL_VLD_SIG_AE_octl_inside_data_vld_4(unsigned int uoctl_inside_data_vld_4); +int iSetOCTL_VLD_SIG_AF_octl_inside_data_vld_5(unsigned int uoctl_inside_data_vld_5); +int iSetOCTL_VLD_SIG_AG_octl_inside_data_vld_6(unsigned int uoctl_inside_data_vld_6); +int iSetOCTL_VLD_SIG_AH_octl_inside_data_vld_7(unsigned int uoctl_inside_data_vld_7); +int iSetCPI_OCTL_CPATH_CRDT_icpl_sm_crdt_num(unsigned int uicpl_sm_crdt_num); +int iSetCPI_OCTL_CPATH_CRDT_icpl_vio_crdt_num(unsigned int uicpl_vio_crdt_num); +int iSetCPI_OCTL_CPATH_CRDT_osch_host_crdt_num(unsigned int uosch_host_crdt_num); +int iSetCPI_OCTL_CPATH_CRDT_cpi_cpath_proc_bypass(unsigned int ucpi_cpath_proc_bypass); +int iSetCTRL_BUS_CFG_ONE_ctrl_bus_one(unsigned int uctrl_bus_one); +int iSetCTRL_BUS_CFG_TWO_ctrl_bus_two(unsigned int uctrl_bus_two); +int iSetCTRL_BUS_CFG_THREE_ctrl_bus_three(unsigned int uctrl_bus_three); +int iSetCTRL_BUS_CFG_FOUR_ctrl_bus_four(unsigned int uctrl_bus_four); +int iSetCTRL_BUS_CFG_FIVE_ctrl_bus_five(unsigned int uctrl_bus_five); +int iSetBAK_FOR_ECO_AA_bak_for_eco_b(unsigned int ubak_for_eco_b); +int iSetBAK_FOR_ECO_AA_bak_for_eco_a(unsigned int ubak_for_eco_a); +int iSetBAK_FOR_ECO_BB_bak_for_eco_d(unsigned int ubak_for_eco_d); +int iSetBAK_FOR_ECO_BB_bak_for_eco_c(unsigned int ubak_for_eco_c); +int iSetOCTL_HEAD_STORAGE_DFX_M_perxin_unknown_cmd_head_0(unsigned int uperxin_unknown_cmd_head_0); +int iSetOCTL_HEAD_STORAGE_DFX_N_perxin_unknown_cmd_head_1(unsigned int uperxin_unknown_cmd_head_1); +int iSetOCTL_HEAD_STORAGE_DFX_O_perxin_unknown_cmd_head_2(unsigned int uperxin_unknown_cmd_head_2); +int iSetOCTL_HEAD_STORAGE_DFX_P_perxin_unknown_cmd_head_3(unsigned int uperxin_unknown_cmd_head_3); +int iSetBAK_FOR_ECO_CC_bak_for_eco_f(unsigned int ubak_for_eco_f); +int iSetBAK_FOR_ECO_CC_bak_for_eco_e(unsigned int ubak_for_eco_e); +int iSetBAK_FOR_ECO_DD_bak_for_eco_h(unsigned int ubak_for_eco_h); +int iSetBAK_FOR_ECO_DD_bak_for_eco_g(unsigned int ubak_for_eco_g); +int iSetBAK_FOR_ECO_EE_bak_for_eco_j(unsigned int ubak_for_eco_j); +int iSetBAK_FOR_ECO_EE_bak_for_eco_i(unsigned int ubak_for_eco_i); +int iSetCPI_SM_CHL_CFG_EN_A_cpi_sm_chl_cfg_en_a(unsigned int ucpi_sm_chl_cfg_en_a); +int iSetCPI_SM_CHL_CFG_EN_B_cpi_sm_chl_cfg_en_b(unsigned int ucpi_sm_chl_cfg_en_b); +int iSetCPI_OCTL_MUL_WR_CFG_octl_mul_wr_dma_attr_offset(unsigned int uoctl_mul_wr_dma_attr_offset); +int iSetCPI_OCTL_MUL_WR_CFG_octl_mul_wr_so_ro(unsigned int uoctl_mul_wr_so_ro); +int iSetCPI_OCTL_MUL_WR_CFG_octl_mul_wr_soro_attr_en(unsigned int uoctl_mul_wr_soro_attr_en); +int iSetCPI_OCTL_CQE_CTL_CFG_cqe_cmd_fifo_alfull_gap(unsigned int ucqe_cmd_fifo_alfull_gap); +int iSetCPI_OCTL_CQE_CTL_CFG_l2nic_ci_force_update(unsigned int ul2nic_ci_force_update); + +/* Define the union csr_osch_tlp_drop_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_port0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt_port0_u; + +/* Define the union csr_osch_tlp_drop_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_port1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt_port1_u; + +/* Define the union csr_osch_tlp_drop_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_port2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt_port2_u; + +/* Define the union csr_osch_tlp_drop_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_port3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt_port3_u; + +/* Define the union csr_osch_tlp_drop_cnt_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_port4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt_port4_u; + +/* Define the union csr_osch_tlp_error_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_err_count_port3 : 8; /* [7:0] */ + u32 osch_tlp_err_count_port2 : 8; /* [15:8] */ + u32 osch_tlp_err_count_port1 : 8; /* [23:16] */ + u32 osch_tlp_err_count_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_error_cnt0_u; + +/* Define the union csr_osch_tlp_error_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_err_count_port4 : 8; /* [7:0] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_error_cnt1_u; + +/* Define the union csr_osch_tlp_drop_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt0_u; + +/* Define the union csr_osch_tlp_drop_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt1_u; + +/* Define the union csr_osch_tlp_drop_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt2_u; + +/* Define the union csr_osch_tlp_drop_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt3_u; + +/* Define the union csr_osch_tlp_drop_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt4_u; + +/* Define the union csr_osch_tlp_drop_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt5_u; + +/* Define the union csr_osch_tlp_drop_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt6_u; + +/* Define the union csr_osch_tlp_drop_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt7_u; + +/* Define the union csr_osch_tlp_drop_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt8_u; + +/* Define the union csr_osch_tlp_drop_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt9_u; + +/* Define the union csr_osch_tlp_drop_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt10_u; + +/* Define the union csr_osch_tlp_drop_cnt11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt11_u; + +/* Define the union csr_osch_tlp_drop_cnt12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt12_u; + +/* Define the union csr_osch_tlp_drop_cnt13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt13_u; + +/* Define the union csr_osch_tlp_drop_cnt14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt14_u; + +/* Define the union csr_osch_tlp_drop_cnt15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_cnt15_u; + +/* Define the union csr_osch_tlp_drop_func01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func1 : 12; /* [11:0] */ + u32 rsv_1 : 4; /* [15:12] */ + u32 osch_tlp_drop_func0 : 12; /* [27:16] */ + u32 rsv_2 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func01_u; + +/* Define the union csr_osch_tlp_drop_func23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func3 : 12; /* [11:0] */ + u32 rsv_3 : 4; /* [15:12] */ + u32 osch_tlp_drop_func2 : 12; /* [27:16] */ + u32 rsv_4 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func23_u; + +/* Define the union csr_osch_tlp_drop_func45_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func5 : 12; /* [11:0] */ + u32 rsv_5 : 4; /* [15:12] */ + u32 osch_tlp_drop_func4 : 12; /* [27:16] */ + u32 rsv_6 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func45_u; + +/* Define the union csr_osch_tlp_drop_func67_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func7 : 12; /* [11:0] */ + u32 rsv_7 : 4; /* [15:12] */ + u32 osch_tlp_drop_func6 : 12; /* [27:16] */ + u32 rsv_8 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func67_u; + +/* Define the union csr_osch_tlp_drop_func89_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func9 : 12; /* [11:0] */ + u32 rsv_9 : 4; /* [15:12] */ + u32 osch_tlp_drop_func8 : 12; /* [27:16] */ + u32 rsv_10 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func89_u; + +/* Define the union csr_osch_tlp_drop_func1011_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func11 : 12; /* [11:0] */ + u32 rsv_11 : 4; /* [15:12] */ + u32 osch_tlp_drop_func10 : 12; /* [27:16] */ + u32 rsv_12 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func1011_u; + +/* Define the union csr_osch_tlp_drop_func1213_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func13 : 12; /* [11:0] */ + u32 rsv_13 : 4; /* [15:12] */ + u32 osch_tlp_drop_func12 : 12; /* [27:16] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func1213_u; + +/* Define the union csr_osch_tlp_drop_func1415_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_func15 : 12; /* [11:0] */ + u32 rsv_15 : 4; /* [15:12] */ + u32 osch_tlp_drop_func14 : 12; /* [27:16] */ + u32 rsv_16 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_func1415_u; + +/* Define the union csr_osch_ceqe_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ceqe_drop_cnt : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ceqe_drop_cnt_u; + +/* Define the union csr_osch_ceqe_pi_overflow_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ceqe_pi_overfl_qid : 12; /* [11:0] */ + u32 rsv_18 : 19; /* [30:12] */ + u32 osch_ceqe_pi_overfl : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ceqe_pi_overflow_u; + +/* Define the union csr_osch_fifo_overflow_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_overflow_id : 6; /* [5:0] */ + u32 rsv_19 : 25; /* [30:6] */ + u32 osch_fifo_overflow : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_overflow_low_u; + +/* Define the union csr_osch_req_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_port_busy_src : 30; /* [29:0] */ + u32 rsv_20 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_req_timeout_u; + +/* Define the union csr_osch_fifo_empt_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_empty_high : 28; /* [27:0] */ + u32 rsv_21 : 3; /* [30:28] */ + u32 osch_empty : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_empt_high_u; + +/* Define the union csr_osch_fifo_empt_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_empty_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_empt_low_u; + +/* Define the union csr_osch_fifo_afull_high_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_afull_high : 28; /* [27:0] */ + u32 rsv_22 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_afull_high_u; + +/* Define the union csr_osch_fifo_afull_low_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_afull_low : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_afull_low_u; + +/* Define the union csr_osch_payload_fifo_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo_ctrl_all_port : 7; /* [6:0] */ + u32 rsv_23 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_payload_fifo_ctrl_u; + +/* Define the union csr_osch_msi_tx_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_msi_tx_fifo_ctrl_port3 : 7; /* [6:0] */ + u32 rsv_24 : 1; /* [7] */ + u32 osch_msi_tx_fifo_ctrl_port2 : 7; /* [14:8] */ + u32 rsv_25 : 1; /* [15] */ + u32 osch_msi_tx_fifo_ctrl_port1 : 7; /* [22:16] */ + u32 rsv_26 : 1; /* [23] */ + u32 osch_msi_tx_fifo_ctrl_port0 : 7; /* [30:24] */ + u32 rsv_27 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_msi_tx_fifo_ctrl0_u; + +/* Define the union csr_osch_msi_tx_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_msi_tx_fifo_ctrl_port4 : 7; /* [6:0] */ + u32 rsv_28 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_msi_tx_fifo_ctrl1_u; + +/* Define the union csr_osch_atomic_tx_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_atomic_tx_fifo_ctrl_port3 : 7; /* [6:0] */ + u32 rsv_29 : 1; /* [7] */ + u32 osch_atomic_tx_fifo_ctrl_port2 : 7; /* [14:8] */ + u32 rsv_30 : 1; /* [15] */ + u32 osch_atomic_tx_fifo_ctrl_port1 : 7; /* [22:16] */ + u32 rsv_31 : 1; /* [23] */ + u32 osch_atomic_tx_fifo_ctrl_port0 : 7; /* [30:24] */ + u32 rsv_32 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_atomic_tx_fifo_ctrl0_u; + +/* Define the union csr_osch_atomic_tx_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_atomic_tx_fifo_ctrl_port4 : 7; /* [6:0] */ + u32 rsv_33 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_atomic_tx_fifo_ctrl1_u; + +/* Define the union csr_osch_ceqe_tx_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ceqe_tx_fifo_ctrl_port3 : 7; /* [6:0] */ + u32 rsv_34 : 1; /* [7] */ + u32 osch_ceqe_tx_fifo_ctrl_port2 : 7; /* [14:8] */ + u32 rsv_35 : 1; /* [15] */ + u32 osch_ceqe_tx_fifo_ctrl_port1 : 7; /* [22:16] */ + u32 rsv_36 : 1; /* [23] */ + u32 osch_ceqe_tx_fifo_ctrl_port0 : 7; /* [30:24] */ + u32 rsv_37 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ceqe_tx_fifo_ctrl0_u; + +/* Define the union csr_osch_ceqe_tx_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ceqe_tx_fifo_ctrl_port4 : 7; /* [6:0] */ + u32 rsv_38 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ceqe_tx_fifo_ctrl1_u; + +/* Define the union csr_osch_cpld_tx_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpld_tx_fifo_ctrl_port3 : 6; /* [5:0] */ + u32 rsv_39 : 2; /* [7:6] */ + u32 osch_cpld_tx_fifo_ctrl_port2 : 6; /* [13:8] */ + u32 rsv_40 : 2; /* [15:14] */ + u32 osch_cpld_tx_fifo_ctrl_port1 : 6; /* [21:16] */ + u32 rsv_41 : 2; /* [23:22] */ + u32 osch_cpld_tx_fifo_ctrl_port0 : 6; /* [29:24] */ + u32 rsv_42 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpld_tx_fifo_ctrl0_u; + +/* Define the union csr_osch_cpld_tx_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpld_tx_fifo_ctrl_port4 : 6; /* [5:0] */ + u32 rsv_43 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpld_tx_fifo_ctrl1_u; + +/* Define the union csr_osch_fifo_empt_tophigh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_empty_tophigh : 14; /* [13:0] */ + u32 rsv_44 : 2; /* [15:14] */ + u32 osch_port_pipe_empty : 5; /* [20:16] */ + u32 osch_port_sch_pipe_empty : 2; /* [22:21] */ + u32 rsv_45 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_empt_tophigh_u; + +/* Define the union csr_osch_fifo_afull_tophigh_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_fifo_afull_tophigh : 14; /* [13:0] */ + u32 rsv_46 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_fifo_afull_tophigh_u; + +/* Define the union csr_osch_cpath_q0_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q0_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_cpath_q0_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_cpath_q0_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_cpath_q0_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q0_fifo_ctrl0_u; + +/* Define the union csr_osch_cpath_q0_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q0_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q0_fifo_ctrl1_u; + +/* Define the union csr_osch_cpath_q1_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q1_fifo_ctrl_port2 : 9; /* [8:0] */ + u32 osch_cpath_q1_fifo_ctrl_port1 : 9; /* [17:9] */ + u32 osch_cpath_q1_fifo_ctrl_port0 : 9; /* [26:18] */ + u32 rsv_48 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q1_fifo_ctrl0_u; + +/* Define the union csr_osch_cpath_q1_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q1_fifo_ctrl_port4 : 9; /* [8:0] */ + u32 osch_cpath_q1_fifo_ctrl_port3 : 9; /* [17:9] */ + u32 rsv_49 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q1_fifo_ctrl1_u; + +/* Define the union csr_osch_cpath_q2_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q2_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_cpath_q2_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_cpath_q2_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_cpath_q2_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q2_fifo_ctrl0_u; + +/* Define the union csr_osch_cpath_q2_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q2_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_50 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_cpath_q2_fifo_ctrl1_u; + +/* Define the union csr_osch_dpath_q0_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q0_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_dpath_q0_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_dpath_q0_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_dpath_q0_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q0_fifo_ctrl0_u; + +/* Define the union csr_osch_dpath_q0_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q0_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_51 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q0_fifo_ctrl1_u; + +/* Define the union csr_osch_dpath_q1_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q1_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_dpath_q1_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_dpath_q1_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_dpath_q1_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q1_fifo_ctrl0_u; + +/* Define the union csr_osch_dpath_q1_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q1_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_52 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q1_fifo_ctrl1_u; + +/* Define the union csr_osch_dpath_q2_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q2_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_dpath_q2_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_dpath_q2_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_dpath_q2_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q2_fifo_ctrl0_u; + +/* Define the union csr_osch_dpath_q2_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q2_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_53 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q2_fifo_ctrl1_u; + +/* Define the union csr_osch_dpath_q3_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q3_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_dpath_q3_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_dpath_q3_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_dpath_q3_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q3_fifo_ctrl0_u; + +/* Define the union csr_osch_dpath_q3_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q3_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_54 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q3_fifo_ctrl1_u; + +/* Define the union csr_osch_dpath_q4_fifo_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q4_fifo_ctrl_port3 : 8; /* [7:0] */ + u32 osch_dpath_q4_fifo_ctrl_port2 : 8; /* [15:8] */ + u32 osch_dpath_q4_fifo_ctrl_port1 : 8; /* [23:16] */ + u32 osch_dpath_q4_fifo_ctrl_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q4_fifo_ctrl0_u; + +/* Define the union csr_osch_dpath_q4_fifo_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q4_fifo_ctrl_port4 : 8; /* [7:0] */ + u32 rsv_55 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dpath_q4_fifo_ctrl1_u; + +/* Define the union csr_osch_reserved0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_resved0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_reserved0_u; + +/* Define the union csr_osch_reserved1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_resved1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_reserved1_u; + +/* Define the union csr_osch_reserved2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_resved2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_reserved2_u; + +/* Define the union csr_glb_post_head_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_post_head_credit : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_post_head_credit_u; + +/* Define the union csr_glb_post_payload_credit_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_post_payload_credit_h : 16; /* [15:0] */ + u32 rsv_56 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_post_payload_credit_h_u; + +/* Define the union csr_glb_post_payload_credit_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_post_payload_credit_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_post_payload_credit_l_u; + +/* Define the union csr_glb_non_post_head_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_post_head_credit : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_non_post_head_credit_u; + +/* Define the union csr_glb_non_post_payload_credit_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_post_payload_credit_h : 16; /* [15:0] */ + u32 rsv_57 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_non_post_payload_credit_h_u; + +/* Define the union csr_glb_non_post_payload_credit_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_non_post_payload_credit_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_non_post_payload_credit_l_u; + +/* Define the union csr_glb_cpl_head_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpl_head_credit : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpl_head_credit_u; + +/* Define the union csr_glb_cpl_payload_credit_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpl_payload_credit_h : 16; /* [15:0] */ + u32 rsv_58 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpl_payload_credit_h_u; + +/* Define the union csr_glb_cpl_payload_credit_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_cpl_payload_credit_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cpl_payload_credit_l_u; + +/* Define the union csr_glb_osch_ceqe_in_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_ceqe_in_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_ceqe_in_cnt_u; + +/* Define the union csr_glb_osch_ceqe_out_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_ceqe_out_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_ceqe_out_cnt_u; + +/* Define the union csr_glb_ceqe_drop_tail_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ceqe_drop_tail : 5; /* [4:0] */ + u32 ceqe_cls_glb_offs_drop_en : 1; /* [5] */ + u32 rsv_59 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_ceqe_drop_tail_u; + +/* Define the union csr_osch_tlp_post_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_post_count_port0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_post_cnt_port0_u; + +/* Define the union csr_osch_tlp_post_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_post_count_port1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_post_cnt_port1_u; + +/* Define the union csr_osch_tlp_post_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_post_count_port2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_post_cnt_port2_u; + +/* Define the union csr_osch_tlp_post_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_post_count_port3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_post_cnt_port3_u; + +/* Define the union csr_osch_tlp_post_cnt_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_post_count_port4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_post_cnt_port4_u; + +/* Define the union csr_osch_tlp_non_post_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_non_post_count_port0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_non_post_cnt_port0_u; + +/* Define the union csr_osch_tlp_non_post_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_non_post_count_port1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_non_post_cnt_port1_u; + +/* Define the union csr_osch_tlp_non_post_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_non_post_count_port2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_non_post_cnt_port2_u; + +/* Define the union csr_osch_tlp_non_post_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_non_post_count_port3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_non_post_cnt_port3_u; + +/* Define the union csr_osch_tlp_non_post_cnt_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_non_post_count_port4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_non_post_cnt_port4_u; + +/* Define the union csr_osch_tlp_cpl_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_cpl_count_port0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_cpl_cnt_port0_u; + +/* Define the union csr_osch_tlp_cpl_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_cpl_count_port1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_cpl_cnt_port1_u; + +/* Define the union csr_osch_tlp_cpl_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_cpl_count_port2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_cpl_cnt_port2_u; + +/* Define the union csr_osch_tlp_cpl_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_cpl_count_port3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_cpl_cnt_port3_u; + +/* Define the union csr_osch_tlp_cpl_cnt_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_cpl_count_port4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_cpl_cnt_port4_u; + +/* Define the union csr_osch_int_ceq_credit_port01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_int_ceq_credit_port1 : 9; /* [8:0] */ + u32 rsv_60 : 7; /* [15:9] */ + u32 osch_int_ceq_credit_port0 : 9; /* [24:16] */ + u32 rsv_61 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_int_ceq_credit_port01_u; + +/* Define the union csr_osch_int_ceq_credit_port23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_int_ceq_credit_port3 : 9; /* [8:0] */ + u32 rsv_62 : 7; /* [15:9] */ + u32 osch_int_ceq_credit_port2 : 9; /* [24:16] */ + u32 rsv_63 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_int_ceq_credit_port23_u; + +/* Define the union csr_osch_int_ceq_credit_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_int_ceq_credit_port4 : 9; /* [8:0] */ + u32 rsv_64 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_int_ceq_credit_port4_u; + +/* Define the union csr_osch_esch_dpath_bp_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_bp_q4 : 5; /* [4:0] */ + u32 osch_esch_dpath_bp_q3 : 5; /* [9:5] */ + u32 osch_esch_dpath_bp_q2 : 5; /* [14:10] */ + u32 osch_esch_dpath_bp_q1 : 5; /* [19:15] */ + u32 osch_esch_dpath_bp_q0 : 5; /* [24:20] */ + u32 rsv_65 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_bp_sts_u; + +/* Define the union csr_osch_esch_dpath_q0_bp_thd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q0_bp_thd_port3 : 6; /* [5:0] */ + u32 rsv_66 : 2; /* [7:6] */ + u32 osch_esch_dpath_q0_bp_thd_port2 : 6; /* [13:8] */ + u32 rsv_67 : 2; /* [15:14] */ + u32 osch_esch_dpath_q0_bp_thd_port1 : 6; /* [21:16] */ + u32 rsv_68 : 2; /* [23:22] */ + u32 osch_esch_dpath_q0_bp_thd_port0 : 6; /* [29:24] */ + u32 rsv_69 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q0_bp_thd0_u; + +/* Define the union csr_osch_esch_dpath_q0_bp_thd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q0_bp_thd_port4 : 6; /* [5:0] */ + u32 rsv_70 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q0_bp_thd1_u; + +/* Define the union csr_osch_esch_dpath_q1_bp_thd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q1_bp_thd_port3 : 6; /* [5:0] */ + u32 rsv_71 : 2; /* [7:6] */ + u32 osch_esch_dpath_q1_bp_thd_port2 : 6; /* [13:8] */ + u32 rsv_72 : 2; /* [15:14] */ + u32 osch_esch_dpath_q1_bp_thd_port1 : 6; /* [21:16] */ + u32 rsv_73 : 2; /* [23:22] */ + u32 osch_esch_dpath_q1_bp_thd_port0 : 6; /* [29:24] */ + u32 rsv_74 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q1_bp_thd0_u; + +/* Define the union csr_osch_esch_dpath_q1_bp_thd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q1_bp_thd_port4 : 6; /* [5:0] */ + u32 rsv_75 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q1_bp_thd1_u; + +/* Define the union csr_osch_esch_dpath_q2_bp_thd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q2_bp_thd_port3 : 6; /* [5:0] */ + u32 rsv_76 : 2; /* [7:6] */ + u32 osch_esch_dpath_q2_bp_thd_port2 : 6; /* [13:8] */ + u32 rsv_77 : 2; /* [15:14] */ + u32 osch_esch_dpath_q2_bp_thd_port1 : 6; /* [21:16] */ + u32 rsv_78 : 2; /* [23:22] */ + u32 osch_esch_dpath_q2_bp_thd_port0 : 6; /* [29:24] */ + u32 rsv_79 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q2_bp_thd0_u; + +/* Define the union csr_osch_esch_dpath_q2_bp_thd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q2_bp_thd_port4 : 6; /* [5:0] */ + u32 rsv_80 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q2_bp_thd1_u; + +/* Define the union csr_osch_esch_dpath_q3_bp_thd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q3_bp_thd_port3 : 6; /* [5:0] */ + u32 rsv_81 : 2; /* [7:6] */ + u32 osch_esch_dpath_q3_bp_thd_port2 : 6; /* [13:8] */ + u32 rsv_82 : 2; /* [15:14] */ + u32 osch_esch_dpath_q3_bp_thd_port1 : 6; /* [21:16] */ + u32 rsv_83 : 2; /* [23:22] */ + u32 osch_esch_dpath_q3_bp_thd_port0 : 6; /* [29:24] */ + u32 rsv_84 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q3_bp_thd0_u; + +/* Define the union csr_osch_esch_dpath_q3_bp_thd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q3_bp_thd_port4 : 6; /* [5:0] */ + u32 rsv_85 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q3_bp_thd1_u; + +/* Define the union csr_osch_esch_dpath_q4_bp_thd0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q4_bp_thd_port3 : 6; /* [5:0] */ + u32 rsv_86 : 2; /* [7:6] */ + u32 osch_esch_dpath_q4_bp_thd_port2 : 6; /* [13:8] */ + u32 rsv_87 : 2; /* [15:14] */ + u32 osch_esch_dpath_q4_bp_thd_port1 : 6; /* [21:16] */ + u32 rsv_88 : 2; /* [23:22] */ + u32 osch_esch_dpath_q4_bp_thd_port0 : 6; /* [29:24] */ + u32 rsv_89 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q4_bp_thd0_u; + +/* Define the union csr_osch_esch_dpath_q4_bp_thd1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_esch_dpath_q4_bp_thd_port4 : 6; /* [5:0] */ + u32 rsv_90 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_esch_dpath_q4_bp_thd1_u; + +/* Define the union csr_osch_perf_watch_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_perf_watch_en : 1; /* [0] */ + u32 rsv_91 : 3; /* [3:1] */ + u32 osch_perf_watch_port_idx : 3; /* [6:4] */ + u32 rsv_92 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_perf_watch_en_u; + +/* Define the union csr_osch_perf_watch_period_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_perf_watch_period : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_perf_watch_period_u; + +/* Define the union csr_osch_perf_watch_byte_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_perf_watch_byte : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_perf_watch_byte_u; + +/* Define the union csr_osch_perf_watch_tlp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_perf_watch_tlp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_perf_watch_tlp_u; + +/* Define the union csr_port_out_sch_dwrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_sch_dwrr_weight : 13; /* [12:0] */ + u32 rsv_93 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_out_sch_dwrr_weight_u; + +/* Define the union csr_port_rd_src_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_src_dwrr_weight2 : 16; /* [15:0] */ + u32 rsv_94 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_src_weight1_u; + +/* Define the union csr_port_rd_src_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_src_dwrr_weight0 : 16; /* [15:0] */ + u32 port_rd_src_dwrr_weight1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_src_weight0_u; + +/* Define the union csr_port_rd_dpath_wrr_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_dpath_wrr_weight4 : 6; /* [5:0] */ + u32 rsv_95 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_dpath_wrr_weight1_u; + +/* Define the union csr_port_rd_dpath_wrr_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_dpath_wrr_weight0 : 6; /* [5:0] */ + u32 rsv_96 : 2; /* [7:6] */ + u32 port_rd_dpath_wrr_weight1 : 6; /* [13:8] */ + u32 rsv_97 : 2; /* [15:14] */ + u32 port_rd_dpath_wrr_weight2 : 6; /* [21:16] */ + u32 rsv_98 : 2; /* [23:22] */ + u32 port_rd_dpath_wrr_weight3 : 6; /* [29:24] */ + u32 rsv_99 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_dpath_wrr_weight0_u; + +/* Define the union csr_port_rd_non_dpath_wrr_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_ndpath_wrr_weight4 : 6; /* [5:0] */ + u32 rsv_100 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_non_dpath_wrr_weight1_u; + +/* Define the union csr_port_rd_non_dpath_wrr_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_rd_ndpath_wrr_weight0 : 6; /* [5:0] */ + u32 rsv_101 : 2; /* [7:6] */ + u32 port_rd_ndpath_wrr_weight1 : 6; /* [13:8] */ + u32 rsv_102 : 2; /* [15:14] */ + u32 port_rd_ndpath_wrr_weight2 : 6; /* [21:16] */ + u32 rsv_103 : 2; /* [23:22] */ + u32 port_rd_ndpath_wrr_weight3 : 6; /* [29:24] */ + u32 rsv_104 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_rd_non_dpath_wrr_weight0_u; + +/* Define the union csr_port_wr_wrr_weight2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_wr_wrr_weight8 : 6; /* [5:0] */ + u32 rsv_105 : 2; /* [7:6] */ + u32 port_wr_wrr_weight9 : 6; /* [13:8] */ + u32 rsv_106 : 2; /* [15:14] */ + u32 port_wr_wrr_weight10 : 6; /* [21:16] */ + u32 rsv_107 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_wr_wrr_weight2_u; + +/* Define the union csr_port_wr_wrr_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_wr_wrr_weight4 : 6; /* [5:0] */ + u32 rsv_108 : 2; /* [7:6] */ + u32 port_wr_wrr_weight5 : 6; /* [13:8] */ + u32 rsv_109 : 2; /* [15:14] */ + u32 port_wr_wrr_weight6 : 6; /* [21:16] */ + u32 rsv_110 : 2; /* [23:22] */ + u32 port_wr_wrr_weight7 : 6; /* [29:24] */ + u32 rsv_111 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_wr_wrr_weight1_u; + +/* Define the union csr_port_wr_wrr_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port_wr_wrr_weight0 : 6; /* [5:0] */ + u32 rsv_112 : 2; /* [7:6] */ + u32 port_wr_wrr_weight1 : 6; /* [13:8] */ + u32 rsv_113 : 2; /* [15:14] */ + u32 port_wr_wrr_weight2 : 6; /* [21:16] */ + u32 rsv_114 : 2; /* [23:22] */ + u32 port_wr_wrr_weight3 : 6; /* [29:24] */ + u32 rsv_115 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_port_wr_wrr_weight0_u; + +/* Define the union csr_cfg_doorbell_crdt_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_doorbell_crdt_bp_th : 6; /* [5:0] */ + u32 rsv_116 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_doorbell_crdt_bp_th_u; + +/* Define the union csr_doorbell_wr_cmd_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 doorbell_wr_cmd_crdt_err : 1; /* [0] */ + u32 rsv_117 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_doorbell_wr_cmd_crdt_err_u; + +/* Define the union csr_osch_ctrl_doorbell_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ctrl_doorbell_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ctrl_doorbell_cnt_u; + +/* Define the union csr_pcie_wr_payload_crdt_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_wr_payload_crdt_cnt0 : 16; /* [15:0] */ + u32 pcie_wr_head_crdt_cnt0 : 12; /* [27:16] */ + u32 pcie_wr_payload_busy0 : 1; /* [28] */ + u32 pcie_wr_head_busy0 : 1; /* [29] */ + u32 rsv_118 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_wr_payload_crdt_cnt0_u; + +/* Define the union csr_pcie_rd_payload_crdt_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rd_payload_crdt_cnt0 : 16; /* [15:0] */ + u32 pcie_rd_head_crdt_cnt0 : 12; /* [27:16] */ + u32 pcie_rd_payload_busy0 : 1; /* [28] */ + u32 pcie_rd_head_busy0 : 1; /* [29] */ + u32 rsv_119 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rd_payload_crdt_cnt0_u; + +/* Define the union csr_pcie_cpl_payload_crdt_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_cpl_payload_crdt_cnt0 : 16; /* [15:0] */ + u32 pcie_cpl_head_crdt_cnt0 : 12; /* [27:16] */ + u32 pcie_cpl_payload_busy0 : 1; /* [28] */ + u32 pcie_cpl_head_busy0 : 1; /* [29] */ + u32 rsv_120 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cpl_payload_crdt_cnt0_u; + +/* Define the union csr_pcie_wr_payload_crdt_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_wr_payload_crdt_cnt1 : 16; /* [15:0] */ + u32 pcie_wr_head_crdt_cnt1 : 12; /* [27:16] */ + u32 pcie_wr_payload_busy1 : 1; /* [28] */ + u32 pcie_wr_head_busy1 : 1; /* [29] */ + u32 rsv_121 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_wr_payload_crdt_cnt1_u; + +/* Define the union csr_pcie_rd_payload_crdt_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rd_payload_crdt_cnt1 : 16; /* [15:0] */ + u32 pcie_rd_head_crdt_cnt1 : 12; /* [27:16] */ + u32 pcie_rd_payload_busy1 : 1; /* [28] */ + u32 pcie_rd_head_busy1 : 1; /* [29] */ + u32 rsv_122 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rd_payload_crdt_cnt1_u; + +/* Define the union csr_pcie_cpl_payload_crdt_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_cpl_payload_crdt_cnt1 : 16; /* [15:0] */ + u32 pcie_cpl_head_crdt_cnt1 : 12; /* [27:16] */ + u32 pcie_cpl_payload_busy1 : 1; /* [28] */ + u32 pcie_cpl_head_busy1 : 1; /* [29] */ + u32 rsv_123 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cpl_payload_crdt_cnt1_u; + +/* Define the union csr_pcie_wr_payload_crdt_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_wr_payload_crdt_cnt2 : 16; /* [15:0] */ + u32 pcie_wr_head_crdt_cnt2 : 12; /* [27:16] */ + u32 pcie_wr_payload_busy2 : 1; /* [28] */ + u32 pcie_wr_head_busy2 : 1; /* [29] */ + u32 rsv_124 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_wr_payload_crdt_cnt2_u; + +/* Define the union csr_pcie_rd_payload_crdt_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rd_payload_crdt_cnt2 : 16; /* [15:0] */ + u32 pcie_rd_head_crdt_cnt2 : 12; /* [27:16] */ + u32 pcie_rd_payload_busy2 : 1; /* [28] */ + u32 pcie_rd_head_busy2 : 1; /* [29] */ + u32 rsv_125 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rd_payload_crdt_cnt2_u; + +/* Define the union csr_pcie_cpl_payload_crdt_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_cpl_payload_crdt_cnt2 : 16; /* [15:0] */ + u32 pcie_cpl_head_crdt_cnt2 : 12; /* [27:16] */ + u32 pcie_cpl_payload_busy2 : 1; /* [28] */ + u32 pcie_cpl_head_busy2 : 1; /* [29] */ + u32 rsv_126 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cpl_payload_crdt_cnt2_u; + +/* Define the union csr_pcie_wr_payload_crdt_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_wr_payload_crdt_cnt3 : 16; /* [15:0] */ + u32 pcie_wr_head_crdt_cnt3 : 12; /* [27:16] */ + u32 pcie_wr_payload_busy3 : 1; /* [28] */ + u32 pcie_wr_head_busy3 : 1; /* [29] */ + u32 rsv_127 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_wr_payload_crdt_cnt3_u; + +/* Define the union csr_pcie_rd_payload_crdt_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rd_payload_crdt_cnt3 : 16; /* [15:0] */ + u32 pcie_rd_head_crdt_cnt3 : 12; /* [27:16] */ + u32 pcie_rd_payload_busy3 : 1; /* [28] */ + u32 pcie_rd_head_busy3 : 1; /* [29] */ + u32 rsv_128 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rd_payload_crdt_cnt3_u; + +/* Define the union csr_pcie_cpl_payload_crdt_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_cpl_payload_crdt_cnt3 : 16; /* [15:0] */ + u32 pcie_cpl_head_crdt_cnt3 : 12; /* [27:16] */ + u32 pcie_cpl_payload_busy3 : 1; /* [28] */ + u32 pcie_cpl_head_busy3 : 1; /* [29] */ + u32 rsv_129 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cpl_payload_crdt_cnt3_u; + +/* Define the union csr_pcie_wr_payload_crdt_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_wr_payload_crdt_cnt4 : 16; /* [15:0] */ + u32 pcie_wr_head_crdt_cnt4 : 12; /* [27:16] */ + u32 pcie_wr_payload_busy4 : 1; /* [28] */ + u32 pcie_wr_head_busy4 : 1; /* [29] */ + u32 rsv_130 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_wr_payload_crdt_cnt4_u; + +/* Define the union csr_pcie_rd_payload_crdt_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_rd_payload_crdt_cnt4 : 16; /* [15:0] */ + u32 pcie_rd_head_crdt_cnt4 : 12; /* [27:16] */ + u32 pcie_rd_payload_busy4 : 1; /* [28] */ + u32 pcie_rd_head_busy4 : 1; /* [29] */ + u32 rsv_131 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_rd_payload_crdt_cnt4_u; + +/* Define the union csr_pcie_cpl_payload_crdt_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pcie_cpl_payload_crdt_cnt4 : 16; /* [15:0] */ + u32 pcie_cpl_head_crdt_cnt4 : 12; /* [27:16] */ + u32 pcie_cpl_payload_busy4 : 1; /* [28] */ + u32 pcie_cpl_head_busy4 : 1; /* [29] */ + u32 rsv_132 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pcie_cpl_payload_crdt_cnt4_u; + +/* Define the union csr_osch_ecc_inj_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_cpld_fifo_inj : 10; /* [9:0] */ + u32 cpi_osch_nl2nic_req_mem_inj : 10; /* [19:10] */ + u32 cpi_osch_ceqe_tx_fifo_inj : 10; /* [29:20] */ + u32 rsv_133 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_0_u; + +/* Define the union csr_osch_ecc_inj_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_dpath_q0_fifo_inj : 10; /* [9:0] */ + u32 cpi_osch_dpath_q1_fifo_inj : 10; /* [19:10] */ + u32 cpi_osch_dpath_q2_fifo_inj : 10; /* [29:20] */ + u32 rsv_134 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_1_u; + +/* Define the union csr_osch_ecc_inj_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_dpath_q3_fifo_inj : 10; /* [9:0] */ + u32 cpi_osch_dpath_q4_fifo_inj : 10; /* [19:10] */ + u32 cpi_osch_atomic_tx_fifo_inj : 10; /* [29:20] */ + u32 rsv_135 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_2_u; + +/* Define the union csr_osch_ecc_inj_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_cpath_q0_fifo_inj : 10; /* [9:0] */ + u32 cpi_osch_cpath_q1_fifo_inj : 10; /* [19:10] */ + u32 cpi_osch_cpath_q2_fifo_inj : 10; /* [29:20] */ + u32 rsv_136 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_3_u; + +/* Define the union csr_osch_ecc_inj_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_msi_tx_fifo_inj : 10; /* [9:0] */ + u32 cpi_osch_atomic64_fifo_inj : 10; /* [19:10] */ + u32 cpi_osch_ceqe_buf_fifo_inj : 2; /* [21:20] */ + u32 cpi_osch_payload_fifo_inj : 2; /* [23:22] */ + u32 cpi_osch_payload_fifo1_inj : 2; /* [25:24] */ + u32 cpi_osch_payload_fifo_hva_inj : 2; /* [27:26] */ + u32 cpi_osch_payload_fifo1_hva_inj : 2; /* [29:28] */ + u32 cpi_osch_doorbell_fifo_inj : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_4_u; + +/* Define the union csr_osch_ecc_inj_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_osch_payload_fifo_np_inj : 2; /* [1:0] */ + u32 cpi_osch_payload_fifo1_np_inj : 2; /* [3:2] */ + u32 cpi_osch_payload_fifo_hva_np_inj : 2; /* [5:4] */ + u32 cpi_osch_payload_fifo1_hva_np_inj : 2; /* [7:6] */ + u32 rsv_137 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_inj_5_u; + +/* Define the union csr_osch_ecc_int_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpld_fifo_ecc_err : 10; /* [9:0] */ + u32 osch_nl2nic_req_mem_ecc_err : 10; /* [19:10] */ + u32 osch_ceqe_tx_fifo_ecc_err : 10; /* [29:20] */ + u32 rsv_138 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_0_u; + +/* Define the union csr_osch_ecc_int_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q0_fifo_ecc_err : 10; /* [9:0] */ + u32 osch_dpath_q1_fifo_ecc_err : 10; /* [19:10] */ + u32 osch_dpath_q2_fifo_ecc_err : 10; /* [29:20] */ + u32 rsv_139 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_1_u; + +/* Define the union csr_osch_ecc_int_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q3_fifo_ecc_err : 10; /* [9:0] */ + u32 osch_dpath_q4_fifo_ecc_err : 10; /* [19:10] */ + u32 osch_atomic_tx_fifo_ecc_err : 10; /* [29:20] */ + u32 rsv_140 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_2_u; + +/* Define the union csr_osch_ecc_int_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q0_fifo_ecc_err : 10; /* [9:0] */ + u32 osch_cpath_q1_fifo_ecc_err : 10; /* [19:10] */ + u32 osch_cpath_q2_fifo_ecc_err : 10; /* [29:20] */ + u32 rsv_141 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_3_u; + +/* Define the union csr_osch_ecc_int_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_msi_tx_fifo_ecc_err : 10; /* [9:0] */ + u32 osch_atomic64_fifo_ecc_err : 10; /* [19:10] */ + u32 osch_ceqe_buf_fifo_ecc_err : 2; /* [21:20] */ + u32 osch_payload_fifo_ecc_err : 2; /* [23:22] */ + u32 osch_payload_fifo1_ecc_err : 2; /* [25:24] */ + u32 osch_payload_fifo_hva_ecc_err : 2; /* [27:26] */ + u32 osch_payload_fifo1_hva_ecc_err : 2; /* [29:28] */ + u32 osch_doorbell_fifo_ecc_err : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_4_u; + +/* Define the union csr_osch_ecc_int_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo_np_ecc_err : 2; /* [1:0] */ + u32 osch_payload_fifo1_np_ecc_err : 2; /* [3:2] */ + u32 osch_payload_fifo_hva_np_ecc_err : 2; /* [5:4] */ + u32 osch_payload_fifo1_hva_np_ecc_err : 2; /* [7:6] */ + u32 rsv_142 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_5_u; + +/* Define the union csr_osch_ecc_int_en_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpld_fifo_ecc_int_en : 10; /* [9:0] */ + u32 osch_nl2nic_req_mem_ecc_int_en : 10; /* [19:10] */ + u32 osch_ceqe_tx_fifo_ecc_int_en : 10; /* [29:20] */ + u32 rsv_143 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_0_u; + +/* Define the union csr_osch_ecc_int_en_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q0_fifo_ecc_int_en : 10; /* [9:0] */ + u32 osch_dpath_q1_fifo_ecc_int_en : 10; /* [19:10] */ + u32 osch_dpath_q2_fifo_ecc_int_en : 10; /* [29:20] */ + u32 rsv_144 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_1_u; + +/* Define the union csr_osch_ecc_int_en_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dpath_q3_fifo_ecc_int_en : 10; /* [9:0] */ + u32 osch_dpath_q4_fifo_ecc_int_en : 10; /* [19:10] */ + u32 osch_atomic_tx_fifo_ecc_int_en : 10; /* [29:20] */ + u32 rsv_145 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_2_u; + +/* Define the union csr_osch_ecc_int_en_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_cpath_q0_fifo_ecc_int_en : 10; /* [9:0] */ + u32 osch_cpath_q1_fifo_ecc_int_en : 10; /* [19:10] */ + u32 osch_cpath_q2_fifo_ecc_int_en : 10; /* [29:20] */ + u32 rsv_146 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_3_u; + +/* Define the union csr_osch_ecc_int_en_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_msi_tx_fifo_ecc_int_en : 10; /* [9:0] */ + u32 osch_atomic64_fifo_ecc_int_en : 10; /* [19:10] */ + u32 osch_ceqe_buf_fifo_ecc_int_en : 2; /* [21:20] */ + u32 osch_payload_fifo_ecc_int_en : 2; /* [23:22] */ + u32 osch_payload_fifo1_ecc_int_en : 2; /* [25:24] */ + u32 osch_payload_fifo_hva_ecc_int_en : 2; /* [27:26] */ + u32 osch_payload_fifo1_hva_ecc_int_en : 2; /* [29:28] */ + u32 osch_doorbell_fifo_ecc_int_en : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_4_u; + +/* Define the union csr_osch_ecc_int_en_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo_np_ecc_int_en : 2; /* [1:0] */ + u32 osch_payload_fifo1_np_ecc_int_en : 2; /* [3:2] */ + u32 osch_payload_fifo_hva_np_ecc_int_en : 2; /* [5:4] */ + u32 osch_payload_fifo1_hva_np_ecc_int_en : 2; /* [7:6] */ + u32 rsv_147 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_int_en_5_u; + +/* Define the union csr_osch_ecc_err_addr_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo1_ecc_erraddr : 10; /* [9:0] */ + u32 osch_payload_fifo_hva_ecc_erraddr : 10; /* [19:10] */ + u32 osch_payload_fifo1_hva_ecc_erraddr : 10; /* [29:20] */ + u32 rsv_148 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_0_u; + +/* Define the union csr_osch_ecc_err_addr_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_port0_ecc_erraddr : 10; /* [9:0] */ + u32 osch_ceqe_buf_ecc_erraddr : 12; /* [21:10] */ + u32 osch_payload_fifo_ecc_erraddr : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_1_u; + +/* Define the union csr_osch_ecc_err_addr_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_port1_ecc_erraddr : 10; /* [9:0] */ + u32 osch_port2_ecc_erraddr : 10; /* [19:10] */ + u32 osch_port3_ecc_erraddr : 10; /* [29:20] */ + u32 rsv_149 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_2_u; + +/* Define the union csr_osch_ecc_err_addr_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_port4_ecc_erraddr : 10; /* [9:0] */ + u32 osch_payload_fifo1_hva_np_ecc_erraddr : 10; /* [19:10] */ + u32 osch_doorbell_fifo_ecc_erraddr : 10; /* [29:20] */ + u32 rsv_150 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_3_u; + +/* Define the union csr_osch_ecc_err_addr_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo_np_ecc_erraddr : 10; /* [9:0] */ + u32 osch_payload_fifo1_np_ecc_erraddr : 10; /* [19:10] */ + u32 osch_payload_fifo_hva_np_ecc_erraddr : 10; /* [29:20] */ + u32 rsv_151 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_4_u; + +/* Define the union csr_osch_ecc_err_addr_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_ecc_err_addr_port0_sel : 4; /* [3:0] */ + u32 osch_ecc_err_addr_port1_sel : 4; /* [7:4] */ + u32 osch_ecc_err_addr_port2_sel : 4; /* [11:8] */ + u32 osch_ecc_err_addr_port3_sel : 4; /* [15:12] */ + u32 osch_ecc_err_addr_port4_sel : 4; /* [19:16] */ + u32 rsv_152 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_ecc_err_addr_sel_u; + +/* Define the union csr_osch_overflow_int_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic64_tx_fifo_overf : 5; /* [4:0] */ + u32 payload_fifo_hva_overf_np : 1; /* [5] */ + u32 payload_fifo1_hva_overf_np : 1; /* [6] */ + u32 payload_fifo1_overf_np : 1; /* [7] */ + u32 payload_fifo_overf_np : 1; /* [8] */ + u32 payload_fifo_hva_overf : 1; /* [9] */ + u32 payload_fifo1_hva_overf : 1; /* [10] */ + u32 payload_fifo1_overf : 1; /* [11] */ + u32 dbell_fifo_overf : 1; /* [12] */ + u32 payload_fifo_overf : 1; /* [13] */ + u32 rsv_153 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_0_u; + +/* Define the union csr_osch_overflow_int_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_q2_fifo_overf : 5; /* [4:0] */ + u32 cpath_q1_fifo_overf : 5; /* [9:5] */ + u32 cpath_q0_fifo_overf : 5; /* [14:10] */ + u32 ceqe_tx_fifo_overf : 5; /* [19:15] */ + u32 atomic_tx_fifo_overf : 5; /* [24:20] */ + u32 msi_tx_fifo_overf : 5; /* [29:25] */ + u32 rsv_154 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_1_u; + +/* Define the union csr_osch_overflow_int_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpld_fifo_overf : 5; /* [4:0] */ + u32 dpath_q4_fifo_overf : 5; /* [9:5] */ + u32 dpath_q3_fifo_overf : 5; /* [14:10] */ + u32 dpath_q2_fifo_overf : 5; /* [19:15] */ + u32 dpath_q1_fifo_overf : 5; /* [24:20] */ + u32 dpath_q0_fifo_overf : 5; /* [29:25] */ + u32 rsv_155 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_2_u; + +/* Define the union csr_osch_overflow_int_en_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 atomic64_tx_fifo_overf_int_en : 5; /* [4:0] */ + u32 payload_fifo_hva_overf_np_int_en : 1; /* [5] */ + u32 payload_fifo1_hva_overf_np_int_en : 1; /* [6] */ + u32 payload_fifo1_overf_np_int_en : 1; /* [7] */ + u32 payload_fifo_overf_np_int_en : 1; /* [8] */ + u32 payload_fifo_hva_overf_int_en : 1; /* [9] */ + u32 payload_fifo1_hva_overf_int_en : 1; /* [10] */ + u32 payload_fifo1_overf_int_en : 1; /* [11] */ + u32 dbell_fifo_overf_int_en : 1; /* [12] */ + u32 payload_fifo_overf_int_en : 1; /* [13] */ + u32 rsv_156 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_en_0_u; + +/* Define the union csr_osch_overflow_int_en_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpath_q2_fifo_overf_int_en : 5; /* [4:0] */ + u32 cpath_q1_fifo_overf_int_en : 5; /* [9:5] */ + u32 cpath_q0_fifo_overf_int_en : 5; /* [14:10] */ + u32 ceqe_tx_fifo_overf_int_en : 5; /* [19:15] */ + u32 atomic_tx_fifo_overf_int_en : 5; /* [24:20] */ + u32 msi_tx_fifo_overf_int_en : 5; /* [29:25] */ + u32 rsv_157 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_en_1_u; + +/* Define the union csr_osch_overflow_int_en_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpld_fifo_overf_int_en : 5; /* [4:0] */ + u32 dpath_q4_fifo_overf_int_en : 5; /* [9:5] */ + u32 dpath_q3_fifo_overf_int_en : 5; /* [14:10] */ + u32 dpath_q2_fifo_overf_int_en : 5; /* [19:15] */ + u32 dpath_q1_fifo_overf_int_en : 5; /* [24:20] */ + u32 dpath_q0_fifo_overf_int_en : 5; /* [29:25] */ + u32 rsv_158 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_overflow_int_en_2_u; + +/* Define the union csr_osch_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_port_timeout : 5; /* [4:0] */ + u32 port_sch_tlp_err : 1; /* [5] */ + u32 port_sch_tlp_err_hva : 1; /* [6] */ + u32 port_sch_tlp_err_npcpl : 1; /* [7] */ + u32 port_sch_tlp_err_hva_npcpl : 1; /* [8] */ + u32 cpi_osch_ceqe_drop_req : 1; /* [9] */ + u32 port_sch_phy_addr_err : 1; /* [10] */ + u32 port_sch_phy_addr_err_npcpl : 1; /* [11] */ + u32 rsv_159 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_crt_err_u; + +/* Define the union csr_osch_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dpath_req_drop_p : 5; /* [4:0] */ + u32 cpi_osch_int_ceq_credit_err_p : 5; /* [9:5] */ + u32 osch_loss_sopeop_err : 10; /* [19:10] */ + u32 rsv_160 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_uncrt_err_u; + +/* Define the union csr_osch_crt_err_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_port_timeout_int_en : 5; /* [4:0] */ + u32 port_sch_tlp_err_int_en : 1; /* [5] */ + u32 port_sch_tlp_err_hva_int_en : 1; /* [6] */ + u32 port_sch_tlp_err_npcpl_int_en : 1; /* [7] */ + u32 port_sch_tlp_err_hva_npcpl_int_en : 1; /* [8] */ + u32 cpi_osch_ceqe_drop_req_int_en : 1; /* [9] */ + u32 port_sch_phy_addr_err_int_en : 1; /* [10] */ + u32 port_sch_phy_addr_err_npcpl_int_en : 1; /* [11] */ + u32 rsv_161 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_crt_err_int_en_u; + +/* Define the union csr_osch_uncrt_err_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dpath_req_drop_p_int_en : 5; /* [4:0] */ + u32 cpi_osch_int_ceq_credit_err_p_int_en : 5; /* [9:5] */ + u32 osch_loss_sopeop_err_int_en : 10; /* [19:10] */ + u32 rsv_162 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_uncrt_err_int_en_u; + +/* Define the union csr_osch_active_en_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 active_en_cfg_value : 5; /* [4:0] */ + u32 active_en_cfg_enable : 5; /* [9:5] */ + u32 rsv_163 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_active_en_cfg_u; + +/* Define the union csr_osch_nl2nic_outstanding_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_non_l2nic_outstanding_bp_th : 15; /* [14:0] */ + u32 rsv_164 : 1; /* [15] */ + u32 cfg_non_l2nic_outstanding_bp_en : 5; /* [20:16] */ + u32 rsv_165 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_nl2nic_outstanding_bp_cfg_u; + +/* Define the union csr_ceq_cls_fifo_st_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ceq_cls_fifo_st_err : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ceq_cls_fifo_st_err_u; + +/* Define the union csr_glb_cqe_ci_d_chl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_ceqe_sch_period : 8; /* [7:0] */ + u32 glb_osch_non_l2nic_outstanding_cfg : 2; /* [9:8] */ + u32 rsv_166 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cqe_ci_d_chl_u; + +/* Define the union csr_glb_dma_so_ro_replace_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_dma_so_ro_cfg : 2; /* [1:0] */ + u32 rsv_167 : 2; /* [3:2] */ + u32 glb_dma_so_ro_replace_mode : 1; /* [4] */ + u32 rsv_168 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_dma_so_ro_replace_u; + +/* Define the union csr_glb_osch_rls_tag_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_rls_tag_en : 1; /* [0] */ + u32 rsv_169 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_rls_tag_en_u; + +/* Define the union csr_glb_osch_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_timeout_cfg : 15; /* [14:0] */ + u32 rsv_170 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_timeout_u; + +/* Define the union csr_glb_cp_cqe_credit_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 port4_cqe_credit_cfg : 2; /* [1:0] */ + u32 rsv_171 : 2; /* [3:2] */ + u32 port3_cqe_credit_cfg : 2; /* [5:4] */ + u32 rsv_172 : 2; /* [7:6] */ + u32 port2_cqe_credit_cfg : 2; /* [9:8] */ + u32 rsv_173 : 2; /* [11:10] */ + u32 port1_cqe_credit_cfg : 2; /* [13:12] */ + u32 rsv_174 : 2; /* [15:14] */ + u32 port0_cqe_credit_cfg : 2; /* [17:16] */ + u32 rsv_175 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_cp_cqe_credit_port_u; + +/* Define the union csr_glb_osch_addr_hi_lmt_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_hi_lmt_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_hi_lmt_h_u; + +/* Define the union csr_glb_osch_addr_hi_lmt_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_hi_lmt_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_hi_lmt_l_u; + +/* Define the union csr_glb_osch_addr_lo_lmt_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_lo_lmt_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_lo_lmt_h_u; + +/* Define the union csr_glb_osch_addr_lo_lmt_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_lo_lmt_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_lo_lmt_l_u; + +/* Define the union csr_glb_osch_addr_out_range_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_out_range_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_out_range_h_u; + +/* Define the union csr_glb_osch_addr_out_range_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_osch_addr_out_range_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_glb_osch_addr_out_range_l_u; + +/* Define the union csr_osch_payload_fifo1_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_payload_fifo1_ctrl_all_port : 7; /* [6:0] */ + u32 rsv_176 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_payload_fifo1_ctrl_u; + +/* Define the union csr_osch_dbell_fifo_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_dbell_fifo_ctrl_all_port : 7; /* [6:0] */ + u32 rsv_177 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_dbell_fifo_ctrl_u; + +/* Define the union csr_cfg_doorbell_wr_cmd_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_doorbell_wr_cmd_en : 5; /* [4:0] */ + u32 rsv_178 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_doorbell_wr_cmd_en_u; + +/* Define the union csr_cfg_doorbell_crdt_initial_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_doorbell_crdt_initial : 5; /* [4:0] */ + u32 rsv_179 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_doorbell_crdt_initial_u; + +/* Define the union csr_cfg_dpath_xts_rd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_dpath_xts_rd_chl : 5; /* [4:0] */ + u32 cfg_dpath_xts_rd_en : 1; /* [5] */ + u32 rsv_180 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_dpath_xts_rd_u; + +/* Define the union csr_cfg_round_bit_check_mod_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_round_bit_check_mod : 1; /* [0] */ + u32 rsv_181 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_round_bit_check_mod_u; + +/* Define the union csr_cfg_port1_to_port0_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port1_to_port0_mode : 1; /* [0] */ + u32 rsv_182 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_port1_to_port0_mode_u; + +/* Define the union csr_cfg_non_l2nic_loop2_edge_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_non_l2nic_loop2_edge_en : 1; /* [0] */ + u32 rsv_183 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_non_l2nic_loop2_edge_en_u; + +/* Define the union csr_cfg_cur_cpl_timeout_drop_max_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cur_cpl_timeout_drop_max : 20; /* [19:0] */ + u32 rsv_184 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_cur_cpl_timeout_drop_max_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt_port0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count_port0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt_port0_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt_port1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count_port1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt_port1_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt_port2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count_port2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt_port2_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt_port3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count_port3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt_port3_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt_port4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count_port4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt_port4_u; + +/* Define the union csr_osch_tlp_npcpl_error_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_err_count_port3 : 8; /* [7:0] */ + u32 osch_tlp_npcpl_err_count_port2 : 8; /* [15:8] */ + u32 osch_tlp_npcpl_err_count_port1 : 8; /* [23:16] */ + u32 osch_tlp_npcpl_err_count_port0 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_error_cnt0_u; + +/* Define the union csr_osch_tlp_npcpl_error_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_err_count_port4 : 8; /* [7:0] */ + u32 rsv_185 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_error_cnt1_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt0_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt1_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt2_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt3_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt4_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt5_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt6_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt7_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt8_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt9_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt10_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt11_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt12_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt13_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt14_u; + +/* Define the union csr_osch_tlp_npcpl_drop_cnt15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_npcpl_drop_count15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_npcpl_drop_cnt15_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt0_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt1_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt2_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt3_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt4_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt5_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt6_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt7_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt8_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt9_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt10_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt11_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt12_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt13_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt14_u; + +/* Define the union csr_osch_tlp_hva_p_drop_cnt15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_p_drop_count15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_p_drop_cnt15_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt0_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt1_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt2_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt3_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt4_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt5_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt6_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt7_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt8_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt9_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt10_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt11_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt12_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt13_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt14_u; + +/* Define the union csr_osch_tlp_hva_npcpl_drop_cnt15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_hva_npcpl_drop_count15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_hva_npcpl_drop_cnt15_u; + +/* Define the union csr_osch_tlp_drop_count_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_tlp_drop_count_mode : 16; /* [15:0] */ + u32 rsv_186 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_tlp_drop_count_mode_u; + +/* Define the union csr_osch_npcpl_perf_watch_byte_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_npcpl_perf_watch_byte : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_npcpl_perf_watch_byte_u; + +/* Define the union csr_osch_npcpl_perf_watch_tlp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_npcpl_perf_watch_tlp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_npcpl_perf_watch_tlp_u; + +/* Define the union csr_osch_hva_p_perf_watch_byte_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_hva_p_perf_watch_byte : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_hva_p_perf_watch_byte_u; + +/* Define the union csr_osch_hva_p_perf_watch_tlp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_hva_p_perf_watch_tlp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_hva_p_perf_watch_tlp_u; + +/* Define the union csr_osch_hva_npcpl_perf_watch_byte_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_hva_npcpl_perf_watch_byte : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_hva_npcpl_perf_watch_byte_u; + +/* Define the union csr_osch_hva_npcpl_perf_watch_tlp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 osch_hva_npcpl_perf_watch_tlp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_osch_hva_npcpl_perf_watch_tlp_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_osch_tlp_drop_cnt_port0_u osch_tlp_drop_cnt_port0; /* 0 */ + volatile csr_osch_tlp_drop_cnt_port1_u osch_tlp_drop_cnt_port1; /* 4 */ + volatile csr_osch_tlp_drop_cnt_port2_u osch_tlp_drop_cnt_port2; /* 8 */ + volatile csr_osch_tlp_drop_cnt_port3_u osch_tlp_drop_cnt_port3; /* C */ + volatile csr_osch_tlp_drop_cnt_port4_u osch_tlp_drop_cnt_port4; /* 10 */ + volatile csr_osch_tlp_error_cnt0_u osch_tlp_error_cnt0; /* 14 */ + volatile csr_osch_tlp_error_cnt1_u osch_tlp_error_cnt1; /* 18 */ + volatile csr_osch_tlp_drop_cnt0_u osch_tlp_drop_cnt0; /* 20 */ + volatile csr_osch_tlp_drop_cnt1_u osch_tlp_drop_cnt1; /* 24 */ + volatile csr_osch_tlp_drop_cnt2_u osch_tlp_drop_cnt2; /* 28 */ + volatile csr_osch_tlp_drop_cnt3_u osch_tlp_drop_cnt3; /* 2C */ + volatile csr_osch_tlp_drop_cnt4_u osch_tlp_drop_cnt4; /* 30 */ + volatile csr_osch_tlp_drop_cnt5_u osch_tlp_drop_cnt5; /* 34 */ + volatile csr_osch_tlp_drop_cnt6_u osch_tlp_drop_cnt6; /* 38 */ + volatile csr_osch_tlp_drop_cnt7_u osch_tlp_drop_cnt7; /* 3C */ + volatile csr_osch_tlp_drop_cnt8_u osch_tlp_drop_cnt8; /* 40 */ + volatile csr_osch_tlp_drop_cnt9_u osch_tlp_drop_cnt9; /* 44 */ + volatile csr_osch_tlp_drop_cnt10_u osch_tlp_drop_cnt10; /* 48 */ + volatile csr_osch_tlp_drop_cnt11_u osch_tlp_drop_cnt11; /* 4C */ + volatile csr_osch_tlp_drop_cnt12_u osch_tlp_drop_cnt12; /* 50 */ + volatile csr_osch_tlp_drop_cnt13_u osch_tlp_drop_cnt13; /* 54 */ + volatile csr_osch_tlp_drop_cnt14_u osch_tlp_drop_cnt14; /* 58 */ + volatile csr_osch_tlp_drop_cnt15_u osch_tlp_drop_cnt15; /* 5C */ + volatile csr_osch_tlp_drop_func01_u osch_tlp_drop_func01; /* 60 */ + volatile csr_osch_tlp_drop_func23_u osch_tlp_drop_func23; /* 64 */ + volatile csr_osch_tlp_drop_func45_u osch_tlp_drop_func45; /* 68 */ + volatile csr_osch_tlp_drop_func67_u osch_tlp_drop_func67; /* 6C */ + volatile csr_osch_tlp_drop_func89_u osch_tlp_drop_func89; /* 70 */ + volatile csr_osch_tlp_drop_func1011_u osch_tlp_drop_func1011; /* 74 */ + volatile csr_osch_tlp_drop_func1213_u osch_tlp_drop_func1213; /* 78 */ + volatile csr_osch_tlp_drop_func1415_u osch_tlp_drop_func1415; /* 7C */ + volatile csr_osch_ceqe_drop_cnt_u osch_ceqe_drop_cnt; /* 90 */ + volatile csr_osch_ceqe_pi_overflow_u osch_ceqe_pi_overflow; /* 94 */ + volatile csr_osch_fifo_overflow_low_u osch_fifo_overflow_low; /* 98 */ + volatile csr_osch_req_timeout_u osch_req_timeout; /* 9C */ + volatile csr_osch_fifo_empt_high_u osch_fifo_empt_high; /* A0 */ + volatile csr_osch_fifo_empt_low_u osch_fifo_empt_low; /* A4 */ + volatile csr_osch_fifo_afull_high_u osch_fifo_afull_high; /* A8 */ + volatile csr_osch_fifo_afull_low_u osch_fifo_afull_low; /* AC */ + volatile csr_osch_payload_fifo_ctrl_u osch_payload_fifo_ctrl; /* B0 */ + volatile csr_osch_msi_tx_fifo_ctrl0_u osch_msi_tx_fifo_ctrl0; /* B4 */ + volatile csr_osch_msi_tx_fifo_ctrl1_u osch_msi_tx_fifo_ctrl1; /* B8 */ + volatile csr_osch_atomic_tx_fifo_ctrl0_u osch_atomic_tx_fifo_ctrl0; /* BC */ + volatile csr_osch_atomic_tx_fifo_ctrl1_u osch_atomic_tx_fifo_ctrl1; /* C0 */ + volatile csr_osch_ceqe_tx_fifo_ctrl0_u osch_ceqe_tx_fifo_ctrl0; /* C4 */ + volatile csr_osch_ceqe_tx_fifo_ctrl1_u osch_ceqe_tx_fifo_ctrl1; /* C8 */ + volatile csr_osch_cpld_tx_fifo_ctrl0_u osch_cpld_tx_fifo_ctrl0; /* D0 */ + volatile csr_osch_cpld_tx_fifo_ctrl1_u osch_cpld_tx_fifo_ctrl1; /* D4 */ + volatile csr_osch_fifo_empt_tophigh_u osch_fifo_empt_tophigh; /* D8 */ + volatile csr_osch_fifo_afull_tophigh_u osch_fifo_afull_tophigh; /* DC */ + volatile csr_osch_cpath_q0_fifo_ctrl0_u osch_cpath_q0_fifo_ctrl0; /* F0 */ + volatile csr_osch_cpath_q0_fifo_ctrl1_u osch_cpath_q0_fifo_ctrl1; /* F4 */ + volatile csr_osch_cpath_q1_fifo_ctrl0_u osch_cpath_q1_fifo_ctrl0; /* 100 */ + volatile csr_osch_cpath_q1_fifo_ctrl1_u osch_cpath_q1_fifo_ctrl1; /* 104 */ + volatile csr_osch_cpath_q2_fifo_ctrl0_u osch_cpath_q2_fifo_ctrl0; /* 110 */ + volatile csr_osch_cpath_q2_fifo_ctrl1_u osch_cpath_q2_fifo_ctrl1; /* 114 */ + volatile csr_osch_dpath_q0_fifo_ctrl0_u osch_dpath_q0_fifo_ctrl0; /* 120 */ + volatile csr_osch_dpath_q0_fifo_ctrl1_u osch_dpath_q0_fifo_ctrl1; /* 124 */ + volatile csr_osch_dpath_q1_fifo_ctrl0_u osch_dpath_q1_fifo_ctrl0; /* 130 */ + volatile csr_osch_dpath_q1_fifo_ctrl1_u osch_dpath_q1_fifo_ctrl1; /* 134 */ + volatile csr_osch_dpath_q2_fifo_ctrl0_u osch_dpath_q2_fifo_ctrl0; /* 140 */ + volatile csr_osch_dpath_q2_fifo_ctrl1_u osch_dpath_q2_fifo_ctrl1; /* 144 */ + volatile csr_osch_dpath_q3_fifo_ctrl0_u osch_dpath_q3_fifo_ctrl0; /* 150 */ + volatile csr_osch_dpath_q3_fifo_ctrl1_u osch_dpath_q3_fifo_ctrl1; /* 154 */ + volatile csr_osch_dpath_q4_fifo_ctrl0_u osch_dpath_q4_fifo_ctrl0; /* 160 */ + volatile csr_osch_dpath_q4_fifo_ctrl1_u osch_dpath_q4_fifo_ctrl1; /* 164 */ + volatile csr_osch_reserved0_u osch_reserved0; /* 170 */ + volatile csr_osch_reserved1_u osch_reserved1; /* 174 */ + volatile csr_osch_reserved2_u osch_reserved2; /* 178 */ + volatile csr_glb_post_head_credit_u glb_post_head_credit; /* 180 */ + volatile csr_glb_post_payload_credit_h_u glb_post_payload_credit_h; /* 184 */ + volatile csr_glb_post_payload_credit_l_u glb_post_payload_credit_l; /* 188 */ + volatile csr_glb_non_post_head_credit_u glb_non_post_head_credit; /* 190 */ + volatile csr_glb_non_post_payload_credit_h_u glb_non_post_payload_credit_h; /* 194 */ + volatile csr_glb_non_post_payload_credit_l_u glb_non_post_payload_credit_l; /* 198 */ + volatile csr_glb_cpl_head_credit_u glb_cpl_head_credit; /* 1A0 */ + volatile csr_glb_cpl_payload_credit_h_u glb_cpl_payload_credit_h; /* 1A4 */ + volatile csr_glb_cpl_payload_credit_l_u glb_cpl_payload_credit_l; /* 1A8 */ + volatile csr_glb_osch_ceqe_in_cnt_u glb_osch_ceqe_in_cnt; /* 1B0 */ + volatile csr_glb_osch_ceqe_out_cnt_u glb_osch_ceqe_out_cnt; /* 1B4 */ + volatile csr_glb_ceqe_drop_tail_u glb_ceqe_drop_tail; /* 1C0 */ + volatile csr_osch_tlp_post_cnt_port0_u osch_tlp_post_cnt_port0; /* 1D0 */ + volatile csr_osch_tlp_post_cnt_port1_u osch_tlp_post_cnt_port1; /* 1D4 */ + volatile csr_osch_tlp_post_cnt_port2_u osch_tlp_post_cnt_port2; /* 1D8 */ + volatile csr_osch_tlp_post_cnt_port3_u osch_tlp_post_cnt_port3; /* 1DC */ + volatile csr_osch_tlp_post_cnt_port4_u osch_tlp_post_cnt_port4; /* 1E0 */ + volatile csr_osch_tlp_non_post_cnt_port0_u osch_tlp_non_post_cnt_port0; /* 1F0 */ + volatile csr_osch_tlp_non_post_cnt_port1_u osch_tlp_non_post_cnt_port1; /* 1F4 */ + volatile csr_osch_tlp_non_post_cnt_port2_u osch_tlp_non_post_cnt_port2; /* 1F8 */ + volatile csr_osch_tlp_non_post_cnt_port3_u osch_tlp_non_post_cnt_port3; /* 1FC */ + volatile csr_osch_tlp_non_post_cnt_port4_u osch_tlp_non_post_cnt_port4; /* 200 */ + volatile csr_osch_tlp_cpl_cnt_port0_u osch_tlp_cpl_cnt_port0; /* 210 */ + volatile csr_osch_tlp_cpl_cnt_port1_u osch_tlp_cpl_cnt_port1; /* 214 */ + volatile csr_osch_tlp_cpl_cnt_port2_u osch_tlp_cpl_cnt_port2; /* 218 */ + volatile csr_osch_tlp_cpl_cnt_port3_u osch_tlp_cpl_cnt_port3; /* 21C */ + volatile csr_osch_tlp_cpl_cnt_port4_u osch_tlp_cpl_cnt_port4; /* 220 */ + volatile csr_osch_int_ceq_credit_port01_u osch_int_ceq_credit_port01; /* 230 */ + volatile csr_osch_int_ceq_credit_port23_u osch_int_ceq_credit_port23; /* 234 */ + volatile csr_osch_int_ceq_credit_port4_u osch_int_ceq_credit_port4; /* 238 */ + volatile csr_osch_esch_dpath_bp_sts_u osch_esch_dpath_bp_sts; /* 240 */ + volatile csr_osch_esch_dpath_q0_bp_thd0_u osch_esch_dpath_q0_bp_thd0; /* 250 */ + volatile csr_osch_esch_dpath_q0_bp_thd1_u osch_esch_dpath_q0_bp_thd1; /* 254 */ + volatile csr_osch_esch_dpath_q1_bp_thd0_u osch_esch_dpath_q1_bp_thd0; /* 260 */ + volatile csr_osch_esch_dpath_q1_bp_thd1_u osch_esch_dpath_q1_bp_thd1; /* 264 */ + volatile csr_osch_esch_dpath_q2_bp_thd0_u osch_esch_dpath_q2_bp_thd0; /* 270 */ + volatile csr_osch_esch_dpath_q2_bp_thd1_u osch_esch_dpath_q2_bp_thd1; /* 274 */ + volatile csr_osch_esch_dpath_q3_bp_thd0_u osch_esch_dpath_q3_bp_thd0; /* 280 */ + volatile csr_osch_esch_dpath_q3_bp_thd1_u osch_esch_dpath_q3_bp_thd1; /* 284 */ + volatile csr_osch_esch_dpath_q4_bp_thd0_u osch_esch_dpath_q4_bp_thd0; /* 290 */ + volatile csr_osch_esch_dpath_q4_bp_thd1_u osch_esch_dpath_q4_bp_thd1; /* 294 */ + volatile csr_osch_perf_watch_en_u osch_perf_watch_en; /* 298 */ + volatile csr_osch_perf_watch_period_u osch_perf_watch_period; /* 2A0 */ + volatile csr_osch_perf_watch_byte_u osch_perf_watch_byte; /* 2A4 */ + volatile csr_osch_perf_watch_tlp_u osch_perf_watch_tlp; /* 2A8 */ + volatile csr_port_out_sch_dwrr_weight_u port_out_sch_dwrr_weight[5]; /* 300 */ + volatile csr_port_rd_src_weight1_u port_rd_src_weight1[5]; /* 304 */ + volatile csr_port_rd_src_weight0_u port_rd_src_weight0[5]; /* 308 */ + volatile csr_port_rd_dpath_wrr_weight1_u port_rd_dpath_wrr_weight1[5]; /* 30C */ + volatile csr_port_rd_dpath_wrr_weight0_u port_rd_dpath_wrr_weight0[5]; /* 310 */ + volatile csr_port_rd_non_dpath_wrr_weight1_u port_rd_non_dpath_wrr_weight1[5]; /* 314 */ + volatile csr_port_rd_non_dpath_wrr_weight0_u port_rd_non_dpath_wrr_weight0[5]; /* 318 */ + volatile csr_port_wr_wrr_weight2_u port_wr_wrr_weight2[5]; /* 320 */ + volatile csr_port_wr_wrr_weight1_u port_wr_wrr_weight1[5]; /* 324 */ + volatile csr_port_wr_wrr_weight0_u port_wr_wrr_weight0[5]; /* 328 */ + volatile csr_cfg_doorbell_crdt_bp_th_u cfg_doorbell_crdt_bp_th[5]; /* 32C */ + volatile csr_doorbell_wr_cmd_crdt_err_u doorbell_wr_cmd_crdt_err[5]; /* 330 */ + volatile csr_osch_ctrl_doorbell_cnt_u osch_ctrl_doorbell_cnt; /* 500 */ + volatile csr_pcie_wr_payload_crdt_cnt0_u pcie_wr_payload_crdt_cnt0; /* 504 */ + volatile csr_pcie_rd_payload_crdt_cnt0_u pcie_rd_payload_crdt_cnt0; /* 508 */ + volatile csr_pcie_cpl_payload_crdt_cnt0_u pcie_cpl_payload_crdt_cnt0; /* 50C */ + volatile csr_pcie_wr_payload_crdt_cnt1_u pcie_wr_payload_crdt_cnt1; /* 510 */ + volatile csr_pcie_rd_payload_crdt_cnt1_u pcie_rd_payload_crdt_cnt1; /* 514 */ + volatile csr_pcie_cpl_payload_crdt_cnt1_u pcie_cpl_payload_crdt_cnt1; /* 518 */ + volatile csr_pcie_wr_payload_crdt_cnt2_u pcie_wr_payload_crdt_cnt2; /* 51C */ + volatile csr_pcie_rd_payload_crdt_cnt2_u pcie_rd_payload_crdt_cnt2; /* 520 */ + volatile csr_pcie_cpl_payload_crdt_cnt2_u pcie_cpl_payload_crdt_cnt2; /* 524 */ + volatile csr_pcie_wr_payload_crdt_cnt3_u pcie_wr_payload_crdt_cnt3; /* 528 */ + volatile csr_pcie_rd_payload_crdt_cnt3_u pcie_rd_payload_crdt_cnt3; /* 52C */ + volatile csr_pcie_cpl_payload_crdt_cnt3_u pcie_cpl_payload_crdt_cnt3; /* 530 */ + volatile csr_pcie_wr_payload_crdt_cnt4_u pcie_wr_payload_crdt_cnt4; /* 534 */ + volatile csr_pcie_rd_payload_crdt_cnt4_u pcie_rd_payload_crdt_cnt4; /* 538 */ + volatile csr_pcie_cpl_payload_crdt_cnt4_u pcie_cpl_payload_crdt_cnt4; /* 53C */ + volatile csr_osch_ecc_inj_0_u osch_ecc_inj_0; /* 540 */ + volatile csr_osch_ecc_inj_1_u osch_ecc_inj_1; /* 544 */ + volatile csr_osch_ecc_inj_2_u osch_ecc_inj_2; /* 548 */ + volatile csr_osch_ecc_inj_3_u osch_ecc_inj_3; /* 54C */ + volatile csr_osch_ecc_inj_4_u osch_ecc_inj_4; /* 550 */ + volatile csr_osch_ecc_inj_5_u osch_ecc_inj_5; /* 554 */ + volatile csr_osch_ecc_int_0_u osch_ecc_int_0; /* 558 */ + volatile csr_osch_ecc_int_1_u osch_ecc_int_1; /* 55C */ + volatile csr_osch_ecc_int_2_u osch_ecc_int_2; /* 560 */ + volatile csr_osch_ecc_int_3_u osch_ecc_int_3; /* 564 */ + volatile csr_osch_ecc_int_4_u osch_ecc_int_4; /* 568 */ + volatile csr_osch_ecc_int_5_u osch_ecc_int_5; /* 56C */ + volatile csr_osch_ecc_int_en_0_u osch_ecc_int_en_0; /* 570 */ + volatile csr_osch_ecc_int_en_1_u osch_ecc_int_en_1; /* 574 */ + volatile csr_osch_ecc_int_en_2_u osch_ecc_int_en_2; /* 578 */ + volatile csr_osch_ecc_int_en_3_u osch_ecc_int_en_3; /* 57C */ + volatile csr_osch_ecc_int_en_4_u osch_ecc_int_en_4; /* 580 */ + volatile csr_osch_ecc_int_en_5_u osch_ecc_int_en_5; /* 584 */ + volatile csr_osch_ecc_err_addr_0_u osch_ecc_err_addr_0; /* 588 */ + volatile csr_osch_ecc_err_addr_1_u osch_ecc_err_addr_1; /* 58C */ + volatile csr_osch_ecc_err_addr_2_u osch_ecc_err_addr_2; /* 590 */ + volatile csr_osch_ecc_err_addr_3_u osch_ecc_err_addr_3; /* 594 */ + volatile csr_osch_ecc_err_addr_4_u osch_ecc_err_addr_4; /* 598 */ + volatile csr_osch_ecc_err_addr_sel_u osch_ecc_err_addr_sel; /* 59C */ + volatile csr_osch_overflow_int_0_u osch_overflow_int_0; /* 5A0 */ + volatile csr_osch_overflow_int_1_u osch_overflow_int_1; /* 5A4 */ + volatile csr_osch_overflow_int_2_u osch_overflow_int_2; /* 5A8 */ + volatile csr_osch_overflow_int_en_0_u osch_overflow_int_en_0; /* 5AC */ + volatile csr_osch_overflow_int_en_1_u osch_overflow_int_en_1; /* 5B0 */ + volatile csr_osch_overflow_int_en_2_u osch_overflow_int_en_2; /* 5B4 */ + volatile csr_osch_crt_err_u osch_crt_err; /* 5B8 */ + volatile csr_osch_uncrt_err_u osch_uncrt_err; /* 5BC */ + volatile csr_osch_crt_err_int_en_u osch_crt_err_int_en; /* 5C0 */ + volatile csr_osch_uncrt_err_int_en_u osch_uncrt_err_int_en; /* 5C4 */ + volatile csr_osch_active_en_cfg_u osch_active_en_cfg; /* 5C8 */ + volatile csr_osch_nl2nic_outstanding_bp_cfg_u osch_nl2nic_outstanding_bp_cfg; /* 5CC */ + volatile csr_ceq_cls_fifo_st_err_u ceq_cls_fifo_st_err; /* 600 */ + volatile csr_glb_cqe_ci_d_chl_u glb_cqe_ci_d_chl; /* 604 */ + volatile csr_glb_dma_so_ro_replace_u glb_dma_so_ro_replace; /* 608 */ + volatile csr_glb_osch_rls_tag_en_u glb_osch_rls_tag_en; /* 60C */ + volatile csr_glb_osch_timeout_u glb_osch_timeout; /* 610 */ + volatile csr_glb_cp_cqe_credit_port_u glb_cp_cqe_credit_port; /* 614 */ + volatile csr_glb_osch_addr_hi_lmt_h_u glb_osch_addr_hi_lmt_h; /* 618 */ + volatile csr_glb_osch_addr_hi_lmt_l_u glb_osch_addr_hi_lmt_l; /* 61C */ + volatile csr_glb_osch_addr_lo_lmt_h_u glb_osch_addr_lo_lmt_h; /* 620 */ + volatile csr_glb_osch_addr_lo_lmt_l_u glb_osch_addr_lo_lmt_l; /* 624 */ + volatile csr_glb_osch_addr_out_range_h_u glb_osch_addr_out_range_h; /* 628 */ + volatile csr_glb_osch_addr_out_range_l_u glb_osch_addr_out_range_l; /* 62C */ + volatile csr_osch_payload_fifo1_ctrl_u osch_payload_fifo1_ctrl; /* 630 */ + volatile csr_osch_dbell_fifo_ctrl_u osch_dbell_fifo_ctrl; /* 634 */ + volatile csr_cfg_doorbell_wr_cmd_en_u cfg_doorbell_wr_cmd_en; /* 638 */ + volatile csr_cfg_doorbell_crdt_initial_u cfg_doorbell_crdt_initial; /* 63C */ + volatile csr_cfg_dpath_xts_rd_u cfg_dpath_xts_rd; /* 640 */ + volatile csr_cfg_round_bit_check_mod_u cfg_round_bit_check_mod; /* 650 */ + volatile csr_cfg_port1_to_port0_mode_u cfg_port1_to_port0_mode; /* 660 */ + volatile csr_cfg_non_l2nic_loop2_edge_en_u cfg_non_l2nic_loop2_edge_en; /* 670 */ + volatile csr_cfg_cur_cpl_timeout_drop_max_u cfg_cur_cpl_timeout_drop_max; /* 674 */ + volatile csr_osch_tlp_npcpl_drop_cnt_port0_u osch_tlp_npcpl_drop_cnt_port0; /* 700 */ + volatile csr_osch_tlp_npcpl_drop_cnt_port1_u osch_tlp_npcpl_drop_cnt_port1; /* 704 */ + volatile csr_osch_tlp_npcpl_drop_cnt_port2_u osch_tlp_npcpl_drop_cnt_port2; /* 708 */ + volatile csr_osch_tlp_npcpl_drop_cnt_port3_u osch_tlp_npcpl_drop_cnt_port3; /* 70C */ + volatile csr_osch_tlp_npcpl_drop_cnt_port4_u osch_tlp_npcpl_drop_cnt_port4; /* 710 */ + volatile csr_osch_tlp_npcpl_error_cnt0_u osch_tlp_npcpl_error_cnt0; /* 714 */ + volatile csr_osch_tlp_npcpl_error_cnt1_u osch_tlp_npcpl_error_cnt1; /* 718 */ + volatile csr_osch_tlp_npcpl_drop_cnt0_u osch_tlp_npcpl_drop_cnt0; /* 720 */ + volatile csr_osch_tlp_npcpl_drop_cnt1_u osch_tlp_npcpl_drop_cnt1; /* 724 */ + volatile csr_osch_tlp_npcpl_drop_cnt2_u osch_tlp_npcpl_drop_cnt2; /* 728 */ + volatile csr_osch_tlp_npcpl_drop_cnt3_u osch_tlp_npcpl_drop_cnt3; /* 72C */ + volatile csr_osch_tlp_npcpl_drop_cnt4_u osch_tlp_npcpl_drop_cnt4; /* 730 */ + volatile csr_osch_tlp_npcpl_drop_cnt5_u osch_tlp_npcpl_drop_cnt5; /* 734 */ + volatile csr_osch_tlp_npcpl_drop_cnt6_u osch_tlp_npcpl_drop_cnt6; /* 738 */ + volatile csr_osch_tlp_npcpl_drop_cnt7_u osch_tlp_npcpl_drop_cnt7; /* 73C */ + volatile csr_osch_tlp_npcpl_drop_cnt8_u osch_tlp_npcpl_drop_cnt8; /* 740 */ + volatile csr_osch_tlp_npcpl_drop_cnt9_u osch_tlp_npcpl_drop_cnt9; /* 744 */ + volatile csr_osch_tlp_npcpl_drop_cnt10_u osch_tlp_npcpl_drop_cnt10; /* 748 */ + volatile csr_osch_tlp_npcpl_drop_cnt11_u osch_tlp_npcpl_drop_cnt11; /* 74C */ + volatile csr_osch_tlp_npcpl_drop_cnt12_u osch_tlp_npcpl_drop_cnt12; /* 750 */ + volatile csr_osch_tlp_npcpl_drop_cnt13_u osch_tlp_npcpl_drop_cnt13; /* 754 */ + volatile csr_osch_tlp_npcpl_drop_cnt14_u osch_tlp_npcpl_drop_cnt14; /* 758 */ + volatile csr_osch_tlp_npcpl_drop_cnt15_u osch_tlp_npcpl_drop_cnt15; /* 75C */ + volatile csr_osch_tlp_hva_p_drop_cnt0_u osch_tlp_hva_p_drop_cnt0; /* 760 */ + volatile csr_osch_tlp_hva_p_drop_cnt1_u osch_tlp_hva_p_drop_cnt1; /* 764 */ + volatile csr_osch_tlp_hva_p_drop_cnt2_u osch_tlp_hva_p_drop_cnt2; /* 768 */ + volatile csr_osch_tlp_hva_p_drop_cnt3_u osch_tlp_hva_p_drop_cnt3; /* 76C */ + volatile csr_osch_tlp_hva_p_drop_cnt4_u osch_tlp_hva_p_drop_cnt4; /* 770 */ + volatile csr_osch_tlp_hva_p_drop_cnt5_u osch_tlp_hva_p_drop_cnt5; /* 774 */ + volatile csr_osch_tlp_hva_p_drop_cnt6_u osch_tlp_hva_p_drop_cnt6; /* 778 */ + volatile csr_osch_tlp_hva_p_drop_cnt7_u osch_tlp_hva_p_drop_cnt7; /* 77C */ + volatile csr_osch_tlp_hva_p_drop_cnt8_u osch_tlp_hva_p_drop_cnt8; /* 780 */ + volatile csr_osch_tlp_hva_p_drop_cnt9_u osch_tlp_hva_p_drop_cnt9; /* 784 */ + volatile csr_osch_tlp_hva_p_drop_cnt10_u osch_tlp_hva_p_drop_cnt10; /* 788 */ + volatile csr_osch_tlp_hva_p_drop_cnt11_u osch_tlp_hva_p_drop_cnt11; /* 78C */ + volatile csr_osch_tlp_hva_p_drop_cnt12_u osch_tlp_hva_p_drop_cnt12; /* 790 */ + volatile csr_osch_tlp_hva_p_drop_cnt13_u osch_tlp_hva_p_drop_cnt13; /* 794 */ + volatile csr_osch_tlp_hva_p_drop_cnt14_u osch_tlp_hva_p_drop_cnt14; /* 798 */ + volatile csr_osch_tlp_hva_p_drop_cnt15_u osch_tlp_hva_p_drop_cnt15; /* 79C */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt0_u osch_tlp_hva_npcpl_drop_cnt0; /* 7A0 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt1_u osch_tlp_hva_npcpl_drop_cnt1; /* 7A4 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt2_u osch_tlp_hva_npcpl_drop_cnt2; /* 7A8 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt3_u osch_tlp_hva_npcpl_drop_cnt3; /* 7AC */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt4_u osch_tlp_hva_npcpl_drop_cnt4; /* 7B0 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt5_u osch_tlp_hva_npcpl_drop_cnt5; /* 7B4 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt6_u osch_tlp_hva_npcpl_drop_cnt6; /* 7B8 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt7_u osch_tlp_hva_npcpl_drop_cnt7; /* 7BC */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt8_u osch_tlp_hva_npcpl_drop_cnt8; /* 7C0 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt9_u osch_tlp_hva_npcpl_drop_cnt9; /* 7C4 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt10_u osch_tlp_hva_npcpl_drop_cnt10; /* 7C8 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt11_u osch_tlp_hva_npcpl_drop_cnt11; /* 7CC */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt12_u osch_tlp_hva_npcpl_drop_cnt12; /* 7D0 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt13_u osch_tlp_hva_npcpl_drop_cnt13; /* 7D4 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt14_u osch_tlp_hva_npcpl_drop_cnt14; /* 7D8 */ + volatile csr_osch_tlp_hva_npcpl_drop_cnt15_u osch_tlp_hva_npcpl_drop_cnt15; /* 7DC */ + volatile csr_osch_tlp_drop_count_mode_u osch_tlp_drop_count_mode; /* 7E0 */ + volatile csr_osch_npcpl_perf_watch_byte_u osch_npcpl_perf_watch_byte; /* 7E8 */ + volatile csr_osch_npcpl_perf_watch_tlp_u osch_npcpl_perf_watch_tlp; /* 7EC */ + volatile csr_osch_hva_p_perf_watch_byte_u osch_hva_p_perf_watch_byte; /* 7F0 */ + volatile csr_osch_hva_p_perf_watch_tlp_u osch_hva_p_perf_watch_tlp; /* 7F4 */ + volatile csr_osch_hva_npcpl_perf_watch_byte_u osch_hva_npcpl_perf_watch_byte; /* 7F8 */ + volatile csr_osch_hva_npcpl_perf_watch_tlp_u osch_hva_npcpl_perf_watch_tlp; /* 7FC */ +} S_cpi_osch_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cpi_osch_csr */ +extern volatile S_cpi_osch_csr_REGS_TYPE *gopcpi_osch_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetOSCH_TLP_DROP_CNT_PORT0_osch_tlp_drop_count_port0(unsigned int uosch_tlp_drop_count_port0); +int iSetOSCH_TLP_DROP_CNT_PORT1_osch_tlp_drop_count_port1(unsigned int uosch_tlp_drop_count_port1); +int iSetOSCH_TLP_DROP_CNT_PORT2_osch_tlp_drop_count_port2(unsigned int uosch_tlp_drop_count_port2); +int iSetOSCH_TLP_DROP_CNT_PORT3_osch_tlp_drop_count_port3(unsigned int uosch_tlp_drop_count_port3); +int iSetOSCH_TLP_DROP_CNT_PORT4_osch_tlp_drop_count_port4(unsigned int uosch_tlp_drop_count_port4); +int iSetOSCH_TLP_ERROR_CNT0_osch_tlp_err_count_port3(unsigned int uosch_tlp_err_count_port3); +int iSetOSCH_TLP_ERROR_CNT0_osch_tlp_err_count_port2(unsigned int uosch_tlp_err_count_port2); +int iSetOSCH_TLP_ERROR_CNT0_osch_tlp_err_count_port1(unsigned int uosch_tlp_err_count_port1); +int iSetOSCH_TLP_ERROR_CNT0_osch_tlp_err_count_port0(unsigned int uosch_tlp_err_count_port0); +int iSetOSCH_TLP_ERROR_CNT1_osch_tlp_err_count_port4(unsigned int uosch_tlp_err_count_port4); +int iSetOSCH_TLP_DROP_CNT0_osch_tlp_drop_count0(unsigned int uosch_tlp_drop_count0); +int iSetOSCH_TLP_DROP_CNT1_osch_tlp_drop_count1(unsigned int uosch_tlp_drop_count1); +int iSetOSCH_TLP_DROP_CNT2_osch_tlp_drop_count2(unsigned int uosch_tlp_drop_count2); +int iSetOSCH_TLP_DROP_CNT3_osch_tlp_drop_count3(unsigned int uosch_tlp_drop_count3); +int iSetOSCH_TLP_DROP_CNT4_osch_tlp_drop_count4(unsigned int uosch_tlp_drop_count4); +int iSetOSCH_TLP_DROP_CNT5_osch_tlp_drop_count5(unsigned int uosch_tlp_drop_count5); +int iSetOSCH_TLP_DROP_CNT6_osch_tlp_drop_count6(unsigned int uosch_tlp_drop_count6); +int iSetOSCH_TLP_DROP_CNT7_osch_tlp_drop_count7(unsigned int uosch_tlp_drop_count7); +int iSetOSCH_TLP_DROP_CNT8_osch_tlp_drop_count8(unsigned int uosch_tlp_drop_count8); +int iSetOSCH_TLP_DROP_CNT9_osch_tlp_drop_count9(unsigned int uosch_tlp_drop_count9); +int iSetOSCH_TLP_DROP_CNT10_osch_tlp_drop_count10(unsigned int uosch_tlp_drop_count10); +int iSetOSCH_TLP_DROP_CNT11_osch_tlp_drop_count11(unsigned int uosch_tlp_drop_count11); +int iSetOSCH_TLP_DROP_CNT12_osch_tlp_drop_count12(unsigned int uosch_tlp_drop_count12); +int iSetOSCH_TLP_DROP_CNT13_osch_tlp_drop_count13(unsigned int uosch_tlp_drop_count13); +int iSetOSCH_TLP_DROP_CNT14_osch_tlp_drop_count14(unsigned int uosch_tlp_drop_count14); +int iSetOSCH_TLP_DROP_CNT15_osch_tlp_drop_count15(unsigned int uosch_tlp_drop_count15); +int iSetOSCH_TLP_DROP_FUNC01_osch_tlp_drop_func1(unsigned int uosch_tlp_drop_func1); +int iSetOSCH_TLP_DROP_FUNC01_osch_tlp_drop_func0(unsigned int uosch_tlp_drop_func0); +int iSetOSCH_TLP_DROP_FUNC23_osch_tlp_drop_func3(unsigned int uosch_tlp_drop_func3); +int iSetOSCH_TLP_DROP_FUNC23_osch_tlp_drop_func2(unsigned int uosch_tlp_drop_func2); +int iSetOSCH_TLP_DROP_FUNC45_osch_tlp_drop_func5(unsigned int uosch_tlp_drop_func5); +int iSetOSCH_TLP_DROP_FUNC45_osch_tlp_drop_func4(unsigned int uosch_tlp_drop_func4); +int iSetOSCH_TLP_DROP_FUNC67_osch_tlp_drop_func7(unsigned int uosch_tlp_drop_func7); +int iSetOSCH_TLP_DROP_FUNC67_osch_tlp_drop_func6(unsigned int uosch_tlp_drop_func6); +int iSetOSCH_TLP_DROP_FUNC89_osch_tlp_drop_func9(unsigned int uosch_tlp_drop_func9); +int iSetOSCH_TLP_DROP_FUNC89_osch_tlp_drop_func8(unsigned int uosch_tlp_drop_func8); +int iSetOSCH_TLP_DROP_FUNC1011_osch_tlp_drop_func11(unsigned int uosch_tlp_drop_func11); +int iSetOSCH_TLP_DROP_FUNC1011_osch_tlp_drop_func10(unsigned int uosch_tlp_drop_func10); +int iSetOSCH_TLP_DROP_FUNC1213_osch_tlp_drop_func13(unsigned int uosch_tlp_drop_func13); +int iSetOSCH_TLP_DROP_FUNC1213_osch_tlp_drop_func12(unsigned int uosch_tlp_drop_func12); +int iSetOSCH_TLP_DROP_FUNC1415_osch_tlp_drop_func15(unsigned int uosch_tlp_drop_func15); +int iSetOSCH_TLP_DROP_FUNC1415_osch_tlp_drop_func14(unsigned int uosch_tlp_drop_func14); +int iSetOSCH_CEQE_DROP_CNT_osch_ceqe_drop_cnt(unsigned int uosch_ceqe_drop_cnt); +int iSetOSCH_CEQE_PI_OVERFLOW_osch_ceqe_pi_overfl_qid(unsigned int uosch_ceqe_pi_overfl_qid); +int iSetOSCH_CEQE_PI_OVERFLOW_osch_ceqe_pi_overfl(unsigned int uosch_ceqe_pi_overfl); +int iSetOSCH_FIFO_OVERFLOW_LOW_osch_fifo_overflow_id(unsigned int uosch_fifo_overflow_id); +int iSetOSCH_FIFO_OVERFLOW_LOW_osch_fifo_overflow(unsigned int uosch_fifo_overflow); +int iSetOSCH_REQ_TIMEOUT_cur_port_busy_src(unsigned int ucur_port_busy_src); +int iSetOSCH_FIFO_EMPT_HIGH_osch_fifo_empty_high(unsigned int uosch_fifo_empty_high); +int iSetOSCH_FIFO_EMPT_HIGH_osch_empty(unsigned int uosch_empty); +int iSetOSCH_FIFO_EMPT_LOW_osch_fifo_empty_low(unsigned int uosch_fifo_empty_low); +int iSetOSCH_FIFO_AFULL_HIGH_osch_fifo_afull_high(unsigned int uosch_fifo_afull_high); +int iSetOSCH_FIFO_AFULL_LOW_osch_fifo_afull_low(unsigned int uosch_fifo_afull_low); +int iSetOSCH_PAYLOAD_FIFO_CTRL_osch_payload_fifo_ctrl_all_port(unsigned int uosch_payload_fifo_ctrl_all_port); +int iSetOSCH_MSI_TX_FIFO_CTRL0_osch_msi_tx_fifo_ctrl_port3(unsigned int uosch_msi_tx_fifo_ctrl_port3); +int iSetOSCH_MSI_TX_FIFO_CTRL0_osch_msi_tx_fifo_ctrl_port2(unsigned int uosch_msi_tx_fifo_ctrl_port2); +int iSetOSCH_MSI_TX_FIFO_CTRL0_osch_msi_tx_fifo_ctrl_port1(unsigned int uosch_msi_tx_fifo_ctrl_port1); +int iSetOSCH_MSI_TX_FIFO_CTRL0_osch_msi_tx_fifo_ctrl_port0(unsigned int uosch_msi_tx_fifo_ctrl_port0); +int iSetOSCH_MSI_TX_FIFO_CTRL1_osch_msi_tx_fifo_ctrl_port4(unsigned int uosch_msi_tx_fifo_ctrl_port4); +int iSetOSCH_ATOMIC_TX_FIFO_CTRL0_osch_atomic_tx_fifo_ctrl_port3(unsigned int uosch_atomic_tx_fifo_ctrl_port3); +int iSetOSCH_ATOMIC_TX_FIFO_CTRL0_osch_atomic_tx_fifo_ctrl_port2(unsigned int uosch_atomic_tx_fifo_ctrl_port2); +int iSetOSCH_ATOMIC_TX_FIFO_CTRL0_osch_atomic_tx_fifo_ctrl_port1(unsigned int uosch_atomic_tx_fifo_ctrl_port1); +int iSetOSCH_ATOMIC_TX_FIFO_CTRL0_osch_atomic_tx_fifo_ctrl_port0(unsigned int uosch_atomic_tx_fifo_ctrl_port0); +int iSetOSCH_ATOMIC_TX_FIFO_CTRL1_osch_atomic_tx_fifo_ctrl_port4(unsigned int uosch_atomic_tx_fifo_ctrl_port4); +int iSetOSCH_CEQE_TX_FIFO_CTRL0_osch_ceqe_tx_fifo_ctrl_port3(unsigned int uosch_ceqe_tx_fifo_ctrl_port3); +int iSetOSCH_CEQE_TX_FIFO_CTRL0_osch_ceqe_tx_fifo_ctrl_port2(unsigned int uosch_ceqe_tx_fifo_ctrl_port2); +int iSetOSCH_CEQE_TX_FIFO_CTRL0_osch_ceqe_tx_fifo_ctrl_port1(unsigned int uosch_ceqe_tx_fifo_ctrl_port1); +int iSetOSCH_CEQE_TX_FIFO_CTRL0_osch_ceqe_tx_fifo_ctrl_port0(unsigned int uosch_ceqe_tx_fifo_ctrl_port0); +int iSetOSCH_CEQE_TX_FIFO_CTRL1_osch_ceqe_tx_fifo_ctrl_port4(unsigned int uosch_ceqe_tx_fifo_ctrl_port4); +int iSetOSCH_CPLD_TX_FIFO_CTRL0_osch_cpld_tx_fifo_ctrl_port3(unsigned int uosch_cpld_tx_fifo_ctrl_port3); +int iSetOSCH_CPLD_TX_FIFO_CTRL0_osch_cpld_tx_fifo_ctrl_port2(unsigned int uosch_cpld_tx_fifo_ctrl_port2); +int iSetOSCH_CPLD_TX_FIFO_CTRL0_osch_cpld_tx_fifo_ctrl_port1(unsigned int uosch_cpld_tx_fifo_ctrl_port1); +int iSetOSCH_CPLD_TX_FIFO_CTRL0_osch_cpld_tx_fifo_ctrl_port0(unsigned int uosch_cpld_tx_fifo_ctrl_port0); +int iSetOSCH_CPLD_TX_FIFO_CTRL1_osch_cpld_tx_fifo_ctrl_port4(unsigned int uosch_cpld_tx_fifo_ctrl_port4); +int iSetOSCH_FIFO_EMPT_TOPHIGH_osch_fifo_empty_tophigh(unsigned int uosch_fifo_empty_tophigh); +int iSetOSCH_FIFO_EMPT_TOPHIGH_osch_port_pipe_empty(unsigned int uosch_port_pipe_empty); +int iSetOSCH_FIFO_EMPT_TOPHIGH_osch_port_sch_pipe_empty(unsigned int uosch_port_sch_pipe_empty); +int iSetOSCH_FIFO_AFULL_TOPHIGH_osch_fifo_afull_tophigh(unsigned int uosch_fifo_afull_tophigh); +int iSetOSCH_CPATH_Q0_FIFO_CTRL0_osch_cpath_q0_fifo_ctrl_port3(unsigned int uosch_cpath_q0_fifo_ctrl_port3); +int iSetOSCH_CPATH_Q0_FIFO_CTRL0_osch_cpath_q0_fifo_ctrl_port2(unsigned int uosch_cpath_q0_fifo_ctrl_port2); +int iSetOSCH_CPATH_Q0_FIFO_CTRL0_osch_cpath_q0_fifo_ctrl_port1(unsigned int uosch_cpath_q0_fifo_ctrl_port1); +int iSetOSCH_CPATH_Q0_FIFO_CTRL0_osch_cpath_q0_fifo_ctrl_port0(unsigned int uosch_cpath_q0_fifo_ctrl_port0); +int iSetOSCH_CPATH_Q0_FIFO_CTRL1_osch_cpath_q0_fifo_ctrl_port4(unsigned int uosch_cpath_q0_fifo_ctrl_port4); +int iSetOSCH_CPATH_Q1_FIFO_CTRL0_osch_cpath_q1_fifo_ctrl_port2(unsigned int uosch_cpath_q1_fifo_ctrl_port2); +int iSetOSCH_CPATH_Q1_FIFO_CTRL0_osch_cpath_q1_fifo_ctrl_port1(unsigned int uosch_cpath_q1_fifo_ctrl_port1); +int iSetOSCH_CPATH_Q1_FIFO_CTRL0_osch_cpath_q1_fifo_ctrl_port0(unsigned int uosch_cpath_q1_fifo_ctrl_port0); +int iSetOSCH_CPATH_Q1_FIFO_CTRL1_osch_cpath_q1_fifo_ctrl_port4(unsigned int uosch_cpath_q1_fifo_ctrl_port4); +int iSetOSCH_CPATH_Q1_FIFO_CTRL1_osch_cpath_q1_fifo_ctrl_port3(unsigned int uosch_cpath_q1_fifo_ctrl_port3); +int iSetOSCH_CPATH_Q2_FIFO_CTRL0_osch_cpath_q2_fifo_ctrl_port3(unsigned int uosch_cpath_q2_fifo_ctrl_port3); +int iSetOSCH_CPATH_Q2_FIFO_CTRL0_osch_cpath_q2_fifo_ctrl_port2(unsigned int uosch_cpath_q2_fifo_ctrl_port2); +int iSetOSCH_CPATH_Q2_FIFO_CTRL0_osch_cpath_q2_fifo_ctrl_port1(unsigned int uosch_cpath_q2_fifo_ctrl_port1); +int iSetOSCH_CPATH_Q2_FIFO_CTRL0_osch_cpath_q2_fifo_ctrl_port0(unsigned int uosch_cpath_q2_fifo_ctrl_port0); +int iSetOSCH_CPATH_Q2_FIFO_CTRL1_osch_cpath_q2_fifo_ctrl_port4(unsigned int uosch_cpath_q2_fifo_ctrl_port4); +int iSetOSCH_DPATH_Q0_FIFO_CTRL0_osch_dpath_q0_fifo_ctrl_port3(unsigned int uosch_dpath_q0_fifo_ctrl_port3); +int iSetOSCH_DPATH_Q0_FIFO_CTRL0_osch_dpath_q0_fifo_ctrl_port2(unsigned int uosch_dpath_q0_fifo_ctrl_port2); +int iSetOSCH_DPATH_Q0_FIFO_CTRL0_osch_dpath_q0_fifo_ctrl_port1(unsigned int uosch_dpath_q0_fifo_ctrl_port1); +int iSetOSCH_DPATH_Q0_FIFO_CTRL0_osch_dpath_q0_fifo_ctrl_port0(unsigned int uosch_dpath_q0_fifo_ctrl_port0); +int iSetOSCH_DPATH_Q0_FIFO_CTRL1_osch_dpath_q0_fifo_ctrl_port4(unsigned int uosch_dpath_q0_fifo_ctrl_port4); +int iSetOSCH_DPATH_Q1_FIFO_CTRL0_osch_dpath_q1_fifo_ctrl_port3(unsigned int uosch_dpath_q1_fifo_ctrl_port3); +int iSetOSCH_DPATH_Q1_FIFO_CTRL0_osch_dpath_q1_fifo_ctrl_port2(unsigned int uosch_dpath_q1_fifo_ctrl_port2); +int iSetOSCH_DPATH_Q1_FIFO_CTRL0_osch_dpath_q1_fifo_ctrl_port1(unsigned int uosch_dpath_q1_fifo_ctrl_port1); +int iSetOSCH_DPATH_Q1_FIFO_CTRL0_osch_dpath_q1_fifo_ctrl_port0(unsigned int uosch_dpath_q1_fifo_ctrl_port0); +int iSetOSCH_DPATH_Q1_FIFO_CTRL1_osch_dpath_q1_fifo_ctrl_port4(unsigned int uosch_dpath_q1_fifo_ctrl_port4); +int iSetOSCH_DPATH_Q2_FIFO_CTRL0_osch_dpath_q2_fifo_ctrl_port3(unsigned int uosch_dpath_q2_fifo_ctrl_port3); +int iSetOSCH_DPATH_Q2_FIFO_CTRL0_osch_dpath_q2_fifo_ctrl_port2(unsigned int uosch_dpath_q2_fifo_ctrl_port2); +int iSetOSCH_DPATH_Q2_FIFO_CTRL0_osch_dpath_q2_fifo_ctrl_port1(unsigned int uosch_dpath_q2_fifo_ctrl_port1); +int iSetOSCH_DPATH_Q2_FIFO_CTRL0_osch_dpath_q2_fifo_ctrl_port0(unsigned int uosch_dpath_q2_fifo_ctrl_port0); +int iSetOSCH_DPATH_Q2_FIFO_CTRL1_osch_dpath_q2_fifo_ctrl_port4(unsigned int uosch_dpath_q2_fifo_ctrl_port4); +int iSetOSCH_DPATH_Q3_FIFO_CTRL0_osch_dpath_q3_fifo_ctrl_port3(unsigned int uosch_dpath_q3_fifo_ctrl_port3); +int iSetOSCH_DPATH_Q3_FIFO_CTRL0_osch_dpath_q3_fifo_ctrl_port2(unsigned int uosch_dpath_q3_fifo_ctrl_port2); +int iSetOSCH_DPATH_Q3_FIFO_CTRL0_osch_dpath_q3_fifo_ctrl_port1(unsigned int uosch_dpath_q3_fifo_ctrl_port1); +int iSetOSCH_DPATH_Q3_FIFO_CTRL0_osch_dpath_q3_fifo_ctrl_port0(unsigned int uosch_dpath_q3_fifo_ctrl_port0); +int iSetOSCH_DPATH_Q3_FIFO_CTRL1_osch_dpath_q3_fifo_ctrl_port4(unsigned int uosch_dpath_q3_fifo_ctrl_port4); +int iSetOSCH_DPATH_Q4_FIFO_CTRL0_osch_dpath_q4_fifo_ctrl_port3(unsigned int uosch_dpath_q4_fifo_ctrl_port3); +int iSetOSCH_DPATH_Q4_FIFO_CTRL0_osch_dpath_q4_fifo_ctrl_port2(unsigned int uosch_dpath_q4_fifo_ctrl_port2); +int iSetOSCH_DPATH_Q4_FIFO_CTRL0_osch_dpath_q4_fifo_ctrl_port1(unsigned int uosch_dpath_q4_fifo_ctrl_port1); +int iSetOSCH_DPATH_Q4_FIFO_CTRL0_osch_dpath_q4_fifo_ctrl_port0(unsigned int uosch_dpath_q4_fifo_ctrl_port0); +int iSetOSCH_DPATH_Q4_FIFO_CTRL1_osch_dpath_q4_fifo_ctrl_port4(unsigned int uosch_dpath_q4_fifo_ctrl_port4); +int iSetOSCH_RESERVED0_osch_resved0(unsigned int uosch_resved0); +int iSetOSCH_RESERVED1_osch_resved1(unsigned int uosch_resved1); +int iSetOSCH_RESERVED2_osch_resved2(unsigned int uosch_resved2); +int iSetGLB_POST_HEAD_CREDIT_glb_post_head_credit(unsigned int uglb_post_head_credit); +int iSetGLB_POST_PAYLOAD_CREDIT_H_glb_post_payload_credit_h(unsigned int uglb_post_payload_credit_h); +int iSetGLB_POST_PAYLOAD_CREDIT_L_glb_post_payload_credit_l(unsigned int uglb_post_payload_credit_l); +int iSetGLB_NON_POST_HEAD_CREDIT_glb_non_post_head_credit(unsigned int uglb_non_post_head_credit); +int iSetGLB_NON_POST_PAYLOAD_CREDIT_H_glb_non_post_payload_credit_h(unsigned int uglb_non_post_payload_credit_h); +int iSetGLB_NON_POST_PAYLOAD_CREDIT_L_glb_non_post_payload_credit_l(unsigned int uglb_non_post_payload_credit_l); +int iSetGLB_CPL_HEAD_CREDIT_glb_cpl_head_credit(unsigned int uglb_cpl_head_credit); +int iSetGLB_CPL_PAYLOAD_CREDIT_H_glb_cpl_payload_credit_h(unsigned int uglb_cpl_payload_credit_h); +int iSetGLB_CPL_PAYLOAD_CREDIT_L_glb_cpl_payload_credit_l(unsigned int uglb_cpl_payload_credit_l); +int iSetGLB_OSCH_CEQE_IN_CNT_glb_osch_ceqe_in_cnt(unsigned int uglb_osch_ceqe_in_cnt); +int iSetGLB_OSCH_CEQE_OUT_CNT_glb_osch_ceqe_out_cnt(unsigned int uglb_osch_ceqe_out_cnt); +int iSetGLB_CEQE_DROP_TAIL_glb_ceqe_drop_tail(unsigned int uglb_ceqe_drop_tail); +int iSetGLB_CEQE_DROP_TAIL_ceqe_cls_glb_offs_drop_en(unsigned int uceqe_cls_glb_offs_drop_en); +int iSetOSCH_TLP_POST_CNT_PORT0_osch_tlp_post_count_port0(unsigned int uosch_tlp_post_count_port0); +int iSetOSCH_TLP_POST_CNT_PORT1_osch_tlp_post_count_port1(unsigned int uosch_tlp_post_count_port1); +int iSetOSCH_TLP_POST_CNT_PORT2_osch_tlp_post_count_port2(unsigned int uosch_tlp_post_count_port2); +int iSetOSCH_TLP_POST_CNT_PORT3_osch_tlp_post_count_port3(unsigned int uosch_tlp_post_count_port3); +int iSetOSCH_TLP_POST_CNT_PORT4_osch_tlp_post_count_port4(unsigned int uosch_tlp_post_count_port4); +int iSetOSCH_TLP_NON_POST_CNT_PORT0_osch_tlp_non_post_count_port0(unsigned int uosch_tlp_non_post_count_port0); +int iSetOSCH_TLP_NON_POST_CNT_PORT1_osch_tlp_non_post_count_port1(unsigned int uosch_tlp_non_post_count_port1); +int iSetOSCH_TLP_NON_POST_CNT_PORT2_osch_tlp_non_post_count_port2(unsigned int uosch_tlp_non_post_count_port2); +int iSetOSCH_TLP_NON_POST_CNT_PORT3_osch_tlp_non_post_count_port3(unsigned int uosch_tlp_non_post_count_port3); +int iSetOSCH_TLP_NON_POST_CNT_PORT4_osch_tlp_non_post_count_port4(unsigned int uosch_tlp_non_post_count_port4); +int iSetOSCH_TLP_CPL_CNT_PORT0_osch_tlp_cpl_count_port0(unsigned int uosch_tlp_cpl_count_port0); +int iSetOSCH_TLP_CPL_CNT_PORT1_osch_tlp_cpl_count_port1(unsigned int uosch_tlp_cpl_count_port1); +int iSetOSCH_TLP_CPL_CNT_PORT2_osch_tlp_cpl_count_port2(unsigned int uosch_tlp_cpl_count_port2); +int iSetOSCH_TLP_CPL_CNT_PORT3_osch_tlp_cpl_count_port3(unsigned int uosch_tlp_cpl_count_port3); +int iSetOSCH_TLP_CPL_CNT_PORT4_osch_tlp_cpl_count_port4(unsigned int uosch_tlp_cpl_count_port4); +int iSetOSCH_INT_CEQ_CREDIT_PORT01_osch_int_ceq_credit_port1(unsigned int uosch_int_ceq_credit_port1); +int iSetOSCH_INT_CEQ_CREDIT_PORT01_osch_int_ceq_credit_port0(unsigned int uosch_int_ceq_credit_port0); +int iSetOSCH_INT_CEQ_CREDIT_PORT23_osch_int_ceq_credit_port3(unsigned int uosch_int_ceq_credit_port3); +int iSetOSCH_INT_CEQ_CREDIT_PORT23_osch_int_ceq_credit_port2(unsigned int uosch_int_ceq_credit_port2); +int iSetOSCH_INT_CEQ_CREDIT_PORT4_osch_int_ceq_credit_port4(unsigned int uosch_int_ceq_credit_port4); +int iSetOSCH_ESCH_DPATH_BP_STS_osch_esch_dpath_bp_q4(unsigned int uosch_esch_dpath_bp_q4); +int iSetOSCH_ESCH_DPATH_BP_STS_osch_esch_dpath_bp_q3(unsigned int uosch_esch_dpath_bp_q3); +int iSetOSCH_ESCH_DPATH_BP_STS_osch_esch_dpath_bp_q2(unsigned int uosch_esch_dpath_bp_q2); +int iSetOSCH_ESCH_DPATH_BP_STS_osch_esch_dpath_bp_q1(unsigned int uosch_esch_dpath_bp_q1); +int iSetOSCH_ESCH_DPATH_BP_STS_osch_esch_dpath_bp_q0(unsigned int uosch_esch_dpath_bp_q0); +int iSetOSCH_ESCH_DPATH_Q0_BP_THD0_osch_esch_dpath_q0_bp_thd_port3(unsigned int uosch_esch_dpath_q0_bp_thd_port3); +int iSetOSCH_ESCH_DPATH_Q0_BP_THD0_osch_esch_dpath_q0_bp_thd_port2(unsigned int uosch_esch_dpath_q0_bp_thd_port2); +int iSetOSCH_ESCH_DPATH_Q0_BP_THD0_osch_esch_dpath_q0_bp_thd_port1(unsigned int uosch_esch_dpath_q0_bp_thd_port1); +int iSetOSCH_ESCH_DPATH_Q0_BP_THD0_osch_esch_dpath_q0_bp_thd_port0(unsigned int uosch_esch_dpath_q0_bp_thd_port0); +int iSetOSCH_ESCH_DPATH_Q0_BP_THD1_osch_esch_dpath_q0_bp_thd_port4(unsigned int uosch_esch_dpath_q0_bp_thd_port4); +int iSetOSCH_ESCH_DPATH_Q1_BP_THD0_osch_esch_dpath_q1_bp_thd_port3(unsigned int uosch_esch_dpath_q1_bp_thd_port3); +int iSetOSCH_ESCH_DPATH_Q1_BP_THD0_osch_esch_dpath_q1_bp_thd_port2(unsigned int uosch_esch_dpath_q1_bp_thd_port2); +int iSetOSCH_ESCH_DPATH_Q1_BP_THD0_osch_esch_dpath_q1_bp_thd_port1(unsigned int uosch_esch_dpath_q1_bp_thd_port1); +int iSetOSCH_ESCH_DPATH_Q1_BP_THD0_osch_esch_dpath_q1_bp_thd_port0(unsigned int uosch_esch_dpath_q1_bp_thd_port0); +int iSetOSCH_ESCH_DPATH_Q1_BP_THD1_osch_esch_dpath_q1_bp_thd_port4(unsigned int uosch_esch_dpath_q1_bp_thd_port4); +int iSetOSCH_ESCH_DPATH_Q2_BP_THD0_osch_esch_dpath_q2_bp_thd_port3(unsigned int uosch_esch_dpath_q2_bp_thd_port3); +int iSetOSCH_ESCH_DPATH_Q2_BP_THD0_osch_esch_dpath_q2_bp_thd_port2(unsigned int uosch_esch_dpath_q2_bp_thd_port2); +int iSetOSCH_ESCH_DPATH_Q2_BP_THD0_osch_esch_dpath_q2_bp_thd_port1(unsigned int uosch_esch_dpath_q2_bp_thd_port1); +int iSetOSCH_ESCH_DPATH_Q2_BP_THD0_osch_esch_dpath_q2_bp_thd_port0(unsigned int uosch_esch_dpath_q2_bp_thd_port0); +int iSetOSCH_ESCH_DPATH_Q2_BP_THD1_osch_esch_dpath_q2_bp_thd_port4(unsigned int uosch_esch_dpath_q2_bp_thd_port4); +int iSetOSCH_ESCH_DPATH_Q3_BP_THD0_osch_esch_dpath_q3_bp_thd_port3(unsigned int uosch_esch_dpath_q3_bp_thd_port3); +int iSetOSCH_ESCH_DPATH_Q3_BP_THD0_osch_esch_dpath_q3_bp_thd_port2(unsigned int uosch_esch_dpath_q3_bp_thd_port2); +int iSetOSCH_ESCH_DPATH_Q3_BP_THD0_osch_esch_dpath_q3_bp_thd_port1(unsigned int uosch_esch_dpath_q3_bp_thd_port1); +int iSetOSCH_ESCH_DPATH_Q3_BP_THD0_osch_esch_dpath_q3_bp_thd_port0(unsigned int uosch_esch_dpath_q3_bp_thd_port0); +int iSetOSCH_ESCH_DPATH_Q3_BP_THD1_osch_esch_dpath_q3_bp_thd_port4(unsigned int uosch_esch_dpath_q3_bp_thd_port4); +int iSetOSCH_ESCH_DPATH_Q4_BP_THD0_osch_esch_dpath_q4_bp_thd_port3(unsigned int uosch_esch_dpath_q4_bp_thd_port3); +int iSetOSCH_ESCH_DPATH_Q4_BP_THD0_osch_esch_dpath_q4_bp_thd_port2(unsigned int uosch_esch_dpath_q4_bp_thd_port2); +int iSetOSCH_ESCH_DPATH_Q4_BP_THD0_osch_esch_dpath_q4_bp_thd_port1(unsigned int uosch_esch_dpath_q4_bp_thd_port1); +int iSetOSCH_ESCH_DPATH_Q4_BP_THD0_osch_esch_dpath_q4_bp_thd_port0(unsigned int uosch_esch_dpath_q4_bp_thd_port0); +int iSetOSCH_ESCH_DPATH_Q4_BP_THD1_osch_esch_dpath_q4_bp_thd_port4(unsigned int uosch_esch_dpath_q4_bp_thd_port4); +int iSetOSCH_PERF_WATCH_EN_osch_perf_watch_en(unsigned int uosch_perf_watch_en); +int iSetOSCH_PERF_WATCH_EN_osch_perf_watch_port_idx(unsigned int uosch_perf_watch_port_idx); +int iSetOSCH_PERF_WATCH_PERIOD_osch_perf_watch_period(unsigned int uosch_perf_watch_period); +int iSetOSCH_PERF_WATCH_BYTE_osch_perf_watch_byte(unsigned int uosch_perf_watch_byte); +int iSetOSCH_PERF_WATCH_TLP_osch_perf_watch_tlp(unsigned int uosch_perf_watch_tlp); +int iSetPORT_OUT_SCH_DWRR_WEIGHT_port_sch_dwrr_weight(unsigned int uport_sch_dwrr_weight); +int iSetPORT_RD_SRC_WEIGHT1_port_rd_src_dwrr_weight2(unsigned int uport_rd_src_dwrr_weight2); +int iSetPORT_RD_SRC_WEIGHT0_port_rd_src_dwrr_weight0(unsigned int uport_rd_src_dwrr_weight0); +int iSetPORT_RD_SRC_WEIGHT0_port_rd_src_dwrr_weight1(unsigned int uport_rd_src_dwrr_weight1); +int iSetPORT_RD_DPATH_WRR_WEIGHT1_port_rd_dpath_wrr_weight4(unsigned int uport_rd_dpath_wrr_weight4); +int iSetPORT_RD_DPATH_WRR_WEIGHT0_port_rd_dpath_wrr_weight0(unsigned int uport_rd_dpath_wrr_weight0); +int iSetPORT_RD_DPATH_WRR_WEIGHT0_port_rd_dpath_wrr_weight1(unsigned int uport_rd_dpath_wrr_weight1); +int iSetPORT_RD_DPATH_WRR_WEIGHT0_port_rd_dpath_wrr_weight2(unsigned int uport_rd_dpath_wrr_weight2); +int iSetPORT_RD_DPATH_WRR_WEIGHT0_port_rd_dpath_wrr_weight3(unsigned int uport_rd_dpath_wrr_weight3); +int iSetPORT_RD_NON_DPATH_WRR_WEIGHT1_port_rd_ndpath_wrr_weight4(unsigned int uport_rd_ndpath_wrr_weight4); +int iSetPORT_RD_NON_DPATH_WRR_WEIGHT0_port_rd_ndpath_wrr_weight0(unsigned int uport_rd_ndpath_wrr_weight0); +int iSetPORT_RD_NON_DPATH_WRR_WEIGHT0_port_rd_ndpath_wrr_weight1(unsigned int uport_rd_ndpath_wrr_weight1); +int iSetPORT_RD_NON_DPATH_WRR_WEIGHT0_port_rd_ndpath_wrr_weight2(unsigned int uport_rd_ndpath_wrr_weight2); +int iSetPORT_RD_NON_DPATH_WRR_WEIGHT0_port_rd_ndpath_wrr_weight3(unsigned int uport_rd_ndpath_wrr_weight3); +int iSetPORT_WR_WRR_WEIGHT2_port_wr_wrr_weight8(unsigned int uport_wr_wrr_weight8); +int iSetPORT_WR_WRR_WEIGHT2_port_wr_wrr_weight9(unsigned int uport_wr_wrr_weight9); +int iSetPORT_WR_WRR_WEIGHT2_port_wr_wrr_weight10(unsigned int uport_wr_wrr_weight10); +int iSetPORT_WR_WRR_WEIGHT1_port_wr_wrr_weight4(unsigned int uport_wr_wrr_weight4); +int iSetPORT_WR_WRR_WEIGHT1_port_wr_wrr_weight5(unsigned int uport_wr_wrr_weight5); +int iSetPORT_WR_WRR_WEIGHT1_port_wr_wrr_weight6(unsigned int uport_wr_wrr_weight6); +int iSetPORT_WR_WRR_WEIGHT1_port_wr_wrr_weight7(unsigned int uport_wr_wrr_weight7); +int iSetPORT_WR_WRR_WEIGHT0_port_wr_wrr_weight0(unsigned int uport_wr_wrr_weight0); +int iSetPORT_WR_WRR_WEIGHT0_port_wr_wrr_weight1(unsigned int uport_wr_wrr_weight1); +int iSetPORT_WR_WRR_WEIGHT0_port_wr_wrr_weight2(unsigned int uport_wr_wrr_weight2); +int iSetPORT_WR_WRR_WEIGHT0_port_wr_wrr_weight3(unsigned int uport_wr_wrr_weight3); +int iSetCFG_DOORBELL_CRDT_BP_TH_cfg_doorbell_crdt_bp_th(unsigned int ucfg_doorbell_crdt_bp_th); +int iSetDOORBELL_WR_CMD_CRDT_ERR_doorbell_wr_cmd_crdt_err(unsigned int udoorbell_wr_cmd_crdt_err); +int iSetOSCH_CTRL_DOORBELL_CNT_osch_ctrl_doorbell_cnt(unsigned int uosch_ctrl_doorbell_cnt); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT0_pcie_wr_payload_crdt_cnt0(unsigned int upcie_wr_payload_crdt_cnt0); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT0_pcie_wr_head_crdt_cnt0(unsigned int upcie_wr_head_crdt_cnt0); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT0_pcie_wr_payload_busy0(unsigned int upcie_wr_payload_busy0); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT0_pcie_wr_head_busy0(unsigned int upcie_wr_head_busy0); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT0_pcie_rd_payload_crdt_cnt0(unsigned int upcie_rd_payload_crdt_cnt0); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT0_pcie_rd_head_crdt_cnt0(unsigned int upcie_rd_head_crdt_cnt0); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT0_pcie_rd_payload_busy0(unsigned int upcie_rd_payload_busy0); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT0_pcie_rd_head_busy0(unsigned int upcie_rd_head_busy0); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT0_pcie_cpl_payload_crdt_cnt0(unsigned int upcie_cpl_payload_crdt_cnt0); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT0_pcie_cpl_head_crdt_cnt0(unsigned int upcie_cpl_head_crdt_cnt0); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT0_pcie_cpl_payload_busy0(unsigned int upcie_cpl_payload_busy0); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT0_pcie_cpl_head_busy0(unsigned int upcie_cpl_head_busy0); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT1_pcie_wr_payload_crdt_cnt1(unsigned int upcie_wr_payload_crdt_cnt1); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT1_pcie_wr_head_crdt_cnt1(unsigned int upcie_wr_head_crdt_cnt1); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT1_pcie_wr_payload_busy1(unsigned int upcie_wr_payload_busy1); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT1_pcie_wr_head_busy1(unsigned int upcie_wr_head_busy1); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT1_pcie_rd_payload_crdt_cnt1(unsigned int upcie_rd_payload_crdt_cnt1); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT1_pcie_rd_head_crdt_cnt1(unsigned int upcie_rd_head_crdt_cnt1); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT1_pcie_rd_payload_busy1(unsigned int upcie_rd_payload_busy1); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT1_pcie_rd_head_busy1(unsigned int upcie_rd_head_busy1); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT1_pcie_cpl_payload_crdt_cnt1(unsigned int upcie_cpl_payload_crdt_cnt1); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT1_pcie_cpl_head_crdt_cnt1(unsigned int upcie_cpl_head_crdt_cnt1); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT1_pcie_cpl_payload_busy1(unsigned int upcie_cpl_payload_busy1); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT1_pcie_cpl_head_busy1(unsigned int upcie_cpl_head_busy1); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT2_pcie_wr_payload_crdt_cnt2(unsigned int upcie_wr_payload_crdt_cnt2); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT2_pcie_wr_head_crdt_cnt2(unsigned int upcie_wr_head_crdt_cnt2); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT2_pcie_wr_payload_busy2(unsigned int upcie_wr_payload_busy2); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT2_pcie_wr_head_busy2(unsigned int upcie_wr_head_busy2); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT2_pcie_rd_payload_crdt_cnt2(unsigned int upcie_rd_payload_crdt_cnt2); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT2_pcie_rd_head_crdt_cnt2(unsigned int upcie_rd_head_crdt_cnt2); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT2_pcie_rd_payload_busy2(unsigned int upcie_rd_payload_busy2); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT2_pcie_rd_head_busy2(unsigned int upcie_rd_head_busy2); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT2_pcie_cpl_payload_crdt_cnt2(unsigned int upcie_cpl_payload_crdt_cnt2); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT2_pcie_cpl_head_crdt_cnt2(unsigned int upcie_cpl_head_crdt_cnt2); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT2_pcie_cpl_payload_busy2(unsigned int upcie_cpl_payload_busy2); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT2_pcie_cpl_head_busy2(unsigned int upcie_cpl_head_busy2); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT3_pcie_wr_payload_crdt_cnt3(unsigned int upcie_wr_payload_crdt_cnt3); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT3_pcie_wr_head_crdt_cnt3(unsigned int upcie_wr_head_crdt_cnt3); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT3_pcie_wr_payload_busy3(unsigned int upcie_wr_payload_busy3); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT3_pcie_wr_head_busy3(unsigned int upcie_wr_head_busy3); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT3_pcie_rd_payload_crdt_cnt3(unsigned int upcie_rd_payload_crdt_cnt3); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT3_pcie_rd_head_crdt_cnt3(unsigned int upcie_rd_head_crdt_cnt3); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT3_pcie_rd_payload_busy3(unsigned int upcie_rd_payload_busy3); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT3_pcie_rd_head_busy3(unsigned int upcie_rd_head_busy3); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT3_pcie_cpl_payload_crdt_cnt3(unsigned int upcie_cpl_payload_crdt_cnt3); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT3_pcie_cpl_head_crdt_cnt3(unsigned int upcie_cpl_head_crdt_cnt3); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT3_pcie_cpl_payload_busy3(unsigned int upcie_cpl_payload_busy3); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT3_pcie_cpl_head_busy3(unsigned int upcie_cpl_head_busy3); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT4_pcie_wr_payload_crdt_cnt4(unsigned int upcie_wr_payload_crdt_cnt4); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT4_pcie_wr_head_crdt_cnt4(unsigned int upcie_wr_head_crdt_cnt4); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT4_pcie_wr_payload_busy4(unsigned int upcie_wr_payload_busy4); +int iSetPCIE_WR_PAYLOAD_CRDT_CNT4_pcie_wr_head_busy4(unsigned int upcie_wr_head_busy4); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT4_pcie_rd_payload_crdt_cnt4(unsigned int upcie_rd_payload_crdt_cnt4); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT4_pcie_rd_head_crdt_cnt4(unsigned int upcie_rd_head_crdt_cnt4); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT4_pcie_rd_payload_busy4(unsigned int upcie_rd_payload_busy4); +int iSetPCIE_RD_PAYLOAD_CRDT_CNT4_pcie_rd_head_busy4(unsigned int upcie_rd_head_busy4); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT4_pcie_cpl_payload_crdt_cnt4(unsigned int upcie_cpl_payload_crdt_cnt4); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT4_pcie_cpl_head_crdt_cnt4(unsigned int upcie_cpl_head_crdt_cnt4); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT4_pcie_cpl_payload_busy4(unsigned int upcie_cpl_payload_busy4); +int iSetPCIE_CPL_PAYLOAD_CRDT_CNT4_pcie_cpl_head_busy4(unsigned int upcie_cpl_head_busy4); +int iSetOSCH_ECC_INJ_0_cpi_osch_cpld_fifo_inj(unsigned int ucpi_osch_cpld_fifo_inj); +int iSetOSCH_ECC_INJ_0_cpi_osch_nl2nic_req_mem_inj(unsigned int ucpi_osch_nl2nic_req_mem_inj); +int iSetOSCH_ECC_INJ_0_cpi_osch_ceqe_tx_fifo_inj(unsigned int ucpi_osch_ceqe_tx_fifo_inj); +int iSetOSCH_ECC_INJ_1_cpi_osch_dpath_q0_fifo_inj(unsigned int ucpi_osch_dpath_q0_fifo_inj); +int iSetOSCH_ECC_INJ_1_cpi_osch_dpath_q1_fifo_inj(unsigned int ucpi_osch_dpath_q1_fifo_inj); +int iSetOSCH_ECC_INJ_1_cpi_osch_dpath_q2_fifo_inj(unsigned int ucpi_osch_dpath_q2_fifo_inj); +int iSetOSCH_ECC_INJ_2_cpi_osch_dpath_q3_fifo_inj(unsigned int ucpi_osch_dpath_q3_fifo_inj); +int iSetOSCH_ECC_INJ_2_cpi_osch_dpath_q4_fifo_inj(unsigned int ucpi_osch_dpath_q4_fifo_inj); +int iSetOSCH_ECC_INJ_2_cpi_osch_atomic_tx_fifo_inj(unsigned int ucpi_osch_atomic_tx_fifo_inj); +int iSetOSCH_ECC_INJ_3_cpi_osch_cpath_q0_fifo_inj(unsigned int ucpi_osch_cpath_q0_fifo_inj); +int iSetOSCH_ECC_INJ_3_cpi_osch_cpath_q1_fifo_inj(unsigned int ucpi_osch_cpath_q1_fifo_inj); +int iSetOSCH_ECC_INJ_3_cpi_osch_cpath_q2_fifo_inj(unsigned int ucpi_osch_cpath_q2_fifo_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_msi_tx_fifo_inj(unsigned int ucpi_osch_msi_tx_fifo_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_atomic64_fifo_inj(unsigned int ucpi_osch_atomic64_fifo_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_ceqe_buf_fifo_inj(unsigned int ucpi_osch_ceqe_buf_fifo_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_payload_fifo_inj(unsigned int ucpi_osch_payload_fifo_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_payload_fifo1_inj(unsigned int ucpi_osch_payload_fifo1_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_payload_fifo_hva_inj(unsigned int ucpi_osch_payload_fifo_hva_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_payload_fifo1_hva_inj(unsigned int ucpi_osch_payload_fifo1_hva_inj); +int iSetOSCH_ECC_INJ_4_cpi_osch_doorbell_fifo_inj(unsigned int ucpi_osch_doorbell_fifo_inj); +int iSetOSCH_ECC_INJ_5_cpi_osch_payload_fifo_np_inj(unsigned int ucpi_osch_payload_fifo_np_inj); +int iSetOSCH_ECC_INJ_5_cpi_osch_payload_fifo1_np_inj(unsigned int ucpi_osch_payload_fifo1_np_inj); +int iSetOSCH_ECC_INJ_5_cpi_osch_payload_fifo_hva_np_inj(unsigned int ucpi_osch_payload_fifo_hva_np_inj); +int iSetOSCH_ECC_INJ_5_cpi_osch_payload_fifo1_hva_np_inj(unsigned int ucpi_osch_payload_fifo1_hva_np_inj); +int iSetOSCH_ECC_INT_0_osch_cpld_fifo_ecc_err(unsigned int uosch_cpld_fifo_ecc_err); +int iSetOSCH_ECC_INT_0_osch_nl2nic_req_mem_ecc_err(unsigned int uosch_nl2nic_req_mem_ecc_err); +int iSetOSCH_ECC_INT_0_osch_ceqe_tx_fifo_ecc_err(unsigned int uosch_ceqe_tx_fifo_ecc_err); +int iSetOSCH_ECC_INT_1_osch_dpath_q0_fifo_ecc_err(unsigned int uosch_dpath_q0_fifo_ecc_err); +int iSetOSCH_ECC_INT_1_osch_dpath_q1_fifo_ecc_err(unsigned int uosch_dpath_q1_fifo_ecc_err); +int iSetOSCH_ECC_INT_1_osch_dpath_q2_fifo_ecc_err(unsigned int uosch_dpath_q2_fifo_ecc_err); +int iSetOSCH_ECC_INT_2_osch_dpath_q3_fifo_ecc_err(unsigned int uosch_dpath_q3_fifo_ecc_err); +int iSetOSCH_ECC_INT_2_osch_dpath_q4_fifo_ecc_err(unsigned int uosch_dpath_q4_fifo_ecc_err); +int iSetOSCH_ECC_INT_2_osch_atomic_tx_fifo_ecc_err(unsigned int uosch_atomic_tx_fifo_ecc_err); +int iSetOSCH_ECC_INT_3_osch_cpath_q0_fifo_ecc_err(unsigned int uosch_cpath_q0_fifo_ecc_err); +int iSetOSCH_ECC_INT_3_osch_cpath_q1_fifo_ecc_err(unsigned int uosch_cpath_q1_fifo_ecc_err); +int iSetOSCH_ECC_INT_3_osch_cpath_q2_fifo_ecc_err(unsigned int uosch_cpath_q2_fifo_ecc_err); +int iSetOSCH_ECC_INT_4_osch_msi_tx_fifo_ecc_err(unsigned int uosch_msi_tx_fifo_ecc_err); +int iSetOSCH_ECC_INT_4_osch_atomic64_fifo_ecc_err(unsigned int uosch_atomic64_fifo_ecc_err); +int iSetOSCH_ECC_INT_4_osch_ceqe_buf_fifo_ecc_err(unsigned int uosch_ceqe_buf_fifo_ecc_err); +int iSetOSCH_ECC_INT_4_osch_payload_fifo_ecc_err(unsigned int uosch_payload_fifo_ecc_err); +int iSetOSCH_ECC_INT_4_osch_payload_fifo1_ecc_err(unsigned int uosch_payload_fifo1_ecc_err); +int iSetOSCH_ECC_INT_4_osch_payload_fifo_hva_ecc_err(unsigned int uosch_payload_fifo_hva_ecc_err); +int iSetOSCH_ECC_INT_4_osch_payload_fifo1_hva_ecc_err(unsigned int uosch_payload_fifo1_hva_ecc_err); +int iSetOSCH_ECC_INT_4_osch_doorbell_fifo_ecc_err(unsigned int uosch_doorbell_fifo_ecc_err); +int iSetOSCH_ECC_INT_5_osch_payload_fifo_np_ecc_err(unsigned int uosch_payload_fifo_np_ecc_err); +int iSetOSCH_ECC_INT_5_osch_payload_fifo1_np_ecc_err(unsigned int uosch_payload_fifo1_np_ecc_err); +int iSetOSCH_ECC_INT_5_osch_payload_fifo_hva_np_ecc_err(unsigned int uosch_payload_fifo_hva_np_ecc_err); +int iSetOSCH_ECC_INT_5_osch_payload_fifo1_hva_np_ecc_err(unsigned int uosch_payload_fifo1_hva_np_ecc_err); +int iSetOSCH_ECC_INT_EN_0_osch_cpld_fifo_ecc_int_en(unsigned int uosch_cpld_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_0_osch_nl2nic_req_mem_ecc_int_en(unsigned int uosch_nl2nic_req_mem_ecc_int_en); +int iSetOSCH_ECC_INT_EN_0_osch_ceqe_tx_fifo_ecc_int_en(unsigned int uosch_ceqe_tx_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_1_osch_dpath_q0_fifo_ecc_int_en(unsigned int uosch_dpath_q0_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_1_osch_dpath_q1_fifo_ecc_int_en(unsigned int uosch_dpath_q1_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_1_osch_dpath_q2_fifo_ecc_int_en(unsigned int uosch_dpath_q2_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_2_osch_dpath_q3_fifo_ecc_int_en(unsigned int uosch_dpath_q3_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_2_osch_dpath_q4_fifo_ecc_int_en(unsigned int uosch_dpath_q4_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_2_osch_atomic_tx_fifo_ecc_int_en(unsigned int uosch_atomic_tx_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_3_osch_cpath_q0_fifo_ecc_int_en(unsigned int uosch_cpath_q0_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_3_osch_cpath_q1_fifo_ecc_int_en(unsigned int uosch_cpath_q1_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_3_osch_cpath_q2_fifo_ecc_int_en(unsigned int uosch_cpath_q2_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_msi_tx_fifo_ecc_int_en(unsigned int uosch_msi_tx_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_atomic64_fifo_ecc_int_en(unsigned int uosch_atomic64_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_ceqe_buf_fifo_ecc_int_en(unsigned int uosch_ceqe_buf_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_payload_fifo_ecc_int_en(unsigned int uosch_payload_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_payload_fifo1_ecc_int_en(unsigned int uosch_payload_fifo1_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_payload_fifo_hva_ecc_int_en(unsigned int uosch_payload_fifo_hva_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_payload_fifo1_hva_ecc_int_en(unsigned int uosch_payload_fifo1_hva_ecc_int_en); +int iSetOSCH_ECC_INT_EN_4_osch_doorbell_fifo_ecc_int_en(unsigned int uosch_doorbell_fifo_ecc_int_en); +int iSetOSCH_ECC_INT_EN_5_osch_payload_fifo_np_ecc_int_en(unsigned int uosch_payload_fifo_np_ecc_int_en); +int iSetOSCH_ECC_INT_EN_5_osch_payload_fifo1_np_ecc_int_en(unsigned int uosch_payload_fifo1_np_ecc_int_en); +int iSetOSCH_ECC_INT_EN_5_osch_payload_fifo_hva_np_ecc_int_en(unsigned int uosch_payload_fifo_hva_np_ecc_int_en); +int iSetOSCH_ECC_INT_EN_5_osch_payload_fifo1_hva_np_ecc_int_en(unsigned int uosch_payload_fifo1_hva_np_ecc_int_en); +int iSetOSCH_ECC_ERR_ADDR_0_osch_payload_fifo1_ecc_erraddr(unsigned int uosch_payload_fifo1_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_0_osch_payload_fifo_hva_ecc_erraddr(unsigned int uosch_payload_fifo_hva_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_0_osch_payload_fifo1_hva_ecc_erraddr(unsigned int uosch_payload_fifo1_hva_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_1_osch_port0_ecc_erraddr(unsigned int uosch_port0_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_1_osch_ceqe_buf_ecc_erraddr(unsigned int uosch_ceqe_buf_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_1_osch_payload_fifo_ecc_erraddr(unsigned int uosch_payload_fifo_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_2_osch_port1_ecc_erraddr(unsigned int uosch_port1_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_2_osch_port2_ecc_erraddr(unsigned int uosch_port2_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_2_osch_port3_ecc_erraddr(unsigned int uosch_port3_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_3_osch_port4_ecc_erraddr(unsigned int uosch_port4_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_3_osch_payload_fifo1_hva_np_ecc_erraddr(unsigned int uosch_payload_fifo1_hva_np_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_3_osch_doorbell_fifo_ecc_erraddr(unsigned int uosch_doorbell_fifo_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_4_osch_payload_fifo_np_ecc_erraddr(unsigned int uosch_payload_fifo_np_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_4_osch_payload_fifo1_np_ecc_erraddr(unsigned int uosch_payload_fifo1_np_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_4_osch_payload_fifo_hva_np_ecc_erraddr(unsigned int uosch_payload_fifo_hva_np_ecc_erraddr); +int iSetOSCH_ECC_ERR_ADDR_SEL_osch_ecc_err_addr_port0_sel(unsigned int uosch_ecc_err_addr_port0_sel); +int iSetOSCH_ECC_ERR_ADDR_SEL_osch_ecc_err_addr_port1_sel(unsigned int uosch_ecc_err_addr_port1_sel); +int iSetOSCH_ECC_ERR_ADDR_SEL_osch_ecc_err_addr_port2_sel(unsigned int uosch_ecc_err_addr_port2_sel); +int iSetOSCH_ECC_ERR_ADDR_SEL_osch_ecc_err_addr_port3_sel(unsigned int uosch_ecc_err_addr_port3_sel); +int iSetOSCH_ECC_ERR_ADDR_SEL_osch_ecc_err_addr_port4_sel(unsigned int uosch_ecc_err_addr_port4_sel); +int iSetOSCH_OVERFLOW_INT_0_atomic64_tx_fifo_overf(unsigned int uatomic64_tx_fifo_overf); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo_hva_overf_np(unsigned int upayload_fifo_hva_overf_np); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo1_hva_overf_np(unsigned int upayload_fifo1_hva_overf_np); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo1_overf_np(unsigned int upayload_fifo1_overf_np); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo_overf_np(unsigned int upayload_fifo_overf_np); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo_hva_overf(unsigned int upayload_fifo_hva_overf); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo1_hva_overf(unsigned int upayload_fifo1_hva_overf); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo1_overf(unsigned int upayload_fifo1_overf); +int iSetOSCH_OVERFLOW_INT_0_dbell_fifo_overf(unsigned int udbell_fifo_overf); +int iSetOSCH_OVERFLOW_INT_0_payload_fifo_overf(unsigned int upayload_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_cpath_q2_fifo_overf(unsigned int ucpath_q2_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_cpath_q1_fifo_overf(unsigned int ucpath_q1_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_cpath_q0_fifo_overf(unsigned int ucpath_q0_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_ceqe_tx_fifo_overf(unsigned int uceqe_tx_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_atomic_tx_fifo_overf(unsigned int uatomic_tx_fifo_overf); +int iSetOSCH_OVERFLOW_INT_1_msi_tx_fifo_overf(unsigned int umsi_tx_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_cpld_fifo_overf(unsigned int ucpld_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_dpath_q4_fifo_overf(unsigned int udpath_q4_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_dpath_q3_fifo_overf(unsigned int udpath_q3_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_dpath_q2_fifo_overf(unsigned int udpath_q2_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_dpath_q1_fifo_overf(unsigned int udpath_q1_fifo_overf); +int iSetOSCH_OVERFLOW_INT_2_dpath_q0_fifo_overf(unsigned int udpath_q0_fifo_overf); +int iSetOSCH_OVERFLOW_INT_EN_0_atomic64_tx_fifo_overf_int_en(unsigned int uatomic64_tx_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo_hva_overf_np_int_en(unsigned int upayload_fifo_hva_overf_np_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo1_hva_overf_np_int_en(unsigned int upayload_fifo1_hva_overf_np_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo1_overf_np_int_en(unsigned int upayload_fifo1_overf_np_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo_overf_np_int_en(unsigned int upayload_fifo_overf_np_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo_hva_overf_int_en(unsigned int upayload_fifo_hva_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo1_hva_overf_int_en(unsigned int upayload_fifo1_hva_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo1_overf_int_en(unsigned int upayload_fifo1_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_dbell_fifo_overf_int_en(unsigned int udbell_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_0_payload_fifo_overf_int_en(unsigned int upayload_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_cpath_q2_fifo_overf_int_en(unsigned int ucpath_q2_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_cpath_q1_fifo_overf_int_en(unsigned int ucpath_q1_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_cpath_q0_fifo_overf_int_en(unsigned int ucpath_q0_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_ceqe_tx_fifo_overf_int_en(unsigned int uceqe_tx_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_atomic_tx_fifo_overf_int_en(unsigned int uatomic_tx_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_1_msi_tx_fifo_overf_int_en(unsigned int umsi_tx_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_cpld_fifo_overf_int_en(unsigned int ucpld_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_dpath_q4_fifo_overf_int_en(unsigned int udpath_q4_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_dpath_q3_fifo_overf_int_en(unsigned int udpath_q3_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_dpath_q2_fifo_overf_int_en(unsigned int udpath_q2_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_dpath_q1_fifo_overf_int_en(unsigned int udpath_q1_fifo_overf_int_en); +int iSetOSCH_OVERFLOW_INT_EN_2_dpath_q0_fifo_overf_int_en(unsigned int udpath_q0_fifo_overf_int_en); +int iSetOSCH_CRT_ERR_cur_port_timeout(unsigned int ucur_port_timeout); +int iSetOSCH_CRT_ERR_port_sch_tlp_err(unsigned int uport_sch_tlp_err); +int iSetOSCH_CRT_ERR_port_sch_tlp_err_hva(unsigned int uport_sch_tlp_err_hva); +int iSetOSCH_CRT_ERR_port_sch_tlp_err_npcpl(unsigned int uport_sch_tlp_err_npcpl); +int iSetOSCH_CRT_ERR_port_sch_tlp_err_hva_npcpl(unsigned int uport_sch_tlp_err_hva_npcpl); +int iSetOSCH_CRT_ERR_cpi_osch_ceqe_drop_req(unsigned int ucpi_osch_ceqe_drop_req); +int iSetOSCH_CRT_ERR_port_sch_phy_addr_err(unsigned int uport_sch_phy_addr_err); +int iSetOSCH_CRT_ERR_port_sch_phy_addr_err_npcpl(unsigned int uport_sch_phy_addr_err_npcpl); +int iSetOSCH_UNCRT_ERR_dpath_req_drop_p(unsigned int udpath_req_drop_p); +int iSetOSCH_UNCRT_ERR_cpi_osch_int_ceq_credit_err_p(unsigned int ucpi_osch_int_ceq_credit_err_p); +int iSetOSCH_UNCRT_ERR_osch_loss_sopeop_err(unsigned int uosch_loss_sopeop_err); +int iSetOSCH_CRT_ERR_INT_EN_cur_port_timeout_int_en(unsigned int ucur_port_timeout_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_tlp_err_int_en(unsigned int uport_sch_tlp_err_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_tlp_err_hva_int_en(unsigned int uport_sch_tlp_err_hva_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_tlp_err_npcpl_int_en(unsigned int uport_sch_tlp_err_npcpl_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_tlp_err_hva_npcpl_int_en(unsigned int uport_sch_tlp_err_hva_npcpl_int_en); +int iSetOSCH_CRT_ERR_INT_EN_cpi_osch_ceqe_drop_req_int_en(unsigned int ucpi_osch_ceqe_drop_req_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_phy_addr_err_int_en(unsigned int uport_sch_phy_addr_err_int_en); +int iSetOSCH_CRT_ERR_INT_EN_port_sch_phy_addr_err_npcpl_int_en(unsigned int uport_sch_phy_addr_err_npcpl_int_en); +int iSetOSCH_UNCRT_ERR_INT_EN_dpath_req_drop_p_int_en(unsigned int udpath_req_drop_p_int_en); +int iSetOSCH_UNCRT_ERR_INT_EN_cpi_osch_int_ceq_credit_err_p_int_en(unsigned int ucpi_osch_int_ceq_credit_err_p_int_en); +int iSetOSCH_UNCRT_ERR_INT_EN_osch_loss_sopeop_err_int_en(unsigned int uosch_loss_sopeop_err_int_en); +int iSetOSCH_ACTIVE_EN_CFG_active_en_cfg_value(unsigned int uactive_en_cfg_value); +int iSetOSCH_ACTIVE_EN_CFG_active_en_cfg_enable(unsigned int uactive_en_cfg_enable); +int iSetOSCH_NL2NIC_OUTSTANDING_BP_CFG_cfg_non_l2nic_outstanding_bp_th(unsigned int ucfg_non_l2nic_outstanding_bp_th); +int iSetOSCH_NL2NIC_OUTSTANDING_BP_CFG_cfg_non_l2nic_outstanding_bp_en(unsigned int ucfg_non_l2nic_outstanding_bp_en); +int iSetCEQ_CLS_FIFO_ST_ERR_ceq_cls_fifo_st_err(unsigned int uceq_cls_fifo_st_err); +int iSetGLB_CQE_CI_D_CHL_glb_ceqe_sch_period(unsigned int uglb_ceqe_sch_period); +int iSetGLB_CQE_CI_D_CHL_glb_osch_non_l2nic_outstanding_cfg(unsigned int uglb_osch_non_l2nic_outstanding_cfg); +int iSetGLB_DMA_SO_RO_REPLACE_glb_dma_so_ro_cfg(unsigned int uglb_dma_so_ro_cfg); +int iSetGLB_DMA_SO_RO_REPLACE_glb_dma_so_ro_replace_mode(unsigned int uglb_dma_so_ro_replace_mode); +int iSetGLB_OSCH_RLS_TAG_EN_glb_osch_rls_tag_en(unsigned int uglb_osch_rls_tag_en); +int iSetGLB_OSCH_TIMEOUT_glb_osch_timeout_cfg(unsigned int uglb_osch_timeout_cfg); +int iSetGLB_CP_CQE_CREDIT_PORT_port4_cqe_credit_cfg(unsigned int uport4_cqe_credit_cfg); +int iSetGLB_CP_CQE_CREDIT_PORT_port3_cqe_credit_cfg(unsigned int uport3_cqe_credit_cfg); +int iSetGLB_CP_CQE_CREDIT_PORT_port2_cqe_credit_cfg(unsigned int uport2_cqe_credit_cfg); +int iSetGLB_CP_CQE_CREDIT_PORT_port1_cqe_credit_cfg(unsigned int uport1_cqe_credit_cfg); +int iSetGLB_CP_CQE_CREDIT_PORT_port0_cqe_credit_cfg(unsigned int uport0_cqe_credit_cfg); +int iSetGLB_OSCH_ADDR_HI_LMT_H_glb_osch_addr_hi_lmt_h(unsigned int uglb_osch_addr_hi_lmt_h); +int iSetGLB_OSCH_ADDR_HI_LMT_L_glb_osch_addr_hi_lmt_l(unsigned int uglb_osch_addr_hi_lmt_l); +int iSetGLB_OSCH_ADDR_LO_LMT_H_glb_osch_addr_lo_lmt_h(unsigned int uglb_osch_addr_lo_lmt_h); +int iSetGLB_OSCH_ADDR_LO_LMT_L_glb_osch_addr_lo_lmt_l(unsigned int uglb_osch_addr_lo_lmt_l); +int iSetGLB_OSCH_ADDR_OUT_RANGE_H_glb_osch_addr_out_range_h(unsigned int uglb_osch_addr_out_range_h); +int iSetGLB_OSCH_ADDR_OUT_RANGE_L_glb_osch_addr_out_range_l(unsigned int uglb_osch_addr_out_range_l); +int iSetOSCH_PAYLOAD_FIFO1_CTRL_osch_payload_fifo1_ctrl_all_port(unsigned int uosch_payload_fifo1_ctrl_all_port); +int iSetOSCH_DBELL_FIFO_CTRL_osch_dbell_fifo_ctrl_all_port(unsigned int uosch_dbell_fifo_ctrl_all_port); +int iSetCFG_DOORBELL_WR_CMD_EN_cfg_doorbell_wr_cmd_en(unsigned int ucfg_doorbell_wr_cmd_en); +int iSetCFG_DOORBELL_CRDT_INITIAL_cfg_doorbell_crdt_initial(unsigned int ucfg_doorbell_crdt_initial); +int iSetCFG_DPATH_XTS_RD_cfg_dpath_xts_rd_chl(unsigned int ucfg_dpath_xts_rd_chl); +int iSetCFG_DPATH_XTS_RD_cfg_dpath_xts_rd_en(unsigned int ucfg_dpath_xts_rd_en); +int iSetCFG_ROUND_BIT_CHECK_MOD_cfg_round_bit_check_mod(unsigned int ucfg_round_bit_check_mod); +int iSetCFG_PORT1_TO_PORT0_MODE_cfg_port1_to_port0_mode(unsigned int ucfg_port1_to_port0_mode); +int iSetCFG_NON_L2NIC_LOOP2_EDGE_EN_cfg_non_l2nic_loop2_edge_en(unsigned int ucfg_non_l2nic_loop2_edge_en); +int iSetCFG_CUR_CPL_TIMEOUT_DROP_MAX_cfg_cur_cpl_timeout_drop_max(unsigned int ucfg_cur_cpl_timeout_drop_max); +int iSetOSCH_TLP_NPCPL_DROP_CNT_PORT0_osch_tlp_npcpl_drop_count_port0(unsigned int uosch_tlp_npcpl_drop_count_port0); +int iSetOSCH_TLP_NPCPL_DROP_CNT_PORT1_osch_tlp_npcpl_drop_count_port1(unsigned int uosch_tlp_npcpl_drop_count_port1); +int iSetOSCH_TLP_NPCPL_DROP_CNT_PORT2_osch_tlp_npcpl_drop_count_port2(unsigned int uosch_tlp_npcpl_drop_count_port2); +int iSetOSCH_TLP_NPCPL_DROP_CNT_PORT3_osch_tlp_npcpl_drop_count_port3(unsigned int uosch_tlp_npcpl_drop_count_port3); +int iSetOSCH_TLP_NPCPL_DROP_CNT_PORT4_osch_tlp_npcpl_drop_count_port4(unsigned int uosch_tlp_npcpl_drop_count_port4); +int iSetOSCH_TLP_NPCPL_ERROR_CNT0_osch_tlp_npcpl_err_count_port3(unsigned int uosch_tlp_npcpl_err_count_port3); +int iSetOSCH_TLP_NPCPL_ERROR_CNT0_osch_tlp_npcpl_err_count_port2(unsigned int uosch_tlp_npcpl_err_count_port2); +int iSetOSCH_TLP_NPCPL_ERROR_CNT0_osch_tlp_npcpl_err_count_port1(unsigned int uosch_tlp_npcpl_err_count_port1); +int iSetOSCH_TLP_NPCPL_ERROR_CNT0_osch_tlp_npcpl_err_count_port0(unsigned int uosch_tlp_npcpl_err_count_port0); +int iSetOSCH_TLP_NPCPL_ERROR_CNT1_osch_tlp_npcpl_err_count_port4(unsigned int uosch_tlp_npcpl_err_count_port4); +int iSetOSCH_TLP_NPCPL_DROP_CNT0_osch_tlp_npcpl_drop_count0(unsigned int uosch_tlp_npcpl_drop_count0); +int iSetOSCH_TLP_NPCPL_DROP_CNT1_osch_tlp_npcpl_drop_count1(unsigned int uosch_tlp_npcpl_drop_count1); +int iSetOSCH_TLP_NPCPL_DROP_CNT2_osch_tlp_npcpl_drop_count2(unsigned int uosch_tlp_npcpl_drop_count2); +int iSetOSCH_TLP_NPCPL_DROP_CNT3_osch_tlp_npcpl_drop_count3(unsigned int uosch_tlp_npcpl_drop_count3); +int iSetOSCH_TLP_NPCPL_DROP_CNT4_osch_tlp_npcpl_drop_count4(unsigned int uosch_tlp_npcpl_drop_count4); +int iSetOSCH_TLP_NPCPL_DROP_CNT5_osch_tlp_npcpl_drop_count5(unsigned int uosch_tlp_npcpl_drop_count5); +int iSetOSCH_TLP_NPCPL_DROP_CNT6_osch_tlp_npcpl_drop_count6(unsigned int uosch_tlp_npcpl_drop_count6); +int iSetOSCH_TLP_NPCPL_DROP_CNT7_osch_tlp_npcpl_drop_count7(unsigned int uosch_tlp_npcpl_drop_count7); +int iSetOSCH_TLP_NPCPL_DROP_CNT8_osch_tlp_npcpl_drop_count8(unsigned int uosch_tlp_npcpl_drop_count8); +int iSetOSCH_TLP_NPCPL_DROP_CNT9_osch_tlp_npcpl_drop_count9(unsigned int uosch_tlp_npcpl_drop_count9); +int iSetOSCH_TLP_NPCPL_DROP_CNT10_osch_tlp_npcpl_drop_count10(unsigned int uosch_tlp_npcpl_drop_count10); +int iSetOSCH_TLP_NPCPL_DROP_CNT11_osch_tlp_npcpl_drop_count11(unsigned int uosch_tlp_npcpl_drop_count11); +int iSetOSCH_TLP_NPCPL_DROP_CNT12_osch_tlp_npcpl_drop_count12(unsigned int uosch_tlp_npcpl_drop_count12); +int iSetOSCH_TLP_NPCPL_DROP_CNT13_osch_tlp_npcpl_drop_count13(unsigned int uosch_tlp_npcpl_drop_count13); +int iSetOSCH_TLP_NPCPL_DROP_CNT14_osch_tlp_npcpl_drop_count14(unsigned int uosch_tlp_npcpl_drop_count14); +int iSetOSCH_TLP_NPCPL_DROP_CNT15_osch_tlp_npcpl_drop_count15(unsigned int uosch_tlp_npcpl_drop_count15); +int iSetOSCH_TLP_HVA_P_DROP_CNT0_osch_tlp_hva_p_drop_count0(unsigned int uosch_tlp_hva_p_drop_count0); +int iSetOSCH_TLP_HVA_P_DROP_CNT1_osch_tlp_hva_p_drop_count1(unsigned int uosch_tlp_hva_p_drop_count1); +int iSetOSCH_TLP_HVA_P_DROP_CNT2_osch_tlp_hva_p_drop_count2(unsigned int uosch_tlp_hva_p_drop_count2); +int iSetOSCH_TLP_HVA_P_DROP_CNT3_osch_tlp_hva_p_drop_count3(unsigned int uosch_tlp_hva_p_drop_count3); +int iSetOSCH_TLP_HVA_P_DROP_CNT4_osch_tlp_hva_p_drop_count4(unsigned int uosch_tlp_hva_p_drop_count4); +int iSetOSCH_TLP_HVA_P_DROP_CNT5_osch_tlp_hva_p_drop_count5(unsigned int uosch_tlp_hva_p_drop_count5); +int iSetOSCH_TLP_HVA_P_DROP_CNT6_osch_tlp_hva_p_drop_count6(unsigned int uosch_tlp_hva_p_drop_count6); +int iSetOSCH_TLP_HVA_P_DROP_CNT7_osch_tlp_hva_p_drop_count7(unsigned int uosch_tlp_hva_p_drop_count7); +int iSetOSCH_TLP_HVA_P_DROP_CNT8_osch_tlp_hva_p_drop_count8(unsigned int uosch_tlp_hva_p_drop_count8); +int iSetOSCH_TLP_HVA_P_DROP_CNT9_osch_tlp_hva_p_drop_count9(unsigned int uosch_tlp_hva_p_drop_count9); +int iSetOSCH_TLP_HVA_P_DROP_CNT10_osch_tlp_hva_p_drop_count10(unsigned int uosch_tlp_hva_p_drop_count10); +int iSetOSCH_TLP_HVA_P_DROP_CNT11_osch_tlp_hva_p_drop_count11(unsigned int uosch_tlp_hva_p_drop_count11); +int iSetOSCH_TLP_HVA_P_DROP_CNT12_osch_tlp_hva_p_drop_count12(unsigned int uosch_tlp_hva_p_drop_count12); +int iSetOSCH_TLP_HVA_P_DROP_CNT13_osch_tlp_hva_p_drop_count13(unsigned int uosch_tlp_hva_p_drop_count13); +int iSetOSCH_TLP_HVA_P_DROP_CNT14_osch_tlp_hva_p_drop_count14(unsigned int uosch_tlp_hva_p_drop_count14); +int iSetOSCH_TLP_HVA_P_DROP_CNT15_osch_tlp_hva_p_drop_count15(unsigned int uosch_tlp_hva_p_drop_count15); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT0_osch_tlp_hva_npcpl_drop_count0(unsigned int uosch_tlp_hva_npcpl_drop_count0); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT1_osch_tlp_hva_npcpl_drop_count1(unsigned int uosch_tlp_hva_npcpl_drop_count1); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT2_osch_tlp_hva_npcpl_drop_count2(unsigned int uosch_tlp_hva_npcpl_drop_count2); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT3_osch_tlp_hva_npcpl_drop_count3(unsigned int uosch_tlp_hva_npcpl_drop_count3); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT4_osch_tlp_hva_npcpl_drop_count4(unsigned int uosch_tlp_hva_npcpl_drop_count4); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT5_osch_tlp_hva_npcpl_drop_count5(unsigned int uosch_tlp_hva_npcpl_drop_count5); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT6_osch_tlp_hva_npcpl_drop_count6(unsigned int uosch_tlp_hva_npcpl_drop_count6); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT7_osch_tlp_hva_npcpl_drop_count7(unsigned int uosch_tlp_hva_npcpl_drop_count7); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT8_osch_tlp_hva_npcpl_drop_count8(unsigned int uosch_tlp_hva_npcpl_drop_count8); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT9_osch_tlp_hva_npcpl_drop_count9(unsigned int uosch_tlp_hva_npcpl_drop_count9); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT10_osch_tlp_hva_npcpl_drop_count10(unsigned int uosch_tlp_hva_npcpl_drop_count10); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT11_osch_tlp_hva_npcpl_drop_count11(unsigned int uosch_tlp_hva_npcpl_drop_count11); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT12_osch_tlp_hva_npcpl_drop_count12(unsigned int uosch_tlp_hva_npcpl_drop_count12); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT13_osch_tlp_hva_npcpl_drop_count13(unsigned int uosch_tlp_hva_npcpl_drop_count13); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT14_osch_tlp_hva_npcpl_drop_count14(unsigned int uosch_tlp_hva_npcpl_drop_count14); +int iSetOSCH_TLP_HVA_NPCPL_DROP_CNT15_osch_tlp_hva_npcpl_drop_count15(unsigned int uosch_tlp_hva_npcpl_drop_count15); +int iSetOSCH_TLP_DROP_COUNT_MODE_osch_tlp_drop_count_mode(unsigned int uosch_tlp_drop_count_mode); +int iSetOSCH_NPCPL_PERF_WATCH_BYTE_osch_npcpl_perf_watch_byte(unsigned int uosch_npcpl_perf_watch_byte); +int iSetOSCH_NPCPL_PERF_WATCH_TLP_osch_npcpl_perf_watch_tlp(unsigned int uosch_npcpl_perf_watch_tlp); +int iSetOSCH_HVA_P_PERF_WATCH_BYTE_osch_hva_p_perf_watch_byte(unsigned int uosch_hva_p_perf_watch_byte); +int iSetOSCH_HVA_P_PERF_WATCH_TLP_osch_hva_p_perf_watch_tlp(unsigned int uosch_hva_p_perf_watch_tlp); +int iSetOSCH_HVA_NPCPL_PERF_WATCH_BYTE_osch_hva_npcpl_perf_watch_byte(unsigned int uosch_hva_npcpl_perf_watch_byte); +int iSetOSCH_HVA_NPCPL_PERF_WATCH_TLP_osch_hva_npcpl_perf_watch_tlp(unsigned int uosch_hva_npcpl_perf_watch_tlp); + + +#endif // CPI_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_dfx_glb_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_dfx_glb_reg_offset.h new file mode 100644 index 000000000..9b0618cf7 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_dfx_glb_reg_offset.h @@ -0,0 +1,236 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2016, Hisilicon Technologies Co. Ltd. +// File name : cpi_dfx_glb_reg_offset.h +// Project line : IT产品线 +// Department : 图灵ICT处理器开发部 +// Author : xxx +// Version : V100 +// Date : 2014/5/8 +// Description : Hi 1822 is a throughput of 100Gbps CNA chip. It provide large bandwith, low latency, scalability +// converged network solution, support network convergency, virtualization, protocol offload, and serves IT product and +// CT product. Others : Generated automatically by nManager V4.0.2.5 History : xxx 2016/10/25 15:05:13 +// Create file +// ****************************************************************************** + +#ifndef CPI_DFX_GLB_REG_OFFSET_H +#define CPI_DFX_GLB_REG_OFFSET_H + +/* CPI_DFX_GLB Base address of Module's Register */ +#define HI1822_CPI_DFX_GLB_BASE (0x41af000) +#define CPI_DFX_TYPE_GLB (0x0) + +/* **************************************************************************** */ +/* HI1822 CPI_DFX_GLB Registers' Definitions */ +/* **************************************************************************** */ + +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_CFG_REG (HI1822_CPI_DFX_GLB_BASE + 0x0) /* CPI debug control */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_MRD_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x4) /* CPI debug Rx Mrd TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_MWR_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x8) /* CPI debug Rx Mwr TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_CPL_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0xC) /* CPI debug Rx CPL/CPLD TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_DBL_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x10) /* CPI debug Rx UR Mrd TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_DWQE_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x14) /* CPI debug Rx UR Mrd TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_ESL__TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x18) /* CPI debug Rx others TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_BAR_HIT6_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x1C) /* CPI debug Rx BAR hit == 6 TLP counter */ +#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_STS_REG (HI1822_CPI_DFX_GLB_BASE + 0x400) /* CPI BP WATCH Status */ +#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_WINDOW_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x404) /* CPI backpressure watch window */ +#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_BITMAP_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x408) /* CPI backpressure watch bitmap */ +#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_START_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x40C) /* CPI backpressure watch start */ +#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x410) /* CPI backpressure watch counter */ +#define HI1822_CPI_DFX_GLB_GLB_CSR_TIMEOUT_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x414) +#define HI1822_CPI_DFX_GLB_DWQE_API_NO_ENOUGH_DATA_REG (HI1822_CPI_DFX_GLB_BASE + 0x418) +#define HI1822_CPI_DFX_GLB_DWQE_DBL_NO_ENOUGH_DATA_REG (HI1822_CPI_DFX_GLB_BASE + 0x41C) +#define HI1822_CPI_DFX_GLB_NORM_DBL_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x420) +#define HI1822_CPI_DFX_GLB_NORM_DBL_TX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x424) +#define HI1822_CPI_DFX_GLB_DWQE_DBL_TX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x428) +#define HI1822_CPI_DFX_GLB_DWQE_API_TX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x42C) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_BP_MSK_REG (HI1822_CPI_DFX_GLB_BASE + 0x430) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_CNT_PORT_REG (HI1822_CPI_DFX_GLB_BASE + 0x434) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_BP_ON_PORT_REG (HI1822_CPI_DFX_GLB_BASE + 0x438) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_BP_OFF_PORT_REG (HI1822_CPI_DFX_GLB_BASE + 0x43C) +#define HI1822_CPI_DFX_GLB_DWQE_REQ_BUF_BGN_REG (HI1822_CPI_DFX_GLB_BASE + 0x440) +#define HI1822_CPI_DFX_GLB_DWQE_DROPPING_IN_TX_REG (HI1822_CPI_DFX_GLB_BASE + 0x444) +#define HI1822_CPI_DFX_GLB_DWQE_DROPPING_NO_BUF_REG (HI1822_CPI_DFX_GLB_BASE + 0x448) +#define HI1822_CPI_DFX_GLB_DWQE_DBL_WITHOUT_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x44C) +#define HI1822_CPI_DFX_GLB_DWQE_TX_DBL_AFTER_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x450) +#define HI1822_CPI_DFX_GLB_DWQE_NO_DBL_AFTER_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x454) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_OVERWRITE_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x458) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_AGING_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x45C) +#define HI1822_CPI_DFX_GLB_DWQE_TX_REQ_FIFO_PUSH_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x460) +#define HI1822_CPI_DFX_GLB_DWQE_TX_REQ_FIFO_POP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x464) +#define HI1822_CPI_DFX_GLB_DWQE_TX_REQ_FIFO_STS_REG (HI1822_CPI_DFX_GLB_BASE + 0x468) +#define HI1822_CPI_DFX_GLB_CPI_DPATH_O_FSM_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x46C) +#define HI1822_CPI_DFX_GLB_CPI_DPATH_O_CNT_TYPE_REG (HI1822_CPI_DFX_GLB_BASE + 0x470) +#define HI1822_CPI_DFX_GLB_DWQE_DROPPING_INVLD_REG (HI1822_CPI_DFX_GLB_BASE + 0x474) +#define HI1822_CPI_DFX_GLB_DWQE_SW_FORCE_DROP_REG (HI1822_CPI_DFX_GLB_BASE + 0x478) +#define HI1822_CPI_DFX_GLB_ICTL_DBL_REQ_SOP_NULL_REG (HI1822_CPI_DFX_GLB_BASE + 0x47C) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x480) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x484) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x488) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x48C) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x490) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x494) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x498) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x49C) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x4A0) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x4A4) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x4A8) +#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x4AC) +#define HI1822_CPI_DFX_GLB_CEQ_CI_SW_WR_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4B0) +#define HI1822_CPI_DFX_GLB_AEQ_CI_SW_WR_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4B4) +#define HI1822_CPI_DFX_GLB_CEQ_TX_INT_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4B8) +#define HI1822_CPI_DFX_GLB_AEQ_TX_INT_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4BC) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_WR_PCIE_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4C0) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_WR_UCPU_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4C4) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_RD_PCIE_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4C8) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_RD_UCPU_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4CC) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_OSCH_CPL_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4D0) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_ICTL_CPL_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4D4) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_APICTL_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4D8) +#define HI1822_CPI_DFX_GLB_CPI_PCIE_MB_AEQE_TO_DST_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4DC) +#define HI1822_CPI_DFX_GLB_CPI_PCIE_MB_AEQE_TO_SRC_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4E0) +#define HI1822_CPI_DFX_GLB_CPI_PCIE_MB_STAT_TO_SRC_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4E4) +#define HI1822_CPI_DFX_GLB_CPI_UCPU_MB_AEQE_TO_DST_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4E8) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_AEQ_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4EC) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_CEQ_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4F0) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_API_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4F4) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_INTCTL_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4F8) +#define HI1822_CPI_DFX_GLB_CPI_IPUSH_UPITF_CLP_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4FC) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR0_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x500) /* CPI internal RAM ECC error injection */ +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x504) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x508) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x50C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x510) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x514) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x518) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x51C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x520) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x524) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x528) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x52C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x530) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x534) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x538) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x53C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x540) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x544) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x548) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x54C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x550) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x554) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x558) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x55C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x560) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x564) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x568) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x56C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x570) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x574) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x578) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x57C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR8_REG (HI1822_CPI_DFX_GLB_BASE + 0x580) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x590) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x594) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x598) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x59C) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x5A0) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x5A4) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x5A8) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x5AC) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR8_REG (HI1822_CPI_DFX_GLB_BASE + 0x5B0) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR9_REG (HI1822_CPI_DFX_GLB_BASE + 0x5B4) +#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR10_REG (HI1822_CPI_DFX_GLB_BASE + 0x5B8) +#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5C0) +#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5C4) +#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED2_REG (HI1822_CPI_DFX_GLB_BASE + 0x5C8) +#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED3_REG (HI1822_CPI_DFX_GLB_BASE + 0x5CC) +#define HI1822_CPI_DFX_GLB_GLB_CPI_UNCRT_ERR_CODE0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5D0) +#define HI1822_CPI_DFX_GLB_GLB_CPI_UNCRT_ERR_CODE1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5D4) +#define HI1822_CPI_DFX_GLB_GLB_CPI_CRT_ERR_CODE0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5D8) +#define HI1822_CPI_DFX_GLB_GLB_CPI_CRT_ERR_CODE1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5DC) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_DBG0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5E0) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_DBG1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5E4) +#define HI1822_CPI_DFX_GLB_DWQE_BUF_DBG2_REG (HI1822_CPI_DFX_GLB_BASE + 0x5E8) +#define HI1822_CPI_DFX_GLB_ICTL_RX_MWR_TLP_PASS_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5F0) +#define HI1822_CPI_DFX_GLB_ICTL_RX_MWR_TLP_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5F4) +#define HI1822_CPI_DFX_GLB_ICTL_RX_MRD_TLP_PASS_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5F8) +#define HI1822_CPI_DFX_GLB_ICTL_RX_UNS_NP_TLP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5FC) +#define HI1822_CPI_DFX_GLB_PCIE_ICTL_SOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x600) +#define HI1822_CPI_DFX_GLB_PCIE_ICTL_EOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x604) +#define HI1822_CPI_DFX_GLB_ICTL_IPUSH_SOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x608) +#define HI1822_CPI_DFX_GLB_ICTL_IPUSH_EOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x60C) +#define HI1822_CPI_DFX_GLB_GLB_MB_GRP_TX_REQ_REG (HI1822_CPI_DFX_GLB_BASE + 0x610) +#define HI1822_CPI_DFX_GLB_GLB_MB_IN_GRP_TX_REQ_REG (HI1822_CPI_DFX_GLB_BASE + 0x614) +#define HI1822_CPI_DFX_GLB_GLB_MB_GRP_GRANT_REG (HI1822_CPI_DFX_GLB_BASE + 0x618) +#define HI1822_CPI_DFX_GLB_GLB_MB_IN_GRP_GRANT_REG (HI1822_CPI_DFX_GLB_BASE + 0x61C) +#define HI1822_CPI_DFX_GLB_GLB_MB_TX_START_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x620) +#define HI1822_CPI_DFX_GLB_GLB_MB_TX_ILLEGAL_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x624) +#define HI1822_CPI_DFX_GLB_GLB_MB_TX_ILLEGAL_CODE_REG (HI1822_CPI_DFX_GLB_BASE + 0x628) +#define HI1822_CPI_DFX_GLB_GLB_MB_FSM_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x62C) +#define HI1822_CPI_DFX_GLB_DFX_DPATH_O_HISTORY_REG (HI1822_CPI_DFX_GLB_BASE + 0x630) +#define HI1822_CPI_DFX_GLB_DFX_DPATH_O_STATUS_REG (HI1822_CPI_DFX_GLB_BASE + 0x634) +#define HI1822_CPI_DFX_GLB_ICTL_INBD_FIFO_STS_REG (HI1822_CPI_DFX_GLB_BASE + 0x638) +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_INC_CFG_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x640) /* non-MAC Timestamp timer configuration */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_CALIBRATION_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x644) /* non-MAC Timestamp timer calibration */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_WR_DATA0_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x648) /* non-MAC Timestamp timer write data 0 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_WR_DATA1_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x64C) /* non-MAC Timestamp timer write data 1 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_WR_DATA2_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x650) /* non-MAC Timestamp timer write data 2 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_RD_DATA0_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x654) /* non-MAC Timestamp timer read data 0 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_RD_DATA1_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x658) /* non-MAC Timestamp timer read data 1 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_RD_DATA2_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x65C) /* non-MAC Timestamp timer read data 2 */ +#define HI1822_CPI_DFX_GLB_NON_PTP_TS_UP_EN_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x660) /* non-MAC Timestamp timer update enable */ +#define HI1822_CPI_DFX_GLB_NON_PTP_DSTR_CFG_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x664) /* non-MAC Timestamp distribute configuration */ +#define HI1822_CPI_DFX_GLB_PCIE_PENDING_TAG_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x670) /* 接收来自PCIe的数目 */ +#define HI1822_CPI_DFX_GLB_ICTL_SND_ERR_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x674) /* 发送给PCIe AER的数目 */ +#define HI1822_CPI_DFX_GLB_ICTL_RX_CPLD_TLP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x678) +#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x680) +#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x684) +#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x688) +#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x68C) +#define HI1822_CPI_DFX_GLB_NORM_DBL_RX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x690) +#define HI1822_CPI_DFX_GLB_NORM_DBL_FORCE_DROP_REG (HI1822_CPI_DFX_GLB_BASE + 0x694) +#define HI1822_CPI_DFX_GLB_DWQE_RX_BUF_BGN_REG (HI1822_CPI_DFX_GLB_BASE + 0x698) +#define HI1822_CPI_DFX_GLB_DWQE_ILLEGAL_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x69C) +#define HI1822_CPI_DFX_GLB_DWQE_DBL_FORCE_DROP_NO_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x6A0) +#define HI1822_CPI_DFX_GLB_DWQE_DBL_FORCE_DROP_AFT_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x6A4) +#define HI1822_CPI_DFX_GLB_AEQ_FSM_DBG_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x6A8) +#define HI1822_CPI_DFX_GLB_CEQ_FSM_DBG_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x6AC) +#define HI1822_CPI_DFX_GLB_GLB_UCPU_MSI_FUNC_IDX_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x6B0) /* the function index when ucpu access CSRs in the INT_CTL */ +#define HI1822_CPI_DFX_GLB_PCIE_INBD_ITF_WIND_CTL_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x6B4) /* the control register to measure the inbound itf */ +#define HI1822_CPI_DFX_GLB_PCIE_INBD_ITF_WIND_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x6B8) /* the result for the window detect for the mode */ +#define HI1822_CPI_DFX_GLB_PCIE_INBD_ITF_WIND_TLP_CNT_REG \ + (HI1822_CPI_DFX_GLB_BASE + 0x6BC) /* the result for the window detect for the TLP */ +#define HI1822_CPI_DFX_GLB_GLB_DBG_CNT_DBL_GRP_EN_REG (HI1822_CPI_DFX_GLB_BASE + 0x6C0) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_TIMER_CFG_REG (HI1822_CPI_DFX_GLB_BASE + 0x6C4) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CFG_PORT01_REG (HI1822_CPI_DFX_GLB_BASE + 0x6C8) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CFG_PORT23_REG (HI1822_CPI_DFX_GLB_BASE + 0x6CC) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x6D0) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x6D4) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x6D8) +#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x6DC) + +#endif // CPI_DFX_GLB_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_reg_offset.h new file mode 100644 index 000000000..78829c792 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/cpi_reg_offset.h @@ -0,0 +1,4698 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : cpi_reg_offset.h +// Project line : IT产品线 +// Department : 图灵ICT处理器开发部 +// Author : xxx +// Version : V100 +// Date : +// Description : Hi 1823 is a throughput of 100Gbps CNA chip. It provide large bandwith, low latency, scalability +// converged network solution, support network convergency, virtualization, protocol offload, and serves IT product and +// CT product. Others : Generated automatically by nManager V5.1 History : xxx 2020/07/27 20:37:29 Create +// file +// ****************************************************************************** + +#ifndef CPI_REG_OFFSET_H +#define CPI_REG_OFFSET_H + +/* msi_cap_csr Base address of Module's Register */ +#define CSR_MSI_CAP_CSR_BASE (0x43F9000) + +/* **************************************************************************** */ +/* msi_cap_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MSI_CAP_CSR_MSI_CAP_CSR_DW0_0_REG (CSR_MSI_CAP_CSR_BASE + 0x0) +#define CSR_MSI_CAP_CSR_MSI_CAP_CSR_DW0_1_REG (CSR_MSI_CAP_CSR_BASE + 0x4) + +/* up_itf_csr Base address of Module's Register */ +#define CSR_UP_ITF_CSR_BASE (0x43AE000) + +/* **************************************************************************** */ +/* up_itf_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_UP_ITF_CSR_UP_PCIE_STATUS_REG (CSR_UP_ITF_CSR_BASE + 0x0) /* PCIe端口link实时状态。 */ +#define CSR_UP_ITF_CSR_UP_INT_STATUS_REG (CSR_UP_ITF_CSR_BASE + 0x4) /* 中断状态寄存器；写1清除对应比特中断。 */ +#define CSR_UP_ITF_CSR_UP_INT_CTL_REG (CSR_UP_ITF_CSR_BASE + 0x8) /* uP interrupt control */ +#define CSR_UP_ITF_CSR_UP_DIRECT_ACCESS_LOCK_REG (CSR_UP_ITF_CSR_BASE + 0xC) /* direct access lock */ +#define CSR_UP_ITF_CSR_UP_AEQ_LEN_REG (CSR_UP_ITF_CSR_BASE + 0x10) /* uP AEQ length and AEQE size */ +#define CSR_UP_ITF_CSR_UP_AEQ_BA_REG (CSR_UP_ITF_CSR_BASE + 0x14) /* uP AEQ ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_AEQ_CI_REG (CSR_UP_ITF_CSR_BASE + 0x18) /* uP AEQ ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_AEQ_PI_REG (CSR_UP_ITF_CSR_BASE + 0x1C) /* uP AEQ ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_RX_API_BUF_LEN_REG (CSR_UP_ITF_CSR_BASE + 0x20) /* uP API Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_RX_API_BUF_BA_REG (CSR_UP_ITF_CSR_BASE + 0x24) /* uP API Rx ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_RX_API_BUF_CI_REG (CSR_UP_ITF_CSR_BASE + 0x28) /* uP API Rx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_RX_API_BUF_PI_REG (CSR_UP_ITF_CSR_BASE + 0x2C) /* uP API Rx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TX_API_CTL_REG (CSR_UP_ITF_CSR_BASE + 0x30) /* uP API Tx control register */ +#define CSR_UP_ITF_CSR_UP_TX_API_CTL_VIO_REG (CSR_UP_ITF_CSR_BASE + 0x34) /* mpu tx api ctrl register for VirtIO/NVMe \ + */ +#define CSR_UP_ITF_CSR_UP_RB_TIMEOUT_REG (CSR_UP_ITF_CSR_BASE + 0x38) /* UP RINGBuffer申请时间约束。 */ +#define CSR_UP_ITF_CSR_UP_XFER_CTRL_REG (CSR_UP_ITF_CSR_BASE + 0x3C) /* UP AXI接口控制寄存器 */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_0_REG (CSR_UP_ITF_CSR_BASE + 0x40) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_1_REG (CSR_UP_ITF_CSR_BASE + 0x44) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_2_REG (CSR_UP_ITF_CSR_BASE + 0x48) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_3_REG (CSR_UP_ITF_CSR_BASE + 0x4C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_4_REG (CSR_UP_ITF_CSR_BASE + 0x50) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_5_REG (CSR_UP_ITF_CSR_BASE + 0x54) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_6_REG (CSR_UP_ITF_CSR_BASE + 0x58) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_7_REG (CSR_UP_ITF_CSR_BASE + 0x5C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_8_REG (CSR_UP_ITF_CSR_BASE + 0x60) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_9_REG (CSR_UP_ITF_CSR_BASE + 0x64) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_10_REG (CSR_UP_ITF_CSR_BASE + 0x68) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_11_REG (CSR_UP_ITF_CSR_BASE + 0x6C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_12_REG (CSR_UP_ITF_CSR_BASE + 0x70) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_13_REG (CSR_UP_ITF_CSR_BASE + 0x74) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_14_REG (CSR_UP_ITF_CSR_BASE + 0x78) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_15_REG (CSR_UP_ITF_CSR_BASE + 0x7C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_16_REG (CSR_UP_ITF_CSR_BASE + 0x80) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_17_REG (CSR_UP_ITF_CSR_BASE + 0x84) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_18_REG (CSR_UP_ITF_CSR_BASE + 0x88) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_19_REG (CSR_UP_ITF_CSR_BASE + 0x8C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_20_REG (CSR_UP_ITF_CSR_BASE + 0x90) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_21_REG (CSR_UP_ITF_CSR_BASE + 0x94) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_22_REG (CSR_UP_ITF_CSR_BASE + 0x98) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_23_REG (CSR_UP_ITF_CSR_BASE + 0x9C) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_24_REG (CSR_UP_ITF_CSR_BASE + 0xA0) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_25_REG (CSR_UP_ITF_CSR_BASE + 0xA4) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_26_REG (CSR_UP_ITF_CSR_BASE + 0xA8) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_27_REG (CSR_UP_ITF_CSR_BASE + 0xAC) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_28_REG (CSR_UP_ITF_CSR_BASE + 0xB0) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_29_REG (CSR_UP_ITF_CSR_BASE + 0xB4) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_30_REG (CSR_UP_ITF_CSR_BASE + 0xB8) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_TX_API_PAYLOAD_31_REG (CSR_UP_ITF_CSR_BASE + 0xBC) /* the payload data of the uP Tx API */ +#define CSR_UP_ITF_CSR_UP_INT_COLL_REG (CSR_UP_ITF_CSR_BASE + 0xC8) /* uP interrupt collection. */ +#define CSR_UP_ITF_CSR_UP_INT_TIMEOUT_REG (CSR_UP_ITF_CSR_BASE + 0xCC) /* uP interrupt collection timeout. */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_0_REG (CSR_UP_ITF_CSR_BASE + 0xD0) /* uP TLP Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_1_REG (CSR_UP_ITF_CSR_BASE + 0xF0) /* uP TLP Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_2_REG (CSR_UP_ITF_CSR_BASE + 0x110) /* uP TLP Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_LEN_3_REG (CSR_UP_ITF_CSR_BASE + 0x130) /* uP TLP Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_0_REG (CSR_UP_ITF_CSR_BASE + 0xD4) /* uP TLP ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_1_REG (CSR_UP_ITF_CSR_BASE + 0xF4) /* uP TLP ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_2_REG (CSR_UP_ITF_CSR_BASE + 0x114) /* uP TLP ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_BA_3_REG (CSR_UP_ITF_CSR_BASE + 0x134) /* uP TLP ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_0_REG (CSR_UP_ITF_CSR_BASE + 0xD8) /* uP TLP ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_1_REG (CSR_UP_ITF_CSR_BASE + 0xF8) /* uP TLP ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_2_REG (CSR_UP_ITF_CSR_BASE + 0x118) /* uP TLP ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_CI_3_REG (CSR_UP_ITF_CSR_BASE + 0x138) /* uP TLP ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_0_REG (CSR_UP_ITF_CSR_BASE + 0xDC) /* uP TLP ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_1_REG (CSR_UP_ITF_CSR_BASE + 0xFC) /* uP TLP ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_2_REG (CSR_UP_ITF_CSR_BASE + 0x11C) /* uP TLP ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_RX_PI_3_REG (CSR_UP_ITF_CSR_BASE + 0x13C) /* uP TLP ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_0_REG (CSR_UP_ITF_CSR_BASE + 0xE0) /* uP TLP Tx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_1_REG (CSR_UP_ITF_CSR_BASE + 0x100) /* uP TLP Tx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_2_REG (CSR_UP_ITF_CSR_BASE + 0x120) /* uP TLP Tx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_LEN_3_REG (CSR_UP_ITF_CSR_BASE + 0x140) /* uP TLP Tx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_0_REG (CSR_UP_ITF_CSR_BASE + 0xE4) /* uP TLP TX ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_1_REG (CSR_UP_ITF_CSR_BASE + 0x104) /* uP TLP TX ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_2_REG (CSR_UP_ITF_CSR_BASE + 0x124) /* uP TLP TX ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_BA_3_REG (CSR_UP_ITF_CSR_BASE + 0x144) /* uP TLP TX ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_0_REG (CSR_UP_ITF_CSR_BASE + 0xE8) /* uP TLP Tx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_1_REG (CSR_UP_ITF_CSR_BASE + 0x108) /* uP TLP Tx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_2_REG (CSR_UP_ITF_CSR_BASE + 0x128) /* uP TLP Tx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_CI_3_REG (CSR_UP_ITF_CSR_BASE + 0x148) /* uP TLP Tx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_0_REG (CSR_UP_ITF_CSR_BASE + 0xEC) /* uP TLP Tx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_1_REG (CSR_UP_ITF_CSR_BASE + 0x10C) /* uP TLP Tx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_2_REG (CSR_UP_ITF_CSR_BASE + 0x12C) /* uP TLP Tx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_TLP_TX_PI_3_REG (CSR_UP_ITF_CSR_BASE + 0x14C) /* uP TLP Tx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x150) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x170) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x190) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_LEN_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1B0) /* uP MCTP Rx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x154) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x174) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x194) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_BA_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1B4) /* uP MCTP Rx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x158) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x178) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x198) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_CI_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1B8) /* uP MCTP Rx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x15C) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x17C) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x19C) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPRX_PI_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1BC) /* uP MCTP Rx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x160) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x180) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1A0) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_LEN_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1C0) /* uP MCTP Tx ring buffer length for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x164) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x184) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1A4) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_BA_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1C4) /* uP MCTP Tx ring buffer base address for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x168) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x188) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1A8) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_CI_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1C8) /* uP MCTP Tx ring buffer CI for PCIe port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_0_REG \ + (CSR_UP_ITF_CSR_BASE + 0x16C) /* uP MCTP Tx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_1_REG \ + (CSR_UP_ITF_CSR_BASE + 0x18C) /* uP MCTP Tx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_2_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1AC) /* uP MCTP Tx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_MCTPTX_PI_3_REG \ + (CSR_UP_ITF_CSR_BASE + 0x1CC) /* uP MCTP Tx ring buffer PI for port[pcie_idx] */ +#define CSR_UP_ITF_CSR_UP_CSR_CTL_REG (CSR_UP_ITF_CSR_BASE + 0x200) /* UP访问系统CSR寄存器的控制寄存器 */ +#define CSR_UP_ITF_CSR_UP_CSR_DATA0_REG (CSR_UP_ITF_CSR_BASE + 0x204) /* UP访问CSR的数据寄存器0 */ +#define CSR_UP_ITF_CSR_UP_CSR_DATA1_REG (CSR_UP_ITF_CSR_BASE + 0x208) /* UP访问CSR的数据寄存器1 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_0_REG (CSR_UP_ITF_CSR_BASE + 0x300) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_1_REG (CSR_UP_ITF_CSR_BASE + 0x304) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_2_REG (CSR_UP_ITF_CSR_BASE + 0x308) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_3_REG (CSR_UP_ITF_CSR_BASE + 0x30C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_4_REG (CSR_UP_ITF_CSR_BASE + 0x310) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_5_REG (CSR_UP_ITF_CSR_BASE + 0x314) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_6_REG (CSR_UP_ITF_CSR_BASE + 0x318) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_7_REG (CSR_UP_ITF_CSR_BASE + 0x31C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_8_REG (CSR_UP_ITF_CSR_BASE + 0x320) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_9_REG (CSR_UP_ITF_CSR_BASE + 0x324) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_10_REG (CSR_UP_ITF_CSR_BASE + 0x328) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_11_REG (CSR_UP_ITF_CSR_BASE + 0x32C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_12_REG (CSR_UP_ITF_CSR_BASE + 0x330) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_13_REG (CSR_UP_ITF_CSR_BASE + 0x334) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_14_REG (CSR_UP_ITF_CSR_BASE + 0x338) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_15_REG (CSR_UP_ITF_CSR_BASE + 0x33C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_16_REG (CSR_UP_ITF_CSR_BASE + 0x340) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_17_REG (CSR_UP_ITF_CSR_BASE + 0x344) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_18_REG (CSR_UP_ITF_CSR_BASE + 0x348) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_19_REG (CSR_UP_ITF_CSR_BASE + 0x34C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_20_REG (CSR_UP_ITF_CSR_BASE + 0x350) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_21_REG (CSR_UP_ITF_CSR_BASE + 0x354) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_22_REG (CSR_UP_ITF_CSR_BASE + 0x358) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_23_REG (CSR_UP_ITF_CSR_BASE + 0x35C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_24_REG (CSR_UP_ITF_CSR_BASE + 0x360) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_25_REG (CSR_UP_ITF_CSR_BASE + 0x364) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_26_REG (CSR_UP_ITF_CSR_BASE + 0x368) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_27_REG (CSR_UP_ITF_CSR_BASE + 0x36C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_28_REG (CSR_UP_ITF_CSR_BASE + 0x370) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_29_REG (CSR_UP_ITF_CSR_BASE + 0x374) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_30_REG (CSR_UP_ITF_CSR_BASE + 0x378) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_31_REG (CSR_UP_ITF_CSR_BASE + 0x37C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_32_REG (CSR_UP_ITF_CSR_BASE + 0x380) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_33_REG (CSR_UP_ITF_CSR_BASE + 0x384) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_34_REG (CSR_UP_ITF_CSR_BASE + 0x388) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_35_REG (CSR_UP_ITF_CSR_BASE + 0x38C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_36_REG (CSR_UP_ITF_CSR_BASE + 0x390) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_37_REG (CSR_UP_ITF_CSR_BASE + 0x394) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_38_REG (CSR_UP_ITF_CSR_BASE + 0x398) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_39_REG (CSR_UP_ITF_CSR_BASE + 0x39C) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_40_REG (CSR_UP_ITF_CSR_BASE + 0x3A0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_41_REG (CSR_UP_ITF_CSR_BASE + 0x3A4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_42_REG (CSR_UP_ITF_CSR_BASE + 0x3A8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_43_REG (CSR_UP_ITF_CSR_BASE + 0x3AC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_44_REG (CSR_UP_ITF_CSR_BASE + 0x3B0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_45_REG (CSR_UP_ITF_CSR_BASE + 0x3B4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_46_REG (CSR_UP_ITF_CSR_BASE + 0x3B8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_47_REG (CSR_UP_ITF_CSR_BASE + 0x3BC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_48_REG (CSR_UP_ITF_CSR_BASE + 0x3C0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_49_REG (CSR_UP_ITF_CSR_BASE + 0x3C4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_50_REG (CSR_UP_ITF_CSR_BASE + 0x3C8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_51_REG (CSR_UP_ITF_CSR_BASE + 0x3CC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_52_REG (CSR_UP_ITF_CSR_BASE + 0x3D0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_53_REG (CSR_UP_ITF_CSR_BASE + 0x3D4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_54_REG (CSR_UP_ITF_CSR_BASE + 0x3D8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_55_REG (CSR_UP_ITF_CSR_BASE + 0x3DC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_56_REG (CSR_UP_ITF_CSR_BASE + 0x3E0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_57_REG (CSR_UP_ITF_CSR_BASE + 0x3E4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_58_REG (CSR_UP_ITF_CSR_BASE + 0x3E8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_59_REG (CSR_UP_ITF_CSR_BASE + 0x3EC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_60_REG (CSR_UP_ITF_CSR_BASE + 0x3F0) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_61_REG (CSR_UP_ITF_CSR_BASE + 0x3F4) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_62_REG (CSR_UP_ITF_CSR_BASE + 0x3F8) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_API_RDAT_63_REG (CSR_UP_ITF_CSR_BASE + 0x3FC) /* UP API Load访问的读数据 */ +#define CSR_UP_ITF_CSR_UP_MEM_CTRL_REG (CSR_UP_ITF_CSR_BASE + 0x400) /* 接口Memory属性配置寄存器。保持为默认值。 */ +#define CSR_UP_ITF_CSR_UP_RB_DBGCTL_REG (CSR_UP_ITF_CSR_BASE + 0x404) /* UP RingBuffer Debug控制寄存器 */ +#define CSR_UP_ITF_CSR_UP_RB_DBGDAT0_REG (CSR_UP_ITF_CSR_BASE + 0x408) /* RingBuffer指针状态。 */ +#define CSR_UP_ITF_CSR_UP_RB_DBGDAT1_REG (CSR_UP_ITF_CSR_BASE + 0x40C) /* RingBuffer数据个数状态。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG0_REG (CSR_UP_ITF_CSR_BASE + 0x410) /* 内部状态0。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG1_REG (CSR_UP_ITF_CSR_BASE + 0x414) /* 内部状态1。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG2_REG (CSR_UP_ITF_CSR_BASE + 0x418) /* 内部状态2。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG3_0_REG (CSR_UP_ITF_CSR_BASE + 0x420) /* 内部状态3。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG3_1_REG (CSR_UP_ITF_CSR_BASE + 0x424) /* 内部状态3。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG3_2_REG (CSR_UP_ITF_CSR_BASE + 0x428) /* 内部状态3。 */ +#define CSR_UP_ITF_CSR_UP_FSM_DBG3_3_REG (CSR_UP_ITF_CSR_BASE + 0x42C) /* 内部状态3。 */ +#define CSR_UP_ITF_CSR_UP_MEM_DBG0_REG (CSR_UP_ITF_CSR_BASE + 0x430) /* Memory错误注入寄存器 */ +#define CSR_UP_ITF_CSR_UP_MEM_DBG1_REG (CSR_UP_ITF_CSR_BASE + 0x434) /* MEM错误状态寄存器1 */ +#define CSR_UP_ITF_CSR_UP_MEM_DBG2_REG (CSR_UP_ITF_CSR_BASE + 0x438) /* MEM错误状态寄存器2 */ +#define CSR_UP_ITF_CSR_UP_MEM_DBG3_REG (CSR_UP_ITF_CSR_BASE + 0x43C) /* MEM错误状态寄存器3 */ +#define CSR_UP_ITF_CSR_UP_DBG_ST0_REG (CSR_UP_ITF_CSR_BASE + 0x440) /* DFX状态寄存器0 */ +#define CSR_UP_ITF_CSR_UP_DBG_ST1_REG (CSR_UP_ITF_CSR_BASE + 0x444) /* DFX状态寄存器1 */ +#define CSR_UP_ITF_CSR_UP_DBG_ST2_REG (CSR_UP_ITF_CSR_BASE + 0x448) /* DFX状态寄存器2 */ +#define CSR_UP_ITF_CSR_UP_DBG_ST3_REG (CSR_UP_ITF_CSR_BASE + 0x44C) /* DFX状态寄存器3 */ +#define CSR_UP_ITF_CSR_UP_MEM_DBG4_REG (CSR_UP_ITF_CSR_BASE + 0x450) /* MEM错误状态寄存器4 */ +#define CSR_UP_ITF_CSR_UP_DBG_CNT0_REG (CSR_UP_ITF_CSR_BASE + 0x460) /* DFX统计寄存器0 */ +#define CSR_UP_ITF_CSR_UP_DBG_CNT1_REG (CSR_UP_ITF_CSR_BASE + 0x464) +#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_LEN_REG (CSR_UP_ITF_CSR_BASE + 0x470) /* uP MB Rx ring buffer length */ +#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_BA_REG (CSR_UP_ITF_CSR_BASE + 0x474) /* uP MB Rx ring buffer base address */ +#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_CI_REG (CSR_UP_ITF_CSR_BASE + 0x478) /* uP MB Rx ring buffer CI */ +#define CSR_UP_ITF_CSR_UP_RX_MB_BUF_PI_REG (CSR_UP_ITF_CSR_BASE + 0x47C) /* uP MB Rx ring buffer PI */ +#define CSR_UP_ITF_CSR_UP_BAR_MAP_REG (CSR_UP_ITF_CSR_BASE + 0x480) /* CPI BAR空间映射 */ +#define CSR_UP_ITF_CSR_UP_ACC_FUNC_IDX_REG (CSR_UP_ITF_CSR_BASE + 0x484) +#define CSR_UP_ITF_CSR_UP_INT_STATUS2_REG (CSR_UP_ITF_CSR_BASE + 0x490) /* 中断状态寄存器；写1清除对应比特中断。 */ +#define CSR_UP_ITF_CSR_UP_INT_CTL2_REG (CSR_UP_ITF_CSR_BASE + 0x494) /* uP interrupt control */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_OTD_TH_REG (CSR_UP_ITF_CSR_BASE + 0x4A0) /* 并发度门限 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_OTD_CNT_REG (CSR_UP_ITF_CSR_BASE + 0x4A4) /* 并发数统计 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_OTD_REC_REG (CSR_UP_ITF_CSR_BASE + 0x4A8) /* 并发数恢复 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD0_REG (CSR_UP_ITF_CSR_BASE + 0x4B0) /* 丢弃情况记录 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD1_REG (CSR_UP_ITF_CSR_BASE + 0x4B4) /* 丢弃情况记录 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD2_REG (CSR_UP_ITF_CSR_BASE + 0x4B8) /* 丢弃情况记录 */ +#define CSR_UP_ITF_CSR_UP_VIOAEQ_DROP_RCD3_REG (CSR_UP_ITF_CSR_BASE + 0x4BC) /* 丢弃情况记录 */ +#define CSR_UP_ITF_CSR_UP_UNCRT_ERR_DIS_REG (CSR_UP_ITF_CSR_BASE + 0x4C0) + +/* func_com_csr Base address of Module's Register */ +#define CSR_FUNC_COM_CSR_BASE (0x4000000) + +/* **************************************************************************** */ +/* func_com_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE0_0_REG (CSR_FUNC_COM_CSR_BASE + 0x0) /* Function attribute0 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE0_1_REG (CSR_FUNC_COM_CSR_BASE + 0x80) /* Function attribute0 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE1_0_REG (CSR_FUNC_COM_CSR_BASE + 0x4) /* Function attribute1 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE1_1_REG (CSR_FUNC_COM_CSR_BASE + 0x84) /* Function attribute1 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE2_0_REG (CSR_FUNC_COM_CSR_BASE + 0x8) /* function attribute2 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE2_1_REG (CSR_FUNC_COM_CSR_BASE + 0x88) /* function attribute2 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE3_0_REG (CSR_FUNC_COM_CSR_BASE + 0xC) /* Function attribute3 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE3_1_REG (CSR_FUNC_COM_CSR_BASE + 0x8C) /* Function attribute3 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE4_0_REG (CSR_FUNC_COM_CSR_BASE + 0x10) /* Function attribute4 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE4_1_REG (CSR_FUNC_COM_CSR_BASE + 0x90) /* Function attribute4 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE5_0_REG (CSR_FUNC_COM_CSR_BASE + 0x14) /* Function attribute5 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE5_1_REG (CSR_FUNC_COM_CSR_BASE + 0x94) /* Function attribute5 */ +#define CSR_FUNC_COM_CSR_FUNCTION_ATTRIBUTE6_0_REG (CSR_FUNC_COM_CSR_BASE + 0x18) /* Function attribute6 */ + +#define CSR_FUNC_COM_CSR_FUNCTION_TSK0_0_REG (CSR_FUNC_COM_CSR_BASE + 0x20) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_0_REG (CSR_FUNC_COM_CSR_BASE + 0x24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_1_REG (CSR_FUNC_COM_CSR_BASE + 0xA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_2_REG (CSR_FUNC_COM_CSR_BASE + 0x124) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_3_REG (CSR_FUNC_COM_CSR_BASE + 0x1A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_4_REG (CSR_FUNC_COM_CSR_BASE + 0x224) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_5_REG (CSR_FUNC_COM_CSR_BASE + 0x2A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_6_REG (CSR_FUNC_COM_CSR_BASE + 0x324) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_7_REG (CSR_FUNC_COM_CSR_BASE + 0x3A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_8_REG (CSR_FUNC_COM_CSR_BASE + 0x424) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_9_REG (CSR_FUNC_COM_CSR_BASE + 0x4A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_10_REG (CSR_FUNC_COM_CSR_BASE + 0x524) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_11_REG (CSR_FUNC_COM_CSR_BASE + 0x5A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_12_REG (CSR_FUNC_COM_CSR_BASE + 0x624) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_13_REG (CSR_FUNC_COM_CSR_BASE + 0x6A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_14_REG (CSR_FUNC_COM_CSR_BASE + 0x724) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_15_REG (CSR_FUNC_COM_CSR_BASE + 0x7A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_16_REG (CSR_FUNC_COM_CSR_BASE + 0x824) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_17_REG (CSR_FUNC_COM_CSR_BASE + 0x8A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_18_REG (CSR_FUNC_COM_CSR_BASE + 0x924) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_19_REG (CSR_FUNC_COM_CSR_BASE + 0x9A4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_20_REG (CSR_FUNC_COM_CSR_BASE + 0xA24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_21_REG (CSR_FUNC_COM_CSR_BASE + 0xAA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_22_REG (CSR_FUNC_COM_CSR_BASE + 0xB24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_23_REG (CSR_FUNC_COM_CSR_BASE + 0xBA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_24_REG (CSR_FUNC_COM_CSR_BASE + 0xC24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_25_REG (CSR_FUNC_COM_CSR_BASE + 0xCA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_26_REG (CSR_FUNC_COM_CSR_BASE + 0xD24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_27_REG (CSR_FUNC_COM_CSR_BASE + 0xDA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_28_REG (CSR_FUNC_COM_CSR_BASE + 0xE24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_29_REG (CSR_FUNC_COM_CSR_BASE + 0xEA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_30_REG (CSR_FUNC_COM_CSR_BASE + 0xF24) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK1_31_REG (CSR_FUNC_COM_CSR_BASE + 0xFA4) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_0_REG (CSR_FUNC_COM_CSR_BASE + 0x28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_1_REG (CSR_FUNC_COM_CSR_BASE + 0xA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_2_REG (CSR_FUNC_COM_CSR_BASE + 0x128) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_3_REG (CSR_FUNC_COM_CSR_BASE + 0x1A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_4_REG (CSR_FUNC_COM_CSR_BASE + 0x228) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_5_REG (CSR_FUNC_COM_CSR_BASE + 0x2A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_6_REG (CSR_FUNC_COM_CSR_BASE + 0x328) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_7_REG (CSR_FUNC_COM_CSR_BASE + 0x3A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_8_REG (CSR_FUNC_COM_CSR_BASE + 0x428) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_9_REG (CSR_FUNC_COM_CSR_BASE + 0x4A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_10_REG (CSR_FUNC_COM_CSR_BASE + 0x528) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_11_REG (CSR_FUNC_COM_CSR_BASE + 0x5A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_12_REG (CSR_FUNC_COM_CSR_BASE + 0x628) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_13_REG (CSR_FUNC_COM_CSR_BASE + 0x6A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_14_REG (CSR_FUNC_COM_CSR_BASE + 0x728) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_15_REG (CSR_FUNC_COM_CSR_BASE + 0x7A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_16_REG (CSR_FUNC_COM_CSR_BASE + 0x828) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_17_REG (CSR_FUNC_COM_CSR_BASE + 0x8A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_18_REG (CSR_FUNC_COM_CSR_BASE + 0x928) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_19_REG (CSR_FUNC_COM_CSR_BASE + 0x9A8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_20_REG (CSR_FUNC_COM_CSR_BASE + 0xA28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_21_REG (CSR_FUNC_COM_CSR_BASE + 0xAA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_22_REG (CSR_FUNC_COM_CSR_BASE + 0xB28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_23_REG (CSR_FUNC_COM_CSR_BASE + 0xBA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_24_REG (CSR_FUNC_COM_CSR_BASE + 0xC28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_25_REG (CSR_FUNC_COM_CSR_BASE + 0xCA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_26_REG (CSR_FUNC_COM_CSR_BASE + 0xD28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_27_REG (CSR_FUNC_COM_CSR_BASE + 0xDA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_28_REG (CSR_FUNC_COM_CSR_BASE + 0xE28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_29_REG (CSR_FUNC_COM_CSR_BASE + 0xEA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_30_REG (CSR_FUNC_COM_CSR_BASE + 0xF28) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK2_31_REG (CSR_FUNC_COM_CSR_BASE + 0xFA8) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_0_REG (CSR_FUNC_COM_CSR_BASE + 0x2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_1_REG (CSR_FUNC_COM_CSR_BASE + 0xAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_2_REG (CSR_FUNC_COM_CSR_BASE + 0x12C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_3_REG (CSR_FUNC_COM_CSR_BASE + 0x1AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_4_REG (CSR_FUNC_COM_CSR_BASE + 0x22C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_5_REG (CSR_FUNC_COM_CSR_BASE + 0x2AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_6_REG (CSR_FUNC_COM_CSR_BASE + 0x32C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_7_REG (CSR_FUNC_COM_CSR_BASE + 0x3AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_8_REG (CSR_FUNC_COM_CSR_BASE + 0x42C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_9_REG (CSR_FUNC_COM_CSR_BASE + 0x4AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_10_REG (CSR_FUNC_COM_CSR_BASE + 0x52C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_11_REG (CSR_FUNC_COM_CSR_BASE + 0x5AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_12_REG (CSR_FUNC_COM_CSR_BASE + 0x62C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_13_REG (CSR_FUNC_COM_CSR_BASE + 0x6AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_14_REG (CSR_FUNC_COM_CSR_BASE + 0x72C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_15_REG (CSR_FUNC_COM_CSR_BASE + 0x7AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_16_REG (CSR_FUNC_COM_CSR_BASE + 0x82C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_17_REG (CSR_FUNC_COM_CSR_BASE + 0x8AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_18_REG (CSR_FUNC_COM_CSR_BASE + 0x92C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_19_REG (CSR_FUNC_COM_CSR_BASE + 0x9AC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_20_REG (CSR_FUNC_COM_CSR_BASE + 0xA2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_21_REG (CSR_FUNC_COM_CSR_BASE + 0xAAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_22_REG (CSR_FUNC_COM_CSR_BASE + 0xB2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_23_REG (CSR_FUNC_COM_CSR_BASE + 0xBAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_24_REG (CSR_FUNC_COM_CSR_BASE + 0xC2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_25_REG (CSR_FUNC_COM_CSR_BASE + 0xCAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_26_REG (CSR_FUNC_COM_CSR_BASE + 0xD2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_27_REG (CSR_FUNC_COM_CSR_BASE + 0xDAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_28_REG (CSR_FUNC_COM_CSR_BASE + 0xE2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_29_REG (CSR_FUNC_COM_CSR_BASE + 0xEAC) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_30_REG (CSR_FUNC_COM_CSR_BASE + 0xF2C) +#define CSR_FUNC_COM_CSR_FUNCTION_TSK3_31_REG (CSR_FUNC_COM_CSR_BASE + 0xFAC) +#define CSR_FUNC_COM_CSR_FUNC_REMAP_TABLE_ENTR_0_REG (CSR_FUNC_COM_CSR_BASE + 0x30) /* function remap table entry */ +#define CSR_FUNC_COM_CSR_FUNC_REMAP_TABLE_ENTR_1_REG (CSR_FUNC_COM_CSR_BASE + 0xB0) /* function remap table entry */ +#define CSR_FUNC_COM_CSR_FUNC_AEQ_CI_INDIR_WR_REG \ + (CSR_FUNC_COM_CSR_BASE + 0x50) /* AEQ CI simple indirect access path */ +#define CSR_FUNC_COM_CSR_FUNC_CEQ_CI_INDIR_WR_REG \ + (CSR_FUNC_COM_CSR_BASE + 0x54) /* CEQ CI simple indirect access path */ +#define CSR_FUNC_COM_CSR_FUNC_MSI_CLR_INDIR_WR_REG \ + (CSR_FUNC_COM_CSR_BASE + 0x58) /* MSI_CTL CLR simple indirect access path */ +#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT0_REG (CSR_FUNC_COM_CSR_BASE + 0x60) /* ppf election results in port0 */ +#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT1_REG (CSR_FUNC_COM_CSR_BASE + 0x64) /* ppf election results in port1 */ +#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT2_REG (CSR_FUNC_COM_CSR_BASE + 0x68) /* ppf election results in port2 */ +#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT3_REG (CSR_FUNC_COM_CSR_BASE + 0x6C) /* ppf election results in port3 */ +#define CSR_FUNC_COM_CSR_FUNC_PPF_ELECT_PORT4_REG (CSR_FUNC_COM_CSR_BASE + 0x70) /* ppf election results in port4 */ + +/* func_mb_dat_csr Base address of Module's Register */ +#define CSR_FUNC_MB_DAT_CSR_BASE (0x4080000) + +/* **************************************************************************** */ +/* func_mb_dat_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_0_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x0) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_0_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x80) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_1_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x4) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_1_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x84) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_2_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x8) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_2_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x88) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_3_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xC) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_3_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x8C) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_4_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x10) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_4_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x90) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_5_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x14) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_5_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x94) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_6_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x18) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_6_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x98) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_7_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x1C) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_7_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x9C) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_8_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x20) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_8_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xA0) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_9_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x24) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_9_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xA4) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_10_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x28) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_10_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xA8) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_11_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x2C) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_11_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xAC) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_12_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x30) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_12_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xB0) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_13_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x34) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_13_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xB4) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_14_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x38) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_14_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xB8) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_15_0_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0x3C) /* mailbox data */ +#define CSR_FUNC_MB_DAT_CSR_MAILBOX_DAT_15_1_REG (CSR_FUNC_MB_DAT_CSR_BASE + 0xBC) /* mailbox data */ + +/* func_mb_csr Base address of Module's Register */ +#define CSR_FUNC_MB_CSR_BASE (0x4100000) + +/* **************************************************************************** */ +/* func_mb_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_MB_CSR_MAILBOX_CONTROL_0_REG (CSR_FUNC_MB_CSR_BASE + 0x0) /* Maibox control */ +#define CSR_FUNC_MB_CSR_MAILBOX_CONTROL_1_REG (CSR_FUNC_MB_CSR_BASE + 0x80) /* Maibox control */ +#define CSR_FUNC_MB_CSR_MAILBOX_INT_OFFSET_0_REG (CSR_FUNC_MB_CSR_BASE + 0x4) /* Mailbox interrupt offset */ +#define CSR_FUNC_MB_CSR_MAILBOX_INT_OFFSET_1_REG (CSR_FUNC_MB_CSR_BASE + 0x84) /* Mailbox interrupt offset */ +#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_H_0_REG \ + (CSR_FUNC_MB_CSR_BASE + 0x8) /* Maibox data sending result back address high 32 bits */ +#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_H_1_REG \ + (CSR_FUNC_MB_CSR_BASE + 0x88) /* Maibox data sending result back address high 32 bits */ +#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_L_0_REG \ + (CSR_FUNC_MB_CSR_BASE + 0xC) /* Maibox data sending result back address low 32 bits */ +#define CSR_FUNC_MB_CSR_MAILBOX_RESULT_BACK_L_1_REG \ + (CSR_FUNC_MB_CSR_BASE + 0x8C) /* Maibox data sending result back address low 32 bits */ + +/* func_aeq_csr Base address of Module's Register */ +#define CSR_FUNC_AEQ_CSR_BASE (0x4181000) + +/* **************************************************************************** */ +/* func_aeq_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_AEQ_CSR_AEQ_CTL_0_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x0) /* Each PF use offset = 0x200 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2200. */ +#define CSR_FUNC_AEQ_CSR_AEQ_CTL_0_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x80) /* Each PF use offset = 0x200 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2200. */ +#define CSR_FUNC_AEQ_CSR_AEQ_CTL_1_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x4) /* Each PF use offset = 0x204 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2204. */ +#define CSR_FUNC_AEQ_CSR_AEQ_CTL_1_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x84) /* Each PF use offset = 0x204 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2204. */ +#define CSR_FUNC_AEQ_CSR_AEQ_CI_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x8) /* Each PF use offset = 0x208 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2208. */ +#define CSR_FUNC_AEQ_CSR_AEQ_CI_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x88) /* Each PF use offset = 0x208 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2208. */ +#define CSR_FUNC_AEQ_CSR_AEQ_PI_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xC) /* Each PF use offset = 0x20C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x220C. */ +#define CSR_FUNC_AEQ_CSR_AEQ_PI_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x8C) /* Each PF use offset = 0x20C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x220C. */ +#define CSR_FUNC_AEQ_CSR_AEQ_INDIR_IDX_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + \ + 0x10) /* Each PF use offset = 0x210 to access this csr. VF offset = 0x2210.MPU cann't access this CSR. */ +#define CSR_FUNC_AEQ_CSR_AEQ_INDIR_IDX_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + \ + 0x90) /* Each PF use offset = 0x210 to access this csr. VF offset = 0x2210.MPU cann't access this CSR. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_H_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x40) /* Each PF use offset = 0x240 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2240. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_H_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xC0) /* Each PF use offset = 0x240 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2240. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_L_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x44) /* Each PF use offset = 0x244 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2244. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT0_L_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xC4) /* Each PF use offset = 0x244 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2244. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_H_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x48) /* Each PF use offset = 0x248 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2248. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_H_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xC8) /* Each PF use offset = 0x248 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2248. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_L_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x4C) /* Each PF use offset = 0x24C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x224C. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT1_L_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xCC) /* Each PF use offset = 0x24C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x224C. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_H_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x50) /* Each PF use offset = 0x250 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2250. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_H_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xD0) /* Each PF use offset = 0x250 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2250. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_L_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x54) /* Each PF use offset = 0x254 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2254. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT2_L_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xD4) /* Each PF use offset = 0x254 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2254. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_H_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x58) /* Each PF use offset = 0x258 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2258. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_H_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xD8) /* Each PF use offset = 0x258 to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x2258. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_L_0_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0x5C) /* Each PF use offset = 0x25C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x225C. */ +#define CSR_FUNC_AEQ_CSR_FUNCTION_AEQ_MTT3_L_1_REG \ + (CSR_FUNC_AEQ_CSR_BASE + 0xDC) /* Each PF use offset = 0x25C to access this csr after correct configuration of \ + AEQ_INDIR_IDX.VF offset = 0x225C. */ + +/* func_ceq_csr Base address of Module's Register */ +#define CSR_FUNC_CEQ_CSR_BASE (0x4281000) + +/* **************************************************************************** */ +/* func_ceq_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_CEQ_CSR_CEQ_CTL_0_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x0) /* Each PF use offset = 0x280 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2280. */ +#define CSR_FUNC_CEQ_CSR_CEQ_CTL_0_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x80) /* Each PF use offset = 0x280 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2280. */ +#define CSR_FUNC_CEQ_CSR_CEQ_CTL_1_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x4) /* Each PF use offset = 0x284 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2284. */ +#define CSR_FUNC_CEQ_CSR_CEQ_CTL_1_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x84) /* Each PF use offset = 0x284 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2284. */ +#define CSR_FUNC_CEQ_CSR_CEQ_CI_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x8) /* Each PF use offset = 0x288 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2288. */ +#define CSR_FUNC_CEQ_CSR_CEQ_CI_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x88) /* Each PF use offset = 0x288 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x2288. */ +#define CSR_FUNC_CEQ_CSR_CEQ_PI_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xC) /* Each PF use offset = 0x28C to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x228C. */ +#define CSR_FUNC_CEQ_CSR_CEQ_PI_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x8C) /* Each PF use offset = 0x28C to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x228C. */ +#define CSR_FUNC_CEQ_CSR_CEQ_INDIR_IDX_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + \ + 0x10) /* Each PF use offset = 0x290 to access this csr. VF offset = 0x2290.MPU can't access this CSR. */ +#define CSR_FUNC_CEQ_CSR_CEQ_INDIR_IDX_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + \ + 0x90) /* Each PF use offset = 0x290 to access this csr. VF offset = 0x2290.MPU can't access this CSR. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x40) /* Each PF use offset = 0x2C0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xC0) /* Each PF use offset = 0x2C0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x44) /* Each PF use offset = 0x2C4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT0_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xC4) /* Each PF use offset = 0x2C4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x48) /* Each PF use offset = 0x2C8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xC8) /* Each PF use offset = 0x2C8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22C8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x4C) /* Each PF use offset = 0x2CC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22CC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT1_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xCC) /* Each PF use offset = 0x2CC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22CC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x50) /* Each PF use offset = 0x2D0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xD0) /* Each PF use offset = 0x2D0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x54) /* Each PF use offset = 0x2D4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT2_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xD4) /* Each PF use offset = 0x2D4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x58) /* Each PF use offset = 0x2D8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xD8) /* Each PF use offset = 0x2D8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22D8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x5C) /* Each PF use offset = 0x2DC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22DC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT3_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xDC) /* Each PF use offset = 0x2DC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22DC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x60) /* Each PF use offset = 0x2E0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xE0) /* Each PF use offset = 0x2E0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x64) /* Each PF use offset = 0x2E4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT4_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xE4) /* Each PF use offset = 0x2E4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x68) /* Each PF use offset = 0x2E8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xE8) /* Each PF use offset = 0x2E8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22E8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x6C) /* Each PF use offset = 0x2EC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22EC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT5_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xEC) /* Each PF use offset = 0x2EC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22EC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x70) /* Each PF use offset = 0x2F0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xF0) /* Each PF use offset = 0x2F0 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F0. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x74) /* Each PF use offset = 0x2F4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT6_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xF4) /* Each PF use offset = 0x2F4 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F4. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_H_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x78) /* Each PF use offset = 0x2F8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_H_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xF8) /* Each PF use offset = 0x2F8 to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22F8. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_L_0_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0x7C) /* Each PF use offset = 0x2FC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22FC. */ +#define CSR_FUNC_CEQ_CSR_FUNCTION_CEQ_MTT7_L_1_REG \ + (CSR_FUNC_CEQ_CSR_BASE + 0xFC) /* Each PF use offset = 0x2FC to access this csr after correct configuration of \ + CEQ_INDIR_IDX.VF offset = 0x22FC. */ + +/* func_int_csr Base address of Module's Register */ +#define CSR_FUNC_INT_CSR_BASE (0x4301000) + +/* **************************************************************************** */ +/* func_int_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_0_0_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x0) /* Each PF use offset = 0x300 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2300. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_0_1_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x20) /* Each PF use offset = 0x300 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2300. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_1_0_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x4) /* Each PF use offset = 0x304 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2304. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_1_1_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x24) /* Each PF use offset = 0x304 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2304. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_2_0_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x8) /* Each PF use offset = 0x308 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2308. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_2_1_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x28) /* Each PF use offset = 0x308 to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x2308. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_3_0_REG \ + (CSR_FUNC_INT_CSR_BASE + 0xC) /* Each PF use offset = 0x30C to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x230C. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_3_1_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x2C) /* Each PF use offset = 0x30C to access this csr after correct configuration of \ + MSI_CONTROL_INDIR_IDX. VF offset = 0x230C. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_INDIR_IDX_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0x10) /* Each PF use offset = 0x310 to access this csr. VF offset = 0x2310.MPU can't access this CSR. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_4_0_REG (CSR_FUNC_INT_CSR_BASE + 0x14) /* It is only access by MPU. */ +#define CSR_FUNC_INT_CSR_MSI_CONTROL_CSR_4_1_REG (CSR_FUNC_INT_CSR_BASE + 0x34) /* It is only access by MPU. */ +#define CSR_FUNC_INT_CSR_FUNCTION_DMA_ATTR_ENTR_0_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x80000) /* Each PF use offset = 0x380 to access this csr after correct configuration of \ + DMA_ATTR_INDIR_IDX.VF offset = 0x2380. */ +#define CSR_FUNC_INT_CSR_FUNCTION_DMA_ATTR_ENTR_1_REG \ + (CSR_FUNC_INT_CSR_BASE + 0x80004) /* Each PF use offset = 0x380 to access this csr after correct configuration of \ + DMA_ATTR_INDIR_IDX.VF offset = 0x2380. */ +#define CSR_FUNC_INT_CSR_DMA_ATTR_INDIR_IDX_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0x10) /* Each PF use offset = 0x390 to access this csr. VF offset = 0x2390.MPU can't access this CSR. */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0000) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0080) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0100) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0180) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0200) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0280) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0300) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0380) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0400) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0480) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0500) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0580) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0600) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0680) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0700) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0780) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0800) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0880) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0900) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0980) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F00) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK0_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F80) /* PF's virutal INTx mask bit (each PF will use offset=0x0000 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0004) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0084) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0104) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0184) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0204) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0284) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0304) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0384) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0404) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0484) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0504) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0584) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0604) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0684) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0704) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0784) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0804) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0884) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0904) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0984) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F04) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK1_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F84) /* PF's virutal INTx mask bit (each PF will use offset=0x0004 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0008) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0088) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0108) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0188) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0208) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0288) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0308) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0388) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0408) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0488) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0508) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0588) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0608) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0688) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0708) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0788) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0808) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0888) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0908) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0988) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F08) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK2_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F88) /* PF's virutal INTx mask bit (each PF will use offset=0x0008 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA000C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA008C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA010C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA018C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA020C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA028C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA030C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA038C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA040C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA048C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA050C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA058C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA060C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA068C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA070C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA078C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA080C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA088C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA090C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA098C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F0C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_MASK3_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F8C) /* PF's virutal INTx mask bit (each PF will use offset=0x000C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0010) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0090) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0110) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0190) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0210) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0290) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0310) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0390) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0410) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0490) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0510) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0590) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0610) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0690) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0710) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0790) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0810) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0890) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0910) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0990) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F10) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS0_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F90) /* PF's virutal INTx status bit (each PF will use offset=0x0010 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0014) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0094) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0114) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0194) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0214) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0294) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0314) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0394) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0414) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0494) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0514) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0594) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0614) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0694) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0714) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0794) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0814) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0894) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0914) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0994) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F14) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS1_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F94) /* PF's virutal INTx status bit (each PF will use offset=0x0014 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0018) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0098) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0118) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0198) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0218) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0298) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0318) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0398) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0418) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0498) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0518) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0598) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0618) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0698) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0718) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0798) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0818) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0898) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0918) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0998) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F18) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS2_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F98) /* PF's virutal INTx status bit (each PF will use offset=0x0018 to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_0_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA001C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_1_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA009C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_2_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA011C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_3_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA019C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_4_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA021C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_5_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA029C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_6_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA031C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_7_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA039C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_8_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA041C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_9_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA049C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_10_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA051C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_11_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA059C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_12_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA061C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_13_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA069C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_14_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA071C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_15_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA079C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_16_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA081C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_17_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA089C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_18_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA091C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_19_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA099C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_20_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_21_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0A9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_22_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_23_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0B9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_24_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_25_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0C9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_26_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_27_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0D9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_28_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_29_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0E9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_30_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F1C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ +#define CSR_FUNC_INT_CSR_PF_INTX_STATUS3_31_REG \ + (CSR_FUNC_INT_CSR_BASE + \ + 0xA0F9C) /* PF's virutal INTx status bit (each PF will use offset=0x001C to access this CSR) */ + +/* host_csr Base address of Module's Register */ +#define CSR_HOST_CSR_BASE (0x43AC000) + +/* **************************************************************************** */ +/* host_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HOST_CSR_PPF_ELECTION_0_REG \ + (CSR_HOST_CSR_BASE + \ + 0x0) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_PPF_ELECTION_1_REG \ + (CSR_HOST_CSR_BASE + \ + 0x4) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_PPF_ELECTION_2_REG \ + (CSR_HOST_CSR_BASE + \ + 0x8) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_PPF_ELECTION_3_REG \ + (CSR_HOST_CSR_BASE + \ + 0xC) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_PPF_ELECTION_4_REG \ + (CSR_HOST_CSR_BASE + \ + 0x10) /* PPF election.(each PF will use offset=0x000 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_MPF_ELECTION_REG \ + (CSR_HOST_CSR_BASE + \ + 0x20) /* MPF election.(each PF will use offset=0x020 to access this CSR)此地址不受直接访问权限控制。 */ +#define CSR_HOST_CSR_UCPU_CLP_SIZE_0_REG \ + (CSR_HOST_CSR_BASE + 0x40) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_SIZE_1_REG \ + (CSR_HOST_CSR_BASE + 0x60) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_SIZE_2_REG \ + (CSR_HOST_CSR_BASE + 0x80) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_SIZE_3_REG \ + (CSR_HOST_CSR_BASE + 0xA0) /* CLP传输的缓存大小配置寄存器。 (each PF will use offset=0x040 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQBASE_0_REG \ + (CSR_HOST_CSR_BASE + 0x44) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQBASE_1_REG \ + (CSR_HOST_CSR_BASE + 0x64) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQBASE_2_REG \ + (CSR_HOST_CSR_BASE + 0x84) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQBASE_3_REG \ + (CSR_HOST_CSR_BASE + 0xA4) /* CLP请求缓存的基地址。 (each PF will use offset=0x044 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_0_REG \ + (CSR_HOST_CSR_BASE + 0x48) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_1_REG \ + (CSR_HOST_CSR_BASE + 0x68) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_2_REG \ + (CSR_HOST_CSR_BASE + 0x88) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSPBASE_3_REG \ + (CSR_HOST_CSR_BASE + 0xA8) /* CLP响应缓存的基地址。 (each PF will use offset=0x048 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQ_0_REG \ + (CSR_HOST_CSR_BASE + 0x4C) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQ_1_REG \ + (CSR_HOST_CSR_BASE + 0x6C) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQ_2_REG \ + (CSR_HOST_CSR_BASE + 0x8C) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_REQ_3_REG \ + (CSR_HOST_CSR_BASE + 0xAC) /* CLP命令请求寄存器。 (each PF will use offset=0x04C to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSP_0_REG \ + (CSR_HOST_CSR_BASE + 0x50) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSP_1_REG \ + (CSR_HOST_CSR_BASE + 0x70) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSP_2_REG \ + (CSR_HOST_CSR_BASE + 0x90) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */ +#define CSR_HOST_CSR_UCPU_CLP_RSP_3_REG \ + (CSR_HOST_CSR_BASE + 0xB0) /* CLP命令请求寄存器。(each PF will use offset=0x050 to access this CSR) */ +#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_0_REG \ + (CSR_HOST_CSR_BASE + \ + 0xC0) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */ +#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_1_REG \ + (CSR_HOST_CSR_BASE + \ + 0xC8) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */ +#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_2_REG \ + (CSR_HOST_CSR_BASE + \ + 0xD0) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */ +#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_3_REG \ + (CSR_HOST_CSR_BASE + \ + 0xD8) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */ +#define CSR_HOST_CSR_HOST_MPU_NOTIFY_CTL_4_REG \ + (CSR_HOST_CSR_BASE + \ + 0xE0) /* control CSR for communication from HOST to MPU.(each PF will use offset=0x0C0 to access this CSR) */ +#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_0_REG \ + (CSR_HOST_CSR_BASE + \ + 0xC4) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */ +#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_1_REG \ + (CSR_HOST_CSR_BASE + \ + 0xCC) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */ +#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_2_REG \ + (CSR_HOST_CSR_BASE + \ + 0xD4) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */ +#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_3_REG \ + (CSR_HOST_CSR_BASE + \ + 0xDC) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */ +#define CSR_HOST_CSR_MPU_HOST_NOTIFY_CTL_4_REG \ + (CSR_HOST_CSR_BASE + \ + 0xE4) /* control CSR for communication from MPU to HOST.(each PF will use offset=0x0C4 to access this CSR) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x100) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x104) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x108) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x10C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x110) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x114) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x118) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x11C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x120) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x124) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x128) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x12C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x130) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x134) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x138) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x13C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x140) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x144) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x148) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x14C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x150) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x154) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x158) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x15C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x160) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x164) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x168) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x16C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x170) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x174) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x178) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST0_MPU_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x17C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x180) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x184) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x188) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x18C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x190) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x194) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x198) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x19C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x1A0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x1A4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x1A8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x1AC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x1B0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x1B4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x1B8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x1BC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x1C0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x1C4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x1C8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x1CC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x1D0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x1D4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x1D8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x1DC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x1E0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x1E4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x1E8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x1EC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x1F0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x1F4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x1F8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST0_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x1FC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x200) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x204) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x208) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x20C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x210) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x214) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x218) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x21C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x220) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x224) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x228) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x22C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x230) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x234) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x238) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x23C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x240) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x244) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x248) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x24C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x250) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x254) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x258) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x25C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x260) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x264) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x268) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x26C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x270) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x274) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x278) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST1_MPU_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x27C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x280) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x284) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x288) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x28C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x290) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x294) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x298) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x29C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x2A0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x2A4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x2A8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x2AC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x2B0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x2B4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x2B8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x2BC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x2C0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x2C4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x2C8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x2CC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x2D0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x2D4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x2D8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x2DC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x2E0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x2E4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x2E8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x2EC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x2F0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x2F4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x2F8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST1_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x2FC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x300) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x304) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x308) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x30C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x310) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x314) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x318) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x31C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x320) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x324) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x328) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x32C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x330) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x334) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x338) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x33C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x340) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x344) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x348) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x34C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x350) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x354) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x358) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x35C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x360) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x364) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x368) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x36C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x370) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x374) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x378) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST2_MPU_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x37C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x380) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x384) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x388) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x38C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x390) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x394) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x398) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x39C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x3A0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x3A4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x3A8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x3AC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x3B0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x3B4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x3B8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x3BC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x3C0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x3C4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x3C8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x3CC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x3D0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x3D4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x3D8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x3DC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x3E0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x3E4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x3E8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x3EC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x3F0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x3F4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x3F8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST2_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x3FC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x400) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x404) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x408) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x40C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x410) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x414) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x418) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x41C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x420) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x424) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x428) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x42C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x430) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x434) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x438) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x43C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x440) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x444) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x448) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x44C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x450) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x454) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x458) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x45C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x460) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x464) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x468) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x46C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x470) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x474) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x478) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST3_MPU_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x47C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x480) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x484) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x488) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x48C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x490) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x494) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x498) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x49C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x4A0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x4A4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x4A8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x4AC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x4B0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x4B4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x4B8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x4BC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x4C0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x4C4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x4C8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x4CC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x4D0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x4D4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x4D8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x4DC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x4E0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x4E4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x4E8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x4EC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x4F0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x4F4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x4F8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST3_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x4FC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x500) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x504) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x508) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x50C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x510) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x514) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x518) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x51C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x520) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x524) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x528) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x52C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x530) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x534) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x538) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x53C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x540) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x544) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x548) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x54C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x550) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x554) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x558) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x55C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x560) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x564) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x568) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x56C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x570) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x574) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x578) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_HOST4_MPU_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x57C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x100~0x17C to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_0_REG \ + (CSR_HOST_CSR_BASE + 0x580) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_1_REG \ + (CSR_HOST_CSR_BASE + 0x584) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_2_REG \ + (CSR_HOST_CSR_BASE + 0x588) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_3_REG \ + (CSR_HOST_CSR_BASE + 0x58C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_4_REG \ + (CSR_HOST_CSR_BASE + 0x590) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_5_REG \ + (CSR_HOST_CSR_BASE + 0x594) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_6_REG \ + (CSR_HOST_CSR_BASE + 0x598) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_7_REG \ + (CSR_HOST_CSR_BASE + 0x59C) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_8_REG \ + (CSR_HOST_CSR_BASE + 0x5A0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_9_REG \ + (CSR_HOST_CSR_BASE + 0x5A4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_10_REG \ + (CSR_HOST_CSR_BASE + 0x5A8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_11_REG \ + (CSR_HOST_CSR_BASE + 0x5AC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_12_REG \ + (CSR_HOST_CSR_BASE + 0x5B0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_13_REG \ + (CSR_HOST_CSR_BASE + 0x5B4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_14_REG \ + (CSR_HOST_CSR_BASE + 0x5B8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_15_REG \ + (CSR_HOST_CSR_BASE + 0x5BC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_16_REG \ + (CSR_HOST_CSR_BASE + 0x5C0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_17_REG \ + (CSR_HOST_CSR_BASE + 0x5C4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_18_REG \ + (CSR_HOST_CSR_BASE + 0x5C8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_19_REG \ + (CSR_HOST_CSR_BASE + 0x5CC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_20_REG \ + (CSR_HOST_CSR_BASE + 0x5D0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_21_REG \ + (CSR_HOST_CSR_BASE + 0x5D4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_22_REG \ + (CSR_HOST_CSR_BASE + 0x5D8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_23_REG \ + (CSR_HOST_CSR_BASE + 0x5DC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_24_REG \ + (CSR_HOST_CSR_BASE + 0x5E0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_25_REG \ + (CSR_HOST_CSR_BASE + 0x5E4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_26_REG \ + (CSR_HOST_CSR_BASE + 0x5E8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_27_REG \ + (CSR_HOST_CSR_BASE + 0x5EC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_28_REG \ + (CSR_HOST_CSR_BASE + 0x5F0) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_29_REG \ + (CSR_HOST_CSR_BASE + 0x5F4) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_30_REG \ + (CSR_HOST_CSR_BASE + 0x5F8) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ +#define CSR_HOST_CSR_MPU_HOST4_NOTIFY_DATA_31_REG \ + (CSR_HOST_CSR_BASE + 0x5FC) /* data registers for communication between host and MPU.(each PF will use \ + offset=0x180~0x1FC to access corresponding host CSRs) */ + +/* glb_csr Base address of Module's Register */ +#define CSR_GLB_CSR_BASE (0x43AD000) + +/* **************************************************************************** */ +/* glb_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_GLB_CSR_GLB_CPI_VERSION_CSR_REG (CSR_GLB_CSR_BASE + 0x0) +#define CSR_GLB_CSR_GLB_X86_REQ_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x4) +#define CSR_GLB_CSR_GLB_X86_CPL_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x8) +#define CSR_GLB_CSR_GLB_SPU_X86_ACC_WEIGHT_REG (CSR_GLB_CSR_BASE + 0xC) +#define CSR_GLB_CSR_GLB_PORT_MODE_REG (CSR_GLB_CSR_BASE + 0x10) +#define CSR_GLB_CSR_GLB_SPU_REQ_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x14) +#define CSR_GLB_CSR_GLB_SPU_CPL_CRD_FLUSH_CTL_REG (CSR_GLB_CSR_BASE + 0x18) +#define CSR_GLB_CSR_GLB_RES_PER_FUNC_REG (CSR_GLB_CSR_BASE + 0x50) /* The global resources for each function */ +#define CSR_GLB_CSR_API_GAP_CTL_REG (CSR_GLB_CSR_BASE + 0x54) /* API sending gap configuration */ +#define CSR_GLB_CSR_DIR_WQE_GAP_CTL_REG (CSR_GLB_CSR_BASE + 0x58) /* Direct WQE sending gap configuration */ +#define CSR_GLB_CSR_DIR_WQE_TIMEOUT_REG (CSR_GLB_CSR_BASE + 0x5C) /* Direct WQE timeout configuration */ +#define CSR_GLB_CSR_GLB_SW_SRCH_TCAM_CTL_REG (CSR_GLB_CSR_BASE + 0x80) +#define CSR_GLB_CSR_GLB_SW_SRCH_TCAM_RSLT_REG (CSR_GLB_CSR_BASE + 0x84) +#define CSR_GLB_CSR_GLB_APB_TIMER_CFG_REG (CSR_GLB_CSR_BASE + 0x88) /* The threshold for wait timer in the I_CTL */ +#define CSR_GLB_CSR_GLB_SRV_TYPE_FOR_DDB_REG \ + (CSR_GLB_CSR_BASE + 0x8C) /* The Srv_Type in the doorbell API generated by direct WQE */ +#define CSR_GLB_CSR_GLB_NL2N_INLINE_OTD_REG (CSR_GLB_CSR_BASE + 0x90) /* Outstanding of NL2N sub-command */ +#define CSR_GLB_CSR_GLB_NL2N_INLINE_NUM_TH_REG \ + (CSR_GLB_CSR_BASE + 0x94) /* Upper threshold of local NL2N sub-command. */ +#define CSR_GLB_CSR_GLB_TILEP_POLL_GAP_REG (CSR_GLB_CSR_BASE + 0x98) /* Poll gap of tile proxy */ +#define CSR_GLB_CSR_GLB_MB_TX_LEGAL_CHK_REG \ + (CSR_GLB_CSR_BASE + 0xA0) /* check the mailbox sendor and receiver whether legal */ +#define CSR_GLB_CSR_GLB_CPL_CTRL_REG (CSR_GLB_CSR_BASE + 0xA8) /* CPL Control */ +#define CSR_GLB_CSR_UCPU_MB_TX_CTL_REG (CSR_GLB_CSR_BASE + 0xB0) /* the UCPU MB send control */ +#define CSR_GLB_CSR_UCPU_ALLOW_VF_CFG_REG (CSR_GLB_CSR_BASE + 0xBC) /* the UCPU alow VF have configure right */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_0_REG (CSR_GLB_CSR_BASE + 0xC0) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_1_REG (CSR_GLB_CSR_BASE + 0xC4) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_2_REG (CSR_GLB_CSR_BASE + 0xC8) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_3_REG (CSR_GLB_CSR_BASE + 0xCC) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_4_REG (CSR_GLB_CSR_BASE + 0xD0) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_5_REG (CSR_GLB_CSR_BASE + 0xD4) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_6_REG (CSR_GLB_CSR_BASE + 0xD8) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_7_REG (CSR_GLB_CSR_BASE + 0xDC) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_8_REG (CSR_GLB_CSR_BASE + 0xE0) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_9_REG (CSR_GLB_CSR_BASE + 0xE4) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_10_REG (CSR_GLB_CSR_BASE + 0xE8) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_11_REG (CSR_GLB_CSR_BASE + 0xEC) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_12_REG (CSR_GLB_CSR_BASE + 0xF0) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_13_REG (CSR_GLB_CSR_BASE + 0xF4) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_14_REG (CSR_GLB_CSR_BASE + 0xF8) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_UCPU_MB_TX_DATA_15_REG (CSR_GLB_CSR_BASE + 0xFC) /* the UCPU MB data to be sent */ +#define CSR_GLB_CSR_PF_EPROM_OFFSET_BASE_REG (CSR_GLB_CSR_BASE + 0x100) /* The Expansion ROM offset configuration */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_CTRL0_REG \ + (CSR_GLB_CSR_BASE + 0x200) /* CPI internal table indirect access ctrl registers */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_CTRL1_REG \ + (CSR_GLB_CSR_BASE + 0x204) /* CPI internal table indirect access ctrl registers */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_0_REG (CSR_GLB_CSR_BASE + 0x210) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_1_REG (CSR_GLB_CSR_BASE + 0x214) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_2_REG (CSR_GLB_CSR_BASE + 0x218) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_3_REG (CSR_GLB_CSR_BASE + 0x21C) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_4_REG (CSR_GLB_CSR_BASE + 0x220) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_5_REG (CSR_GLB_CSR_BASE + 0x224) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_6_REG (CSR_GLB_CSR_BASE + 0x228) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_TBL_INDIR_DATA_7_REG (CSR_GLB_CSR_BASE + 0x22C) /* CPI internal table indirect access data */ +#define CSR_GLB_CSR_CPI_INDIR_PATH_RING_CTRL_REG (CSR_GLB_CSR_BASE + 0x230) /* pcie indir to ring path control */ +#define CSR_GLB_CSR_CPI_INDIR_PATH_RING_DAT0_REG (CSR_GLB_CSR_BASE + 0x234) /* pcie indir to ring path data0 */ +#define CSR_GLB_CSR_CPI_INDIR_PATH_RING_DAT1_REG (CSR_GLB_CSR_BASE + 0x238) /* pcie indir to ring path data0 */ +#define CSR_GLB_CSR_CPI_RAM_INIT_REQ_REG (CSR_GLB_CSR_BASE + 0x240) /* CPI internal RAM initial request */ +#define CSR_GLB_CSR_CPI_RAM_INIT_STS0_REG (CSR_GLB_CSR_BASE + 0x250) /* CPI internal RAM initial status 0 */ +#define CSR_GLB_CSR_CPI_RAM_INIT_STS1_REG (CSR_GLB_CSR_BASE + 0x254) /* CPI internal RAM initial status 1 */ +#define CSR_GLB_CSR_CPI_MB_TX_GAP_REG (CSR_GLB_CSR_BASE + 0x260) /* CPI control the mailobx sending gap */ +#define CSR_GLB_CSR_GLB_CPI_RAM_ECC_BYPASS_REG (CSR_GLB_CSR_BASE + 0x280) /* CPI internal RAM test mode */ +#define CSR_GLB_CSR_GLB_MB_SHP_HOST0_REG (CSR_GLB_CSR_BASE + 0x290) /* mailbox shaper control csr for host0 */ +#define CSR_GLB_CSR_GLB_MB_SHP_HOST1_REG (CSR_GLB_CSR_BASE + 0x294) /* mailbox shaper control csr for host1 */ +#define CSR_GLB_CSR_GLB_MB_SHP_HOST2_REG (CSR_GLB_CSR_BASE + 0x298) /* mailbox shaper control csr for host2 */ +#define CSR_GLB_CSR_GLB_MB_SHP_HOST3_REG (CSR_GLB_CSR_BASE + 0x29C) /* mailbox shaper control csr for host3 */ +#define CSR_GLB_CSR_GLB_MB_SHP_HOST4_REG (CSR_GLB_CSR_BASE + 0x2A0) /* mailbox shaper control csr for host4 */ +#define CSR_GLB_CSR_GLB_MB_SHP_UNIT_REG (CSR_GLB_CSR_BASE + 0x2A4) /* mailbox shaper time unit */ +#define CSR_GLB_CSR_GLB_MB_RIGHT_CFG_REG (CSR_GLB_CSR_BASE + 0x2A8) +#define CSR_GLB_CSR_GLB_CSR_ACC_TIMEOUT_REG (CSR_GLB_CSR_BASE + 0x2B0) +#define CSR_GLB_CSR_GLB_CPI_RS_ND_PE_CRDIT_REG (CSR_GLB_CSR_BASE + 0x2B8) +#define CSR_GLB_CSR_GLB_NP_CTX_CFG_REG (CSR_GLB_CSR_BASE + 0x2F0) +#define CSR_GLB_CSR_GLB_IPUSH_FIFO_BP_REG (CSR_GLB_CSR_BASE + 0x318) +#define CSR_GLB_CSR_GLB_IPUSH_FIFO_STS_REG (CSR_GLB_CSR_BASE + 0x31C) +#define CSR_GLB_CSR_GLB_CPATH_INT_BITMAP_REG (CSR_GLB_CSR_BASE + 0x340) /* non-cpi INT的中断屏蔽寄存器 */ +#define CSR_GLB_CSR_GLB_DWQE_BUF_VLD_NUM_REG (CSR_GLB_CSR_BASE + 0x344) /* Direct WQE Buffer的可用参数 */ +#define CSR_GLB_CSR_DIR_WQE_BYTE_ORDER_EN_REG (CSR_GLB_CSR_BASE + 0x354) /* Direct WQE字节序转换使能 */ +#define CSR_GLB_CSR_FAKE_VFID_CAL_CFG_REG (CSR_GLB_CSR_BASE + 0x360) /* fake VFID此寄存器配置要保证全局一致。 */ +#define CSR_GLB_CSR_FAKE_VFID_ENABLE_REG (CSR_GLB_CSR_BASE + 0x364) /* fake VFID此寄存器配置要保证全局一致。 */ +#define CSR_GLB_CSR_DBL_FAKE_VFID_CBIT_EN_REG (CSR_GLB_CSR_BASE + 0x368) +#define CSR_GLB_CSR_DBL_SRV_TYPE_ILLEGAL_REG (CSR_GLB_CSR_BASE + 0x36C) +#define CSR_GLB_CSR_GLB_DWQE_LB_HASH_ACC_REG (CSR_GLB_CSR_BASE + 0x370) /* load balance此寄存器配置要保证全局一致。 */ +#define CSR_GLB_CSR_GLB_DWQE_LB_MOD_REG (CSR_GLB_CSR_BASE + 0x374) /* load balance此寄存器配置要保证全局一致。 */ +#define CSR_GLB_CSR_GLB_DWQE_SMF_PG_REG (CSR_GLB_CSR_BASE + 0x378) /* load balance此寄存器配置要保证全局一致。 */ +#define CSR_GLB_CSR_VIRTIO_BYTE_ORDER_DIS_REG (CSR_GLB_CSR_BASE + 0x380) /* VIRTIO_ITF字节序转换disable */ +#define CSR_GLB_CSR_NVME_RSV_ADDR_RANGE_REG (CSR_GLB_CSR_BASE + 0x384) +#define CSR_GLB_CSR_VIRTIO_LB_MOD_REG (CSR_GLB_CSR_BASE + 0x388) +#define CSR_GLB_CSR_VIRTIO_OTD_MAX_TH_REG (CSR_GLB_CSR_BASE + 0x38C) +#define CSR_GLB_CSR_GLB_FLXQ_MAP_EN_REG (CSR_GLB_CSR_BASE + 0x390) +#define CSR_GLB_CSR_GLB_AEQ_IDX_FOR_VF_REG (CSR_GLB_CSR_BASE + 0x3A0) /* 第一个VF所对应物理资源AEQ的起始编号。 */ +#define CSR_GLB_CSR_PTP_TS_UPDT_CFG_REG (CSR_GLB_CSR_BASE + 0x3AC) /* Timestamp timer update */ +#define CSR_GLB_CSR_PTP_TS_INC_CFG_REG (CSR_GLB_CSR_BASE + 0x3B0) /* Timestamp timer configuration */ +#define CSR_GLB_CSR_PTP_TS_CALIBRATION_REG (CSR_GLB_CSR_BASE + 0x3B4) /* Timestamp timer calibration */ +#define CSR_GLB_CSR_PTP_TS_WR_DATA0_REG (CSR_GLB_CSR_BASE + 0x3B8) /* Timestamp timer write data 0 */ +#define CSR_GLB_CSR_PTP_TS_WR_DATA1_REG (CSR_GLB_CSR_BASE + 0x3BC) /* Timestamp timer write data 1 */ +#define CSR_GLB_CSR_PTP_TS_WR_DATA2_REG (CSR_GLB_CSR_BASE + 0x3C0) /* Timestamp timer write data 2 */ +#define CSR_GLB_CSR_PTP_TS_RD_DATA0_REG (CSR_GLB_CSR_BASE + 0x3C4) /* Timestamp timer read data 0 */ +#define CSR_GLB_CSR_PTP_TS_RD_DATA1_REG (CSR_GLB_CSR_BASE + 0x3C8) /* Timestamp timer read data 1 */ +#define CSR_GLB_CSR_PTP_TS_RD_DATA2_REG (CSR_GLB_CSR_BASE + 0x3CC) /* Timestamp timer read data 2 */ +#define CSR_GLB_CSR_PTP_TS_UP_EN_REG \ + (CSR_GLB_CSR_BASE + \ + 0x3D0) /* Timestamp timer update enableAttention, bit[3:0] should be configured in onehot mode. */ +#define CSR_GLB_CSR_PTP_DSTR_CFG_REG (CSR_GLB_CSR_BASE + 0x3D4) /* Timestamp distribute configuration */ +#define CSR_GLB_CSR_NON_PTP_TS_INC_CFG_REG (CSR_GLB_CSR_BASE + 0x3D8) /* non-MAC Timestamp timer configuration */ +#define CSR_GLB_CSR_NON_PTP_TS_CALIBRATION_REG (CSR_GLB_CSR_BASE + 0x3DC) /* non-MAC Timestamp timer calibration */ +#define CSR_GLB_CSR_NON_PTP_TS_WR_DATA0_REG (CSR_GLB_CSR_BASE + 0x3E0) /* non-MAC Timestamp timer write data 0 */ +#define CSR_GLB_CSR_NON_PTP_TS_WR_DATA1_REG (CSR_GLB_CSR_BASE + 0x3E4) /* non-MAC Timestamp timer write data 1 */ +#define CSR_GLB_CSR_NON_PTP_TS_WR_DATA2_REG (CSR_GLB_CSR_BASE + 0x3E8) /* non-MAC Timestamp timer write data 2 */ +#define CSR_GLB_CSR_NON_PTP_TS_RD_DATA0_REG (CSR_GLB_CSR_BASE + 0x3EC) /* non-MAC Timestamp timer read data 0 */ +#define CSR_GLB_CSR_NON_PTP_TS_RD_DATA1_REG (CSR_GLB_CSR_BASE + 0x3F0) /* non-MAC Timestamp timer read data 1 */ +#define CSR_GLB_CSR_NON_PTP_TS_RD_DATA2_REG (CSR_GLB_CSR_BASE + 0x3F4) /* non-MAC Timestamp timer read data 2 */ +#define CSR_GLB_CSR_NON_PTP_TS_UP_EN_REG \ + (CSR_GLB_CSR_BASE + \ + 0x3F8) /* non-MAC Timestamp timer update enable.Attention, bit[2:0] should be configured in onehot mode. */ +#define CSR_GLB_CSR_NON_PTP_DSTR_CFG_REG (CSR_GLB_CSR_BASE + 0x3FC) /* non-MAC Timestamp distribute configuration */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_0_REG (CSR_GLB_CSR_BASE + 0x400) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_1_REG (CSR_GLB_CSR_BASE + 0x404) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_2_REG (CSR_GLB_CSR_BASE + 0x408) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_3_REG (CSR_GLB_CSR_BASE + 0x40C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_4_REG (CSR_GLB_CSR_BASE + 0x410) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_5_REG (CSR_GLB_CSR_BASE + 0x414) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_6_REG (CSR_GLB_CSR_BASE + 0x418) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_7_REG (CSR_GLB_CSR_BASE + 0x41C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_8_REG (CSR_GLB_CSR_BASE + 0x420) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_9_REG (CSR_GLB_CSR_BASE + 0x424) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_10_REG (CSR_GLB_CSR_BASE + 0x428) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_11_REG (CSR_GLB_CSR_BASE + 0x42C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_12_REG (CSR_GLB_CSR_BASE + 0x430) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_13_REG (CSR_GLB_CSR_BASE + 0x434) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_14_REG (CSR_GLB_CSR_BASE + 0x438) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_15_REG (CSR_GLB_CSR_BASE + 0x43C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_16_REG (CSR_GLB_CSR_BASE + 0x440) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_17_REG (CSR_GLB_CSR_BASE + 0x444) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_18_REG (CSR_GLB_CSR_BASE + 0x448) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_19_REG (CSR_GLB_CSR_BASE + 0x44C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_20_REG (CSR_GLB_CSR_BASE + 0x450) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_21_REG (CSR_GLB_CSR_BASE + 0x454) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_22_REG (CSR_GLB_CSR_BASE + 0x458) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_23_REG (CSR_GLB_CSR_BASE + 0x45C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_24_REG (CSR_GLB_CSR_BASE + 0x460) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_25_REG (CSR_GLB_CSR_BASE + 0x464) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_26_REG (CSR_GLB_CSR_BASE + 0x468) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_27_REG (CSR_GLB_CSR_BASE + 0x46C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_28_REG (CSR_GLB_CSR_BASE + 0x470) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_29_REG (CSR_GLB_CSR_BASE + 0x474) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_30_REG (CSR_GLB_CSR_BASE + 0x478) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_31_REG (CSR_GLB_CSR_BASE + 0x47C) /* vf offset for the PF */ +#define CSR_GLB_CSR_GLB_VF_OFFSET_FOR_PF_32_REG (CSR_GLB_CSR_BASE + 0x480) /* vf offset for the PF */ + +/* api_chn_csr Base address of Module's Register */ +#define CSR_API_CHN_CSR_BASE (0x43A4000) + +/* **************************************************************************** */ +/* api_chn_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_API_CHN_CSR_API_CHAIN_ADDR_H_0_REG \ + (CSR_API_CHN_CSR_BASE + \ + 0x0) /* high 32 bits address of an API chain一个PF最多分配128份api chain资源。全局共有256份api chain资源。 */ +#define CSR_API_CHN_CSR_API_CHAIN_ADDR_H_1_REG \ + (CSR_API_CHN_CSR_BASE + \ + 0x80) /* high 32 bits address of an API chain一个PF最多分配128份api chain资源。全局共有256份api chain资源。 */ +#define CSR_API_CHN_CSR_API_CHAIN_ADDR_L_0_REG (CSR_API_CHN_CSR_BASE + 0x4) /* low 32 bits address of an API chain */ +#define CSR_API_CHN_CSR_API_CHAIN_ADDR_L_1_REG (CSR_API_CHN_CSR_BASE + 0x84) /* low 32 bits address of an API chain */ +#define CSR_API_CHN_CSR_API_STATUS_ADDR_H_0_REG \ + (CSR_API_CHN_CSR_BASE + 0x8) /* High 32 bits address to write back status */ +#define CSR_API_CHN_CSR_API_STATUS_ADDR_H_1_REG \ + (CSR_API_CHN_CSR_BASE + 0x88) /* High 32 bits address to write back status */ +#define CSR_API_CHN_CSR_API_STATUS_ADDR_L_0_REG \ + (CSR_API_CHN_CSR_BASE + 0xC) /* Low 32 bits address to write back status */ +#define CSR_API_CHN_CSR_API_STATUS_ADDR_L_1_REG \ + (CSR_API_CHN_CSR_BASE + 0x8C) /* Low 32 bits address to write back status */ +#define CSR_API_CHN_CSR_API_CHAIN_LEN_0_REG (CSR_API_CHN_CSR_BASE + 0x10) /* The API chain length */ +#define CSR_API_CHN_CSR_API_CHAIN_LEN_1_REG (CSR_API_CHN_CSR_BASE + 0x90) /* The API chain length */ +#define CSR_API_CHN_CSR_API_CHAIN_CTL_0_REG (CSR_API_CHN_CSR_BASE + 0x14) /* API chain attribute */ +#define CSR_API_CHN_CSR_API_CHAIN_CTL_1_REG (CSR_API_CHN_CSR_BASE + 0x94) /* API chain attribute */ +#define CSR_API_CHN_CSR_API_CHAIN_DMA_ATTR_0_REG (CSR_API_CHN_CSR_BASE + 0x18) /* API TPH control filed */ +#define CSR_API_CHN_CSR_API_CHAIN_DMA_ATTR_1_REG (CSR_API_CHN_CSR_BASE + 0x98) /* API TPH control filed */ +#define CSR_API_CHN_CSR_API_CHAIN_PI_0_REG (CSR_API_CHN_CSR_BASE + 0x1C) /* The PI value of an API chain */ +#define CSR_API_CHN_CSR_API_CHAIN_PI_1_REG (CSR_API_CHN_CSR_BASE + 0x9C) /* The PI value of an API chain */ +#define CSR_API_CHN_CSR_API_CHAIN_REQ_0_REG (CSR_API_CHN_CSR_BASE + 0x20) /* API chain control */ +#define CSR_API_CHN_CSR_API_CHAIN_REQ_1_REG (CSR_API_CHN_CSR_BASE + 0xA0) /* API chain control */ +#define CSR_API_CHN_CSR_API_STATUS_0_0_REG (CSR_API_CHN_CSR_BASE + 0x30) /* API Chain Status */ +#define CSR_API_CHN_CSR_API_STATUS_0_1_REG (CSR_API_CHN_CSR_BASE + 0xB0) /* API Chain Status */ +#define CSR_API_CHN_CSR_API_STATUS_1_0_REG (CSR_API_CHN_CSR_BASE + 0x34) /* API Chain Current Address H */ +#define CSR_API_CHN_CSR_API_STATUS_1_1_REG (CSR_API_CHN_CSR_BASE + 0xB4) /* API Chain Current Address H */ +#define CSR_API_CHN_CSR_API_STATUS_2_0_REG (CSR_API_CHN_CSR_BASE + 0x38) /* API Chain Current Address L */ +#define CSR_API_CHN_CSR_API_STATUS_2_1_REG (CSR_API_CHN_CSR_BASE + 0xB8) /* API Chain Current Address L */ + +/* dfx_glb_csr Base address of Module's Register */ +#define CSR_DFX_GLB_CSR_BASE (0x43AF000) + +/* **************************************************************************** */ +/* dfx_glb_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_0_REG (CSR_DFX_GLB_CSR_BASE + 0x0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_1_REG (CSR_DFX_GLB_CSR_BASE + 0x10) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_2_REG (CSR_DFX_GLB_CSR_BASE + 0x20) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_3_REG (CSR_DFX_GLB_CSR_BASE + 0x30) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_4_REG (CSR_DFX_GLB_CSR_BASE + 0x40) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_5_REG (CSR_DFX_GLB_CSR_BASE + 0x50) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_6_REG (CSR_DFX_GLB_CSR_BASE + 0x60) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_7_REG (CSR_DFX_GLB_CSR_BASE + 0x70) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_8_REG (CSR_DFX_GLB_CSR_BASE + 0x80) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_9_REG (CSR_DFX_GLB_CSR_BASE + 0x90) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_10_REG (CSR_DFX_GLB_CSR_BASE + 0xA0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_11_REG (CSR_DFX_GLB_CSR_BASE + 0xB0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_12_REG (CSR_DFX_GLB_CSR_BASE + 0xC0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_13_REG (CSR_DFX_GLB_CSR_BASE + 0xD0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_14_REG (CSR_DFX_GLB_CSR_BASE + 0xE0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_CFG_15_REG (CSR_DFX_GLB_CSR_BASE + 0xF0) /* CPI debug control */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_0_REG (CSR_DFX_GLB_CSR_BASE + 0x4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_1_REG (CSR_DFX_GLB_CSR_BASE + 0x14) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_2_REG (CSR_DFX_GLB_CSR_BASE + 0x24) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_3_REG (CSR_DFX_GLB_CSR_BASE + 0x34) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_4_REG (CSR_DFX_GLB_CSR_BASE + 0x44) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_5_REG (CSR_DFX_GLB_CSR_BASE + 0x54) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_6_REG (CSR_DFX_GLB_CSR_BASE + 0x64) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_7_REG (CSR_DFX_GLB_CSR_BASE + 0x74) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_8_REG (CSR_DFX_GLB_CSR_BASE + 0x84) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_9_REG (CSR_DFX_GLB_CSR_BASE + 0x94) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_10_REG (CSR_DFX_GLB_CSR_BASE + 0xA4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_11_REG (CSR_DFX_GLB_CSR_BASE + 0xB4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_12_REG (CSR_DFX_GLB_CSR_BASE + 0xC4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_13_REG (CSR_DFX_GLB_CSR_BASE + 0xD4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_14_REG (CSR_DFX_GLB_CSR_BASE + 0xE4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_TLP_CNT_15_REG (CSR_DFX_GLB_CSR_BASE + 0xF4) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_0_REG (CSR_DFX_GLB_CSR_BASE + 0x8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_1_REG (CSR_DFX_GLB_CSR_BASE + 0x18) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_2_REG (CSR_DFX_GLB_CSR_BASE + 0x28) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_3_REG (CSR_DFX_GLB_CSR_BASE + 0x38) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_4_REG (CSR_DFX_GLB_CSR_BASE + 0x48) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_5_REG (CSR_DFX_GLB_CSR_BASE + 0x58) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_6_REG (CSR_DFX_GLB_CSR_BASE + 0x68) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_7_REG (CSR_DFX_GLB_CSR_BASE + 0x78) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_8_REG (CSR_DFX_GLB_CSR_BASE + 0x88) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_9_REG (CSR_DFX_GLB_CSR_BASE + 0x98) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_10_REG (CSR_DFX_GLB_CSR_BASE + 0xA8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_11_REG (CSR_DFX_GLB_CSR_BASE + 0xB8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_12_REG (CSR_DFX_GLB_CSR_BASE + 0xC8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_13_REG (CSR_DFX_GLB_CSR_BASE + 0xD8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_14_REG (CSR_DFX_GLB_CSR_BASE + 0xE8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DBL_CNT_15_REG (CSR_DFX_GLB_CSR_BASE + 0xF8) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_0_REG (CSR_DFX_GLB_CSR_BASE + 0xC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_1_REG (CSR_DFX_GLB_CSR_BASE + 0x1C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_2_REG (CSR_DFX_GLB_CSR_BASE + 0x2C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_3_REG (CSR_DFX_GLB_CSR_BASE + 0x3C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_4_REG (CSR_DFX_GLB_CSR_BASE + 0x4C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_5_REG (CSR_DFX_GLB_CSR_BASE + 0x5C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_6_REG (CSR_DFX_GLB_CSR_BASE + 0x6C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_7_REG (CSR_DFX_GLB_CSR_BASE + 0x7C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_8_REG (CSR_DFX_GLB_CSR_BASE + 0x8C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_9_REG (CSR_DFX_GLB_CSR_BASE + 0x9C) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_10_REG (CSR_DFX_GLB_CSR_BASE + 0xAC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_11_REG (CSR_DFX_GLB_CSR_BASE + 0xBC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_12_REG (CSR_DFX_GLB_CSR_BASE + 0xCC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_13_REG (CSR_DFX_GLB_CSR_BASE + 0xDC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_14_REG (CSR_DFX_GLB_CSR_BASE + 0xEC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_DEBUG_RX_DWQE_CNT_15_REG (CSR_DFX_GLB_CSR_BASE + 0xFC) /* CPI debug Rx TLP counter */ +#define CSR_DFX_GLB_CSR_GLB_PORT0_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x100) +#define CSR_DFX_GLB_CSR_GLB_PORT1_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x104) +#define CSR_DFX_GLB_CSR_GLB_PORT2_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x108) +#define CSR_DFX_GLB_CSR_GLB_PORT3_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x10C) +#define CSR_DFX_GLB_CSR_GLB_PORT4_NPCPL_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x110) +#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_OK_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x114) +#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x118) +#define CSR_DFX_GLB_CSR_DFX_ICTL_SOP_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x11C) +#define CSR_DFX_GLB_CSR_DFX_ICTL_MPU_ACC_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x120) +#define CSR_DFX_GLB_CSR_DFX_ICTL_IPUSH_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x124) +#define CSR_DFX_GLB_CSR_DFX_ICTL_VIO_TLP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x128) +#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_IO_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x12C) +#define CSR_DFX_GLB_CSR_DFX_ICTL_RX_TLP_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x130) +#define CSR_DFX_GLB_CSR_GLB_CPI_PORT_BP_EN_CFG_REG (CSR_DFX_GLB_CSR_BASE + 0x134) +#define CSR_DFX_GLB_CSR_DFX_ICTL_FATAL_MSK0_REG (CSR_DFX_GLB_CSR_BASE + 0x140) +#define CSR_DFX_GLB_CSR_DFX_ICTL_FATAL_MSK1_REG (CSR_DFX_GLB_CSR_BASE + 0x144) +#define CSR_DFX_GLB_CSR_DFX_ICTL_FATAL_MSK2_REG (CSR_DFX_GLB_CSR_BASE + 0x148) +#define CSR_DFX_GLB_CSR_DFX_ICTL_NONFATAL_MSK0_REG (CSR_DFX_GLB_CSR_BASE + 0x150) +#define CSR_DFX_GLB_CSR_DFX_ICTL_NONFATAL_MSK1_REG (CSR_DFX_GLB_CSR_BASE + 0x154) +#define CSR_DFX_GLB_CSR_DFX_ICTL_NONFATAL_MSK2_REG (CSR_DFX_GLB_CSR_BASE + 0x158) +#define CSR_DFX_GLB_CSR_DFX_ICTL_ERR_PLS0_REG (CSR_DFX_GLB_CSR_BASE + 0x160) +#define CSR_DFX_GLB_CSR_DFX_ICTL_ERR_PLS1_REG (CSR_DFX_GLB_CSR_BASE + 0x164) +#define CSR_DFX_GLB_CSR_DFX_ICTL_ERR_PLS2_REG (CSR_DFX_GLB_CSR_BASE + 0x168) +#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_STS_REG (CSR_DFX_GLB_CSR_BASE + 0x400) /* CPI BP WATCH Status */ +#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_WINDOW_REG (CSR_DFX_GLB_CSR_BASE + 0x404) /* CPI backpressure watch window */ +#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_BITMAP_REG (CSR_DFX_GLB_CSR_BASE + 0x408) /* CPI backpressure watch bitmap */ +#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_START_REG (CSR_DFX_GLB_CSR_BASE + 0x40C) /* CPI backpressure watch start */ +#define CSR_DFX_GLB_CSR_GLB_CPI_BP_WATCH_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x410) /* CPI backpressure watch counter */ +#define CSR_DFX_GLB_CSR_GLB_CSR_TIMEOUT_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x414) +#define CSR_DFX_GLB_CSR_DWQE_API_NO_ENOUGH_DATA_REG (CSR_DFX_GLB_CSR_BASE + 0x418) +#define CSR_DFX_GLB_CSR_DWQE_DBL_NO_ENOUGH_DATA_REG (CSR_DFX_GLB_CSR_BASE + 0x41C) +#define CSR_DFX_GLB_CSR_NORM_DBL_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x420) +#define CSR_DFX_GLB_CSR_NORM_DBL_TX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x424) +#define CSR_DFX_GLB_CSR_DWQE_DBL_TX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x428) +#define CSR_DFX_GLB_CSR_DWQE_API_TX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x42C) +#define CSR_DFX_GLB_CSR_DWQE_BUF_BP_MSK_REG (CSR_DFX_GLB_CSR_BASE + 0x430) +#define CSR_DFX_GLB_CSR_DWQE_BUF_CNT_PORT_REG (CSR_DFX_GLB_CSR_BASE + 0x434) +#define CSR_DFX_GLB_CSR_DWQE_BUF_BP_ON_PORT_REG (CSR_DFX_GLB_CSR_BASE + 0x438) +#define CSR_DFX_GLB_CSR_DWQE_BUF_BP_OFF_PORT_REG (CSR_DFX_GLB_CSR_BASE + 0x43C) +#define CSR_DFX_GLB_CSR_DWQE_REQ_BUF_BGN_REG (CSR_DFX_GLB_CSR_BASE + 0x440) +#define CSR_DFX_GLB_CSR_DWQE_DROPPING_IN_TX_REG (CSR_DFX_GLB_CSR_BASE + 0x444) +#define CSR_DFX_GLB_CSR_DWQE_DROPPING_NO_BUF_REG (CSR_DFX_GLB_CSR_BASE + 0x448) +#define CSR_DFX_GLB_CSR_DWQE_DBL_WITHOUT_API_REG (CSR_DFX_GLB_CSR_BASE + 0x44C) +#define CSR_DFX_GLB_CSR_DWQE_TX_DBL_AFTER_API_REG (CSR_DFX_GLB_CSR_BASE + 0x450) +#define CSR_DFX_GLB_CSR_DWQE_NO_DBL_AFTER_API_REG (CSR_DFX_GLB_CSR_BASE + 0x454) +#define CSR_DFX_GLB_CSR_DWQE_BUF_OVERWRITE_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x458) +#define CSR_DFX_GLB_CSR_DWQE_BUF_AGING_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x45C) +#define CSR_DFX_GLB_CSR_DWQE_TX_REQ_FIFO_PUSH_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x460) +#define CSR_DFX_GLB_CSR_DWQE_TX_REQ_FIFO_POP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x464) +#define CSR_DFX_GLB_CSR_DWQE_TX_REQ_FIFO_STS_REG (CSR_DFX_GLB_CSR_BASE + 0x468) +#define CSR_DFX_GLB_CSR_DWQE_DROPPING_INVLD_REG (CSR_DFX_GLB_CSR_BASE + 0x474) +#define CSR_DFX_GLB_CSR_DWQE_SW_FORCE_DROP_REG (CSR_DFX_GLB_CSR_BASE + 0x478) +#define CSR_DFX_GLB_CSR_ICTL_DBL_REQ_SOP_NULL_REG (CSR_DFX_GLB_CSR_BASE + 0x47C) +#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_AEQE_TO_MPU_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x480) +#define CSR_DFX_GLB_CSR_DFX_RX_DWQE_DDB_CNT0_REG (CSR_DFX_GLB_CSR_BASE + 0x4A0) +#define CSR_DFX_GLB_CSR_DFX_RX_DWQE_DDB_CNT1_REG (CSR_DFX_GLB_CSR_BASE + 0x4A4) +#define CSR_DFX_GLB_CSR_DFX_RX_DBL_SRV_CNT0_REG (CSR_DFX_GLB_CSR_BASE + 0x4A8) +#define CSR_DFX_GLB_CSR_DFX_RX_DBL_SRV_CNT1_REG (CSR_DFX_GLB_CSR_BASE + 0x4AC) +#define CSR_DFX_GLB_CSR_GLB_DFX_CFG_SRV_TYPE_REG (CSR_DFX_GLB_CSR_BASE + 0x4B0) +#define CSR_DFX_GLB_CSR_AEQ_CI_SW_WR_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4B4) +#define CSR_DFX_GLB_CSR_AEQ_TX_INT_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4BC) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_WR_PCIE_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4C0) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_WR_UCPU_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4C4) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_RD_PCIE_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4C8) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_RD_UCPU_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4CC) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_OSCH_CPL_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4D0) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_ICTL_CPL_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4D4) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_APICTL_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4D8) +#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_AEQE_TO_DST_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4DC) +#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_AEQE_TO_SRC_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4E0) +#define CSR_DFX_GLB_CSR_CPI_PCIE_MB_STAT_TO_SRC_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4E4) +#define CSR_DFX_GLB_CSR_CPI_UCPU_MB_AEQE_TO_DST_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4E8) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_AEQ_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4EC) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_CEQ_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4F0) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_API_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4F4) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_CSR_INTCTL_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4F8) +#define CSR_DFX_GLB_CSR_CPI_IPUSH_UPITF_CLP_REQ_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x4FC) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR0_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x500) /* CPI internal RAM ECC error injection */ +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR1_REG (CSR_DFX_GLB_CSR_BASE + 0x504) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR2_REG (CSR_DFX_GLB_CSR_BASE + 0x508) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_INJ_ERR3_REG (CSR_DFX_GLB_CSR_BASE + 0x50C) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_MERR0_REG (CSR_DFX_GLB_CSR_BASE + 0x520) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_MERR1_REG (CSR_DFX_GLB_CSR_BASE + 0x524) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR0_REG (CSR_DFX_GLB_CSR_BASE + 0x540) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR1_REG (CSR_DFX_GLB_CSR_BASE + 0x544) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR0_REG (CSR_DFX_GLB_CSR_BASE + 0x560) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR1_REG (CSR_DFX_GLB_CSR_BASE + 0x564) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR2_REG (CSR_DFX_GLB_CSR_BASE + 0x568) +#define CSR_DFX_GLB_CSR_CPI_RAM_ECC_ERR_ADDR3_REG (CSR_DFX_GLB_CSR_BASE + 0x56C) +#define CSR_DFX_GLB_CSR_IPUSH_RESERVED0_REG (CSR_DFX_GLB_CSR_BASE + 0x5C0) +#define CSR_DFX_GLB_CSR_IPUSH_RESERVED1_REG (CSR_DFX_GLB_CSR_BASE + 0x5C4) +#define CSR_DFX_GLB_CSR_IPUSH_RESERVED2_REG (CSR_DFX_GLB_CSR_BASE + 0x5C8) +#define CSR_DFX_GLB_CSR_IPUSH_RESERVED3_REG (CSR_DFX_GLB_CSR_BASE + 0x5CC) +#define CSR_DFX_GLB_CSR_GLB_CPI_UNCRT_ERR_CODE0_REG (CSR_DFX_GLB_CSR_BASE + 0x5D0) +#define CSR_DFX_GLB_CSR_GLB_CPI_UNCRT_ERR_CODE1_REG (CSR_DFX_GLB_CSR_BASE + 0x5D4) +#define CSR_DFX_GLB_CSR_GLB_CPI_CRT_ERR_CODE0_REG (CSR_DFX_GLB_CSR_BASE + 0x5D8) +#define CSR_DFX_GLB_CSR_GLB_CPI_CRT_ERR_CODE1_REG (CSR_DFX_GLB_CSR_BASE + 0x5DC) +#define CSR_DFX_GLB_CSR_DWQE_BUF_DBG0_REG (CSR_DFX_GLB_CSR_BASE + 0x5E0) +#define CSR_DFX_GLB_CSR_DWQE_BUF_DBG1_REG (CSR_DFX_GLB_CSR_BASE + 0x5E4) +#define CSR_DFX_GLB_CSR_DWQE_BUF_DBG2_REG (CSR_DFX_GLB_CSR_BASE + 0x5E8) +#define CSR_DFX_GLB_CSR_DWQE_BUG_DBG3_REG (CSR_DFX_GLB_CSR_BASE + 0x5EC) +#define CSR_DFX_GLB_CSR_GLB_MB_GRP_TX_REQ_H_REG (CSR_DFX_GLB_CSR_BASE + 0x5F0) +#define CSR_DFX_GLB_CSR_GLB_MB_GRP_TX_REQ_L_REG (CSR_DFX_GLB_CSR_BASE + 0x5F4) +#define CSR_DFX_GLB_CSR_GLB_MB_GRP_GRANT_H_REG (CSR_DFX_GLB_CSR_BASE + 0x5F8) +#define CSR_DFX_GLB_CSR_GLB_MB_GRP_GRANT_L_REG (CSR_DFX_GLB_CSR_BASE + 0x5FC) +#define CSR_DFX_GLB_CSR_ICTL_IPUSH_SOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x608) +#define CSR_DFX_GLB_CSR_ICTL_IPUSH_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x60C) +#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_TX_REQ_H_REG (CSR_DFX_GLB_CSR_BASE + 0x610) +#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_TX_REQ_L_REG (CSR_DFX_GLB_CSR_BASE + 0x614) +#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_GRANT_H_REG (CSR_DFX_GLB_CSR_BASE + 0x618) +#define CSR_DFX_GLB_CSR_GLB_MB_IN_GRP_GRANT_L_REG (CSR_DFX_GLB_CSR_BASE + 0x61C) +#define CSR_DFX_GLB_CSR_GLB_MB_TX_START_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x620) +#define CSR_DFX_GLB_CSR_GLB_MB_TX_ILLEGAL_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x624) +#define CSR_DFX_GLB_CSR_GLB_MB_TX_ILLEGAL_CODE_REG (CSR_DFX_GLB_CSR_BASE + 0x628) +#define CSR_DFX_GLB_CSR_GLB_MB_FSM_STATE_REG (CSR_DFX_GLB_CSR_BASE + 0x62C) +#define CSR_DFX_GLB_CSR_ICTL_INBD_FIFO_STS_REG (CSR_DFX_GLB_CSR_BASE + 0x638) +#define CSR_DFX_GLB_CSR_ICTL_DBL_SOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x640) +#define CSR_DFX_GLB_CSR_ICTL_DBL_EOP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x644) +#define CSR_DFX_GLB_CSR_DWQE_DROP_NO_WR_BUF_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x648) +#define CSR_DFX_GLB_CSR_DWQE_WR_BUF_COMPLETE_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x64C) +#define CSR_DFX_GLB_CSR_NORM_DBL_RX_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x690) +#define CSR_DFX_GLB_CSR_NORM_DBL_FORCE_DROP_REG (CSR_DFX_GLB_CSR_BASE + 0x694) +#define CSR_DFX_GLB_CSR_DWQE_RX_BUF_BGN_REG (CSR_DFX_GLB_CSR_BASE + 0x698) +#define CSR_DFX_GLB_CSR_DWQE_ILLEGAL_DROP_CNT_REG (CSR_DFX_GLB_CSR_BASE + 0x69C) +#define CSR_DFX_GLB_CSR_DWQE_DBL_FORCE_DROP_NO_API_REG (CSR_DFX_GLB_CSR_BASE + 0x6A0) +#define CSR_DFX_GLB_CSR_DWQE_DBL_FORCE_DROP_AFT_API_REG (CSR_DFX_GLB_CSR_BASE + 0x6A4) +#define CSR_DFX_GLB_CSR_AEQ_FSM_DBG_STATE_REG (CSR_DFX_GLB_CSR_BASE + 0x6A8) +#define CSR_DFX_GLB_CSR_GLB_UCPU_MSI_FUNC_IDX_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x6B0) /* the function index when ucpu access CSRs in the INT_CTL */ +#define CSR_DFX_GLB_CSR_GLB_PCIE_INBD_ITF_WIND_CTL_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x6B4) /* the control register to measure the inbound itf */ +#define CSR_DFX_GLB_CSR_GLB_PCIE_INBD_ITF_WIND_CNT_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x6B8) /* the result for the window detect for the mode */ +#define CSR_DFX_GLB_CSR_GLB_PCIE_INBD_ITF_WIND_TLP_CNT_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x6BC) /* the result for the window detect for the TLP */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CNT_DBL_GRP_EN_REG (CSR_DFX_GLB_CSR_BASE + 0x6C0) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_TIMER_CFG_REG (CSR_DFX_GLB_CSR_BASE + 0x6C4) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CFG_PORT01_REG (CSR_DFX_GLB_CSR_BASE + 0x6C8) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CFG_PORT23_REG (CSR_DFX_GLB_CSR_BASE + 0x6CC) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT0_REG (CSR_DFX_GLB_CSR_BASE + 0x6D0) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT1_REG (CSR_DFX_GLB_CSR_BASE + 0x6D4) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT2_REG (CSR_DFX_GLB_CSR_BASE + 0x6D8) +#define CSR_DFX_GLB_CSR_GLB_DBL_CRD_CNT_PORT3_REG (CSR_DFX_GLB_CSR_BASE + 0x6DC) +#define CSR_DFX_GLB_CSR_CPATH_ENJ_A_FATAL_MSK_REG (CSR_DFX_GLB_CSR_BASE + 0x700) +#define CSR_DFX_GLB_CSR_CPATH_ENJ_A_NONFATAL_MSK_REG (CSR_DFX_GLB_CSR_BASE + 0x704) +#define CSR_DFX_GLB_CSR_CPATH_ENJ_FIFO_AFUL_TH_REG (CSR_DFX_GLB_CSR_BASE + 0x708) +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT0_REG (CSR_DFX_GLB_CSR_BASE + 0x710) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT1_REG (CSR_DFX_GLB_CSR_BASE + 0x714) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT2_REG (CSR_DFX_GLB_CSR_BASE + 0x718) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT3_REG (CSR_DFX_GLB_CSR_BASE + 0x71C) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT4_REG (CSR_DFX_GLB_CSR_BASE + 0x720) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT5_REG (CSR_DFX_GLB_CSR_BASE + 0x724) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT6_REG (CSR_DFX_GLB_CSR_BASE + 0x728) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_CNT7_REG (CSR_DFX_GLB_CSR_BASE + 0x72C) /* CPATH_ENJ模块的dfx寄存器 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO0_REG (CSR_DFX_GLB_CSR_BASE + 0x730) /* CPATH内下RING FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO1_REG (CSR_DFX_GLB_CSR_BASE + 0x734) /* CPATH内下RING FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO2_REG (CSR_DFX_GLB_CSR_BASE + 0x738) /* CPATH内上RING FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO3_REG \ + (CSR_DFX_GLB_CSR_BASE + 0x73C) /* CPATH内ICPL返回完成包接口FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO4_REG (CSR_DFX_GLB_CSR_BASE + 0x740) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO5_REG (CSR_DFX_GLB_CSR_BASE + 0x744) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO6_REG (CSR_DFX_GLB_CSR_BASE + 0x748) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO7_REG (CSR_DFX_GLB_CSR_BASE + 0x74C) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO8_REG (CSR_DFX_GLB_CSR_BASE + 0x750) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_ENJ_FIFO9_REG (CSR_DFX_GLB_CSR_BASE + 0x754) /* CPATH内FIFO状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO0_REG (CSR_DFX_GLB_CSR_BASE + 0x758) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO1_REG (CSR_DFX_GLB_CSR_BASE + 0x75C) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO2_REG (CSR_DFX_GLB_CSR_BASE + 0x760) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO3_REG (CSR_DFX_GLB_CSR_BASE + 0x764) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO4_REG (CSR_DFX_GLB_CSR_BASE + 0x768) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO5_REG (CSR_DFX_GLB_CSR_BASE + 0x76C) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO6_REG (CSR_DFX_GLB_CSR_BASE + 0x770) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO7_REG (CSR_DFX_GLB_CSR_BASE + 0x774) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO8_REG (CSR_DFX_GLB_CSR_BASE + 0x778) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO9_REG (CSR_DFX_GLB_CSR_BASE + 0x77C) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO10_REG (CSR_DFX_GLB_CSR_BASE + 0x780) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO11_REG (CSR_DFX_GLB_CSR_BASE + 0x784) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO12_REG (CSR_DFX_GLB_CSR_BASE + 0x788) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_GLB_DBG_CPATH_RO13_REG (CSR_DFX_GLB_CSR_BASE + 0x78C) /* CPATH内实时状态 */ +#define CSR_DFX_GLB_CSR_CPATH_ENJ_PLS_REG (CSR_DFX_GLB_CSR_BASE + 0x7A0) +#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS0_REG (CSR_DFX_GLB_CSR_BASE + 0x7B0) /* ctrl_bus配置值，软件不要改。 */ +#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS1_REG (CSR_DFX_GLB_CSR_BASE + 0x7B4) /* ctrl_bus配置值，软件不要改。 */ +#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS2_REG (CSR_DFX_GLB_CSR_BASE + 0x7B8) /* ctrl_bus配置值，软件不要改。 */ +#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS3_REG (CSR_DFX_GLB_CSR_BASE + 0x7BC) /* ctrl_bus配置值，软件不要改。 */ +#define CSR_DFX_GLB_CSR_CTRL_MEM_CTRL_BUS4_REG (CSR_DFX_GLB_CSR_BASE + 0x7C0) /* ctrl_bus配置值，软件不要改。 */ +#define CSR_DFX_GLB_CSR_CTRL_TCAM_CTRL_BUS0_REG (CSR_DFX_GLB_CSR_BASE + 0x7C4) /* ctrl_bus配置值，软件不要改。 */ + +/* dfx_ctrl_top_csr Base address of Module's Register */ +#define CSR_DFX_CTRL_TOP_CSR_BASE (0x43AF800) + +/* **************************************************************************** */ +/* dfx_ctrl_top_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x0) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_ARB_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x8) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x10) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x14) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x18) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x20) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x24) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x28) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x30) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x34) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x38) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_12_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x3C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_13_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x40) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_14_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x44) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_15_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x48) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_16_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_17_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x50) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_18_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x54) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_19_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x58) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_20_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x5C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_21_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x60) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_22_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x64) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_23_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x68) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_24_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_25_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x70) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_26_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x74) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_27_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x78) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_28_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x7C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_29_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x80) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_30_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x84) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_31_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x88) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_32_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x8C) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_33_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x90) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_DFX_CNT_34_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x94) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DTIF_ERR_PLS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xA0) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DTIF_FATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xA4) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DTIF_NONFATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xA8) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO0_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xB0) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO1_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xB4) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO2_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xB8) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO3_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xBC) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO4_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC0) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO5_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC4) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO6_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xC8) +#define CSR_DFX_CTRL_TOP_CSR_DTIF_FIFO7_STS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0xCC) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_FIFO_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x100) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_ARB_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x108) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x110) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x114) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x118) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x11C) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x120) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x124) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x128) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x12C) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x130) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x134) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x138) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_QMAP_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x13C) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DB_ARB_QMAP_ERR_PLS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x150) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DB_ARB_QMAP_FATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x154) +#define CSR_DFX_CTRL_TOP_CSR_DFX_DB_ARB_QMAP_NONFATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x158) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_RO_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x180) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_RO_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x184) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_20_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x198) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_21_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x19C) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1A0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1A4) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1A8) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1AC) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1B0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1B4) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1B8) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1BC) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C4) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1C8) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1CC) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_12_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1D0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_13_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1D4) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_14_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1D8) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_15_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1DC) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_16_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1E0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_17_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1E4) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_18_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1E8) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_DFX_CNT_19_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1EC) +#define CSR_DFX_CTRL_TOP_CSR_DFX_CTL_MISC_ERR_PLS_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1F0) +#define CSR_DFX_CTRL_TOP_CSR_DFX_CTL_MISC_FATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1F4) +#define CSR_DFX_CTRL_TOP_CSR_DFX_CTL_MISC_NONFATAL_MSK_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x1F8) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x200) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x204) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x208) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_3_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x20C) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_4_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x210) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_5_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x214) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_6_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x218) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_7_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x21C) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_8_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x220) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_9_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x224) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_10_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x228) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CNT_11_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x22C) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_FIFO_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x280) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_FIFO_STS_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x290) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_STS_RO_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x294) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_DFX_CNT_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2A0) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_DFX_CNT_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2A4) +#define CSR_DFX_CTRL_TOP_CSR_CPL_CTL_DFX_CNT_2_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x2A8) +#define CSR_DFX_CTRL_TOP_CSR_DB_ARB_WEIGHT_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x400) +#define CSR_DFX_CTRL_TOP_CSR_OSCH_DB_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x404) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_DB_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x408) +#define CSR_DFX_CTRL_TOP_CSR_DWQE_DB_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x40C) +#define CSR_DFX_CTRL_TOP_CSR_QMAP_TCAM_RSVD_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x410) +#define CSR_DFX_CTRL_TOP_CSR_NVME_DB_COS_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x440) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_DB_COS_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x444) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x448) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_CFG_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x44C) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_ITF_DFX_STS0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x490) +#define CSR_DFX_CTRL_TOP_CSR_VIO_FLR_DLY_TIMER_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x498) +#define CSR_DFX_CTRL_TOP_CSR_VIO_FLR_DLY_TIMER_UNIT_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x49C) +#define CSR_DFX_CTRL_TOP_CSR_VIO_FLR_ENABLE_DLY_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4A0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_MCTP_RX_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4B0) +#define CSR_DFX_CTRL_TOP_CSR_IB_MISC_PCIE_ITF_CFG_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x4B4) +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_RSVD_Q_CFG_0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x500) /* VIRTIO缺省队列配置 */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_RSVD_Q_CFG_1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x504) /* VIRTIO缺省队列配置 */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_COS_SQ_CFG0_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6A0) /* 三网合一功能的cos配置 */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_COS_SQ_CFG1_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6A4) /* 三网合一功能的cos配置 */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_COS_SQ_RP_EN_ALL_REG \ + (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6A8) /* 三网合一时替换使能cos功能 */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_DIRECT_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6AC) /* 将满水线DFX */ +#define CSR_DFX_CTRL_TOP_CSR_VIRTIO_API_FIFO_AF_TH_REG (CSR_DFX_CTRL_TOP_CSR_BASE + 0x6B0) /* 将满水线DFX */ + +/* dfx_cpath_csr Base address of Module's Register */ +#define CSR_DFX_CPATH_CSR_BASE (0x43B0800) + +/* **************************************************************************** */ +/* dfx_cpath_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_DFX_CPATH_CSR_CPATH_CSR_INJ_ENJ_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x10) +#define CSR_DFX_CPATH_CSR_CPATH_INBD_INJ_ENJ_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x14) +#define CSR_DFX_CPATH_CSR_CPATH_NON_CPI_INT_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x1C) +#define CSR_DFX_CPATH_CSR_CPATH_ENJ_RSVD_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x20) +#define CSR_DFX_CPATH_CSR_CPATH_ENJ_NML_CNT_REG (CSR_DFX_CPATH_CSR_BASE + 0x24) +#define CSR_DFX_CPATH_CSR_CPATH_INBD_OUBD_CNT_TYPE_REG (CSR_DFX_CPATH_CSR_BASE + 0x2C) +#define CSR_DFX_CPATH_CSR_CPATH_FIFO_AFUL_GAP_0_REG (CSR_DFX_CPATH_CSR_BASE + 0x30) +#define CSR_DFX_CPATH_CSR_CPATH_RESERVD_REG (CSR_DFX_CPATH_CSR_BASE + 0x3C) /* ECO保留 */ +#define CSR_DFX_CPATH_CSR_CPATH_ITF_STS_OUT_REG (CSR_DFX_CPATH_CSR_BASE + 0x44) +#define CSR_DFX_CPATH_CSR_CPATH_CSR_SFIFO_PE1_REG (CSR_DFX_CPATH_CSR_BASE + 0x4C) +#define CSR_DFX_CPATH_CSR_CPATH_CSR_SFIFO_PE0_REG (CSR_DFX_CPATH_CSR_BASE + 0x50) +#define CSR_DFX_CPATH_CSR_CPATH_CSR_SFIFO_PI_REG (CSR_DFX_CPATH_CSR_BASE + 0x54) +#define CSR_DFX_CPATH_CSR_CPATH_INBD_SFIFO_PE1_REG (CSR_DFX_CPATH_CSR_BASE + 0x58) +#define CSR_DFX_CPATH_CSR_CPATH_INBD_SFIFO_PE0_REG (CSR_DFX_CPATH_CSR_BASE + 0x5C) +#define CSR_DFX_CPATH_CSR_CPATH_INBD_SFIFO_PI_REG (CSR_DFX_CPATH_CSR_BASE + 0x60) +#define CSR_DFX_CPATH_CSR_CPATH_OUT_PLS_REG (CSR_DFX_CPATH_CSR_BASE + 0x70) +#define CSR_DFX_CPATH_CSR_GLB_IJT_NODE_ID_BITMAP_REG (CSR_DFX_CPATH_CSR_BASE + 0x80) +#define CSR_DFX_CPATH_CSR_GLB_EJT_NODE_ID_BITMAP_REG (CSR_DFX_CPATH_CSR_BASE + 0x84) +#define CSR_DFX_CPATH_CSR_CPATH_OUT_A_FATAL_MSK_REG (CSR_DFX_CPATH_CSR_BASE + 0x100) +#define CSR_DFX_CPATH_CSR_CPATH_OUT_A_NONFATAL_MSK_REG (CSR_DFX_CPATH_CSR_BASE + 0x104) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK0_REG (CSR_DFX_CPATH_CSR_BASE + 0x110) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK1_REG (CSR_DFX_CPATH_CSR_BASE + 0x114) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK2_REG (CSR_DFX_CPATH_CSR_BASE + 0x118) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK3_REG (CSR_DFX_CPATH_CSR_BASE + 0x11C) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK4_REG (CSR_DFX_CPATH_CSR_BASE + 0x120) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK5_REG (CSR_DFX_CPATH_CSR_BASE + 0x124) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK6_REG (CSR_DFX_CPATH_CSR_BASE + 0x128) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK7_REG (CSR_DFX_CPATH_CSR_BASE + 0x12C) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK8_REG (CSR_DFX_CPATH_CSR_BASE + 0x130) +#define CSR_DFX_CPATH_CSR_DFX_CPATH_PE_RSP_LCK9_REG (CSR_DFX_CPATH_CSR_BASE + 0x134) + +/* dfx_apictl_csr Base address of Module's Register */ +#define CSR_DFX_APICTL_CSR_BASE (0x43B2000) + +/* **************************************************************************** */ +/* dfx_apictl_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_DFX_APICTL_CSR_APICTL_DBG_SEL_REG (CSR_DFX_APICTL_CSR_BASE + 0x0) +#define CSR_DFX_APICTL_CSR_APICTL_AF_TH0_REG (CSR_DFX_APICTL_CSR_BASE + 0x4) +#define CSR_DFX_APICTL_CSR_APICTL_AF_TH1_REG (CSR_DFX_APICTL_CSR_BASE + 0x8) +#define CSR_DFX_APICTL_CSR_APICTL_AF_TH2_REG (CSR_DFX_APICTL_CSR_BASE + 0xC) +#define CSR_DFX_APICTL_CSR_APICTL_AF_TH3_REG (CSR_DFX_APICTL_CSR_BASE + 0x10) +#define CSR_DFX_APICTL_CSR_APICTL_CNT2_REG (CSR_DFX_APICTL_CSR_BASE + 0x18) +#define CSR_DFX_APICTL_CSR_APICTL_CNT3_REG (CSR_DFX_APICTL_CSR_BASE + 0x1C) +#define CSR_DFX_APICTL_CSR_APICTL_CNT4_REG (CSR_DFX_APICTL_CSR_BASE + 0x20) +#define CSR_DFX_APICTL_CSR_APICTL_CNT5_REG (CSR_DFX_APICTL_CSR_BASE + 0x24) +#define CSR_DFX_APICTL_CSR_APICTL_CNT6_REG (CSR_DFX_APICTL_CSR_BASE + 0x28) +#define CSR_DFX_APICTL_CSR_APICTL_RESERVD_REG (CSR_DFX_APICTL_CSR_BASE + 0x2C) /* ECO保留 */ +#define CSR_DFX_APICTL_CSR_APICTL_OUT_A_PLS_REG (CSR_DFX_APICTL_CSR_BASE + 0x30) +#define CSR_DFX_APICTL_CSR_APICTL_OUT_B_PLS_REG (CSR_DFX_APICTL_CSR_BASE + 0x34) +#define CSR_DFX_APICTL_CSR_APICTL_NON_CSR_TIMER_TH_REG (CSR_DFX_APICTL_CSR_BASE + 0x38) +#define CSR_DFX_APICTL_CSR_APICTL_CSR_TIMER_TH_REG (CSR_DFX_APICTL_CSR_BASE + 0x3C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_A_REG (CSR_DFX_APICTL_CSR_BASE + 0x40) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_B_REG (CSR_DFX_APICTL_CSR_BASE + 0x44) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_C_REG (CSR_DFX_APICTL_CSR_BASE + 0x48) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_D_REG (CSR_DFX_APICTL_CSR_BASE + 0x4C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_E_REG (CSR_DFX_APICTL_CSR_BASE + 0x50) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_F_REG (CSR_DFX_APICTL_CSR_BASE + 0x54) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_G_REG (CSR_DFX_APICTL_CSR_BASE + 0x58) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_H_REG (CSR_DFX_APICTL_CSR_BASE + 0x5C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_I_REG (CSR_DFX_APICTL_CSR_BASE + 0x60) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_J_REG (CSR_DFX_APICTL_CSR_BASE + 0x64) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_K_REG (CSR_DFX_APICTL_CSR_BASE + 0x68) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_L_REG (CSR_DFX_APICTL_CSR_BASE + 0x6C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_M_REG (CSR_DFX_APICTL_CSR_BASE + 0x70) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_N_REG (CSR_DFX_APICTL_CSR_BASE + 0x74) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_O_REG (CSR_DFX_APICTL_CSR_BASE + 0x78) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_P_REG (CSR_DFX_APICTL_CSR_BASE + 0x7C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_Q_REG (CSR_DFX_APICTL_CSR_BASE + 0x80) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_R_REG (CSR_DFX_APICTL_CSR_BASE + 0x84) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_S_REG (CSR_DFX_APICTL_CSR_BASE + 0x88) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_T_REG (CSR_DFX_APICTL_CSR_BASE + 0x8C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_U_REG (CSR_DFX_APICTL_CSR_BASE + 0x90) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_V_REG (CSR_DFX_APICTL_CSR_BASE + 0x94) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_W_REG (CSR_DFX_APICTL_CSR_BASE + 0x98) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_X_REG (CSR_DFX_APICTL_CSR_BASE + 0x9C) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_Y_REG (CSR_DFX_APICTL_CSR_BASE + 0xA0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_OUT_Z_REG (CSR_DFX_APICTL_CSR_BASE + 0xA4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_A_REG (CSR_DFX_APICTL_CSR_BASE + 0xB0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_B_REG (CSR_DFX_APICTL_CSR_BASE + 0xB4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_C_REG (CSR_DFX_APICTL_CSR_BASE + 0xB8) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_D_REG (CSR_DFX_APICTL_CSR_BASE + 0xBC) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_E_REG (CSR_DFX_APICTL_CSR_BASE + 0xC0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_F_REG (CSR_DFX_APICTL_CSR_BASE + 0xC4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_G_REG (CSR_DFX_APICTL_CSR_BASE + 0xC8) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_H_REG (CSR_DFX_APICTL_CSR_BASE + 0xCC) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_I_REG (CSR_DFX_APICTL_CSR_BASE + 0xD0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_J_REG (CSR_DFX_APICTL_CSR_BASE + 0xD4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_K_REG (CSR_DFX_APICTL_CSR_BASE + 0xD8) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_L_REG (CSR_DFX_APICTL_CSR_BASE + 0xDC) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_M_REG (CSR_DFX_APICTL_CSR_BASE + 0xE0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_N_REG (CSR_DFX_APICTL_CSR_BASE + 0xE4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_O_REG (CSR_DFX_APICTL_CSR_BASE + 0xE8) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_P_REG (CSR_DFX_APICTL_CSR_BASE + 0xEC) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_Q_REG (CSR_DFX_APICTL_CSR_BASE + 0xF0) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_R_REG (CSR_DFX_APICTL_CSR_BASE + 0xF4) +#define CSR_DFX_APICTL_CSR_APICTL_DBG_FIFO_S_REG (CSR_DFX_APICTL_CSR_BASE + 0xF8) +#define CSR_DFX_APICTL_CSR_INBD_RING_BUF_CRDT_REG \ + (CSR_DFX_APICTL_CSR_BASE + 0x108) /* inbound API到uP侧的非bypass ring buffer 信用控制寄存器 */ +#define CSR_DFX_APICTL_CSR_INBD_CMD_RD_SO_RO_REG \ + (CSR_DFX_APICTL_CSR_BASE + 0x10C) /* API chain发送到host侧的读写命令SO/RO控制寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_RO_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x110) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_RO_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x114) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x118) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x11C) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_2_REG (CSR_DFX_APICTL_CSR_BASE + 0x120) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_3_REG (CSR_DFX_APICTL_CSR_BASE + 0x124) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_4_REG (CSR_DFX_APICTL_CSR_BASE + 0x128) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_5_REG (CSR_DFX_APICTL_CSR_BASE + 0x12C) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_6_REG (CSR_DFX_APICTL_CSR_BASE + 0x130) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_7_REG (CSR_DFX_APICTL_CSR_BASE + 0x134) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_8_REG (CSR_DFX_APICTL_CSR_BASE + 0x138) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_9_REG (CSR_DFX_APICTL_CSR_BASE + 0x13C) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_10_REG (CSR_DFX_APICTL_CSR_BASE + 0x140) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_11_REG (CSR_DFX_APICTL_CSR_BASE + 0x144) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_12_REG (CSR_DFX_APICTL_CSR_BASE + 0x148) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_13_REG (CSR_DFX_APICTL_CSR_BASE + 0x14C) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_TILEP_DFX_CNT_14_REG (CSR_DFX_APICTL_CSR_BASE + 0x150) /* TILE代理模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_RO_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x180) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_RO_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x184) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_0_REG (CSR_DFX_APICTL_CSR_BASE + 0x188) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_1_REG (CSR_DFX_APICTL_CSR_BASE + 0x18C) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_2_REG (CSR_DFX_APICTL_CSR_BASE + 0x190) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_3_REG (CSR_DFX_APICTL_CSR_BASE + 0x194) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_4_REG (CSR_DFX_APICTL_CSR_BASE + 0x198) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_5_REG (CSR_DFX_APICTL_CSR_BASE + 0x19C) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_6_REG (CSR_DFX_APICTL_CSR_BASE + 0x1A0) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_7_REG (CSR_DFX_APICTL_CSR_BASE + 0x1A4) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_8_REG (CSR_DFX_APICTL_CSR_BASE + 0x1A8) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_9_REG (CSR_DFX_APICTL_CSR_BASE + 0x1AC) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_10_REG (CSR_DFX_APICTL_CSR_BASE + 0x1B0) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_11_REG (CSR_DFX_APICTL_CSR_BASE + 0x1B4) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_12_REG (CSR_DFX_APICTL_CSR_BASE + 0x1B8) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_NL2_DFX_CNT_13_REG (CSR_DFX_APICTL_CSR_BASE + 0x1BC) /* NL2模块DFX寄存器 */ +#define CSR_DFX_APICTL_CSR_APICTL_OUT_A_FATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x200) +#define CSR_DFX_APICTL_CSR_APICTL_OUT_B_FATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x204) +#define CSR_DFX_APICTL_CSR_APICTL_OUT_A_NONFATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x210) +#define CSR_DFX_APICTL_CSR_APICTL_OUT_B_NONFATAL_MSK_REG (CSR_DFX_APICTL_CSR_BASE + 0x214) +#define CSR_DFX_APICTL_CSR_GLB_API_CHN_RIGHT_CTL0_REG (CSR_DFX_APICTL_CSR_BASE + 0x220) /* api chain权限控制 */ +#define CSR_DFX_APICTL_CSR_GLB_API_CHN_RIGHT_CTL1_REG (CSR_DFX_APICTL_CSR_BASE + 0x224) /* api chain权限控制 */ +#define CSR_DFX_APICTL_CSR_GLB_API_CHN_RIGHT_CTL2_REG (CSR_DFX_APICTL_CSR_BASE + 0x228) /* api chain权限控制 */ +#define CSR_DFX_APICTL_CSR_APICTL_TAG_CMP_TH_REG (CSR_DFX_APICTL_CSR_BASE + 0x230) +#define CSR_DFX_APICTL_CSR_APIITF_DFX_CNT0_REG (CSR_DFX_APICTL_CSR_BASE + 0x240) +#define CSR_DFX_APICTL_CSR_APIITF_DFX_CNT1_REG (CSR_DFX_APICTL_CSR_BASE + 0x244) +#define CSR_DFX_APICTL_CSR_APIITF_DFX_CNT2_REG (CSR_DFX_APICTL_CSR_BASE + 0x248) +#define CSR_DFX_APICTL_CSR_APIITF_RING_DEST_ILLG_SRC_REG (CSR_DFX_APICTL_CSR_BASE + 0x24C) + +/* CPI_DMA_CSR Base address of Module's Register */ +#define CSR_CPI_DMA_CSR_BASE (0x43B3000) + +/* **************************************************************************** */ +/* CPI_DMA_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPI_DMA_CSR_DMA_INDRECT_CTRL_REG (CSR_CPI_DMA_CSR_BASE + 0x0) /* CPI DMA 中间接访控制寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_TIMEOUT_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x4) /* dma Indirect Access Timeout Register。 */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_0_REG (CSR_CPI_DMA_CSR_BASE + 0x8) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_1_REG (CSR_CPI_DMA_CSR_BASE + 0xC) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_2_REG (CSR_CPI_DMA_CSR_BASE + 0x10) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_3_REG (CSR_CPI_DMA_CSR_BASE + 0x14) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_4_REG (CSR_CPI_DMA_CSR_BASE + 0x18) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_5_REG (CSR_CPI_DMA_CSR_BASE + 0x1C) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_6_REG (CSR_CPI_DMA_CSR_BASE + 0x20) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_DMA_INDRECT_DATA_7_REG (CSR_CPI_DMA_CSR_BASE + 0x24) /* dma Indirect Access Data Register */ +#define CSR_CPI_DMA_CSR_CPI_DMA_RAM_TMODE_REG (CSR_CPI_DMA_CSR_BASE + 0x40) /* CPI internal RAM test mode */ +#define CSR_CPI_DMA_CSR_MSI_BAR_OFFSET_REG (CSR_CPI_DMA_CSR_BASE + 0x44) /* 表示配置MSI bar的偏移。 */ +#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_0_REG (CSR_CPI_DMA_CSR_BASE + 0x50) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_1_REG (CSR_CPI_DMA_CSR_BASE + 0x60) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_2_REG (CSR_CPI_DMA_CSR_BASE + 0x70) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_3_REG (CSR_CPI_DMA_CSR_BASE + 0x80) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_PF_RANGE_PORT_4_REG (CSR_CPI_DMA_CSR_BASE + 0x90) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_0_REG (CSR_CPI_DMA_CSR_BASE + 0x54) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_1_REG (CSR_CPI_DMA_CSR_BASE + 0x64) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_2_REG (CSR_CPI_DMA_CSR_BASE + 0x74) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_3_REG (CSR_CPI_DMA_CSR_BASE + 0x84) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_VF_RANGE_PORT_4_REG (CSR_CPI_DMA_CSR_BASE + 0x94) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_0_REG (CSR_CPI_DMA_CSR_BASE + 0x58) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_1_REG (CSR_CPI_DMA_CSR_BASE + 0x68) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_2_REG (CSR_CPI_DMA_CSR_BASE + 0x78) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_3_REG (CSR_CPI_DMA_CSR_BASE + 0x88) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_LVF_RANGE_PORT_4_REG (CSR_CPI_DMA_CSR_BASE + 0x98) /* PF和端口映射寄存器 */ +#define CSR_CPI_DMA_CSR_CEQ_NUM_ACC_WEIGHT_REG (CSR_CPI_DMA_CSR_BASE + 0xB0) /* CEQ 分配RAM访问权重寄存器 */ +#define CSR_CPI_DMA_CSR_COPY_EP_2_COS_EN_REG (CSR_CPI_DMA_CSR_BASE + 0xB4) /* 第五host copyEP到COS 使能寄存器。 */ +#define CSR_CPI_DMA_CSR_DMA_ATTR_NUM_REG (CSR_CPI_DMA_CSR_BASE + 0xB8) /* CPI内DMA属性配置寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_0_REG (CSR_CPI_DMA_CSR_BASE + 0xBC) /* DMA控制寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_RAM_INIT_REG (CSR_CPI_DMA_CSR_BASE + 0xC0) /* DMA侧ram初始化寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_RAM_STATUS_REG (CSR_CPI_DMA_CSR_BASE + 0xC4) /* DMA侧ram初始化状态寄存器 */ +#define CSR_CPI_DMA_CSR_PCIE_TIMEOUT_REG (CSR_CPI_DMA_CSR_BASE + 0xD0) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_PCIE_TAG_FORCE_REG (CSR_CPI_DMA_CSR_BASE + 0xD4) /* 强制回收某PF/VF的读命令 */ +#define CSR_CPI_DMA_CSR_PCIE_TAG_FORCE_ITF_REG (CSR_CPI_DMA_CSR_BASE + 0xD8) /* 强制回收某PCIe端口的读命令 */ +#define CSR_CPI_DMA_CSR_TIMEOUT_DLY_CFG_REG (CSR_CPI_DMA_CSR_BASE + 0xDC) /* 配置超时tag重复利用的静默时间 */ +#define CSR_CPI_DMA_CSR_PCIE_CFG_MOD_REG (CSR_CPI_DMA_CSR_BASE + 0xE0) /* 表示CPI使用pcie 配置空间的模式 */ +#define CSR_CPI_DMA_CSR_PCIE_CFG_LOC_SET_REG (CSR_CPI_DMA_CSR_BASE + 0xE4) /* 表示CPI使用pcie 配置空间的模式 */ +#define CSR_CPI_DMA_CSR_SPU_CFG_LOC_SET_REG (CSR_CPI_DMA_CSR_BASE + 0xE8) /* 表示CPI使用SPU侧pcie 配置空间的模式 */ +#define CSR_CPI_DMA_CSR_DMA_TOP_ECO0_REG (CSR_CPI_DMA_CSR_BASE + 0xEC) /* DMATOP保留寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_TOP_ECO1_REG (CSR_CPI_DMA_CSR_BASE + 0xF0) /* DMATOP保留寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_TOP_ECO2_REG (CSR_CPI_DMA_CSR_BASE + 0xF4) /* DMATOP保留寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_TOP_ECO3_REG (CSR_CPI_DMA_CSR_BASE + 0xF8) /* DMATOP保留寄存器 */ +#define CSR_CPI_DMA_CSR_DMA_TOP_ECO4_REG (CSR_CPI_DMA_CSR_BASE + 0xFC) /* DMATOP保留寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_0_REG (CSR_CPI_DMA_CSR_BASE + 0x100) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_1_REG (CSR_CPI_DMA_CSR_BASE + 0x120) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_2_REG (CSR_CPI_DMA_CSR_BASE + 0x140) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_3_REG (CSR_CPI_DMA_CSR_BASE + 0x160) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE0_4_REG (CSR_CPI_DMA_CSR_BASE + 0x180) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_0_REG (CSR_CPI_DMA_CSR_BASE + 0x104) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_1_REG (CSR_CPI_DMA_CSR_BASE + 0x124) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_2_REG (CSR_CPI_DMA_CSR_BASE + 0x144) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_3_REG (CSR_CPI_DMA_CSR_BASE + 0x164) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE1_4_REG (CSR_CPI_DMA_CSR_BASE + 0x184) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_0_REG (CSR_CPI_DMA_CSR_BASE + 0x108) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_1_REG (CSR_CPI_DMA_CSR_BASE + 0x128) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_2_REG (CSR_CPI_DMA_CSR_BASE + 0x148) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_3_REG (CSR_CPI_DMA_CSR_BASE + 0x168) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE2_4_REG (CSR_CPI_DMA_CSR_BASE + 0x188) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_0_REG (CSR_CPI_DMA_CSR_BASE + 0x10C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_1_REG (CSR_CPI_DMA_CSR_BASE + 0x12C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_2_REG (CSR_CPI_DMA_CSR_BASE + 0x14C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_3_REG (CSR_CPI_DMA_CSR_BASE + 0x16C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE5_4_REG (CSR_CPI_DMA_CSR_BASE + 0x18C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_0_REG (CSR_CPI_DMA_CSR_BASE + 0x110) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_1_REG (CSR_CPI_DMA_CSR_BASE + 0x130) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_2_REG (CSR_CPI_DMA_CSR_BASE + 0x150) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_3_REG (CSR_CPI_DMA_CSR_BASE + 0x170) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE6_4_REG (CSR_CPI_DMA_CSR_BASE + 0x190) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_0_REG (CSR_CPI_DMA_CSR_BASE + 0x114) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_1_REG (CSR_CPI_DMA_CSR_BASE + 0x134) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_2_REG (CSR_CPI_DMA_CSR_BASE + 0x154) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_3_REG (CSR_CPI_DMA_CSR_BASE + 0x174) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE9_4_REG (CSR_CPI_DMA_CSR_BASE + 0x194) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_0_REG (CSR_CPI_DMA_CSR_BASE + 0x118) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_1_REG (CSR_CPI_DMA_CSR_BASE + 0x138) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_2_REG (CSR_CPI_DMA_CSR_BASE + 0x158) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_3_REG (CSR_CPI_DMA_CSR_BASE + 0x178) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUEA_4_REG (CSR_CPI_DMA_CSR_BASE + 0x198) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_0_REG (CSR_CPI_DMA_CSR_BASE + 0x11C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_1_REG (CSR_CPI_DMA_CSR_BASE + 0x13C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_2_REG (CSR_CPI_DMA_CSR_BASE + 0x15C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_3_REG (CSR_CPI_DMA_CSR_BASE + 0x17C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPL_TIMEOUT_VALUE_DIS_4_REG (CSR_CPI_DMA_CSR_BASE + 0x19C) /* CPI发送读命令超时配置寄存器 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT0_REG (CSR_CPI_DMA_CSR_BASE + 0x240) /* PDI 模块统计计数器0 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT1_REG (CSR_CPI_DMA_CSR_BASE + 0x244) /* PDI 模块统计计数器1 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT2_REG (CSR_CPI_DMA_CSR_BASE + 0x248) /* PDI 模块统计计数器2 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT3_REG (CSR_CPI_DMA_CSR_BASE + 0x24C) /* PDI 模块统计计数器3 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT4_REG (CSR_CPI_DMA_CSR_BASE + 0x250) /* PDI 模块统计计数器4 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT5_REG (CSR_CPI_DMA_CSR_BASE + 0x254) /* PDI 模块统计计数器5 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT6_REG (CSR_CPI_DMA_CSR_BASE + 0x258) /* PDI 模块统计计数器1 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT7_REG (CSR_CPI_DMA_CSR_BASE + 0x25C) /* PDI 模块统计计数器1 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT8_REG (CSR_CPI_DMA_CSR_BASE + 0x260) /* PDI 模块统计计数器1 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT9_REG (CSR_CPI_DMA_CSR_BASE + 0x264) /* PDI 模块统计计数器2 */ +#define CSR_CPI_DMA_CSR_PDI_TAG_CNT10_REG (CSR_CPI_DMA_CSR_BASE + 0x268) /* PDI 模块统计计数器2 */ +#define CSR_CPI_DMA_CSR_CEQ_BLK_CNT_REG (CSR_CPI_DMA_CSR_BASE + 0x2A0) /* CEQ 模块统计计数器 */ +#define CSR_CPI_DMA_CSR_CEQ_CSR_ST_REG (CSR_CPI_DMA_CSR_BASE + 0x2A4) /* CEQ 模块各状态寄存器 */ +#define CSR_CPI_DMA_CSR_FLR_RCV_CNT0_REG (CSR_CPI_DMA_CSR_BASE + 0x2B0) /* CPI接收FLR统计计数器 */ +#define CSR_CPI_DMA_CSR_FLR_RCV_CNT1_REG (CSR_CPI_DMA_CSR_BASE + 0x2B4) /* CPI接收FLR统计计数器 */ +#define CSR_CPI_DMA_CSR_FLR_RCV_CNT2_REG (CSR_CPI_DMA_CSR_BASE + 0x2B8) /* CPI接收FLR统计计数器 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS0_REG (CSR_CPI_DMA_CSR_BASE + 0x2E0) /* CTRL_BUS值，软件不要改 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS1_REG (CSR_CPI_DMA_CSR_BASE + 0x2E4) /* CTRL_BUS值，软件不要改 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS2_REG (CSR_CPI_DMA_CSR_BASE + 0x2E8) /* CTRL_BUS值，软件不要改 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS3_REG (CSR_CPI_DMA_CSR_BASE + 0x2EC) /* CTRL_BUS值，软件不要改 */ +#define CSR_CPI_DMA_CSR_DMA_CTRL_BUS4_REG (CSR_CPI_DMA_CSR_BASE + 0x2F0) /* CTRL_BUS值，软件不要改 */ +#define CSR_CPI_DMA_CSR_DMA_PCIE_INBD_ITF_WIND_CTL_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x300) /* the control register to measure the inbound itf */ +#define CSR_CPI_DMA_CSR_DMA_PCIE_INBD_ITF_WIND_CNT_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x304) /* the result for the window detect for the mode */ +#define CSR_CPI_DMA_CSR_DMA_PCIE_INBD_ITF_WIND_TLP_CNT_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x308) /* the result for the window detect for the TLP */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_0_REG (CSR_CPI_DMA_CSR_BASE + 0x340) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_1_REG (CSR_CPI_DMA_CSR_BASE + 0x344) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_2_REG (CSR_CPI_DMA_CSR_BASE + 0x348) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_3_REG (CSR_CPI_DMA_CSR_BASE + 0x34C) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_4_REG (CSR_CPI_DMA_CSR_BASE + 0x350) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_5_REG (CSR_CPI_DMA_CSR_BASE + 0x354) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_6_REG (CSR_CPI_DMA_CSR_BASE + 0x358) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_7_REG (CSR_CPI_DMA_CSR_BASE + 0x35C) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_8_REG (CSR_CPI_DMA_CSR_BASE + 0x360) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_9_REG (CSR_CPI_DMA_CSR_BASE + 0x364) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_10_REG (CSR_CPI_DMA_CSR_BASE + 0x368) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_11_REG (CSR_CPI_DMA_CSR_BASE + 0x36C) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_12_REG (CSR_CPI_DMA_CSR_BASE + 0x370) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_13_REG (CSR_CPI_DMA_CSR_BASE + 0x374) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_14_REG (CSR_CPI_DMA_CSR_BASE + 0x378) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_RCV_BME_STS_15_REG (CSR_CPI_DMA_CSR_BASE + 0x37C) /* CPI Recive the bme clear cfg */ +#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_SEL_REG (CSR_CPI_DMA_CSR_BASE + 0x380) /* select the tag timeout funciton */ +#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_CLEAR_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x384) /* clear the selected funciton tag timeout */ +#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_ST_OUT_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x388) /* read the selected funciton tag timeout */ +#define CSR_CPI_DMA_CSR_CPI_TAG_TIMEOUT_GROUP_ST_OUT_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x38C) /* read the selected funciton tag timeout */ +#define CSR_CPI_DMA_CSR_CPI_PDI_A_FATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3E0) /* PDI模块中断级别配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_PDI_A_NONFATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3E4) /* PDI模块中断级别配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_PDI_A_INT_PLS_REG (CSR_CPI_DMA_CSR_BASE + 0x3E8) /* PDI模块中断状态寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_PDI_B_FATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3F0) /* PDI模块中断级别配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_PDI_B_NONFATAL_MSK_REG (CSR_CPI_DMA_CSR_BASE + 0x3F4) /* PDI模块中断级别配置寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_PDI_B_INT_PLS_REG (CSR_CPI_DMA_CSR_BASE + 0x3F8) /* PDI模块中断状态寄存器 */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_EN_0_REG (CSR_CPI_DMA_CSR_BASE + 0x400) /* the enable for virtio capability */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_EN_1_REG (CSR_CPI_DMA_CSR_BASE + 0x404) /* the enable for virtio capability */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_EN_127_REG (CSR_CPI_DMA_CSR_BASE + 0x5FC) /* the enable for virtio capability \ + */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_00VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x600) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_01VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x604) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_02VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x608) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_03VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x60C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_04VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x610) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_05VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x614) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_06VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x618) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_07VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x61C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_08VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x620) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_09VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x630) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_10VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x634) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_11VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x638) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_12VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x63C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_13VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x640) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_14VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x644) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_15VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x648) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_16VALUE_PF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x64C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_00VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x680) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_01VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x684) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_02VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x688) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_03VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x68C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_04VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x690) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_05VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x694) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_06VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x698) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_07VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x69C) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_08VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6A0) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_09VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6B0) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_10VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6B4) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_11VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6B8) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_12VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6BC) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_13VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6C0) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_14VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6C4) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_15VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6C8) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_CPI_VIRTIO_CAP_16VALUE_VF_REG \ + (CSR_CPI_DMA_CSR_BASE + 0x6CC) /* the virtio Capability for VirtIO */ +#define CSR_CPI_DMA_CSR_DFX_DMATOP_RAM_ECC_CERR_REG (CSR_CPI_DMA_CSR_BASE + 0x700) +#define CSR_CPI_DMA_CSR_DFX_DMATOP_RAM_ECC_UCERR_REG (CSR_CPI_DMA_CSR_BASE + 0x704) +#define CSR_CPI_DMA_CSR_DFX_DMATOP_RAM_ERR_ADDR_REG (CSR_CPI_DMA_CSR_BASE + 0x708) +#define CSR_CPI_DMA_CSR_DMATOP_ECC_INJ_REQ_REG (CSR_CPI_DMA_CSR_BASE + 0x710) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_A_REG (CSR_CPI_DMA_CSR_BASE + 0x720) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_B_REG (CSR_CPI_DMA_CSR_BASE + 0x724) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_C_REG (CSR_CPI_DMA_CSR_BASE + 0x728) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_D_REG (CSR_CPI_DMA_CSR_BASE + 0x72C) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_E_REG (CSR_CPI_DMA_CSR_BASE + 0x730) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_F_REG (CSR_CPI_DMA_CSR_BASE + 0x734) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_G_REG (CSR_CPI_DMA_CSR_BASE + 0x738) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_H_REG (CSR_CPI_DMA_CSR_BASE + 0x73C) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_I_REG (CSR_CPI_DMA_CSR_BASE + 0x740) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_J_REG (CSR_CPI_DMA_CSR_BASE + 0x744) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_K_REG (CSR_CPI_DMA_CSR_BASE + 0x748) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_L_REG (CSR_CPI_DMA_CSR_BASE + 0x74C) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_M_REG (CSR_CPI_DMA_CSR_BASE + 0x750) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_N_REG (CSR_CPI_DMA_CSR_BASE + 0x754) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_O_REG (CSR_CPI_DMA_CSR_BASE + 0x758) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_P_REG (CSR_CPI_DMA_CSR_BASE + 0x75C) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_Q_REG (CSR_CPI_DMA_CSR_BASE + 0x760) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_R_REG (CSR_CPI_DMA_CSR_BASE + 0x764) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_S_REG (CSR_CPI_DMA_CSR_BASE + 0x768) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_T_REG (CSR_CPI_DMA_CSR_BASE + 0x76C) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_FIFO_ST_U_REG (CSR_CPI_DMA_CSR_BASE + 0x770) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_OUT_A_REG (CSR_CPI_DMA_CSR_BASE + 0x780) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_OUT_B_REG (CSR_CPI_DMA_CSR_BASE + 0x784) +#define CSR_CPI_DMA_CSR_DMATOP_DBG_OUT_C_REG (CSR_CPI_DMA_CSR_BASE + 0x788) + +/* CPI_ICPL_CSR Base address of Module's Register */ +#define CSR_CPI_ICPL_CSR_BASE (0x43B3800) + +/* **************************************************************************** */ +/* CPI_ICPL_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPI_ICPL_CSR_DP_NORMAL_CHL_EN_REG (CSR_CPI_ICPL_CSR_BASE + 0x0) /* 表示dpath普通channel使能寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_RAM_INIT_REG (CSR_CPI_ICPL_CSR_BASE + 0x44) /* DMA侧ram初始化寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_RAM_STATUS_REG (CSR_CPI_ICPL_CSR_BASE + 0x48) /* DMA侧ram初始化状态寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_FIFO_AFUL_CTL_REG (CSR_CPI_ICPL_CSR_BASE + 0x50) +#define CSR_CPI_ICPL_CSR_ICPL_FIFO_AFUL_CTL1_REG (CSR_CPI_ICPL_CSR_BASE + 0x54) +#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x100) /* 当前PCIe 端口分配TAG资源 */ +#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x120) /* 当前PCIe 端口分配TAG资源 */ +#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x140) /* 当前PCIe 端口分配TAG资源 */ +#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x160) /* 当前PCIe 端口分配TAG资源 */ +#define CSR_CPI_ICPL_CSR_ICPL_RES_CFG_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x180) /* 当前PCIe 端口分配TAG资源 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x104) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x124) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x144) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x164) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_CNT_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x184) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x108) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x128) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x148) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x168) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_PKT_CNT_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x188) /* 当前PCIe端口占用的TAG 数目 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x10C) /* 表示PCIe端口内TAG 最大值 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x12C) /* 表示PCIe端口内TAG 最大值 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x14C) /* 表示PCIe端口内TAG 最大值 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x16C) /* 表示PCIe端口内TAG 最大值 */ +#define CSR_CPI_ICPL_CSR_ICPL_TAG_BASE_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x18C) /* 表示PCIe端口内TAG 最大值 */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_0_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x110) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_1_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x130) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_2_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x150) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_3_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x170) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF0_4_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x190) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_0_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x114) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_1_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x134) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_2_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x154) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_3_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x174) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_RDR_BUF1_4_REG \ + (CSR_CPI_ICPL_CSR_BASE + 0x194) /* The reorder buffer configuration in the I_CPL */ +#define CSR_CPI_ICPL_CSR_ICPL_ARB_WEIGHT0_REG (CSR_CPI_ICPL_CSR_BASE + 0x1A0) /* ICPL内仲裁权重寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_ARB_WEIGHT1_REG (CSR_CPI_ICPL_CSR_BASE + 0x1A4) /* ICPL内仲裁权重寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_ARB_WEIGHT2_REG (CSR_CPI_ICPL_CSR_BASE + 0x1A8) /* ICPL内仲裁权重寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_CTRL_MOD_REG (CSR_CPI_ICPL_CSR_BASE + 0x1AC) /* ICPL内模式配置就存起 */ +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_SEL_REG (CSR_CPI_ICPL_CSR_BASE + 0x300) +#define CSR_CPI_ICPL_CSR_ICPL_RTT_CTL_REG (CSR_CPI_ICPL_CSR_BASE + 0x304) /* ICPL控制测量RTT的控制寄存器 */ +#define CSR_CPI_ICPL_CSR_ICPL_RTT_TAG_IDX0_REG (CSR_CPI_ICPL_CSR_BASE + 0x308) /* ICPL用于配置待测量的TAG 编号0。 */ +#define CSR_CPI_ICPL_CSR_ICPL_RTT_TAG_IDX1_REG (CSR_CPI_ICPL_CSR_BASE + 0x30C) /* ICPL用于配置待测量的TAG 编号1。 */ +#define CSR_CPI_ICPL_CSR_ICPL_RTT_TAG_IDX2_REG (CSR_CPI_ICPL_CSR_BASE + 0x310) /* ICPL用于配置待测量的TAG 编号2。 */ +#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG_CTL_REG (CSR_CPI_ICPL_CSR_BASE + 0x314) /* ICPL用于测量RTT范围的控制寄存器。 */ +#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG1_REG (CSR_CPI_ICPL_CSR_BASE + 0x318) +#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG2_REG (CSR_CPI_ICPL_CSR_BASE + 0x31C) +#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG3_REG (CSR_CPI_ICPL_CSR_BASE + 0x320) +#define CSR_CPI_ICPL_CSR_ICPL_RTT_RANG4_REG (CSR_CPI_ICPL_CSR_BASE + 0x324) +#define CSR_CPI_ICPL_CSR_ICPL_RTT_CUR_REG (CSR_CPI_ICPL_CSR_BASE + 0x328) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_A_REG (CSR_CPI_ICPL_CSR_BASE + 0x360) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_B_REG (CSR_CPI_ICPL_CSR_BASE + 0x364) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_C_REG (CSR_CPI_ICPL_CSR_BASE + 0x368) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_D_REG (CSR_CPI_ICPL_CSR_BASE + 0x36C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_E_REG (CSR_CPI_ICPL_CSR_BASE + 0x370) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_F_REG (CSR_CPI_ICPL_CSR_BASE + 0x374) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_G_REG (CSR_CPI_ICPL_CSR_BASE + 0x378) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_H_REG (CSR_CPI_ICPL_CSR_BASE + 0x37C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_I_REG (CSR_CPI_ICPL_CSR_BASE + 0x380) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_J_REG (CSR_CPI_ICPL_CSR_BASE + 0x384) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_K_REG (CSR_CPI_ICPL_CSR_BASE + 0x388) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_L_REG (CSR_CPI_ICPL_CSR_BASE + 0x38C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_M_REG (CSR_CPI_ICPL_CSR_BASE + 0x390) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_N_REG (CSR_CPI_ICPL_CSR_BASE + 0x394) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_O_REG (CSR_CPI_ICPL_CSR_BASE + 0x398) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_P_REG (CSR_CPI_ICPL_CSR_BASE + 0x39C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_Q_REG (CSR_CPI_ICPL_CSR_BASE + 0x3A0) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_R_REG (CSR_CPI_ICPL_CSR_BASE + 0x3A4) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_S_REG (CSR_CPI_ICPL_CSR_BASE + 0x3A8) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_T_REG (CSR_CPI_ICPL_CSR_BASE + 0x3AC) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_U_REG (CSR_CPI_ICPL_CSR_BASE + 0x3B0) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_V_REG (CSR_CPI_ICPL_CSR_BASE + 0x3B4) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_W_REG (CSR_CPI_ICPL_CSR_BASE + 0x3B8) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_X_REG (CSR_CPI_ICPL_CSR_BASE + 0x3BC) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_Y_REG (CSR_CPI_ICPL_CSR_BASE + 0x3C0) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_OUT_Z_REG (CSR_CPI_ICPL_CSR_BASE + 0x3C4) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x400) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x410) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x420) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x430) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x440) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x450) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x460) +#define CSR_CPI_ICPL_CSR_ICPL_DB_SEL_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x470) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x408) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x418) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x428) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x438) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x448) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x458) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x468) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT0_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x478) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x40C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x41C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x42C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x43C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x44C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x45C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x46C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT1_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x47C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT2_REG (CSR_CPI_ICPL_CSR_BASE + 0x480) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT3_REG (CSR_CPI_ICPL_CSR_BASE + 0x484) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT4_REG (CSR_CPI_ICPL_CSR_BASE + 0x488) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_CNT5_REG (CSR_CPI_ICPL_CSR_BASE + 0x48C) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_0_REG (CSR_CPI_ICPL_CSR_BASE + 0x490) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_1_REG (CSR_CPI_ICPL_CSR_BASE + 0x494) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_2_REG (CSR_CPI_ICPL_CSR_BASE + 0x498) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_3_REG (CSR_CPI_ICPL_CSR_BASE + 0x49C) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_4_REG (CSR_CPI_ICPL_CSR_BASE + 0x4A0) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_5_REG (CSR_CPI_ICPL_CSR_BASE + 0x4A4) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_6_REG (CSR_CPI_ICPL_CSR_BASE + 0x4A8) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_7_REG (CSR_CPI_ICPL_CSR_BASE + 0x4AC) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_8_REG (CSR_CPI_ICPL_CSR_BASE + 0x4B0) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_9_REG (CSR_CPI_ICPL_CSR_BASE + 0x4B4) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_10_REG (CSR_CPI_ICPL_CSR_BASE + 0x4B8) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_11_REG (CSR_CPI_ICPL_CSR_BASE + 0x4BC) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_12_REG (CSR_CPI_ICPL_CSR_BASE + 0x4C0) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_13_REG (CSR_CPI_ICPL_CSR_BASE + 0x4C4) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_14_REG (CSR_CPI_ICPL_CSR_BASE + 0x4C8) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_15_REG (CSR_CPI_ICPL_CSR_BASE + 0x4CC) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_16_REG (CSR_CPI_ICPL_CSR_BASE + 0x4D0) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_17_REG (CSR_CPI_ICPL_CSR_BASE + 0x4D4) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_18_REG (CSR_CPI_ICPL_CSR_BASE + 0x4D8) +#define CSR_CPI_ICPL_CSR_ICPL_CHL_CNT_19_REG (CSR_CPI_ICPL_CSR_BASE + 0x4DC) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_A_REG (CSR_CPI_ICPL_CSR_BASE + 0x500) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_B_REG (CSR_CPI_ICPL_CSR_BASE + 0x504) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_C_REG (CSR_CPI_ICPL_CSR_BASE + 0x508) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_D_REG (CSR_CPI_ICPL_CSR_BASE + 0x50C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_E_REG (CSR_CPI_ICPL_CSR_BASE + 0x510) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_F_REG (CSR_CPI_ICPL_CSR_BASE + 0x514) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_G_REG (CSR_CPI_ICPL_CSR_BASE + 0x518) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_H_REG (CSR_CPI_ICPL_CSR_BASE + 0x51C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_I_REG (CSR_CPI_ICPL_CSR_BASE + 0x520) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_J_REG (CSR_CPI_ICPL_CSR_BASE + 0x524) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_K_REG (CSR_CPI_ICPL_CSR_BASE + 0x528) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_L_REG (CSR_CPI_ICPL_CSR_BASE + 0x52C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_M_REG (CSR_CPI_ICPL_CSR_BASE + 0x530) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_N_REG (CSR_CPI_ICPL_CSR_BASE + 0x534) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_O_REG (CSR_CPI_ICPL_CSR_BASE + 0x538) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_P_REG (CSR_CPI_ICPL_CSR_BASE + 0x53C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_Q_REG (CSR_CPI_ICPL_CSR_BASE + 0x540) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_R_REG (CSR_CPI_ICPL_CSR_BASE + 0x544) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_S_REG (CSR_CPI_ICPL_CSR_BASE + 0x548) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_T_REG (CSR_CPI_ICPL_CSR_BASE + 0x54C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_U_REG (CSR_CPI_ICPL_CSR_BASE + 0x550) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_V_REG (CSR_CPI_ICPL_CSR_BASE + 0x554) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_W_REG (CSR_CPI_ICPL_CSR_BASE + 0x558) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_X_REG (CSR_CPI_ICPL_CSR_BASE + 0x55C) +#define CSR_CPI_ICPL_CSR_ICPL_DBG_FIFO_ST_Y_REG (CSR_CPI_ICPL_CSR_BASE + 0x560) +#define CSR_CPI_ICPL_CSR_ICPL_PLSA_FATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5E0) +#define CSR_CPI_ICPL_CSR_ICPL_PLSA_NONFATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5E4) +#define CSR_CPI_ICPL_CSR_ICPL_PLSA_REG (CSR_CPI_ICPL_CSR_BASE + 0x5E8) +#define CSR_CPI_ICPL_CSR_ICPL_PLSB_FATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5F0) +#define CSR_CPI_ICPL_CSR_ICPL_PLSB_NONFATAL_MSK_REG (CSR_CPI_ICPL_CSR_BASE + 0x5F4) +#define CSR_CPI_ICPL_CSR_ICPL_PLSB_REG (CSR_CPI_ICPL_CSR_BASE + 0x5F8) +#define CSR_CPI_ICPL_CSR_DFX_ICPL_RAM_ECC_CERR_REG (CSR_CPI_ICPL_CSR_BASE + 0x600) +#define CSR_CPI_ICPL_CSR_DFX_ICPL_RAM_ECC_UCERR_REG (CSR_CPI_ICPL_CSR_BASE + 0x604) +#define CSR_CPI_ICPL_CSR_DFX_ICPL_RAM_ERR_ADDR_REG (CSR_CPI_ICPL_CSR_BASE + 0x608) +#define CSR_CPI_ICPL_CSR_ICPL_ECC_INJ_REQ_REG (CSR_CPI_ICPL_CSR_BASE + 0x610) + +/* CPI_INTCTL_CSR Base address of Module's Register */ +#define CSR_CPI_INTCTL_CSR_BASE (0x43B4000) + +/* **************************************************************************** */ +/* CPI_INTCTL_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPI_INTCTL_CSR_INTCTL_INT_CTL_REG (CSR_CPI_INTCTL_CSR_BASE + 0x0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_BITMAP_REG (CSR_CPI_INTCTL_CSR_BASE + 0x8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_BITMAP_WNDW_REG (CSR_CPI_INTCTL_CSR_BASE + 0xC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_AB_REG (CSR_CPI_INTCTL_CSR_BASE + 0x10) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_CD_REG (CSR_CPI_INTCTL_CSR_BASE + 0x14) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_EF_REG (CSR_CPI_INTCTL_CSR_BASE + 0x18) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_GH_REG (CSR_CPI_INTCTL_CSR_BASE + 0x1C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_AB_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x20) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_CD_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x24) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_EF_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x28) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FUNC_IDX_GH_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_IPUSH_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x30) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_CFG_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x34) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_MSK_TRIG_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x38) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_COAL_CNT0_REG (CSR_CPI_INTCTL_CSR_BASE + 0x3C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_COAL_CNT1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x40) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_MSI_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x44) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_MSIX_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x48) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_VCT_CNT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x4C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_ASSERT_CNT0_REG (CSR_CPI_INTCTL_CSR_BASE + 0x50) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_ASSERT_CNT1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x54) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_DEASSERT_CNT0_REG (CSR_CPI_INTCTL_CSR_BASE + 0x58) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_INTX_DEASSERT_CNT1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x5C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_A_REG (CSR_CPI_INTCTL_CSR_BASE + 0x60) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_B_REG (CSR_CPI_INTCTL_CSR_BASE + 0x64) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_C_REG (CSR_CPI_INTCTL_CSR_BASE + 0x68) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_D_REG (CSR_CPI_INTCTL_CSR_BASE + 0x6C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_E_REG (CSR_CPI_INTCTL_CSR_BASE + 0x70) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_F_REG (CSR_CPI_INTCTL_CSR_BASE + 0x74) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_G_REG (CSR_CPI_INTCTL_CSR_BASE + 0x78) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_H_REG (CSR_CPI_INTCTL_CSR_BASE + 0x7C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_I_REG (CSR_CPI_INTCTL_CSR_BASE + 0x80) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_J_REG (CSR_CPI_INTCTL_CSR_BASE + 0x84) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_K_REG (CSR_CPI_INTCTL_CSR_BASE + 0x88) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_L_REG (CSR_CPI_INTCTL_CSR_BASE + 0x8C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_M_REG (CSR_CPI_INTCTL_CSR_BASE + 0x90) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_N_REG (CSR_CPI_INTCTL_CSR_BASE + 0x94) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_O_REG (CSR_CPI_INTCTL_CSR_BASE + 0x98) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x9C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_Q_REG (CSR_CPI_INTCTL_CSR_BASE + 0xA0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_R_REG (CSR_CPI_INTCTL_CSR_BASE + 0xA4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_S_REG (CSR_CPI_INTCTL_CSR_BASE + 0xA8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_T_REG (CSR_CPI_INTCTL_CSR_BASE + 0xAC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_U_REG (CSR_CPI_INTCTL_CSR_BASE + 0xB0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_V_REG (CSR_CPI_INTCTL_CSR_BASE + 0xB4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_W_REG (CSR_CPI_INTCTL_CSR_BASE + 0xB8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_X_REG (CSR_CPI_INTCTL_CSR_BASE + 0xBC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_Y_REG (CSR_CPI_INTCTL_CSR_BASE + 0xC0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_Z_REG (CSR_CPI_INTCTL_CSR_BASE + 0xC4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_A_REG (CSR_CPI_INTCTL_CSR_BASE + 0xD0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_B_REG (CSR_CPI_INTCTL_CSR_BASE + 0xD4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_C_REG (CSR_CPI_INTCTL_CSR_BASE + 0xD8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_D_REG (CSR_CPI_INTCTL_CSR_BASE + 0xDC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_E_REG (CSR_CPI_INTCTL_CSR_BASE + 0xE0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_F_REG (CSR_CPI_INTCTL_CSR_BASE + 0xE4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_G_REG (CSR_CPI_INTCTL_CSR_BASE + 0xE8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_H_REG (CSR_CPI_INTCTL_CSR_BASE + 0xEC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_I_REG (CSR_CPI_INTCTL_CSR_BASE + 0xF0) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_J_REG (CSR_CPI_INTCTL_CSR_BASE + 0xF4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_K_REG (CSR_CPI_INTCTL_CSR_BASE + 0xF8) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_L_REG (CSR_CPI_INTCTL_CSR_BASE + 0xFC) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_M_REG (CSR_CPI_INTCTL_CSR_BASE + 0x100) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_N_REG (CSR_CPI_INTCTL_CSR_BASE + 0x104) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_O_REG (CSR_CPI_INTCTL_CSR_BASE + 0x108) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x10C) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_Q_REG (CSR_CPI_INTCTL_CSR_BASE + 0x110) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_FIFO_R_REG (CSR_CPI_INTCTL_CSR_BASE + 0x114) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_DROP_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x120) +#define CSR_CPI_INTCTL_CSR_INTCTL_MSI_BP_TIMEOUT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x200) +#define CSR_CPI_INTCTL_CSR_INTCTL_MSI_BP_TIMEOUT_2ND_01P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x204) +#define CSR_CPI_INTCTL_CSR_INTCTL_MSI_BP_TIMEOUT_2ND_23P_REG (CSR_CPI_INTCTL_CSR_BASE + 0x208) +#define CSR_CPI_INTCTL_CSR_INTCTL_FLR_LIMIT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x220) +#define CSR_CPI_INTCTL_CSR_INTCTL_RESERVD_REG (CSR_CPI_INTCTL_CSR_BASE + 0x230) /* ECO保留 */ +#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_A_FATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2E0) +#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_A_NONFATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2E4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_A_PLUS_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2E8) +#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_B_FATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2F0) +#define CSR_CPI_INTCTL_CSR_INTCTL_OUT_B_NONFATAL_MSK_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2F4) +#define CSR_CPI_INTCTL_CSR_INTCTL_DBG_OUT_B_PLUS_REG (CSR_CPI_INTCTL_CSR_BASE + 0x2F8) +#define CSR_CPI_INTCTL_CSR_INTCTL_RAM_INIT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x310) /* DMA侧ram初始化寄存器 */ +#define CSR_CPI_INTCTL_CSR_INTCTL_RAM_STATUS_REG (CSR_CPI_INTCTL_CSR_BASE + 0x314) /* DMA侧ram初始化状态寄存器 */ +#define CSR_CPI_INTCTL_CSR_INTCTL_CTL_REG (CSR_CPI_INTCTL_CSR_BASE + 0x318) /* intctl模块控制寄存器 */ +#define CSR_CPI_INTCTL_CSR_INTCTL_RES_REG (CSR_CPI_INTCTL_CSR_BASE + 0x31C) /* int ctl 资源配置 */ +#define CSR_CPI_INTCTL_CSR_INTCTL_CSR_ACC_WEIGHT_REG (CSR_CPI_INTCTL_CSR_BASE + 0x320) /* 中断模块访问权重控制寄存器 \ + */ +#define CSR_CPI_INTCTL_CSR_INTCTL1_REG (CSR_CPI_INTCTL_CSR_BASE + 0x324) +#define CSR_CPI_INTCTL_CSR_INTCTL2_REG (CSR_CPI_INTCTL_CSR_BASE + 0x328) +#define CSR_CPI_INTCTL_CSR_INTCTL3_REG (CSR_CPI_INTCTL_CSR_BASE + 0x32C) +#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_ECC_CERR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x400) +#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_ECC_UCERR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x404) +#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_ERR_ADDR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x408) +#define CSR_CPI_INTCTL_CSR_DFX_INTCTL_RAM_MULTI_ERR_ADDR_REG (CSR_CPI_INTCTL_CSR_BASE + 0x40C) +#define CSR_CPI_INTCTL_CSR_INTCTL_ECC_INJ_REQ_REG (CSR_CPI_INTCTL_CSR_BASE + 0x410) + +/* CPI_OCTL_CSR Base address of Module's Register */ +#define CSR_CPI_OCTL_CSR_BASE (0x43B4800) + +/* **************************************************************************** */ +/* CPI_OCTL_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_CTRL0_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x0) /* CPI_OCTL internal table indirect access ctrl registers */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_CTRL1_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x4) /* CPI_OCTL internal table indirect access ctrl registers */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_0_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x8) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_1_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0xC) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_2_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x10) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_3_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x14) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_4_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x18) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_5_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x1C) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_6_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x20) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_TBL_INDIR_DATA_7_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x24) /* CPI_OCTL internal table indirect access data */ +#define CSR_CPI_OCTL_CSR_OCTL_RAM_INIT_REQ_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x28) /* CPI_OCTL internal RAM initial request */ +#define CSR_CPI_OCTL_CSR_OCTL_RAM_INIT_STS_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C) /* CPI_OCTL internal RAM initial status \ + */ +#define CSR_CPI_OCTL_CSR_PRE_SUB_DAT_CRD_CPB_REG (CSR_CPI_OCTL_CSR_BASE + 0x30) /* Data Credit presub value from CPB \ + */ +#define CSR_CPI_OCTL_CSR_L2NIC_CI_WR_CHL_CFG_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x34) /* specifies the D-Path channel for the CI write. */ +#define CSR_CPI_OCTL_CSR_CQE_WR_CHL_CFG_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x38) /* specifies the D-Path channel for the CQE write. */ +#define CSR_CPI_OCTL_CSR_PCIE_PORT_CFG_REG \ + (CSR_CPI_OCTL_CSR_BASE + 0x3C) /* specifies which PCIe port's FIFO configuration */ +#define CSR_CPI_OCTL_CSR_DMA_PE_YYY_FIFO_DEPTH_PORT012_REG (CSR_CPI_OCTL_CSR_BASE + 0x40) +#define CSR_CPI_OCTL_CSR_DMA_PE_YYY_FIFO_DEPTH_PORT34_REG (CSR_CPI_OCTL_CSR_BASE + 0x44) +#define CSR_CPI_OCTL_CSR_CPI_PREALLOC_CPB_BUF_REG (CSR_CPI_OCTL_CSR_BASE + 0x48) /* the pre-alloc CPB buffers */ +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x50) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x54) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x58) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x5C) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_5_REG (CSR_CPI_OCTL_CSR_BASE + 0x60) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_6_REG (CSR_CPI_OCTL_CSR_BASE + 0x64) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_7_REG (CSR_CPI_OCTL_CSR_BASE + 0x68) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_8_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_9_REG (CSR_CPI_OCTL_CSR_BASE + 0x70) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_10_REG (CSR_CPI_OCTL_CSR_BASE + 0x74) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_11_REG (CSR_CPI_OCTL_CSR_BASE + 0x78) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_12_REG (CSR_CPI_OCTL_CSR_BASE + 0x7C) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_13_REG (CSR_CPI_OCTL_CSR_BASE + 0x80) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_14_REG (CSR_CPI_OCTL_CSR_BASE + 0x84) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_15_REG (CSR_CPI_OCTL_CSR_BASE + 0x88) +#define CSR_CPI_OCTL_CSR_OCTL_CUT_THR_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x8C) +#define CSR_CPI_OCTL_CSR_OCTL_IN_CMD_CHNL_SRC_SEL_REG (CSR_CPI_OCTL_CSR_BASE + 0x94) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_REG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x98) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_REG_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x9C) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0xA0) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_B_REG (CSR_CPI_OCTL_CSR_BASE + 0xA4) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_C_REG (CSR_CPI_OCTL_CSR_BASE + 0xA8) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_DETECT_RO_REG_D_REG (CSR_CPI_OCTL_CSR_BASE + 0xAC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_A_REG (CSR_CPI_OCTL_CSR_BASE + 0xB0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_B_REG (CSR_CPI_OCTL_CSR_BASE + 0xB4) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_C_REG (CSR_CPI_OCTL_CSR_BASE + 0xB8) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_D_REG (CSR_CPI_OCTL_CSR_BASE + 0xBC) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_E_REG (CSR_CPI_OCTL_CSR_BASE + 0xC0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_F_REG (CSR_CPI_OCTL_CSR_BASE + 0xC4) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_G_REG (CSR_CPI_OCTL_CSR_BASE + 0xC8) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_H_REG (CSR_CPI_OCTL_CSR_BASE + 0xCC) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_I_REG (CSR_CPI_OCTL_CSR_BASE + 0xD0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_J_REG (CSR_CPI_OCTL_CSR_BASE + 0xD4) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_K_REG (CSR_CPI_OCTL_CSR_BASE + 0xD8) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_L_REG (CSR_CPI_OCTL_CSR_BASE + 0xDC) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_M_REG (CSR_CPI_OCTL_CSR_BASE + 0xE0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_N_REG (CSR_CPI_OCTL_CSR_BASE + 0xE4) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_O_REG (CSR_CPI_OCTL_CSR_BASE + 0xE8) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_P_REG (CSR_CPI_OCTL_CSR_BASE + 0xEC) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_Q_REG (CSR_CPI_OCTL_CSR_BASE + 0xF0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_R_REG (CSR_CPI_OCTL_CSR_BASE + 0xF4) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_S_REG (CSR_CPI_OCTL_CSR_BASE + 0xF8) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_T_REG (CSR_CPI_OCTL_CSR_BASE + 0xFC) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_U_REG (CSR_CPI_OCTL_CSR_BASE + 0x100) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_V_REG (CSR_CPI_OCTL_CSR_BASE + 0x104) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_W_REG (CSR_CPI_OCTL_CSR_BASE + 0x108) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_X_REG (CSR_CPI_OCTL_CSR_BASE + 0x10C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_Y_REG (CSR_CPI_OCTL_CSR_BASE + 0x110) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_Z_REG (CSR_CPI_OCTL_CSR_BASE + 0x114) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x118) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x11C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x120) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x124) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x128) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x12C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x130) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x134) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x138) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x13C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x140) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x144) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x148) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x14C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x150) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x154) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x158) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AR_REG (CSR_CPI_OCTL_CSR_BASE + 0x15C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AS_REG (CSR_CPI_OCTL_CSR_BASE + 0x160) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AT_REG (CSR_CPI_OCTL_CSR_BASE + 0x164) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AU_REG (CSR_CPI_OCTL_CSR_BASE + 0x168) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AV_REG (CSR_CPI_OCTL_CSR_BASE + 0x16C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AW_REG (CSR_CPI_OCTL_CSR_BASE + 0x170) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AX_REG (CSR_CPI_OCTL_CSR_BASE + 0x174) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AY_REG (CSR_CPI_OCTL_CSR_BASE + 0x178) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_AZ_REG (CSR_CPI_OCTL_CSR_BASE + 0x17C) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BA_REG (CSR_CPI_OCTL_CSR_BASE + 0x180) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BB_REG (CSR_CPI_OCTL_CSR_BASE + 0x184) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BC_REG (CSR_CPI_OCTL_CSR_BASE + 0x188) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1A0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1E0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x220) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x260) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AA_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2A0) /* CAP */ +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1A4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1E4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x224) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x264) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AB_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2A4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1A8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1E8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x228) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x268) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AC_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2A8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1AC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1EC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x22C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x26C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AD_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2AC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1B0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1F0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x230) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x270) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AE_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2B0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1B4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1F4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x234) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x274) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AF_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2B4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1B8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1F8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x238) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x278) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AG_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2B8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1BC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x1FC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x23C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x27C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AH_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2BC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1C0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x200) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x240) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x280) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AI_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1C4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x204) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x244) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x284) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AJ_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1C8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x208) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x248) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x288) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AK_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2C8) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1CC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x20C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x24C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x28C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AL_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2CC) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1D0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x210) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x250) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x290) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AM_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2D0) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x1D4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x214) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x254) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x294) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_PORT_AN_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x2D4) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BD_REG (CSR_CPI_OCTL_CSR_BASE + 0x300) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BE_REG (CSR_CPI_OCTL_CSR_BASE + 0x304) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BF_REG (CSR_CPI_OCTL_CSR_BASE + 0x308) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BG_REG (CSR_CPI_OCTL_CSR_BASE + 0x30C) +#define CSR_CPI_OCTL_CSR_OCTL_CMD_CNT_BH_REG (CSR_CPI_OCTL_CSR_BASE + 0x310) +#define CSR_CPI_OCTL_CSR_OCTL_DPATH_O_ERR_DFX_REG (CSR_CPI_OCTL_CSR_BASE + 0x340) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BK_REG (CSR_CPI_OCTL_CSR_BASE + 0x350) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BL_REG (CSR_CPI_OCTL_CSR_BASE + 0x354) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x358) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x35C) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x360) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x364) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x368) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x36C) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x370) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x374) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x378) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x37C) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x380) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x384) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x388) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x38C) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x390) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x394) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x398) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AR_REG (CSR_CPI_OCTL_CSR_BASE + 0x39C) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AS_REG (CSR_CPI_OCTL_CSR_BASE + 0x3A0) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AT_REG (CSR_CPI_OCTL_CSR_BASE + 0x3A4) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AU_REG (CSR_CPI_OCTL_CSR_BASE + 0x3A8) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AV_REG (CSR_CPI_OCTL_CSR_BASE + 0x3AC) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AW_REG (CSR_CPI_OCTL_CSR_BASE + 0x3B0) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AX_REG (CSR_CPI_OCTL_CSR_BASE + 0x3B4) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AY_REG (CSR_CPI_OCTL_CSR_BASE + 0x3B8) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_AZ_REG (CSR_CPI_OCTL_CSR_BASE + 0x3BC) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BA_REG (CSR_CPI_OCTL_CSR_BASE + 0x3C0) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BB_REG (CSR_CPI_OCTL_CSR_BASE + 0x3C4) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BC_REG (CSR_CPI_OCTL_CSR_BASE + 0x3C8) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BD_REG (CSR_CPI_OCTL_CSR_BASE + 0x3CC) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BE_REG (CSR_CPI_OCTL_CSR_BASE + 0x3D0) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BF_REG (CSR_CPI_OCTL_CSR_BASE + 0x3D4) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BG_REG (CSR_CPI_OCTL_CSR_BASE + 0x3D8) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BH_REG (CSR_CPI_OCTL_CSR_BASE + 0x3DC) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BI_REG (CSR_CPI_OCTL_CSR_BASE + 0x3E0) +#define CSR_CPI_OCTL_CSR_OCTL_SUB_ERR_CFG_BJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x3E4) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_BYPASS_REG (CSR_CPI_OCTL_CSR_BASE + 0x3F8) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_INJ_REQ_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x3FC) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_INJ_REQ_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x400) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_INJ_REQ_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x404) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_ERR_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x408) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_ERR_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x40C) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_ECC_ERR_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x410) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x414) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x418) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x41C) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x420) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x424) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x428) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x42C) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x430) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x434) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x438) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x43C) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x440) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x444) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x448) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x44C) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x450) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x454) +#define CSR_CPI_OCTL_CSR_OCTL_RAM_LINK_LIST_AR_REG (CSR_CPI_OCTL_CSR_BASE + 0x458) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x45C) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x460) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x464) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x468) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x46C) +#define CSR_CPI_OCTL_CSR_OCTL_IN_BP_SIG_F_REG (CSR_CPI_OCTL_CSR_BASE + 0x470) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x474) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x478) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x47C) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x480) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_ST_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x484) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_AFON_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x488) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_AFON_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x48C) +#define CSR_CPI_OCTL_CSR_OCTL_FIFO_AFON_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x490) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x4A0) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x4A4) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x4A8) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x4AC) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x4B0) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x4B4) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x4B8) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x4BC) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AI_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C0) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AJ_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C4) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AK_REG (CSR_CPI_OCTL_CSR_BASE + 0x4C8) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AL_REG (CSR_CPI_OCTL_CSR_BASE + 0x4CC) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AM_REG (CSR_CPI_OCTL_CSR_BASE + 0x4D0) +#define CSR_CPI_OCTL_CSR_OCTL_EC_SORO_ATTR_TBL_FIRST_REG (CSR_CPI_OCTL_CSR_BASE + 0x4E4) +#define CSR_CPI_OCTL_CSR_OCTL_EC_SORO_ATTR_TBL_SECOND_REG (CSR_CPI_OCTL_CSR_BASE + 0x4E8) +#define CSR_CPI_OCTL_CSR_OCTL_EC_CHANNEL_ENABLE_REG (CSR_CPI_OCTL_CSR_BASE + 0x4EC) +#define CSR_CPI_OCTL_CSR_OCTL_SM_CBUF_I_READY_CHNL_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x4F0) +#define CSR_CPI_OCTL_CSR_OCTL_SM_CBUF_I_READY_CHNL_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x4F4) +#define CSR_CPI_OCTL_CSR_OCTL_MUL_HOST_DIF_RD_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x4F8) +#define CSR_CPI_OCTL_CSR_OCTL_DB_WR_ADDR_L_REG (CSR_CPI_OCTL_CSR_BASE + 0x4FC) +#define CSR_CPI_OCTL_CSR_OCTL_DB_WR_ADDR_H_REG (CSR_CPI_OCTL_CSR_BASE + 0x500) +#define CSR_CPI_OCTL_CSR_OCTL_ENDIAN_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x504) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x560) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x564) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x568) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x56C) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x570) +#define CSR_CPI_OCTL_CSR_OCTL_FSM_ST_F_REG (CSR_CPI_OCTL_CSR_BASE + 0x574) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x578) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x57C) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_C_REG (CSR_CPI_OCTL_CSR_BASE + 0x580) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_D_REG (CSR_CPI_OCTL_CSR_BASE + 0x584) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_E_REG (CSR_CPI_OCTL_CSR_BASE + 0x588) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_F_REG (CSR_CPI_OCTL_CSR_BASE + 0x58C) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_G_REG (CSR_CPI_OCTL_CSR_BASE + 0x590) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_H_REG (CSR_CPI_OCTL_CSR_BASE + 0x594) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AN_REG (CSR_CPI_OCTL_CSR_BASE + 0x598) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AO_REG (CSR_CPI_OCTL_CSR_BASE + 0x59C) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AP_REG (CSR_CPI_OCTL_CSR_BASE + 0x5A0) +#define CSR_CPI_OCTL_CSR_OCTL_ERR_SIG_AQ_REG (CSR_CPI_OCTL_CSR_BASE + 0x5A4) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_I_REG (CSR_CPI_OCTL_CSR_BASE + 0x5A8) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_J_REG (CSR_CPI_OCTL_CSR_BASE + 0x5AC) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_K_REG (CSR_CPI_OCTL_CSR_BASE + 0x5B0) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_L_REG (CSR_CPI_OCTL_CSR_BASE + 0x5B4) +#define CSR_CPI_OCTL_CSR_OCTL_PE_PARSER_CFG_1ST_REG (CSR_CPI_OCTL_CSR_BASE + 0x650) +#define CSR_CPI_OCTL_CSR_OCTL_LOOP_ST_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x654) +#define CSR_CPI_OCTL_CSR_OCTL_LOOP_ST_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x658) +#define CSR_CPI_OCTL_CSR_OCTL_DFX_SIG_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x65C) +#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x674) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x684) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x694) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x6A4) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_PF_RANGE_PORT_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x6B4) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x678) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x688) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x698) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x6A8) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VF_RANGE_PORT_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x6B8) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_0_REG (CSR_CPI_OCTL_CSR_BASE + 0x67C) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_1_REG (CSR_CPI_OCTL_CSR_BASE + 0x68C) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_2_REG (CSR_CPI_OCTL_CSR_BASE + 0x69C) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_3_REG (CSR_CPI_OCTL_CSR_BASE + 0x6AC) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_LVF_RANGE_PORT_4_REG (CSR_CPI_OCTL_CSR_BASE + 0x6BC) /* PF和端口映射寄存器 */ +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C0) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AB_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C4) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AC_REG (CSR_CPI_OCTL_CSR_BASE + 0x6C8) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AD_REG (CSR_CPI_OCTL_CSR_BASE + 0x6CC) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AE_REG (CSR_CPI_OCTL_CSR_BASE + 0x6D0) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AF_REG (CSR_CPI_OCTL_CSR_BASE + 0x6D4) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AG_REG (CSR_CPI_OCTL_CSR_BASE + 0x6D8) +#define CSR_CPI_OCTL_CSR_OCTL_VLD_SIG_AH_REG (CSR_CPI_OCTL_CSR_BASE + 0x6DC) +#define CSR_CPI_OCTL_CSR_CPI_OCTL_CPATH_CRDT_REG (CSR_CPI_OCTL_CSR_BASE + 0x718) /* CPATH信用配置寄存器 */ +#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_ONE_REG (CSR_CPI_OCTL_CSR_BASE + 0x71C) +#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_TWO_REG (CSR_CPI_OCTL_CSR_BASE + 0x720) +#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_THREE_REG (CSR_CPI_OCTL_CSR_BASE + 0x724) +#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_FOUR_REG (CSR_CPI_OCTL_CSR_BASE + 0x728) +#define CSR_CPI_OCTL_CSR_CTRL_BUS_CFG_FIVE_REG (CSR_CPI_OCTL_CSR_BASE + 0x72C) +#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_AA_REG (CSR_CPI_OCTL_CSR_BASE + 0x730) +#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_BB_REG (CSR_CPI_OCTL_CSR_BASE + 0x734) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_M_REG (CSR_CPI_OCTL_CSR_BASE + 0x738) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_N_REG (CSR_CPI_OCTL_CSR_BASE + 0x73C) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_O_REG (CSR_CPI_OCTL_CSR_BASE + 0x740) +#define CSR_CPI_OCTL_CSR_OCTL_HEAD_STORAGE_DFX_P_REG (CSR_CPI_OCTL_CSR_BASE + 0x744) +#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_CC_REG (CSR_CPI_OCTL_CSR_BASE + 0x748) +#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_DD_REG (CSR_CPI_OCTL_CSR_BASE + 0x74C) +#define CSR_CPI_OCTL_CSR_BAK_FOR_ECO_EE_REG (CSR_CPI_OCTL_CSR_BASE + 0x750) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_EN_A_REG (CSR_CPI_OCTL_CSR_BASE + 0x754) +#define CSR_CPI_OCTL_CSR_CPI_SM_CHL_CFG_EN_B_REG (CSR_CPI_OCTL_CSR_BASE + 0x758) +#define CSR_CPI_OCTL_CSR_CPI_OCTL_MUL_WR_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x75C) +#define CSR_CPI_OCTL_CSR_CPI_OCTL_CQE_CTL_CFG_REG (CSR_CPI_OCTL_CSR_BASE + 0x760) + +/* CPI_OSCH_CSR Base address of Module's Register */ +#define CSR_CPI_OSCH_CSR_BASE (0x43B5000) + +/* **************************************************************************** */ +/* CPI_OSCH_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x0) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x4) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x8) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xC) /* 单纯 的基于port统计drop数量。对应PCIe P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT_PORT4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x10) /* 单纯 的基于port统计drop数量。对应HVA P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_ERROR_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x14) /* 单纯的基于port统计err数量。对应P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_ERROR_CNT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x18) /* 单纯的基于port统计err数量。对应P类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x20) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是PCIe的P报文。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x24) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x28) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x2C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x30) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x34) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x38) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x3C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x40) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x44) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x48) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x4C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x50) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x54) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x58) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC01_REG (CSR_CPI_OSCH_CSR_BASE + 0x60) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC23_REG (CSR_CPI_OSCH_CSR_BASE + 0x64) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC45_REG (CSR_CPI_OSCH_CSR_BASE + 0x68) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC67_REG (CSR_CPI_OSCH_CSR_BASE + 0x6C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC89_REG (CSR_CPI_OSCH_CSR_BASE + 0x70) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC1011_REG (CSR_CPI_OSCH_CSR_BASE + 0x74) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC1213_REG (CSR_CPI_OSCH_CSR_BASE + 0x78) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_FUNC1415_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C) +#define CSR_CPI_OSCH_CSR_OSCH_CEQE_DROP_CNT_REG (CSR_CPI_OSCH_CSR_BASE + 0x90) /* ceqe drop counter统计。 */ +#define CSR_CPI_OSCH_CSR_OSCH_CEQE_PI_OVERFLOW_REG (CSR_CPI_OSCH_CSR_BASE + 0x94) /* 有统计信号 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_OVERFLOW_LOW_REG \ + (CSR_CPI_OSCH_CSR_BASE + \ + 0x98) /* osch所有的fifo overflow统计信号这个地方使用OR的方式操作overflow告警，不对，需要展开。 */ +#define CSR_CPI_OSCH_CSR_OSCH_REQ_TIMEOUT_REG (CSR_CPI_OSCH_CSR_BASE + 0x9C) /* 检测oschoutbound request 超时状态 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_EMPT_HIGH_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xA0) /* osch 所有fifo的empty告警信号，中域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_EMPT_LOW_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xA4) /* osch 所有fifo的empty告警信号，低域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_AFULL_HIGH_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xA8) /* osch 所有fifo的AFULL告警信号，中域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_AFULL_LOW_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xAC) /* osch 所有fifo的AFULL告警信号，低域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_PAYLOAD_FIFO_CTRL_REG (CSR_CPI_OSCH_CSR_BASE + 0xB0) /* payload fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_OSCH_MSI_TX_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xB4) /* msi_tx fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_OSCH_MSI_TX_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xB8) /* msi_tx fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ATOMIC_TX_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xBC) /* atomic_tx fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ATOMIC_TX_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xC0) /* atomic_tx fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_OSCH_CEQE_TX_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xC4) /* ceqe_tx fifo的afull反压门限。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_CEQE_TX_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xC8) /* ceqe_tx fifo的afull反压门限。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_CPLD_TX_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xD0) /* cpld_tx fifo的afull反压门限。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_CPLD_TX_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xD4) /* cpld_tx fifo的afull反压门限。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_EMPT_TOPHIGH_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xD8) /* osch 所有fifo的empty告警信号，最高域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_FIFO_AFULL_TOPHIGH_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0xDC) /* osch 所有fifo的AFULL告警信号，高域段 */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q0_FIFO_CTRL0_REG (CSR_CPI_OSCH_CSR_BASE + 0xF0) /* CPATH Q0FIFO的afull反压门限， \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q0_FIFO_CTRL1_REG (CSR_CPI_OSCH_CSR_BASE + 0xF4) /* CPATH Q0FIFO的afull反压门限， \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q1_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x100) /* CPATH Q1FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q1_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x104) /* CPATH Q1FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q2_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x110) /* CPATH Q2FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_CPATH_Q2_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x114) /* CPATH Q2FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q0_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x120) /* DPATH Q0FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q0_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x124) /* DPATH Q0FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q1_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x130) /* DPATH Q1FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q1_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x134) /* DPATH Q1FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q2_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x140) /* DPATH Q2FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q2_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x144) /* DPATH Q2FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q3_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x150) /* DPATH Q3FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q3_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x154) /* DPATH Q3FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q4_FIFO_CTRL0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x160) /* DPATH Q4FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_DPATH_Q4_FIFO_CTRL1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x164) /* DPATH Q4FIFO的afull反压门限， */ +#define CSR_CPI_OSCH_CSR_OSCH_RESERVED0_REG (CSR_CPI_OSCH_CSR_BASE + 0x170) +#define CSR_CPI_OSCH_CSR_OSCH_RESERVED1_REG (CSR_CPI_OSCH_CSR_BASE + 0x174) +#define CSR_CPI_OSCH_CSR_OSCH_RESERVED2_REG (CSR_CPI_OSCH_CSR_BASE + 0x178) +#define CSR_CPI_OSCH_CSR_GLB_POST_HEAD_CREDIT_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x180) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_POST_PAYLOAD_CREDIT_H_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x184) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_POST_PAYLOAD_CREDIT_L_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x188) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_NON_POST_HEAD_CREDIT_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x190) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_NON_POST_PAYLOAD_CREDIT_H_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x194) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_NON_POST_PAYLOAD_CREDIT_L_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x198) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_CPL_HEAD_CREDIT_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x1A0) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_CPL_PAYLOAD_CREDIT_H_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x1A4) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_CPL_PAYLOAD_CREDIT_L_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x1A8) /* 不使用（pcie3.0相关的FC信用信号）。 */ +#define CSR_CPI_OSCH_CSR_GLB_OSCH_CEQE_IN_CNT_REG (CSR_CPI_OSCH_CSR_BASE + 0x1B0) /* 内部capture信号 */ +#define CSR_CPI_OSCH_CSR_GLB_OSCH_CEQE_OUT_CNT_REG (CSR_CPI_OSCH_CSR_BASE + 0x1B4) +#define CSR_CPI_OSCH_CSR_GLB_CEQE_DROP_TAIL_REG (CSR_CPI_OSCH_CSR_BASE + 0x1C0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT0_REG (CSR_CPI_OSCH_CSR_BASE + 0x1D0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x1D4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x1D8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x1DC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_POST_CNT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x1E0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT0_REG (CSR_CPI_OSCH_CSR_BASE + 0x1F0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x1F4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x1F8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x1FC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NON_POST_CNT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x200) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT0_REG (CSR_CPI_OSCH_CSR_BASE + 0x210) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x214) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x218) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x21C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_CPL_CNT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x220) +#define CSR_CPI_OSCH_CSR_OSCH_INT_CEQ_CREDIT_PORT01_REG (CSR_CPI_OSCH_CSR_BASE + 0x230) +#define CSR_CPI_OSCH_CSR_OSCH_INT_CEQ_CREDIT_PORT23_REG (CSR_CPI_OSCH_CSR_BASE + 0x234) +#define CSR_CPI_OSCH_CSR_OSCH_INT_CEQ_CREDIT_PORT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x238) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_BP_STS_REG (CSR_CPI_OSCH_CSR_BASE + 0x240) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q0_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x250) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q0_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x254) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q1_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x260) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q1_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x264) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q2_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x270) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q2_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x274) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q3_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x280) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q3_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x284) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q4_BP_THD0_REG (CSR_CPI_OSCH_CSR_BASE + 0x290) +#define CSR_CPI_OSCH_CSR_OSCH_ESCH_DPATH_Q4_BP_THD1_REG (CSR_CPI_OSCH_CSR_BASE + 0x294) +#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x298) +#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_PERIOD_REG (CSR_CPI_OSCH_CSR_BASE + 0x2A0) +#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x2A4) /* PCIE的P类型TLP长度统计 */ +#define CSR_CPI_OSCH_CSR_OSCH_PERF_WATCH_TLP_REG (CSR_CPI_OSCH_CSR_BASE + 0x2A8) /* PCIE的P类型TLP长度统计 */ +#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x300) /* each port out-bound scheduling weight */ +#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x340) /* each port out-bound scheduling weight */ +#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x380) /* each port out-bound scheduling weight */ +#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3C0) /* each port out-bound scheduling weight */ +#define CSR_CPI_OSCH_CSR_PORT_OUT_SCH_DWRR_WEIGHT_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x400) /* each port out-bound scheduling weight */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x304) /* port C-Path Queues' scheduling weight for 2nd read scheduling */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x344) /* port C-Path Queues' scheduling weight for 2nd read scheduling */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x384) /* port C-Path Queues' scheduling weight for 2nd read scheduling */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3C4) /* port C-Path Queues' scheduling weight for 2nd read scheduling */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT1_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x404) /* port C-Path Queues' scheduling weight for 2nd read scheduling */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x308) /* port read scheduling weight for different queue. */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x348) /* port read scheduling weight for different queue. */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x388) /* port read scheduling weight for different queue. */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3C8) /* port read scheduling weight for different queue. */ +#define CSR_CPI_OSCH_CSR_PORT_RD_SRC_WEIGHT0_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x408) /* port read scheduling weight for different queue. */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x30C) /* dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x34C) /* dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x38C) /* dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3CC) /* dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT1_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x40C) /* dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x310) /* dpath rd channel WRR weight inj a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x350) /* dpath rd channel WRR weight inj a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x390) /* dpath rd channel WRR weight inj a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3D0) /* dpath rd channel WRR weight inj a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_DPATH_WRR_WEIGHT0_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x410) /* dpath rd channel WRR weight inj a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x314) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x354) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x394) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3D4) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT1_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x414) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x318) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x358) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x398) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3D8) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_RD_NON_DPATH_WRR_WEIGHT0_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x418) /* non-dpath rd channel WRR weight in a port */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x320) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x360) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3A0) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3E0) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT2_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x420) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x324) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x364) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3A4) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3E4) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT1_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x424) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x328) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x368) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3A8) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3E8) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_PORT_WR_WRR_WEIGHT0_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x428) /* wr channel WRR weight in a port \ + */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x32C) /* wr cmd 转DOORBELL的信用的反压门限 */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x36C) /* wr cmd 转DOORBELL的信用的反压门限 */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3AC) /* wr cmd 转DOORBELL的信用的反压门限 */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x3EC) /* wr cmd 转DOORBELL的信用的反压门限 */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_BP_TH_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x42C) /* wr cmd 转DOORBELL的信用的反压门限 */ +#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x330) /* doorbell 溢出历史告警。 */ +#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x370) /* doorbell 溢出历史告警。 */ +#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x3B0) /* doorbell 溢出历史告警。 */ +#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x3F0) /* doorbell 溢出历史告警。 */ +#define CSR_CPI_OSCH_CSR_DOORBELL_WR_CMD_CRDT_ERR_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x430) /* doorbell 溢出历史告警。 */ +#define CSR_CPI_OSCH_CSR_OSCH_CTRL_DOORBELL_CNT_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x500) /* 伪装成DMA 写命令发送给CPI_CTRL的doorbell，对齐的统计计数。 */ +#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x504) /* 通道0 WR 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x508) /* 通道0 RD 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x50C) /* 通道0 CPL 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x510) /* 通道1 WR 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x514) /* 通道1 RD 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x518) /* 通道1 CPL 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x51C) /* 通道2 WR 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x520) /* 通道2 RD 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x524) /* 通道2 CPL 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x528) /* 通道3 WR 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x52C) /* 通道3 RD 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x530) /* 通道3 CPL 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_WR_PAYLOAD_CRDT_CNT4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x534) /* 通道4 WR 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_RD_PAYLOAD_CRDT_CNT4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x538) /* 通道4 RD 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_PCIE_CPL_PAYLOAD_CRDT_CNT4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x53C) /* 通道4 CPL 命令PCIE信用申请状态 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x540) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x544) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x548) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x54C) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x550) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INJ_5_REG (CSR_CPI_OSCH_CSR_BASE + 0x554) /* OSCH内MEMORY的ECC注错控制。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_0_REG (CSR_CPI_OSCH_CSR_BASE + 0x558) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_1_REG (CSR_CPI_OSCH_CSR_BASE + 0x55C) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_2_REG (CSR_CPI_OSCH_CSR_BASE + 0x560) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_3_REG (CSR_CPI_OSCH_CSR_BASE + 0x564) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_4_REG (CSR_CPI_OSCH_CSR_BASE + 0x568) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_5_REG (CSR_CPI_OSCH_CSR_BASE + 0x56C) /* OSCH内MEMORY的ECC单bit/多bit中断上报。 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x570) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x574) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x578) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x57C) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x580) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_INT_EN_5_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x584) /* OSCH内MEMORY的ECC单bit/多bit中断上报开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x588) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x58C) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x590) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x594) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x598) /* OSCH内MEMORY的ECC单bit/多bit 错误地址锁存值。 */ +#define CSR_CPI_OSCH_CSR_OSCH_ECC_ERR_ADDR_SEL_REG (CSR_CPI_OSCH_CSR_BASE + 0x59C) /* PORT0~4内ECC 错误地址上报选择 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5A0) /* OSCH内FIFO的overflow告警中断上报。 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5A4) /* OSCH内FIFO的overflow告警中断上报。 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5A8) /* OSCH内FIFO的overflow告警中断上报。 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_EN_0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5AC) /* OSCH内FIFO的overflow告警中断开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_EN_1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5B0) /* OSCH内FIFO的overflow告警中断开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_OVERFLOW_INT_EN_2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5B4) /* OSCH内FIFO的overflow告警中断开关。 */ +#define CSR_CPI_OSCH_CSR_OSCH_CRT_ERR_REG (CSR_CPI_OSCH_CSR_BASE + 0x5B8) /* OSCH内的可纠错误中断上报 */ +#define CSR_CPI_OSCH_CSR_OSCH_UNCRT_ERR_REG (CSR_CPI_OSCH_CSR_BASE + 0x5BC) /* OSCH内的不可纠错误中断上报 */ +#define CSR_CPI_OSCH_CSR_OSCH_CRT_ERR_INT_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C0) /* OSCH内的可纠错误中断上报开关 */ +#define CSR_CPI_OSCH_CSR_OSCH_UNCRT_ERR_INT_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C4) /* OSCH内的不可纠错误中断上报开关 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_ACTIVE_EN_CFG_REG (CSR_CPI_OSCH_CSR_BASE + 0x5C8) /* OSCH内的tx_crd_active_en自定义输出 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_NL2NIC_OUTSTANDING_BP_CFG_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x5CC) /* OSCH内各port的AAD FIFO的non l2nic outstanding的bp门限 */ +#define CSR_CPI_OSCH_CSR_CEQ_CLS_FIFO_ST_ERR_REG (CSR_CPI_OSCH_CSR_BASE + 0x600) /* cqe cls fifo status_err */ +#define CSR_CPI_OSCH_CSR_GLB_CQE_CI_D_CHL_REG (CSR_CPI_OSCH_CSR_BASE + 0x604) /* CQE_CI_DP_CHL */ +#define CSR_CPI_OSCH_CSR_GLB_DMA_SO_RO_REPLACE_REG (CSR_CPI_OSCH_CSR_BASE + 0x608) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_RLS_TAG_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x60C) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_TIMEOUT_REG (CSR_CPI_OSCH_CSR_BASE + 0x610) +#define CSR_CPI_OSCH_CSR_GLB_CP_CQE_CREDIT_PORT_REG (CSR_CPI_OSCH_CSR_BASE + 0x614) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_HI_LMT_H_REG (CSR_CPI_OSCH_CSR_BASE + 0x618) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_HI_LMT_L_REG (CSR_CPI_OSCH_CSR_BASE + 0x61C) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_LO_LMT_H_REG (CSR_CPI_OSCH_CSR_BASE + 0x620) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_LO_LMT_L_REG (CSR_CPI_OSCH_CSR_BASE + 0x624) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_OUT_RANGE_H_REG (CSR_CPI_OSCH_CSR_BASE + 0x628) +#define CSR_CPI_OSCH_CSR_GLB_OSCH_ADDR_OUT_RANGE_L_REG (CSR_CPI_OSCH_CSR_BASE + 0x62C) +#define CSR_CPI_OSCH_CSR_OSCH_PAYLOAD_FIFO1_CTRL_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x630) /* payload fifo1的afull反压门限。(位宽转换FIFO) */ +#define CSR_CPI_OSCH_CSR_OSCH_DBELL_FIFO_CTRL_REG (CSR_CPI_OSCH_CSR_BASE + 0x634) /* doorbell fifo的afull反压门限。 */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_WR_CMD_EN_REG (CSR_CPI_OSCH_CSR_BASE + 0x638) /* wr cmd 转DOORBELL的使能信号。 \ + */ +#define CSR_CPI_OSCH_CSR_CFG_DOORBELL_CRDT_INITIAL_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x63C) /* wr cmd 转DOORBELL的信用的置位信号 */ +#define CSR_CPI_OSCH_CSR_CFG_DPATH_XTS_RD_REG (CSR_CPI_OSCH_CSR_BASE + 0x640) /* 针对XTS对应通道的配置使能 */ +#define CSR_CPI_OSCH_CSR_CFG_ROUND_BIT_CHECK_MOD_REG (CSR_CPI_OSCH_CSR_BASE + 0x650) /* ROUND BIT 检查开关。 */ +#define CSR_CPI_OSCH_CSR_CFG_PORT1_TO_PORT0_MODE_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x660) /* PORT1 channel到PORT0资源的路由开关。 */ +#define CSR_CPI_OSCH_CSR_CFG_NON_L2NIC_LOOP2_EDGE_EN_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x670) /* 在non l2nic inline 数据在第二轮进入Dpath_rd通路时。是否判定F_L边界。 */ +#define CSR_CPI_OSCH_CSR_CFG_CUR_CPL_TIMEOUT_DROP_MAX_REG (CSR_CPI_OSCH_CSR_BASE + 0x674) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x700) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x704) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT2_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x708) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT3_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x70C) /* 单纯 的基于port统计drop数量。对应PCIe NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT_PORT4_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x710) /* 单纯 的基于port统计drop数量。对应HVA NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_ERROR_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x714) /* 单纯的基于port统计err数量。对应NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_ERROR_CNT1_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x718) /* 单纯的基于port统计err数量。对应NPCPL类型 */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x720) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是PCIE的NP/CPL报文 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x724) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x728) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x72C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x730) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x734) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x738) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x73C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x740) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x744) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x748) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x74C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x750) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x754) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x758) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_NPCPL_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x75C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x760) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是HVA端口的的P报文 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x764) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x768) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x76C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x770) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x774) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x778) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x77C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x780) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x784) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x788) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x78C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x790) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x794) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x798) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_P_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x79C) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT0_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x7A0) /* 通过vfid，来针对目标function进行drop统计，只能同时统计16个function。对应目标function可配置。对应统计项是HVA端口的的NP/CPL报文 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT1_REG (CSR_CPI_OSCH_CSR_BASE + 0x7A4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT2_REG (CSR_CPI_OSCH_CSR_BASE + 0x7A8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT3_REG (CSR_CPI_OSCH_CSR_BASE + 0x7AC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT4_REG (CSR_CPI_OSCH_CSR_BASE + 0x7B0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT5_REG (CSR_CPI_OSCH_CSR_BASE + 0x7B4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT6_REG (CSR_CPI_OSCH_CSR_BASE + 0x7B8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT7_REG (CSR_CPI_OSCH_CSR_BASE + 0x7BC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT8_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT9_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT10_REG (CSR_CPI_OSCH_CSR_BASE + 0x7C8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT11_REG (CSR_CPI_OSCH_CSR_BASE + 0x7CC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT12_REG (CSR_CPI_OSCH_CSR_BASE + 0x7D0) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT13_REG (CSR_CPI_OSCH_CSR_BASE + 0x7D4) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT14_REG (CSR_CPI_OSCH_CSR_BASE + 0x7D8) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_HVA_NPCPL_DROP_CNT15_REG (CSR_CPI_OSCH_CSR_BASE + 0x7DC) +#define CSR_CPI_OSCH_CSR_OSCH_TLP_DROP_COUNT_MODE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7E0) +#define CSR_CPI_OSCH_CSR_OSCH_NPCPL_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7E8) /* PCIE的NPCPL类型TLP长度统计 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_NPCPL_PERF_WATCH_TLP_REG (CSR_CPI_OSCH_CSR_BASE + 0x7EC) /* PCIE的NPCPL类型TLP长度统计 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_HVA_P_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7F0) /* HVA的P类型TLP长度统计 */ +#define CSR_CPI_OSCH_CSR_OSCH_HVA_P_PERF_WATCH_TLP_REG (CSR_CPI_OSCH_CSR_BASE + 0x7F4) /* HVA的NPCPL类型TLP长度统计 */ +#define CSR_CPI_OSCH_CSR_OSCH_HVA_NPCPL_PERF_WATCH_BYTE_REG (CSR_CPI_OSCH_CSR_BASE + 0x7F8) /* HVA的P类型TLP长度统计 \ + */ +#define CSR_CPI_OSCH_CSR_OSCH_HVA_NPCPL_PERF_WATCH_TLP_REG \ + (CSR_CPI_OSCH_CSR_BASE + 0x7FC) /* HVA的NPCPL类型TLP长度统计 */ + +#endif // CPI_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_c_union_define.h new file mode 100644 index 000000000..71faa9bfd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_c_union_define.h @@ -0,0 +1,6226 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : crypto_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/7/25 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/07/25 10:01:08 Create file +// ****************************************************************************** + +#ifndef CRYPTO_C_UNION_DEFINE_H +#define CRYPTO_C_UNION_DEFINE_H +/* Define the union csr_am_ctrl_global_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_shutdown_req : 1; /* [0] */ + u32 ctrl_lat_stat_rd_en : 1; /* [1] */ + u32 ctrl_lat_stat_wr_en : 1; /* [2] */ + u32 rsv_0 : 1; /* [3] */ + u32 rd_rate_limit : 4; /* [7:4] */ + u32 wr_rate_limit : 4; /* [11:8] */ + u32 rsv_1 : 4; /* [15:12] */ + u32 ctrl_en_rd_256byte_global : 1; /* [16] */ + u32 ctrl_en_wr_256byte_global : 1; /* [17] */ + u32 ctrl_clkgt_en : 1; /* [18] */ + u32 rsv_2 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_ctrl_global_u; + +/* Define the union csr_am_ctrl_latency_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_lat_rd_port_sel : 4; /* [3:0] */ + u32 rsv_3 : 4; /* [7:4] */ + u32 ctrl_lat_wr_port_sel : 4; /* [11:8] */ + u32 rsv_4 : 4; /* [15:12] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_ctrl_latency_sel_u; + +/* Define the union csr_am_ctrl_ptl_wr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctrl_ptl_wr_64byte : 1; /* [0] */ + u32 rsv_6 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_ctrl_ptl_wr_u; + +/* Define the union csr_am_cfg_max_trans_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_rd_trans : 8; /* [7:0] */ + u32 cfg_max_wr_trans : 8; /* [15:8] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_cfg_max_trans_u; + +/* Define the union csr_am_cfg_single_port_max_trans_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_max_sgl_port_rd_trans : 8; /* [7:0] */ + u32 cfg_max_sgl_port_wr_trans : 8; /* [15:8] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_cfg_single_port_max_trans_u; + +/* Define the union csr_am_cfg_port_rd_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port_rd_en : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_cfg_port_rd_en_u; + +/* Define the union csr_am_cfg_port_wr_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_port_wr_en : 16; /* [15:0] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_cfg_port_wr_en_u; + +/* Define the union csr_am_curr_aw_w_fifo_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_w_tx_port : 16; /* [15:0] */ + u32 curr_w_tx_stock : 2; /* [17:16] */ + u32 curr_w_tx_idle : 1; /* [18] */ + u32 rsv_11 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_aw_w_fifo_sts_u; + +/* Define the union csr_am_curr_port_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_port_sts : 16; /* [15:0] */ + u32 curr_wr_port_sts : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_port_sts_u; + +/* Define the union csr_am_rob_ecc_int_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rob_ecc_err_onebit : 1; /* [0] */ + u32 rob_ecc_err_multpl : 1; /* [1] */ + u32 rsv_12 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_rob_ecc_int_sts_u; + +/* Define the union csr_am_rob_ecc_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ecc_err_detect_int_msk : 1; /* [0] */ + u32 cfg_ecc_err_multpl_int_msk : 1; /* [1] */ + u32 rsv_13 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_rob_ecc_int_mask_u; + +/* Define the union csr_am_rob_ecc_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rob_ecc_onebit_err_addr : 12; /* [11:0] */ + u32 rob_ecc_multpl_err_addr : 12; /* [23:12] */ + u32 rsv_14 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_rob_ecc_err_addr_u; + +/* Define the union csr_am_curr_max_rd_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_max_rd_latency : 16; /* [15:0] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_max_rd_latency_u; + +/* Define the union csr_am_curr_ava_rd_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_ava_rd_latency : 16; /* [15:0] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_ava_rd_latency_u; + +/* Define the union csr_am_curr_rd_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_latency : 16; /* [15:0] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_rd_latency_u; + +/* Define the union csr_am_curr_max_wr_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_max_wr_latency : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_max_wr_latency_u; + +/* Define the union csr_am_curr_ava_wr_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_ava_wr_latency : 16; /* [15:0] */ + u32 rsv_19 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_ava_wr_latency_u; + +/* Define the union csr_am_curr_wr_latency_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_wr_latency : 16; /* [15:0] */ + u32 rsv_20 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_wr_latency_u; + +/* Define the union csr_am_curr_trans_return_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_all_rd_returned : 1; /* [0] */ + u32 curr_all_wr_returned : 1; /* [1] */ + u32 rsv_21 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_trans_return_u; + +/* Define the union csr_am_curr_rd_max_txid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_max_txid : 7; /* [6:0] */ + u32 rsv_22 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_rd_max_txid_u; + +/* Define the union csr_am_curr_wr_max_txid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_wr_max_txid : 7; /* [6:0] */ + u32 rsv_23 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_wr_max_txid_u; + +/* Define the union csr_am_curr_rd_txid_sts_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_txid_sts_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_rd_txid_sts_0_u; + +/* Define the union csr_am_curr_rd_txid_sts_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_txid_sts_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_rd_txid_sts_1_u; + +/* Define the union csr_am_curr_rd_txid_sts_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_rd_txid_sts_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_rd_txid_sts_2_u; + +/* Define the union csr_am_curr_wr_txid_sts_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_wr_txid_sts_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_wr_txid_sts_0_u; + +/* Define the union csr_am_curr_wr_txid_sts_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_wr_txid_sts_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_wr_txid_sts_1_u; + +/* Define the union csr_am_curr_wr_txid_sts_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 curr_wr_txid_sts_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_curr_wr_txid_sts_2_u; + +/* Define the union csr_am_alarm_rresp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alarm_rresp_0 : 1; /* [0] */ + u32 alarm_rresp_1 : 1; /* [1] */ + u32 alarm_rresp_2 : 1; /* [2] */ + u32 alarm_rresp_3 : 1; /* [3] */ + u32 rsv_24 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_alarm_rresp_u; + +/* Define the union csr_am_alarm_bresp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alarm_bresp_0 : 1; /* [0] */ + u32 alarm_bresp_1 : 1; /* [1] */ + u32 alarm_bresp_2 : 1; /* [2] */ + u32 alarm_bresp_3 : 1; /* [3] */ + u32 rsv_25 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_am_alarm_bresp_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_am_ctrl_global_u am_ctrl_global; /* 0 */ + volatile csr_am_ctrl_latency_sel_u am_ctrl_latency_sel; /* 4 */ + volatile csr_am_ctrl_ptl_wr_u am_ctrl_ptl_wr; /* 8 */ + volatile csr_am_cfg_max_trans_u am_cfg_max_trans; /* 10 */ + volatile csr_am_cfg_single_port_max_trans_u am_cfg_single_port_max_trans; /* 14 */ + volatile csr_am_cfg_port_rd_en_u am_cfg_port_rd_en; /* 18 */ + volatile csr_am_cfg_port_wr_en_u am_cfg_port_wr_en; /* 1C */ + volatile csr_am_curr_aw_w_fifo_sts_u am_curr_aw_w_fifo_sts; /* 20 */ + volatile csr_am_curr_port_sts_u am_curr_port_sts; /* 100 */ + volatile csr_am_rob_ecc_int_sts_u am_rob_ecc_int_sts; /* 104 */ + volatile csr_am_rob_ecc_int_mask_u am_rob_ecc_int_mask; /* 108 */ + volatile csr_am_rob_ecc_err_addr_u am_rob_ecc_err_addr; /* 10C */ + volatile csr_am_curr_max_rd_latency_u am_curr_max_rd_latency; /* 110 */ + volatile csr_am_curr_ava_rd_latency_u am_curr_ava_rd_latency; /* 114 */ + volatile csr_am_curr_rd_latency_u am_curr_rd_latency; /* 118 */ + volatile csr_am_curr_max_wr_latency_u am_curr_max_wr_latency; /* 130 */ + volatile csr_am_curr_ava_wr_latency_u am_curr_ava_wr_latency; /* 134 */ + volatile csr_am_curr_wr_latency_u am_curr_wr_latency; /* 138 */ + volatile csr_am_curr_trans_return_u am_curr_trans_return; /* 150 */ + volatile csr_am_curr_rd_max_txid_u am_curr_rd_max_txid; /* 154 */ + volatile csr_am_curr_wr_max_txid_u am_curr_wr_max_txid; /* 158 */ + volatile csr_am_curr_rd_txid_sts_0_u am_curr_rd_txid_sts_0; /* 160 */ + volatile csr_am_curr_rd_txid_sts_1_u am_curr_rd_txid_sts_1; /* 164 */ + volatile csr_am_curr_rd_txid_sts_2_u am_curr_rd_txid_sts_2; /* 168 */ + volatile csr_am_curr_wr_txid_sts_0_u am_curr_wr_txid_sts_0; /* 170 */ + volatile csr_am_curr_wr_txid_sts_1_u am_curr_wr_txid_sts_1; /* 174 */ + volatile csr_am_curr_wr_txid_sts_2_u am_curr_wr_txid_sts_2; /* 178 */ + volatile csr_am_alarm_rresp_u am_alarm_rresp; /* 180 */ + volatile csr_am_alarm_bresp_u am_alarm_bresp; /* 184 */ +} S_am_ooo_cfg_REGS_TYPE; + +/* Declare the struct pointor of the module am_ooo_cfg */ +extern volatile S_am_ooo_cfg_REGS_TYPE *gopam_ooo_cfgAllReg; + +/* Declare the functions that set the member value */ +int iSetAM_CTRL_GLOBAL_ctrl_shutdown_req(unsigned int uctrl_shutdown_req); +int iSetAM_CTRL_GLOBAL_ctrl_lat_stat_rd_en(unsigned int uctrl_lat_stat_rd_en); +int iSetAM_CTRL_GLOBAL_ctrl_lat_stat_wr_en(unsigned int uctrl_lat_stat_wr_en); +int iSetAM_CTRL_GLOBAL_rd_rate_limit(unsigned int urd_rate_limit); +int iSetAM_CTRL_GLOBAL_wr_rate_limit(unsigned int uwr_rate_limit); +int iSetAM_CTRL_GLOBAL_ctrl_en_rd_256byte_global(unsigned int uctrl_en_rd_256byte_global); +int iSetAM_CTRL_GLOBAL_ctrl_en_wr_256byte_global(unsigned int uctrl_en_wr_256byte_global); +int iSetAM_CTRL_GLOBAL_ctrl_clkgt_en(unsigned int uctrl_clkgt_en); +int iSetAM_CTRL_LATENCY_SEL_ctrl_lat_rd_port_sel(unsigned int uctrl_lat_rd_port_sel); +int iSetAM_CTRL_LATENCY_SEL_ctrl_lat_wr_port_sel(unsigned int uctrl_lat_wr_port_sel); +int iSetAM_CTRL_PTL_WR_ctrl_ptl_wr_64byte(unsigned int uctrl_ptl_wr_64byte); +int iSetAM_CFG_MAX_TRANS_cfg_max_rd_trans(unsigned int ucfg_max_rd_trans); +int iSetAM_CFG_MAX_TRANS_cfg_max_wr_trans(unsigned int ucfg_max_wr_trans); +int iSetAM_CFG_SINGLE_PORT_MAX_TRANS_cfg_max_sgl_port_rd_trans(unsigned int ucfg_max_sgl_port_rd_trans); +int iSetAM_CFG_SINGLE_PORT_MAX_TRANS_cfg_max_sgl_port_wr_trans(unsigned int ucfg_max_sgl_port_wr_trans); +int iSetAM_CFG_PORT_RD_EN_cfg_port_rd_en(unsigned int ucfg_port_rd_en); +int iSetAM_CFG_PORT_WR_EN_cfg_port_wr_en(unsigned int ucfg_port_wr_en); +int iSetAM_CURR_AW_W_FIFO_STS_curr_w_tx_port(unsigned int ucurr_w_tx_port); +int iSetAM_CURR_AW_W_FIFO_STS_curr_w_tx_stock(unsigned int ucurr_w_tx_stock); +int iSetAM_CURR_AW_W_FIFO_STS_curr_w_tx_idle(unsigned int ucurr_w_tx_idle); +int iSetAM_CURR_PORT_STS_curr_rd_port_sts(unsigned int ucurr_rd_port_sts); +int iSetAM_CURR_PORT_STS_curr_wr_port_sts(unsigned int ucurr_wr_port_sts); +int iSetAM_ROB_ECC_INT_STS_rob_ecc_err_onebit(unsigned int urob_ecc_err_onebit); +int iSetAM_ROB_ECC_INT_STS_rob_ecc_err_multpl(unsigned int urob_ecc_err_multpl); +int iSetAM_ROB_ECC_INT_MASK_cfg_ecc_err_detect_int_msk(unsigned int ucfg_ecc_err_detect_int_msk); +int iSetAM_ROB_ECC_INT_MASK_cfg_ecc_err_multpl_int_msk(unsigned int ucfg_ecc_err_multpl_int_msk); +int iSetAM_ROB_ECC_ERR_ADDR_rob_ecc_onebit_err_addr(unsigned int urob_ecc_onebit_err_addr); +int iSetAM_ROB_ECC_ERR_ADDR_rob_ecc_multpl_err_addr(unsigned int urob_ecc_multpl_err_addr); +int iSetAM_CURR_MAX_RD_LATENCY_curr_max_rd_latency(unsigned int ucurr_max_rd_latency); +int iSetAM_CURR_AVA_RD_LATENCY_curr_ava_rd_latency(unsigned int ucurr_ava_rd_latency); +int iSetAM_CURR_RD_LATENCY_curr_rd_latency(unsigned int ucurr_rd_latency); +int iSetAM_CURR_MAX_WR_LATENCY_curr_max_wr_latency(unsigned int ucurr_max_wr_latency); +int iSetAM_CURR_AVA_WR_LATENCY_curr_ava_wr_latency(unsigned int ucurr_ava_wr_latency); +int iSetAM_CURR_WR_LATENCY_curr_wr_latency(unsigned int ucurr_wr_latency); +int iSetAM_CURR_TRANS_RETURN_curr_all_rd_returned(unsigned int ucurr_all_rd_returned); +int iSetAM_CURR_TRANS_RETURN_curr_all_wr_returned(unsigned int ucurr_all_wr_returned); +int iSetAM_CURR_RD_MAX_TXID_curr_rd_max_txid(unsigned int ucurr_rd_max_txid); +int iSetAM_CURR_WR_MAX_TXID_curr_wr_max_txid(unsigned int ucurr_wr_max_txid); +int iSetAM_CURR_RD_TXID_STS_0_curr_rd_txid_sts_0(unsigned int ucurr_rd_txid_sts_0); +int iSetAM_CURR_RD_TXID_STS_1_curr_rd_txid_sts_1(unsigned int ucurr_rd_txid_sts_1); +int iSetAM_CURR_RD_TXID_STS_2_curr_rd_txid_sts_2(unsigned int ucurr_rd_txid_sts_2); +int iSetAM_CURR_WR_TXID_STS_0_curr_wr_txid_sts_0(unsigned int ucurr_wr_txid_sts_0); +int iSetAM_CURR_WR_TXID_STS_1_curr_wr_txid_sts_1(unsigned int ucurr_wr_txid_sts_1); +int iSetAM_CURR_WR_TXID_STS_2_curr_wr_txid_sts_2(unsigned int ucurr_wr_txid_sts_2); +int iSetAM_ALARM_RRESP_alarm_rresp_0(unsigned int ualarm_rresp_0); +int iSetAM_ALARM_RRESP_alarm_rresp_1(unsigned int ualarm_rresp_1); +int iSetAM_ALARM_RRESP_alarm_rresp_2(unsigned int ualarm_rresp_2); +int iSetAM_ALARM_RRESP_alarm_rresp_3(unsigned int ualarm_rresp_3); +int iSetAM_ALARM_BRESP_alarm_bresp_0(unsigned int ualarm_bresp_0); +int iSetAM_ALARM_BRESP_alarm_bresp_1(unsigned int ualarm_bresp_1); +int iSetAM_ALARM_BRESP_alarm_bresp_2(unsigned int ualarm_bresp_2); +int iSetAM_ALARM_BRESP_alarm_bresp_3(unsigned int ualarm_bresp_3); + +/* Define the union csr_cryptorx_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptorx_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptorx_version_u; + +/* Define the union csr_cryptorx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_0 : 3; /* [26:24] */ + u32 crx_enable : 1; /* [27] */ + u32 crx_int_issue : 1; /* [28] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptorx_int_vector_u; + +/* Define the union csr_cryptorx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_int_data : 4; /* [3:0] */ + u32 rsv_2 : 12; /* [15:4] */ + u32 crx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptorx_int_u; + +/* Define the union csr_cryptorx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_int_en : 4; /* [3:0] */ + u32 rsv_3 : 12; /* [15:4] */ + u32 crx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptorx_int_en_u; + +/* Define the union csr_crx_lp_top_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_lp_top_err : 1; /* [0] */ + u32 crx_lp_top_err_inj : 1; /* [1] */ + u32 crx_lp_top_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_lp_top_err_u; + +/* Define the union csr_crx_lp_gcm_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_lp_gcm_err : 1; /* [0] */ + u32 crx_lp_gcm_err_inj : 1; /* [1] */ + u32 crx_lp_gcm_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_lp_gcm_err_u; + +/* Define the union csr_crx_lp_cbc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_lp_cbc_err : 1; /* [0] */ + u32 crx_lp_cbc_err_inj : 1; /* [1] */ + u32 crx_lp_cbc_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_lp_cbc_err_u; + +/* Define the union csr_crx_xts_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_xts_err : 1; /* [0] */ + u32 crx_xts_err_inj : 1; /* [1] */ + u32 crx_xts_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_xts_err_u; + +/* Define the union csr_crx_tmout_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_tmout_cfg : 24; /* [23:0] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_tmout_cfg_u; + +/* Define the union csr_ipsec_rx_crg_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_ipsec_rx : 1; /* [0] */ + u32 icg_en_ipsec_csr_rx : 1; /* [1] */ + u32 icg_en_cbc_rx : 1; /* [2] */ + u32 icg_en_gcm_rx : 1; /* [3] */ + u32 rsv_5 : 4; /* [7:4] */ + u32 srst_req_ipsec_rx : 1; /* [8] */ + u32 srst_req_ipsec_csr_rx : 1; /* [9] */ + u32 srst_req_cbc_rx : 1; /* [10] */ + u32 srst_req_gcm_rx : 1; /* [11] */ + u32 rsv_6 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_rx_crg_cfg_u; + +/* Define the union csr_crx_mem_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_mem_init : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_mem_init_u; + +/* Define the union csr_crx_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_mem_init_done : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_mem_init_done_u; + +/* Define the union csr_crx_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_mem_power_mode : 6; /* [5:0] */ + u32 crx_tp_ram_tmod : 8; /* [13:6] */ + u32 crx_sp_ram_tmod : 7; /* [20:14] */ + u32 crx_ecc_bypass : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_mem_ctrl_u; + +/* Define the union csr_crx_reg_cnt_clr_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_clr_ce : 1; /* [0] */ + u32 snap_en : 1; /* [1] */ + u32 rsv_10 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_reg_cnt_clr_ce_u; + +/* Define the union csr_crx_chx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_gcm_ch_cfg : 5; /* [4:0] */ + u32 rsv_11 : 3; /* [7:5] */ + u32 crx_cbc_ch_cfg : 5; /* [12:8] */ + u32 rsv_12 : 3; /* [15:13] */ + u32 crx_xts_ch_cfg : 5; /* [20:16] */ + u32 rsv_13 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_chx_cfg_u; + +/* Define the union csr_crx_credit_o_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_pkt_credit_o_cfg : 6; /* [5:0] */ + u32 rsv_14 : 2; /* [7:6] */ + u32 crx_lpch_cmd_credit_o_cfg : 5; /* [12:8] */ + u32 rsv_15 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_credit_o_cfg_u; + +/* Define the union csr_crx_credit2_o_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_lpch_credit2_o_sum : 7; /* [6:0] */ + u32 rsv_16 : 1; /* [7] */ + u32 crx_gcm_credit2_o_cfg : 7; /* [14:8] */ + u32 rsv_17 : 1; /* [15] */ + u32 crx_cbc_credit2_o_cfg : 7; /* [22:16] */ + u32 rsv_18 : 1; /* [23] */ + u32 crx_prealc_pkt_credit2 : 4; /* [27:24] */ + u32 rsv_19 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_credit2_o_cfg_u; + +/* Define the union csr_crx_ctrl_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_ctrl_rsv : 24; /* [23:0] */ + u32 rsv_20 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_ctrl_rsv_u; + +/* Define the union csr_crx_stat_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_stat_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_stat_rsv_u; + +/* Define the union csr_crx_ept_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_ept : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_ept_u; + +/* Define the union csr_crx_full_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_full : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_full_u; + +/* Define the union csr_crx_dft_mem_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_dft_mem_ctrl_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_dft_mem_ctrl_0_u; + +/* Define the union csr_crx_dft_mem_ctrl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_dft_mem_ctrl_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_dft_mem_ctrl_1_u; + +/* Define the union csr_crx_dft_mem_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_dft_mem_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_dft_mem_ctrl_2_u; + +/* Define the union csr_crx_dft_mem_ctrl_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_dft_mem_ctrl_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_dft_mem_ctrl_3_u; + +/* Define the union csr_crx_dft_mem_ctrl_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_dft_mem_ctrl_4 : 6; /* [5:0] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_dft_mem_ctrl_4_u; + +/* Define the union csr_crx_err1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_ecc_err1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_err1_cnt_u; + +/* Define the union csr_crx_ecc_err2_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_ecc_err2_addr : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_ecc_err2_addr_u; + +/* Define the union csr_crx_top_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_top_int_en : 8; /* [7:0] */ + u32 rsv_23 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_top_int_en_u; + +/* Define the union csr_crx_top_alm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_top_alm : 8; /* [7:0] */ + u32 rsv_24 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_top_alm_u; + +/* Define the union csr_crx_credit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_gcm_credit_i_err : 1; /* [0] */ + u32 crx_cbc_credit_i_err : 1; /* [1] */ + u32 crx_xts_credit_i_err : 1; /* [2] */ + u32 rsv_25 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_credit_err_u; + +/* Define the union csr_crx_inn_credit_i_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_gcm_inn_credit_i_err : 1; /* [0] */ + u32 crx_cbc_inn_credit_i_err : 1; /* [1] */ + u32 crx_xts_inn_credit_i_err : 1; /* [2] */ + u32 rsv_26 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_inn_credit_i_err_u; + +/* Define the union csr_crx_pkt_cnt_i_pre_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_pkt_cnt_i_pre : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_pkt_cnt_i_pre_u; + +/* Define the union csr_crx_chk_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_chk_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_chk_err_cnt_u; + +/* Define the union csr_crx_tfc_pad_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_tfc_pad_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_tfc_pad_err_cnt_u; + +/* Define the union csr_crx_other_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_other_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_other_err_cnt_u; + +/* Define the union csr_crx_pkt_cnt_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_pkt_cnt_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_pkt_cnt_i_u; + +/* Define the union csr_crx_pkt_cnt_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_pkt_cnt_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_pkt_cnt_o_u; + +/* Define the union csr_cryptorx_if_i_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptorx_if_i_cnt : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptorx_if_i_cnt_u; + +/* Define the union csr_crx_bdsplit_len_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_bdsplit_len_i : 12; /* [11:0] */ + u32 rsv_29 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_bdsplit_len_i_u; + +/* Define the union csr_crx_bdsplit_len_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_bdsplit_len_o : 12; /* [11:0] */ + u32 rsv_30 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_bdsplit_len_o_u; + +/* Define the union csr_crx_pkt_cmb_len_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 crx_pkt_cmb_len_o : 12; /* [11:0] */ + u32 rsv_31 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_crx_pkt_cmb_len_o_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cryptorx_version_u cryptorx_version; /* 0 */ + volatile csr_cryptorx_int_vector_u cryptorx_int_vector; /* 60 */ + volatile csr_cryptorx_int_u cryptorx_int; /* 64 */ + volatile csr_cryptorx_int_en_u cryptorx_int_en; /* 68 */ + volatile csr_crx_lp_top_err_u crx_lp_top_err; /* 6C */ + volatile csr_crx_lp_gcm_err_u crx_lp_gcm_err; /* 70 */ + volatile csr_crx_lp_cbc_err_u crx_lp_cbc_err; /* 74 */ + volatile csr_crx_xts_err_u crx_xts_err; /* 78 */ + volatile csr_crx_tmout_cfg_u crx_tmout_cfg; /* 80 */ + volatile csr_ipsec_rx_crg_cfg_u ipsec_rx_crg_cfg; /* 84 */ + volatile csr_crx_mem_init_u crx_mem_init; /* 100 */ + volatile csr_crx_mem_init_done_u crx_mem_init_done; /* 104 */ + volatile csr_crx_mem_ctrl_u crx_mem_ctrl; /* 108 */ + volatile csr_crx_reg_cnt_clr_ce_u crx_reg_cnt_clr_ce; /* 10C */ + volatile csr_crx_chx_cfg_u crx_chx_cfg; /* 120 */ + volatile csr_crx_credit_o_cfg_u crx_credit_o_cfg; /* 128 */ + volatile csr_crx_credit2_o_cfg_u crx_credit2_o_cfg; /* 12C */ + volatile csr_crx_ctrl_rsv_u crx_ctrl_rsv; /* 130 */ + volatile csr_crx_stat_rsv_u crx_stat_rsv; /* 134 */ + volatile csr_crx_ept_u crx_ept; /* 138 */ + volatile csr_crx_full_u crx_full; /* 13C */ + volatile csr_crx_dft_mem_ctrl_0_u crx_dft_mem_ctrl_0; /* 150 */ + volatile csr_crx_dft_mem_ctrl_1_u crx_dft_mem_ctrl_1; /* 154 */ + volatile csr_crx_dft_mem_ctrl_2_u crx_dft_mem_ctrl_2; /* 158 */ + volatile csr_crx_dft_mem_ctrl_3_u crx_dft_mem_ctrl_3; /* 15C */ + volatile csr_crx_dft_mem_ctrl_4_u crx_dft_mem_ctrl_4; /* 160 */ + volatile csr_crx_err1_cnt_u crx_err1_cnt; /* 170 */ + volatile csr_crx_ecc_err2_addr_u crx_ecc_err2_addr; /* 174 */ + volatile csr_crx_top_int_en_u crx_top_int_en; /* 178 */ + volatile csr_crx_top_alm_u crx_top_alm; /* 17C */ + volatile csr_crx_credit_err_u crx_credit_err; /* 200 */ + volatile csr_crx_inn_credit_i_err_u crx_inn_credit_i_err; /* 204 */ + volatile csr_crx_pkt_cnt_i_pre_u crx_pkt_cnt_i_pre[3]; /* 310 */ + volatile csr_crx_chk_err_cnt_u crx_chk_err_cnt; /* 320 */ + volatile csr_crx_tfc_pad_err_cnt_u crx_tfc_pad_err_cnt; /* 324 */ + volatile csr_crx_other_err_cnt_u crx_other_err_cnt; /* 328 */ + volatile csr_crx_pkt_cnt_i_u crx_pkt_cnt_i[3]; /* 210 */ + volatile csr_crx_pkt_cnt_o_u crx_pkt_cnt_o[3]; /* 220 */ + volatile csr_cryptorx_if_i_cnt_u cryptorx_if_i_cnt[3]; /* 280 */ + volatile csr_crx_bdsplit_len_i_u crx_bdsplit_len_i[3]; /* 2A0 */ + volatile csr_crx_bdsplit_len_o_u crx_bdsplit_len_o[3]; /* 2C0 */ + volatile csr_crx_pkt_cmb_len_o_u crx_pkt_cmb_len_o[3]; /* 2E0 */ +} S_cryptorx_inout_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cryptorx_inout_csr */ +extern volatile S_cryptorx_inout_csr_REGS_TYPE *gopcryptorx_inout_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCRYPTORX_VERSION_cryptorx_version(unsigned int ucryptorx_version); +int iSetCRYPTORX_INT_VECTOR_crx_cpi_int_index(unsigned int ucrx_cpi_int_index); +int iSetCRYPTORX_INT_VECTOR_crx_enable(unsigned int ucrx_enable); +int iSetCRYPTORX_INT_VECTOR_crx_int_issue(unsigned int ucrx_int_issue); +int iSetCRYPTORX_INT_crx_int_data(unsigned int ucrx_int_data); +int iSetCRYPTORX_INT_crx_program_csr_id_ro(unsigned int ucrx_program_csr_id_ro); +int iSetCRYPTORX_INT_EN_crx_int_en(unsigned int ucrx_int_en); +int iSetCRYPTORX_INT_EN_crx_program_csr_id(unsigned int ucrx_program_csr_id); +int iSetCRX_LP_TOP_ERR_crx_lp_top_err(unsigned int ucrx_lp_top_err); +int iSetCRX_LP_TOP_ERR_crx_lp_top_err_inj(unsigned int ucrx_lp_top_err_inj); +int iSetCRX_LP_TOP_ERR_crx_lp_top_err_sticky(unsigned int ucrx_lp_top_err_sticky); +int iSetCRX_LP_GCM_ERR_crx_lp_gcm_err(unsigned int ucrx_lp_gcm_err); +int iSetCRX_LP_GCM_ERR_crx_lp_gcm_err_inj(unsigned int ucrx_lp_gcm_err_inj); +int iSetCRX_LP_GCM_ERR_crx_lp_gcm_err_sticky(unsigned int ucrx_lp_gcm_err_sticky); +int iSetCRX_LP_CBC_ERR_crx_lp_cbc_err(unsigned int ucrx_lp_cbc_err); +int iSetCRX_LP_CBC_ERR_crx_lp_cbc_err_inj(unsigned int ucrx_lp_cbc_err_inj); +int iSetCRX_LP_CBC_ERR_crx_lp_cbc_err_sticky(unsigned int ucrx_lp_cbc_err_sticky); +int iSetCRX_XTS_ERR_crx_xts_err(unsigned int ucrx_xts_err); +int iSetCRX_XTS_ERR_crx_xts_err_inj(unsigned int ucrx_xts_err_inj); +int iSetCRX_XTS_ERR_crx_xts_err_sticky(unsigned int ucrx_xts_err_sticky); +int iSetCRX_TMOUT_CFG_crx_tmout_cfg(unsigned int ucrx_tmout_cfg); +int iSetIPSEC_RX_CRG_CFG_icg_en_ipsec_rx(unsigned int uicg_en_ipsec_rx); +int iSetIPSEC_RX_CRG_CFG_icg_en_ipsec_csr_rx(unsigned int uicg_en_ipsec_csr_rx); +int iSetIPSEC_RX_CRG_CFG_icg_en_cbc_rx(unsigned int uicg_en_cbc_rx); +int iSetIPSEC_RX_CRG_CFG_icg_en_gcm_rx(unsigned int uicg_en_gcm_rx); +int iSetIPSEC_RX_CRG_CFG_srst_req_ipsec_rx(unsigned int usrst_req_ipsec_rx); +int iSetIPSEC_RX_CRG_CFG_srst_req_ipsec_csr_rx(unsigned int usrst_req_ipsec_csr_rx); +int iSetIPSEC_RX_CRG_CFG_srst_req_cbc_rx(unsigned int usrst_req_cbc_rx); +int iSetIPSEC_RX_CRG_CFG_srst_req_gcm_rx(unsigned int usrst_req_gcm_rx); +int iSetCRX_MEM_INIT_crx_mem_init(unsigned int ucrx_mem_init); +int iSetCRX_MEM_INIT_DONE_crx_mem_init_done(unsigned int ucrx_mem_init_done); +int iSetCRX_MEM_CTRL_crx_mem_power_mode(unsigned int ucrx_mem_power_mode); +int iSetCRX_MEM_CTRL_crx_tp_ram_tmod(unsigned int ucrx_tp_ram_tmod); +int iSetCRX_MEM_CTRL_crx_sp_ram_tmod(unsigned int ucrx_sp_ram_tmod); +int iSetCRX_MEM_CTRL_crx_ecc_bypass(unsigned int ucrx_ecc_bypass); +int iSetCRX_REG_CNT_CLR_CE_cnt_clr_ce(unsigned int ucnt_clr_ce); +int iSetCRX_REG_CNT_CLR_CE_snap_en(unsigned int usnap_en); +int iSetCRX_CHX_CFG_crx_gcm_ch_cfg(unsigned int ucrx_gcm_ch_cfg); +int iSetCRX_CHX_CFG_crx_cbc_ch_cfg(unsigned int ucrx_cbc_ch_cfg); +int iSetCRX_CHX_CFG_crx_xts_ch_cfg(unsigned int ucrx_xts_ch_cfg); +int iSetCRX_CREDIT_O_CFG_crx_pkt_credit_o_cfg(unsigned int ucrx_pkt_credit_o_cfg); +int iSetCRX_CREDIT_O_CFG_crx_lpch_cmd_credit_o_cfg(unsigned int ucrx_lpch_cmd_credit_o_cfg); +int iSetCRX_CREDIT2_O_CFG_crx_lpch_credit2_o_sum(unsigned int ucrx_lpch_credit2_o_sum); +int iSetCRX_CREDIT2_O_CFG_crx_gcm_credit2_o_cfg(unsigned int ucrx_gcm_credit2_o_cfg); +int iSetCRX_CREDIT2_O_CFG_crx_cbc_credit2_o_cfg(unsigned int ucrx_cbc_credit2_o_cfg); +int iSetCRX_CREDIT2_O_CFG_crx_prealc_pkt_credit2(unsigned int ucrx_prealc_pkt_credit2); +int iSetCRX_CTRL_RSV_crx_ctrl_rsv(unsigned int ucrx_ctrl_rsv); +int iSetCRX_STAT_RSV_crx_stat_rsv(unsigned int ucrx_stat_rsv); +int iSetCRX_EPT_crx_ept(unsigned int ucrx_ept); +int iSetCRX_FULL_crx_full(unsigned int ucrx_full); +int iSetCRX_DFT_MEM_CTRL_0_crx_dft_mem_ctrl_0(unsigned int ucrx_dft_mem_ctrl_0); +int iSetCRX_DFT_MEM_CTRL_1_crx_dft_mem_ctrl_1(unsigned int ucrx_dft_mem_ctrl_1); +int iSetCRX_DFT_MEM_CTRL_2_crx_dft_mem_ctrl_2(unsigned int ucrx_dft_mem_ctrl_2); +int iSetCRX_DFT_MEM_CTRL_3_crx_dft_mem_ctrl_3(unsigned int ucrx_dft_mem_ctrl_3); +int iSetCRX_DFT_MEM_CTRL_4_crx_dft_mem_ctrl_4(unsigned int ucrx_dft_mem_ctrl_4); +int iSetCRX_ERR1_CNT_crx_ecc_err1_cnt(unsigned int ucrx_ecc_err1_cnt); +int iSetCRX_ECC_ERR2_ADDR_crx_ecc_err2_addr(unsigned int ucrx_ecc_err2_addr); +int iSetCRX_TOP_INT_EN_crx_top_int_en(unsigned int ucrx_top_int_en); +int iSetCRX_TOP_ALM_crx_top_alm(unsigned int ucrx_top_alm); +int iSetCRX_CREDIT_ERR_crx_gcm_credit_i_err(unsigned int ucrx_gcm_credit_i_err); +int iSetCRX_CREDIT_ERR_crx_cbc_credit_i_err(unsigned int ucrx_cbc_credit_i_err); +int iSetCRX_CREDIT_ERR_crx_xts_credit_i_err(unsigned int ucrx_xts_credit_i_err); +int iSetCRX_INN_CREDIT_I_ERR_crx_gcm_inn_credit_i_err(unsigned int ucrx_gcm_inn_credit_i_err); +int iSetCRX_INN_CREDIT_I_ERR_crx_cbc_inn_credit_i_err(unsigned int ucrx_cbc_inn_credit_i_err); +int iSetCRX_INN_CREDIT_I_ERR_crx_xts_inn_credit_i_err(unsigned int ucrx_xts_inn_credit_i_err); +int iSetCRX_PKT_CNT_I_PRE_crx_pkt_cnt_i_pre(unsigned int ucrx_pkt_cnt_i_pre); +int iSetCRX_CHK_ERR_CNT_crx_chk_err_cnt(unsigned int ucrx_chk_err_cnt); +int iSetCRX_TFC_PAD_ERR_CNT_crx_tfc_pad_err_cnt(unsigned int ucrx_tfc_pad_err_cnt); +int iSetCRX_OTHER_ERR_CNT_crx_other_err_cnt(unsigned int ucrx_other_err_cnt); +int iSetCRX_PKT_CNT_I_crx_pkt_cnt_i(unsigned int ucrx_pkt_cnt_i); +int iSetCRX_PKT_CNT_O_crx_pkt_cnt_o(unsigned int ucrx_pkt_cnt_o); +int iSetCRYPTORX_IF_I_CNT_cryptorx_if_i_cnt(unsigned int ucryptorx_if_i_cnt); +int iSetCRX_BDSPLIT_LEN_I_crx_bdsplit_len_i(unsigned int ucrx_bdsplit_len_i); +int iSetCRX_BDSPLIT_LEN_O_crx_bdsplit_len_o(unsigned int ucrx_bdsplit_len_o); +int iSetCRX_PKT_CMB_LEN_O_crx_pkt_cmb_len_o(unsigned int ucrx_pkt_cmb_len_o); + +/* Define the union csr_ctx_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptotx_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_version_u; + +/* Define the union csr_ctx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_0 : 3; /* [26:24] */ + u32 ctx_enable : 1; /* [27] */ + u32 ctx_int_issue : 1; /* [28] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_int_vector_u; + +/* Define the union csr_ctx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_int_data : 5; /* [4:0] */ + u32 rsv_2 : 11; /* [15:5] */ + u32 ctx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_int_u; + +/* Define the union csr_ctx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_int_en : 5; /* [4:0] */ + u32 rsv_3 : 11; /* [15:5] */ + u32 ctx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_int_en_u; + +/* Define the union csr_ctx_top_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_top_err : 1; /* [0] */ + u32 ctx_top_err_inj : 1; /* [1] */ + u32 ctx_top_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_top_err_u; + +/* Define the union csr_ctx_lp_gcm_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_gcm_err : 1; /* [0] */ + u32 ctx_lp_gcm_err_inj : 1; /* [1] */ + u32 ctx_lp_gcm_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_gcm_err_u; + +/* Define the union csr_ctx_lp_cbc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_cbc_err : 1; /* [0] */ + u32 ctx_lp_cbc_err_inj : 1; /* [1] */ + u32 ctx_lp_cbc_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_cbc_err_u; + +/* Define the union csr_ctx_ec_xts_ec_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_xts_ec_err : 1; /* [0] */ + u32 ctx_ec_xts_ec_err_inj : 1; /* [1] */ + u32 ctx_ec_xts_ec_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_xts_ec_err_u; + +/* Define the union csr_ctx_ec_xts_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_xts_err : 1; /* [0] */ + u32 ctx_ec_xts_err_inj : 1; /* [1] */ + u32 ctx_ec_xts_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_xts_err_u; + +/* Define the union csr_ctx_tmout_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_tmout_cfg : 24; /* [23:0] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_tmout_cfg_u; + +/* Define the union csr_ipsec_tx_crg_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icg_en_ipsec_tx : 1; /* [0] */ + u32 icg_en_ipsec_csr_tx : 1; /* [1] */ + u32 icg_en_cbc_tx : 1; /* [2] */ + u32 icg_en_gcm_tx : 1; /* [3] */ + u32 rsv_5 : 4; /* [7:4] */ + u32 srst_req_ipsec_tx : 1; /* [8] */ + u32 srst_req_ipsec_csr_tx : 1; /* [9] */ + u32 srst_req_cbc_tx : 1; /* [10] */ + u32 srst_req_gcm_tx : 1; /* [11] */ + u32 rsv_6 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_tx_crg_cfg_u; + +/* Define the union csr_ctx_mem_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_mem_init : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_mem_init_u; + +/* Define the union csr_ctx_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_mem_init_done : 1; /* [0] */ + u32 rsv_8 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_mem_init_done_u; + +/* Define the union csr_ctx_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_mem_power_mode : 6; /* [5:0] */ + u32 ctx_tp_ram_tmod : 8; /* [13:6] */ + u32 ctx_sp_ram_tmod : 7; /* [20:14] */ + u32 ctx_ecc_bypass : 1; /* [21] */ + u32 rsv_9 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_mem_ctrl_u; + +/* Define the union csr_ctx_reg_cnt_clr_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_clr_ce : 1; /* [0] */ + u32 snap_en : 1; /* [1] */ + u32 rsv_10 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_reg_cnt_clr_ce_u; + +/* Define the union csr_ctx_lp_chx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_gcm_ch_cfg : 5; /* [4:0] */ + u32 rsv_11 : 3; /* [7:5] */ + u32 ctx_cbc_ch_cfg : 5; /* [12:8] */ + u32 rsv_12 : 3; /* [15:13] */ + u32 ctx_rsa_ch_cfg : 5; /* [20:16] */ + u32 rsv_13 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_chx_cfg_u; + +/* Define the union csr_ctx_ec_chx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_xts_ec_ch_cfg : 5; /* [4:0] */ + u32 rsv_14 : 3; /* [7:5] */ + u32 ctx_xts_ch_cfg : 5; /* [12:8] */ + u32 rsv_15 : 3; /* [15:13] */ + u32 ctx_ec_ch_cfg : 5; /* [20:16] */ + u32 rsv_16 : 3; /* [23:21] */ + u32 ctx_mhd_ch_cfg : 5; /* [28:24] */ + u32 rsv_17 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_chx_cfg_u; + +/* Define the union csr_ctx_necch_credit_o_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_necch_credit_o_cfg : 5; /* [4:0] */ + u32 rsv_18 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_necch_credit_o_cfg_u; + +/* Define the union csr_ctx_ecch_credit_o_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ecch_credit_o_cfg : 5; /* [4:0] */ + u32 rsv_19 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ecch_credit_o_cfg_u; + +/* Define the union csr_ctx_ctrl_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ctrl_rsv : 24; /* [23:0] */ + u32 rsv_20 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ctrl_rsv_u; + +/* Define the union csr_ctx_stat_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_stat_rsv : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_stat_rsv_u; + +/* Define the union csr_ctx_lp_ept_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_ept : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_ept_u; + +/* Define the union csr_ctx_lp_full_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_full : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_full_u; + +/* Define the union csr_ctx_ec_ept_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_ept : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_ept_u; + +/* Define the union csr_ctx_ec_full_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_full : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_full_u; + +/* Define the union csr_ctx_dft_mem_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_dft_mem_ctrl_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_dft_mem_ctrl_0_u; + +/* Define the union csr_ctx_dft_mem_ctrl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_dft_mem_ctrl_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_dft_mem_ctrl_1_u; + +/* Define the union csr_ctx_dft_mem_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_dft_mem_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_dft_mem_ctrl_2_u; + +/* Define the union csr_ctx_dft_mem_ctrl_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_dft_mem_ctrl_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_dft_mem_ctrl_3_u; + +/* Define the union csr_ctx_dft_mem_ctrl_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_dft_mem_ctrl_4 : 6; /* [5:0] */ + u32 rsv_21 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_dft_mem_ctrl_4_u; + +/* Define the union csr_ctx_top_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_top_int_en : 8; /* [7:0] */ + u32 rsv_22 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_top_int_en_u; + +/* Define the union csr_ctx_top_alm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_top_alm : 8; /* [7:0] */ + u32 rsv_23 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_top_alm_u; + +/* Define the union csr_ctx_credit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_gcm_credit_i_err : 1; /* [0] */ + u32 ctx_cbc_credit_i_err : 1; /* [1] */ + u32 ctx_rsa_credit_i_err : 1; /* [2] */ + u32 ctx_xts_ec_credit_i_err : 1; /* [3] */ + u32 ctx_xts_credit_i_err : 1; /* [4] */ + u32 ctx_ec_credit_i_err : 1; /* [5] */ + u32 ctx_mhd_credit_i_err : 1; /* [6] */ + u32 ctx_byp_credit_i_err : 1; /* [7] */ + u32 rsv_24 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_credit_err_u; + +/* Define the union csr_ctx_inn_credit_i_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_gcm_inn_credit_i_err : 1; /* [0] */ + u32 ctx_cbc_inn_credit_i_err : 1; /* [1] */ + u32 ctx_rsa_inn_credit_i_err : 1; /* [2] */ + u32 ctx_xts_ec_inn_credit_i_err : 1; /* [3] */ + u32 ctx_xts_inn_credit_i_err : 1; /* [4] */ + u32 rsv_25 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_inn_credit_i_err_u; + +/* Define the union csr_ctx_lp_pkt_cnt_i_pre_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_pkt_cnt_i_pre : 8; /* [7:0] */ + u32 rsv_26 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_pkt_cnt_i_pre_u; + +/* Define the union csr_ctx_ec_pkt_cnt_i_pre_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_pkt_cnt_i_pre : 8; /* [7:0] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_pkt_cnt_i_pre_u; + +/* Define the union csr_ctx_bd_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_bd_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_bd_err_cnt_u; + +/* Define the union csr_ctx_len_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_len_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_len_err_cnt_u; + +/* Define the union csr_ctx_lp_pkt_cnt_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_pkt_cnt_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_pkt_cnt_i_u; + +/* Define the union csr_ctx_ec_pkt_cnt_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_pkt_cnt_i : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_pkt_cnt_i_u; + +/* Define the union csr_ctx_lp_pkt_cnt_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_lp_pkt_cnt_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_lp_pkt_cnt_o_u; + +/* Define the union csr_ctx_ec_pkt_cnt_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_ec_pkt_cnt_o : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_ec_pkt_cnt_o_u; + +/* Define the union csr_cryptotx_if_i_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cryptotx_if_i_cnt : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cryptotx_if_i_cnt_u; + +/* Define the union csr_ctx_bdsplit_len_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_bdsplit_len_i : 12; /* [11:0] */ + u32 rsv_29 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_bdsplit_len_i_u; + +/* Define the union csr_ctx_bdsplit_len_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_bdsplit_len_o : 12; /* [11:0] */ + u32 rsv_30 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_bdsplit_len_o_u; + +/* Define the union csr_ctx_pkt_cmb_len_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctx_pkt_cmb_len_o : 12; /* [11:0] */ + u32 rsv_31 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ctx_pkt_cmb_len_o_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_ctx_version_u ctx_version; /* 0 */ + volatile csr_ctx_int_vector_u ctx_int_vector; /* 60 */ + volatile csr_ctx_int_u ctx_int; /* 64 */ + volatile csr_ctx_int_en_u ctx_int_en; /* 68 */ + volatile csr_ctx_top_err_u ctx_top_err; /* 6C */ + volatile csr_ctx_lp_gcm_err_u ctx_lp_gcm_err; /* 70 */ + volatile csr_ctx_lp_cbc_err_u ctx_lp_cbc_err; /* 74 */ + volatile csr_ctx_ec_xts_ec_err_u ctx_ec_xts_ec_err; /* 78 */ + volatile csr_ctx_ec_xts_err_u ctx_ec_xts_err; /* 7C */ + volatile csr_ctx_tmout_cfg_u ctx_tmout_cfg; /* 80 */ + volatile csr_ipsec_tx_crg_cfg_u ipsec_tx_crg_cfg; /* 84 */ + volatile csr_ctx_mem_init_u ctx_mem_init; /* 100 */ + volatile csr_ctx_mem_init_done_u ctx_mem_init_done; /* 104 */ + volatile csr_ctx_mem_ctrl_u ctx_mem_ctrl; /* 108 */ + volatile csr_ctx_reg_cnt_clr_ce_u ctx_reg_cnt_clr_ce; /* 10C */ + volatile csr_ctx_lp_chx_cfg_u ctx_lp_chx_cfg; /* 120 */ + volatile csr_ctx_ec_chx_cfg_u ctx_ec_chx_cfg; /* 124 */ + volatile csr_ctx_necch_credit_o_cfg_u ctx_necch_credit_o_cfg; /* 128 */ + volatile csr_ctx_ecch_credit_o_cfg_u ctx_ecch_credit_o_cfg; /* 12C */ + volatile csr_ctx_ctrl_rsv_u ctx_ctrl_rsv; /* 130 */ + volatile csr_ctx_stat_rsv_u ctx_stat_rsv; /* 134 */ + volatile csr_ctx_lp_ept_u ctx_lp_ept; /* 140 */ + volatile csr_ctx_lp_full_u ctx_lp_full; /* 144 */ + volatile csr_ctx_ec_ept_u ctx_ec_ept; /* 148 */ + volatile csr_ctx_ec_full_u ctx_ec_full; /* 14C */ + volatile csr_ctx_dft_mem_ctrl_0_u ctx_dft_mem_ctrl_0; /* 150 */ + volatile csr_ctx_dft_mem_ctrl_1_u ctx_dft_mem_ctrl_1; /* 154 */ + volatile csr_ctx_dft_mem_ctrl_2_u ctx_dft_mem_ctrl_2; /* 158 */ + volatile csr_ctx_dft_mem_ctrl_3_u ctx_dft_mem_ctrl_3; /* 15C */ + volatile csr_ctx_dft_mem_ctrl_4_u ctx_dft_mem_ctrl_4; /* 160 */ + volatile csr_ctx_top_int_en_u ctx_top_int_en; /* 178 */ + volatile csr_ctx_top_alm_u ctx_top_alm; /* 17C */ + volatile csr_ctx_credit_err_u ctx_credit_err; /* 200 */ + volatile csr_ctx_inn_credit_i_err_u ctx_inn_credit_i_err; /* 204 */ + volatile csr_ctx_lp_pkt_cnt_i_pre_u ctx_lp_pkt_cnt_i_pre[3]; /* 310 */ + volatile csr_ctx_ec_pkt_cnt_i_pre_u ctx_ec_pkt_cnt_i_pre[5]; /* 320 */ + volatile csr_ctx_bd_err_cnt_u ctx_bd_err_cnt; /* 340 */ + volatile csr_ctx_len_err_cnt_u ctx_len_err_cnt; /* 344 */ + volatile csr_ctx_lp_pkt_cnt_i_u ctx_lp_pkt_cnt_i[3]; /* 210 */ + volatile csr_ctx_ec_pkt_cnt_i_u ctx_ec_pkt_cnt_i[5]; /* 220 */ + volatile csr_ctx_lp_pkt_cnt_o_u ctx_lp_pkt_cnt_o[3]; /* 240 */ + volatile csr_ctx_ec_pkt_cnt_o_u ctx_ec_pkt_cnt_o[5]; /* 260 */ + volatile csr_cryptotx_if_i_cnt_u cryptotx_if_i_cnt[5]; /* 280 */ + volatile csr_ctx_bdsplit_len_i_u ctx_bdsplit_len_i[5]; /* 2A0 */ + volatile csr_ctx_bdsplit_len_o_u ctx_bdsplit_len_o[5]; /* 2C0 */ + volatile csr_ctx_pkt_cmb_len_o_u ctx_pkt_cmb_len_o[5]; /* 2E0 */ +} S_cryptotx_inout_csr_REGS_TYPE; + +/* Declare the struct pointor of the module cryptotx_inout_csr */ +extern volatile S_cryptotx_inout_csr_REGS_TYPE *gopcryptotx_inout_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCTX_VERSION_cryptotx_version(unsigned int ucryptotx_version); +int iSetCTX_INT_VECTOR_ctx_cpi_int_index(unsigned int uctx_cpi_int_index); +int iSetCTX_INT_VECTOR_ctx_enable(unsigned int uctx_enable); +int iSetCTX_INT_VECTOR_ctx_int_issue(unsigned int uctx_int_issue); +int iSetCTX_INT_ctx_int_data(unsigned int uctx_int_data); +int iSetCTX_INT_ctx_program_csr_id_ro(unsigned int uctx_program_csr_id_ro); +int iSetCTX_INT_EN_ctx_int_en(unsigned int uctx_int_en); +int iSetCTX_INT_EN_ctx_program_csr_id(unsigned int uctx_program_csr_id); +int iSetCTX_TOP_ERR_ctx_top_err(unsigned int uctx_top_err); +int iSetCTX_TOP_ERR_ctx_top_err_inj(unsigned int uctx_top_err_inj); +int iSetCTX_TOP_ERR_ctx_top_err_sticky(unsigned int uctx_top_err_sticky); +int iSetCTX_LP_GCM_ERR_ctx_lp_gcm_err(unsigned int uctx_lp_gcm_err); +int iSetCTX_LP_GCM_ERR_ctx_lp_gcm_err_inj(unsigned int uctx_lp_gcm_err_inj); +int iSetCTX_LP_GCM_ERR_ctx_lp_gcm_err_sticky(unsigned int uctx_lp_gcm_err_sticky); +int iSetCTX_LP_CBC_ERR_ctx_lp_cbc_err(unsigned int uctx_lp_cbc_err); +int iSetCTX_LP_CBC_ERR_ctx_lp_cbc_err_inj(unsigned int uctx_lp_cbc_err_inj); +int iSetCTX_LP_CBC_ERR_ctx_lp_cbc_err_sticky(unsigned int uctx_lp_cbc_err_sticky); +int iSetCTX_EC_XTS_EC_ERR_ctx_ec_xts_ec_err(unsigned int uctx_ec_xts_ec_err); +int iSetCTX_EC_XTS_EC_ERR_ctx_ec_xts_ec_err_inj(unsigned int uctx_ec_xts_ec_err_inj); +int iSetCTX_EC_XTS_EC_ERR_ctx_ec_xts_ec_err_sticky(unsigned int uctx_ec_xts_ec_err_sticky); +int iSetCTX_EC_XTS_ERR_ctx_ec_xts_err(unsigned int uctx_ec_xts_err); +int iSetCTX_EC_XTS_ERR_ctx_ec_xts_err_inj(unsigned int uctx_ec_xts_err_inj); +int iSetCTX_EC_XTS_ERR_ctx_ec_xts_err_sticky(unsigned int uctx_ec_xts_err_sticky); +int iSetCTX_TMOUT_CFG_ctx_tmout_cfg(unsigned int uctx_tmout_cfg); +int iSetIPSEC_TX_CRG_CFG_icg_en_ipsec_tx(unsigned int uicg_en_ipsec_tx); +int iSetIPSEC_TX_CRG_CFG_icg_en_ipsec_csr_tx(unsigned int uicg_en_ipsec_csr_tx); +int iSetIPSEC_TX_CRG_CFG_icg_en_cbc_tx(unsigned int uicg_en_cbc_tx); +int iSetIPSEC_TX_CRG_CFG_icg_en_gcm_tx(unsigned int uicg_en_gcm_tx); +int iSetIPSEC_TX_CRG_CFG_srst_req_ipsec_tx(unsigned int usrst_req_ipsec_tx); +int iSetIPSEC_TX_CRG_CFG_srst_req_ipsec_csr_tx(unsigned int usrst_req_ipsec_csr_tx); +int iSetIPSEC_TX_CRG_CFG_srst_req_cbc_tx(unsigned int usrst_req_cbc_tx); +int iSetIPSEC_TX_CRG_CFG_srst_req_gcm_tx(unsigned int usrst_req_gcm_tx); +int iSetCTX_MEM_INIT_ctx_mem_init(unsigned int uctx_mem_init); +int iSetCTX_MEM_INIT_DONE_ctx_mem_init_done(unsigned int uctx_mem_init_done); +int iSetCTX_MEM_CTRL_ctx_mem_power_mode(unsigned int uctx_mem_power_mode); +int iSetCTX_MEM_CTRL_ctx_tp_ram_tmod(unsigned int uctx_tp_ram_tmod); +int iSetCTX_MEM_CTRL_ctx_sp_ram_tmod(unsigned int uctx_sp_ram_tmod); +int iSetCTX_MEM_CTRL_ctx_ecc_bypass(unsigned int uctx_ecc_bypass); +int iSetCTX_REG_CNT_CLR_CE_cnt_clr_ce(unsigned int ucnt_clr_ce); +int iSetCTX_REG_CNT_CLR_CE_snap_en(unsigned int usnap_en); +int iSetCTX_LP_CHX_CFG_ctx_gcm_ch_cfg(unsigned int uctx_gcm_ch_cfg); +int iSetCTX_LP_CHX_CFG_ctx_cbc_ch_cfg(unsigned int uctx_cbc_ch_cfg); +int iSetCTX_LP_CHX_CFG_ctx_rsa_ch_cfg(unsigned int uctx_rsa_ch_cfg); +int iSetCTX_EC_CHX_CFG_ctx_xts_ec_ch_cfg(unsigned int uctx_xts_ec_ch_cfg); +int iSetCTX_EC_CHX_CFG_ctx_xts_ch_cfg(unsigned int uctx_xts_ch_cfg); +int iSetCTX_EC_CHX_CFG_ctx_ec_ch_cfg(unsigned int uctx_ec_ch_cfg); +int iSetCTX_EC_CHX_CFG_ctx_mhd_ch_cfg(unsigned int uctx_mhd_ch_cfg); +int iSetCTX_NECCH_CREDIT_O_CFG_ctx_necch_credit_o_cfg(unsigned int uctx_necch_credit_o_cfg); +int iSetCTX_ECCH_CREDIT_O_CFG_ctx_ecch_credit_o_cfg(unsigned int uctx_ecch_credit_o_cfg); +int iSetCTX_CTRL_RSV_ctx_ctrl_rsv(unsigned int uctx_ctrl_rsv); +int iSetCTX_STAT_RSV_ctx_stat_rsv(unsigned int uctx_stat_rsv); +int iSetCTX_LP_EPT_ctx_lp_ept(unsigned int uctx_lp_ept); +int iSetCTX_LP_FULL_ctx_lp_full(unsigned int uctx_lp_full); +int iSetCTX_EC_EPT_ctx_ec_ept(unsigned int uctx_ec_ept); +int iSetCTX_EC_FULL_ctx_ec_full(unsigned int uctx_ec_full); +int iSetCTX_DFT_MEM_CTRL_0_ctx_dft_mem_ctrl_0(unsigned int uctx_dft_mem_ctrl_0); +int iSetCTX_DFT_MEM_CTRL_1_ctx_dft_mem_ctrl_1(unsigned int uctx_dft_mem_ctrl_1); +int iSetCTX_DFT_MEM_CTRL_2_ctx_dft_mem_ctrl_2(unsigned int uctx_dft_mem_ctrl_2); +int iSetCTX_DFT_MEM_CTRL_3_ctx_dft_mem_ctrl_3(unsigned int uctx_dft_mem_ctrl_3); +int iSetCTX_DFT_MEM_CTRL_4_ctx_dft_mem_ctrl_4(unsigned int uctx_dft_mem_ctrl_4); +int iSetCTX_TOP_INT_EN_ctx_top_int_en(unsigned int uctx_top_int_en); +int iSetCTX_TOP_ALM_ctx_top_alm(unsigned int uctx_top_alm); +int iSetCTX_CREDIT_ERR_ctx_gcm_credit_i_err(unsigned int uctx_gcm_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_cbc_credit_i_err(unsigned int uctx_cbc_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_rsa_credit_i_err(unsigned int uctx_rsa_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_xts_ec_credit_i_err(unsigned int uctx_xts_ec_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_xts_credit_i_err(unsigned int uctx_xts_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_ec_credit_i_err(unsigned int uctx_ec_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_mhd_credit_i_err(unsigned int uctx_mhd_credit_i_err); +int iSetCTX_CREDIT_ERR_ctx_byp_credit_i_err(unsigned int uctx_byp_credit_i_err); +int iSetCTX_INN_CREDIT_I_ERR_ctx_gcm_inn_credit_i_err(unsigned int uctx_gcm_inn_credit_i_err); +int iSetCTX_INN_CREDIT_I_ERR_ctx_cbc_inn_credit_i_err(unsigned int uctx_cbc_inn_credit_i_err); +int iSetCTX_INN_CREDIT_I_ERR_ctx_rsa_inn_credit_i_err(unsigned int uctx_rsa_inn_credit_i_err); +int iSetCTX_INN_CREDIT_I_ERR_ctx_xts_ec_inn_credit_i_err(unsigned int uctx_xts_ec_inn_credit_i_err); +int iSetCTX_INN_CREDIT_I_ERR_ctx_xts_inn_credit_i_err(unsigned int uctx_xts_inn_credit_i_err); +int iSetCTX_LP_PKT_CNT_I_PRE_ctx_lp_pkt_cnt_i_pre(unsigned int uctx_lp_pkt_cnt_i_pre); +int iSetCTX_EC_PKT_CNT_I_PRE_ctx_ec_pkt_cnt_i_pre(unsigned int uctx_ec_pkt_cnt_i_pre); +int iSetCTX_BD_ERR_CNT_ctx_bd_err_cnt(unsigned int uctx_bd_err_cnt); +int iSetCTX_LEN_ERR_CNT_ctx_len_err_cnt(unsigned int uctx_len_err_cnt); +int iSetCTX_LP_PKT_CNT_I_ctx_lp_pkt_cnt_i(unsigned int uctx_lp_pkt_cnt_i); +int iSetCTX_EC_PKT_CNT_I_ctx_ec_pkt_cnt_i(unsigned int uctx_ec_pkt_cnt_i); +int iSetCTX_LP_PKT_CNT_O_ctx_lp_pkt_cnt_o(unsigned int uctx_lp_pkt_cnt_o); +int iSetCTX_EC_PKT_CNT_O_ctx_ec_pkt_cnt_o(unsigned int uctx_ec_pkt_cnt_o); +int iSetCRYPTOTX_IF_I_CNT_cryptotx_if_i_cnt(unsigned int ucryptotx_if_i_cnt); +int iSetCTX_BDSPLIT_LEN_I_ctx_bdsplit_len_i(unsigned int uctx_bdsplit_len_i); +int iSetCTX_BDSPLIT_LEN_O_ctx_bdsplit_len_o(unsigned int uctx_bdsplit_len_o); +int iSetCTX_PKT_CMB_LEN_O_ctx_pkt_cmb_len_o(unsigned int uctx_pkt_cmb_len_o); + +/* Define the union csr_hpre_core_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_core_enb0 : 1; /* [0] */ + u32 hpre_core_enb1 : 1; /* [1] */ + u32 hpre_core_enb2 : 1; /* [2] */ + u32 hpre_core_enb3 : 1; /* [3] */ + u32 rsv_0 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_enb_u; + +/* Define the union csr_hpre_cluster_dyn_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_cluster_dyn_enb : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cluster_dyn_enb_u; + +/* Define the union csr_hpre_core_ini_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_core_ini_cfg : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_ini_cfg_u; + +/* Define the union csr_hpre_core_ini_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_core_status0 : 1; /* [0] */ + u32 hpre_core_status1 : 1; /* [1] */ + u32 hpre_core_status2 : 1; /* [2] */ + u32 hpre_core_status3 : 1; /* [3] */ + u32 rsv_3 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_ini_status_u; + +/* Define the union csr_hpre_err_bit_inject_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_bit_inject_en : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_err_bit_inject_en_u; + +/* Define the union csr_hpre_core_shb_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 shb_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_shb_cfg_u; + +/* Define the union csr_hpre_core_shb_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 shb_warning : 4; /* [3:0] */ + u32 rsv_5 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_shb_st_u; + +/* Define the union csr_hpre_core_idle_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_arb_st : 4; /* [3:0] */ + u32 rsv_6 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_idle_st_u; + +/* Define the union csr_hpre_core_status_inquire_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_core_status_inquire_req : 1; /* [0] */ + u32 hpre_core_status_inquire_content : 11; /* [11:1] */ + u32 core_idx : 2; /* [13:12] */ + u32 rsv_7 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_status_inquire_u; + +/* Define the union csr_hpre_core_status_result_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_core_status_result : 18; /* [17:0] */ + u32 result_core_idx : 2; /* [19:18] */ + u32 latest_inquire_content : 11; /* [30:20] */ + u32 hpre_core_status_result_rdy : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_status_result_u; + +/* Define the union csr_hpre_core_err_bit_inject_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ej_core_idx : 2; /* [1:0] */ + u32 ej_cmd : 4; /* [5:2] */ + u32 ram_bit0_inject : 13; /* [18:6] */ + u32 ram_bit1_inject : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_core_err_bit_inject_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_hpre_core_enb_u hpre_core_enb; /* 4 */ + volatile csr_hpre_cluster_dyn_enb_u hpre_cluster_dyn_enb; /* 10 */ + volatile csr_hpre_core_ini_cfg_u hpre_core_ini_cfg; /* 20 */ + volatile csr_hpre_core_ini_status_u hpre_core_ini_status; /* 80 */ + volatile csr_hpre_err_bit_inject_en_u hpre_err_bit_inject_en; /* 84 */ + volatile csr_hpre_core_shb_cfg_u hpre_core_shb_cfg; /* 88 */ + volatile csr_hpre_core_shb_st_u hpre_core_shb_st; /* 8C */ + volatile csr_hpre_core_idle_st_u hpre_core_idle_st; /* 90 */ + volatile csr_hpre_core_status_inquire_u hpre_core_status_inquire; /* 100 */ + volatile csr_hpre_core_status_result_u hpre_core_status_result; /* 104 */ + volatile csr_hpre_core_err_bit_inject_u hpre_core_err_bit_inject; /* 108 */ +} S_hpre_cluster_REGS_TYPE; + +/* Declare the struct pointor of the module hpre_cluster */ +extern volatile S_hpre_cluster_REGS_TYPE *gophpre_clusterAllReg; + +/* Declare the functions that set the member value */ +int iSetHPRE_CORE_ENB_hpre_core_enb0(unsigned int uhpre_core_enb0); +int iSetHPRE_CORE_ENB_hpre_core_enb1(unsigned int uhpre_core_enb1); +int iSetHPRE_CORE_ENB_hpre_core_enb2(unsigned int uhpre_core_enb2); +int iSetHPRE_CORE_ENB_hpre_core_enb3(unsigned int uhpre_core_enb3); +int iSetHPRE_CLUSTER_DYN_ENB_hpre_cluster_dyn_enb(unsigned int uhpre_cluster_dyn_enb); +int iSetHPRE_CORE_INI_CFG_hpre_core_ini_cfg(unsigned int uhpre_core_ini_cfg); +int iSetHPRE_CORE_INI_STATUS_hpre_core_status0(unsigned int uhpre_core_status0); +int iSetHPRE_CORE_INI_STATUS_hpre_core_status1(unsigned int uhpre_core_status1); +int iSetHPRE_CORE_INI_STATUS_hpre_core_status2(unsigned int uhpre_core_status2); +int iSetHPRE_CORE_INI_STATUS_hpre_core_status3(unsigned int uhpre_core_status3); +int iSetHPRE_ERR_BIT_INJECT_EN_err_bit_inject_en(unsigned int uerr_bit_inject_en); +int iSetHPRE_CORE_SHB_CFG_shb_num(unsigned int ushb_num); +int iSetHPRE_CORE_SHB_ST_shb_warning(unsigned int ushb_warning); +int iSetHPRE_CORE_IDLE_ST_core_arb_st(unsigned int ucore_arb_st); +int iSetHPRE_CORE_STATUS_INQUIRE_hpre_core_status_inquire_req(unsigned int uhpre_core_status_inquire_req); +int iSetHPRE_CORE_STATUS_INQUIRE_hpre_core_status_inquire_content(unsigned int uhpre_core_status_inquire_content); +int iSetHPRE_CORE_STATUS_INQUIRE_core_idx(unsigned int ucore_idx); +int iSetHPRE_CORE_STATUS_RESULT_hpre_core_status_result(unsigned int uhpre_core_status_result); +int iSetHPRE_CORE_STATUS_RESULT_result_core_idx(unsigned int uresult_core_idx); +int iSetHPRE_CORE_STATUS_RESULT_latest_inquire_content(unsigned int ulatest_inquire_content); +int iSetHPRE_CORE_STATUS_RESULT_hpre_core_status_result_rdy(unsigned int uhpre_core_status_result_rdy); +int iSetHPRE_CORE_ERR_BIT_INJECT_ej_core_idx(unsigned int uej_core_idx); +int iSetHPRE_CORE_ERR_BIT_INJECT_ej_cmd(unsigned int uej_cmd); +int iSetHPRE_CORE_ERR_BIT_INJECT_ram_bit0_inject(unsigned int uram_bit0_inject); +int iSetHPRE_CORE_ERR_BIT_INJECT_ram_bit1_inject(unsigned int uram_bit1_inject); + +/* Define the union csr_hpre_common_cnt_clr_ce_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_clr_ce : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_common_cnt_clr_ce_u; + +/* Define the union csr_hpre_cfg_axqos_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 awqos : 4; /* [3:0] */ + u32 arqos : 4; /* [7:4] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cfg_axqos_u; + +/* Define the union csr_hpre_cfg_axcache_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 awcache : 4; /* [3:0] */ + u32 arcache : 4; /* [7:4] */ + u32 rsv_1 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cfg_axcache_u; + +/* Define the union csr_hpre_cfg_rdchn_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdchn_ini : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cfg_rdchn_ini_u; + +/* Define the union csr_hpre_cfg_awuser_fp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 aw_fp1_enb : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cfg_awuser_fp_cfg_u; + +/* Define the union csr_hpre_cfg_bd_endian_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_endian : 2; /* [1:0] */ + u32 rsv_4 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_cfg_bd_endian_u; + +/* Define the union csr_hpre_ecc_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_bypass : 1; /* [0] */ + u32 rsv_5 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_ecc_bypass_u; + +/* Define the union csr_hpre_ras_int_width_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ras_int_width : 10; /* [9:0] */ + u32 rsv_6 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_ras_int_width_cfg_u; + +/* Define the union csr_hpre_poison_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rd_poison_bypass : 1; /* [0] */ + u32 wr_poison_bypass : 1; /* [1] */ + u32 rsv_7 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_poison_bypass_u; + +/* Define the union csr_hpre_bd_aruser_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_aruser_snpattr : 1; /* [0] */ + u32 bd_aruser_cmd_type : 3; /* [3:1] */ + u32 bd_aruser_type : 2; /* [5:4] */ + u32 bd_aruser_cleaninvalid : 1; /* [6] */ + u32 bd_aruser_fna : 1; /* [7] */ + u32 bd_aruser_fa : 1; /* [8] */ + u32 bd_aruser_ssv : 1; /* [9] */ + u32 rsv_8 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_bd_aruser_cfg_u; + +/* Define the union csr_hpre_bd_awuser_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bd_awuser_snpattr : 1; /* [0] */ + u32 bd_awuser_cmd_type : 3; /* [3:1] */ + u32 bd_awuser_type : 2; /* [5:4] */ + u32 bd_awuser_fp1_enb : 1; /* [6] */ + u32 bd_awuser_fna : 1; /* [7] */ + u32 bd_awuser_fa : 1; /* [8] */ + u32 bd_awuser_ssv : 1; /* [9] */ + u32 rsv_9 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_bd_awuser_cfg_u; + +/* Define the union csr_hpre_types_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 task_type_enb : 1; /* [0] */ + u32 rsv_10 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_types_enb_u; + +/* Define the union csr_hpre_data_aruser_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_aruser_snpattr : 1; /* [0] */ + u32 data_aruser_cmd_type : 3; /* [3:1] */ + u32 data_aruser_type : 2; /* [5:4] */ + u32 data_aruser_cleaninvalid : 1; /* [6] */ + u32 data_aruser_fna : 1; /* [7] */ + u32 data_aruser_fa : 1; /* [8] */ + u32 data_aruser_ssv : 1; /* [9] */ + u32 rsv_11 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_data_aruser_cfg_u; + +/* Define the union csr_hpre_data_awuser_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_awuser_snpattr : 1; /* [0] */ + u32 data_awuser_cmd_type : 3; /* [3:1] */ + u32 data_awuser_type : 2; /* [5:4] */ + u32 data_awuser_fp1_enb : 1; /* [6] */ + u32 data_awuser_fna : 1; /* [7] */ + u32 data_awuser_fa : 1; /* [8] */ + u32 data_awuser_ssv : 1; /* [9] */ + u32 rsv_12 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_data_awuser_cfg_u; + +/* Define the union csr_hpre_am_ooo_shutdown_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 am_ooo_shutdown_enb : 1; /* [0] */ + u32 rsv_13 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_am_ooo_shutdown_enb_u; + +/* Define the union csr_hpre_hac_int_msk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_ecc_1bit_err_msk : 1; /* [0] */ + u32 core_ecc_2bit_err_msk : 1; /* [1] */ + u32 dat_wb_poison_msk : 1; /* [2] */ + u32 dat_rd_poison_msk : 1; /* [3] */ + u32 bd_rd_poison_msk : 1; /* [4] */ + u32 ooo_ecc_2bit_err_msk : 1; /* [5] */ + u32 cluster1_shb_timeout_msk : 1; /* [6] */ + u32 cluster2_shb_timeout_msk : 1; /* [7] */ + u32 cluster3_shb_timeout_msk : 1; /* [8] */ + u32 cluster4_shb_timeout_msk : 1; /* [9] */ + u32 ooo_rdrsp_err_msk : 6; /* [15:10] */ + u32 ooo_wrrsp_err_msk : 6; /* [21:16] */ + u32 qmv2_ecc_1bit_err_msk : 1; /* [22] */ + u32 qmv2_ecc_2bit_err_msk : 1; /* [23] */ + u32 datrd_ecc_1bit_err_msk : 1; /* [24] */ + u32 datrd_ecc_2bit_err_msk : 1; /* [25] */ + u32 rsv_14 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_int_msk_u; + +/* Define the union csr_hpre_ras_ecc1bit_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_ras_ecc1bit_th : 16; /* [15:0] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_ras_ecc1bit_th_u; + +/* Define the union csr_hpre_hac_ras_ce_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hac_ras_ce_enb : 26; /* [25:0] */ + u32 rsv_16 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_ce_enb_u; + +/* Define the union csr_hpre_hac_ras_nfe_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hac_ras_nfe_enb : 26; /* [25:0] */ + u32 rsv_17 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_nfe_enb_u; + +/* Define the union csr_hpre_hac_ras_fe_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hac_ras_fe_enb : 26; /* [25:0] */ + u32 rsv_18 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_fe_enb_u; + +/* Define the union csr_hpre_hac_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_ecc_1bit_err_int_set : 1; /* [0] */ + u32 core_ecc_2bit_err_int_set : 1; /* [1] */ + u32 dat_wb_poison_int_set : 1; /* [2] */ + u32 dat_rd_poison_int_set : 1; /* [3] */ + u32 bd_rd_poison_int_set : 1; /* [4] */ + u32 ooo_ecc_2bit_err_int_set : 1; /* [5] */ + u32 cluster1_shb_timeout_int_set : 1; /* [6] */ + u32 cluster2_shb_timeout_int_set : 1; /* [7] */ + u32 cluster3_shb_timeout_int_set : 1; /* [8] */ + u32 cluster4_shb_timeout_int_set : 1; /* [9] */ + u32 ooo_rdrsp_err_int_set : 6; /* [15:10] */ + u32 ooo_wrrsp_err_int_set : 6; /* [21:16] */ + u32 qmv2_ecc_1bit_err_int_set : 1; /* [22] */ + u32 qmv2_ecc_2bit_err_int_set : 1; /* [23] */ + u32 datrd_ecc_1bit_err_int_set : 1; /* [24] */ + u32 datrd_ecc_2bit_err_int_set : 1; /* [25] */ + u32 rsv_19 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_int_set_u; + +/* Define the union csr_hpre_hac_rint_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_ecc_1bit_err_rint : 1; /* [0] */ + u32 core_ecc_2bit_err_rint : 1; /* [1] */ + u32 dat_wb_poison_rint : 1; /* [2] */ + u32 dat_rd_poison_rint : 1; /* [3] */ + u32 bd_rd_poison_rint : 1; /* [4] */ + u32 ooo_ecc_2bit_err_rint : 1; /* [5] */ + u32 cluster1_shb_timeout_rint : 1; /* [6] */ + u32 cluster2_shb_timeout_rint : 1; /* [7] */ + u32 cluster3_shb_timeout_rint : 1; /* [8] */ + u32 cluster4_shb_timeout_rint : 1; /* [9] */ + u32 ooo_rdrsp_err_rint : 6; /* [15:10] */ + u32 ooo_wrrsp_err_rint : 6; /* [21:16] */ + u32 qmv2_ecc_1bit_err_rint : 1; /* [22] */ + u32 qmv2_ecc_2bit_err_rint : 1; /* [23] */ + u32 datrd_ecc_1bit_err_rint : 1; /* [24] */ + u32 datrd_ecc_2bit_err_rint : 1; /* [25] */ + u32 rsv_20 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_rint_u; + +/* Define the union csr_hpre_hac_int_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 core_ecc_1bit_err_int_st : 1; /* [0] */ + u32 core_ecc_2bit_err_int_st : 1; /* [1] */ + u32 dat_wb_poison_int_st : 1; /* [2] */ + u32 dat_rd_poison_int_st : 1; /* [3] */ + u32 bd_rd_poison_int_st : 1; /* [4] */ + u32 ooo_ecc_2bit_err_int_st : 1; /* [5] */ + u32 cluster1_shb_timeout_int_st : 1; /* [6] */ + u32 cluster2_shb_timeout_int_st : 1; /* [7] */ + u32 cluster3_shb_timeout_int_st : 1; /* [8] */ + u32 cluster4_shb_timeout_int_st : 1; /* [9] */ + u32 ooo_rdrsp_err_int_st : 6; /* [15:10] */ + u32 ooo_wrrsp_err_int_st : 6; /* [21:16] */ + u32 qmv2_ecc_1bit_err_int_st : 1; /* [22] */ + u32 qmv2_ecc_2bit_err_int_st : 1; /* [23] */ + u32 datrd_ecc_1bit_err_int_st : 1; /* [24] */ + u32 datrd_ecc_2bit_err_int_st : 1; /* [25] */ + u32 rsv_21 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_int_st_u; + +/* Define the union csr_hpre_fifo_afull_his1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_rd_chn_fifo_afull_his : 4; /* [3:0] */ + u32 rsv_22 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_afull_his1_u; + +/* Define the union csr_hpre_fifo_afull_his2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_wb_chn_fifo_afull_his : 16; /* [15:0] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_afull_his2_u; + +/* Define the union csr_hpre_fifo_afull_his3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdtn_fifo_afull_his : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_afull_his3_u; + +/* Define the union csr_hpre_fifo_full_his1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 data_rd_chn_fifo_full_his : 4; /* [3:0] */ + u32 rsv_24 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_full_his1_u; + +/* Define the union csr_hpre_fifo_full_his2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_wb_chn_fifo_full_his : 16; /* [15:0] */ + u32 rsv_25 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_full_his2_u; + +/* Define the union csr_hpre_fifo_full_his3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdtn_fifo_full_his : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_full_his3_u; + +/* Define the union csr_hpre_fifo_empty_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_rd_chn_fifo_empty : 4; /* [3:0] */ + u32 rsv_26 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_empty_st1_u; + +/* Define the union csr_hpre_fifo_empty_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dat_wb_chn_fifo_empty : 16; /* [15:0] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_empty_st2_u; + +/* Define the union csr_hpre_fifo_empty_st3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdtn_fifo_empty : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fifo_empty_st3_u; + +/* Define the union csr_hpre_mem_ebit_inj_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iobuf_err_bit_inject_en : 1; /* [0] */ + u32 qmv2_err_bit_inject_en : 1; /* [1] */ + u32 rsv_28 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ebit_inj_en_u; + +/* Define the union csr_hpre_mem_ebit_inj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iobuf_ram0_err_bit_inj : 2; /* [1:0] */ + u32 iobuf_ram1_err_bit_inj : 2; /* [3:2] */ + u32 iobuf_ram2_err_bit_inj : 2; /* [5:4] */ + u32 iobuf_ram3_err_bit_inj : 2; /* [7:6] */ + u32 qmv2_storem_errbit_inj : 2; /* [9:8] */ + u32 qmv2_store_comp_m_errbit_inj : 2; /* [11:10] */ + u32 rsv_29 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ebit_inj_u; + +/* Define the union csr_hpre_qmv2_mem_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qmv2_storem_err_addr : 8; /* [7:0] */ + u32 qmv2_store_comp_m_err_addr : 8; /* [15:8] */ + u32 rsv_30 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_qmv2_mem_err_addr_u; + +/* Define the union csr_hpre_clkgate_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clk_gate_enable : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_clkgate_enb_u; + +/* Define the union csr_hpre_crypt_do_crt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_do_credit : 4; /* [3:0] */ + u32 rsv_32 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_crypt_do_crt_u; + +/* Define the union csr_hpre_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_cpi_int_index : 24; /* [23:0] */ + u32 rsv_33 : 3; /* [26:24] */ + u32 hpre_enable : 1; /* [27] */ + u32 hpre_int_issue : 1; /* [28] */ + u32 rsv_34 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_int_vector_u; + +/* Define the union csr_hpre_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_int_data : 6; /* [5:0] */ + u32 rsv_35 : 10; /* [15:6] */ + u32 hpre_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_int_u; + +/* Define the union csr_hpre_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_int_en : 6; /* [5:0] */ + u32 rsv_36 : 10; /* [15:6] */ + u32 hpre_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_int_en_u; + +/* Define the union csr_hpre_hac_ras_ce_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_hac_ras_ce_err : 1; /* [0] */ + u32 hpre_hac_ras_ce_err_inj : 1; /* [1] */ + u32 hpre_hac_ras_ce_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_ce_err_u; + +/* Define the union csr_hpre_hac_ras_fe_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_hac_ras_fe_err : 1; /* [0] */ + u32 hpre_hac_ras_fe_err_inj : 1; /* [1] */ + u32 hpre_hac_ras_fe_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_fe_err_u; + +/* Define the union csr_hpre_hac_ras_nfe_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_hac_ras_nfe_err : 1; /* [0] */ + u32 hpre_hac_ras_nfe_err_inj : 1; /* [1] */ + u32 hpre_hac_ras_nfe_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_hac_ras_nfe_err_u; + +/* Define the union csr_int_sram_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_sram_err : 1; /* [0] */ + u32 int_sram_err_inj : 1; /* [1] */ + u32 int_sram_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_int_sram_err_u; + +/* Define the union csr_hpre_di_fsm_timeout_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_di_fsm_timeout_err : 1; /* [0] */ + u32 hpre_di_fsm_timeout_err_inj : 1; /* [1] */ + u32 hpre_di_fsm_timeout_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_di_fsm_timeout_err_u; + +/* Define the union csr_hpre_do_fsm_timeout_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_do_fsm_timeout_err : 1; /* [0] */ + u32 hpre_do_fsm_timeout_err_inj : 1; /* [1] */ + u32 hpre_do_fsm_timeout_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_do_fsm_timeout_err_u; + +/* Define the union csr_hpre_dido_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 di_sop_overlapped_err : 1; /* [0] */ + u32 di_eop_len_nomatch_err : 1; /* [1] */ + u32 di_alg_err : 1; /* [2] */ + u32 di_len_err : 1; /* [3] */ + u32 di_strb_err : 1; /* [4] */ + u32 di_fifo_err : 1; /* [5] */ + u32 di_axi_wr_err : 1; /* [6] */ + u32 di_credit_err : 1; /* [7] */ + u32 do_credit_err : 1; /* [8] */ + u32 do_fifo_err : 1; /* [9] */ + u32 do_axi_rd_err : 1; /* [10] */ + u32 rsv_37 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_dido_err_info_u; + +/* Define the union csr_hpre_fsm_shb_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fsm_shb_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_fsm_shb_cfg_u; + +/* Define the union csr_hpre_mem_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_mem_ctrl_0_bus : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ctrl_0_u; + +/* Define the union csr_hpre_mem_ctrl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_mem_ctrl_1_bus : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ctrl_1_u; + +/* Define the union csr_hpre_mem_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_mem_ctrl_2_bus : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ctrl_2_u; + +/* Define the union csr_hpre_mem_ctrl_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_mem_ctrl_3_bus : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ctrl_3_u; + +/* Define the union csr_hpre_mem_ctrl_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_mem_ctrl_4_bus : 6; /* [5:0] */ + u32 rsv_38 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_mem_ctrl_4_u; + +/* Define the union csr_hpre_rdchn_ini_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rdchn_ini_st : 1; /* [0] */ + u32 rsv_39 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_rdchn_ini_st_u; + +/* Define the union csr_hpre_ecc1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_ecc1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_ecc1bit_err_cnt_u; + +/* Define the union csr_hpre_ecc2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_ecc2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_ecc2bit_err_cnt_u; + +/* Define the union csr_hpre_peh_eco1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_peh_eco1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_peh_eco1_u; + +/* Define the union csr_hpre_peh_eco2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_peh_eco2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_peh_eco2_u; + +/* Define the union csr_hpre_peh_eco3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_peh_eco3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_peh_eco3_u; + +/* Define the union csr_hpre_peh_eco4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_peh_eco4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_peh_eco4_u; + +/* Define the union csr_hpre_peh_eco5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_peh_eco5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_peh_eco5_u; + +/* Define the union csr_hpre_eco1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_eco1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_eco1_u; + +/* Define the union csr_hpre_eco2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_eco2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_eco2_u; + +/* Define the union csr_hpre_eco3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_eco3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_eco3_u; + +/* Define the union csr_hpre_eco4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hpre_eco4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hpre_eco4_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_hpre_cfg_axqos_u hpre_cfg_axqos; /* C */ + volatile csr_hpre_cfg_axcache_u hpre_cfg_axcache; /* 10 */ + volatile csr_hpre_cfg_rdchn_ini_u hpre_cfg_rdchn_ini; /* 14 */ + volatile csr_hpre_cfg_awuser_fp_cfg_u hpre_cfg_awuser_fp_cfg; /* 18 */ + volatile csr_hpre_cfg_bd_endian_u hpre_cfg_bd_endian; /* 20 */ + volatile csr_hpre_ecc_bypass_u hpre_ecc_bypass; /* 24 */ + volatile csr_hpre_ras_int_width_cfg_u hpre_ras_int_width_cfg; /* 28 */ + volatile csr_hpre_poison_bypass_u hpre_poison_bypass; /* 2C */ + volatile csr_hpre_bd_aruser_cfg_u hpre_bd_aruser_cfg; /* 30 */ + volatile csr_hpre_bd_awuser_cfg_u hpre_bd_awuser_cfg; /* 34 */ + volatile csr_hpre_types_enb_u hpre_types_enb; /* 38 */ + volatile csr_hpre_data_aruser_cfg_u hpre_data_aruser_cfg; /* 3C */ + volatile csr_hpre_data_awuser_cfg_u hpre_data_awuser_cfg; /* 40 */ + volatile csr_hpre_am_ooo_shutdown_enb_u hpre_am_ooo_shutdown_enb; /* 44 */ + volatile csr_hpre_hac_int_msk_u hpre_hac_int_msk; /* 400 */ + volatile csr_hpre_ras_ecc1bit_th_u hpre_ras_ecc1bit_th; /* 40C */ + volatile csr_hpre_hac_ras_ce_enb_u hpre_hac_ras_ce_enb; /* 410 */ + volatile csr_hpre_hac_ras_nfe_enb_u hpre_hac_ras_nfe_enb; /* 414 */ + volatile csr_hpre_hac_ras_fe_enb_u hpre_hac_ras_fe_enb; /* 418 */ + volatile csr_hpre_hac_int_set_u hpre_hac_int_set; /* 500 */ + volatile csr_hpre_hac_rint_u hpre_hac_rint; /* 600 */ + volatile csr_hpre_hac_int_st_u hpre_hac_int_st; /* 800 */ + volatile csr_hpre_fifo_afull_his1_u hpre_fifo_afull_his1; /* 810 */ + volatile csr_hpre_fifo_afull_his2_u hpre_fifo_afull_his2; /* 814 */ + volatile csr_hpre_fifo_afull_his3_u hpre_fifo_afull_his3; /* 818 */ + volatile csr_hpre_fifo_full_his1_u hpre_fifo_full_his1; /* 840 */ + volatile csr_hpre_fifo_full_his2_u hpre_fifo_full_his2; /* 844 */ + volatile csr_hpre_fifo_full_his3_u hpre_fifo_full_his3; /* 848 */ + volatile csr_hpre_fifo_empty_st1_u hpre_fifo_empty_st1; /* 880 */ + volatile csr_hpre_fifo_empty_st2_u hpre_fifo_empty_st2; /* 884 */ + volatile csr_hpre_fifo_empty_st3_u hpre_fifo_empty_st3; /* 888 */ + volatile csr_hpre_mem_ebit_inj_en_u hpre_mem_ebit_inj_en; /* 900 */ + volatile csr_hpre_mem_ebit_inj_u hpre_mem_ebit_inj; /* 904 */ + volatile csr_hpre_qmv2_mem_err_addr_u hpre_qmv2_mem_err_addr; /* 908 */ + volatile csr_hpre_clkgate_enb_u hpre_clkgate_enb; /* 90C */ + volatile csr_hpre_crypt_do_crt_u hpre_crypt_do_crt; /* 910 */ + volatile csr_hpre_int_vector_u hpre_int_vector; /* 914 */ + volatile csr_hpre_int_u hpre_int; /* 918 */ + volatile csr_hpre_int_en_u hpre_int_en; /* 91C */ + volatile csr_hpre_hac_ras_ce_err_u hpre_hac_ras_ce_err; /* 920 */ + volatile csr_hpre_hac_ras_fe_err_u hpre_hac_ras_fe_err; /* 924 */ + volatile csr_hpre_hac_ras_nfe_err_u hpre_hac_ras_nfe_err; /* 928 */ + volatile csr_int_sram_err_u int_sram_err; /* 92C */ + volatile csr_hpre_di_fsm_timeout_err_u hpre_di_fsm_timeout_err; /* 930 */ + volatile csr_hpre_do_fsm_timeout_err_u hpre_do_fsm_timeout_err; /* 934 */ + volatile csr_hpre_dido_err_info_u hpre_dido_err_info; /* 938 */ + volatile csr_hpre_fsm_shb_cfg_u hpre_fsm_shb_cfg; /* 93C */ + volatile csr_hpre_mem_ctrl_0_u hpre_mem_ctrl_0; /* 940 */ + volatile csr_hpre_mem_ctrl_1_u hpre_mem_ctrl_1; /* 944 */ + volatile csr_hpre_mem_ctrl_2_u hpre_mem_ctrl_2; /* 948 */ + volatile csr_hpre_mem_ctrl_3_u hpre_mem_ctrl_3; /* 94C */ + volatile csr_hpre_mem_ctrl_4_u hpre_mem_ctrl_4; /* 950 */ + volatile csr_hpre_rdchn_ini_st_u hpre_rdchn_ini_st; /* A00 */ + volatile csr_hpre_ecc1bit_err_cnt_u hpre_ecc1bit_err_cnt; /* A04 */ + volatile csr_hpre_ecc2bit_err_cnt_u hpre_ecc2bit_err_cnt; /* A08 */ + volatile csr_hpre_peh_eco1_u hpre_peh_eco1; /* A10 */ + volatile csr_hpre_peh_eco2_u hpre_peh_eco2; /* A14 */ + volatile csr_hpre_peh_eco3_u hpre_peh_eco3; /* A18 */ + volatile csr_hpre_peh_eco4_u hpre_peh_eco4; /* A1C */ + volatile csr_hpre_peh_eco5_u hpre_peh_eco5; /* A20 */ + volatile csr_hpre_eco1_u hpre_eco1; /* A24 */ + volatile csr_hpre_eco2_u hpre_eco2; /* A28 */ + volatile csr_hpre_eco3_u hpre_eco3; /* A2C */ + volatile csr_hpre_eco4_u hpre_eco4; /* A30 */ +} S_hpre_common_REGS_TYPE; + +/* Declare the struct pointor of the module hpre_common */ +extern volatile S_hpre_common_REGS_TYPE *gophpre_commonAllReg; + +/* Declare the functions that set the member value */ +int iSetHPRE_CFG_AXQOS_awqos(unsigned int uawqos); +int iSetHPRE_CFG_AXQOS_arqos(unsigned int uarqos); +int iSetHPRE_CFG_AXCACHE_awcache(unsigned int uawcache); +int iSetHPRE_CFG_AXCACHE_arcache(unsigned int uarcache); +int iSetHPRE_CFG_RDCHN_INI_rdchn_ini(unsigned int urdchn_ini); +int iSetHPRE_CFG_AWUSER_FP_CFG_aw_fp1_enb(unsigned int uaw_fp1_enb); +int iSetHPRE_CFG_BD_ENDIAN_bd_endian(unsigned int ubd_endian); +int iSetHPRE_ECC_BYPASS_ecc_bypass(unsigned int uecc_bypass); +int iSetHPRE_RAS_INT_WIDTH_CFG_ras_int_width(unsigned int uras_int_width); +int iSetHPRE_POISON_BYPASS_rd_poison_bypass(unsigned int urd_poison_bypass); +int iSetHPRE_POISON_BYPASS_wr_poison_bypass(unsigned int uwr_poison_bypass); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_snpattr(unsigned int ubd_aruser_snpattr); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_cmd_type(unsigned int ubd_aruser_cmd_type); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_type(unsigned int ubd_aruser_type); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_cleaninvalid(unsigned int ubd_aruser_cleaninvalid); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_fna(unsigned int ubd_aruser_fna); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_fa(unsigned int ubd_aruser_fa); +int iSetHPRE_BD_ARUSER_CFG_bd_aruser_ssv(unsigned int ubd_aruser_ssv); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_snpattr(unsigned int ubd_awuser_snpattr); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_cmd_type(unsigned int ubd_awuser_cmd_type); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_type(unsigned int ubd_awuser_type); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_fp1_enb(unsigned int ubd_awuser_fp1_enb); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_fna(unsigned int ubd_awuser_fna); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_fa(unsigned int ubd_awuser_fa); +int iSetHPRE_BD_AWUSER_CFG_bd_awuser_ssv(unsigned int ubd_awuser_ssv); +int iSetHPRE_TYPES_ENB_task_type_enb(unsigned int utask_type_enb); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_snpattr(unsigned int udata_aruser_snpattr); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_cmd_type(unsigned int udata_aruser_cmd_type); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_type(unsigned int udata_aruser_type); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_cleaninvalid(unsigned int udata_aruser_cleaninvalid); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_fna(unsigned int udata_aruser_fna); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_fa(unsigned int udata_aruser_fa); +int iSetHPRE_DATA_ARUSER_CFG_data_aruser_ssv(unsigned int udata_aruser_ssv); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_snpattr(unsigned int udata_awuser_snpattr); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_cmd_type(unsigned int udata_awuser_cmd_type); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_type(unsigned int udata_awuser_type); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_fp1_enb(unsigned int udata_awuser_fp1_enb); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_fna(unsigned int udata_awuser_fna); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_fa(unsigned int udata_awuser_fa); +int iSetHPRE_DATA_AWUSER_CFG_data_awuser_ssv(unsigned int udata_awuser_ssv); +int iSetHPRE_AM_OOO_SHUTDOWN_ENB_am_ooo_shutdown_enb(unsigned int uam_ooo_shutdown_enb); +int iSetHPRE_HAC_INT_MSK_core_ecc_1bit_err_msk(unsigned int ucore_ecc_1bit_err_msk); +int iSetHPRE_HAC_INT_MSK_core_ecc_2bit_err_msk(unsigned int ucore_ecc_2bit_err_msk); +int iSetHPRE_HAC_INT_MSK_dat_wb_poison_msk(unsigned int udat_wb_poison_msk); +int iSetHPRE_HAC_INT_MSK_dat_rd_poison_msk(unsigned int udat_rd_poison_msk); +int iSetHPRE_HAC_INT_MSK_bd_rd_poison_msk(unsigned int ubd_rd_poison_msk); +int iSetHPRE_HAC_INT_MSK_ooo_ecc_2bit_err_msk(unsigned int uooo_ecc_2bit_err_msk); +int iSetHPRE_HAC_INT_MSK_cluster1_shb_timeout_msk(unsigned int ucluster1_shb_timeout_msk); +int iSetHPRE_HAC_INT_MSK_cluster2_shb_timeout_msk(unsigned int ucluster2_shb_timeout_msk); +int iSetHPRE_HAC_INT_MSK_cluster3_shb_timeout_msk(unsigned int ucluster3_shb_timeout_msk); +int iSetHPRE_HAC_INT_MSK_cluster4_shb_timeout_msk(unsigned int ucluster4_shb_timeout_msk); +int iSetHPRE_HAC_INT_MSK_ooo_rdrsp_err_msk(unsigned int uooo_rdrsp_err_msk); +int iSetHPRE_HAC_INT_MSK_ooo_wrrsp_err_msk(unsigned int uooo_wrrsp_err_msk); +int iSetHPRE_HAC_INT_MSK_qmv2_ecc_1bit_err_msk(unsigned int uqmv2_ecc_1bit_err_msk); +int iSetHPRE_HAC_INT_MSK_qmv2_ecc_2bit_err_msk(unsigned int uqmv2_ecc_2bit_err_msk); +int iSetHPRE_HAC_INT_MSK_datrd_ecc_1bit_err_msk(unsigned int udatrd_ecc_1bit_err_msk); +int iSetHPRE_HAC_INT_MSK_datrd_ecc_2bit_err_msk(unsigned int udatrd_ecc_2bit_err_msk); +int iSetHPRE_RAS_ECC1BIT_TH_hpre_ras_ecc1bit_th(unsigned int uhpre_ras_ecc1bit_th); +int iSetHPRE_HAC_RAS_CE_ENB_hac_ras_ce_enb(unsigned int uhac_ras_ce_enb); +int iSetHPRE_HAC_RAS_NFE_ENB_hac_ras_nfe_enb(unsigned int uhac_ras_nfe_enb); +int iSetHPRE_HAC_RAS_FE_ENB_hac_ras_fe_enb(unsigned int uhac_ras_fe_enb); +int iSetHPRE_HAC_INT_SET_core_ecc_1bit_err_int_set(unsigned int ucore_ecc_1bit_err_int_set); +int iSetHPRE_HAC_INT_SET_core_ecc_2bit_err_int_set(unsigned int ucore_ecc_2bit_err_int_set); +int iSetHPRE_HAC_INT_SET_dat_wb_poison_int_set(unsigned int udat_wb_poison_int_set); +int iSetHPRE_HAC_INT_SET_dat_rd_poison_int_set(unsigned int udat_rd_poison_int_set); +int iSetHPRE_HAC_INT_SET_bd_rd_poison_int_set(unsigned int ubd_rd_poison_int_set); +int iSetHPRE_HAC_INT_SET_ooo_ecc_2bit_err_int_set(unsigned int uooo_ecc_2bit_err_int_set); +int iSetHPRE_HAC_INT_SET_cluster1_shb_timeout_int_set(unsigned int ucluster1_shb_timeout_int_set); +int iSetHPRE_HAC_INT_SET_cluster2_shb_timeout_int_set(unsigned int ucluster2_shb_timeout_int_set); +int iSetHPRE_HAC_INT_SET_cluster3_shb_timeout_int_set(unsigned int ucluster3_shb_timeout_int_set); +int iSetHPRE_HAC_INT_SET_cluster4_shb_timeout_int_set(unsigned int ucluster4_shb_timeout_int_set); +int iSetHPRE_HAC_INT_SET_ooo_rdrsp_err_int_set(unsigned int uooo_rdrsp_err_int_set); +int iSetHPRE_HAC_INT_SET_ooo_wrrsp_err_int_set(unsigned int uooo_wrrsp_err_int_set); +int iSetHPRE_HAC_INT_SET_qmv2_ecc_1bit_err_int_set(unsigned int uqmv2_ecc_1bit_err_int_set); +int iSetHPRE_HAC_INT_SET_qmv2_ecc_2bit_err_int_set(unsigned int uqmv2_ecc_2bit_err_int_set); +int iSetHPRE_HAC_INT_SET_datrd_ecc_1bit_err_int_set(unsigned int udatrd_ecc_1bit_err_int_set); +int iSetHPRE_HAC_INT_SET_datrd_ecc_2bit_err_int_set(unsigned int udatrd_ecc_2bit_err_int_set); +int iSetHPRE_HAC_RINT_core_ecc_1bit_err_rint(unsigned int ucore_ecc_1bit_err_rint); +int iSetHPRE_HAC_RINT_core_ecc_2bit_err_rint(unsigned int ucore_ecc_2bit_err_rint); +int iSetHPRE_HAC_RINT_dat_wb_poison_rint(unsigned int udat_wb_poison_rint); +int iSetHPRE_HAC_RINT_dat_rd_poison_rint(unsigned int udat_rd_poison_rint); +int iSetHPRE_HAC_RINT_bd_rd_poison_rint(unsigned int ubd_rd_poison_rint); +int iSetHPRE_HAC_RINT_ooo_ecc_2bit_err_rint(unsigned int uooo_ecc_2bit_err_rint); +int iSetHPRE_HAC_RINT_cluster1_shb_timeout_rint(unsigned int ucluster1_shb_timeout_rint); +int iSetHPRE_HAC_RINT_cluster2_shb_timeout_rint(unsigned int ucluster2_shb_timeout_rint); +int iSetHPRE_HAC_RINT_cluster3_shb_timeout_rint(unsigned int ucluster3_shb_timeout_rint); +int iSetHPRE_HAC_RINT_cluster4_shb_timeout_rint(unsigned int ucluster4_shb_timeout_rint); +int iSetHPRE_HAC_RINT_ooo_rdrsp_err_rint(unsigned int uooo_rdrsp_err_rint); +int iSetHPRE_HAC_RINT_ooo_wrrsp_err_rint(unsigned int uooo_wrrsp_err_rint); +int iSetHPRE_HAC_RINT_qmv2_ecc_1bit_err_rint(unsigned int uqmv2_ecc_1bit_err_rint); +int iSetHPRE_HAC_RINT_qmv2_ecc_2bit_err_rint(unsigned int uqmv2_ecc_2bit_err_rint); +int iSetHPRE_HAC_RINT_datrd_ecc_1bit_err_rint(unsigned int udatrd_ecc_1bit_err_rint); +int iSetHPRE_HAC_RINT_datrd_ecc_2bit_err_rint(unsigned int udatrd_ecc_2bit_err_rint); +int iSetHPRE_HAC_INT_ST_core_ecc_1bit_err_int_st(unsigned int ucore_ecc_1bit_err_int_st); +int iSetHPRE_HAC_INT_ST_core_ecc_2bit_err_int_st(unsigned int ucore_ecc_2bit_err_int_st); +int iSetHPRE_HAC_INT_ST_dat_wb_poison_int_st(unsigned int udat_wb_poison_int_st); +int iSetHPRE_HAC_INT_ST_dat_rd_poison_int_st(unsigned int udat_rd_poison_int_st); +int iSetHPRE_HAC_INT_ST_bd_rd_poison_int_st(unsigned int ubd_rd_poison_int_st); +int iSetHPRE_HAC_INT_ST_ooo_ecc_2bit_err_int_st(unsigned int uooo_ecc_2bit_err_int_st); +int iSetHPRE_HAC_INT_ST_cluster1_shb_timeout_int_st(unsigned int ucluster1_shb_timeout_int_st); +int iSetHPRE_HAC_INT_ST_cluster2_shb_timeout_int_st(unsigned int ucluster2_shb_timeout_int_st); +int iSetHPRE_HAC_INT_ST_cluster3_shb_timeout_int_st(unsigned int ucluster3_shb_timeout_int_st); +int iSetHPRE_HAC_INT_ST_cluster4_shb_timeout_int_st(unsigned int ucluster4_shb_timeout_int_st); +int iSetHPRE_HAC_INT_ST_ooo_rdrsp_err_int_st(unsigned int uooo_rdrsp_err_int_st); +int iSetHPRE_HAC_INT_ST_ooo_wrrsp_err_int_st(unsigned int uooo_wrrsp_err_int_st); +int iSetHPRE_HAC_INT_ST_qmv2_ecc_1bit_err_int_st(unsigned int uqmv2_ecc_1bit_err_int_st); +int iSetHPRE_HAC_INT_ST_qmv2_ecc_2bit_err_int_st(unsigned int uqmv2_ecc_2bit_err_int_st); +int iSetHPRE_HAC_INT_ST_datrd_ecc_1bit_err_int_st(unsigned int udatrd_ecc_1bit_err_int_st); +int iSetHPRE_HAC_INT_ST_datrd_ecc_2bit_err_int_st(unsigned int udatrd_ecc_2bit_err_int_st); +int iSetHPRE_FIFO_AFULL_HIS1_dat_rd_chn_fifo_afull_his(unsigned int udat_rd_chn_fifo_afull_his); +int iSetHPRE_FIFO_AFULL_HIS2_dat_wb_chn_fifo_afull_his(unsigned int udat_wb_chn_fifo_afull_his); +int iSetHPRE_FIFO_AFULL_HIS3_rdtn_fifo_afull_his(unsigned int urdtn_fifo_afull_his); +int iSetHPRE_FIFO_FULL_HIS1_data_rd_chn_fifo_full_his(unsigned int udata_rd_chn_fifo_full_his); +int iSetHPRE_FIFO_FULL_HIS2_dat_wb_chn_fifo_full_his(unsigned int udat_wb_chn_fifo_full_his); +int iSetHPRE_FIFO_FULL_HIS3_rdtn_fifo_full_his(unsigned int urdtn_fifo_full_his); +int iSetHPRE_FIFO_EMPTY_ST1_dat_rd_chn_fifo_empty(unsigned int udat_rd_chn_fifo_empty); +int iSetHPRE_FIFO_EMPTY_ST2_dat_wb_chn_fifo_empty(unsigned int udat_wb_chn_fifo_empty); +int iSetHPRE_FIFO_EMPTY_ST3_rdtn_fifo_empty(unsigned int urdtn_fifo_empty); +int iSetHPRE_MEM_EBIT_INJ_EN_iobuf_err_bit_inject_en(unsigned int uiobuf_err_bit_inject_en); +int iSetHPRE_MEM_EBIT_INJ_EN_qmv2_err_bit_inject_en(unsigned int uqmv2_err_bit_inject_en); +int iSetHPRE_MEM_EBIT_INJ_iobuf_ram0_err_bit_inj(unsigned int uiobuf_ram0_err_bit_inj); +int iSetHPRE_MEM_EBIT_INJ_iobuf_ram1_err_bit_inj(unsigned int uiobuf_ram1_err_bit_inj); +int iSetHPRE_MEM_EBIT_INJ_iobuf_ram2_err_bit_inj(unsigned int uiobuf_ram2_err_bit_inj); +int iSetHPRE_MEM_EBIT_INJ_iobuf_ram3_err_bit_inj(unsigned int uiobuf_ram3_err_bit_inj); +int iSetHPRE_MEM_EBIT_INJ_qmv2_storem_errbit_inj(unsigned int uqmv2_storem_errbit_inj); +int iSetHPRE_MEM_EBIT_INJ_qmv2_store_comp_m_errbit_inj(unsigned int uqmv2_store_comp_m_errbit_inj); +int iSetHPRE_QMV2_MEM_ERR_ADDR_qmv2_storem_err_addr(unsigned int uqmv2_storem_err_addr); +int iSetHPRE_QMV2_MEM_ERR_ADDR_qmv2_store_comp_m_err_addr(unsigned int uqmv2_store_comp_m_err_addr); +int iSetHPRE_CLKGATE_ENB_clk_gate_enable(unsigned int uclk_gate_enable); +int iSetHPRE_CRYPT_DO_CRT_hpre_do_credit(unsigned int uhpre_do_credit); +int iSetHPRE_INT_VECTOR_hpre_cpi_int_index(unsigned int uhpre_cpi_int_index); +int iSetHPRE_INT_VECTOR_hpre_enable(unsigned int uhpre_enable); +int iSetHPRE_INT_VECTOR_hpre_int_issue(unsigned int uhpre_int_issue); +int iSetHPRE_INT_hpre_int_data(unsigned int uhpre_int_data); +int iSetHPRE_INT_hpre_program_csr_id_ro(unsigned int uhpre_program_csr_id_ro); +int iSetHPRE_INT_EN_hpre_int_en(unsigned int uhpre_int_en); +int iSetHPRE_INT_EN_hpre_program_csr_id(unsigned int uhpre_program_csr_id); +int iSetHPRE_HAC_RAS_CE_ERR_hpre_hac_ras_ce_err(unsigned int uhpre_hac_ras_ce_err); +int iSetHPRE_HAC_RAS_CE_ERR_hpre_hac_ras_ce_err_inj(unsigned int uhpre_hac_ras_ce_err_inj); +int iSetHPRE_HAC_RAS_CE_ERR_hpre_hac_ras_ce_err_sticky(unsigned int uhpre_hac_ras_ce_err_sticky); +int iSetHPRE_HAC_RAS_FE_ERR_hpre_hac_ras_fe_err(unsigned int uhpre_hac_ras_fe_err); +int iSetHPRE_HAC_RAS_FE_ERR_hpre_hac_ras_fe_err_inj(unsigned int uhpre_hac_ras_fe_err_inj); +int iSetHPRE_HAC_RAS_FE_ERR_hpre_hac_ras_fe_err_sticky(unsigned int uhpre_hac_ras_fe_err_sticky); +int iSetHPRE_HAC_RAS_NFE_ERR_hpre_hac_ras_nfe_err(unsigned int uhpre_hac_ras_nfe_err); +int iSetHPRE_HAC_RAS_NFE_ERR_hpre_hac_ras_nfe_err_inj(unsigned int uhpre_hac_ras_nfe_err_inj); +int iSetHPRE_HAC_RAS_NFE_ERR_hpre_hac_ras_nfe_err_sticky(unsigned int uhpre_hac_ras_nfe_err_sticky); +int iSetINT_SRAM_ERR_int_sram_err(unsigned int uint_sram_err); +int iSetINT_SRAM_ERR_int_sram_err_inj(unsigned int uint_sram_err_inj); +int iSetINT_SRAM_ERR_int_sram_err_sticky(unsigned int uint_sram_err_sticky); +int iSetHPRE_DI_FSM_TIMEOUT_ERR_hpre_di_fsm_timeout_err(unsigned int uhpre_di_fsm_timeout_err); +int iSetHPRE_DI_FSM_TIMEOUT_ERR_hpre_di_fsm_timeout_err_inj(unsigned int uhpre_di_fsm_timeout_err_inj); +int iSetHPRE_DI_FSM_TIMEOUT_ERR_hpre_di_fsm_timeout_err_sticky(unsigned int uhpre_di_fsm_timeout_err_sticky); +int iSetHPRE_DO_FSM_TIMEOUT_ERR_hpre_do_fsm_timeout_err(unsigned int uhpre_do_fsm_timeout_err); +int iSetHPRE_DO_FSM_TIMEOUT_ERR_hpre_do_fsm_timeout_err_inj(unsigned int uhpre_do_fsm_timeout_err_inj); +int iSetHPRE_DO_FSM_TIMEOUT_ERR_hpre_do_fsm_timeout_err_sticky(unsigned int uhpre_do_fsm_timeout_err_sticky); +int iSetHPRE_DIDO_ERR_INFO_di_sop_overlapped_err(unsigned int udi_sop_overlapped_err); +int iSetHPRE_DIDO_ERR_INFO_di_eop_len_nomatch_err(unsigned int udi_eop_len_nomatch_err); +int iSetHPRE_DIDO_ERR_INFO_di_alg_err(unsigned int udi_alg_err); +int iSetHPRE_DIDO_ERR_INFO_di_len_err(unsigned int udi_len_err); +int iSetHPRE_DIDO_ERR_INFO_di_strb_err(unsigned int udi_strb_err); +int iSetHPRE_DIDO_ERR_INFO_di_fifo_err(unsigned int udi_fifo_err); +int iSetHPRE_DIDO_ERR_INFO_di_axi_wr_err(unsigned int udi_axi_wr_err); +int iSetHPRE_DIDO_ERR_INFO_di_credit_err(unsigned int udi_credit_err); +int iSetHPRE_DIDO_ERR_INFO_do_credit_err(unsigned int udo_credit_err); +int iSetHPRE_DIDO_ERR_INFO_do_fifo_err(unsigned int udo_fifo_err); +int iSetHPRE_DIDO_ERR_INFO_do_axi_rd_err(unsigned int udo_axi_rd_err); +int iSetHPRE_FSM_SHB_CFG_fsm_shb_num(unsigned int ufsm_shb_num); +int iSetHPRE_MEM_CTRL_0_hpre_mem_ctrl_0_bus(unsigned int uhpre_mem_ctrl_0_bus); +int iSetHPRE_MEM_CTRL_1_hpre_mem_ctrl_1_bus(unsigned int uhpre_mem_ctrl_1_bus); +int iSetHPRE_MEM_CTRL_2_hpre_mem_ctrl_2_bus(unsigned int uhpre_mem_ctrl_2_bus); +int iSetHPRE_MEM_CTRL_3_hpre_mem_ctrl_3_bus(unsigned int uhpre_mem_ctrl_3_bus); +int iSetHPRE_MEM_CTRL_4_hpre_mem_ctrl_4_bus(unsigned int uhpre_mem_ctrl_4_bus); +int iSetHPRE_RDCHN_INI_ST_rdchn_ini_st(unsigned int urdchn_ini_st); +int iSetHPRE_ECC1BIT_ERR_CNT_hpre_ecc1bit_err_cnt(unsigned int uhpre_ecc1bit_err_cnt); +int iSetHPRE_ECC2BIT_ERR_CNT_hpre_ecc2bit_err_cnt(unsigned int uhpre_ecc2bit_err_cnt); +int iSetHPRE_PEH_ECO1_hpre_peh_eco1(unsigned int uhpre_peh_eco1); +int iSetHPRE_PEH_ECO2_hpre_peh_eco2(unsigned int uhpre_peh_eco2); +int iSetHPRE_PEH_ECO3_hpre_peh_eco3(unsigned int uhpre_peh_eco3); +int iSetHPRE_PEH_ECO4_hpre_peh_eco4(unsigned int uhpre_peh_eco4); +int iSetHPRE_PEH_ECO5_hpre_peh_eco5(unsigned int uhpre_peh_eco5); +int iSetHPRE_ECO1_hpre_eco1(unsigned int uhpre_eco1); +int iSetHPRE_ECO2_hpre_eco2(unsigned int uhpre_eco2); +int iSetHPRE_ECO3_hpre_eco3(unsigned int uhpre_eco3); +int iSetHPRE_ECO4_hpre_eco4(unsigned int uhpre_eco4); + +/* Define the union csr_cbc_fifo_16k_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_fifo_16k_th : 8; /* [7:0] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_fifo_16k_th_u; + +/* Define the union csr_saa_ch_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 saa_ch_en : 14; /* [13:0] */ + u32 rsv_1 : 2; /* [15:14] */ + u32 cbc_clk_gate_en : 1; /* [16] */ + u32 rsv_2 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_saa_ch_en_u; + +/* Define the union csr_cbc_core_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_core_rsv : 16; /* [15:0] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_core_rsv_u; + +/* Define the union csr_sec_cluster_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_cluster_rsv : 24; /* [23:0] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sec_cluster_rsv_u; + +/* Define the union csr_sec_alu_addr_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alu_addr_i : 10; /* [9:0] */ + u32 rsv_5 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sec_alu_addr_i_u; + +/* Define the union csr_sec_alu_rdata_o_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alu_rdata_o : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sec_alu_rdata_o_u; + +/* Define the union csr_sec_cluster_saa_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sec_cluster_saa_cnt : 12; /* [11:0] */ + u32 rsv_7 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sec_cluster_saa_cnt_u; + +/* Define the union csr_cbc_probe_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_probe_addr : 16; /* [15:0] */ + u32 cbc_probe_cs : 4; /* [19:16] */ + u32 cbc_probe_req : 1; /* [20] */ + u32 rsv_8 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_probe_i_u; + +/* Define the union csr_cbc_probe_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_probe_rdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_probe_rdata_u; + +/* Define the union csr_cbc_fifo_probe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dfx_credit_dis_if : 1; /* [0] */ + u32 cbc_dfx_credit_dis_of : 1; /* [1] */ + u32 cbc_probe_bd_dis : 1; /* [2] */ + u32 rsv_9 : 1; /* [3] */ + u32 cbc_probe_ipsec_re : 1; /* [4] */ + u32 cbc_probe_fifo_sel : 1; /* [5] */ + u32 rsv_10 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_fifo_probe_ctrl_u; + +/* Define the union csr_cbc_fifo_probe_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_fifo_probe_stat : 16; /* [15:0] */ + u32 cbc_probe_ipsec_if_ept : 1; /* [16] */ + u32 cbc_probe_ipsec_of_ept : 1; /* [17] */ + u32 rsv_11 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_fifo_probe_stat_u; + +/* Define the union csr_cbc_bd_err_code_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_bd_err_code : 7; /* [6:0] */ + u32 rsv_12 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_bd_err_code_u; + +/* Define the union csr_cbc_bd_err_code_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_bd_err_code_clr : 1; /* [0] */ + u32 rsv_13 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_bd_err_code_clr_u; + +/* Define the union csr_cbc_bd_err_msk_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_bd_err_msk_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_bd_err_msk_l_u; + +/* Define the union csr_cbc_bd_err_msk_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_bd_err_msk_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_bd_err_msk_h_u; + +/* Define the union csr_cbc_fifo_probe_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_fifo_probe_rdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_fifo_probe_rdata_u; + +/* Define the union csr_cbc_ecc_err1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_ecc_err1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_ecc_err1_cnt_u; + +/* Define the union csr_cbc_ecc_err2_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_ecc_err2_addr : 11; /* [10:0] */ + u32 rsv_14 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_ecc_err2_addr_u; + +/* Define the union csr_ipsec_cbc_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_int_en : 24; /* [23:0] */ + u32 rsv_15 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_int_en_u; + +/* Define the union csr_ipsec_cbc_alm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_alm : 24; /* [23:0] */ + u32 rsv_16 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_alm_u; + +/* Define the union csr_ipsec_cbc_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_sta1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_sta1_u; + +/* Define the union csr_ipsec_cbc_sta2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_sta2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_sta2_u; + +/* Define the union csr_ipsec_cbc_sta3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_sta3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_sta3_u; + +/* Define the union csr_ipsec_cbc_sta4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_cbc_sta4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_cbc_sta4_u; + +/* Define the union csr_cbc_core_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_core_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_core_cnt_u; + +/* Define the union csr_cbc_dft_mem_ctrl_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dft_mem_ctrl_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_dft_mem_ctrl_0_u; + +/* Define the union csr_cbc_dft_mem_ctrl_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dft_mem_ctrl_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_dft_mem_ctrl_1_u; + +/* Define the union csr_cbc_dft_mem_ctrl_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dft_mem_ctrl_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_dft_mem_ctrl_2_u; + +/* Define the union csr_cbc_dft_mem_ctrl_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dft_mem_ctrl_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_dft_mem_ctrl_3_u; + +/* Define the union csr_cbc_dft_mem_ctrl_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cbc_dft_mem_ctrl_4 : 6; /* [5:0] */ + u32 rsv_17 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cbc_dft_mem_ctrl_4_u; + +/* Define the union csr_trng_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_tmout_th : 24; /* [23:0] */ + u32 trng_en : 1; /* [24] */ + u32 drop_random_cfg : 1; /* [25] */ + u32 rsv_18 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cfg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cbc_fifo_16k_th_u cbc_fifo_16k_th; /* 0 */ + volatile csr_saa_ch_en_u saa_ch_en; /* 4 */ + volatile csr_cbc_core_rsv_u cbc_core_rsv; /* 8 */ + volatile csr_sec_cluster_rsv_u sec_cluster_rsv; /* 10 */ + volatile csr_sec_alu_addr_i_u sec_alu_addr_i; /* 14 */ + volatile csr_sec_alu_rdata_o_u sec_alu_rdata_o; /* 18 */ + volatile csr_sec_cluster_saa_cnt_u sec_cluster_saa_cnt[14]; /* 20 */ + volatile csr_cbc_probe_i_u cbc_probe_i; /* 60 */ + volatile csr_cbc_probe_rdata_u cbc_probe_rdata; /* 64 */ + volatile csr_cbc_fifo_probe_ctrl_u cbc_fifo_probe_ctrl; /* 68 */ + volatile csr_cbc_fifo_probe_stat_u cbc_fifo_probe_stat; /* 6C */ + volatile csr_cbc_bd_err_code_u cbc_bd_err_code; /* A0 */ + volatile csr_cbc_bd_err_code_clr_u cbc_bd_err_code_clr; /* A4 */ + volatile csr_cbc_bd_err_msk_l_u cbc_bd_err_msk_l; /* A8 */ + volatile csr_cbc_bd_err_msk_h_u cbc_bd_err_msk_h; /* AC */ + volatile csr_cbc_fifo_probe_rdata_u cbc_fifo_probe_rdata[8]; /* 70 */ + volatile csr_cbc_ecc_err1_cnt_u cbc_ecc_err1_cnt; /* B0 */ + volatile csr_cbc_ecc_err2_addr_u cbc_ecc_err2_addr; /* B4 */ + volatile csr_ipsec_cbc_int_en_u ipsec_cbc_int_en; /* FC */ + volatile csr_ipsec_cbc_alm_u ipsec_cbc_alm; /* 100 */ + volatile csr_ipsec_cbc_sta1_u ipsec_cbc_sta1; /* 104 */ + volatile csr_ipsec_cbc_sta2_u ipsec_cbc_sta2; /* 108 */ + volatile csr_ipsec_cbc_sta3_u ipsec_cbc_sta3; /* 10C */ + volatile csr_ipsec_cbc_sta4_u ipsec_cbc_sta4; /* 110 */ + volatile csr_cbc_core_cnt_u cbc_core_cnt; /* 114 */ + volatile csr_cbc_dft_mem_ctrl_0_u cbc_dft_mem_ctrl_0; /* 150 */ + volatile csr_cbc_dft_mem_ctrl_1_u cbc_dft_mem_ctrl_1; /* 154 */ + volatile csr_cbc_dft_mem_ctrl_2_u cbc_dft_mem_ctrl_2; /* 158 */ + volatile csr_cbc_dft_mem_ctrl_3_u cbc_dft_mem_ctrl_3; /* 15C */ + volatile csr_cbc_dft_mem_ctrl_4_u cbc_dft_mem_ctrl_4; /* 160 */ + volatile csr_trng_cfg_u trng_cfg; /* 170 */ +} S_ipsec_cbc_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ipsec_cbc_csr */ +extern volatile S_ipsec_cbc_csr_REGS_TYPE *gopipsec_cbc_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCBC_FIFO_16K_TH_cbc_fifo_16k_th(unsigned int ucbc_fifo_16k_th); +int iSetSAA_CH_EN_saa_ch_en(unsigned int usaa_ch_en); +int iSetSAA_CH_EN_cbc_clk_gate_en(unsigned int ucbc_clk_gate_en); +int iSetCBC_CORE_RSV_cbc_core_rsv(unsigned int ucbc_core_rsv); +int iSetSEC_CLUSTER_RSV_sec_cluster_rsv(unsigned int usec_cluster_rsv); +int iSetSEC_ALU_ADDR_I_alu_addr_i(unsigned int ualu_addr_i); +int iSetSEC_ALU_RDATA_O_alu_rdata_o(unsigned int ualu_rdata_o); +int iSetSEC_CLUSTER_SAA_CNT_sec_cluster_saa_cnt(unsigned int usec_cluster_saa_cnt); +int iSetCBC_PROBE_I_cbc_probe_addr(unsigned int ucbc_probe_addr); +int iSetCBC_PROBE_I_cbc_probe_cs(unsigned int ucbc_probe_cs); +int iSetCBC_PROBE_I_cbc_probe_req(unsigned int ucbc_probe_req); +int iSetCBC_PROBE_RDATA_cbc_probe_rdata(unsigned int ucbc_probe_rdata); +int iSetCBC_FIFO_PROBE_CTRL_cbc_dfx_credit_dis_if(unsigned int ucbc_dfx_credit_dis_if); +int iSetCBC_FIFO_PROBE_CTRL_cbc_dfx_credit_dis_of(unsigned int ucbc_dfx_credit_dis_of); +int iSetCBC_FIFO_PROBE_CTRL_cbc_probe_bd_dis(unsigned int ucbc_probe_bd_dis); +int iSetCBC_FIFO_PROBE_CTRL_cbc_probe_ipsec_re(unsigned int ucbc_probe_ipsec_re); +int iSetCBC_FIFO_PROBE_CTRL_cbc_probe_fifo_sel(unsigned int ucbc_probe_fifo_sel); +int iSetCBC_FIFO_PROBE_STAT_cbc_fifo_probe_stat(unsigned int ucbc_fifo_probe_stat); +int iSetCBC_FIFO_PROBE_STAT_cbc_probe_ipsec_if_ept(unsigned int ucbc_probe_ipsec_if_ept); +int iSetCBC_FIFO_PROBE_STAT_cbc_probe_ipsec_of_ept(unsigned int ucbc_probe_ipsec_of_ept); +int iSetCBC_BD_ERR_CODE_cbc_bd_err_code(unsigned int ucbc_bd_err_code); +int iSetCBC_BD_ERR_CODE_CLR_cbc_bd_err_code_clr(unsigned int ucbc_bd_err_code_clr); +int iSetCBC_BD_ERR_MSK_L_cbc_bd_err_msk_l(unsigned int ucbc_bd_err_msk_l); +int iSetCBC_BD_ERR_MSK_H_cbc_bd_err_msk_h(unsigned int ucbc_bd_err_msk_h); +int iSetCBC_FIFO_PROBE_RDATA_cbc_fifo_probe_rdata(unsigned int ucbc_fifo_probe_rdata); +int iSetCBC_ECC_ERR1_CNT_cbc_ecc_err1_cnt(unsigned int ucbc_ecc_err1_cnt); +int iSetCBC_ECC_ERR2_ADDR_cbc_ecc_err2_addr(unsigned int ucbc_ecc_err2_addr); +int iSetIPSEC_CBC_INT_EN_ipsec_cbc_int_en(unsigned int uipsec_cbc_int_en); +int iSetIPSEC_CBC_ALM_ipsec_cbc_alm(unsigned int uipsec_cbc_alm); +int iSetIPSEC_CBC_STA1_ipsec_cbc_sta1(unsigned int uipsec_cbc_sta1); +int iSetIPSEC_CBC_STA2_ipsec_cbc_sta2(unsigned int uipsec_cbc_sta2); +int iSetIPSEC_CBC_STA3_ipsec_cbc_sta3(unsigned int uipsec_cbc_sta3); +int iSetIPSEC_CBC_STA4_ipsec_cbc_sta4(unsigned int uipsec_cbc_sta4); +int iSetCBC_CORE_CNT_cbc_core_cnt(unsigned int ucbc_core_cnt); +int iSetCBC_DFT_MEM_CTRL_0_cbc_dft_mem_ctrl_0(unsigned int ucbc_dft_mem_ctrl_0); +int iSetCBC_DFT_MEM_CTRL_1_cbc_dft_mem_ctrl_1(unsigned int ucbc_dft_mem_ctrl_1); +int iSetCBC_DFT_MEM_CTRL_2_cbc_dft_mem_ctrl_2(unsigned int ucbc_dft_mem_ctrl_2); +int iSetCBC_DFT_MEM_CTRL_3_cbc_dft_mem_ctrl_3(unsigned int ucbc_dft_mem_ctrl_3); +int iSetCBC_DFT_MEM_CTRL_4_cbc_dft_mem_ctrl_4(unsigned int ucbc_dft_mem_ctrl_4); +int iSetTRNG_CFG_trng_tmout_th(unsigned int utrng_tmout_th); +int iSetTRNG_CFG_trng_en(unsigned int utrng_en); +int iSetTRNG_CFG_drop_random_cfg(unsigned int udrop_random_cfg); + +/* Define the union csr_gcm_fifo_16k_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_fifo_16k_th : 8; /* [7:0] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_fifo_16k_th_u; + +/* Define the union csr_gcm_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_clk_gate_en : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_ctrl_u; + +/* Define the union csr_gcm_core_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_core_rsv : 16; /* [15:0] */ + u32 rsv_2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_core_rsv_u; + +/* Define the union csr_gcm_cluster_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_cluster_rsv : 24; /* [23:0] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_cluster_rsv_u; + +/* Define the union csr_gcm_probe_i_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_probe_addr : 16; /* [15:0] */ + u32 gcm_probe_cs : 4; /* [19:16] */ + u32 gcm_probe_req : 1; /* [20] */ + u32 rsv_4 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_probe_i_u; + +/* Define the union csr_gcm_probe_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_probe_rdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_probe_rdata_u; + +/* Define the union csr_gcm_fifo_probe_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_dfx_credit_dis_if : 1; /* [0] */ + u32 gcm_dfx_credit_dis_of : 1; /* [1] */ + u32 gcm_probe_bd_dis : 1; /* [2] */ + u32 rsv_5 : 1; /* [3] */ + u32 gcm_probe_ipsec_re : 1; /* [4] */ + u32 gcm_probe_fifo_sel : 1; /* [5] */ + u32 rsv_6 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_fifo_probe_ctrl_u; + +/* Define the union csr_gcm_fifo_probe_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_fifo_probe_stat : 16; /* [15:0] */ + u32 gcm_probe_ipsec_if_ept : 1; /* [16] */ + u32 gcm_probe_ipsec_of_ept : 1; /* [17] */ + u32 rsv_7 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_fifo_probe_stat_u; + +/* Define the union csr_gcm_fifo_probe_rdata_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_fifo_probe_rdata : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_fifo_probe_rdata_u; + +/* Define the union csr_gcm_bd_err_code_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_bd_err_code : 7; /* [6:0] */ + u32 rsv_8 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_bd_err_code_u; + +/* Define the union csr_gcm_bd_err_code_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_bd_err_code_clr : 1; /* [0] */ + u32 rsv_9 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_bd_err_code_clr_u; + +/* Define the union csr_gcm_bd_err_msk_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_bd_err_msk_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_bd_err_msk_l_u; + +/* Define the union csr_gcm_bd_err_msk_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_bd_err_msk_h : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_bd_err_msk_h_u; + +/* Define the union csr_gcm_ecc_err1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_ecc_err1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_ecc_err1_cnt_u; + +/* Define the union csr_gcm_ecc_err2_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 gcm_ecc_err2_addr : 12; /* [11:0] */ + u32 rsv_10 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_gcm_ecc_err2_addr_u; + +/* Define the union csr_ipsec_gcm_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_int_en : 24; /* [23:0] */ + u32 rsv_11 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_int_en_u; + +/* Define the union csr_ipsec_gcm_alm_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_alm : 24; /* [23:0] */ + u32 rsv_12 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_alm_u; + +/* Define the union csr_ipsec_gcm_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta1_u; + +/* Define the union csr_ipsec_gcm_sta2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta2_u; + +/* Define the union csr_ipsec_gcm_sta3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta3_u; + +/* Define the union csr_ipsec_gcm_sta4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta4_u; + +/* Define the union csr_ipsec_gcm_sta5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta5_u; + +/* Define the union csr_ipsec_gcm_sta6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta6_u; + +/* Define the union csr_ipsec_gcm_sta7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta7_u; + +/* Define the union csr_ipsec_gcm_sta8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta8_u; + +/* Define the union csr_ipsec_gcm_sta9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta9_u; + +/* Define the union csr_ipsec_gcm_sta10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta10_u; + +/* Define the union csr_ipsec_gcm_sta11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta11_u; + +/* Define the union csr_ipsec_gcm_sta12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsec_gcm_sta12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsec_gcm_sta12_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_gcm_fifo_16k_th_u gcm_fifo_16k_th; /* 0 */ + volatile csr_gcm_ctrl_u gcm_ctrl; /* 4 */ + volatile csr_gcm_core_rsv_u gcm_core_rsv; /* 8 */ + volatile csr_gcm_cluster_rsv_u gcm_cluster_rsv; /* 10 */ + volatile csr_gcm_probe_i_u gcm_probe_i; /* 20 */ + volatile csr_gcm_probe_rdata_u gcm_probe_rdata; /* 24 */ + volatile csr_gcm_fifo_probe_ctrl_u gcm_fifo_probe_ctrl; /* 28 */ + volatile csr_gcm_fifo_probe_stat_u gcm_fifo_probe_stat; /* 2C */ + volatile csr_gcm_fifo_probe_rdata_u gcm_fifo_probe_rdata[8]; /* 30 */ + volatile csr_gcm_bd_err_code_u gcm_bd_err_code; /* A0 */ + volatile csr_gcm_bd_err_code_clr_u gcm_bd_err_code_clr; /* A4 */ + volatile csr_gcm_bd_err_msk_l_u gcm_bd_err_msk_l; /* A8 */ + volatile csr_gcm_bd_err_msk_h_u gcm_bd_err_msk_h; /* AC */ + volatile csr_gcm_ecc_err1_cnt_u gcm_ecc_err1_cnt; /* B0 */ + volatile csr_gcm_ecc_err2_addr_u gcm_ecc_err2_addr; /* B4 */ + volatile csr_ipsec_gcm_int_en_u ipsec_gcm_int_en; /* FC */ + volatile csr_ipsec_gcm_alm_u ipsec_gcm_alm; /* 100 */ + volatile csr_ipsec_gcm_sta1_u ipsec_gcm_sta1; /* 104 */ + volatile csr_ipsec_gcm_sta2_u ipsec_gcm_sta2; /* 108 */ + volatile csr_ipsec_gcm_sta3_u ipsec_gcm_sta3; /* 10C */ + volatile csr_ipsec_gcm_sta4_u ipsec_gcm_sta4; /* 110 */ + volatile csr_ipsec_gcm_sta5_u ipsec_gcm_sta5; /* 114 */ + volatile csr_ipsec_gcm_sta6_u ipsec_gcm_sta6; /* 118 */ + volatile csr_ipsec_gcm_sta7_u ipsec_gcm_sta7; /* 11C */ + volatile csr_ipsec_gcm_sta8_u ipsec_gcm_sta8; /* 120 */ + volatile csr_ipsec_gcm_sta9_u ipsec_gcm_sta9; /* 124 */ + volatile csr_ipsec_gcm_sta10_u ipsec_gcm_sta10; /* 128 */ + volatile csr_ipsec_gcm_sta11_u ipsec_gcm_sta11; /* 12C */ + volatile csr_ipsec_gcm_sta12_u ipsec_gcm_sta12; /* 130 */ +} S_ipsec_gcm_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ipsec_gcm_csr */ +extern volatile S_ipsec_gcm_csr_REGS_TYPE *gopipsec_gcm_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetGCM_FIFO_16K_TH_gcm_fifo_16k_th(unsigned int ugcm_fifo_16k_th); +int iSetGCM_CTRL_gcm_clk_gate_en(unsigned int ugcm_clk_gate_en); +int iSetGCM_CORE_RSV_gcm_core_rsv(unsigned int ugcm_core_rsv); +int iSetGCM_CLUSTER_RSV_gcm_cluster_rsv(unsigned int ugcm_cluster_rsv); +int iSetGCM_PROBE_I_gcm_probe_addr(unsigned int ugcm_probe_addr); +int iSetGCM_PROBE_I_gcm_probe_cs(unsigned int ugcm_probe_cs); +int iSetGCM_PROBE_I_gcm_probe_req(unsigned int ugcm_probe_req); +int iSetGCM_PROBE_RDATA_gcm_probe_rdata(unsigned int ugcm_probe_rdata); +int iSetGCM_FIFO_PROBE_CTRL_gcm_dfx_credit_dis_if(unsigned int ugcm_dfx_credit_dis_if); +int iSetGCM_FIFO_PROBE_CTRL_gcm_dfx_credit_dis_of(unsigned int ugcm_dfx_credit_dis_of); +int iSetGCM_FIFO_PROBE_CTRL_gcm_probe_bd_dis(unsigned int ugcm_probe_bd_dis); +int iSetGCM_FIFO_PROBE_CTRL_gcm_probe_ipsec_re(unsigned int ugcm_probe_ipsec_re); +int iSetGCM_FIFO_PROBE_CTRL_gcm_probe_fifo_sel(unsigned int ugcm_probe_fifo_sel); +int iSetGCM_FIFO_PROBE_STAT_gcm_fifo_probe_stat(unsigned int ugcm_fifo_probe_stat); +int iSetGCM_FIFO_PROBE_STAT_gcm_probe_ipsec_if_ept(unsigned int ugcm_probe_ipsec_if_ept); +int iSetGCM_FIFO_PROBE_STAT_gcm_probe_ipsec_of_ept(unsigned int ugcm_probe_ipsec_of_ept); +int iSetGCM_FIFO_PROBE_RDATA_gcm_fifo_probe_rdata(unsigned int ugcm_fifo_probe_rdata); +int iSetGCM_BD_ERR_CODE_gcm_bd_err_code(unsigned int ugcm_bd_err_code); +int iSetGCM_BD_ERR_CODE_CLR_gcm_bd_err_code_clr(unsigned int ugcm_bd_err_code_clr); +int iSetGCM_BD_ERR_MSK_L_gcm_bd_err_msk_l(unsigned int ugcm_bd_err_msk_l); +int iSetGCM_BD_ERR_MSK_H_gcm_bd_err_msk_h(unsigned int ugcm_bd_err_msk_h); +int iSetGCM_ECC_ERR1_CNT_gcm_ecc_err1_cnt(unsigned int ugcm_ecc_err1_cnt); +int iSetGCM_ECC_ERR2_ADDR_gcm_ecc_err2_addr(unsigned int ugcm_ecc_err2_addr); +int iSetIPSEC_GCM_INT_EN_ipsec_gcm_int_en(unsigned int uipsec_gcm_int_en); +int iSetIPSEC_GCM_ALM_ipsec_gcm_alm(unsigned int uipsec_gcm_alm); +int iSetIPSEC_GCM_STA1_ipsec_gcm_sta1(unsigned int uipsec_gcm_sta1); +int iSetIPSEC_GCM_STA2_ipsec_gcm_sta2(unsigned int uipsec_gcm_sta2); +int iSetIPSEC_GCM_STA3_ipsec_gcm_sta3(unsigned int uipsec_gcm_sta3); +int iSetIPSEC_GCM_STA4_ipsec_gcm_sta4(unsigned int uipsec_gcm_sta4); +int iSetIPSEC_GCM_STA5_ipsec_gcm_sta5(unsigned int uipsec_gcm_sta5); +int iSetIPSEC_GCM_STA6_ipsec_gcm_sta6(unsigned int uipsec_gcm_sta6); +int iSetIPSEC_GCM_STA7_ipsec_gcm_sta7(unsigned int uipsec_gcm_sta7); +int iSetIPSEC_GCM_STA8_ipsec_gcm_sta8(unsigned int uipsec_gcm_sta8); +int iSetIPSEC_GCM_STA9_ipsec_gcm_sta9(unsigned int uipsec_gcm_sta9); +int iSetIPSEC_GCM_STA10_ipsec_gcm_sta10(unsigned int uipsec_gcm_sta10); +int iSetIPSEC_GCM_STA11_ipsec_gcm_sta11(unsigned int uipsec_gcm_sta11); +int iSetIPSEC_GCM_STA12_ipsec_gcm_sta12(unsigned int uipsec_gcm_sta12); + +/* Define the union csr_xts_key1_cfg7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg7_u; + +/* Define the union csr_xts_key1_cfg6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg6_u; + +/* Define the union csr_xts_key1_cfg5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg5_u; + +/* Define the union csr_xts_key1_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg4_u; + +/* Define the union csr_xts_key1_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg3_u; + +/* Define the union csr_xts_key1_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg2_u; + +/* Define the union csr_xts_key1_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg1_u; + +/* Define the union csr_xts_key1_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key1_cfg0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key1_cfg0_u; + +/* Define the union csr_xts_key2_cfg7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg7_u; + +/* Define the union csr_xts_key2_cfg6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg6_u; + +/* Define the union csr_xts_key2_cfg5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg5_u; + +/* Define the union csr_xts_key2_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg4_u; + +/* Define the union csr_xts_key2_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg3_u; + +/* Define the union csr_xts_key2_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg2_u; + +/* Define the union csr_xts_key2_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg1_u; + +/* Define the union csr_xts_key2_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key2_cfg0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key2_cfg0_u; + +/* Define the union csr_xts_key_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key_idx : 9; /* [8:0] */ + u32 rsv_0 : 7; /* [15:9] */ + u32 xts_key12_sel : 2; /* [17:16] */ + u32 xts_key256_sel : 2; /* [19:18] */ + u32 xts_key_opr : 2; /* [21:20] */ + u32 rsv_1 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key_ctrl_u; + +/* Define the union csr_xts_key_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_key_crc : 16; /* [15:0] */ + u32 xts_key_opr_busy : 1; /* [16] */ + u32 rsv_2 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_key_stat_u; + +/* Define the union csr_xtx_mem_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_mem_init : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xtx_mem_init_u; + +/* Define the union csr_xts_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 xts_mem_init_done : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_xts_mem_init_done_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_xts_key1_cfg7_u xts_key1_cfg7; /* 0 */ + volatile csr_xts_key1_cfg6_u xts_key1_cfg6; /* 4 */ + volatile csr_xts_key1_cfg5_u xts_key1_cfg5; /* 8 */ + volatile csr_xts_key1_cfg4_u xts_key1_cfg4; /* C */ + volatile csr_xts_key1_cfg3_u xts_key1_cfg3; /* 10 */ + volatile csr_xts_key1_cfg2_u xts_key1_cfg2; /* 14 */ + volatile csr_xts_key1_cfg1_u xts_key1_cfg1; /* 18 */ + volatile csr_xts_key1_cfg0_u xts_key1_cfg0; /* 1C */ + volatile csr_xts_key2_cfg7_u xts_key2_cfg7; /* 20 */ + volatile csr_xts_key2_cfg6_u xts_key2_cfg6; /* 24 */ + volatile csr_xts_key2_cfg5_u xts_key2_cfg5; /* 28 */ + volatile csr_xts_key2_cfg4_u xts_key2_cfg4; /* 2C */ + volatile csr_xts_key2_cfg3_u xts_key2_cfg3; /* 30 */ + volatile csr_xts_key2_cfg2_u xts_key2_cfg2; /* 34 */ + volatile csr_xts_key2_cfg1_u xts_key2_cfg1; /* 38 */ + volatile csr_xts_key2_cfg0_u xts_key2_cfg0; /* 3C */ + volatile csr_xts_key_ctrl_u xts_key_ctrl; /* 40 */ + volatile csr_xts_key_stat_u xts_key_stat; /* 44 */ + volatile csr_xtx_mem_init_u xtx_mem_init; /* 48 */ + volatile csr_xts_mem_init_done_u xts_mem_init_done; /* 4C */ +} S_ipsec_key_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ipsec_key_csr */ +extern volatile S_ipsec_key_csr_REGS_TYPE *gopipsec_key_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetXTS_KEY1_CFG7_xts_key1_cfg7(unsigned int uxts_key1_cfg7); +int iSetXTS_KEY1_CFG6_xts_key1_cfg6(unsigned int uxts_key1_cfg6); +int iSetXTS_KEY1_CFG5_xts_key1_cfg5(unsigned int uxts_key1_cfg5); +int iSetXTS_KEY1_CFG4_xts_key1_cfg4(unsigned int uxts_key1_cfg4); +int iSetXTS_KEY1_CFG3_xts_key1_cfg3(unsigned int uxts_key1_cfg3); +int iSetXTS_KEY1_CFG2_xts_key1_cfg2(unsigned int uxts_key1_cfg2); +int iSetXTS_KEY1_CFG1_xts_key1_cfg1(unsigned int uxts_key1_cfg1); +int iSetXTS_KEY1_CFG0_xts_key1_cfg0(unsigned int uxts_key1_cfg0); +int iSetXTS_KEY2_CFG7_xts_key2_cfg7(unsigned int uxts_key2_cfg7); +int iSetXTS_KEY2_CFG6_xts_key2_cfg6(unsigned int uxts_key2_cfg6); +int iSetXTS_KEY2_CFG5_xts_key2_cfg5(unsigned int uxts_key2_cfg5); +int iSetXTS_KEY2_CFG4_xts_key2_cfg4(unsigned int uxts_key2_cfg4); +int iSetXTS_KEY2_CFG3_xts_key2_cfg3(unsigned int uxts_key2_cfg3); +int iSetXTS_KEY2_CFG2_xts_key2_cfg2(unsigned int uxts_key2_cfg2); +int iSetXTS_KEY2_CFG1_xts_key2_cfg1(unsigned int uxts_key2_cfg1); +int iSetXTS_KEY2_CFG0_xts_key2_cfg0(unsigned int uxts_key2_cfg0); +int iSetXTS_KEY_CTRL_xts_key_idx(unsigned int uxts_key_idx); +int iSetXTS_KEY_CTRL_xts_key12_sel(unsigned int uxts_key12_sel); +int iSetXTS_KEY_CTRL_xts_key256_sel(unsigned int uxts_key256_sel); +int iSetXTS_KEY_CTRL_xts_key_opr(unsigned int uxts_key_opr); +int iSetXTS_KEY_STAT_xts_key_crc(unsigned int uxts_key_crc); +int iSetXTS_KEY_STAT_xts_key_opr_busy(unsigned int uxts_key_opr_busy); +int iSetXTX_MEM_INIT_xts_mem_init(unsigned int uxts_mem_init); +int iSetXTS_MEM_INIT_DONE_xts_mem_init_done(unsigned int uxts_mem_init_done); + +/* Define the union csr_sram_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init : 1; /* [0] */ + u32 reg_lowpower : 1; /* [1] */ + u32 ecc_en : 1; /* [2] */ + u32 multi_ecc_report : 1; /* [3] */ + u32 excl_endian : 1; /* [4] */ + u32 cnt_en : 1; /* [5] */ + u32 decerr_report : 1; /* [6] */ + u32 rsv_0 : 1; /* [7] */ + u32 base_addr_en : 1; /* [8] */ + u32 exinc_en : 1; /* [9] */ + u32 exdec_en : 1; /* [10] */ + u32 mbist_en : 1; /* [11] */ + u32 rdwrap_dis : 1; /* [12] */ + u32 rsv_1 : 3; /* [15:13] */ + u32 rsv_2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_ctrl_u; + +/* Define the union csr_sram_state_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 init_over : 1; /* [0] */ + u32 wrfifo_empty : 1; /* [1] */ + u32 rdfifo_empty : 1; /* [2] */ + u32 wdatfifo_empty : 1; /* [3] */ + u32 pipe_empty : 1; /* [4] */ + u32 resp_empty : 1; /* [5] */ + u32 rsv_3 : 2; /* [7:6] */ + u32 decode_error : 1; /* [8] */ + u32 slave_error : 1; /* [9] */ + u32 ns_error : 1; /* [10] */ + u32 single_ecc : 1; /* [11] */ + u32 multi_ecc : 1; /* [12] */ + u32 buscfg_rderr : 1; /* [13] */ + u32 buscfg_wrerr : 1; /* [14] */ + u32 buscfg_wrcft : 1; /* [15] */ + u32 rsv_4 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_state_u; + +/* Define the union csr_sram_sec_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sec_en : 1; /* [0] */ + u32 rsv_5 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_sec_ctrl_u; + +/* Define the union csr_sram_sec_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sec_addr : 13; /* [12:0] */ + u32 rsv_6 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_sec_addr_u; + +/* Define the union csr_sram_sec_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_sec_size : 5; /* [4:0] */ + u32 rsv_7 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_sec_size_u; + +/* Define the union csr_sram_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 reg_base_addr : 13; /* [12:0] */ + u32 rsv_8 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_base_addr_u; + +/* Define the union csr_sram_intmask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 decerr_intmsk : 1; /* [0] */ + u32 slverr_intmsk : 1; /* [1] */ + u32 nserr_intmsk : 1; /* [2] */ + u32 ecc_intmsk : 1; /* [3] */ + u32 cnt0_intmsk : 1; /* [4] */ + u32 cnt1_intmsk : 1; /* [5] */ + u32 cnt2_intmsk : 1; /* [6] */ + u32 cnt3_intmsk : 1; /* [7] */ + u32 buserr_intmsk : 1; /* [8] */ + u32 rsv_9 : 3; /* [11:9] */ + u32 rsv_10 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_intmask_u; + +/* Define the union csr_sram_rawint_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 decerr_rawint : 1; /* [0] */ + u32 slverr_rawint : 1; /* [1] */ + u32 nserr_rawint : 1; /* [2] */ + u32 ecc_rawint : 1; /* [3] */ + u32 cnt0_rawint : 1; /* [4] */ + u32 cnt1_rawint : 1; /* [5] */ + u32 cnt2_rawint : 1; /* [6] */ + u32 cnt3_rawint : 1; /* [7] */ + u32 buserr_rawint : 1; /* [8] */ + u32 rsv_11 : 3; /* [11:9] */ + u32 rsv_12 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_rawint_u; + +/* Define the union csr_sram_intsts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 decerr_intst : 1; /* [0] */ + u32 slverr_intst : 1; /* [1] */ + u32 nserr_intst : 1; /* [2] */ + u32 ecc_intst : 1; /* [3] */ + u32 cnt0_intst : 1; /* [4] */ + u32 cnt1_intst : 1; /* [5] */ + u32 cnt2_intst : 1; /* [6] */ + u32 cnt3_intst : 1; /* [7] */ + u32 buserr_intst : 1; /* [8] */ + u32 rsv_13 : 3; /* [11:9] */ + u32 rsv_14 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_intsts_u; + +/* Define the union csr_sram_intclr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 decerr_intclr : 1; /* [0] */ + u32 slverr_intclr : 1; /* [1] */ + u32 nserr_intclr : 1; /* [2] */ + u32 ecc_intclr : 1; /* [3] */ + u32 cnt0_intclr : 1; /* [4] */ + u32 cnt1_intclr : 1; /* [5] */ + u32 cnt2_intclr : 1; /* [6] */ + u32 cnt3_intclr : 1; /* [7] */ + u32 buserr_intclr : 1; /* [8] */ + u32 rsv_15 : 3; /* [11:9] */ + u32 rsv_16 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_intclr_u; + +/* Define the union csr_sram_ecc_inject_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bit1_sel : 7; /* [6:0] */ + u32 bit1_en : 1; /* [7] */ + u32 bit2_sel : 7; /* [14:8] */ + u32 bit2_en : 1; /* [15] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_ecc_inject_u; + +/* Define the union csr_sram_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 errinfo_id : 16; /* [15:0] */ + u32 errinfo_len : 6; /* [21:16] */ + u32 errinfo_size : 3; /* [24:22] */ + u32 errinfo_burst : 2; /* [26:25] */ + u32 errinfo_lock : 1; /* [27] */ + u32 errinfo_prot : 3; /* [30:28] */ + u32 errinfo_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_err_info_u; + +/* Define the union csr_sram_err_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_err_addr_u; + +/* Define the union csr_sram_ecc_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eccinfo_vec : 2; /* [1:0] */ + u32 rsv_18 : 2; /* [3:2] */ + u32 eccinfo_addr : 13; /* [16:4] */ + u32 rsv_19 : 7; /* [23:17] */ + u32 eccinfo_single : 1; /* [24] */ + u32 eccinfo_multi : 1; /* [25] */ + u32 rsv_20 : 2; /* [27:26] */ + u32 rsv_21 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_ecc_info_u; + +/* Define the union csr_sram_clr_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 clr_state : 1; /* [0] */ + u32 clr_ecc1_cnt : 1; /* [1] */ + u32 clr_ecc2_cnt : 1; /* [2] */ + u32 clr_err_info : 1; /* [3] */ + u32 clr_ecc_info : 1; /* [4] */ + u32 clr_cnt0 : 1; /* [5] */ + u32 clr_cnt1 : 1; /* [6] */ + u32 clr_cnt2 : 1; /* [7] */ + u32 clr_cnt3 : 1; /* [8] */ + u32 rsv_22 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_clr_stat_u; + +/* Define the union csr_sram_ecc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 single_ecc_cnt : 16; /* [15:0] */ + u32 multi_ecc_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_ecc_cnt_u; + +/* Define the union csr_sram_cnt_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_type : 4; /* [3:0] */ + u32 cnt1_type : 4; /* [7:4] */ + u32 cnt2_type : 4; /* [11:8] */ + u32 cnt3_type : 4; /* [15:12] */ + u32 rsv_23 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_cnt_type_u; + +/* Define the union csr_sram_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_cnt0_u; + +/* Define the union csr_sram_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_cnt1_u; + +/* Define the union csr_sram_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_cnt2_u; + +/* Define the union csr_sram_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dfx_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_cnt3_u; + +/* Define the union csr_sram_magic_word_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_24 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_magic_word_u; + +/* Define the union csr_sram_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hisilicon_version : 12; /* [11:0] */ + u32 sub_version : 4; /* [15:12] */ + u32 main_version : 4; /* [19:16] */ + u32 rsv_25 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sram_version_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_sram_ctrl_u sram_ctrl; /* 0 */ + volatile csr_sram_state_u sram_state; /* 4 */ + volatile csr_sram_sec_ctrl_u sram_sec_ctrl; /* 10 */ + volatile csr_sram_sec_addr_u sram_sec_addr; /* 14 */ + volatile csr_sram_sec_size_u sram_sec_size; /* 18 */ + volatile csr_sram_base_addr_u sram_base_addr; /* 20 */ + volatile csr_sram_intmask_u sram_intmask; /* 40 */ + volatile csr_sram_rawint_u sram_rawint; /* 44 */ + volatile csr_sram_intsts_u sram_intsts; /* 48 */ + volatile csr_sram_intclr_u sram_intclr; /* 4C */ + volatile csr_sram_ecc_inject_u sram_ecc_inject; /* 60 */ + volatile csr_sram_err_info_u sram_err_info; /* 64 */ + volatile csr_sram_err_addr_u sram_err_addr; /* 68 */ + volatile csr_sram_ecc_info_u sram_ecc_info; /* 6C */ + volatile csr_sram_clr_stat_u sram_clr_stat; /* 70 */ + volatile csr_sram_ecc_cnt_u sram_ecc_cnt; /* 80 */ + volatile csr_sram_cnt_type_u sram_cnt_type; /* 84 */ + volatile csr_sram_cnt0_u sram_cnt0; /* 88 */ + volatile csr_sram_cnt1_u sram_cnt1; /* 8C */ + volatile csr_sram_cnt2_u sram_cnt2; /* 90 */ + volatile csr_sram_cnt3_u sram_cnt3; /* 94 */ + volatile csr_sram_magic_word_u sram_magic_word; /* 7F0 */ + volatile csr_sram_version_u sram_version; /* C10 */ +} S_sram_REGS_TYPE; + +/* Declare the struct pointor of the module sram */ +extern volatile S_sram_REGS_TYPE *gopsramAllReg; + +/* Declare the functions that set the member value */ +int iSetSRAM_CTRL_init(unsigned int uinit); +int iSetSRAM_CTRL_reg_lowpower(unsigned int ureg_lowpower); +int iSetSRAM_CTRL_ecc_en(unsigned int uecc_en); +int iSetSRAM_CTRL_multi_ecc_report(unsigned int umulti_ecc_report); +int iSetSRAM_CTRL_excl_endian(unsigned int uexcl_endian); +int iSetSRAM_CTRL_cnt_en(unsigned int ucnt_en); +int iSetSRAM_CTRL_decerr_report(unsigned int udecerr_report); +int iSetSRAM_CTRL_base_addr_en(unsigned int ubase_addr_en); +int iSetSRAM_CTRL_exinc_en(unsigned int uexinc_en); +int iSetSRAM_CTRL_exdec_en(unsigned int uexdec_en); +int iSetSRAM_CTRL_mbist_en(unsigned int umbist_en); +int iSetSRAM_CTRL_rdwrap_dis(unsigned int urdwrap_dis); +int iSetSRAM_STATE_init_over(unsigned int uinit_over); +int iSetSRAM_STATE_wrfifo_empty(unsigned int uwrfifo_empty); +int iSetSRAM_STATE_rdfifo_empty(unsigned int urdfifo_empty); +int iSetSRAM_STATE_wdatfifo_empty(unsigned int uwdatfifo_empty); +int iSetSRAM_STATE_pipe_empty(unsigned int upipe_empty); +int iSetSRAM_STATE_resp_empty(unsigned int uresp_empty); +int iSetSRAM_STATE_decode_error(unsigned int udecode_error); +int iSetSRAM_STATE_slave_error(unsigned int uslave_error); +int iSetSRAM_STATE_ns_error(unsigned int uns_error); +int iSetSRAM_STATE_single_ecc(unsigned int usingle_ecc); +int iSetSRAM_STATE_multi_ecc(unsigned int umulti_ecc); +int iSetSRAM_STATE_buscfg_rderr(unsigned int ubuscfg_rderr); +int iSetSRAM_STATE_buscfg_wrerr(unsigned int ubuscfg_wrerr); +int iSetSRAM_STATE_buscfg_wrcft(unsigned int ubuscfg_wrcft); +int iSetSRAM_SEC_CTRL_reg_sec_en(unsigned int ureg_sec_en); +int iSetSRAM_SEC_ADDR_reg_sec_addr(unsigned int ureg_sec_addr); +int iSetSRAM_SEC_SIZE_reg_sec_size(unsigned int ureg_sec_size); +int iSetSRAM_BASE_ADDR_reg_base_addr(unsigned int ureg_base_addr); +int iSetSRAM_INTMASK_decerr_intmsk(unsigned int udecerr_intmsk); +int iSetSRAM_INTMASK_slverr_intmsk(unsigned int uslverr_intmsk); +int iSetSRAM_INTMASK_nserr_intmsk(unsigned int unserr_intmsk); +int iSetSRAM_INTMASK_ecc_intmsk(unsigned int uecc_intmsk); +int iSetSRAM_INTMASK_cnt0_intmsk(unsigned int ucnt0_intmsk); +int iSetSRAM_INTMASK_cnt1_intmsk(unsigned int ucnt1_intmsk); +int iSetSRAM_INTMASK_cnt2_intmsk(unsigned int ucnt2_intmsk); +int iSetSRAM_INTMASK_cnt3_intmsk(unsigned int ucnt3_intmsk); +int iSetSRAM_INTMASK_buserr_intmsk(unsigned int ubuserr_intmsk); +int iSetSRAM_RAWINT_decerr_rawint(unsigned int udecerr_rawint); +int iSetSRAM_RAWINT_slverr_rawint(unsigned int uslverr_rawint); +int iSetSRAM_RAWINT_nserr_rawint(unsigned int unserr_rawint); +int iSetSRAM_RAWINT_ecc_rawint(unsigned int uecc_rawint); +int iSetSRAM_RAWINT_cnt0_rawint(unsigned int ucnt0_rawint); +int iSetSRAM_RAWINT_cnt1_rawint(unsigned int ucnt1_rawint); +int iSetSRAM_RAWINT_cnt2_rawint(unsigned int ucnt2_rawint); +int iSetSRAM_RAWINT_cnt3_rawint(unsigned int ucnt3_rawint); +int iSetSRAM_RAWINT_buserr_rawint(unsigned int ubuserr_rawint); +int iSetSRAM_INTSTS_decerr_intst(unsigned int udecerr_intst); +int iSetSRAM_INTSTS_slverr_intst(unsigned int uslverr_intst); +int iSetSRAM_INTSTS_nserr_intst(unsigned int unserr_intst); +int iSetSRAM_INTSTS_ecc_intst(unsigned int uecc_intst); +int iSetSRAM_INTSTS_cnt0_intst(unsigned int ucnt0_intst); +int iSetSRAM_INTSTS_cnt1_intst(unsigned int ucnt1_intst); +int iSetSRAM_INTSTS_cnt2_intst(unsigned int ucnt2_intst); +int iSetSRAM_INTSTS_cnt3_intst(unsigned int ucnt3_intst); +int iSetSRAM_INTSTS_buserr_intst(unsigned int ubuserr_intst); +int iSetSRAM_INTCLR_decerr_intclr(unsigned int udecerr_intclr); +int iSetSRAM_INTCLR_slverr_intclr(unsigned int uslverr_intclr); +int iSetSRAM_INTCLR_nserr_intclr(unsigned int unserr_intclr); +int iSetSRAM_INTCLR_ecc_intclr(unsigned int uecc_intclr); +int iSetSRAM_INTCLR_cnt0_intclr(unsigned int ucnt0_intclr); +int iSetSRAM_INTCLR_cnt1_intclr(unsigned int ucnt1_intclr); +int iSetSRAM_INTCLR_cnt2_intclr(unsigned int ucnt2_intclr); +int iSetSRAM_INTCLR_cnt3_intclr(unsigned int ucnt3_intclr); +int iSetSRAM_INTCLR_buserr_intclr(unsigned int ubuserr_intclr); +int iSetSRAM_ECC_INJECT_bit1_sel(unsigned int ubit1_sel); +int iSetSRAM_ECC_INJECT_bit1_en(unsigned int ubit1_en); +int iSetSRAM_ECC_INJECT_bit2_sel(unsigned int ubit2_sel); +int iSetSRAM_ECC_INJECT_bit2_en(unsigned int ubit2_en); +int iSetSRAM_ERR_INFO_errinfo_id(unsigned int uerrinfo_id); +int iSetSRAM_ERR_INFO_errinfo_len(unsigned int uerrinfo_len); +int iSetSRAM_ERR_INFO_errinfo_size(unsigned int uerrinfo_size); +int iSetSRAM_ERR_INFO_errinfo_burst(unsigned int uerrinfo_burst); +int iSetSRAM_ERR_INFO_errinfo_lock(unsigned int uerrinfo_lock); +int iSetSRAM_ERR_INFO_errinfo_prot(unsigned int uerrinfo_prot); +int iSetSRAM_ERR_INFO_errinfo_en(unsigned int uerrinfo_en); +int iSetSRAM_ERR_ADDR_ecc_addr(unsigned int uecc_addr); +int iSetSRAM_ECC_INFO_eccinfo_vec(unsigned int ueccinfo_vec); +int iSetSRAM_ECC_INFO_eccinfo_addr(unsigned int ueccinfo_addr); +int iSetSRAM_ECC_INFO_eccinfo_single(unsigned int ueccinfo_single); +int iSetSRAM_ECC_INFO_eccinfo_multi(unsigned int ueccinfo_multi); +int iSetSRAM_CLR_STAT_clr_state(unsigned int uclr_state); +int iSetSRAM_CLR_STAT_clr_ecc1_cnt(unsigned int uclr_ecc1_cnt); +int iSetSRAM_CLR_STAT_clr_ecc2_cnt(unsigned int uclr_ecc2_cnt); +int iSetSRAM_CLR_STAT_clr_err_info(unsigned int uclr_err_info); +int iSetSRAM_CLR_STAT_clr_ecc_info(unsigned int uclr_ecc_info); +int iSetSRAM_CLR_STAT_clr_cnt0(unsigned int uclr_cnt0); +int iSetSRAM_CLR_STAT_clr_cnt1(unsigned int uclr_cnt1); +int iSetSRAM_CLR_STAT_clr_cnt2(unsigned int uclr_cnt2); +int iSetSRAM_CLR_STAT_clr_cnt3(unsigned int uclr_cnt3); +int iSetSRAM_ECC_CNT_single_ecc_cnt(unsigned int usingle_ecc_cnt); +int iSetSRAM_ECC_CNT_multi_ecc_cnt(unsigned int umulti_ecc_cnt); +int iSetSRAM_CNT_TYPE_cnt0_type(unsigned int ucnt0_type); +int iSetSRAM_CNT_TYPE_cnt1_type(unsigned int ucnt1_type); +int iSetSRAM_CNT_TYPE_cnt2_type(unsigned int ucnt2_type); +int iSetSRAM_CNT_TYPE_cnt3_type(unsigned int ucnt3_type); +int iSetSRAM_CNT0_dfx_cnt0(unsigned int udfx_cnt0); +int iSetSRAM_CNT1_dfx_cnt1(unsigned int udfx_cnt1); +int iSetSRAM_CNT2_dfx_cnt2(unsigned int udfx_cnt2); +int iSetSRAM_CNT3_dfx_cnt3(unsigned int udfx_cnt3); + +int iSetSRAM_VERSION_hisilicon_version(unsigned int uhisilicon_version); +int iSetSRAM_VERSION_sub_version(unsigned int usub_version); +int iSetSRAM_VERSION_main_version(unsigned int umain_version); + +/* Define the union csr_trng_output_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_output_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_output_0_u; + +/* Define the union csr_trng_output_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_output_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_output_1_u; + +/* Define the union csr_trng_output_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_output_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_output_2_u; + +/* Define the union csr_trng_output_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_output_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_output_3_u; + +/* Define the union csr_trng_input_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_input_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_input_0_u; + +/* Define the union csr_trng_input_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_input_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_input_1_u; + +/* Define the union csr_trng_input_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_input_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_input_2_u; + +/* Define the union csr_trng_input_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_input_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_input_3_u; + +/* Define the union csr_trng_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready : 1; /* [0] */ + u32 shutdown_oflo : 1; /* [1] */ + u32 stuck_out : 1; /* [2] */ + u32 noise_fail : 1; /* [3] */ + u32 run_fail : 1; /* [4] */ + u32 long_run_fail : 1; /* [5] */ + u32 poker_fail : 1; /* [6] */ + u32 monobit_fail : 1; /* [7] */ + u32 test_ready : 1; /* [8] */ + u32 stuck_nrbg : 1; /* [9] */ + u32 reseed_ai : 1; /* [10] */ + u32 rsv_0 : 2; /* [12:11] */ + u32 repcnt_fail : 1; /* [13] */ + u32 aprop_fail : 1; /* [14] */ + u32 test_stuck_out : 1; /* [15] */ + u32 blocks_available : 8; /* [23:16] */ + u32 blocks_thresh : 7; /* [30:24] */ + u32 need_clock : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_status_u; + +/* Define the union csr_trng_intack_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready_ack : 1; /* [0] */ + u32 shutdown_oflo_ack : 1; /* [1] */ + u32 stuck_out_ack : 1; /* [2] */ + u32 noise_fail_ack : 1; /* [3] */ + u32 run_fail_ack : 1; /* [4] */ + u32 long_run_fail_ack : 1; /* [5] */ + u32 poker_fail_ack : 1; /* [6] */ + u32 monobit_fail_ack : 1; /* [7] */ + u32 test_ready_ack : 1; /* [8] */ + u32 stuck_nrbg_ack : 1; /* [9] */ + u32 open_read_gate : 3; /* [12:10] */ + u32 repcnt_fail_ack : 1; /* [13] */ + u32 aprop_fail_ack : 1; /* [14] */ + u32 test_stuck_out : 1; /* [15] */ + u32 rsv_1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_intack_u; + +/* Define the union csr_trng_control_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ready_mask : 1; /* [0] */ + u32 shutdown_oflo_mask : 1; /* [1] */ + u32 stuck_out_mask : 1; /* [2] */ + u32 noise_fail_mask : 1; /* [3] */ + u32 run_fail_mask : 1; /* [4] */ + u32 long_run_fail_mask : 1; /* [5] */ + u32 poker_fail_mask : 1; /* [6] */ + u32 monobit_fail_mask : 1; /* [7] */ + u32 test_mode : 1; /* [8] */ + u32 stuck_nrbg_mask : 1; /* [9] */ + u32 enable_trng : 1; /* [10] */ + u32 no_whitening : 1; /* [11] */ + u32 drbg_en : 1; /* [12] */ + u32 repcnt_fail_mask : 1; /* [13] */ + u32 aprop_fail_mask : 1; /* [14] */ + u32 re_seed : 1; /* [15] */ + u32 request_data : 1; /* [16] */ + u32 request_hold : 1; /* [17] */ + u32 rsv_2 : 2; /* [19:18] */ + u32 data_blocks : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_control_u; + +/* Define the union csr_trng_config_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 noise_blocks : 5; /* [4:0] */ + u32 use_startup_bits : 1; /* [5] */ + u32 scale : 2; /* [7:6] */ + u32 sample_div : 4; /* [11:8] */ + u32 read_timeout : 4; /* [15:12] */ + u32 sample_cycles : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_config_u; + +/* Define the union csr_trng_alarmcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 alarm_threshold : 8; /* [7:0] */ + u32 rsv_3 : 7; /* [14:8] */ + u32 stall_run_poker : 1; /* [15] */ + u32 shutdown_threshold : 5; /* [20:16] */ + u32 rsv_4 : 2; /* [22:21] */ + u32 shutdown_fatal : 1; /* [23] */ + u32 shutdown_count : 6; /* [29:24] */ + u32 rsv_5 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_alarmcnt_u; + +/* Define the union csr_trng_froenable_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fro_enables : 8; /* [7:0] */ + u32 rsv_6 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_froenable_u; + +/* Define the union csr_trng_frodetune_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fro_detunes : 8; /* [7:0] */ + u32 rsv_7 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_frodetune_u; + +/* Define the union csr_trng_alarmmask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fro_alarmmasks : 8; /* [7:0] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_alarmmask_u; + +/* Define the union csr_trng_alarmstop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fro_alarmstops : 8; /* [7:0] */ + u32 rsv_9 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_alarmstop_u; + +/* Define the union csr_trng_raw_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 shift_reg_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_raw_l_u; + +/* Define the union csr_trng_raw_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 shift_reg_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_raw_h_u; + +/* Define the union csr_trng_spb_tests_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 repcnt : 6; /* [5:0] */ + u32 repcnt_value_h : 2; /* [7:6] */ + u32 aprop_64 : 6; /* [13:8] */ + u32 aprop_64_value_h : 2; /* [15:14] */ + u32 aprop_512 : 8; /* [23:16] */ + u32 aprop_512_h : 4; /* [27:24] */ + u32 show_counters : 1; /* [28] */ + u32 show_values : 1; /* [29] */ + u32 aprop_64_fail : 1; /* [30] */ + u32 aprop_512_fail : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_spb_tests_u; + +/* Define the union csr_trng_count_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sample_cyc_cnt : 16; /* [15:0] */ + u32 noise_blk_cnt : 5; /* [20:16] */ + u32 rsv_10 : 3; /* [23:21] */ + u32 sample_cyc_ext : 6; /* [29:24] */ + u32 rsv_11 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_count_u; + +/* Define the union csr_trng_cond_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_0_u; + +/* Define the union csr_trng_cond_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_1_u; + +/* Define the union csr_trng_cond_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_2_u; + +/* Define the union csr_trng_cond_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_3_u; + +/* Define the union csr_trng_cond_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_159_128 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_4_u; + +/* Define the union csr_trng_cond_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_191_160 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_5_u; + +/* Define the union csr_trng_cond_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_223_192 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_6_u; + +/* Define the union csr_trng_cond_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cf_output_255_224 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_cond_7_u; + +/* Define the union csr_trng_key_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_0_u; + +/* Define the union csr_trng_key_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_1_u; + +/* Define the union csr_trng_key_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_2_u; + +/* Define the union csr_trng_key_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_3_u; + +/* Define the union csr_trng_key_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_159_128 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_4_u; + +/* Define the union csr_trng_key_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_191_160 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_5_u; + +/* Define the union csr_trng_key_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_223_192 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_6_u; + +/* Define the union csr_trng_key_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 key_255_224 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_key_7_u; + +/* Define the union csr_trng_ps_ai_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_0_u; + +/* Define the union csr_trng_ps_ai_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_1_u; + +/* Define the union csr_trng_ps_ai_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_2_u; + +/* Define the union csr_trng_ps_ai_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_127_96 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_3_u; + +/* Define the union csr_trng_ps_ai_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_159_128 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_4_u; + +/* Define the union csr_trng_ps_ai_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_191_160 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_5_u; + +/* Define the union csr_trng_ps_ai_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_223_192 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_6_u; + +/* Define the union csr_trng_ps_ai_7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_255_224 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_7_u; + +/* Define the union csr_trng_ps_ai_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_287_256 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_8_u; + +/* Define the union csr_trng_ps_ai_9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_319_288 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_9_u; + +/* Define the union csr_trng_ps_ai_10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_351_320 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_10_u; + +/* Define the union csr_trng_ps_ai_11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vector_383_352 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ps_ai_11_u; + +/* Define the union csr_trng_run_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_test_count : 15; /* [14:0] */ + u32 run_state : 1; /* [15] */ + u32 run_length_count : 6; /* [21:16] */ + u32 rsv_12 : 2; /* [23:22] */ + u32 run_length_max : 6; /* [29:24] */ + u32 rsv_13 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_cnt_u; + +/* Define the union csr_trng_run_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_1_count_zeroes : 12; /* [11:0] */ + u32 rsv_14 : 4; /* [15:12] */ + u32 run_1_count_ones : 12; /* [27:16] */ + u32 rsv_15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_1_u; + +/* Define the union csr_trng_run_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_2_count_zeroes : 12; /* [11:0] */ + u32 rsv_16 : 4; /* [15:12] */ + u32 run_2_count_ones : 12; /* [27:16] */ + u32 rsv_17 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_2_u; + +/* Define the union csr_trng_run_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_3_count_zeroes : 10; /* [9:0] */ + u32 rsv_18 : 6; /* [15:10] */ + u32 run_3_count_ones : 10; /* [25:16] */ + u32 rsv_19 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_3_u; + +/* Define the union csr_trng_run_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_4_count_zeroes : 9; /* [8:0] */ + u32 rsv_20 : 7; /* [15:9] */ + u32 run_4_count_ones : 9; /* [24:16] */ + u32 rsv_21 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_4_u; + +/* Define the union csr_trng_run_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_5_count_zeroes : 8; /* [7:0] */ + u32 rsv_22 : 8; /* [15:8] */ + u32 run_5_count_ones : 8; /* [23:16] */ + u32 rsv_23 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_5_u; + +/* Define the union csr_trng_run_6_up_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 run_6_up_count_zeroes : 8; /* [7:0] */ + u32 rsv_24 : 8; /* [15:8] */ + u32 run_6_up_count_ones : 8; /* [23:16] */ + u32 rsv_25 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_run_6_up_u; + +/* Define the union csr_trng_monobitcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 monobit_count_l : 17; /* [16:0] */ + u32 monobit_count_h : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_monobitcnt_u; + +/* Define the union csr_trng_poker_3_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 poker_count_0 : 8; /* [7:0] */ + u32 poker_count_1 : 8; /* [15:8] */ + u32 poker_count_2 : 8; /* [23:16] */ + u32 poker_count_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_poker_3_0_u; + +/* Define the union csr_trng_poker_7_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 poker_count_4 : 8; /* [7:0] */ + u32 poker_count_5 : 8; /* [15:8] */ + u32 poker_count_6 : 8; /* [23:16] */ + u32 poker_count_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_poker_7_4_u; + +/* Define the union csr_trng_poker_b_8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 poker_count_8 : 8; /* [7:0] */ + u32 poker_count_9 : 8; /* [15:8] */ + u32 poker_count_a : 8; /* [23:16] */ + u32 poker_count_b : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_poker_b_8_u; + +/* Define the union csr_trng_poker_f_c_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 poker_count_c : 8; /* [7:0] */ + u32 poker_count_d : 8; /* [15:8] */ + u32 poker_count_e : 8; /* [23:16] */ + u32 poker_count_f : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_poker_f_c_u; + +/* Define the union csr_trng_test_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 test_en_out : 1; /* [0] */ + u32 test_patt_fro : 1; /* [1] */ + u32 test_patt_det : 1; /* [2] */ + u32 test_shiftreg : 1; /* [3] */ + u32 cont_poker : 1; /* [4] */ + u32 test_known_noise : 1; /* [5] */ + u32 test_aes_256 : 1; /* [6] */ + u32 test_sp_800_90 : 1; /* [7] */ + u32 test_select : 5; /* [12:8] */ + u32 test_noise : 1; /* [13] */ + u32 test_spb : 1; /* [14] */ + u32 test_cond_func : 1; /* [15] */ + u32 test_pattern : 12; /* [27:16] */ + u32 fro_testin2_not : 1; /* [28] */ + u32 fro_testin3 : 1; /* [29] */ + u32 fro_testin4 : 1; /* [30] */ + u32 test_irq : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_test_u; + +/* Define the union csr_trng_blockcnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_26 : 4; /* [3:0] */ + u32 block_count : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_blockcnt_u; + +/* Define the union csr_trng_options_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 post_processor_option : 3; /* [2:0] */ + u32 rsv_27 : 3; /* [5:3] */ + u32 nr_of_fros : 6; /* [11:6] */ + u32 buffer_size : 3; /* [14:12] */ + u32 rsv_28 : 1; /* [15] */ + u32 pr_test : 1; /* [16] */ + u32 conditioner_option : 2; /* [18:17] */ + u32 detuning_option : 2; /* [20:19] */ + u32 aprop_512 : 1; /* [21] */ + u32 rsv_29 : 1; /* [22] */ + u32 auto_detune : 1; /* [23] */ + u32 detune_counter : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_options_u; + +/* Define the union csr_trng_eip_rev_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 basic_eip_number : 8; /* [7:0] */ + u32 complement_of_basic_eip_number : 8; /* [15:8] */ + u32 hw_patch_level : 4; /* [19:16] */ + u32 minor_hw_revision : 4; /* [23:20] */ + u32 major_hw_revision : 4; /* [27:24] */ + u32 rsv_30 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_eip_rev_u; + +/* Define the union csr_trng_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_mode : 1; /* [0] */ + u32 sec_interface_disable : 1; /* [1] */ + u32 km_interface_disable : 1; /* [2] */ + u32 jtagauth_interface_disable : 1; /* [3] */ + u32 user_interface_disable : 1; /* [4] */ + u32 auto_reseed_enable : 1; /* [5] */ + u32 hpre_interface_disable : 1; /* [6] */ + u32 rsv_31 : 1; /* [7] */ + u32 mem_ctrl : 8; /* [15:8] */ + u32 block_cnt : 12; /* [27:16] */ + u32 rsv_32 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ctrl0_u; + +/* Define the union csr_trng_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 check_reseed_time_gap : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ctrl1_u; + +/* Define the union csr_trng_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_cpi_int_index : 24; /* [23:0] */ + u32 rsv_33 : 3; /* [26:24] */ + u32 trng_issue_enable : 1; /* [27] */ + u32 trng_int_issue : 1; /* [28] */ + u32 rsv_34 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_int_vector_u; + +/* Define the union csr_rng_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rng_en : 1; /* [0] */ + u32 rng_seed_sel : 1; /* [1] */ + u32 rng_ring_en : 1; /* [2] */ + u32 rsv_35 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rng_ctrl_u; + +/* Define the union csr_rng_seed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rng_seed : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rng_seed_u; + +/* Define the union csr_trng_fsm_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pproc_state : 7; /* [6:0] */ + u32 rsv_36 : 1; /* [7] */ + u32 fsm_state : 3; /* [10:8] */ + u32 rsv_37 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_fsm_st_u; + +/* Define the union csr_rng_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rng_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rng_num_u; + +/* Define the union csr_rng_phy_seed_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rng_phy_seed : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rng_phy_seed_u; + +/* Define the union csr_rng_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rng_reload_err : 1; /* [0] */ + u32 rsv_38 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rng_err_u; + +/* Define the union csr_trng_int_set_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_39 : 1; /* [0] */ + u32 shut_down_oflo_intset : 1; /* [1] */ + u32 stuck_out_intset : 1; /* [2] */ + u32 noise_fail_intset : 1; /* [3] */ + u32 run_fail_intset : 1; /* [4] */ + u32 long_run_fail_intset : 1; /* [5] */ + u32 poker_fail_intset : 1; /* [6] */ + u32 monobit_fail_intset : 1; /* [7] */ + u32 rsv_40 : 1; /* [8] */ + u32 stuck_nrbg_intset : 1; /* [9] */ + u32 rsv_41 : 3; /* [12:10] */ + u32 repcnt_fail_intset : 1; /* [13] */ + u32 aprop_fail_intset : 1; /* [14] */ + u32 rsv_42 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_int_set_u; + +/* Define the union csr_trng_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_int_en : 2; /* [1:0] */ + u32 rsv_43 : 14; /* [15:2] */ + u32 trng_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_int_en_u; + +/* Define the union csr_trng_int_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_int_data : 2; /* [1:0] */ + u32 rsv_44 : 14; /* [15:2] */ + u32 trng_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_int_st_u; + +/* Define the union csr_trng_ran_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_random_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ran_data0_u; + +/* Define the union csr_trng_ran_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_random_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ran_data1_u; + +/* Define the union csr_trng_ran_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_random_data2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ran_data2_u; + +/* Define the union csr_trng_ran_data3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 trng_random_data3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_trng_ran_data3_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_trng_output_0_u trng_output_0; /* 0 */ + volatile csr_trng_output_1_u trng_output_1; /* 4 */ + volatile csr_trng_output_2_u trng_output_2; /* 8 */ + volatile csr_trng_output_3_u trng_output_3; /* C */ + volatile csr_trng_input_0_u trng_input_0; /* 0 */ + volatile csr_trng_input_1_u trng_input_1; /* 4 */ + volatile csr_trng_input_2_u trng_input_2; /* 8 */ + volatile csr_trng_input_3_u trng_input_3; /* C */ + volatile csr_trng_status_u trng_status; /* 10 */ + volatile csr_trng_intack_u trng_intack; /* 10 */ + volatile csr_trng_control_u trng_control; /* 14 */ + volatile csr_trng_config_u trng_config; /* 18 */ + volatile csr_trng_alarmcnt_u trng_alarmcnt; /* 1C */ + volatile csr_trng_froenable_u trng_froenable; /* 20 */ + volatile csr_trng_frodetune_u trng_frodetune; /* 24 */ + volatile csr_trng_alarmmask_u trng_alarmmask; /* 28 */ + volatile csr_trng_alarmstop_u trng_alarmstop; /* 2C */ + volatile csr_trng_raw_l_u trng_raw_l; /* 30 */ + volatile csr_trng_raw_h_u trng_raw_h; /* 34 */ + volatile csr_trng_spb_tests_u trng_spb_tests; /* 38 */ + volatile csr_trng_count_u trng_count; /* 3C */ + volatile csr_trng_cond_0_u trng_cond_0; /* 40 */ + volatile csr_trng_cond_1_u trng_cond_1; /* 44 */ + volatile csr_trng_cond_2_u trng_cond_2; /* 48 */ + volatile csr_trng_cond_3_u trng_cond_3; /* 4C */ + volatile csr_trng_cond_4_u trng_cond_4; /* 50 */ + volatile csr_trng_cond_5_u trng_cond_5; /* 54 */ + volatile csr_trng_cond_6_u trng_cond_6; /* 58 */ + volatile csr_trng_cond_7_u trng_cond_7; /* 5C */ + volatile csr_trng_key_0_u trng_key_0; /* 40 */ + volatile csr_trng_key_1_u trng_key_1; /* 44 */ + volatile csr_trng_key_2_u trng_key_2; /* 48 */ + volatile csr_trng_key_3_u trng_key_3; /* 4C */ + volatile csr_trng_key_4_u trng_key_4; /* 50 */ + volatile csr_trng_key_5_u trng_key_5; /* 54 */ + volatile csr_trng_key_6_u trng_key_6; /* 58 */ + volatile csr_trng_key_7_u trng_key_7; /* 5C */ + volatile csr_trng_ps_ai_0_u trng_ps_ai_0; /* 40 */ + volatile csr_trng_ps_ai_1_u trng_ps_ai_1; /* 44 */ + volatile csr_trng_ps_ai_2_u trng_ps_ai_2; /* 48 */ + volatile csr_trng_ps_ai_3_u trng_ps_ai_3; /* 4C */ + volatile csr_trng_ps_ai_4_u trng_ps_ai_4; /* 50 */ + volatile csr_trng_ps_ai_5_u trng_ps_ai_5; /* 54 */ + volatile csr_trng_ps_ai_6_u trng_ps_ai_6; /* 58 */ + volatile csr_trng_ps_ai_7_u trng_ps_ai_7; /* 5C */ + volatile csr_trng_ps_ai_8_u trng_ps_ai_8; /* 60 */ + volatile csr_trng_ps_ai_9_u trng_ps_ai_9; /* 64 */ + volatile csr_trng_ps_ai_10_u trng_ps_ai_10; /* 68 */ + volatile csr_trng_ps_ai_11_u trng_ps_ai_11; /* 6C */ + volatile csr_trng_run_cnt_u trng_run_cnt; /* 40 */ + volatile csr_trng_run_1_u trng_run_1; /* 44 */ + volatile csr_trng_run_2_u trng_run_2; /* 48 */ + volatile csr_trng_run_3_u trng_run_3; /* 4C */ + volatile csr_trng_run_4_u trng_run_4; /* 50 */ + volatile csr_trng_run_5_u trng_run_5; /* 54 */ + volatile csr_trng_run_6_up_u trng_run_6_up; /* 58 */ + volatile csr_trng_monobitcnt_u trng_monobitcnt; /* 5C */ + volatile csr_trng_poker_3_0_u trng_poker_3_0; /* 60 */ + volatile csr_trng_poker_7_4_u trng_poker_7_4; /* 64 */ + volatile csr_trng_poker_b_8_u trng_poker_b_8; /* 68 */ + volatile csr_trng_poker_f_c_u trng_poker_f_c; /* 6C */ + volatile csr_trng_test_u trng_test; /* 70 */ + volatile csr_trng_blockcnt_u trng_blockcnt; /* 74 */ + volatile csr_trng_options_u trng_options; /* 78 */ + volatile csr_trng_eip_rev_u trng_eip_rev; /* 7C */ + volatile csr_trng_ctrl0_u trng_ctrl0; /* C0 */ + volatile csr_trng_ctrl1_u trng_ctrl1; /* C4 */ + volatile csr_trng_int_vector_u trng_int_vector; /* C8 */ + volatile csr_rng_ctrl_u rng_ctrl; /* CC */ + volatile csr_rng_seed_u rng_seed; /* D0 */ + volatile csr_trng_fsm_st_u trng_fsm_st; /* D4 */ + volatile csr_rng_num_u rng_num; /* D8 */ + volatile csr_rng_phy_seed_u rng_phy_seed; /* DC */ + volatile csr_rng_err_u rng_err; /* E0 */ + volatile csr_trng_int_set_u trng_int_set; /* E4 */ + volatile csr_trng_int_en_u trng_int_en; /* E8 */ + volatile csr_trng_int_st_u trng_int_st; /* EC */ + volatile csr_trng_ran_data0_u trng_ran_data0; /* F0 */ + volatile csr_trng_ran_data1_u trng_ran_data1; /* F4 */ + volatile csr_trng_ran_data2_u trng_ran_data2; /* F8 */ + volatile csr_trng_ran_data3_u trng_ran_data3; /* FC */ +} S_trng_csr_REGS_TYPE; + +/* Declare the struct pointor of the module trng_csr */ +extern volatile S_trng_csr_REGS_TYPE *goptrng_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetTRNG_OUTPUT_0_trng_output_31_0(unsigned int utrng_output_31_0); +int iSetTRNG_OUTPUT_1_trng_output_63_32(unsigned int utrng_output_63_32); +int iSetTRNG_OUTPUT_2_trng_output_95_64(unsigned int utrng_output_95_64); +int iSetTRNG_OUTPUT_3_trng_output_127_96(unsigned int utrng_output_127_96); +int iSetTRNG_INPUT_0_trng_input_31_0(unsigned int utrng_input_31_0); +int iSetTRNG_INPUT_1_trng_input_63_32(unsigned int utrng_input_63_32); +int iSetTRNG_INPUT_2_trng_input_95_64(unsigned int utrng_input_95_64); +int iSetTRNG_INPUT_3_trng_input_127_96(unsigned int utrng_input_127_96); +int iSetTRNG_STATUS_ready(unsigned int uready); +int iSetTRNG_STATUS_shutdown_oflo(unsigned int ushutdown_oflo); +int iSetTRNG_STATUS_stuck_out(unsigned int ustuck_out); +int iSetTRNG_STATUS_noise_fail(unsigned int unoise_fail); +int iSetTRNG_STATUS_run_fail(unsigned int urun_fail); +int iSetTRNG_STATUS_long_run_fail(unsigned int ulong_run_fail); +int iSetTRNG_STATUS_poker_fail(unsigned int upoker_fail); +int iSetTRNG_STATUS_monobit_fail(unsigned int umonobit_fail); +int iSetTRNG_STATUS_test_ready(unsigned int utest_ready); +int iSetTRNG_STATUS_stuck_nrbg(unsigned int ustuck_nrbg); +int iSetTRNG_STATUS_reseed_ai(unsigned int ureseed_ai); +int iSetTRNG_STATUS_repcnt_fail(unsigned int urepcnt_fail); +int iSetTRNG_STATUS_aprop_fail(unsigned int uaprop_fail); +int iSetTRNG_STATUS_test_stuck_out(unsigned int utest_stuck_out); +int iSetTRNG_STATUS_blocks_available(unsigned int ublocks_available); +int iSetTRNG_STATUS_blocks_thresh(unsigned int ublocks_thresh); +int iSetTRNG_STATUS_need_clock(unsigned int uneed_clock); +int iSetTRNG_INTACK_ready_ack(unsigned int uready_ack); +int iSetTRNG_INTACK_shutdown_oflo_ack(unsigned int ushutdown_oflo_ack); +int iSetTRNG_INTACK_stuck_out_ack(unsigned int ustuck_out_ack); +int iSetTRNG_INTACK_noise_fail_ack(unsigned int unoise_fail_ack); +int iSetTRNG_INTACK_run_fail_ack(unsigned int urun_fail_ack); +int iSetTRNG_INTACK_long_run_fail_ack(unsigned int ulong_run_fail_ack); +int iSetTRNG_INTACK_poker_fail_ack(unsigned int upoker_fail_ack); +int iSetTRNG_INTACK_monobit_fail_ack(unsigned int umonobit_fail_ack); +int iSetTRNG_INTACK_test_ready_ack(unsigned int utest_ready_ack); +int iSetTRNG_INTACK_stuck_nrbg_ack(unsigned int ustuck_nrbg_ack); +int iSetTRNG_INTACK_open_read_gate(unsigned int uopen_read_gate); +int iSetTRNG_INTACK_repcnt_fail_ack(unsigned int urepcnt_fail_ack); +int iSetTRNG_INTACK_aprop_fail_ack(unsigned int uaprop_fail_ack); +int iSetTRNG_INTACK_test_stuck_out(unsigned int utest_stuck_out); +int iSetTRNG_CONTROL_ready_mask(unsigned int uready_mask); +int iSetTRNG_CONTROL_shutdown_oflo_mask(unsigned int ushutdown_oflo_mask); +int iSetTRNG_CONTROL_stuck_out_mask(unsigned int ustuck_out_mask); +int iSetTRNG_CONTROL_noise_fail_mask(unsigned int unoise_fail_mask); +int iSetTRNG_CONTROL_run_fail_mask(unsigned int urun_fail_mask); +int iSetTRNG_CONTROL_long_run_fail_mask(unsigned int ulong_run_fail_mask); +int iSetTRNG_CONTROL_poker_fail_mask(unsigned int upoker_fail_mask); +int iSetTRNG_CONTROL_monobit_fail_mask(unsigned int umonobit_fail_mask); +int iSetTRNG_CONTROL_test_mode(unsigned int utest_mode); +int iSetTRNG_CONTROL_stuck_nrbg_mask(unsigned int ustuck_nrbg_mask); +int iSetTRNG_CONTROL_enable_trng(unsigned int uenable_trng); +int iSetTRNG_CONTROL_no_whitening(unsigned int uno_whitening); +int iSetTRNG_CONTROL_drbg_en(unsigned int udrbg_en); +int iSetTRNG_CONTROL_repcnt_fail_mask(unsigned int urepcnt_fail_mask); +int iSetTRNG_CONTROL_aprop_fail_mask(unsigned int uaprop_fail_mask); +int iSetTRNG_CONTROL_re_seed(unsigned int ure_seed); +int iSetTRNG_CONTROL_request_data(unsigned int urequest_data); +int iSetTRNG_CONTROL_request_hold(unsigned int urequest_hold); +int iSetTRNG_CONTROL_data_blocks(unsigned int udata_blocks); +int iSetTRNG_CONFIG_noise_blocks(unsigned int unoise_blocks); +int iSetTRNG_CONFIG_use_startup_bits(unsigned int uuse_startup_bits); +int iSetTRNG_CONFIG_scale(unsigned int uscale); +int iSetTRNG_CONFIG_sample_div(unsigned int usample_div); +int iSetTRNG_CONFIG_read_timeout(unsigned int uread_timeout); +int iSetTRNG_CONFIG_sample_cycles(unsigned int usample_cycles); +int iSetTRNG_ALARMCNT_alarm_threshold(unsigned int ualarm_threshold); +int iSetTRNG_ALARMCNT_stall_run_poker(unsigned int ustall_run_poker); +int iSetTRNG_ALARMCNT_shutdown_threshold(unsigned int ushutdown_threshold); +int iSetTRNG_ALARMCNT_shutdown_fatal(unsigned int ushutdown_fatal); +int iSetTRNG_ALARMCNT_shutdown_count(unsigned int ushutdown_count); +int iSetTRNG_FROENABLE_fro_enables(unsigned int ufro_enables); +int iSetTRNG_FRODETUNE_fro_detunes(unsigned int ufro_detunes); +int iSetTRNG_ALARMMASK_fro_alarmmasks(unsigned int ufro_alarmmasks); +int iSetTRNG_ALARMSTOP_fro_alarmstops(unsigned int ufro_alarmstops); +int iSetTRNG_RAW_L_shift_reg_31_0(unsigned int ushift_reg_31_0); +int iSetTRNG_RAW_H_shift_reg_63_32(unsigned int ushift_reg_63_32); +int iSetTRNG_SPB_TESTS_repcnt(unsigned int urepcnt); +int iSetTRNG_SPB_TESTS_repcnt_value_h(unsigned int urepcnt_value_h); +int iSetTRNG_SPB_TESTS_aprop_64(unsigned int uaprop_64); +int iSetTRNG_SPB_TESTS_aprop_64_value_h(unsigned int uaprop_64_value_h); +int iSetTRNG_SPB_TESTS_aprop_512(unsigned int uaprop_512); +int iSetTRNG_SPB_TESTS_aprop_512_h(unsigned int uaprop_512_h); +int iSetTRNG_SPB_TESTS_show_counters(unsigned int ushow_counters); +int iSetTRNG_SPB_TESTS_show_values(unsigned int ushow_values); +int iSetTRNG_SPB_TESTS_aprop_64_fail(unsigned int uaprop_64_fail); +int iSetTRNG_SPB_TESTS_aprop_512_fail(unsigned int uaprop_512_fail); +int iSetTRNG_COUNT_sample_cyc_cnt(unsigned int usample_cyc_cnt); +int iSetTRNG_COUNT_noise_blk_cnt(unsigned int unoise_blk_cnt); +int iSetTRNG_COUNT_sample_cyc_ext(unsigned int usample_cyc_ext); +int iSetTRNG_COND_0_cf_output_31_0(unsigned int ucf_output_31_0); +int iSetTRNG_COND_1_cf_output_63_32(unsigned int ucf_output_63_32); +int iSetTRNG_COND_2_cf_output_95_64(unsigned int ucf_output_95_64); +int iSetTRNG_COND_3_cf_output_127_96(unsigned int ucf_output_127_96); +int iSetTRNG_COND_4_cf_output_159_128(unsigned int ucf_output_159_128); +int iSetTRNG_COND_5_cf_output_191_160(unsigned int ucf_output_191_160); +int iSetTRNG_COND_6_cf_output_223_192(unsigned int ucf_output_223_192); +int iSetTRNG_COND_7_cf_output_255_224(unsigned int ucf_output_255_224); +int iSetTRNG_KEY_0_key_31_0(unsigned int ukey_31_0); +int iSetTRNG_KEY_1_key_63_32(unsigned int ukey_63_32); +int iSetTRNG_KEY_2_key_95_64(unsigned int ukey_95_64); +int iSetTRNG_KEY_3_key_127_96(unsigned int ukey_127_96); +int iSetTRNG_KEY_4_key_159_128(unsigned int ukey_159_128); +int iSetTRNG_KEY_5_key_191_160(unsigned int ukey_191_160); +int iSetTRNG_KEY_6_key_223_192(unsigned int ukey_223_192); +int iSetTRNG_KEY_7_key_255_224(unsigned int ukey_255_224); +int iSetTRNG_PS_AI_0_vector_31_0(unsigned int uvector_31_0); +int iSetTRNG_PS_AI_1_vector_63_32(unsigned int uvector_63_32); +int iSetTRNG_PS_AI_2_vector_95_64(unsigned int uvector_95_64); +int iSetTRNG_PS_AI_3_vector_127_96(unsigned int uvector_127_96); +int iSetTRNG_PS_AI_4_vector_159_128(unsigned int uvector_159_128); +int iSetTRNG_PS_AI_5_vector_191_160(unsigned int uvector_191_160); +int iSetTRNG_PS_AI_6_vector_223_192(unsigned int uvector_223_192); +int iSetTRNG_PS_AI_7_vector_255_224(unsigned int uvector_255_224); +int iSetTRNG_PS_AI_8_vector_287_256(unsigned int uvector_287_256); +int iSetTRNG_PS_AI_9_vector_319_288(unsigned int uvector_319_288); +int iSetTRNG_PS_AI_10_vector_351_320(unsigned int uvector_351_320); +int iSetTRNG_PS_AI_11_vector_383_352(unsigned int uvector_383_352); +int iSetTRNG_RUN_CNT_run_test_count(unsigned int urun_test_count); +int iSetTRNG_RUN_CNT_run_state(unsigned int urun_state); +int iSetTRNG_RUN_CNT_run_length_count(unsigned int urun_length_count); +int iSetTRNG_RUN_CNT_run_length_max(unsigned int urun_length_max); +int iSetTRNG_RUN_1_run_1_count_zeroes(unsigned int urun_1_count_zeroes); +int iSetTRNG_RUN_1_run_1_count_ones(unsigned int urun_1_count_ones); +int iSetTRNG_RUN_2_run_2_count_zeroes(unsigned int urun_2_count_zeroes); +int iSetTRNG_RUN_2_run_2_count_ones(unsigned int urun_2_count_ones); +int iSetTRNG_RUN_3_run_3_count_zeroes(unsigned int urun_3_count_zeroes); +int iSetTRNG_RUN_3_run_3_count_ones(unsigned int urun_3_count_ones); +int iSetTRNG_RUN_4_run_4_count_zeroes(unsigned int urun_4_count_zeroes); +int iSetTRNG_RUN_4_run_4_count_ones(unsigned int urun_4_count_ones); +int iSetTRNG_RUN_5_run_5_count_zeroes(unsigned int urun_5_count_zeroes); +int iSetTRNG_RUN_5_run_5_count_ones(unsigned int urun_5_count_ones); +int iSetTRNG_RUN_6_UP_run_6_up_count_zeroes(unsigned int urun_6_up_count_zeroes); +int iSetTRNG_RUN_6_UP_run_6_up_count_ones(unsigned int urun_6_up_count_ones); +int iSetTRNG_MONOBITCNT_monobit_count_l(unsigned int umonobit_count_l); +int iSetTRNG_MONOBITCNT_monobit_count_h(unsigned int umonobit_count_h); +int iSetTRNG_POKER_3_0_poker_count_0(unsigned int upoker_count_0); +int iSetTRNG_POKER_3_0_poker_count_1(unsigned int upoker_count_1); +int iSetTRNG_POKER_3_0_poker_count_2(unsigned int upoker_count_2); +int iSetTRNG_POKER_3_0_poker_count_3(unsigned int upoker_count_3); +int iSetTRNG_POKER_7_4_poker_count_4(unsigned int upoker_count_4); +int iSetTRNG_POKER_7_4_poker_count_5(unsigned int upoker_count_5); +int iSetTRNG_POKER_7_4_poker_count_6(unsigned int upoker_count_6); +int iSetTRNG_POKER_7_4_poker_count_7(unsigned int upoker_count_7); +int iSetTRNG_POKER_B_8_poker_count_8(unsigned int upoker_count_8); +int iSetTRNG_POKER_B_8_poker_count_9(unsigned int upoker_count_9); +int iSetTRNG_POKER_B_8_poker_count_a(unsigned int upoker_count_a); +int iSetTRNG_POKER_B_8_poker_count_b(unsigned int upoker_count_b); +int iSetTRNG_POKER_F_C_poker_count_c(unsigned int upoker_count_c); +int iSetTRNG_POKER_F_C_poker_count_d(unsigned int upoker_count_d); +int iSetTRNG_POKER_F_C_poker_count_e(unsigned int upoker_count_e); +int iSetTRNG_POKER_F_C_poker_count_f(unsigned int upoker_count_f); +int iSetTRNG_TEST_test_en_out(unsigned int utest_en_out); +int iSetTRNG_TEST_test_patt_fro(unsigned int utest_patt_fro); +int iSetTRNG_TEST_test_patt_det(unsigned int utest_patt_det); +int iSetTRNG_TEST_test_shiftreg(unsigned int utest_shiftreg); +int iSetTRNG_TEST_cont_poker(unsigned int ucont_poker); +int iSetTRNG_TEST_test_known_noise(unsigned int utest_known_noise); +int iSetTRNG_TEST_test_aes_256(unsigned int utest_aes_256); +int iSetTRNG_TEST_test_sp_800_90(unsigned int utest_sp_800_90); +int iSetTRNG_TEST_test_select(unsigned int utest_select); +int iSetTRNG_TEST_test_noise(unsigned int utest_noise); +int iSetTRNG_TEST_test_spb(unsigned int utest_spb); +int iSetTRNG_TEST_test_cond_func(unsigned int utest_cond_func); +int iSetTRNG_TEST_test_pattern(unsigned int utest_pattern); +int iSetTRNG_TEST_fro_testin2_not(unsigned int ufro_testin2_not); +int iSetTRNG_TEST_fro_testin3(unsigned int ufro_testin3); +int iSetTRNG_TEST_fro_testin4(unsigned int ufro_testin4); +int iSetTRNG_TEST_test_irq(unsigned int utest_irq); +int iSetTRNG_BLOCKCNT_block_count(unsigned int ublock_count); +int iSetTRNG_OPTIONS_post_processor_option(unsigned int upost_processor_option); +int iSetTRNG_OPTIONS_nr_of_fros(unsigned int unr_of_fros); +int iSetTRNG_OPTIONS_buffer_size(unsigned int ubuffer_size); +int iSetTRNG_OPTIONS_pr_test(unsigned int upr_test); +int iSetTRNG_OPTIONS_conditioner_option(unsigned int uconditioner_option); +int iSetTRNG_OPTIONS_detuning_option(unsigned int udetuning_option); +int iSetTRNG_OPTIONS_aprop_512(unsigned int uaprop_512); +int iSetTRNG_OPTIONS_auto_detune(unsigned int uauto_detune); +int iSetTRNG_OPTIONS_detune_counter(unsigned int udetune_counter); +int iSetTRNG_EIP_REV_basic_eip_number(unsigned int ubasic_eip_number); +int iSetTRNG_EIP_REV_complement_of_basic_eip_number(unsigned int ucomplement_of_basic_eip_number); +int iSetTRNG_EIP_REV_hw_patch_level(unsigned int uhw_patch_level); +int iSetTRNG_EIP_REV_minor_hw_revision(unsigned int uminor_hw_revision); +int iSetTRNG_EIP_REV_major_hw_revision(unsigned int umajor_hw_revision); +int iSetTRNG_CTRL0_trng_mode(unsigned int utrng_mode); +int iSetTRNG_CTRL0_sec_interface_disable(unsigned int usec_interface_disable); +int iSetTRNG_CTRL0_km_interface_disable(unsigned int ukm_interface_disable); +int iSetTRNG_CTRL0_jtagauth_interface_disable(unsigned int ujtagauth_interface_disable); +int iSetTRNG_CTRL0_user_interface_disable(unsigned int uuser_interface_disable); +int iSetTRNG_CTRL0_auto_reseed_enable(unsigned int uauto_reseed_enable); +int iSetTRNG_CTRL0_hpre_interface_disable(unsigned int uhpre_interface_disable); +int iSetTRNG_CTRL0_mem_ctrl(unsigned int umem_ctrl); +int iSetTRNG_CTRL0_block_cnt(unsigned int ublock_cnt); +int iSetTRNG_CTRL1_check_reseed_time_gap(unsigned int ucheck_reseed_time_gap); +int iSetTRNG_INT_VECTOR_trng_cpi_int_index(unsigned int utrng_cpi_int_index); +int iSetTRNG_INT_VECTOR_trng_issue_enable(unsigned int utrng_issue_enable); +int iSetTRNG_INT_VECTOR_trng_int_issue(unsigned int utrng_int_issue); +int iSetRNG_CTRL_rng_en(unsigned int urng_en); +int iSetRNG_CTRL_rng_seed_sel(unsigned int urng_seed_sel); +int iSetRNG_CTRL_rng_ring_en(unsigned int urng_ring_en); +int iSetRNG_SEED_rng_seed(unsigned int urng_seed); +int iSetTRNG_FSM_ST_pproc_state(unsigned int upproc_state); +int iSetTRNG_FSM_ST_fsm_state(unsigned int ufsm_state); +int iSetRNG_NUM_rng_num(unsigned int urng_num); +int iSetRNG_PHY_SEED_rng_phy_seed(unsigned int urng_phy_seed); +int iSetRNG_ERR_rng_reload_err(unsigned int urng_reload_err); +int iSetTRNG_INT_SET_shut_down_oflo_intset(unsigned int ushut_down_oflo_intset); +int iSetTRNG_INT_SET_stuck_out_intset(unsigned int ustuck_out_intset); +int iSetTRNG_INT_SET_noise_fail_intset(unsigned int unoise_fail_intset); +int iSetTRNG_INT_SET_run_fail_intset(unsigned int urun_fail_intset); +int iSetTRNG_INT_SET_long_run_fail_intset(unsigned int ulong_run_fail_intset); +int iSetTRNG_INT_SET_poker_fail_intset(unsigned int upoker_fail_intset); +int iSetTRNG_INT_SET_monobit_fail_intset(unsigned int umonobit_fail_intset); +int iSetTRNG_INT_SET_stuck_nrbg_intset(unsigned int ustuck_nrbg_intset); +int iSetTRNG_INT_SET_repcnt_fail_intset(unsigned int urepcnt_fail_intset); +int iSetTRNG_INT_SET_aprop_fail_intset(unsigned int uaprop_fail_intset); +int iSetTRNG_INT_EN_trng_int_en(unsigned int utrng_int_en); +int iSetTRNG_INT_EN_trng_program_csr_id(unsigned int utrng_program_csr_id); +int iSetTRNG_INT_ST_trng_int_data(unsigned int utrng_int_data); +int iSetTRNG_INT_ST_trng_program_csr_id_ro(unsigned int utrng_program_csr_id_ro); +int iSetTRNG_RAN_DATA0_trng_random_data0(unsigned int utrng_random_data0); +int iSetTRNG_RAN_DATA1_trng_random_data1(unsigned int utrng_random_data1); +int iSetTRNG_RAN_DATA2_trng_random_data2(unsigned int utrng_random_data2); +int iSetTRNG_RAN_DATA3_trng_random_data3(unsigned int utrng_random_data3); + + +#endif // XXX_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_reg_offset.h new file mode 100644 index 000000000..2050cdd14 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/crypto_reg_offset.h @@ -0,0 +1,1181 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : crypto_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/5/26 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/05/26 16:19:41 Create file +// ****************************************************************************** + +#ifndef CRYPTO_REG_OFFSET_H +#define CRYPTO_REG_OFFSET_H + +/* CRYPTORX_INOUT_CSR Base address of Module's Register */ +#define CSR_CRYPTORX_INOUT_CSR_BASE (0x2000) + +/* **************************************************************************** */ +/* CRYPTORX_INOUT_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_VERSION_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x0) /* 版本寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_INT_VECTOR_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x60) /* 中断向量 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_INT_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x64) /* 中断状态 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_INT_EN_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x68) /* 中断屏蔽 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_LP_TOP_ERR_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x6C) /* CRX环回顶层错误中断寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_LP_GCM_ERR_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x70) /* CRX环回GCM通道错误中断寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_LP_CBC_ERR_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x74) /* CRX环回CBC通道错误中断寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_XTS_ERR_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x78) /* CRX XTS通道错误中断寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_TMOUT_CFG_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x80) /* CRX通道超时阈值 */ +#define CSR_CRYPTORX_INOUT_CSR_IPSEC_RX_CRG_CFG_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x84) /* IPSEC_RX时钟复位配置寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_MEM_INIT_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x100) /* CRYPTORX MEM初始化使能寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_MEM_INIT_DONE_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x104) /* CRYPTORX MEM初始化状态寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_MEM_CTRL_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x108) /* CRYPTORX MEM配置寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_REG_CNT_CLR_CE_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x10C) /* CRYPTORX 中CNT_CYC读清控制信号配置寄存器。 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CHX_CFG_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x120) /* CRX通道SAA配置寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CREDIT_O_CFG_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x128) /* CRX出口CREDIT配置寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CREDIT2_O_CFG_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x12C) /* CRX出口CREDIT2配置寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CTRL_RSV_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x130) /* 控制保留寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_STAT_RSV_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x134) /* 状态保留寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_EPT_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x138) /* CRYPTORX顶层空状态寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_FULL_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x13C) /* CRYPTOTX顶层满状态寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_DFT_MEM_CTRL_0_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x150) /* CRYPTORX DFT_MEM_CTRL寄存器0 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_DFT_MEM_CTRL_1_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x154) /* CRYPTORX DFT_MEM_CTRL寄存器1 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_DFT_MEM_CTRL_2_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x158) /* CRYPTORX DFT_MEM_CTRL寄存器2 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_DFT_MEM_CTRL_3_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x15C) /* CRYPTORX DFT_MEM_CTRL寄存器3 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_DFT_MEM_CTRL_4_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x160) /* CRYPTORX DFT_MEM_CTRL寄存器4 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_ERR1_CNT_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x170) /* CRYPTORX顶层ECC1比特错误计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_ECC_ERR2_ADDR_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x174) /* CRYPTORX顶层ECC2比特错误地址寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_TOP_INT_EN_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x178) /* CRYPTORX顶层中断使能寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_TOP_ALM_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x17C) /* CRYPTORX顶层告警寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CREDIT_ERR_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x200) /* CRYPTO入口CREDIT ERR寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_INN_CREDIT_I_ERR_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x204) /* CRYPTO入口INN CREDIT ERR寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_PRE_0_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x310) /* 入口SOF流量统计寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_PRE_1_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x314) /* 入口SOF流量统计寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_PRE_2_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x318) /* 入口SOF流量统计寄存器 \ + */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_CHK_ERR_CNT_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x320) /* 校验错误统计计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_TFC_PAD_ERR_CNT_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x324) /* TFC_PAD删除失败统计计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_OTHER_ERR_CNT_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x328) /* CRX其余错误统计计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_0_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x210) /* 入口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_1_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x214) /* 入口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_I_2_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x218) /* 入口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_O_0_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x220) /* 出口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_O_1_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x224) /* 出口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CNT_O_2_REG (CSR_CRYPTORX_INOUT_CSR_BASE + 0x228) /* 出口流量统计寄存器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_IF_I_CNT_0_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x280) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_IF_I_CNT_1_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x284) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRYPTORX_IF_I_CNT_2_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x288) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_I_0_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2A0) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_I_1_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2A4) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_I_2_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2A8) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_O_0_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2C0) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_O_1_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2C4) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_BDSPLIT_LEN_O_2_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2C8) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CMB_LEN_O_0_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2E0) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CMB_LEN_O_1_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2E4) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTORX_INOUT_CSR_CRX_PKT_CMB_LEN_O_2_REG \ + (CSR_CRYPTORX_INOUT_CSR_BASE + 0x2E8) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ + +/* CRYPTOTX_INOUT_CSR Base address of Module's Register */ +#define CSR_CRYPTOTX_INOUT_CSR_BASE (0x4000) + +/* **************************************************************************** */ +/* CRYPTOTX_INOUT_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRYPTOTX_INOUT_CSR_CTX_VERSION_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x0) /* 版本寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_INT_VECTOR_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x60) /* 中断向量 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_INT_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x64) /* 中断状态 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_INT_EN_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x68) /* 中断屏蔽 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_TOP_ERR_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x6C) /* CTX环回顶层错误中断寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_GCM_ERR_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x70) /* CTX环回GCM通道错误中断寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_CBC_ERR_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x74) /* CTX环回CBC通道错误中断寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_XTS_EC_ERR_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x78) /* CTX直通XTS_EC通道错误中断寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_XTS_ERR_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x7C) /* CTX直通XTS通道错误中断寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_TMOUT_CFG_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x80) /* CTX通道超时阈值 */ +#define CSR_CRYPTOTX_INOUT_CSR_IPSEC_TX_CRG_CFG_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x84) /* IPSEC_TX时钟复位配置寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_MEM_INIT_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x100) /* CRYPTOTX MEM初始化使能寄存器 \ + */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_MEM_INIT_DONE_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x104) /* CRYPTOTX MEM初始化状态寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_MEM_CTRL_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x108) /* CRYPTOTX MEM配置寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_REG_CNT_CLR_CE_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x10C) /* CRYPTOTX 中CNT_CYC读清控制信号配置寄存器。 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_CHX_CFG_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x120) /* 环回通道SAA配置寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_CHX_CFG_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x124) /* 直通通道SAA映射寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_NECCH_CREDIT_O_CFG_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x128) /* 非EC通道出口CREDIT配置寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_ECCH_CREDIT_O_CFG_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x12C) /* EC通道出口CREDIT配置寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_CTRL_RSV_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x130) /* 控制保留寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_STAT_RSV_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x134) /* 状态保留寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_EPT_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x140) /* CRYPTOTX环回通道顶层空状态寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_FULL_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x144) /* CRYPTOTX环回通道顶层满状态寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_EPT_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x148) /* CRYPTOTX直通通道顶层空状态寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_FULL_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x14C) /* CRYPTOTX直通通道顶层满状态寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_DFT_MEM_CTRL_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x150) /* CRYPTOTX DFT_MEM_CTRL寄存器0 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_DFT_MEM_CTRL_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x154) /* CRYPTOTX DFT_MEM_CTRL寄存器1 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_DFT_MEM_CTRL_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x158) /* CRYPTOTX DFT_MEM_CTRL寄存器2 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_DFT_MEM_CTRL_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x15C) /* CRYPTOTX DFT_MEM_CTRL寄存器3 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_DFT_MEM_CTRL_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x160) /* CRYPTOTX DFT_MEM_CTRL寄存器4 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_TOP_INT_EN_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x178) /* CRYPTOTX顶层中断使能寄存器 \ + */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_TOP_ALM_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x17C) /* CRYPTOTX顶层告警寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_CREDIT_ERR_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x200) /* CRYPTO入口CREDIT ERR寄存器 \ + */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_INN_CREDIT_I_ERR_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x204) /* CRYPTO入口INN CREDIT ERR寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_PRE_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x310) /* 环回通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_PRE_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x314) /* 环回通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_PRE_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x318) /* 环回通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_PRE_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x320) /* 直通通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_PRE_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x324) /* 直通通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_PRE_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x328) /* 直通通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_PRE_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x32C) /* 直通通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_PRE_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x330) /* 直通通道SOF入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BD_ERR_CNT_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x340) /* BD错误统计计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LEN_ERR_CNT_REG (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x344) /* 报文长度错误统计计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x210) /* 环回通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x214) /* 环回通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_I_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x218) /* 环回通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x220) /* 直通通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x224) /* 直通通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x228) /* 直通通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x22C) /* 直通通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_I_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x230) /* 直通通道入口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_O_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x240) /* 环回通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_O_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x244) /* 环回通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_LP_PKT_CNT_O_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x248) /* 环回通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_O_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x260) /* 直通通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_O_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x264) /* 直通通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_O_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x268) /* 直通通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_O_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x26C) /* 直通通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_EC_PKT_CNT_O_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x270) /* 直通通道出口流量统计寄存器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CRYPTOTX_IF_I_CNT_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x280) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CRYPTOTX_IF_I_CNT_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x284) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CRYPTOTX_IF_I_CNT_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x288) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CRYPTOTX_IF_I_CNT_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x28C) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CRYPTOTX_IF_I_CNT_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x290) /* 任务通道内部CREDIT尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_I_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2A0) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_I_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2A4) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_I_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2A8) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_I_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2AC) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_I_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2B0) /* 任务通道内部BDSPLIT_LEN_I尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_O_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2C0) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_O_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2C4) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_O_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2C8) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_O_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2CC) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_BDSPLIT_LEN_O_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2D0) /* 任务通道内部BDSPLIT_LEN_O尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_PKT_CMB_LEN_O_0_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2E0) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_PKT_CMB_LEN_O_1_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2E4) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_PKT_CMB_LEN_O_2_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2E8) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_PKT_CMB_LEN_O_3_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2EC) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ +#define CSR_CRYPTOTX_INOUT_CSR_CTX_PKT_CMB_LEN_O_4_REG \ + (CSR_CRYPTOTX_INOUT_CSR_BASE + 0x2F0) /* 任务通道内部PKT_CMB_LEN尾数计数器 */ + +/* CRX_IPSEC_GCM_CSR Base address of Module's Register */ +#define CSR_CRX_IPSEC_GCM_CSR_BASE (0x3000) + +/* **************************************************************************** */ +/* CRX_IPSEC_GCM_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_16K_TH_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x0) /* GCM通道出口整包缓存FIFO将满阈值 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_CTRL_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x4) /* GCM通道控制寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_CORE_RSV_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x8) /* GCM_CORE保留寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_CLUSTER_RSV_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x10) /* GCM通道ECO寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_PROBE_I_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x20) /* GCM内部MEMPROBE输入信号 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_PROBE_RDATA_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x24) /* GCM内部MEM PROBE输出信号 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_CTRL_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x28) /* GCM通道FIFO PROBE控制寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_STAT_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x2C) /* GCM通道FIFO PROBE状态寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_0_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x30) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_1_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x34) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_2_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x38) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_3_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x3C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_4_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x40) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_5_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x44) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_6_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x48) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_7_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x4C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xA0) /* GCM通道BD_ERR历史状态寄存器 \ + */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_CLR_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xA4) /* GCM通道BD_ERR历史状态清除寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_L_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xA8) /* GCM通道BD_ERR掩码低位寄存器 \ + */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_H_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xAC) /* GCM通道BD_ERR掩码高位寄存器 \ + */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_ECC_ERR1_CNT_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xB0) /* GCM通道ECC1比特错误计数器 */ +#define CSR_CRX_IPSEC_GCM_CSR_GCM_ECC_ERR2_ADDR_REG \ + (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xB4) /* GCM通道ECC2比特错误地址寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_INT_EN_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0xFC) /* GCM通道中断使能寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_ALM_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x100) /* GCM通道告警寄存器 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA1_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x104) /* GCM通道状态寄存器1 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA2_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x108) /* GCM通道状态寄存器2 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA3_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x10C) /* GCM通道状态寄存器3 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA4_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x110) /* GCM通道状态寄存器4 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA5_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x114) /* GCM通道状态寄存器5 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA6_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x118) /* GCM通道状态寄存器6 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA7_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x11C) /* GCM通道状态寄存器7 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA8_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x120) /* GCM通道状态寄存器8 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA9_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x124) /* GCM通道状态寄存器9 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA10_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x128) /* GCM通道状态寄存器10 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA11_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x12C) /* GCM通道状态寄存器11 */ +#define CSR_CRX_IPSEC_GCM_CSR_IPSEC_GCM_STA12_REG (CSR_CRX_IPSEC_GCM_CSR_BASE + 0x130) /* GCM通道状态寄存器12 */ + +/* CTX_IPSEC_GCM_CSR Base address of Module's Register */ +#define CSR_CTX_IPSEC_GCM_CSR_BASE (0x6000) + +/* **************************************************************************** */ +/* CTX_IPSEC_GCM_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_16K_TH_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x0) /* GCM通道出口整包缓存FIFO将满阈值 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_CTRL_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x4) /* GCM通道控制寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_CORE_RSV_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x8) /* GCM_CORE保留寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_CLUSTER_RSV_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x10) /* GCM通道ECO寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_PROBE_I_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x20) /* GCM内部MEMPROBE输入信号 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_PROBE_RDATA_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x24) /* GCM内部MEM PROBE输出信号 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_CTRL_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x28) /* GCM通道FIFO PROBE控制寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_STAT_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x2C) /* GCM通道FIFO PROBE状态寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_0_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x30) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_1_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x34) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_2_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x38) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_3_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x3C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_4_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x40) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_5_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x44) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_6_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x48) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_7_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x4C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xA0) /* GCM通道BD_ERR历史状态寄存器 \ + */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_CLR_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xA4) /* GCM通道BD_ERR历史状态清除寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_L_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xA8) /* GCM通道BD_ERR掩码低位寄存器 \ + */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_H_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xAC) /* GCM通道BD_ERR掩码高位寄存器 \ + */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_ECC_ERR1_CNT_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xB0) /* GCM通道ECC1比特错误计数器 */ +#define CSR_CTX_IPSEC_GCM_CSR_GCM_ECC_ERR2_ADDR_REG \ + (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xB4) /* GCM通道ECC2比特错误地址寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_INT_EN_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0xFC) /* GCM通道中断使能寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_ALM_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x100) /* GCM通道告警寄存器 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA1_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x104) /* GCM通道状态寄存器1 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA2_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x108) /* GCM通道状态寄存器2 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA3_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x10C) /* GCM通道状态寄存器3 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA4_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x110) /* GCM通道状态寄存器4 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA5_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x114) /* GCM通道状态寄存器5 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA6_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x118) /* GCM通道状态寄存器6 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA7_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x11C) /* GCM通道状态寄存器7 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA8_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x120) /* GCM通道状态寄存器8 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA9_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x124) /* GCM通道状态寄存器9 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA10_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x128) /* GCM通道状态寄存器10 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA11_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x12C) /* GCM通道状态寄存器11 */ +#define CSR_CTX_IPSEC_GCM_CSR_IPSEC_GCM_STA12_REG (CSR_CTX_IPSEC_GCM_CSR_BASE + 0x130) /* GCM通道状态寄存器12 */ + +/* CRX_IPSEC_CBC_CSR Base address of Module's Register */ +#define CSR_CRX_IPSEC_CBC_CSR_BASE (0x3400) + +/* **************************************************************************** */ +/* CRX_IPSEC_CBC_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_16K_TH_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x0) /* CBC通道出口整包缓存FIFO将满阈值 */ +#define CSR_CRX_IPSEC_CBC_CSR_SAA_CH_EN_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x4) /* CBC通道内部子通道使能 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_CORE_RSV_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x8) /* CBC_CORE保留寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_RSV_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x10) /* SEC_CLUSTER模块保留寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_ALU_ADDR_I_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x14) /* CLUSTER DFX地址输入寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_ALU_RDATA_O_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x18) /* CLUSTER DFX数据输出寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_0_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x20) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_1_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x24) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_2_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x28) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_3_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x2C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_4_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x30) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_5_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x34) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_6_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x38) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_7_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x3C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_8_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x40) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_9_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x44) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_10_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x48) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_11_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x4C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_12_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x50) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_13_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x54) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_PROBE_I_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x60) /* CBC内部MEMPROBE输入信号 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_PROBE_RDATA_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x64) /* CBC内部MEM PROBE输出信号 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_CTRL_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x68) /* CBC通道FIFO PROBE控制寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_STAT_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x6C) /* CBC通道FIFO PROBE状态寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_BD_ERR_CODE_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xA0) /* CBC通道BD_ERR历史状态寄存器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_BD_ERR_CODE_CLR_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xA4) /* CBC通道BD_ERR历史状态清除寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_BD_ERR_MSK_L_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xA8) /* CBC通道BD_ERR掩码低位寄存器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_BD_ERR_MSK_H_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xAC) /* CBC通道BD_ERR掩码高位寄存器 \ + */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_0_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x70) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_1_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x74) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_2_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x78) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_3_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x7C) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_4_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x80) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_5_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x84) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_6_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x88) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_7_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x8C) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_ECC_ERR1_CNT_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xB0) /* CBC通道ECC1比特错误计数器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_ECC_ERR2_ADDR_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xB4) /* CBC通道ECC2比特错误地址寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_INT_EN_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0xFC) /* CBC通道中断使能寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_ALM_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x100) /* CBC通道告警寄存器 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_STA1_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x104) /* CBC通道状态寄存器1 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_STA2_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x108) /* CBC通道状态寄存器2 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_STA3_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x10C) /* CBC通道状态寄存器3 */ +#define CSR_CRX_IPSEC_CBC_CSR_IPSEC_CBC_STA4_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x110) /* CBC通道状态寄存器4 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_CORE_CNT_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x114) /* CBC通道尾数统计计数器 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_0_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x150) /* CRYPTOBC DFT_MEM_CTRL寄存器0 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_1_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x154) /* CRYPTOBC DFT_MEM_CTRL寄存器1 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_2_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x158) /* CRYPTOBC DFT_MEM_CTRL寄存器2 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_3_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x15C) /* CRYPTOBC DFT_MEM_CTRL寄存器3 */ +#define CSR_CRX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_4_REG \ + (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x160) /* CRYPTOBC DFT_MEM_CTRL寄存器4 */ +#define CSR_CRX_IPSEC_CBC_CSR_TRNG_CFG_REG (CSR_CRX_IPSEC_CBC_CSR_BASE + 0x170) /* 随机数配置寄存器 */ + +/* CTX_IPSEC_CBC_CSR Base address of Module's Register */ +#define CSR_CTX_IPSEC_CBC_CSR_BASE (0x6400) + +/* **************************************************************************** */ +/* CTX_IPSEC_CBC_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_16K_TH_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x0) /* CBC通道出口整包缓存FIFO将满阈值 */ +#define CSR_CTX_IPSEC_CBC_CSR_SAA_CH_EN_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x4) /* CBC通道内部子通道使能 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_CORE_RSV_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x8) /* CBC_CORE保留寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_RSV_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x10) /* SEC_CLUSTER模块保留寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_ALU_ADDR_I_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x14) /* CLUSTER DFX地址输入寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_ALU_RDATA_O_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x18) /* CLUSTER DFX数据输出寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_0_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x20) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_1_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x24) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_2_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x28) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_3_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x2C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_4_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x30) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_5_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x34) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_6_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x38) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_7_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x3C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_8_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x40) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_9_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x44) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_10_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x48) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_11_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x4C) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_12_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x50) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_SEC_CLUSTER_SAA_CNT_13_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x54) /* SAA流量尾数统计计数器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_PROBE_I_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x60) /* CBC内部MEMPROBE输入信号 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_PROBE_RDATA_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x64) /* CBC内部MEM PROBE输出信号 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_CTRL_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x68) /* CBC通道FIFO PROBE控制寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_STAT_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x6C) /* CBC通道FIFO PROBE状态寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_BD_ERR_CODE_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xA0) /* CBC通道BD_ERR历史状态寄存器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_BD_ERR_CODE_CLR_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xA4) /* CBC通道BD_ERR历史状态清除寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_BD_ERR_MSK_L_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xA8) /* CBC通道BD_ERR掩码低位寄存器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_BD_ERR_MSK_H_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xAC) /* CBC通道BD_ERR掩码高位寄存器 \ + */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_0_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x70) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_1_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x74) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_2_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x78) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_3_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x7C) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_4_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x80) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_5_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x84) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_6_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x88) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_FIFO_PROBE_RDATA_7_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x8C) /* CBC通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_ECC_ERR1_CNT_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xB0) /* CBC通道ECC1比特错误计数器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_ECC_ERR2_ADDR_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xB4) /* CBC通道ECC2比特错误地址寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_INT_EN_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0xFC) /* CBC通道中断使能寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_ALM_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x100) /* CBC通道告警寄存器 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_STA1_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x104) /* CBC通道状态寄存器1 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_STA2_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x108) /* CBC通道状态寄存器2 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_STA3_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x10C) /* CBC通道状态寄存器3 */ +#define CSR_CTX_IPSEC_CBC_CSR_IPSEC_CBC_STA4_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x110) /* CBC通道状态寄存器4 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_CORE_CNT_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x114) /* CBC通道尾数统计计数器 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_0_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x150) /* CRYPTOBC DFT_MEM_CTRL寄存器0 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_1_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x154) /* CRYPTOBC DFT_MEM_CTRL寄存器1 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_2_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x158) /* CRYPTOBC DFT_MEM_CTRL寄存器2 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_3_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x15C) /* CRYPTOBC DFT_MEM_CTRL寄存器3 */ +#define CSR_CTX_IPSEC_CBC_CSR_CBC_DFT_MEM_CTRL_4_REG \ + (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x160) /* CRYPTOBC DFT_MEM_CTRL寄存器4 */ +#define CSR_CTX_IPSEC_CBC_CSR_TRNG_CFG_REG (CSR_CTX_IPSEC_CBC_CSR_BASE + 0x170) /* 随机数配置寄存器 */ + +/* CRX_XTS_IPSEC_GCM_CSR Base address of Module's Register */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_BASE (0x3800) + +/* **************************************************************************** */ +/* CRX_XTS_IPSEC_GCM_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_16K_TH_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x0) /* GCM通道出口整包缓存FIFO将满阈值 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_CTRL_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x4) /* GCM通道控制寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_CORE_RSV_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x8) /* GCM_CORE保留寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_CLUSTER_RSV_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x10) /* GCM通道ECO寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_PROBE_I_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x20) /* GCM内部MEMPROBE输入信号 \ + */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_PROBE_RDATA_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x24) /* GCM内部MEM PROBE输出信号 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_CTRL_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x28) /* GCM通道FIFO PROBE控制寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_STAT_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x2C) /* GCM通道FIFO PROBE状态寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_0_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x30) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_1_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x34) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_2_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x38) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_3_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x3C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_4_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x40) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_5_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x44) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_6_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x48) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_7_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x4C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xA0) /* GCM通道BD_ERR历史状态寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_CLR_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xA4) /* GCM通道BD_ERR历史状态清除寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_L_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xA8) /* GCM通道BD_ERR掩码低位寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_H_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xAC) /* GCM通道BD_ERR掩码高位寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_ECC_ERR1_CNT_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xB0) /* GCM通道ECC1比特错误计数器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_GCM_ECC_ERR2_ADDR_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xB4) /* GCM通道ECC2比特错误地址寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_INT_EN_REG \ + (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0xFC) /* GCM通道中断使能寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_ALM_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x100) /* GCM通道告警寄存器 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA1_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x104) /* GCM通道状态寄存器1 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA2_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x108) /* GCM通道状态寄存器2 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA3_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x10C) /* GCM通道状态寄存器3 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA4_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x110) /* GCM通道状态寄存器4 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA5_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x114) /* GCM通道状态寄存器5 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA6_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x118) /* GCM通道状态寄存器6 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA7_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x11C) /* GCM通道状态寄存器7 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA8_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x120) /* GCM通道状态寄存器8 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA9_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x124) /* GCM通道状态寄存器9 */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA10_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x128) /* GCM通道状态寄存器10 \ + */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA11_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x12C) /* GCM通道状态寄存器11 \ + */ +#define CSR_CRX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA12_REG (CSR_CRX_XTS_IPSEC_GCM_CSR_BASE + 0x130) /* GCM通道状态寄存器12 \ + */ + +/* CTX_XTS_IPSEC_GCM_CSR Base address of Module's Register */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_BASE (0x6C00) + +/* **************************************************************************** */ +/* CTX_XTS_IPSEC_GCM_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_16K_TH_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x0) /* GCM通道出口整包缓存FIFO将满阈值 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_CTRL_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x4) /* GCM通道控制寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_CORE_RSV_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x8) /* GCM_CORE保留寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_CLUSTER_RSV_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x10) /* GCM通道ECO寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_PROBE_I_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x20) /* GCM内部MEMPROBE输入信号 \ + */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_PROBE_RDATA_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x24) /* GCM内部MEM PROBE输出信号 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_CTRL_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x28) /* GCM通道FIFO PROBE控制寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_STAT_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x2C) /* GCM通道FIFO PROBE状态寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_0_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x30) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_1_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x34) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_2_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x38) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_3_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x3C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_4_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x40) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_5_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x44) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_6_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x48) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_7_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x4C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xA0) /* GCM通道BD_ERR历史状态寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_CLR_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xA4) /* GCM通道BD_ERR历史状态清除寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_L_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xA8) /* GCM通道BD_ERR掩码低位寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_H_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xAC) /* GCM通道BD_ERR掩码高位寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_ECC_ERR1_CNT_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xB0) /* GCM通道ECC1比特错误计数器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_GCM_ECC_ERR2_ADDR_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xB4) /* GCM通道ECC2比特错误地址寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_INT_EN_REG \ + (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0xFC) /* GCM通道中断使能寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_ALM_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x100) /* GCM通道告警寄存器 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA1_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x104) /* GCM通道状态寄存器1 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA2_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x108) /* GCM通道状态寄存器2 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA3_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x10C) /* GCM通道状态寄存器3 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA4_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x110) /* GCM通道状态寄存器4 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA5_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x114) /* GCM通道状态寄存器5 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA6_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x118) /* GCM通道状态寄存器6 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA7_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x11C) /* GCM通道状态寄存器7 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA8_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x120) /* GCM通道状态寄存器8 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA9_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x124) /* GCM通道状态寄存器9 */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA10_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x128) /* GCM通道状态寄存器10 \ + */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA11_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x12C) /* GCM通道状态寄存器11 \ + */ +#define CSR_CTX_XTS_IPSEC_GCM_CSR_IPSEC_GCM_STA12_REG (CSR_CTX_XTS_IPSEC_GCM_CSR_BASE + 0x130) /* GCM通道状态寄存器12 \ + */ + +/* CTX_XTS_EC_IPSEC_GCM_CSR Base address of Module's Register */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE (0x6800) + +/* **************************************************************************** */ +/* CTX_XTS_EC_IPSEC_GCM_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_16K_TH_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x0) /* GCM通道出口整包缓存FIFO将满阈值 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_CTRL_REG (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x4) /* GCM通道控制寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_CORE_RSV_REG (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x8) /* GCM_CORE保留寄存器 \ + */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_CLUSTER_RSV_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x10) /* GCM通道ECO寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_PROBE_I_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x20) /* GCM内部MEMPROBE输入信号 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_PROBE_RDATA_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x24) /* GCM内部MEM PROBE输出信号 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_CTRL_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x28) /* GCM通道FIFO PROBE控制寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_STAT_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x2C) /* GCM通道FIFO PROBE状态寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_0_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x30) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_1_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x34) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_2_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x38) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_3_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x3C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_4_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x40) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_5_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x44) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_6_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x48) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_FIFO_PROBE_RDATA_7_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x4C) /* GCM通道FIFO PROBE数据寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xA0) /* GCM通道BD_ERR历史状态寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_BD_ERR_CODE_CLR_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xA4) /* GCM通道BD_ERR历史状态清除寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_L_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xA8) /* GCM通道BD_ERR掩码低位寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_BD_ERR_MSK_H_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xAC) /* GCM通道BD_ERR掩码高位寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_ECC_ERR1_CNT_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xB0) /* GCM通道ECC1比特错误计数器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_GCM_ECC_ERR2_ADDR_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xB4) /* GCM通道ECC2比特错误地址寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_INT_EN_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0xFC) /* GCM通道中断使能寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_ALM_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x100) /* GCM通道告警寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA1_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x104) /* GCM通道状态寄存器1 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA2_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x108) /* GCM通道状态寄存器2 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA3_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x10C) /* GCM通道状态寄存器3 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA4_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x110) /* GCM通道状态寄存器4 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA5_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x114) /* GCM通道状态寄存器5 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA6_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x118) /* GCM通道状态寄存器6 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA7_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x11C) /* GCM通道状态寄存器7 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA8_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x120) /* GCM通道状态寄存器8 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA9_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x124) /* GCM通道状态寄存器9 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA10_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x128) /* GCM通道状态寄存器10 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA11_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x12C) /* GCM通道状态寄存器11 */ +#define CSR_CTX_XTS_EC_IPSEC_GCM_CSR_IPSEC_GCM_STA12_REG \ + (CSR_CTX_XTS_EC_IPSEC_GCM_CSR_BASE + 0x130) /* GCM通道状态寄存器12 */ + +/* CRX_XTS_IPSEC_KEY_CSR Base address of Module's Register */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_BASE (0x3A00) + +/* **************************************************************************** */ +/* CRX_XTS_IPSEC_KEY_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG7_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x0) /* XTS_KEY1配置寄存器7 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG6_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x4) /* XTS_KEY1配置寄存器6 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG5_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x8) /* XTS_KEY1配置寄存器5 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG4_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0xC) /* XTS_KEY1配置寄存器4 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG3_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x10) /* XTS_KEY1配置寄存器3 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG2_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x14) /* XTS_KEY1配置寄存器2 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG1_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x18) /* XTS_KEY1配置寄存器1 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG0_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x1C) /* XTS_KEY1配置寄存器0 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG7_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x20) /* XTS_KEY2配置寄存器7 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG6_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x24) /* XTS_KEY2配置寄存器6 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG5_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x28) /* XTS_KEY2配置寄存器5 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG4_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x2C) /* XTS_KEY2配置寄存器4 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG3_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x30) /* XTS_KEY2配置寄存器3 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG2_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x34) /* XTS_KEY2配置寄存器2 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG1_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x38) /* XTS_KEY2配置寄存器1 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG0_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x3C) /* XTS_KEY2配置寄存器0 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY_CTRL_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x40) /* XTS_KEY控制寄存器 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_KEY_STAT_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x44) /* XTS_KEY状态寄存器 */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTX_MEM_INIT_REG (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x48) /* XTS MEM初始化使能寄存器 \ + */ +#define CSR_CRX_XTS_IPSEC_KEY_CSR_XTS_MEM_INIT_DONE_REG \ + (CSR_CRX_XTS_IPSEC_KEY_CSR_BASE + 0x4C) /* XTS MEM初始化状态寄存器 */ + +/* CTX_XTS_IPSEC_KEY_CSR Base address of Module's Register */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_BASE (0x6E00) + +/* **************************************************************************** */ +/* CTX_XTS_IPSEC_KEY_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG7_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x0) /* XTS_KEY1配置寄存器7 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG6_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x4) /* XTS_KEY1配置寄存器6 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG5_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x8) /* XTS_KEY1配置寄存器5 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG4_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0xC) /* XTS_KEY1配置寄存器4 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG3_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x10) /* XTS_KEY1配置寄存器3 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG2_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x14) /* XTS_KEY1配置寄存器2 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG1_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x18) /* XTS_KEY1配置寄存器1 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY1_CFG0_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x1C) /* XTS_KEY1配置寄存器0 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG7_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x20) /* XTS_KEY2配置寄存器7 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG6_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x24) /* XTS_KEY2配置寄存器6 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG5_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x28) /* XTS_KEY2配置寄存器5 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG4_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x2C) /* XTS_KEY2配置寄存器4 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG3_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x30) /* XTS_KEY2配置寄存器3 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG2_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x34) /* XTS_KEY2配置寄存器2 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG1_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x38) /* XTS_KEY2配置寄存器1 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY2_CFG0_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x3C) /* XTS_KEY2配置寄存器0 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY_CTRL_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x40) /* XTS_KEY控制寄存器 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_KEY_STAT_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x44) /* XTS_KEY状态寄存器 */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTX_MEM_INIT_REG (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x48) /* XTS MEM初始化使能寄存器 \ + */ +#define CSR_CTX_XTS_IPSEC_KEY_CSR_XTS_MEM_INIT_DONE_REG \ + (CSR_CTX_XTS_IPSEC_KEY_CSR_BASE + 0x4C) /* XTS MEM初始化状态寄存器 */ + +/* CTX_XTS_EC_IPSEC_KEY_CSR Base address of Module's Register */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE (0x6A00) + +/* **************************************************************************** */ +/* CTX_XTS_EC_IPSEC_KEY_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG7_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x0) /* XTS_KEY1配置寄存器7 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG6_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x4) /* XTS_KEY1配置寄存器6 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG5_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x8) /* XTS_KEY1配置寄存器5 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG4_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0xC) /* XTS_KEY1配置寄存器4 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG3_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x10) /* XTS_KEY1配置寄存器3 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG2_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x14) /* XTS_KEY1配置寄存器2 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG1_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x18) /* XTS_KEY1配置寄存器1 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY1_CFG0_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x1C) /* XTS_KEY1配置寄存器0 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG7_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x20) /* XTS_KEY2配置寄存器7 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG6_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x24) /* XTS_KEY2配置寄存器6 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG5_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x28) /* XTS_KEY2配置寄存器5 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG4_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x2C) /* XTS_KEY2配置寄存器4 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG3_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x30) /* XTS_KEY2配置寄存器3 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG2_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x34) /* XTS_KEY2配置寄存器2 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG1_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x38) /* XTS_KEY2配置寄存器1 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY2_CFG0_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x3C) /* XTS_KEY2配置寄存器0 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY_CTRL_REG (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x40) /* XTS_KEY控制寄存器 \ + */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_KEY_STAT_REG (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x44) /* XTS_KEY状态寄存器 \ + */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTX_MEM_INIT_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x48) /* XTS MEM初始化使能寄存器 */ +#define CSR_CTX_XTS_EC_IPSEC_KEY_CSR_XTS_MEM_INIT_DONE_REG \ + (CSR_CTX_XTS_EC_IPSEC_KEY_CSR_BASE + 0x4C) /* XTS MEM初始化状态寄存器 */ + +/* TRNG_CSR Base address of Module's Register */ +#define CSR_TRNG_CSR_BASE (0xF000) + +/* **************************************************************************** */ +/* TRNG_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_TRNG_CSR_TRNG_OUTPUT_0_REG (CSR_TRNG_CSR_BASE + 0x0) /* 随机数输出寄存器0 */ +#define CSR_TRNG_CSR_TRNG_OUTPUT_1_REG (CSR_TRNG_CSR_BASE + 0x4) /* 随机数输出寄存器1 */ +#define CSR_TRNG_CSR_TRNG_OUTPUT_2_REG (CSR_TRNG_CSR_BASE + 0x8) /* 随机数输出寄存器2 */ +#define CSR_TRNG_CSR_TRNG_OUTPUT_3_REG (CSR_TRNG_CSR_BASE + 0xC) /* 随机数输出寄存器3 */ +#define CSR_TRNG_CSR_TRNG_INPUT_0_REG (CSR_TRNG_CSR_BASE + 0x0) /* 数据输入寄存器0 */ +#define CSR_TRNG_CSR_TRNG_INPUT_1_REG (CSR_TRNG_CSR_BASE + 0x4) /* 数据输入寄存器1 */ +#define CSR_TRNG_CSR_TRNG_INPUT_2_REG (CSR_TRNG_CSR_BASE + 0x8) /* 数据输入寄存器2 */ +#define CSR_TRNG_CSR_TRNG_INPUT_3_REG (CSR_TRNG_CSR_BASE + 0xC) /* 数据输入寄存器3 */ +#define CSR_TRNG_CSR_TRNG_STATUS_REG (CSR_TRNG_CSR_BASE + 0x10) /* 状态寄存器 */ +#define CSR_TRNG_CSR_TRNG_INTACK_REG (CSR_TRNG_CSR_BASE + 0x10) /* 中断清除寄存器 */ +#define CSR_TRNG_CSR_TRNG_CONTROL_REG (CSR_TRNG_CSR_BASE + 0x14) /* 控制寄存器 */ +#define CSR_TRNG_CSR_TRNG_CONFIG_REG (CSR_TRNG_CSR_BASE + 0x18) /* 配置寄存器 */ +#define CSR_TRNG_CSR_TRNG_ALARMCNT_REG (CSR_TRNG_CSR_BASE + 0x1C) /* 关断中断控制寄存器 */ +#define CSR_TRNG_CSR_TRNG_FROENABLE_REG (CSR_TRNG_CSR_BASE + 0x20) /* FRO使能寄存器 */ +#define CSR_TRNG_CSR_TRNG_FRODETUNE_REG (CSR_TRNG_CSR_BASE + 0x24) /* FRO调节寄存器 */ +#define CSR_TRNG_CSR_TRNG_ALARMMASK_REG (CSR_TRNG_CSR_BASE + 0x28) /* 告警事件log寄存器 */ +#define CSR_TRNG_CSR_TRNG_ALARMSTOP_REG (CSR_TRNG_CSR_BASE + 0x2C) /* 告警关断寄存器 */ +#define CSR_TRNG_CSR_TRNG_RAW_L_REG (CSR_TRNG_CSR_BASE + 0x30) /* 原始噪声bit低位寄存器 */ +#define CSR_TRNG_CSR_TRNG_RAW_H_REG (CSR_TRNG_CSR_BASE + 0x34) /* 原始噪声bit高位寄存器 */ +#define CSR_TRNG_CSR_TRNG_SPB_TESTS_REG (CSR_TRNG_CSR_BASE + 0x38) /* SP 800-90B测试控制寄存器 */ +#define CSR_TRNG_CSR_TRNG_COUNT_REG (CSR_TRNG_CSR_BASE + 0x3C) /* 主时间计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_COND_0_REG (CSR_TRNG_CSR_BASE + 0x40) /* 加工功能输出寄存器0 */ +#define CSR_TRNG_CSR_TRNG_COND_1_REG (CSR_TRNG_CSR_BASE + 0x44) /* 加工功能输出寄存器1 */ +#define CSR_TRNG_CSR_TRNG_COND_2_REG (CSR_TRNG_CSR_BASE + 0x48) /* 加工功能输出寄存器2 */ +#define CSR_TRNG_CSR_TRNG_COND_3_REG (CSR_TRNG_CSR_BASE + 0x4C) /* 加工功能输出寄存器3 */ +#define CSR_TRNG_CSR_TRNG_COND_4_REG (CSR_TRNG_CSR_BASE + 0x50) /* 加工功能输出寄存器4 */ +#define CSR_TRNG_CSR_TRNG_COND_5_REG (CSR_TRNG_CSR_BASE + 0x54) /* 加工功能输出寄存器5 */ +#define CSR_TRNG_CSR_TRNG_COND_6_REG (CSR_TRNG_CSR_BASE + 0x58) /* 加工功能输出寄存器6 */ +#define CSR_TRNG_CSR_TRNG_COND_7_REG (CSR_TRNG_CSR_BASE + 0x5C) /* 加工功能输出寄存器7 */ +#define CSR_TRNG_CSR_TRNG_KEY_0_REG (CSR_TRNG_CSR_BASE + 0x40) /* DRBG AES-256 key寄存器0 */ +#define CSR_TRNG_CSR_TRNG_KEY_1_REG (CSR_TRNG_CSR_BASE + 0x44) /* DRBG AES-256 key寄存器1 */ +#define CSR_TRNG_CSR_TRNG_KEY_2_REG (CSR_TRNG_CSR_BASE + 0x48) /* DRBG AES-256 key寄存器2 */ +#define CSR_TRNG_CSR_TRNG_KEY_3_REG (CSR_TRNG_CSR_BASE + 0x4C) /* DRBG AES-256 key寄存器3 */ +#define CSR_TRNG_CSR_TRNG_KEY_4_REG (CSR_TRNG_CSR_BASE + 0x50) /* DRBG AES-256 key寄存器4 */ +#define CSR_TRNG_CSR_TRNG_KEY_5_REG (CSR_TRNG_CSR_BASE + 0x54) /* DRBG AES-256 key寄存器5 */ +#define CSR_TRNG_CSR_TRNG_KEY_6_REG (CSR_TRNG_CSR_BASE + 0x58) /* DRBG AES-256 key寄存器6 */ +#define CSR_TRNG_CSR_TRNG_KEY_7_REG (CSR_TRNG_CSR_BASE + 0x5C) /* DRBG AES-256 key寄存器7 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_0_REG (CSR_TRNG_CSR_BASE + 0x40) /* DRBG输入寄存器0 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_1_REG (CSR_TRNG_CSR_BASE + 0x44) /* DRBG输入寄存器1 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_2_REG (CSR_TRNG_CSR_BASE + 0x48) /* DRBG输入寄存器2 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_3_REG (CSR_TRNG_CSR_BASE + 0x4C) /* DRBG输入寄存器3 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_4_REG (CSR_TRNG_CSR_BASE + 0x50) /* DRBG输入寄存器4 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_5_REG (CSR_TRNG_CSR_BASE + 0x54) /* DRBG输入寄存器5 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_6_REG (CSR_TRNG_CSR_BASE + 0x58) /* DRBG输入寄存器6 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_7_REG (CSR_TRNG_CSR_BASE + 0x5C) /* DRBG输入寄存器7 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_8_REG (CSR_TRNG_CSR_BASE + 0x60) /* DRBG输入寄存器8 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_9_REG (CSR_TRNG_CSR_BASE + 0x64) /* DRBG输入寄存器9 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_10_REG (CSR_TRNG_CSR_BASE + 0x68) /* DRBG输入寄存器10 */ +#define CSR_TRNG_CSR_TRNG_PS_AI_11_REG (CSR_TRNG_CSR_BASE + 0x6C) /* DRBG输入寄存器11 */ +#define CSR_TRNG_CSR_TRNG_RUN_CNT_REG (CSR_TRNG_CSR_BASE + 0x40) /* bits和runs 计数器状态寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_1_REG (CSR_TRNG_CSR_BASE + 0x44) /* 1bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_2_REG (CSR_TRNG_CSR_BASE + 0x48) /* 2bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_3_REG (CSR_TRNG_CSR_BASE + 0x4C) /* 3bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_4_REG (CSR_TRNG_CSR_BASE + 0x50) /* 4bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_5_REG (CSR_TRNG_CSR_BASE + 0x54) /* 5bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_RUN_6_UP_REG (CSR_TRNG_CSR_BASE + 0x58) /* 大于等于6bit 0/1 runs计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_MONOBITCNT_REG (CSR_TRNG_CSR_BASE + 0x5C) /* “Monobit”测试计数器寄存器 */ +#define CSR_TRNG_CSR_TRNG_POKER_3_0_REG (CSR_TRNG_CSR_BASE + 0x60) /* “Poker”测试计数器0-3寄存器 */ +#define CSR_TRNG_CSR_TRNG_POKER_7_4_REG (CSR_TRNG_CSR_BASE + 0x64) /* “Poker”测试计数器4-7寄存器 */ +#define CSR_TRNG_CSR_TRNG_POKER_B_8_REG (CSR_TRNG_CSR_BASE + 0x68) /* “Poker”测试计数器8-B寄存器 */ +#define CSR_TRNG_CSR_TRNG_POKER_F_C_REG (CSR_TRNG_CSR_BASE + 0x6C) /* “Poker”测试计数器C-F寄存器 */ +#define CSR_TRNG_CSR_TRNG_TEST_REG (CSR_TRNG_CSR_BASE + 0x70) /* 测试控制寄存器 */ +#define CSR_TRNG_CSR_TRNG_BLOCKCNT_REG (CSR_TRNG_CSR_BASE + 0x74) /* 输出block计数器 */ +#define CSR_TRNG_CSR_TRNG_OPTIONS_REG (CSR_TRNG_CSR_BASE + 0x78) /* 引擎可选信息 */ +#define CSR_TRNG_CSR_TRNG_EIP_REV_REG (CSR_TRNG_CSR_BASE + 0x7C) /* EIP 数字和core版本信息 */ +#define CSR_TRNG_CSR_TRNG_CTRL0_REG (CSR_TRNG_CSR_BASE + 0xC0) /* TRNG全局控制寄存器0 */ +#define CSR_TRNG_CSR_TRNG_CTRL1_REG (CSR_TRNG_CSR_BASE + 0xC4) /* TRNG全局控制寄存器1 */ +#define CSR_TRNG_CSR_TRNG_INT_VECTOR_REG (CSR_TRNG_CSR_BASE + 0xC8) /* 中断向量 */ +#define CSR_TRNG_CSR_RNG_CTRL_REG (CSR_TRNG_CSR_BASE + 0xCC) /* RNG控制寄存器 */ +#define CSR_TRNG_CSR_RNG_SEED_REG (CSR_TRNG_CSR_BASE + 0xD0) /* RNG随机种子配置寄存器 */ +#define CSR_TRNG_CSR_TRNG_FSM_ST_REG (CSR_TRNG_CSR_BASE + 0xD4) /* TRNG core内部状态机实时状态 */ +#define CSR_TRNG_CSR_RNG_NUM_REG (CSR_TRNG_CSR_BASE + 0xD8) /* RNG产生的32bit随机数 */ +#define CSR_TRNG_CSR_RNG_PHY_SEED_REG (CSR_TRNG_CSR_BASE + 0xDC) /* RNG的物理环产生的随机种子 */ +#define CSR_TRNG_CSR_RNG_ERR_REG (CSR_TRNG_CSR_BASE + 0xE0) /* RNG错误状态 */ +#define CSR_TRNG_CSR_TRNG_INT_SET_REG (CSR_TRNG_CSR_BASE + 0xE4) /* 中断置位寄存器 */ +#define CSR_TRNG_CSR_TRNG_INT_EN_REG (CSR_TRNG_CSR_BASE + 0xE8) /* 中断使能 */ +#define CSR_TRNG_CSR_TRNG_INT_ST_REG (CSR_TRNG_CSR_BASE + 0xEC) /* 中断状态 */ +#define CSR_TRNG_CSR_TRNG_RAN_DATA0_REG (CSR_TRNG_CSR_BASE + 0xF0) /* TRNG真随机数生成寄存器（非安全可读） */ +#define CSR_TRNG_CSR_TRNG_RAN_DATA1_REG (CSR_TRNG_CSR_BASE + 0xF4) /* TRNG真随机数生成寄存器（非安全可读） */ +#define CSR_TRNG_CSR_TRNG_RAN_DATA2_REG (CSR_TRNG_CSR_BASE + 0xF8) /* TRNG真随机数生成寄存器（非安全可读） */ +#define CSR_TRNG_CSR_TRNG_RAN_DATA3_REG (CSR_TRNG_CSR_BASE + 0xFC) /* TRNG真随机数生成寄存器（非安全可读） */ + +/* SRAM Base address of Module's Register */ +#define CSR_SRAM_BASE (0x8000) + +/* **************************************************************************** */ +/* SRAM Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SRAM_SRAM_CTRL_REG (CSR_SRAM_BASE + 0x0) /* SRAM控制寄存器 */ +#define CSR_SRAM_SRAM_STATE_REG (CSR_SRAM_BASE + 0x4) /* SRAM状态寄存器 */ +#define CSR_SRAM_SRAM_SEC_CTRL_REG (CSR_SRAM_BASE + 0x10) /* SRAM安全空间控制寄存器 */ +#define CSR_SRAM_SRAM_SEC_ADDR_REG (CSR_SRAM_BASE + 0x14) /* SRAM安全空间地址寄存器 */ +#define CSR_SRAM_SRAM_SEC_SIZE_REG (CSR_SRAM_BASE + 0x18) /* SRAM安全空间Size寄存器 */ +#define CSR_SRAM_SRAM_BASE_ADDR_REG (CSR_SRAM_BASE + 0x20) /* SRAM 基地址地址寄存器 */ +#define CSR_SRAM_SRAM_INTMASK_REG (CSR_SRAM_BASE + 0x40) /* SRAM中断屏蔽寄存器 */ +#define CSR_SRAM_SRAM_RAWINT_REG (CSR_SRAM_BASE + 0x44) /* SRAM原始中断状态寄存器 */ +#define CSR_SRAM_SRAM_INTSTS_REG (CSR_SRAM_BASE + 0x48) /* SRAM中断状态寄存器 */ +#define CSR_SRAM_SRAM_INTCLR_REG (CSR_SRAM_BASE + 0x4C) /* SRAM中断清除寄存器 */ +#define CSR_SRAM_SRAM_ECC_INJECT_REG (CSR_SRAM_BASE + 0x60) /* SRAM ECC注入寄存器 */ +#define CSR_SRAM_SRAM_ERR_INFO_REG (CSR_SRAM_BASE + 0x64) /* SRAM错误操作信息寄存器 */ +#define CSR_SRAM_SRAM_ERR_ADDR_REG (CSR_SRAM_BASE + 0x68) /* SRAM错误操作地址寄存器 */ +#define CSR_SRAM_SRAM_ECC_INFO_REG (CSR_SRAM_BASE + 0x6C) /* SRAM ECC错误寄存器 */ +#define CSR_SRAM_SRAM_CLR_STAT_REG (CSR_SRAM_BASE + 0x70) /* SRAM状态清除寄存器 */ +#define CSR_SRAM_SRAM_ECC_CNT_REG (CSR_SRAM_BASE + 0x80) /* SRAM ECC错误计数器 */ +#define CSR_SRAM_SRAM_CNT_TYPE_REG (CSR_SRAM_BASE + 0x84) /* SRAM DFX计数器类型控制寄存器 */ +#define CSR_SRAM_SRAM_CNT0_REG (CSR_SRAM_BASE + 0x88) /* SRAM DFX计数器0 */ +#define CSR_SRAM_SRAM_CNT1_REG (CSR_SRAM_BASE + 0x8C) /* SRAM DFX计数器0 */ +#define CSR_SRAM_SRAM_CNT2_REG (CSR_SRAM_BASE + 0x90) /* SRAM DFX计数器0 */ +#define CSR_SRAM_SRAM_CNT3_REG (CSR_SRAM_BASE + 0x94) /* SRAM DFX计数器0 */ +#define CSR_SRAM_SRAM_MAGIC_WORD_REG (CSR_SRAM_BASE + 0x7F0) /* SRAM版本修改寄存器 */ +#define CSR_SRAM_SRAM_VERSION_REG (CSR_SRAM_BASE + 0xC10) /* SRAM版本寄存器 */ + +/* AM_OOO_CFG Base address of Module's Register */ +#define CSR_AM_OOO_CFG_BASE (0x9000) + +/* **************************************************************************** */ +/* AM_OOO_CFG Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_AM_OOO_CFG_AM_CTRL_GLOBAL_REG (CSR_AM_OOO_CFG_BASE + 0x0) /* 全局控制 */ +#define CSR_AM_OOO_CFG_AM_CTRL_LATENCY_SEL_REG (CSR_AM_OOO_CFG_BASE + 0x4) /* 选择对某个通道进行总线访问延迟统计。 */ +#define CSR_AM_OOO_CFG_AM_CTRL_PTL_WR_REG (CSR_AM_OOO_CFG_BASE + 0x8) /* 控制使能PARTIAL WR操作 */ +#define CSR_AM_OOO_CFG_AM_CFG_MAX_TRANS_REG (CSR_AM_OOO_CFG_BASE + 0x10) /* 配置全局允许的最大outstanding数量 */ +#define CSR_AM_OOO_CFG_AM_CFG_SINGLE_PORT_MAX_TRANS_REG \ + (CSR_AM_OOO_CFG_BASE + 0x14) /* 配置全局允许的最大outstanding数量 */ +#define CSR_AM_OOO_CFG_AM_CFG_PORT_RD_EN_REG (CSR_AM_OOO_CFG_BASE + 0x18) /* 配置允许打开的内部读端口 */ +#define CSR_AM_OOO_CFG_AM_CFG_PORT_WR_EN_REG (CSR_AM_OOO_CFG_BASE + 0x1C) /* 配置允许打开的内部写端口 */ +#define CSR_AM_OOO_CFG_AM_CURR_AW_W_FIFO_STS_REG (CSR_AM_OOO_CFG_BASE + 0x20) /* AW与W之间FIFO的当前状态 */ +#define CSR_AM_OOO_CFG_AM_CURR_PORT_STS_REG (CSR_AM_OOO_CFG_BASE + 0x100) /* 内部读写端口的当前工作状态 */ +#define CSR_AM_OOO_CFG_AM_ROB_ECC_INT_STS_REG \ + (CSR_AM_OOO_CFG_BASE + 0x104) /* Reorder Buffer所用Memory发生ECC错误中断状态 */ +#define CSR_AM_OOO_CFG_AM_ROB_ECC_INT_MASK_REG \ + (CSR_AM_OOO_CFG_BASE + 0x108) /* Reorder Buffer所用Memory发生ECC错误中断使能信号 */ +#define CSR_AM_OOO_CFG_AM_ROB_ECC_ERR_ADDR_REG \ + (CSR_AM_OOO_CFG_BASE + 0x10C) /* Reorder Buffer所用Memory发生ECC错误对应的地址 */ +#define CSR_AM_OOO_CFG_AM_CURR_MAX_RD_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x110) /* 指定内部端口读访问操作最大延迟 */ +#define CSR_AM_OOO_CFG_AM_CURR_AVA_RD_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x114) /* 指定内部端口读访问操作平均延迟 */ +#define CSR_AM_OOO_CFG_AM_CURR_RD_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x118) /* 读延迟实时状态 */ +#define CSR_AM_OOO_CFG_AM_CURR_MAX_WR_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x130) /* 指定内部端口写访问操作最大延迟 */ +#define CSR_AM_OOO_CFG_AM_CURR_AVA_WR_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x134) /* 指定内部端口写访问操作平均延迟 */ +#define CSR_AM_OOO_CFG_AM_CURR_WR_LATENCY_REG (CSR_AM_OOO_CFG_BASE + 0x138) /* 写完成延迟实时状态 */ +#define CSR_AM_OOO_CFG_AM_CURR_TRANS_RETURN_REG \ + (CSR_AM_OOO_CFG_BASE + 0x150) /* 读写通道发出的续写outstnading操作完成状态 */ +#define CSR_AM_OOO_CFG_AM_CURR_RD_MAX_TXID_REG (CSR_AM_OOO_CFG_BASE + 0x154) /* 读通道transaction ID的最大使用量 */ +#define CSR_AM_OOO_CFG_AM_CURR_WR_MAX_TXID_REG (CSR_AM_OOO_CFG_BASE + 0x158) /* 写通道transaction ID的最大使用量 */ +#define CSR_AM_OOO_CFG_AM_CURR_RD_TXID_STS_0_REG (CSR_AM_OOO_CFG_BASE + 0x160) /* 读方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_CURR_RD_TXID_STS_1_REG (CSR_AM_OOO_CFG_BASE + 0x164) /* 读方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_CURR_RD_TXID_STS_2_REG (CSR_AM_OOO_CFG_BASE + 0x168) /* 读方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_CURR_WR_TXID_STS_0_REG (CSR_AM_OOO_CFG_BASE + 0x170) /* 写方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_CURR_WR_TXID_STS_1_REG (CSR_AM_OOO_CFG_BASE + 0x174) /* 写方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_CURR_WR_TXID_STS_2_REG (CSR_AM_OOO_CFG_BASE + 0x178) /* 写方向各个transaction ID的空闲状态 \ + */ +#define CSR_AM_OOO_CFG_AM_ALARM_RRESP_REG (CSR_AM_OOO_CFG_BASE + 0x180) /* 读方向RESP出错告警信号 */ +#define CSR_AM_OOO_CFG_AM_ALARM_BRESP_REG (CSR_AM_OOO_CFG_BASE + 0x184) /* 写方向BRESP出错告警信号 */ + +/* HPRE_COMMON Base address of Module's Register */ +#define CSR_HPRE_COMMON_BASE (0xA000) + +/* **************************************************************************** */ +/* HPRE_COMMON Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HPRE_COMMON_HPRE_CNT_CLR_CE (CSR_HPRE_COMMON_BASE + 0x0) /* HPRE CNT CLR CE配置 */ +#define CSR_HPRE_COMMON_HPRE_CFG_AXQOS_REG (CSR_HPRE_COMMON_BASE + 0xC) /* HPRE AXI MASTER的AXQOS配置 */ +#define CSR_HPRE_COMMON_HPRE_CFG_AXCACHE_REG (CSR_HPRE_COMMON_BASE + 0x10) /* HPRE AXI MASTER的AXCACHE配置 */ +#define CSR_HPRE_COMMON_HPRE_CFG_RDCHN_INI_REG (CSR_HPRE_COMMON_BASE + 0x14) /* HPRE读通道SRAM初始化配置 */ +#define CSR_HPRE_COMMON_HPRE_CFG_AWUSER_FP_CFG_REG (CSR_HPRE_COMMON_BASE + 0x18) /* AW USER FP域段配置 */ +#define CSR_HPRE_COMMON_HPRE_CFG_BD_ENDIAN_REG (CSR_HPRE_COMMON_BASE + 0x20) /* 输入/输出BD的大小端配置 */ +#define CSR_HPRE_COMMON_HPRE_ECC_BYPASS_REG (CSR_HPRE_COMMON_BASE + 0x24) /* SRAM ECC校验旁路控制寄存器 */ +#define CSR_HPRE_COMMON_HPRE_RAS_INT_WIDTH_CFG_REG (CSR_HPRE_COMMON_BASE + 0x28) /* RAS中断脉冲宽度配置寄存器 */ +#define CSR_HPRE_COMMON_HPRE_POISON_BYPASS_REG (CSR_HPRE_COMMON_BASE + 0x2C) /* AXI MASTER读写污染域屏蔽配置寄存器 */ +#define CSR_HPRE_COMMON_HPRE_BD_ARUSER_CFG_REG (CSR_HPRE_COMMON_BASE + 0x30) /* 模块读BD的AR USER属性配置寄存器。 */ +#define CSR_HPRE_COMMON_HPRE_BD_AWUSER_CFG_REG (CSR_HPRE_COMMON_BASE + 0x34) /* 模块写BD的AW USER属性配置寄存器。 */ +#define CSR_HPRE_COMMON_HPRE_TYPES_ENB_REG (CSR_HPRE_COMMON_BASE + 0x38) /* 任务类型使能 */ +#define CSR_HPRE_COMMON_HPRE_DATA_ARUSER_CFG_REG (CSR_HPRE_COMMON_BASE + 0x3C) /* 模块读数据的AR USER属性配置寄存器。 \ + */ +#define CSR_HPRE_COMMON_HPRE_DATA_AWUSER_CFG_REG (CSR_HPRE_COMMON_BASE + 0x40) /* 模块写数据的AW USER属性配置寄存器。 \ + */ +#define CSR_HPRE_COMMON_HPRE_AM_OOO_SHUTDOWN_ENB_REG (CSR_HPRE_COMMON_BASE + 0x44) /* HPRE的AM OOO关闭使能 */ +#define CSR_HPRE_COMMON_HPRE_HAC_INT_MSK_REG \ + (CSR_HPRE_COMMON_BASE + 0x400) /* HPRE HAC中断的屏蔽寄存器(不包含QM的中断) */ +#define CSR_HPRE_COMMON_HPRE_RAS_ECC1BIT_TH_REG (CSR_HPRE_COMMON_BASE + 0x40C) /* ECC1bit错误上报阈值配置 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_CE_ENB_REG (CSR_HPRE_COMMON_BASE + 0x410) /* HPRE HAC中断上报RAS CE中断使能 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_NFE_ENB_REG (CSR_HPRE_COMMON_BASE + 0x414) /* HPRE HAC中断上报RAS NFE中断使能 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_FE_ENB_REG (CSR_HPRE_COMMON_BASE + 0x418) /* HPRE HAC中断上报RAS FE中断使能 */ +#define CSR_HPRE_COMMON_HPRE_HAC_INT_SET_REG (CSR_HPRE_COMMON_BASE + 0x500) /* HPRE_HAC_RINT置位寄存器 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RINT_REG (CSR_HPRE_COMMON_BASE + 0x600) /* HPRE HAC原始中断 */ +#define CSR_HPRE_COMMON_HPRE_HAC_INT_ST_REG (CSR_HPRE_COMMON_BASE + 0x800) /* HPRE HAC中断状态 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_AFULL_HIS1_REG \ + (CSR_HPRE_COMMON_BASE + 0x810) /* FIFO曾经出现将满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_AFULL_HIS2_REG \ + (CSR_HPRE_COMMON_BASE + 0x814) /* FIFO曾经出现将满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_AFULL_HIS3_REG \ + (CSR_HPRE_COMMON_BASE + 0x818) /* FIFO曾经出现将满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_FULL_HIS1_REG \ + (CSR_HPRE_COMMON_BASE + 0x840) /* FIFO曾经出现满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_FULL_HIS2_REG \ + (CSR_HPRE_COMMON_BASE + 0x844) /* FIFO曾经出现满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_FULL_HIS3_REG \ + (CSR_HPRE_COMMON_BASE + 0x848) /* FIFO曾经出现满的记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_EMPTY_ST1_REG \ + (CSR_HPRE_COMMON_BASE + 0x880) /* FIFO空状态记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_EMPTY_ST2_REG \ + (CSR_HPRE_COMMON_BASE + 0x884) /* FIFO空状态记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_FIFO_EMPTY_ST3_REG \ + (CSR_HPRE_COMMON_BASE + 0x888) /* FIFO空状态记录，这是一个FPGA版本DFX寄存器，只在FPGA版本有效。 */ +#define CSR_HPRE_COMMON_HPRE_MEM_EBIT_INJ_EN_REG \ + (CSR_HPRE_COMMON_BASE + 0x900) /* HPRE读通道和QMV2内部 MEM故障注入使能 */ +#define CSR_HPRE_COMMON_HPRE_MEM_EBIT_INJ_REG (CSR_HPRE_COMMON_BASE + 0x904) /* HPRE读通道和QMV2内部 MEM故障注入 */ +#define CSR_HPRE_COMMON_HPRE_QMV2_MEM_ERR_ADDR_REG (CSR_HPRE_COMMON_BASE + 0x908) /* HPRE的QMV2内部MEM出错地址记录 */ +#define CSR_HPRE_COMMON_HPRE_CLKGATE_ENB_REG (CSR_HPRE_COMMON_BASE + 0x90C) /* HPRE算法核动态门控使能 */ +#define CSR_HPRE_COMMON_HPRE_CRYPT_DO_CRT_REG (CSR_HPRE_COMMON_BASE + 0x910) /* HPRE输出端口信用值 */ +#define CSR_HPRE_COMMON_HPRE_INT_VECTOR_REG (CSR_HPRE_COMMON_BASE + 0x914) /* HPRE中断向量 */ +#define CSR_HPRE_COMMON_HPRE_INT_REG (CSR_HPRE_COMMON_BASE + 0x918) /* HPRE中断状态 */ +#define CSR_HPRE_COMMON_HPRE_INT_EN_REG (CSR_HPRE_COMMON_BASE + 0x91C) /* HPRE中断屏蔽 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_CE_ERR_REG (CSR_HPRE_COMMON_BASE + 0x920) /* HPRE加速器CE中断 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_FE_ERR_REG (CSR_HPRE_COMMON_BASE + 0x924) /* HPRE加速器FE中断 */ +#define CSR_HPRE_COMMON_HPRE_HAC_RAS_NFE_ERR_REG (CSR_HPRE_COMMON_BASE + 0x928) /* HPRE加速器NFE中断 */ +#define CSR_HPRE_COMMON_INT_SRAM_ERR_REG (CSR_HPRE_COMMON_BASE + 0x92C) /* SRAM中断 */ +#define CSR_HPRE_COMMON_HPRE_DI_FSM_TIMEOUT_ERR_REG (CSR_HPRE_COMMON_BASE + 0x930) /* DI状态机超时 */ +#define CSR_HPRE_COMMON_HPRE_DO_FSM_TIMEOUT_ERR_REG (CSR_HPRE_COMMON_BASE + 0x934) /* DO状态机超时 */ +#define CSR_HPRE_COMMON_HPRE_DIDO_ERR_INFO_REG (CSR_HPRE_COMMON_BASE + 0x938) /* di/do曾出现异常信息 */ +#define CSR_HPRE_COMMON_HPRE_FSM_SHB_CFG_REG (CSR_HPRE_COMMON_BASE + 0x93C) /* 智能心跳上限配置 */ +#define CSR_HPRE_COMMON_HPRE_MEM_CTRL_0_REG (CSR_HPRE_COMMON_BASE + 0x940) /* HPRE中MEM_CTRL寄存器0 */ +#define CSR_HPRE_COMMON_HPRE_MEM_CTRL_1_REG (CSR_HPRE_COMMON_BASE + 0x944) /* HPRE中MEM_CTRL寄存器1 */ +#define CSR_HPRE_COMMON_HPRE_MEM_CTRL_2_REG (CSR_HPRE_COMMON_BASE + 0x948) /* HPRE中MEM_CTRL寄存器2 */ +#define CSR_HPRE_COMMON_HPRE_MEM_CTRL_3_REG (CSR_HPRE_COMMON_BASE + 0x94C) /* HPRE中MEM_CTRL寄存器3 */ +#define CSR_HPRE_COMMON_HPRE_MEM_CTRL_4_REG (CSR_HPRE_COMMON_BASE + 0x950) /* HPRE中MEM_CTRL寄存器4 */ +#define CSR_HPRE_COMMON_HPRE_RDCHN_INI_ST_REG (CSR_HPRE_COMMON_BASE + 0xA00) /* HPRE 读数据通道 SRAM初始化状态 */ +#define CSR_HPRE_COMMON_HPRE_ECC1BIT_ERR_CNT_REG (CSR_HPRE_COMMON_BASE + 0xA04) /* Memory出现ECC1bit错误统计寄存器。 \ + */ +#define CSR_HPRE_COMMON_HPRE_ECC2BIT_ERR_CNT_REG (CSR_HPRE_COMMON_BASE + 0xA08) /* Memory出现ECC2bit错误统计寄存器。 \ + */ +#define CSR_HPRE_COMMON_HPRE_PEH_ECO1_REG (CSR_HPRE_COMMON_BASE + 0xA10) /* PEH ECO寄存器组1 */ +#define CSR_HPRE_COMMON_HPRE_PEH_ECO2_REG (CSR_HPRE_COMMON_BASE + 0xA14) /* PEH ECO寄存器组2 */ +#define CSR_HPRE_COMMON_HPRE_PEH_ECO3_REG (CSR_HPRE_COMMON_BASE + 0xA18) /* PEH ECO寄存器组3 */ +#define CSR_HPRE_COMMON_HPRE_PEH_ECO4_REG (CSR_HPRE_COMMON_BASE + 0xA1C) /* PEH ECO寄存器组4 */ +#define CSR_HPRE_COMMON_HPRE_PEH_ECO5_REG (CSR_HPRE_COMMON_BASE + 0xA20) /* PEH ECO寄存器组5 */ +#define CSR_HPRE_COMMON_HPRE_ECO1_REG (CSR_HPRE_COMMON_BASE + 0xA24) /* ECO寄存器1 */ +#define CSR_HPRE_COMMON_HPRE_ECO2_REG (CSR_HPRE_COMMON_BASE + 0xA28) /* ECO寄存器2 */ +#define CSR_HPRE_COMMON_HPRE_ECO3_REG (CSR_HPRE_COMMON_BASE + 0xA2C) /* ECO寄存器3 */ +#define CSR_HPRE_COMMON_HPRE_ECO4_REG (CSR_HPRE_COMMON_BASE + 0xA30) /* ECO寄存器4 */ + +/* HPRE_CLUSTER1 Base address of Module's Register */ +#define CSR_HPRE_CLUSTER1_BASE (0xB000) +/* HPRE_CLUSTER2 Base address of Module's Register */ +#define CSR_HPRE_CLUSTER2_BASE (0xC000) +/* HPRE_CLUSTER3 Base address of Module's Register */ +#define CSR_HPRE_CLUSTER3_BASE (0xD000) +/* HPRE_CLUSTER4 Base address of Module's Register */ +#define CSR_HPRE_CLUSTER4_BASE (0xE000) + +/* **************************************************************************** */ +/* HPRE_CLUSTER Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_HPRE_CLUSTER_HPRE_CORE_ENB_REG(base_addr) ((base_addr) + 0x4) /* HPRE算法核使能 */ +#define CSR_HPRE_CLUSTER_HPRE_CLUSTER_DYN_ENB_REG(base_addr) ((base_addr) + 0x10) /* HPRE CLUSTER动态时钟门控使能 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_INI_CFG_REG(base_addr) ((base_addr) + 0x20) /* HPRE算法核初始化配置使能 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_INI_STATUS_REG(base_addr) ((base_addr) + 0x80) /* HPRE算法核memory初始化状态查询 */ +#define CSR_HPRE_CLUSTER_HPRE_ERR_BIT_INJECT_EN_REG(base_addr) ((base_addr) + 0x84) /* SRAM故障注入使能 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_SHB_CFG_REG(base_addr) ((base_addr) + 0x88) /* 智能心跳上限配置 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_SHB_ST_REG(base_addr) ((base_addr) + 0x8C) /* 算法核智能心跳状态查询 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_IDLE_ST_REG(base_addr) ((base_addr) + 0x90) /* CLUSTER算法核空闲状态查询 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_STATUS_INQUIRE_REG(base_addr) ((base_addr) + 0x100) /* HPRE算法核状态查询 */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_STATUS_RESULT_REG(base_addr) \ + ((base_addr) + 0x104) /* HPRE算法核状态数据返回（考虑到数据返回有延迟，配置完HPRE_CORE_STATUS_INQUIRE后，需要等待若干HPRE周期后(10个HPRE周期，约10ns)，再去查询本寄存器的值） \ + */ +#define CSR_HPRE_CLUSTER_HPRE_CORE_ERR_BIT_INJECT_REG(base_addr) ((base_addr) + 0x108) + +#endif // CRYPTO_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_c_union_define.h new file mode 100644 index 000000000..ccc021ecf --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_c_union_define.h @@ -0,0 +1,1340 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : esch_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/12/11 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/12/11 20:09:30 Create file +// ****************************************************************************** + +#ifndef ESCH_C_UNION_DEFINE_H +#define ESCH_C_UNION_DEFINE_H + +/* Define the union csr_esch_cos_ch_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_ch_map_link : 6; /* [5:0] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_cos_ch_map_u; + +/* Define the union csr_esch_mem_cfg_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_ok : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mem_cfg_ok_u; + +/* Define the union csr_esch_ppop_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_q_bp_mask : 1; /* [0] */ + u32 rsv_2 : 3; /* [3:1] */ + u32 eps_q_grp_csr_cfg : 7; /* [10:4] */ + u32 rsv_3 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_ppop_bp_cfg_u; + +/* Define the union csr_esch_ppop_bp_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_q_grp_bp_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_ppop_bp_st_u; + +/* Define the union csr_esch_lb_prm_bp_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_lb_cos_map : 6; /* [5:0] */ + u32 rsv_4 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_lb_prm_bp_map_u; + +/* Define the union csr_esch_host_fifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_host_fifo_th : 5; /* [4:0] */ + u32 rsv_5 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_host_fifo_th_u; + +/* Define the union csr_esch_hostlb_fifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_host_lb_fifo_th : 5; /* [4:0] */ + u32 rsv_6 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hostlb_fifo_th_u; + +/* Define the union csr_esch_net_fifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_net_fifo_th : 5; /* [4:0] */ + u32 rsv_7 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_net_fifo_th_u; + +/* Define the union csr_esch_netlb_fifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_net_lb_fifo_th : 5; /* [4:0] */ + u32 rsv_8 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_netlb_fifo_th_u; + +/* Define the union csr_esch_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_init_start : 1; /* [0] */ + u32 mem_power_ctrl : 3; /* [3:1] */ + u32 mem_timing_ctrl : 7; /* [10:4] */ + u32 mem_ecc_enable : 1; /* [11] */ + u32 mem_init_done : 1; /* [12] */ + u32 rsv_9 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mem_ctrl_u; + +/* Define the union csr_esch_mem_err_req0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_ram_err_req0 : 16; /* [15:0] */ + u32 eps_ram_err_req1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mem_err_req0_u; + +/* Define the union csr_esch_mem_err_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_ram_err_req4 : 2; /* [1:0] */ + u32 eps_ram_err_req3 : 2; /* [3:2] */ + u32 eps_ram_err_req2 : 2; /* [5:4] */ + u32 hps_ram_err_req2 : 2; /* [7:6] */ + u32 hps_ram_err_req1 : 2; /* [9:8] */ + u32 hps_ram_err_req0 : 2; /* [11:10] */ + u32 rsv_10 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mem_err_req1_u; + +/* Define the union csr_esch_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_11 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_12 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int_vector_u; + +/* Define the union csr_esch_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_13 : 10; /* [15:6] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int_u; + +/* Define the union csr_esch_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 6; /* [5:0] */ + u32 rsv_14 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int_en_u; + +/* Define the union csr_esch_int0_sticky0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esch_mem_err0 : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 esch_int0_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int0_sticky0_u; + +/* Define the union csr_esch_int0_sticky1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esch_mem_err1 : 1; /* [0] */ + u32 int_insrt1 : 1; /* [1] */ + u32 esch_int1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int0_sticky1_u; + +/* Define the union csr_esch_int0_sticky2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 esch_fifo_err : 1; /* [0] */ + u32 int_insrt2 : 1; /* [1] */ + u32 esch_int2_sticky : 4; /* [5:2] */ + u32 rsv_15 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_int0_sticky2_u; + +/* Define the union csr_esch_fcnp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fcnp_ref_size_cfg : 10; /* [9:0] */ + u32 rsv_16 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_fcnp_cfg_u; + +/* Define the union csr_esch_cpb_ch_cdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_chan_credit : 5; /* [4:0] */ + u32 cpb_chan_id : 6; /* [10:5] */ + u32 cpb_chan_type : 3; /* [13:11] */ + u32 rsv_17 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_cpb_ch_cdt_cfg_u; + +/* Define the union csr_esch_hps_nml_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_normal_cos_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_nml_cos_bp_u; + +/* Define the union csr_esch_hps_up_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_mpu_bp : 1; /* [0] */ + u32 hps_spu_cos_bp : 8; /* [8:1] */ + u32 rsv_18 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_up_bp_u; + +/* Define the union csr_esch_hps_lb_cos_high_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_cos_high_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_cos_high_bp_u; + +/* Define the union csr_esch_hps_lb_cos_low_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_cos_low_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_cos_low_bp_u; + +/* Define the union csr_esch_eps_cos_high_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_high_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_eps_cos_high_bp_u; + +/* Define the union csr_esch_eps_cos_low_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_low_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_eps_cos_low_bp_u; + +/* Define the union csr_esch_eps_lb_type_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_type_bp : 3; /* [2:0] */ + u32 rsv_19 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_eps_lb_type_bp_u; + +/* Define the union csr_esch_mag_high_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_esch_chan_bp_high32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mag_high_cos_bp_u; + +/* Define the union csr_esch_mag_low_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_esch_chan_bp_low32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_mag_low_cos_bp_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_esch_cos_ch_map_u esch_cos_ch_map[40]; /* 0 */ + volatile csr_esch_mem_cfg_ok_u esch_mem_cfg_ok; /* A0 */ + volatile csr_esch_ppop_bp_cfg_u esch_ppop_bp_cfg; /* A4 */ + volatile csr_esch_ppop_bp_st_u esch_ppop_bp_st; /* A8 */ + volatile csr_esch_lb_prm_bp_map_u esch_lb_prm_bp_map[192]; /* 100 */ + volatile csr_esch_host_fifo_th_u esch_host_fifo_th[33]; /* 400 */ + volatile csr_esch_hostlb_fifo_th_u esch_hostlb_fifo_th[64]; /* 500 */ + volatile csr_esch_net_fifo_th_u esch_net_fifo_th[64]; /* 600 */ + volatile csr_esch_netlb_fifo_th_u esch_netlb_fifo_th[3]; /* 700 */ + volatile csr_esch_mem_ctrl_u esch_mem_ctrl; /* 750 */ + volatile csr_esch_mem_err_req0_u esch_mem_err_req0; /* 754 */ + volatile csr_esch_mem_err_req1_u esch_mem_err_req1; /* 758 */ + volatile csr_esch_int_vector_u esch_int_vector; /* 760 */ + volatile csr_esch_int_u esch_int; /* 764 */ + volatile csr_esch_int_en_u esch_int_en; /* 768 */ + volatile csr_esch_int0_sticky0_u esch_int0_sticky0; /* 76C */ + volatile csr_esch_int0_sticky1_u esch_int0_sticky1; /* 770 */ + volatile csr_esch_int0_sticky2_u esch_int0_sticky2; /* 774 */ + volatile csr_esch_fcnp_cfg_u esch_fcnp_cfg; /* 778 */ + volatile csr_esch_cpb_ch_cdt_cfg_u esch_cpb_ch_cdt_cfg; /* 77C */ + volatile csr_esch_hps_nml_cos_bp_u esch_hps_nml_cos_bp; /* 780 */ + volatile csr_esch_hps_up_bp_u esch_hps_up_bp; /* 784 */ + volatile csr_esch_hps_lb_cos_high_bp_u esch_hps_lb_cos_high_bp; /* 788 */ + volatile csr_esch_hps_lb_cos_low_bp_u esch_hps_lb_cos_low_bp; /* 78C */ + volatile csr_esch_eps_cos_high_bp_u esch_eps_cos_high_bp; /* 790 */ + volatile csr_esch_eps_cos_low_bp_u esch_eps_cos_low_bp; /* 794 */ + volatile csr_esch_eps_lb_type_bp_u esch_eps_lb_type_bp; /* 79C */ + volatile csr_esch_mag_high_cos_bp_u esch_mag_high_cos_bp; /* 7A0 */ + volatile csr_esch_mag_low_cos_bp_u esch_mag_low_cos_bp; /* 7A4 */ +} S_esch_top_csr_REGS_TYPE; + +/* Declare the struct pointor of the module esch_top_csr */ +extern volatile S_esch_top_csr_REGS_TYPE *gopesch_top_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetESCH_COS_CH_MAP_cos_ch_map_link(unsigned int ucos_ch_map_link); +int iSetESCH_MEM_CFG_OK_cfg_ok(unsigned int ucfg_ok); +int iSetESCH_PPOP_BP_CFG_eps_q_bp_mask(unsigned int ueps_q_bp_mask); +int iSetESCH_PPOP_BP_CFG_eps_q_grp_csr_cfg(unsigned int ueps_q_grp_csr_cfg); +int iSetESCH_PPOP_BP_ST_eps_q_grp_bp_st(unsigned int ueps_q_grp_bp_st); +int iSetESCH_LB_PRM_BP_MAP_prm_lb_cos_map(unsigned int uprm_lb_cos_map); +int iSetESCH_HOST_FIFO_TH_cpb_host_fifo_th(unsigned int ucpb_host_fifo_th); +int iSetESCH_HOSTLB_FIFO_TH_cpb_host_lb_fifo_th(unsigned int ucpb_host_lb_fifo_th); +int iSetESCH_NET_FIFO_TH_cpb_net_fifo_th(unsigned int ucpb_net_fifo_th); +int iSetESCH_NETLB_FIFO_TH_cpb_net_lb_fifo_th(unsigned int ucpb_net_lb_fifo_th); +int iSetESCH_MEM_CTRL_mem_init_start(unsigned int umem_init_start); +int iSetESCH_MEM_CTRL_mem_power_ctrl(unsigned int umem_power_ctrl); +int iSetESCH_MEM_CTRL_mem_timing_ctrl(unsigned int umem_timing_ctrl); +int iSetESCH_MEM_CTRL_mem_ecc_enable(unsigned int umem_ecc_enable); +int iSetESCH_MEM_CTRL_mem_init_done(unsigned int umem_init_done); +int iSetESCH_MEM_ERR_REQ0_eps_ram_err_req0(unsigned int ueps_ram_err_req0); +int iSetESCH_MEM_ERR_REQ0_eps_ram_err_req1(unsigned int ueps_ram_err_req1); +int iSetESCH_MEM_ERR_REQ1_eps_ram_err_req4(unsigned int ueps_ram_err_req4); +int iSetESCH_MEM_ERR_REQ1_eps_ram_err_req3(unsigned int ueps_ram_err_req3); +int iSetESCH_MEM_ERR_REQ1_eps_ram_err_req2(unsigned int ueps_ram_err_req2); +int iSetESCH_MEM_ERR_REQ1_hps_ram_err_req2(unsigned int uhps_ram_err_req2); +int iSetESCH_MEM_ERR_REQ1_hps_ram_err_req1(unsigned int uhps_ram_err_req1); +int iSetESCH_MEM_ERR_REQ1_hps_ram_err_req0(unsigned int uhps_ram_err_req0); +int iSetESCH_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetESCH_INT_VECTOR_enable(unsigned int uenable); +int iSetESCH_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetESCH_INT_int_data(unsigned int uint_data); +int iSetESCH_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetESCH_INT_EN_int_en(unsigned int uint_en); +int iSetESCH_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetESCH_INT0_STICKY0_esch_mem_err0(unsigned int uesch_mem_err0); +int iSetESCH_INT0_STICKY0_int_insrt0(unsigned int uint_insrt0); +int iSetESCH_INT0_STICKY0_esch_int0_sticky(unsigned int uesch_int0_sticky); +int iSetESCH_INT0_STICKY1_esch_mem_err1(unsigned int uesch_mem_err1); +int iSetESCH_INT0_STICKY1_int_insrt1(unsigned int uint_insrt1); +int iSetESCH_INT0_STICKY1_esch_int1_sticky(unsigned int uesch_int1_sticky); +int iSetESCH_INT0_STICKY2_esch_fifo_err(unsigned int uesch_fifo_err); +int iSetESCH_INT0_STICKY2_int_insrt2(unsigned int uint_insrt2); +int iSetESCH_INT0_STICKY2_esch_int2_sticky(unsigned int uesch_int2_sticky); +int iSetESCH_FCNP_CFG_fcnp_ref_size_cfg(unsigned int ufcnp_ref_size_cfg); +int iSetESCH_CPB_CH_CDT_CFG_cpb_chan_credit(unsigned int ucpb_chan_credit); +int iSetESCH_CPB_CH_CDT_CFG_cpb_chan_id(unsigned int ucpb_chan_id); +int iSetESCH_CPB_CH_CDT_CFG_cpb_chan_type(unsigned int ucpb_chan_type); +int iSetESCH_HPS_NML_COS_BP_hps_normal_cos_bp(unsigned int uhps_normal_cos_bp); +int iSetESCH_HPS_UP_BP_hps_mpu_bp(unsigned int uhps_mpu_bp); +int iSetESCH_HPS_UP_BP_hps_spu_cos_bp(unsigned int uhps_spu_cos_bp); +int iSetESCH_HPS_LB_COS_HIGH_BP_hps_lb_cos_high_bp(unsigned int uhps_lb_cos_high_bp); +int iSetESCH_HPS_LB_COS_LOW_BP_hps_lb_cos_low_bp(unsigned int uhps_lb_cos_low_bp); +int iSetESCH_EPS_COS_HIGH_BP_eps_cos_high_bp(unsigned int ueps_cos_high_bp); +int iSetESCH_EPS_COS_LOW_BP_eps_cos_low_bp(unsigned int ueps_cos_low_bp); +int iSetESCH_EPS_LB_TYPE_BP_eps_lb_type_bp(unsigned int ueps_lb_type_bp); +int iSetESCH_MAG_HIGH_COS_BP_mag_esch_chan_bp_high32(unsigned int umag_esch_chan_bp_high32); +int iSetESCH_MAG_LOW_COS_BP_mag_esch_chan_bp_low32(unsigned int umag_esch_chan_bp_low32); + +/* Define the union csr_eps_q_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_q_indrect_addr : 24; /* [23:0] */ + u32 eps_q_indrect_tab : 4; /* [27:24] */ + u32 eps_q_indrect_stat : 2; /* [29:28] */ + u32 eps_q_indrect_mode : 1; /* [30] */ + u32 eps_q_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_q_indrect_ctrl_u; + +/* Define the union csr_eps_q_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_q_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_q_indrect_timeout_u; + +/* Define the union csr_eps_q_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_q_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_q_indrect_data_u; + +/* Define the union csr_eps_cos_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_indrect_addr : 24; /* [23:0] */ + u32 eps_cos_indrect_tab : 4; /* [27:24] */ + u32 eps_cos_indrect_stat : 2; /* [29:28] */ + u32 eps_cos_indrect_mode : 1; /* [30] */ + u32 eps_cos_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_cos_indrect_ctrl_u; + +/* Define the union csr_eps_cos_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_cos_indrect_timeout_u; + +/* Define the union csr_eps_cos_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_cos_indrect_data_u; + +/* Define the union csr_eps_tc_p_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_tc_p_indrect_addr : 24; /* [23:0] */ + u32 eps_tc_p_indrect_tab : 4; /* [27:24] */ + u32 eps_tc_p_indrect_stat : 2; /* [29:28] */ + u32 eps_tc_p_indrect_mode : 1; /* [30] */ + u32 eps_tc_p_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_tc_p_indrect_ctrl_u; + +/* Define the union csr_eps_tc_p_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_tc_p_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_tc_p_indrect_timeout_u; + +/* Define the union csr_eps_tc_p_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_tc_p_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_tc_p_indrect_data_u; + +/* Define the union csr_eps_lb_q_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_q_indrect_addr : 24; /* [23:0] */ + u32 eps_lb_q_indrect_tab : 4; /* [27:24] */ + u32 eps_lb_q_indrect_stat : 2; /* [29:28] */ + u32 eps_lb_q_indrect_mode : 1; /* [30] */ + u32 eps_lb_q_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_q_indrect_ctrl_u; + +/* Define the union csr_eps_lb_q_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_q_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_q_indrect_timeout_u; + +/* Define the union csr_eps_lb_q_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_q_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_q_indrect_data_u; + +/* Define the union csr_eps_lb_p_t_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_p_t_indrect_addr : 24; /* [23:0] */ + u32 eps_lb_p_t_indrect_tab : 4; /* [27:24] */ + u32 eps_lb_p_t_indrect_stat : 2; /* [29:28] */ + u32 eps_lb_p_t_indrect_mode : 1; /* [30] */ + u32 eps_lb_p_t_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_p_t_indrect_ctrl_u; + +/* Define the union csr_eps_lb_p_t_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_p_t_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_p_t_indrect_timeout_u; + +/* Define the union csr_eps_lb_p_t_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_p_t_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_p_t_indrect_data_u; + +/* Define the union csr_eps_p_soft_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_port_soft_bp_cfg : 8; /* [7:0] */ + u32 rsv_0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_p_soft_bp_cfg_u; + +/* Define the union csr_eps_cos_bp_en0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_bp_en_p0 : 8; /* [7:0] */ + u32 eps_cos_bp_en_p1 : 8; /* [15:8] */ + u32 eps_cos_bp_en_p2 : 8; /* [23:16] */ + u32 eps_cos_bp_en_p3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_cos_bp_en0_u; + +/* Define the union csr_eps_cos_bp_en1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_cos_bp_en_p4 : 8; /* [7:0] */ + u32 eps_cos_bp_en_p5 : 8; /* [15:8] */ + u32 eps_cos_bp_en_p6 : 8; /* [23:16] */ + u32 eps_cos_bp_en_p7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_cos_bp_en1_u; + +/* Define the union csr_eps_bp_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_bp_mode : 8; /* [7:0] */ + u32 eps_rw_rsv0 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_bp_mode_u; + +/* Define the union csr_eps_root_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_port_grp_cir_cfg : 25; /* [24:0] */ + u32 rsv_1 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_root_cir_cfg_u; + +/* Define the union csr_eps_lb_root_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_cir_cfg : 25; /* [24:0] */ + u32 rsv_2 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_root_cir_cfg_u; + +/* Define the union csr_eps_all_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_all_cir_cfg : 25; /* [24:0] */ + u32 rsv_3 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_all_cir_cfg_u; + +/* Define the union csr_eps_root_cir_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_root_cir_cnt : 26; /* [25:0] */ + u32 rsv_4 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_root_cir_cnt_u; + +/* Define the union csr_eps_lb_root_cir_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_root_cir_cnt : 26; /* [25:0] */ + u32 rsv_5 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_root_cir_cnt_u; + +/* Define the union csr_eps_root_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_root_wgt_cfg : 24; /* [23:0] */ + u32 rsv_6 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_root_wgt_cfg_u; + +/* Define the union csr_eps_nml_root_wgt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_nml_root_wgt_cnt : 25; /* [24:0] */ + u32 rsv_7 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_nml_root_wgt_cnt_u; + +/* Define the union csr_eps_lb_root_wgt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_lb_root_wgt_cnt : 25; /* [24:0] */ + u32 rsv_8 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_lb_root_wgt_cnt_u; + +/* Define the union csr_eps_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_mem_ecc_err0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_ecc_1bit_err_cnt_u; + +/* Define the union csr_eps_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_mem_ecc_err1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_ecc_2bit_err_cnt_u; + +/* Define the union csr_eps_dqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_dqs_rec : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_dqs_cnt_u; + +/* Define the union csr_eps_eqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_eqs_rec : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_eqs_cnt_u; + +/* Define the union csr_eps_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eps_fifo_cnt : 4; /* [3:0] */ + u32 rsv_9 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_fifo_cnt_u; + +/* Define the union csr_eps_inner_err_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sel_queue_err : 1; /* [0] */ + u32 dqs_qid_err : 1; /* [1] */ + u32 dqs_over_err : 1; /* [2] */ + u32 dqs_late_err : 1; /* [3] */ + u32 rsv_10 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eps_inner_err_st_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_eps_q_indrect_ctrl_u eps_q_indrect_ctrl; /* 0 */ + volatile csr_eps_q_indrect_timeout_u eps_q_indrect_timeout; /* 4 */ + volatile csr_eps_q_indrect_data_u eps_q_indrect_data; /* 8 */ + volatile csr_eps_cos_indrect_ctrl_u eps_cos_indrect_ctrl; /* 10 */ + volatile csr_eps_cos_indrect_timeout_u eps_cos_indrect_timeout; /* 14 */ + volatile csr_eps_cos_indrect_data_u eps_cos_indrect_data; /* 18 */ + volatile csr_eps_tc_p_indrect_ctrl_u eps_tc_p_indrect_ctrl; /* 20 */ + volatile csr_eps_tc_p_indrect_timeout_u eps_tc_p_indrect_timeout; /* 24 */ + volatile csr_eps_tc_p_indrect_data_u eps_tc_p_indrect_data; /* 28 */ + volatile csr_eps_lb_q_indrect_ctrl_u eps_lb_q_indrect_ctrl; /* 30 */ + volatile csr_eps_lb_q_indrect_timeout_u eps_lb_q_indrect_timeout; /* 34 */ + volatile csr_eps_lb_q_indrect_data_u eps_lb_q_indrect_data; /* 38 */ + volatile csr_eps_lb_p_t_indrect_ctrl_u eps_lb_p_t_indrect_ctrl; /* 40 */ + volatile csr_eps_lb_p_t_indrect_timeout_u eps_lb_p_t_indrect_timeout; /* 44 */ + volatile csr_eps_lb_p_t_indrect_data_u eps_lb_p_t_indrect_data; /* 48 */ + volatile csr_eps_p_soft_bp_cfg_u eps_p_soft_bp_cfg; /* 50 */ + volatile csr_eps_cos_bp_en0_u eps_cos_bp_en0; /* 54 */ + volatile csr_eps_cos_bp_en1_u eps_cos_bp_en1; /* 58 */ + volatile csr_eps_bp_mode_u eps_bp_mode; /* 5C */ + volatile csr_eps_root_cir_cfg_u eps_root_cir_cfg; /* 60 */ + volatile csr_eps_lb_root_cir_cfg_u eps_lb_root_cir_cfg; /* 64 */ + volatile csr_eps_all_cir_cfg_u eps_all_cir_cfg; /* 68 */ + volatile csr_eps_root_cir_cnt_u eps_root_cir_cnt; /* 6C */ + volatile csr_eps_lb_root_cir_cnt_u eps_lb_root_cir_cnt; /* 70 */ + volatile csr_eps_root_wgt_cfg_u eps_root_wgt_cfg; /* 78 */ + volatile csr_eps_nml_root_wgt_cnt_u eps_nml_root_wgt_cnt; /* 80 */ + volatile csr_eps_lb_root_wgt_cnt_u eps_lb_root_wgt_cnt; /* 84 */ + volatile csr_eps_ecc_1bit_err_cnt_u eps_ecc_1bit_err_cnt; /* 100 */ + volatile csr_eps_ecc_2bit_err_cnt_u eps_ecc_2bit_err_cnt; /* 104 */ + volatile csr_eps_dqs_cnt_u eps_dqs_cnt; /* 108 */ + volatile csr_eps_eqs_cnt_u eps_eqs_cnt; /* 10C */ + volatile csr_eps_fifo_cnt_u eps_fifo_cnt; /* 110 */ + volatile csr_eps_inner_err_st_u eps_inner_err_st; /* 114 */ +} S_esch_eps_csr_REGS_TYPE; + +/* Declare the struct pointor of the module esch_eps_csr */ +extern volatile S_esch_eps_csr_REGS_TYPE *gopesch_eps_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetEPS_Q_INDRECT_CTRL_eps_q_indrect_addr(unsigned int ueps_q_indrect_addr); +int iSetEPS_Q_INDRECT_CTRL_eps_q_indrect_tab(unsigned int ueps_q_indrect_tab); +int iSetEPS_Q_INDRECT_CTRL_eps_q_indrect_stat(unsigned int ueps_q_indrect_stat); +int iSetEPS_Q_INDRECT_CTRL_eps_q_indrect_mode(unsigned int ueps_q_indrect_mode); +int iSetEPS_Q_INDRECT_CTRL_eps_q_indrect_vld(unsigned int ueps_q_indrect_vld); +int iSetEPS_Q_INDRECT_TIMEOUT_eps_q_indrect_timeout(unsigned int ueps_q_indrect_timeout); +int iSetEPS_Q_INDRECT_DATA_eps_q_indrect_data(unsigned int ueps_q_indrect_data); +int iSetEPS_COS_INDRECT_CTRL_eps_cos_indrect_addr(unsigned int ueps_cos_indrect_addr); +int iSetEPS_COS_INDRECT_CTRL_eps_cos_indrect_tab(unsigned int ueps_cos_indrect_tab); +int iSetEPS_COS_INDRECT_CTRL_eps_cos_indrect_stat(unsigned int ueps_cos_indrect_stat); +int iSetEPS_COS_INDRECT_CTRL_eps_cos_indrect_mode(unsigned int ueps_cos_indrect_mode); +int iSetEPS_COS_INDRECT_CTRL_eps_cos_indrect_vld(unsigned int ueps_cos_indrect_vld); +int iSetEPS_COS_INDRECT_TIMEOUT_eps_cos_indrect_timeout(unsigned int ueps_cos_indrect_timeout); +int iSetEPS_COS_INDRECT_DATA_eps_cos_indrect_data(unsigned int ueps_cos_indrect_data); +int iSetEPS_TC_P_INDRECT_CTRL_eps_tc_p_indrect_addr(unsigned int ueps_tc_p_indrect_addr); +int iSetEPS_TC_P_INDRECT_CTRL_eps_tc_p_indrect_tab(unsigned int ueps_tc_p_indrect_tab); +int iSetEPS_TC_P_INDRECT_CTRL_eps_tc_p_indrect_stat(unsigned int ueps_tc_p_indrect_stat); +int iSetEPS_TC_P_INDRECT_CTRL_eps_tc_p_indrect_mode(unsigned int ueps_tc_p_indrect_mode); +int iSetEPS_TC_P_INDRECT_CTRL_eps_tc_p_indrect_vld(unsigned int ueps_tc_p_indrect_vld); +int iSetEPS_TC_P_INDRECT_TIMEOUT_eps_tc_p_indrect_timeout(unsigned int ueps_tc_p_indrect_timeout); +int iSetEPS_TC_P_INDRECT_DATA_eps_tc_p_indrect_data(unsigned int ueps_tc_p_indrect_data); +int iSetEPS_LB_Q_INDRECT_CTRL_eps_lb_q_indrect_addr(unsigned int ueps_lb_q_indrect_addr); +int iSetEPS_LB_Q_INDRECT_CTRL_eps_lb_q_indrect_tab(unsigned int ueps_lb_q_indrect_tab); +int iSetEPS_LB_Q_INDRECT_CTRL_eps_lb_q_indrect_stat(unsigned int ueps_lb_q_indrect_stat); +int iSetEPS_LB_Q_INDRECT_CTRL_eps_lb_q_indrect_mode(unsigned int ueps_lb_q_indrect_mode); +int iSetEPS_LB_Q_INDRECT_CTRL_eps_lb_q_indrect_vld(unsigned int ueps_lb_q_indrect_vld); +int iSetEPS_LB_Q_INDRECT_TIMEOUT_eps_lb_q_indrect_timeout(unsigned int ueps_lb_q_indrect_timeout); +int iSetEPS_LB_Q_INDRECT_DATA_eps_lb_q_indrect_data(unsigned int ueps_lb_q_indrect_data); +int iSetEPS_LB_P_T_INDRECT_CTRL_eps_lb_p_t_indrect_addr(unsigned int ueps_lb_p_t_indrect_addr); +int iSetEPS_LB_P_T_INDRECT_CTRL_eps_lb_p_t_indrect_tab(unsigned int ueps_lb_p_t_indrect_tab); +int iSetEPS_LB_P_T_INDRECT_CTRL_eps_lb_p_t_indrect_stat(unsigned int ueps_lb_p_t_indrect_stat); +int iSetEPS_LB_P_T_INDRECT_CTRL_eps_lb_p_t_indrect_mode(unsigned int ueps_lb_p_t_indrect_mode); +int iSetEPS_LB_P_T_INDRECT_CTRL_eps_lb_p_t_indrect_vld(unsigned int ueps_lb_p_t_indrect_vld); +int iSetEPS_LB_P_T_INDRECT_TIMEOUT_eps_lb_p_t_indrect_timeout(unsigned int ueps_lb_p_t_indrect_timeout); +int iSetEPS_LB_P_T_INDRECT_DATA_eps_lb_p_t_indrect_data(unsigned int ueps_lb_p_t_indrect_data); +int iSetEPS_P_SOFT_BP_CFG_eps_port_soft_bp_cfg(unsigned int ueps_port_soft_bp_cfg); +int iSetEPS_COS_BP_EN0_eps_cos_bp_en_p0(unsigned int ueps_cos_bp_en_p0); +int iSetEPS_COS_BP_EN0_eps_cos_bp_en_p1(unsigned int ueps_cos_bp_en_p1); +int iSetEPS_COS_BP_EN0_eps_cos_bp_en_p2(unsigned int ueps_cos_bp_en_p2); +int iSetEPS_COS_BP_EN0_eps_cos_bp_en_p3(unsigned int ueps_cos_bp_en_p3); +int iSetEPS_COS_BP_EN1_eps_cos_bp_en_p4(unsigned int ueps_cos_bp_en_p4); +int iSetEPS_COS_BP_EN1_eps_cos_bp_en_p5(unsigned int ueps_cos_bp_en_p5); +int iSetEPS_COS_BP_EN1_eps_cos_bp_en_p6(unsigned int ueps_cos_bp_en_p6); +int iSetEPS_COS_BP_EN1_eps_cos_bp_en_p7(unsigned int ueps_cos_bp_en_p7); +int iSetEPS_BP_MODE_eps_bp_mode(unsigned int ueps_bp_mode); +int iSetEPS_BP_MODE_eps_rw_rsv0(unsigned int ueps_rw_rsv0); +int iSetEPS_ROOT_CIR_CFG_eps_port_grp_cir_cfg(unsigned int ueps_port_grp_cir_cfg); +int iSetEPS_LB_ROOT_CIR_CFG_eps_lb_cir_cfg(unsigned int ueps_lb_cir_cfg); +int iSetEPS_ALL_CIR_CFG_eps_all_cir_cfg(unsigned int ueps_all_cir_cfg); +int iSetEPS_ROOT_CIR_CNT_eps_root_cir_cnt(unsigned int ueps_root_cir_cnt); +int iSetEPS_LB_ROOT_CIR_CNT_eps_lb_root_cir_cnt(unsigned int ueps_lb_root_cir_cnt); +int iSetEPS_ROOT_WGT_CFG_eps_root_wgt_cfg(unsigned int ueps_root_wgt_cfg); +int iSetEPS_NML_ROOT_WGT_CNT_eps_nml_root_wgt_cnt(unsigned int ueps_nml_root_wgt_cnt); +int iSetEPS_LB_ROOT_WGT_CNT_eps_lb_root_wgt_cnt(unsigned int ueps_lb_root_wgt_cnt); +int iSetEPS_ECC_1BIT_ERR_CNT_eps_mem_ecc_err0(unsigned int ueps_mem_ecc_err0); +int iSetEPS_ECC_2BIT_ERR_CNT_eps_mem_ecc_err1(unsigned int ueps_mem_ecc_err1); +int iSetEPS_DQS_CNT_eps_dqs_rec(unsigned int ueps_dqs_rec); +int iSetEPS_EQS_CNT_eps_eqs_rec(unsigned int ueps_eqs_rec); +int iSetEPS_FIFO_CNT_eps_fifo_cnt(unsigned int ueps_fifo_cnt); +int iSetEPS_INNER_ERR_ST_sel_queue_err(unsigned int usel_queue_err); +int iSetEPS_INNER_ERR_ST_dqs_qid_err(unsigned int udqs_qid_err); +int iSetEPS_INNER_ERR_ST_dqs_over_err(unsigned int udqs_over_err); +int iSetEPS_INNER_ERR_ST_dqs_late_err(unsigned int udqs_late_err); + +/* Define the union csr_hps_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_indrect_addr : 24; /* [23:0] */ + u32 hps_indrect_tab : 4; /* [27:24] */ + u32 hps_indrect_stat : 2; /* [29:28] */ + u32 hps_indrect_mode : 1; /* [30] */ + u32 hps_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hps_indrect_ctrl_u; + +/* Define the union csr_hps_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hps_indrect_timeout_u; + +/* Define the union csr_hps_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_hps_indrect_data_u; + +/* Define the union csr_esch_hps_cppi_shap_type_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hp_shaper_pkt_len : 18; /* [17:0] */ + u32 rsv_0 : 2; /* [19:18] */ + u32 hps_up_shaper_type_cfg : 1; /* [20] */ + u32 rsv_1 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_cppi_shap_type_cfg_u; + +/* Define the union csr_esch_hps_soft_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_port_soft_bp_cfg : 6; /* [5:0] */ + u32 rsv_2 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_soft_bp_cfg_u; + +/* Define the union csr_esch_hps_root_shap_type_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hp_root_shaper_pkt_len : 18; /* [17:0] */ + u32 rsv_3 : 2; /* [19:18] */ + u32 hps_root_shaper_type_cfg : 1; /* [20] */ + u32 rsv_4 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_root_shap_type_cfg_u; + +/* Define the union csr_esch_hps_upq_shap_type_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_upq_shaper_type_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_upq_shap_type_cfg_u; + +/* Define the union csr_esch_hps_all_root_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_root_wgt_cfg : 12; /* [11:0] */ + u32 hps_root_wgt_cfg : 12; /* [23:12] */ + u32 rsv_5 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_all_root_wgt_cfg_u; + +/* Define the union csr_esch_hps_root_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_root_cir_cfg : 25; /* [24:0] */ + u32 rsv_6 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_root_cir_cfg_u; + +/* Define the union csr_esch_hps_lb_root_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_root_cir_cfg : 25; /* [24:0] */ + u32 rsv_7 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_root_cir_cfg_u; + +/* Define the union csr_esch_hps_lb_p_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_port_wgt_cfg : 12; /* [11:0] */ + u32 rsv_8 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_p_wgt_cfg_u; + +/* Define the union csr_esch_hps_lb_p_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_port_cir_cfg : 25; /* [24:0] */ + u32 rsv_9 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_p_cir_cfg_u; + +/* Define the union csr_esch_hps_lb_q_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_q_wgt_cfg : 12; /* [11:0] */ + u32 rsv_10 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_q_wgt_cfg_u; + +/* Define the union csr_esch_hps_lb_q_cir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_q_cir_cfg : 25; /* [24:0] */ + u32 rsv_11 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_q_cir_cfg_u; + +/* Define the union csr_esch_hps_root_wgt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_root_wgtcnt : 25; /* [24:0] */ + u32 rsv_12 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_root_wgt_cnt_u; + +/* Define the union csr_esch_hps_lb_p_wgt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_port_wgtcnt : 25; /* [24:0] */ + u32 rsv_13 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_p_wgt_cnt_u; + +/* Define the union csr_esch_hps_lb_q_wgt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_q_wgtcnt : 25; /* [24:0] */ + u32 rsv_14 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_q_wgt_cnt_u; + +/* Define the union csr_esch_hps_root_cir_token_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_r_cir_token : 26; /* [25:0] */ + u32 rsv_15 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_root_cir_token_u; + +/* Define the union csr_esch_hps_lb_p_cir_token_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_p_cir_token : 26; /* [25:0] */ + u32 rsv_16 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_p_cir_token_u; + +/* Define the union csr_esch_hps_lb_q_cir_token_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_lb_q_cir_token : 26; /* [25:0] */ + u32 rsv_17 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_lb_q_cir_token_u; + +/* Define the union csr_esch_hps_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_mem_ecc_err0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_ecc_1bit_err_cnt_u; + +/* Define the union csr_esch_hps_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_mem_ecc_err1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_ecc_2bit_err_cnt_u; + +/* Define the union csr_esch_hps_dqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_dqs_rec : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_dqs_cnt_u; + +/* Define the union csr_esch_hps_eqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hps_eqs_rec : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_esch_hps_eqs_cnt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_hps_indrect_ctrl_u hps_indrect_ctrl; /* 0 */ + volatile csr_hps_indrect_timeout_u hps_indrect_timeout; /* 4 */ + volatile csr_hps_indrect_data_u hps_indrect_data; /* 8 */ + volatile csr_esch_hps_cppi_shap_type_cfg_u esch_hps_cppi_shap_type_cfg; /* 14 */ + volatile csr_esch_hps_soft_bp_cfg_u esch_hps_soft_bp_cfg; /* 18 */ + volatile csr_esch_hps_root_shap_type_cfg_u esch_hps_root_shap_type_cfg; /* 1C */ + volatile csr_esch_hps_upq_shap_type_cfg_u esch_hps_upq_shap_type_cfg; /* 60 */ + volatile csr_esch_hps_all_root_wgt_cfg_u esch_hps_all_root_wgt_cfg; /* 100 */ + volatile csr_esch_hps_root_cir_cfg_u esch_hps_root_cir_cfg; /* 104 */ + volatile csr_esch_hps_lb_root_cir_cfg_u esch_hps_lb_root_cir_cfg; /* 108 */ + volatile csr_esch_hps_lb_p_wgt_cfg_u esch_hps_lb_p_wgt_cfg[8]; /* 110 */ + volatile csr_esch_hps_lb_p_cir_cfg_u esch_hps_lb_p_cir_cfg[8]; /* 130 */ + volatile csr_esch_hps_lb_q_wgt_cfg_u esch_hps_lb_q_wgt_cfg[64]; /* 150 */ + volatile csr_esch_hps_lb_q_cir_cfg_u esch_hps_lb_q_cir_cfg[64]; /* 250 */ + volatile csr_esch_hps_root_wgt_cnt_u esch_hps_root_wgt_cnt[2]; /* 400 */ + volatile csr_esch_hps_lb_p_wgt_cnt_u esch_hps_lb_p_wgt_cnt[8]; /* 410 */ + volatile csr_esch_hps_lb_q_wgt_cnt_u esch_hps_lb_q_wgt_cnt[64]; /* 430 */ + volatile csr_esch_hps_root_cir_token_u esch_hps_root_cir_token[2]; /* 530 */ + volatile csr_esch_hps_lb_p_cir_token_u esch_hps_lb_p_cir_token[8]; /* 540 */ + volatile csr_esch_hps_lb_q_cir_token_u esch_hps_lb_q_cir_token[64]; /* 560 */ + volatile csr_esch_hps_ecc_1bit_err_cnt_u esch_hps_ecc_1bit_err_cnt; /* 660 */ + volatile csr_esch_hps_ecc_2bit_err_cnt_u esch_hps_ecc_2bit_err_cnt; /* 664 */ + volatile csr_esch_hps_dqs_cnt_u esch_hps_dqs_cnt; /* 668 */ + volatile csr_esch_hps_eqs_cnt_u esch_hps_eqs_cnt; /* 66C */ +} S_esch_hps_csr_REGS_TYPE; + +/* Declare the struct pointor of the module esch_hps_csr */ +extern volatile S_esch_hps_csr_REGS_TYPE *gopesch_hps_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetHPS_INDRECT_CTRL_hps_indrect_addr(unsigned int uhps_indrect_addr); +int iSetHPS_INDRECT_CTRL_hps_indrect_tab(unsigned int uhps_indrect_tab); +int iSetHPS_INDRECT_CTRL_hps_indrect_stat(unsigned int uhps_indrect_stat); +int iSetHPS_INDRECT_CTRL_hps_indrect_mode(unsigned int uhps_indrect_mode); +int iSetHPS_INDRECT_CTRL_hps_indrect_vld(unsigned int uhps_indrect_vld); +int iSetHPS_INDRECT_TIMEOUT_hps_indrect_timeout(unsigned int uhps_indrect_timeout); +int iSetHPS_INDRECT_DATA_hps_indrect_data(unsigned int uhps_indrect_data); +int iSetESCH_HPS_CPPI_SHAP_TYPE_CFG_hp_shaper_pkt_len(unsigned int uhp_shaper_pkt_len); +int iSetESCH_HPS_CPPI_SHAP_TYPE_CFG_hps_up_shaper_type_cfg(unsigned int uhps_up_shaper_type_cfg); +int iSetESCH_HPS_SOFT_BP_CFG_hps_port_soft_bp_cfg(unsigned int uhps_port_soft_bp_cfg); +int iSetESCH_HPS_ROOT_SHAP_TYPE_CFG_hp_root_shaper_pkt_len(unsigned int uhp_root_shaper_pkt_len); +int iSetESCH_HPS_ROOT_SHAP_TYPE_CFG_hps_root_shaper_type_cfg(unsigned int uhps_root_shaper_type_cfg); +int iSetESCH_HPS_UPQ_SHAP_TYPE_CFG_hps_upq_shaper_type_cfg(unsigned int uhps_upq_shaper_type_cfg); +int iSetESCH_HPS_ALL_ROOT_WGT_CFG_hps_lb_root_wgt_cfg(unsigned int uhps_lb_root_wgt_cfg); +int iSetESCH_HPS_ALL_ROOT_WGT_CFG_hps_root_wgt_cfg(unsigned int uhps_root_wgt_cfg); +int iSetESCH_HPS_ROOT_CIR_CFG_hps_root_cir_cfg(unsigned int uhps_root_cir_cfg); +int iSetESCH_HPS_LB_ROOT_CIR_CFG_hps_lb_root_cir_cfg(unsigned int uhps_lb_root_cir_cfg); +int iSetESCH_HPS_LB_P_WGT_CFG_hps_lb_port_wgt_cfg(unsigned int uhps_lb_port_wgt_cfg); +int iSetESCH_HPS_LB_P_CIR_CFG_hps_lb_port_cir_cfg(unsigned int uhps_lb_port_cir_cfg); +int iSetESCH_HPS_LB_Q_WGT_CFG_hps_lb_q_wgt_cfg(unsigned int uhps_lb_q_wgt_cfg); +int iSetESCH_HPS_LB_Q_CIR_CFG_hps_lb_q_cir_cfg(unsigned int uhps_lb_q_cir_cfg); +int iSetESCH_HPS_ROOT_WGT_CNT_hps_root_wgtcnt(unsigned int uhps_root_wgtcnt); +int iSetESCH_HPS_LB_P_WGT_CNT_hps_lb_port_wgtcnt(unsigned int uhps_lb_port_wgtcnt); +int iSetESCH_HPS_LB_Q_WGT_CNT_hps_lb_q_wgtcnt(unsigned int uhps_lb_q_wgtcnt); +int iSetESCH_HPS_ROOT_CIR_TOKEN_hps_lb_r_cir_token(unsigned int uhps_lb_r_cir_token); +int iSetESCH_HPS_LB_P_CIR_TOKEN_hps_lb_p_cir_token(unsigned int uhps_lb_p_cir_token); +int iSetESCH_HPS_LB_Q_CIR_TOKEN_hps_lb_q_cir_token(unsigned int uhps_lb_q_cir_token); +int iSetESCH_HPS_ECC_1BIT_ERR_CNT_hps_mem_ecc_err0(unsigned int uhps_mem_ecc_err0); +int iSetESCH_HPS_ECC_2BIT_ERR_CNT_hps_mem_ecc_err1(unsigned int uhps_mem_ecc_err1); +int iSetESCH_HPS_DQS_CNT_hps_dqs_rec(unsigned int uhps_dqs_rec); +int iSetESCH_HPS_EQS_CNT_hps_eqs_rec(unsigned int uhps_eqs_rec); + + +#endif // ESCH_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_reg_offset.h new file mode 100644 index 000000000..52f6a1cd0 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/esch_reg_offset.h @@ -0,0 +1,802 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : esch_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/12/11 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/12/11 20:09:31 Create file +// ****************************************************************************** + +#ifndef ESCH_REG_OFFSET_H +#define ESCH_REG_OFFSET_H + +/* ESCH_TOP_CSR Base address of Module's Register */ +#define CSR_ESCH_TOP_CSR_BASE (0xB000) + +/* **************************************************************************** */ +/* ESCH_TOP_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x0) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x4) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x8) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_3_REG (CSR_ESCH_TOP_CSR_BASE + 0xC) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x10) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x14) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x18) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x20) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x24) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x28) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x30) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x34) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x38) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x40) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x44) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x48) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x4C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x50) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x54) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x58) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x60) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x64) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x68) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x70) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x74) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x78) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x7C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x80) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x84) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x88) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x8C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x90) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x94) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x98) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_COS_CH_MAP_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x9C) /* COS to CPI CH MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_MEM_CFG_OK_REG (CSR_ESCH_TOP_CSR_BASE + 0xA0) /* ESCH使能配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_PPOP_BP_CFG_REG (CSR_ESCH_TOP_CSR_BASE + 0xA4) /* DFX CFG */ +#define CSR_ESCH_TOP_CSR_ESCH_PPOP_BP_ST_REG (CSR_ESCH_TOP_CSR_BASE + 0xA8) +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x100) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x104) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x108) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x10C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x110) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x114) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x118) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x11C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x120) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x124) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x128) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x12C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x130) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x134) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x138) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x13C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x140) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x144) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x148) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x14C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x150) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x154) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x158) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x15C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x160) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x164) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x168) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x16C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x170) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x174) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x178) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x17C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x180) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x184) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x188) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x18C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x190) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x194) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x198) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x19C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_40_REG (CSR_ESCH_TOP_CSR_BASE + 0x1A0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_41_REG (CSR_ESCH_TOP_CSR_BASE + 0x1A4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_42_REG (CSR_ESCH_TOP_CSR_BASE + 0x1A8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_43_REG (CSR_ESCH_TOP_CSR_BASE + 0x1AC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_44_REG (CSR_ESCH_TOP_CSR_BASE + 0x1B0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_45_REG (CSR_ESCH_TOP_CSR_BASE + 0x1B4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_46_REG (CSR_ESCH_TOP_CSR_BASE + 0x1B8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_47_REG (CSR_ESCH_TOP_CSR_BASE + 0x1BC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_48_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_49_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_50_REG (CSR_ESCH_TOP_CSR_BASE + 0x1C8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_51_REG (CSR_ESCH_TOP_CSR_BASE + 0x1CC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_52_REG (CSR_ESCH_TOP_CSR_BASE + 0x1D0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_53_REG (CSR_ESCH_TOP_CSR_BASE + 0x1D4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_54_REG (CSR_ESCH_TOP_CSR_BASE + 0x1D8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_55_REG (CSR_ESCH_TOP_CSR_BASE + 0x1DC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_56_REG (CSR_ESCH_TOP_CSR_BASE + 0x1E0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_57_REG (CSR_ESCH_TOP_CSR_BASE + 0x1E4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_58_REG (CSR_ESCH_TOP_CSR_BASE + 0x1E8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_59_REG (CSR_ESCH_TOP_CSR_BASE + 0x1EC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_60_REG (CSR_ESCH_TOP_CSR_BASE + 0x1F0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_61_REG (CSR_ESCH_TOP_CSR_BASE + 0x1F4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_62_REG (CSR_ESCH_TOP_CSR_BASE + 0x1F8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_63_REG (CSR_ESCH_TOP_CSR_BASE + 0x1FC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_64_REG (CSR_ESCH_TOP_CSR_BASE + 0x200) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_65_REG (CSR_ESCH_TOP_CSR_BASE + 0x204) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_66_REG (CSR_ESCH_TOP_CSR_BASE + 0x208) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_67_REG (CSR_ESCH_TOP_CSR_BASE + 0x20C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_68_REG (CSR_ESCH_TOP_CSR_BASE + 0x210) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_69_REG (CSR_ESCH_TOP_CSR_BASE + 0x214) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_70_REG (CSR_ESCH_TOP_CSR_BASE + 0x218) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_71_REG (CSR_ESCH_TOP_CSR_BASE + 0x21C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_72_REG (CSR_ESCH_TOP_CSR_BASE + 0x220) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_73_REG (CSR_ESCH_TOP_CSR_BASE + 0x224) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_74_REG (CSR_ESCH_TOP_CSR_BASE + 0x228) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_75_REG (CSR_ESCH_TOP_CSR_BASE + 0x22C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_76_REG (CSR_ESCH_TOP_CSR_BASE + 0x230) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_77_REG (CSR_ESCH_TOP_CSR_BASE + 0x234) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_78_REG (CSR_ESCH_TOP_CSR_BASE + 0x238) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_79_REG (CSR_ESCH_TOP_CSR_BASE + 0x23C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_80_REG (CSR_ESCH_TOP_CSR_BASE + 0x240) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_81_REG (CSR_ESCH_TOP_CSR_BASE + 0x244) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_82_REG (CSR_ESCH_TOP_CSR_BASE + 0x248) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_83_REG (CSR_ESCH_TOP_CSR_BASE + 0x24C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_84_REG (CSR_ESCH_TOP_CSR_BASE + 0x250) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_85_REG (CSR_ESCH_TOP_CSR_BASE + 0x254) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_86_REG (CSR_ESCH_TOP_CSR_BASE + 0x258) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_87_REG (CSR_ESCH_TOP_CSR_BASE + 0x25C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_88_REG (CSR_ESCH_TOP_CSR_BASE + 0x260) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_89_REG (CSR_ESCH_TOP_CSR_BASE + 0x264) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_90_REG (CSR_ESCH_TOP_CSR_BASE + 0x268) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_91_REG (CSR_ESCH_TOP_CSR_BASE + 0x26C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_92_REG (CSR_ESCH_TOP_CSR_BASE + 0x270) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_93_REG (CSR_ESCH_TOP_CSR_BASE + 0x274) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_94_REG (CSR_ESCH_TOP_CSR_BASE + 0x278) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_95_REG (CSR_ESCH_TOP_CSR_BASE + 0x27C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_96_REG (CSR_ESCH_TOP_CSR_BASE + 0x280) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_97_REG (CSR_ESCH_TOP_CSR_BASE + 0x284) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_98_REG (CSR_ESCH_TOP_CSR_BASE + 0x288) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_99_REG (CSR_ESCH_TOP_CSR_BASE + 0x28C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_100_REG (CSR_ESCH_TOP_CSR_BASE + 0x290) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_101_REG (CSR_ESCH_TOP_CSR_BASE + 0x294) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_102_REG (CSR_ESCH_TOP_CSR_BASE + 0x298) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_103_REG (CSR_ESCH_TOP_CSR_BASE + 0x29C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_104_REG (CSR_ESCH_TOP_CSR_BASE + 0x2A0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_105_REG (CSR_ESCH_TOP_CSR_BASE + 0x2A4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_106_REG (CSR_ESCH_TOP_CSR_BASE + 0x2A8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_107_REG (CSR_ESCH_TOP_CSR_BASE + 0x2AC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_108_REG (CSR_ESCH_TOP_CSR_BASE + 0x2B0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_109_REG (CSR_ESCH_TOP_CSR_BASE + 0x2B4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_110_REG (CSR_ESCH_TOP_CSR_BASE + 0x2B8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_111_REG (CSR_ESCH_TOP_CSR_BASE + 0x2BC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_112_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_113_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_114_REG (CSR_ESCH_TOP_CSR_BASE + 0x2C8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_115_REG (CSR_ESCH_TOP_CSR_BASE + 0x2CC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_116_REG (CSR_ESCH_TOP_CSR_BASE + 0x2D0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_117_REG (CSR_ESCH_TOP_CSR_BASE + 0x2D4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_118_REG (CSR_ESCH_TOP_CSR_BASE + 0x2D8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_119_REG (CSR_ESCH_TOP_CSR_BASE + 0x2DC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_120_REG (CSR_ESCH_TOP_CSR_BASE + 0x2E0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_121_REG (CSR_ESCH_TOP_CSR_BASE + 0x2E4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_122_REG (CSR_ESCH_TOP_CSR_BASE + 0x2E8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_123_REG (CSR_ESCH_TOP_CSR_BASE + 0x2EC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_124_REG (CSR_ESCH_TOP_CSR_BASE + 0x2F0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_125_REG (CSR_ESCH_TOP_CSR_BASE + 0x2F4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_126_REG (CSR_ESCH_TOP_CSR_BASE + 0x2F8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_127_REG (CSR_ESCH_TOP_CSR_BASE + 0x2FC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_128_REG (CSR_ESCH_TOP_CSR_BASE + 0x300) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_129_REG (CSR_ESCH_TOP_CSR_BASE + 0x304) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_130_REG (CSR_ESCH_TOP_CSR_BASE + 0x308) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_131_REG (CSR_ESCH_TOP_CSR_BASE + 0x30C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_132_REG (CSR_ESCH_TOP_CSR_BASE + 0x310) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_133_REG (CSR_ESCH_TOP_CSR_BASE + 0x314) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_134_REG (CSR_ESCH_TOP_CSR_BASE + 0x318) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_135_REG (CSR_ESCH_TOP_CSR_BASE + 0x31C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_136_REG (CSR_ESCH_TOP_CSR_BASE + 0x320) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_137_REG (CSR_ESCH_TOP_CSR_BASE + 0x324) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_138_REG (CSR_ESCH_TOP_CSR_BASE + 0x328) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_139_REG (CSR_ESCH_TOP_CSR_BASE + 0x32C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_140_REG (CSR_ESCH_TOP_CSR_BASE + 0x330) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_141_REG (CSR_ESCH_TOP_CSR_BASE + 0x334) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_142_REG (CSR_ESCH_TOP_CSR_BASE + 0x338) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_143_REG (CSR_ESCH_TOP_CSR_BASE + 0x33C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_144_REG (CSR_ESCH_TOP_CSR_BASE + 0x340) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_145_REG (CSR_ESCH_TOP_CSR_BASE + 0x344) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_146_REG (CSR_ESCH_TOP_CSR_BASE + 0x348) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_147_REG (CSR_ESCH_TOP_CSR_BASE + 0x34C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_148_REG (CSR_ESCH_TOP_CSR_BASE + 0x350) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_149_REG (CSR_ESCH_TOP_CSR_BASE + 0x354) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_150_REG (CSR_ESCH_TOP_CSR_BASE + 0x358) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_151_REG (CSR_ESCH_TOP_CSR_BASE + 0x35C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_152_REG (CSR_ESCH_TOP_CSR_BASE + 0x360) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_153_REG (CSR_ESCH_TOP_CSR_BASE + 0x364) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_154_REG (CSR_ESCH_TOP_CSR_BASE + 0x368) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_155_REG (CSR_ESCH_TOP_CSR_BASE + 0x36C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_156_REG (CSR_ESCH_TOP_CSR_BASE + 0x370) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_157_REG (CSR_ESCH_TOP_CSR_BASE + 0x374) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_158_REG (CSR_ESCH_TOP_CSR_BASE + 0x378) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_159_REG (CSR_ESCH_TOP_CSR_BASE + 0x37C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_160_REG (CSR_ESCH_TOP_CSR_BASE + 0x380) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_161_REG (CSR_ESCH_TOP_CSR_BASE + 0x384) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_162_REG (CSR_ESCH_TOP_CSR_BASE + 0x388) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_163_REG (CSR_ESCH_TOP_CSR_BASE + 0x38C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_164_REG (CSR_ESCH_TOP_CSR_BASE + 0x390) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_165_REG (CSR_ESCH_TOP_CSR_BASE + 0x394) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_166_REG (CSR_ESCH_TOP_CSR_BASE + 0x398) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_167_REG (CSR_ESCH_TOP_CSR_BASE + 0x39C) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_168_REG (CSR_ESCH_TOP_CSR_BASE + 0x3A0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_169_REG (CSR_ESCH_TOP_CSR_BASE + 0x3A4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_170_REG (CSR_ESCH_TOP_CSR_BASE + 0x3A8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_171_REG (CSR_ESCH_TOP_CSR_BASE + 0x3AC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_172_REG (CSR_ESCH_TOP_CSR_BASE + 0x3B0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_173_REG (CSR_ESCH_TOP_CSR_BASE + 0x3B4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_174_REG (CSR_ESCH_TOP_CSR_BASE + 0x3B8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_175_REG (CSR_ESCH_TOP_CSR_BASE + 0x3BC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_176_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_177_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_178_REG (CSR_ESCH_TOP_CSR_BASE + 0x3C8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_179_REG (CSR_ESCH_TOP_CSR_BASE + 0x3CC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_180_REG (CSR_ESCH_TOP_CSR_BASE + 0x3D0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_181_REG (CSR_ESCH_TOP_CSR_BASE + 0x3D4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_182_REG (CSR_ESCH_TOP_CSR_BASE + 0x3D8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_183_REG (CSR_ESCH_TOP_CSR_BASE + 0x3DC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_184_REG (CSR_ESCH_TOP_CSR_BASE + 0x3E0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_185_REG (CSR_ESCH_TOP_CSR_BASE + 0x3E4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_186_REG (CSR_ESCH_TOP_CSR_BASE + 0x3E8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_187_REG (CSR_ESCH_TOP_CSR_BASE + 0x3EC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_188_REG (CSR_ESCH_TOP_CSR_BASE + 0x3F0) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_189_REG (CSR_ESCH_TOP_CSR_BASE + 0x3F4) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_190_REG (CSR_ESCH_TOP_CSR_BASE + 0x3F8) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_LB_PRM_BP_MAP_191_REG (CSR_ESCH_TOP_CSR_BASE + 0x3FC) /* NETWORK LB Q SOURCE MAP */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x400) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x404) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x408) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x40C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x410) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x414) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x418) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x41C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x420) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x424) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x428) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x42C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x430) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x434) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x438) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x43C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x440) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x444) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x448) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x44C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x450) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x454) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x458) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x45C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x460) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x464) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x468) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x46C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x470) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x474) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x478) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x47C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOST_FIFO_TH_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x480) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x500) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x504) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x508) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x50C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x510) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x514) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x518) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x51C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x520) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x524) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x528) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x52C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x530) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x534) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x538) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x53C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x540) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x544) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x548) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x54C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x550) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x554) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x558) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x55C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x560) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x564) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x568) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x56C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x570) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x574) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x578) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x57C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x580) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x584) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x588) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x58C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x590) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x594) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x598) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x59C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_40_REG (CSR_ESCH_TOP_CSR_BASE + 0x5A0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_41_REG (CSR_ESCH_TOP_CSR_BASE + 0x5A4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_42_REG (CSR_ESCH_TOP_CSR_BASE + 0x5A8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_43_REG (CSR_ESCH_TOP_CSR_BASE + 0x5AC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_44_REG (CSR_ESCH_TOP_CSR_BASE + 0x5B0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_45_REG (CSR_ESCH_TOP_CSR_BASE + 0x5B4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_46_REG (CSR_ESCH_TOP_CSR_BASE + 0x5B8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_47_REG (CSR_ESCH_TOP_CSR_BASE + 0x5BC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_48_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_49_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_50_REG (CSR_ESCH_TOP_CSR_BASE + 0x5C8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_51_REG (CSR_ESCH_TOP_CSR_BASE + 0x5CC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_52_REG (CSR_ESCH_TOP_CSR_BASE + 0x5D0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_53_REG (CSR_ESCH_TOP_CSR_BASE + 0x5D4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_54_REG (CSR_ESCH_TOP_CSR_BASE + 0x5D8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_55_REG (CSR_ESCH_TOP_CSR_BASE + 0x5DC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_56_REG (CSR_ESCH_TOP_CSR_BASE + 0x5E0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_57_REG (CSR_ESCH_TOP_CSR_BASE + 0x5E4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_58_REG (CSR_ESCH_TOP_CSR_BASE + 0x5E8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_59_REG (CSR_ESCH_TOP_CSR_BASE + 0x5EC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_60_REG (CSR_ESCH_TOP_CSR_BASE + 0x5F0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_61_REG (CSR_ESCH_TOP_CSR_BASE + 0x5F4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_62_REG (CSR_ESCH_TOP_CSR_BASE + 0x5F8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_HOSTLB_FIFO_TH_63_REG (CSR_ESCH_TOP_CSR_BASE + 0x5FC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x600) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x604) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x608) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_3_REG (CSR_ESCH_TOP_CSR_BASE + 0x60C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_4_REG (CSR_ESCH_TOP_CSR_BASE + 0x610) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_5_REG (CSR_ESCH_TOP_CSR_BASE + 0x614) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_6_REG (CSR_ESCH_TOP_CSR_BASE + 0x618) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_7_REG (CSR_ESCH_TOP_CSR_BASE + 0x61C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_8_REG (CSR_ESCH_TOP_CSR_BASE + 0x620) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_9_REG (CSR_ESCH_TOP_CSR_BASE + 0x624) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_10_REG (CSR_ESCH_TOP_CSR_BASE + 0x628) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_11_REG (CSR_ESCH_TOP_CSR_BASE + 0x62C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_12_REG (CSR_ESCH_TOP_CSR_BASE + 0x630) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_13_REG (CSR_ESCH_TOP_CSR_BASE + 0x634) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_14_REG (CSR_ESCH_TOP_CSR_BASE + 0x638) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_15_REG (CSR_ESCH_TOP_CSR_BASE + 0x63C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_16_REG (CSR_ESCH_TOP_CSR_BASE + 0x640) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_17_REG (CSR_ESCH_TOP_CSR_BASE + 0x644) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_18_REG (CSR_ESCH_TOP_CSR_BASE + 0x648) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_19_REG (CSR_ESCH_TOP_CSR_BASE + 0x64C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_20_REG (CSR_ESCH_TOP_CSR_BASE + 0x650) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_21_REG (CSR_ESCH_TOP_CSR_BASE + 0x654) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_22_REG (CSR_ESCH_TOP_CSR_BASE + 0x658) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_23_REG (CSR_ESCH_TOP_CSR_BASE + 0x65C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_24_REG (CSR_ESCH_TOP_CSR_BASE + 0x660) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_25_REG (CSR_ESCH_TOP_CSR_BASE + 0x664) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_26_REG (CSR_ESCH_TOP_CSR_BASE + 0x668) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_27_REG (CSR_ESCH_TOP_CSR_BASE + 0x66C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_28_REG (CSR_ESCH_TOP_CSR_BASE + 0x670) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_29_REG (CSR_ESCH_TOP_CSR_BASE + 0x674) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_30_REG (CSR_ESCH_TOP_CSR_BASE + 0x678) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_31_REG (CSR_ESCH_TOP_CSR_BASE + 0x67C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_32_REG (CSR_ESCH_TOP_CSR_BASE + 0x680) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_33_REG (CSR_ESCH_TOP_CSR_BASE + 0x684) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_34_REG (CSR_ESCH_TOP_CSR_BASE + 0x688) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_35_REG (CSR_ESCH_TOP_CSR_BASE + 0x68C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_36_REG (CSR_ESCH_TOP_CSR_BASE + 0x690) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_37_REG (CSR_ESCH_TOP_CSR_BASE + 0x694) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_38_REG (CSR_ESCH_TOP_CSR_BASE + 0x698) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_39_REG (CSR_ESCH_TOP_CSR_BASE + 0x69C) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_40_REG (CSR_ESCH_TOP_CSR_BASE + 0x6A0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_41_REG (CSR_ESCH_TOP_CSR_BASE + 0x6A4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_42_REG (CSR_ESCH_TOP_CSR_BASE + 0x6A8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_43_REG (CSR_ESCH_TOP_CSR_BASE + 0x6AC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_44_REG (CSR_ESCH_TOP_CSR_BASE + 0x6B0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_45_REG (CSR_ESCH_TOP_CSR_BASE + 0x6B4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_46_REG (CSR_ESCH_TOP_CSR_BASE + 0x6B8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_47_REG (CSR_ESCH_TOP_CSR_BASE + 0x6BC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_48_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_49_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_50_REG (CSR_ESCH_TOP_CSR_BASE + 0x6C8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_51_REG (CSR_ESCH_TOP_CSR_BASE + 0x6CC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_52_REG (CSR_ESCH_TOP_CSR_BASE + 0x6D0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_53_REG (CSR_ESCH_TOP_CSR_BASE + 0x6D4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_54_REG (CSR_ESCH_TOP_CSR_BASE + 0x6D8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_55_REG (CSR_ESCH_TOP_CSR_BASE + 0x6DC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_56_REG (CSR_ESCH_TOP_CSR_BASE + 0x6E0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_57_REG (CSR_ESCH_TOP_CSR_BASE + 0x6E4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_58_REG (CSR_ESCH_TOP_CSR_BASE + 0x6E8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_59_REG (CSR_ESCH_TOP_CSR_BASE + 0x6EC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_60_REG (CSR_ESCH_TOP_CSR_BASE + 0x6F0) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_61_REG (CSR_ESCH_TOP_CSR_BASE + 0x6F4) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_62_REG (CSR_ESCH_TOP_CSR_BASE + 0x6F8) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NET_FIFO_TH_63_REG (CSR_ESCH_TOP_CSR_BASE + 0x6FC) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NETLB_FIFO_TH_0_REG (CSR_ESCH_TOP_CSR_BASE + 0x700) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NETLB_FIFO_TH_1_REG (CSR_ESCH_TOP_CSR_BASE + 0x704) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_NETLB_FIFO_TH_2_REG (CSR_ESCH_TOP_CSR_BASE + 0x708) /* 信用反压阈值配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_MEM_CTRL_REG (CSR_ESCH_TOP_CSR_BASE + 0x750) /* MEM 配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_MEM_ERR_REQ0_REG (CSR_ESCH_TOP_CSR_BASE + 0x754) /* MEM 配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_MEM_ERR_REQ1_REG (CSR_ESCH_TOP_CSR_BASE + 0x758) /* MEM 配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT_VECTOR_REG (CSR_ESCH_TOP_CSR_BASE + 0x760) /* 中断向量 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT_REG (CSR_ESCH_TOP_CSR_BASE + 0x764) /* 中断状态 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT_EN_REG (CSR_ESCH_TOP_CSR_BASE + 0x768) /* 中断屏蔽 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT0_STICKY0_REG (CSR_ESCH_TOP_CSR_BASE + 0x76C) /* 中断0的sticky信息 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT0_STICKY1_REG (CSR_ESCH_TOP_CSR_BASE + 0x770) /* 中断1的sticky信息 */ +#define CSR_ESCH_TOP_CSR_ESCH_INT0_STICKY2_REG (CSR_ESCH_TOP_CSR_BASE + 0x774) /* 中断2的sticky信息 */ +#define CSR_ESCH_TOP_CSR_ESCH_FCNP_CFG_REG (CSR_ESCH_TOP_CSR_BASE + 0x778) /* FCNPshaper固定桶深配置 */ +#define CSR_ESCH_TOP_CSR_ESCH_CPB_CH_CDT_CFG_REG (CSR_ESCH_TOP_CSR_BASE + 0x77C) /* 信用深度统计 */ +#define CSR_ESCH_TOP_CSR_ESCH_HPS_NML_COS_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x780) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_HPS_UP_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x784) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_HPS_LB_COS_HIGH_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x788) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_HPS_LB_COS_LOW_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x78C) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_EPS_COS_HIGH_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x790) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_EPS_COS_LOW_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x794) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_EPS_LB_TYPE_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x79C) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_MAG_HIGH_COS_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x7A0) /* 信用反压 */ +#define CSR_ESCH_TOP_CSR_ESCH_MAG_LOW_COS_BP_REG (CSR_ESCH_TOP_CSR_BASE + 0x7A4) /* 信用反压 */ + +/* ESCH_EPS_CSR Base address of Module's Register */ +#define CSR_ESCH_EPS_CSR_BASE (0xA800) + +/* **************************************************************************** */ +/* ESCH_EPS_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_ESCH_EPS_CSR_EPS_Q_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x0) /* EPS 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_Q_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x4) /* EPS 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_Q_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x8) /* EPS 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_COS_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x10) /* EPS COS间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_COS_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x14) /* EPS COS间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_COS_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x18) /* EPS COS间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_TC_P_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x20) /* EPS TC和Port间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_TC_P_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x24) /* EPS TC和Port间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_TC_P_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x28) /* EPS TC和Port间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_Q_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x30) /* EPS LB 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_Q_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x34) /* EPS LB 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_Q_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x38) /* EPS LB 队列间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_P_T_INDRECT_CTRL_REG (CSR_ESCH_EPS_CSR_BASE + 0x40) /* EPS LB Port和Type间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_P_T_INDRECT_TIMEOUT_REG (CSR_ESCH_EPS_CSR_BASE + 0x44) /* EPS LB Port和Type间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_P_T_INDRECT_DATA_REG (CSR_ESCH_EPS_CSR_BASE + 0x48) /* EPS LB Port和Type间接访问 */ +#define CSR_ESCH_EPS_CSR_EPS_P_SOFT_BP_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x50) /* EPS PORT节点软反压配置 */ +#define CSR_ESCH_EPS_CSR_EPS_COS_BP_EN0_REG (CSR_ESCH_EPS_CSR_BASE + 0x54) /* ETH端口队列反压响应使能寄存器0 */ +#define CSR_ESCH_EPS_CSR_EPS_COS_BP_EN1_REG (CSR_ESCH_EPS_CSR_BASE + 0x58) /* ETH端口队列反压响应使能寄存器1 */ +#define CSR_ESCH_EPS_CSR_EPS_BP_MODE_REG (CSR_ESCH_EPS_CSR_BASE + 0x5C) /* EPS BP 模式配置 register. */ +#define CSR_ESCH_EPS_CSR_EPS_ROOT_CIR_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x60) /* EPS PORT GRP CIR shaper配置 */ +#define CSR_ESCH_EPS_CSR_EPS_LB_ROOT_CIR_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x64) /* EPS LB PORT GRP CIR shaper配置 */ +#define CSR_ESCH_EPS_CSR_EPS_ALL_CIR_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x68) /* EPS ALL CIR shaper配置 */ +#define CSR_ESCH_EPS_CSR_EPS_ROOT_CIR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x6C) /* EPS_ROOT_CIR_CNT */ +#define CSR_ESCH_EPS_CSR_EPS_LB_ROOT_CIR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x70) /* EPS_LB_ROOT_CIR_CNT */ +#define CSR_ESCH_EPS_CSR_EPS_ROOT_WGT_CFG_REG (CSR_ESCH_EPS_CSR_BASE + 0x78) /* EPS_ROOT_WGT_CNT */ +#define CSR_ESCH_EPS_CSR_EPS_NML_ROOT_WGT_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x80) /* NML ROOT_WGT */ +#define CSR_ESCH_EPS_CSR_EPS_LB_ROOT_WGT_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x84) /* LB_ROOT_WGT */ +#define CSR_ESCH_EPS_CSR_EPS_ECC_1BIT_ERR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x100) /* EPS 1bit ECC错误计数统计 */ +#define CSR_ESCH_EPS_CSR_EPS_ECC_2BIT_ERR_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x104) /* EPS 2bit ECC错误计数统计 */ +#define CSR_ESCH_EPS_CSR_EPS_DQS_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x108) /* 出队次数统计 */ +#define CSR_ESCH_EPS_CSR_EPS_EQS_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x10C) /* 入队次数统计 */ +#define CSR_ESCH_EPS_CSR_EPS_FIFO_CNT_REG (CSR_ESCH_EPS_CSR_BASE + 0x110) /* EPS FIFO当前深度 */ +#define CSR_ESCH_EPS_CSR_EPS_INNER_ERR_ST_REG (CSR_ESCH_EPS_CSR_BASE + 0x114) /* EPS 内部错误状态 */ + +/* ESCH_HPS_CSR Base address of Module's Register */ +#define CSR_ESCH_HPS_CSR_BASE (0xA000) + +/* **************************************************************************** */ +/* ESCH_HPS_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_ESCH_HPS_CSR_HPS_INDRECT_CTRL_REG (CSR_ESCH_HPS_CSR_BASE + 0x0) /* 间接访问寄存器 */ +#define CSR_ESCH_HPS_CSR_HPS_INDRECT_TIMEOUT_REG (CSR_ESCH_HPS_CSR_BASE + 0x4) /* 间接访问寄存器 */ +#define CSR_ESCH_HPS_CSR_HPS_INDRECT_DATA_REG (CSR_ESCH_HPS_CSR_BASE + 0x8) /* 间接访问寄存器 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_CPPI_SHAP_TYPE_CFG_REG \ + (CSR_ESCH_HPS_CSR_BASE + 0x14) /* HPS CPPI PORT SHAPER整形类型配置寄存器 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_SOFT_BP_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x18) /* HPS PORT节点软反压配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_SHAP_TYPE_CFG_REG \ + (CSR_ESCH_HPS_CSR_BASE + 0x1C) /* HPS CPPI PORT SHAPER整形类型配置寄存器 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_UPQ_SHAP_TYPE_CFG_REG \ + (CSR_ESCH_HPS_CSR_BASE + 0x60) /* HPS UP QUEUE SHAPER整形类型配置寄存器 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ALL_ROOT_WGT_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x100) /* ROOT DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_CIR_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x104) /* Normal RootCIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_ROOT_CIR_CFG_REG (CSR_ESCH_HPS_CSR_BASE + 0x108) /* loopback RootCIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x110) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x114) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x118) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x11C) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x120) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x124) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x128) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x12C) /* LB Port DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x130) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x134) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x138) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x13C) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x140) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x144) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x148) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x14C) /* LB Port CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x150) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x154) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x158) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x15C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x160) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x164) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x168) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x16C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x170) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x174) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x178) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x17C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x180) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x184) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x188) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x18C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x190) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x194) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x198) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x19C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x1A0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x1A4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x1A8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x1AC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x1B0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x1B4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x1B8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x1BC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x1C0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x1C4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x1C8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x1CC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x1D0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x1D4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x1D8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x1DC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x1E0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x1E4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x1E8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x1EC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x1F0) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x1F4) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x1F8) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x1FC) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x200) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x204) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x208) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x20C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x210) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x214) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x218) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x21C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x220) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x224) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x228) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x22C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x230) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x234) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x238) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x23C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x240) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x244) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x248) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CFG_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x24C) /* LB Queue DWRR权重配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x250) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x254) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x258) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x25C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x260) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x264) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x268) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x26C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x270) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x274) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x278) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x27C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x280) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x284) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x288) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x28C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x290) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x294) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x298) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x29C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x2A0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x2A4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x2A8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x2AC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x2B0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x2B4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x2B8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x2BC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x2C0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x2C4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x2C8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x2CC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x2D0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x2D4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x2D8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x2DC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x2E0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x2E4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x2E8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x2EC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x2F0) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x2F4) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x2F8) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x2FC) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x300) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x304) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x308) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x30C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x310) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x314) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x318) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x31C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x320) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x324) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x328) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x32C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x330) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x334) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x338) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x33C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x340) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x344) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x348) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_CFG_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x34C) /* LB Queue CIR配置 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_WGT_CNT_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x400) /* ROOT级 DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_WGT_CNT_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x404) /* ROOT级 DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x410) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x414) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x418) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x41C) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x420) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x424) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x428) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_WGT_CNT_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x42C) /* LB_P DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x430) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x434) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x438) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x43C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x440) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x444) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x448) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x44C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x450) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x454) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x458) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x45C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x460) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x464) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x468) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x46C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x470) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x474) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x478) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x47C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x480) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x484) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x488) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x48C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x490) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x494) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x498) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x49C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x4A0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x4A4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x4A8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x4AC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x4B0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x4B4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x4B8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x4BC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x4C0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x4C4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x4C8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x4CC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x4D0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x4D4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x4D8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x4DC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x4E0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x4E4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x4E8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x4EC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x4F0) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x4F4) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x4F8) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x4FC) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x500) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x504) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x508) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x50C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x510) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x514) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x518) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x51C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x520) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x524) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x528) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_WGT_CNT_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x52C) /* LB_Q DWRR WGT CNT */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_CIR_TOKEN_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x530) /* ROOT CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ROOT_CIR_TOKEN_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x534) /* ROOT CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x540) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x544) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x548) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x54C) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x550) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x554) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x558) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_P_CIR_TOKEN_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x55C) /* LB_P CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_0_REG (CSR_ESCH_HPS_CSR_BASE + 0x560) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_1_REG (CSR_ESCH_HPS_CSR_BASE + 0x564) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_2_REG (CSR_ESCH_HPS_CSR_BASE + 0x568) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_3_REG (CSR_ESCH_HPS_CSR_BASE + 0x56C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_4_REG (CSR_ESCH_HPS_CSR_BASE + 0x570) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_5_REG (CSR_ESCH_HPS_CSR_BASE + 0x574) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_6_REG (CSR_ESCH_HPS_CSR_BASE + 0x578) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_7_REG (CSR_ESCH_HPS_CSR_BASE + 0x57C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_8_REG (CSR_ESCH_HPS_CSR_BASE + 0x580) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_9_REG (CSR_ESCH_HPS_CSR_BASE + 0x584) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_10_REG (CSR_ESCH_HPS_CSR_BASE + 0x588) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_11_REG (CSR_ESCH_HPS_CSR_BASE + 0x58C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_12_REG (CSR_ESCH_HPS_CSR_BASE + 0x590) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_13_REG (CSR_ESCH_HPS_CSR_BASE + 0x594) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_14_REG (CSR_ESCH_HPS_CSR_BASE + 0x598) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_15_REG (CSR_ESCH_HPS_CSR_BASE + 0x59C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_16_REG (CSR_ESCH_HPS_CSR_BASE + 0x5A0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_17_REG (CSR_ESCH_HPS_CSR_BASE + 0x5A4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_18_REG (CSR_ESCH_HPS_CSR_BASE + 0x5A8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_19_REG (CSR_ESCH_HPS_CSR_BASE + 0x5AC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_20_REG (CSR_ESCH_HPS_CSR_BASE + 0x5B0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_21_REG (CSR_ESCH_HPS_CSR_BASE + 0x5B4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_22_REG (CSR_ESCH_HPS_CSR_BASE + 0x5B8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_23_REG (CSR_ESCH_HPS_CSR_BASE + 0x5BC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_24_REG (CSR_ESCH_HPS_CSR_BASE + 0x5C0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_25_REG (CSR_ESCH_HPS_CSR_BASE + 0x5C4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_26_REG (CSR_ESCH_HPS_CSR_BASE + 0x5C8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_27_REG (CSR_ESCH_HPS_CSR_BASE + 0x5CC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_28_REG (CSR_ESCH_HPS_CSR_BASE + 0x5D0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_29_REG (CSR_ESCH_HPS_CSR_BASE + 0x5D4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_30_REG (CSR_ESCH_HPS_CSR_BASE + 0x5D8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_31_REG (CSR_ESCH_HPS_CSR_BASE + 0x5DC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_32_REG (CSR_ESCH_HPS_CSR_BASE + 0x5E0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_33_REG (CSR_ESCH_HPS_CSR_BASE + 0x5E4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_34_REG (CSR_ESCH_HPS_CSR_BASE + 0x5E8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_35_REG (CSR_ESCH_HPS_CSR_BASE + 0x5EC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_36_REG (CSR_ESCH_HPS_CSR_BASE + 0x5F0) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_37_REG (CSR_ESCH_HPS_CSR_BASE + 0x5F4) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_38_REG (CSR_ESCH_HPS_CSR_BASE + 0x5F8) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_39_REG (CSR_ESCH_HPS_CSR_BASE + 0x5FC) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_40_REG (CSR_ESCH_HPS_CSR_BASE + 0x600) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_41_REG (CSR_ESCH_HPS_CSR_BASE + 0x604) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_42_REG (CSR_ESCH_HPS_CSR_BASE + 0x608) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_43_REG (CSR_ESCH_HPS_CSR_BASE + 0x60C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_44_REG (CSR_ESCH_HPS_CSR_BASE + 0x610) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_45_REG (CSR_ESCH_HPS_CSR_BASE + 0x614) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_46_REG (CSR_ESCH_HPS_CSR_BASE + 0x618) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_47_REG (CSR_ESCH_HPS_CSR_BASE + 0x61C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_48_REG (CSR_ESCH_HPS_CSR_BASE + 0x620) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_49_REG (CSR_ESCH_HPS_CSR_BASE + 0x624) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_50_REG (CSR_ESCH_HPS_CSR_BASE + 0x628) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_51_REG (CSR_ESCH_HPS_CSR_BASE + 0x62C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_52_REG (CSR_ESCH_HPS_CSR_BASE + 0x630) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_53_REG (CSR_ESCH_HPS_CSR_BASE + 0x634) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_54_REG (CSR_ESCH_HPS_CSR_BASE + 0x638) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_55_REG (CSR_ESCH_HPS_CSR_BASE + 0x63C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_56_REG (CSR_ESCH_HPS_CSR_BASE + 0x640) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_57_REG (CSR_ESCH_HPS_CSR_BASE + 0x644) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_58_REG (CSR_ESCH_HPS_CSR_BASE + 0x648) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_59_REG (CSR_ESCH_HPS_CSR_BASE + 0x64C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_60_REG (CSR_ESCH_HPS_CSR_BASE + 0x650) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_61_REG (CSR_ESCH_HPS_CSR_BASE + 0x654) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_62_REG (CSR_ESCH_HPS_CSR_BASE + 0x658) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_LB_Q_CIR_TOKEN_63_REG (CSR_ESCH_HPS_CSR_BASE + 0x65C) /* LB_Q CIR TOKEN数量 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ECC_1BIT_ERR_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x660) /* HPS 1bit ECC错误计数统计 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_ECC_2BIT_ERR_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x664) /* HPS 2bit ECC错误计数统计 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_DQS_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x668) /* 出队次数统计 */ +#define CSR_ESCH_HPS_CSR_ESCH_HPS_EQS_CNT_REG (CSR_ESCH_HPS_CSR_BASE + 0x66C) /* 入队次数统计 */ + +#endif // ESCH_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_addr_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_addr_define.h new file mode 100644 index 000000000..3461ea022 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_addr_define.h @@ -0,0 +1,384 @@ +#ifndef HI1823_CSR_SM_ADDR_DEFINE_H +#define HI1823_CSR_SM_ADDR_DEFINE_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* * __cplusplus */ + +/* * smrt_csr base address */ +#define CSR_SMRT_CSR_BASE_ADDR 0xa00 + +/* * SMRT_CSR address */ +#define CSR_SMRT_VERSION_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x0) +#define CSR_SMXR_CFG1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x4) +#define CSR_SMXR_CFG0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x8) +#define CSR_SMXT_CFG_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0xC) +#define CSR_SMXR_TM_GRT01_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x10) +#define CSR_SMXR_TM_GRT23_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x14) +#define CSR_SMRT_INT_VECTOR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x18) +#define CSR_SMRT_INT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x1C) +#define CSR_SMRT_INT_MASK_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x20) +#define CSR_SMXR_REQ_MEM_CRT_ERR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x24) +#define CSR_SMXR_REQ_MEM_UNCRT_ERR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x28) +#define CSR_SMXR_MISS_SOP_EOP_ERR_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x2C) +#define CSR_SMXR_INDRECT_CTRL_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x30) +#define CSR_SMXR_INDRECT_TIMEOUT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x34) +#define CSR_SMXR_INDRECT_DATA_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x38) +#define CSR_SMXT_CAP_CFG_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x3C) +#define CSR_SMXT_CAP_FIELD_CFG_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x40) +#define CSR_SMXT_CNT_CFG0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x44) +#define CSR_SMXT_CNT_CFG1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x48) +#define CSR_SMXT_CNT0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x4C) +#define CSR_SMXT_CNT1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x50) +#define CSR_SMXT_CNT2_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x54) +#define CSR_SMXT_CNT3_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x58) +#define CSR_SMXT_CRDT_CNT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x5C) +#define CSR_SMXT_FIFO_DEPTH0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x60) +#define CSR_SMXT_FIFO_DEPTH1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x68) +#define CSR_TL0_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x6C) +#define CSR_TL1_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x70) +#define CSR_RQST_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x74) +#define CSR_RSP_Q_DEP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x78) +#define CSR_RQST_CRDT_CNT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x7C) +#define CSR_RESP_CRDT_CNT_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x80) +#define CSR_SMXR_CNT0_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x84) +#define CSR_SMXR_CNT1_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x88) +#define CSR_SMXR_CNT2_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x8C) +#define CSR_SMXR_CNT3_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x90) +#define CSR_SMXT_CTP_ADDR (CSR_SMRT_CSR_BASE_ADDR + 0x94) +/* * smir_csr base address */ +#define CSR_SMIR_CSR_BASE_ADDR 0x100 + +/* * SMIR_CSR address */ +#define CSR_SMIR_VERSION_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x0) +#define CSR_SMIR_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x4) +#define CSR_SMIR_HASH_SEED0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x8) +#define CSR_SMIR_HASH_SEED1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xC) +#define CSR_SMIR_INT_VECTOR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x10) +#define CSR_SMIR_INT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x14) +#define CSR_SMIR_INT_MASK_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x18) +#define CSR_SMIR_ERR_SPEC_TH_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x1C) +#define CSR_SMIR_REQ_MSG_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x20) +#define CSR_SMIR_RESP_MSG_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x24) +#define CSR_SMIR_MEM_ECC_CRT_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x28) +#define CSR_SMIR_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x2C) +#define CSR_SMIR_INDRECT_CTRL_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x30) +#define CSR_SMIR_INDRECT_TIMEOUT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x34) +#define CSR_SMIR_INDRECT_DATA_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x38) +#define CSR_SMIR_CAP0_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x3C) +#define CSR_SMIR_CAP1_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x40) +#define CSR_SMIR_CAP2_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x44) +#define CSR_SMIR_CAP3_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x48) +#define CSR_SMIR_CAP4_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x4C) +#define CSR_SMIR_CAP6_CFG_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x50) +#define CSR_SMIR_EN_CNT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x54) +#define CSR_SMIR_CNT0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x58) +#define CSR_SMIR_CNT1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x5C) +#define CSR_SMIR_CNT2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x60) +#define CSR_SMIR_CRDT_CNT_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x64) +#define CSR_SMIR_CAP_FLIT0_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x68) +#define CSR_SMIR_CAP_FLIT0_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x70) +#define CSR_SMIR_CAP_FLIT1_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x78) +#define CSR_SMIR_CAP_FLIT1_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x80) +#define CSR_SMIR_CAP_FLIT2_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x88) +#define CSR_SMIR_CAP_FLIT2_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x90) +#define CSR_SMIR_CAP_FLIT3_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0x98) +#define CSR_SMIR_CAP_FLIT3_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xA0) +#define CSR_SMIR_CAP_FLIT4_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xA8) +#define CSR_SMIR_CAP_FLIT4_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xB0) +#define CSR_SMIR_CAP_FLIT5_DATA0_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xB8) +#define CSR_SMIR_CAP_FLIT5_DATA1_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xC0) +#define CSR_SMIR_CAP_FLIT0_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xC8) +#define CSR_SMIR_CAP_FLIT1_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xCC) +#define CSR_SMIR_CAP_FLIT2_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xD0) +#define CSR_SMIR_CAP_FLIT3_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xD4) +#define CSR_SMIR_CAP_FLIT4_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xD8) +#define CSR_SMIR_CAP_FLIT5_DATA2_ADDR (CSR_SMIR_CSR_BASE_ADDR + 0xDC) +/* * smeg0_abuf0_csr base address */ +#define CSR_SMEG0_ABUF0_CSR_BASE_ADDR 0x200 + +/* * SMEG0_ABUF0_CSR address */ +#define CSR_SMEG0_ABUF0_VERSION_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x0) +#define CSR_SM_ABUF_TH_GRW_WM_0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x4) +#define CSR_SM_ABUF_TH_GRW_WM_1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x8) +#define CSR_SM_ABUF_TH_GRW_WM_2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xC) +#define CSR_SM_ABUF_TH_GRW_WM_3_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x10) +#define CSR_SM_ABUF_TH_GRW_WM_4_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x14) +#define CSR_SM_ABUF_TH_GRW_WM_5_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x18) +#define CSR_SM_ABUF_TH_GRW_WM_6_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x1C) +#define CSR_SM_ABUF_TH_SHK_WM_0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x20) +#define CSR_SM_ABUF_TH_SHK_WM_1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x24) +#define CSR_SM_ABUF_TH_SHK_WM_2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x28) +#define CSR_SM_ABUF_TH_SHK_WM_3_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x2C) +#define CSR_SM_ABUF_TH_SHK_WM_4_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x30) +#define CSR_SM_ABUF_TH_SHK_WM_5_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x34) +#define CSR_SM_ABUF_TH_SHK_WM_6_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x38) +#define CSR_SM_ABUF_FLRC_ATTR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x3C) +#define CSR_SM_ABUF_FLRC_NUM_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x40) +#define CSR_SM_ABUF_FLRC_BOUND_U_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x44) +#define CSR_SM_ABUF_FLRC_BOUND_L_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x48) +#define CSR_SM_ABUF_PF_LIFO_CLR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x4C) +#define CSR_SM_ABUF_MEM_CFG_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x50) +#define CSR_SM_ABUF_INT_VECTOR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x54) +#define CSR_SM_ABUF_INT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x58) +#define CSR_SM_ABUF_INT_MASK_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x5C) +#define CSR_SM_ABUF_PBERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x60) +#define CSR_SM_ABUF_FL_UFLOW_ERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x64) +#define CSR_SM_ABUF_FL_OFLOW_ERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x68) +#define CSR_SM_ABUF_FL_TAIL_MISS_ERR_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x6C) +#define CSR_SMEG0_ABUF_INDRECT_CTRL_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x70) +#define CSR_SMEG0_ABUF_INDRECT_TIMEOUT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x74) +#define CSR_SMEG0_ABUF_INDRECT_DATA_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x78) +#define CSR_SM_ABUF_DIS_ALLOC_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x7C) +#define CSR_SM_ABUF_DIS_DE_ALLOC_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x80) +#define CSR_SM_ABUF_FLRC_ST_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x84) +#define CSR_SM_ABUF_EMPTY_FL_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x88) +#define CSR_SM_ABUF_FULL_FL_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x8C) +#define CSR_SM_ABUF_ST_WM_GROW_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x90) +#define CSR_SM_ABUF_ST_WM_SHRINK_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x94) +#define CSR_SM_ABUF_CNT_SEL0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x98) +#define CSR_SM_ABUF_CNT_SEL1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0x9C) +#define CSR_SM_ABUF_COUNTER0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xA0) +#define CSR_SM_ABUF_COUNTER1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xA4) +#define CSR_SM_ABUF_COUNTER2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xA8) +#define CSR_SM_ABUF_COUNTER3_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xAC) +#define CSR_SM_ABUF_COUNTER4_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xB0) +#define CSR_SM_ABUF_COUNTER5_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xB4) +#define CSR_SM_ABUF_PFETCH_FLAG_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xB8) +#define CSR_SM_ABUF_IREQ_LIST_STA_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xBC) +#define CSR_SM_ABUF_TAIL_MISS0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xC0) +#define CSR_SM_ABUF_TAIL_MISS1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xC8) +#define CSR_SM_ABUF_CNT_LIFO_PFETCH_0_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xD0) +#define CSR_SM_ABUF_CNT_LIFO_PFETCH_1_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xD8) +#define CSR_SM_ABUF_CNT_LIFO_PFETCH_2_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xE0) +#define CSR_SM_ABUF_ECC_CFG_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xE4) +#define CSR_SM_ABUF_ECC_1B_ERR_INT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xE8) +#define CSR_SM_ABUF_ECC_2B_ERR_INT_ADDR (CSR_SMEG0_ABUF0_CSR_BASE_ADDR + 0xEC) +/* * smeg0_aget_csr base address */ +#define CSR_SMEG0_AGET_CSR_BASE_ADDR 0x300 + +/* * SMEG0_AGET_CSR address */ +#define CSR_SMEG0_AGET_VERSION_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x0) +#define CSR_SMEG0_AGET_CFG_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x4) +#define CSR_SMEG0_AGET_INT_VECTOR_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x8) +#define CSR_SMEG0_AGET_INT_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0xC) +#define CSR_SMEG0_AGET_INT_MASK_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x10) +#define CSR_SMEG0_AGET_MEM_PRTY_ERR_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x14) +#define CSR_SMEG0_AGET_BOUNDARY_ERR_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x18) +#define CSR_SMEG0_AGET_INDRECT_CTRL_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x1C) +#define CSR_SMEG0_AGET_INDRECT_TIMEOUT_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x20) +#define CSR_SMEG0_AGET_INDRECT_DATA_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x24) +#define CSR_SMEG_CORE_MEM_INIT_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x28) +#define CSR_SMEG0_CNT0_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x2C) +#define CSR_SMEG0_CNT1_ADDR (CSR_SMEG0_AGET_CSR_BASE_ADDR + 0x30) +/* * smeg0_lu_csr base address */ +#define CSR_SMEG0_LU_CSR_BASE_ADDR 0x400 + +/* * SMEG0_LU_CSR address */ +#define CSR_SMEG0_LU_VERSION_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x0) +#define CSR_SMEG0_LU_CHK_ENABLE_CFG_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x4) +#define CSR_SMEG0_LU_INT_VECTOR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x8) +#define CSR_SMEG0_LU_INT_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0xC) +#define CSR_SMEG0_LU_INT_MASK_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x10) +#define CSR_SMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x14) +#define CSR_SMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x18) +#define CSR_SMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x1C) +#define CSR_SMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x20) +#define CSR_SMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x24) +#define CSR_SMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x28) +#define CSR_SMEG0_LU_SW_ERR_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x2C) +#define CSR_SMEG0_LU_INDRECT_CTRL_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x30) +#define CSR_SMEG0_LU_INDRECT_TIMEOUT_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x34) +#define CSR_SMEG0_LU_INDRECT_DATA_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x38) +#define CSR_SMEG0_LU_ERR_INJ_CFG_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x3C) +#define CSR_SMEG0_LU_CNT_CFG_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x40) +#define CSR_SMEG0_LU_CNT0_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x44) +#define CSR_SMEG0_LU_CNT1_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x48) +#define CSR_SMEG0_LU_CNT2_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x4C) +#define CSR_SMEG0_LU_CNT3_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x50) +#define CSR_SMEG0_LU_CTP_ADDR (CSR_SMEG0_LU_CSR_BASE_ADDR + 0x54) +/* * smeg1_csr base address */ +#define CSR_SMEG1_CSR_BASE_ADDR 0x500 + +/* * SMEG1_CSR address */ +#define CSR_SMEG1_VERSION_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x0) +#define CSR_SMEG1_CFG0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x4) +#define CSR_SMEG1_CFG1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x8) +#define CSR_SMEG1_RUNAWAY_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xC) +#define CSR_SMEG1_THREAD_ENABLE_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x10) +#define CSR_SMEG1_TM_TS_FAST2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x14) +#define CSR_SMEG1_TM_TS_FAST3_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x18) +#define CSR_SMEG1_TM_TS_SLOW0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x1C) +#define CSR_SMEG1_TM_TS_SLOW1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x20) +#define CSR_SMEG1_TM_TMT_CFG7_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x24) +#define CSR_SMEG1_TM_TMT_CFG6_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x28) +#define CSR_SMEG1_TM_TMT_CFG5_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x2C) +#define CSR_SMEG1_TM_TMT_CFG4_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x30) +#define CSR_SMEG1_TM_TMT_CFG3_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x34) +#define CSR_SMEG1_TM_TMT_CFG2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x38) +#define CSR_SMEG1_TM_TMT_CFG1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x3C) +#define CSR_SMEG1_TM_TMT_CFG0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x40) +#define CSR_SMEG1_INT_VECTOR_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x44) +#define CSR_SMEG1_INT_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x48) +#define CSR_SMEG1_INT_MASK_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x4C) +#define CSR_SMEG1_ENGINE_SW_ERR_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x50) +#define CSR_SMEG1_ERR0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x54) +#define CSR_SMEG1_ERR0_MASK_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x58) +#define CSR_SMEG1_ERR1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x5C) +#define CSR_SMEG1_ERR1_MASK_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x60) +#define CSR_SMEG1_INDRECT_CTRL_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x64) +#define CSR_SMEG1_INDRECT_TIMEOUT_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x68) +#define CSR_SMEG1_INDRECT_DATA_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x6C) +#define CSR_SMEG1_CNT_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x70) +#define CSR_SMEG1_CNT_MATCH_ID_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x74) +#define CSR_SMEG1_CNT0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x78) +#define CSR_SMEG1_CNT1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x80) +#define CSR_SMEG1_CNT2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x88) +#define CSR_SMEG1_CNT3_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x90) +#define CSR_SMEG1_TCD_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x98) +#define CSR_SMEG1_RUNAWAY_THD_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0x9C) +#define CSR_SMEG1_CTP0_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xA0) +#define CSR_SMEG1_CTP1_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xA8) +#define CSR_SMEG1_CTP2_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xB0) +#define CSR_SMEG1_TMT_EXT_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xB4) +#define CSR_SMEG1_MEM_ECC_ERR_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xB8) +#define CSR_SMMC_CACHE_RESOURCE_CTP_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xBC) +#define CSR_SMEG1_SYNC_API_CFG_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xC0) +#define CSR_SMEG1_CUR_TIMESTAMP_US_ADDR (CSR_SMEG1_CSR_BASE_ADDR + 0xC8) +/* * smit_csr base address */ +#define CSR_SMIT_CSR_BASE_ADDR 0x600 + +/* * SMIT_CSR address */ +#define CSR_SMIT_VERSION_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x0) +#define CSR_SMIT_CFG_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x4) +#define CSR_SMIT_INT_VECTOR_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x8) +#define CSR_SMIT_INT_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0xC) +#define CSR_SMIT_INT_MASK_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x10) +#define CSR_SMIT_ERR_PRTY_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x14) +#define CSR_SMIT_MEM_ECC_CRT_ERR_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x18) +#define CSR_SMIT_MEM_ECC_UNCRT_ERR_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x1C) +#define CSR_SMIT_INDRECT_CTRL_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x20) +#define CSR_SMIT_INDRECT_TIMEOUT_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x24) +#define CSR_SMIT_INDRECT_DATA_ADDR (CSR_SMIT_CSR_BASE_ADDR + 0x28) +/* * smlc_csr base address */ +#define CSR_SMLC_CSR_BASE_ADDR 0x700 + +/* * SMLC_CSR address */ +#define CSR_SMLC_VERSION_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x0) +#define CSR_SMLC_CFG0_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x4) +#define CSR_SMLC_CFG1_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x8) +#define CSR_SMLC_CFG2_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0xC) +#define CSR_SMLC_INT_VECTOR_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x10) +#define CSR_SMLC_INT_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x14) +#define CSR_SMLC_INT_MASK_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x18) +#define CSR_SMLC_SRF_OV_ERR_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x1C) +#define CSR_SMLC_ECC_ERR_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x24) +#define CSR_SMLC_ECC_ERRPR_MASK_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x28) +#define CSR_SMLC_INDRECT_CTRL_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x2C) +#define CSR_SMLC_INDRECT_TIMEOUT_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x30) +#define CSR_SMLC_INDRECT_DATA_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x34) +#define CSR_SMLC_CNT0_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x38) +#define CSR_SMLC_CNT1_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x40) +#define CSR_SMLC_CNT2_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x48) +#define CSR_SMLC_CNT3_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x50) +#define CSR_SMLC_CNT_CFG0_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x58) +#define CSR_SMLC_CNT_CFG1_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x5C) +#define CSR_SMLC_CREDIT_CTP_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x60) +#define CSR_SMLC_FIFO_DEPTH_CTP_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x64) +#define CSR_SMLC_ECC_ERR_CTP_ADDR (CSR_SMLC_CSR_BASE_ADDR + 0x68) +/* * smmc_f_csr base address */ +#define CSR_SMMC_F_CSR_BASE_ADDR 0x800 + +/* * SMMC_F_CSR address */ +#define CSR_SMMC_F_VERSION_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x0) +#define CSR_SMMC_F_MC_CFG_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x4) +#define CSR_SMMC_F_MC_CFG1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x8) +#define CSR_SMMC_HASH_SEED0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xC) +#define CSR_SMMC_HASH_SEED1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x10) +#define CSR_SMMC_F_CFG_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x14) +#define CSR_SMMC_F_MC_INIT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x18) +#define CSR_SMMC_F_MC_RF_TIMEOUT_INTERVAL_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x1C) +#define CSR_SMMC_F_INT_VECTOR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x20) +#define CSR_SMMC_F_INT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x24) +#define CSR_SMMC_F_INT_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x28) +#define CSR_SMMC_F_MC_CACHE_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x2C) +#define CSR_SMMC_F_MC_CACHE_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x30) +#define CSR_SMMC_F_MC_CACHE_ERR_INFO_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x34) +#define CSR_SMMC_F_BUFFER_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x38) +#define CSR_SMMC_F_BUFFER_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x3C) +#define CSR_SMMC_F_BUFFER_ERR_INFO_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x40) +#define CSR_SMMC_F_MC_RF_RTN_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x44) +#define CSR_SMMC_F_MC_RF_TIMEOUT_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x48) +#define CSR_SMMC_F_MC_MULTI_HIT_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x4C) +#define CSR_SMMC_F_VC_CACHE_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x50) +#define CSR_SMMC_F_VC_CACHE_MASK_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x54) +#define CSR_SMMC_F_VC_CACHE_ERR_INFO_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x58) +#define CSR_SMMC_F_INDRECT_CTRL_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x5C) +#define CSR_SMMC_F_INDRECT_TIMEOUT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x60) +#define CSR_SMMC_F_INDRECT_DATA_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x64) +#define CSR_SMMC_F_MC_CNT_ENB_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x68) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x6C) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x70) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x74) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x78) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL2_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x7C) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL3_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x80) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL4_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x84) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL5_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x88) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL6_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x8C) +#define CSR_SMMC_F_MC_CNT_EVENT_SEL7_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x90) +#define CSR_SMMC_F_MC_STATUS_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x94) +#define CSR_SMMC_F_MC_CNT0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0x98) +#define CSR_SMMC_F_MC_CNT1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xA0) +#define CSR_SMMC_F_MC_CNT2_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xA8) +#define CSR_SMMC_F_MC_CNT3_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xB0) +#define CSR_SMMC_F_MC_CNT4_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xB8) +#define CSR_SMMC_F_MC_CNT5_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xC0) +#define CSR_SMMC_F_MC_CNT6_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xC8) +#define CSR_SMMC_F_MC_CNT7_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xD0) +#define CSR_SMMC_F_VC_FIFO_DEPTH0_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xD8) +#define CSR_SMMC_F_VC_FIFO_DEPTH1_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xDC) +#define CSR_SMMC_F_MC_FIFO1_DEPTH_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xE0) +#define CSR_SMMC_F_MC_FIFO2_DEPTH_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xE4) +#define CSR_SMMC_F_ERR_INJ_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xE8) +#define CSR_SMMC_F_GPA_TRANS_ERR_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xEC) +#define CSR_SMMC_F_QU_INTF_CNT_CFG_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xF0) +#define CSR_SMMC_F_QU_INTF_RX_CNT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xF4) +#define CSR_SMMC_F_QU_INTF_TX_CNT_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xF8) +#define CSR_SMMC_F_MC_CFG2_ADDR (CSR_SMMC_F_CSR_BASE_ADDR + 0xFC) +/* * smmc_l_csr base address */ +#define CSR_SMMC_L_CSR_BASE_ADDR 0x900 + +/* * SMMC_L_CSR address */ +#define CSR_SMMC_L_VERSION_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x0) +#define CSR_SMMC_L_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x4) +#define CSR_SMMC_L_STAT_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x8) +#define CSR_SMMC_L_INT_VECTOR_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0xC) +#define CSR_SMMC_L_INT_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x10) +#define CSR_SMMC_L_INT_MASK_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x14) +#define CSR_SMMC_L_MEM_ERR_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x18) +#define CSR_SMMC_L_MEM_ERR_MASK_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x1C) +#define CSR_SMMC_L_MEM_ERR_INFO_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x20) +#define CSR_SMMC_L_INDRECT_CTRL_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x24) +#define CSR_SMMC_L_INDRECT_TIMEOUT_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x28) +#define CSR_SMMC_L_INDRECT_DATA_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x2C) +#define CSR_SMMC_L_CNT_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x30) +#define CSR_SMMC_L_CNT_MATCH_BANK_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x34) +#define CSR_SMMC_L_CNT_MATCH_INSTANCE_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x38) +#define CSR_SMMC_L_CNT0_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x3C) +#define CSR_SMMC_L_CNT1_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x40) +#define CSR_SMMC_L_CNT2_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x44) +#define CSR_SMMC_L_CNT3_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x48) +#define CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP0_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x4C) +#define CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP1_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x50) +#define CSR_SMMC_L_ECC_INJ_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x54) +#define CSR_SMMC_L_PG_CFG_ADDR (CSR_SMMC_L_CSR_BASE_ADDR + 0x58) +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* * __cplusplus */ + +#endif /* * HI1823_CSR_SM_ADDR_DEFINE_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_typedef.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_typedef.h new file mode 100644 index 000000000..8fe38dabe --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hi1823_csr_sm_typedef.h @@ -0,0 +1,12259 @@ +#ifndef HI1823_CSR_SM_TYPEDEF_H +#define HI1823_CSR_SM_TYPEDEF_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* * __cplusplus */ + +/* ** + * Union name : SMRT_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmrtVersion { + struct tagStSmrtVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smrtVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smrtVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMRT_VERSION_U; + +/* ** + * Union name : SMXR_CFG1 + * @brief SMXR cofigure registers + * Description: + */ +typedef union tagUnSmxrCfg1 { + struct tagStSmxrCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int rpUncrtErrInjReq : 1; /* * [31:31]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory.Enable memory check, when use this err + inection function. */ + unsigned int rpCrtErrInjReq : 1; /* * [30:30]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int rpSmUncrtErrMask : 7; /* * [29:23]Fatal Error Mask.For SMLbit[0]：smxt fatal error + mask;bit[1]：smmc_l fatal error maskbit[2]：smeg_core fatal error + maskbit[3~6]：Reserved.For SMFbit[0]：smxr fatal e rror mask;bit[1]：smxt fatal + error mask;bit[2]：smmc_f fatal error maskbit[3]：smeg_core 3 fatal error + maskbit[4]：smeg_core 2 fatal error maskbit[5]：smeg_core 1 fa tal error + maskbit[6]：smeg_core 0 fatal error mask7 fatal error source for SMF and 3 fatal + error source for SML, SW can mask the fatal error of each source respe + ctively.1'b0: Mask the fatal error;1'b1: Unmask the fatal error */ + unsigned int rpSmUncrtErrClr : 1; /* * [22:22]Clr the Fatal error of SML/SMF.SW can write 0 then 1 to generate a + * rising edge to clear the fatal error + */ + unsigned int tifoePftchWqeNum : 2; /* * [21:20]TIFOE pre-fetch API pre-fetch WQE number */ + unsigned int tifoePftchCtl : 2; /* * [19:18]TIFOE pre-fetch API control bit2:1;For details, please refer to + * description of TIFOE prefetch API in Hi1822V100 FS SMF API.docx + */ + unsigned int reserved0 : 1; /* * [17:17]reserved */ + unsigned int memRet1n : 1; /* * [16:16]control of memory pin RET1N */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int iwarpPiCopyEnb : 1; /* * [7:7]IWARP PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int rocePiCopyEnb : 1; /* * [6:6]ROCE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int tifoePiCopyEnb : 1; /* * [5:5]TIFOE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int reserved1 : 2; /* * [4:3]reserved */ + unsigned int smxrCntSel : 2; /* * [2:1]smxr cnt source select:2'b00: Count disable2'b01: Count number of API + segment smxr received;2'b10: Count number of messages smxr received2'b11: Count number + of flitssmxr received */ + unsigned int memChkEn : 1; /* * [0:0]memory check enable.1'b0:disable all memories err check.1'b1:enable all + * memories err check. + */ +#else + unsigned int memChkEn : 1; /* * [0:0]memory check enable.1'b0:disable all memories err check.1'b1:enable all + * memories err check. + */ + unsigned int smxrCntSel : 2; /* * [2:1]smxr cnt source select:2'b00: Count disable2'b01: Count number of API + segment smxr received;2'b10: Count number of messages smxr received2'b11: Count number + of flitssmxr received */ + unsigned int reserved1 : 2; /* * [4:3]reserved */ + unsigned int tifoePiCopyEnb : 1; /* * [5:5]TIFOE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int rocePiCopyEnb : 1; /* * [6:6]ROCE PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int iwarpPiCopyEnb : 1; /* * [7:7]IWARP PI copy enable:1'b0, not copy PI/PMSN from DB to pre-fetch + * API1'b1, copy PI/PMSN from DB to pre-fetch API if PI filed in DB is valid + */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [16:16]control of memory pin RET1N */ + unsigned int reserved0 : 1; /* * [17:17]reserved */ + unsigned int tifoePftchCtl : 2; /* * [19:18]TIFOE pre-fetch API control bit2:1;For details, please refer to + * description of TIFOE prefetch API in Hi1822V100 FS SMF API.docx + */ + unsigned int tifoePftchWqeNum : 2; /* * [21:20]TIFOE pre-fetch API pre-fetch WQE number */ + unsigned int rpSmUncrtErrClr : 1; /* * [22:22]Clr the Fatal error of SML/SMF.SW can write 0 then 1 to generate a + * rising edge to clear the fatal error + */ + unsigned int rpSmUncrtErrMask : 7; /* * [29:23]Fatal Error Mask.For SMLbit[0]：smxt fatal error + mask;bit[1]：smmc_l fatal error maskbit[2]：smeg_core fatal error + maskbit[3~6]：Reserved.For SMFbit[0]：smxr fatal e rror mask;bit[1]：smxt fatal + error mask;bit[2]：smmc_f fatal error maskbit[3]：smeg_core 3 fatal error + maskbit[4]：smeg_core 2 fatal error maskbit[5]：smeg_core 1 fa tal error + maskbit[6]：smeg_core 0 fatal error mask7 fatal error source for SMF and 3 fatal + error source for SML, SW can mask the fatal error of each source respe + ctively.1'b0: Mask the fatal error;1'b1: Unmask the fatal error */ + unsigned int rpCrtErrInjReq : 1; /* * [30:30]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int rpUncrtErrInjReq : 1; /* * [31:31]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory.Enable memory check, when use this err + inection function. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CFG1_U; + +/* ** + * Union name : SMXR_CFG0 + * @brief SMXR cofigure registers + * Description: + */ +typedef union tagUnSmxrCfg0 { + struct tagStSmxrCfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int rpFairnessNum : 16; /* * [31:16]This is the flit numbers to the same smeg_core before fairness + * scheme is execute + */ + unsigned int rpFairnessEn : 1; /* * [15:15]1: turn on XR arbiter fairness0: do not use XR arbiter fairness */ + unsigned int reserved : 1; /* * [14:14] */ + unsigned int rpLbQuLdWqe : 2; /* * [13:12]load balance for ROCE load WQE API from QU:2'b00 - to infra + * pipeline02'b01 - to infra pipeline12'b10 - to infra pipeline22'b11 - to infra + * pipeline3 + */ + unsigned int rpInstIdQuLdWqe : 5; /* * [11:7]instance id for ROCE load WQE API from QU */ + unsigned int rpLbMqm : 2; /* * [6:5]load balance for API from MQM:2'b00 - to infra pipeline02'b01 - to infra + * pipeline12'b10 - to infra pipeline22'b11 - to infra pipeline3 + */ + unsigned int rpInstIdMqm : 5; /* * [4:0]instance id for API from MQM */ +#else + unsigned int rpInstIdMqm : 5; /* * [4:0]instance id for API from MQM */ + unsigned int rpLbMqm : 2; /* * [6:5]load balance for API from MQM:2'b00 - to infra pipeline02'b01 - to infra + * pipeline12'b10 - to infra pipeline22'b11 - to infra pipeline3 + */ + unsigned int rpInstIdQuLdWqe : 5; /* * [11:7]instance id for ROCE load WQE API from QU */ + unsigned int rpLbQuLdWqe : 2; /* * [13:12]load balance for ROCE load WQE API from QU:2'b00 - to infra + * pipeline02'b01 - to infra pipeline12'b10 - to infra pipeline22'b11 - to infra + * pipeline3 + */ + unsigned int reserved : 1; /* * [14:14] */ + unsigned int rpFairnessEn : 1; /* * [15:15]1: turn on XR arbiter fairness0: do not use XR arbiter fairness */ + unsigned int rpFairnessNum : 16; /* * [31:16]This is the flit numbers to the same smeg_core before fairness + * scheme is execute + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CFG0_U; + +/* ** +* Union name : SMXT_CFG +* @brief This is the Smart Memory Infra Cross Transmission (SMXT) module configuration register. The +software use this register for debug. + +* Description: +*/ +typedef union tagUnSmxtCfg { + struct tagStSmxtCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved */ + unsigned int capStart : 1; /* * [6:6]capture api data start; a posedge of this signal triggle a capture action; + * start capture after all capture mode/match fields are configure + */ + unsigned int regCapChSel : 2; /* * [5:4]Capture data source selection.0: send captured message data from ring + request channel to capture data.1: send captured message data from ring response + channel t o capture data.2: RSV in SML; SMF: send captured message data from to_tile0 + channel to capture data.3: RSV in SML; SMF: send captured message data from to_tile1 + channel to capture data. */ + unsigned int disTxEgTl1 : 1; /* * [3:3]disable service for feature engine message transmission to tile1 direct + channel . This is for debug .1: disable.0: enable. Note:only used for debug,users + sh ould know the api counts before config this bit. */ + unsigned int disTxEgTl0 : 1; /* * [2:2]disable service for feature engine message transmission to tile0 direct + channel . This is for debug .1: disable.0: enable. Note:only used for debug,users + sh ould know the api counts before config this bit. */ + unsigned int disTxMc : 1; /* * [1:1]disable service for smmc message transmission . This is for debug .1: + disable.0: enable.Note:only used for debug,users should know the api counts before con + fig this bit. */ + unsigned int disTxEg : 1; /* * [0:0]disable service for feature engine message transmission to ting. This is for + debug .1: disable.0: enable. Note:only used for debug,users should know the api + counts before config this bit. */ +#else + unsigned int disTxEg : 1; /* * [0:0]disable service for feature engine message transmission to ting. This is for + debug .1: disable.0: enable. Note:only used for debug,users should know the api + counts before config this bit. */ + unsigned int disTxMc : 1; /* * [1:1]disable service for smmc message transmission . This is for debug .1: + disable.0: enable.Note:only used for debug,users should know the api counts before con + fig this bit. */ + unsigned int disTxEgTl0 : 1; /* * [2:2]disable service for feature engine message transmission to tile0 direct + channel . This is for debug .1: disable.0: enable. Note:only used for debug,users + sh ould know the api counts before config this bit. */ + unsigned int disTxEgTl1 : 1; /* * [3:3]disable service for feature engine message transmission to tile1 direct + channel . This is for debug .1: disable.0: enable. Note:only used for debug,users + sh ould know the api counts before config this bit. */ + unsigned int regCapChSel : 2; /* * [5:4]Capture data source selection.0: send captured message data from ring + request channel to capture data.1: send captured message data from ring response + channel t o capture data.2: RSV in SML; SMF: send captured message data from to_tile0 + channel to capture data.3: RSV in SML; SMF: send captured message data from to_tile1 + channel to capture data. */ + unsigned int capStart : 1; /* * [6:6]capture api data start; a posedge of this signal triggle a capture action; + * start capture after all capture mode/match fields are configure + */ + unsigned int reserved : 25; /* * [31:7]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CFG_U; + +/* ** + * Union name : SMXR_TM_GRT01 + * @brief Timer Group Routing table element 0 and 1 + * Description: + */ +typedef union tagUnSmxrTmGrt01 { + struct tagStSmxrTmGrt01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int rpTmGrt1 : 13; /* * [28:16]As same as configure for group0 */ + unsigned int reserved1 : 3; /* * [15:13]reserved */ + unsigned int rpTmGrt0 : 13; /* * [12:0]Timer routing table configure for group0:bit12:11 - Load balance factor + indicates which engine core this timer group is instanced to. 00: send to core 0 0 + 1: send to core 1 10: send to core 2 11: send to core 3bit10:9 - This timer group + belong to which hostbit8:5 - Indicates which PF this timer group is m apped into. + Default 0~15 is used as global PPF for up to 4 hostsbit4:0 - Indicates which instance + ID is for timer engine in target engine core. + */ +#else + unsigned int rpTmGrt0 : 13; /* * [12:0]Timer routing table configure for group0:bit12:11 - Load balance factor + indicates which engine core this timer group is instanced to. 00: send to core 0 0 + 1: send to core 1 10: send to core 2 11: send to core 3bit10:9 - This timer group + belong to which hostbit8:5 - Indicates which PF this timer group is m apped into. + Default 0~15 is used as global PPF for up to 4 hostsbit4:0 - Indicates which instance + ID is for timer engine in target engine core. + */ + unsigned int reserved1 : 3; /* * [15:13]reserved */ + unsigned int rpTmGrt1 : 13; /* * [28:16]As same as configure for group0 */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_TM_GRT01_U; + +/* ** + * Union name : SMXR_TM_GRT23 + * @brief Timer Group Routing table element 2 and 3 + * Description: + */ +typedef union tagUnSmxrTmGrt23 { + struct tagStSmxrTmGrt23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int rpTmGrt3 : 13; /* * [28:16]As same as configure for group0 */ + unsigned int reserved1 : 3; /* * [15:13]reserved */ + unsigned int rpTmGrt2 : 13; /* * [12:0]As same as configure for group0 */ +#else + unsigned int rpTmGrt2 : 13; /* * [12:0]As same as configure for group0 */ + unsigned int reserved1 : 3; /* * [15:13]reserved */ + unsigned int rpTmGrt3 : 13; /* * [28:16]As same as configure for group0 */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_TM_GRT23_U; + +/* ** + * Union name : SMRT_INT_VECTOR + * @brief + * Description: + */ +typedef union tagUnSmrtIntVector { + struct tagStSmrtIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMRT_INT_VECTOR_U; + +/* ** + * Union name : SMRT_INT + * @brief SMRT interrupt data + * Description: + */ +typedef union tagUnSmrtInt { + struct tagStSmrtInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMRT_INT_U; + +/* ** + * Union name : SMRT_INT_MASK + * @brief SMIR interrupt mask configuration + * Description: + */ +typedef union tagUnSmrtIntMask { + struct tagStSmrtIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMRT_INT_MASK_U; + +/* ** + * Union name : SMXR_REQ_MEM_CRT_ERR + * @brief ECC correctable memory detected on SMXR request memory + * Description: + */ +typedef union tagUnSmxrReqMemCrtErr { + struct tagStSmxrReqMemCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1 + req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1 + req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_REQ_MEM_CRT_ERR_U; + +/* ** + * Union name : SMXR_REQ_MEM_UNCRT_ERR + * @brief ECC un-correctable memory detected on SMXR request memory + * Description: + */ +typedef union tagUnSmxrReqMemUncrtErr { + struct tagStSmxrReqMemUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1 + req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error sourceBit0: error is detected on tile0 req_mem bit1: error is detected on til e1 + req_membit7:2: error addressbit13:8: error addressbit29:14: reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_REQ_MEM_UNCRT_ERR_U; + +/* ** + * Union name : SMXR_MISS_SOP_EOP_ERR + * @brief SMXR received miss EOP API + * Description: + */ +typedef union tagUnSmxrMissSopEopErr { + struct tagStSmxrMissSopEopErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.31:25 + - thread id;24:19 - src_tag_h;18:14 - src;13:8 - rsv ;7 - tile16 - tile05 + - ring resp4 - ring rqst3 - miss eop2 - miss sop */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.31:25 + - thread id;24:19 - src_tag_h;18:14 - src;13:8 - rsv ;7 - tile16 - tile05 + - ring resp4 - ring rqst3 - miss eop2 - miss sop */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_MISS_SOP_EOP_ERR_U; + +/* ** + * Union name : SMXR_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmxrIndrectCtrl { + struct tagStSmxrIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smxrIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smxrIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smxrIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: DBLB(Doorbeel + * loadbalance table), only in SMF4'b0001: API_CAP: SMXT capture API data （read + * only）others:reserved + */ + unsigned int smxrIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.bit[5:0] memory address DBLB: only + bit 4:0 is v alidAPI_CAP: bit[5:2] flit number, bit[1:0] API DW: 00-flit[127:96], + 01-flit[95:64], 10-flit[63:32], 11-flit[31:0] + */ +#else + unsigned int smxrIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.bit[5:0] memory address DBLB: only + bit 4:0 is v alidAPI_CAP: bit[5:2] flit number, bit[1:0] API DW: 00-flit[127:96], + 01-flit[95:64], 10-flit[63:32], 11-flit[31:0] + */ + unsigned int smxrIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: DBLB(Doorbeel + * loadbalance table), only in SMF4'b0001: API_CAP: SMXT capture API data （read + * only）others:reserved + */ + unsigned int smxrIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smxrIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smxrIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_INDRECT_CTRL_U; + +/* ** + * Union name : SMXR_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmxrIndrectTimeout { + struct tagStSmxrIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smxrIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMXR_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmxrIndrectData { + struct tagStSmxrIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smxrIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_INDRECT_DATA_U; + +/* ** +* Union name : SMXT_CAP_CFG +* @brief smxt capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per field via <cap_sel _en> +in <smxr_en_cnt> ) +* Description: +*/ +typedef union tagUnSmxtCapCfg { + struct tagStSmxtCapCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int capMode : 1; /* * [31:31]capture mode control register. 0:capture mode disable.smir will not + capture any message.1:capture mode enable.smir will compare the selected fields,only the + mes sages matched with all selected fields will be captured. */ + unsigned int reserved : 17; /* * [30:14] */ + unsigned int flit0127123Msk : 5; /* * [13:9]flit0 bit127~bit123 capture mask. 1:corresponding bit must match + * when capture.0:don't care whether corresponding bit match when capture. + */ + unsigned int flit0127123 : 5; /* * [8:4]flit0 bit127~bit123 field to capture . */ + unsigned int capDnidEn : 1; /* * [3:3]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_node_id> field match according field in message. 0 ,No need to match this field + .This field's capture valid.. + */ + unsigned int capThdIdEn : 1; /* * [2:2]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_thd_id> field in message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ + unsigned int capTagHEn : 1; /* * [1:1]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_tag_h> field i n message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ + unsigned int capTagLEn : 1; /* * [0:0]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_tag_l> field i n message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ +#else + unsigned int capTagLEn : 1; /* * [0:0]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_tag_l> field i n message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ + unsigned int capTagHEn : 1; /* * [1:1]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_tag_h> field i n message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ + unsigned int capThdIdEn : 1; /* * [2:2]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_thd_id> field in message match according field in message. 0 ,No need to match + this field .This field's capture valid.. + */ + unsigned int capDnidEn : 1; /* * [3:3]Condition fields enable according to match fields in registers + <SMXT_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + <dst_node_id> field match according field in message. 0 ,No need to match this field + .This field's capture valid.. + */ + unsigned int flit0127123 : 5; /* * [8:4]flit0 bit127~bit123 field to capture . */ + unsigned int flit0127123Msk : 5; /* * [13:9]flit0 bit127~bit123 capture mask. 1:corresponding bit must match + * when capture.0:don't care whether corresponding bit match when capture. + */ + unsigned int reserved : 17; /* * [30:14] */ + unsigned int capMode : 1; /* * [31:31]capture mode control register. 0:capture mode disable.smir will not + capture any message.1:capture mode enable.smir will compare the selected fields,only the + mes sages matched with all selected fields will be captured. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CAP_CFG_U; + +/* ** +* Union name : SMXT_CAP_FIELD_CFG +* @brief SMXT capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per field via <cap_sel _en> +in <smxr_en_cnt> ) +* Description: +*/ +typedef union tagUnSmxtCapFieldCfg { + struct tagStSmxtCapFieldCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 1; /* * [31:31]reserved */ + unsigned int dstNdId : 6; /* * [30:25]<dst_node_id> field to be matchedbit30 is RSV in 1822 */ + unsigned int dstThdId : 7; /* * [24:18]<dst_thd_id> field to be matched */ + unsigned int dstTagH : 6; /* * [17:12]<dst_tag_h> field to be matched. */ + unsigned int dstTagL : 12; /* * [11:0]<dst_tag_l> field to be matched.For response API, only match low 5 bit, + * which is src field for response API + */ +#else + unsigned int dstTagL : 12; /* * [11:0]<dst_tag_l> field to be matched.For response API, only match low 5 bit, + * which is src field for response API + */ + unsigned int dstTagH : 6; /* * [17:12]<dst_tag_h> field to be matched. */ + unsigned int dstThdId : 7; /* * [24:18]<dst_thd_id> field to be matched */ + unsigned int dstNdId : 6; /* * [30:25]<dst_node_id> field to be matchedbit30 is RSV in 1822 */ + unsigned int reserved : 1; /* * [31:31]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CAP_FIELD_CFG_U; + +/* ** +* Union name : SMXT_CNT_CFG0 +* @brief SMXT mappable event counter controal . The software use this control to configure expected +counter mapping . + +* Description: +*/ +typedef union tagUnSmxtCntCfg0 { + struct tagStSmxtCntCfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 7; /* * [31:25]reserved */ + unsigned int + smxtEnCnt1 : 9; /* * [24:16]Couter source select vector for physical counter2. software can configure this + register to decide which counter should be counted into physical counter 2.bit_8: counter + enable1'b0:disable counting.1'b1:enable counting.bit[7:6]: channel selection1'b0:this counter + will only count the request channel to ring.1'b1:this cou nter will only count the response + channel to ring.1'b2:this counter will only count the to_tile0 channel.1'b3:this counter will + only count the to_tile1 channel. bit_5:capture Conditional count enable . This is used for + debug .When Software enable this field, then only messages matched with capture condition + inside regiser < SMXT_cap_cfg> will trigger counting. Otherwise ,counter will be triggerd for + all kinds of messages . 1 : count only when message match capture trigge r condition.0 : count + for all messages.bit[4:0]:counter input selection,config one value to choose which type you + want count:5'h0:flits send out from smeg1 of i nfra 05'h1:messages send out from smeg1 of infra + 05'h2: flits send out from smeg1 of infra 15'h3: messages send out from smeg1 of infra + 15'h4:flits send out fro m smeg1 of infra 25'h5:messages send out from smeg1 of infra 25'h6: + flits send out from smeg1 of infra 35'h7: messages send out from smeg1 of infra 35'h8: flits + send out from smmc5'h9: messages send out from smmc 5'ha:the summation of flits from smeg1 + + smmc5'hb:the summation of messages from smeg1 + smmc5'hc:flits wit h E0 from smeg1 of infra + 0.5'hd:messages with E0 from smeg1 of infra 0. （counter when message EOP with E0）5'he:flits + with E0 from smeg1 of infra 1.5'hf:messages with E0 from smeg1 of infra 1. （counter when + message EOP with E0）5'h10:flits with E0 from smeg1 of infra 2.5'h11:messages with E0 from + smeg1 of infra 2.（counte r when message EOP with E0）5'h12:flits with E0 from smeg1 of + infra 3.5'h13:messages with E0 from smeg1 of infra 3.（counter when message EOP with + E0）5'h14:the su mmation of sop from smeg1+smmc out5'h15:the summation of eop from smeg1+smmc + out5'h16:sop send out from smeg1 infra 0.5'h17:eop send out from smeg1 infra 0.5'h1 8:sop send + out from smeg1 infra 1.5'h19:eop send out from smeg1 infra 1.5'h1a:sop send out from smeg1 + infra 2.5'h1b:eop send out from smeg1 infra 2.5'h1c:sop se nd out from smeg1 infra 3.5'h1d:eop + send out from smeg1 infra 3.5'h1e:sop send out from smmc5'h1f:eop send out from smmc + */ + unsigned int reserved1 : 7; /* * [15:9]reserved */ + unsigned int smxtEnCnt0 : 9; /* * [8:0]as same as SMXT_en_cnt_1 */ +#else + unsigned int smxtEnCnt0 : 9; /* * [8:0]as same as SMXT_en_cnt_1 */ + unsigned int reserved1 : 7; /* * [15:9]reserved */ + unsigned int + smxtEnCnt1 : 9; /* * [24:16]Couter source select vector for physical counter2. software can configure this + register to decide which counter should be counted into physical counter 2.bit_8: counter + enable1'b0:disable counting.1'b1:enable counting.bit[7:6]: channel selection1'b0:this counter + will only count the request channel to ring.1'b1:this cou nter will only count the response + channel to ring.1'b2:this counter will only count the to_tile0 channel.1'b3:this counter will + only count the to_tile1 channel. bit_5:capture Conditional count enable . This is used for + debug .When Software enable this field, then only messages matched with capture condition + inside regiser < SMXT_cap_cfg> will trigger counting. Otherwise ,counter will be triggerd for + all kinds of messages . 1 : count only when message match capture trigge r condition.0 : count + for all messages.bit[4:0]:counter input selection,config one value to choose which type you + want count:5'h0:flits send out from smeg1 of i nfra 05'h1:messages send out from smeg1 of infra + 05'h2: flits send out from smeg1 of infra 15'h3: messages send out from smeg1 of infra + 15'h4:flits send out fro m smeg1 of infra 25'h5:messages send out from smeg1 of infra 25'h6: + flits send out from smeg1 of infra 35'h7: messages send out from smeg1 of infra 35'h8: flits + send out from smmc5'h9: messages send out from smmc 5'ha:the summation of flits from smeg1 + + smmc5'hb:the summation of messages from smeg1 + smmc5'hc:flits wit h E0 from smeg1 of infra + 0.5'hd:messages with E0 from smeg1 of infra 0. （counter when message EOP with E0）5'he:flits + with E0 from smeg1 of infra 1.5'hf:messages with E0 from smeg1 of infra 1. （counter when + message EOP with E0）5'h10:flits with E0 from smeg1 of infra 2.5'h11:messages with E0 from + smeg1 of infra 2.（counte r when message EOP with E0）5'h12:flits with E0 from smeg1 of + infra 3.5'h13:messages with E0 from smeg1 of infra 3.（counter when message EOP with + E0）5'h14:the su mmation of sop from smeg1+smmc out5'h15:the summation of eop from smeg1+smmc + out5'h16:sop send out from smeg1 infra 0.5'h17:eop send out from smeg1 infra 0.5'h1 8:sop send + out from smeg1 infra 1.5'h19:eop send out from smeg1 infra 1.5'h1a:sop send out from smeg1 + infra 2.5'h1b:eop send out from smeg1 infra 2.5'h1c:sop se nd out from smeg1 infra 3.5'h1d:eop + send out from smeg1 infra 3.5'h1e:sop send out from smmc5'h1f:eop send out from smmc + */ + unsigned int reserved0 : 7; /* * [31:25]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT_CFG0_U; + +/* ** +* Union name : SMXT_CNT_CFG1 +* @brief SMXT mappable event counter controal . The software use this control to configure expected +counter mapping . + +* Description: +*/ +typedef union tagUnSmxtCntCfg1 { + struct tagStSmxtCntCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 7; /* * [31:25]reserved */ + unsigned int smxtEnCnt3 : 9; /* * [24:16]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */ + unsigned int reserved1 : 7; /* * [15:9]reserved */ + unsigned int smxtEnCnt2 : 9; /* * [8:0]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */ +#else + unsigned int smxtEnCnt2 : 9; /* * [8:0]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */ + unsigned int reserved1 : 7; /* * [15:9]reserved */ + unsigned int smxtEnCnt3 : 9; /* * [24:16]as same as SMXT_CNT_CFG0.SMXT_en_cnt_1 */ + unsigned int reserved0 : 7; /* * [31:25]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT_CFG1_U; + +/* ** +* Union name : SMXT_CNT0 +* @brief SMXT physical counter 0.software can enable which events to be counted into it via field +<SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> . + +* Description: +*/ +typedef union tagUnSmxtCnt0 { + struct tagStSmxtCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxtCnt0 : 32; /* * [31:0]SMXT physical counter 0.software can enable which events to be counted + * into it via field <SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> . + */ +#else + unsigned int smxtCnt0 : 32; /* * [31:0]SMXT physical counter 0.software can enable which events to be counted + * into it via field <SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> . + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT0_U; + +/* ** +* Union name : SMXT_CNT1 +* @brief SMXT physical counter 1.software can enable which events to be counted into it via field +<SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> . + +* Description: +*/ +typedef union tagUnSmxtCnt1 { + struct tagStSmxtCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxtCnt1 : 32; /* * [31:0]SMXT physical counter 1.software can enable which events to be counted + * into it via field <SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> . + */ +#else + unsigned int smxtCnt1 : 32; /* * [31:0]SMXT physical counter 1.software can enable which events to be counted + * into it via field <SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> . + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT1_U; + +/* ** +* Union name : SMXT_CNT2 +* @brief SMXT physical counter 2.software can enable which events to be counted into it via field +<SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> . + +* Description: +*/ +typedef union tagUnSmxtCnt2 { + struct tagStSmxtCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxtCnt2 : 32; /* * [31:0]SMXT physical counter 2.software can enable which events to be counted + * into it via field <SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> . + */ +#else + unsigned int smxtCnt2 : 32; /* * [31:0]SMXT physical counter 2.software can enable which events to be counted + * into it via field <SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> . + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT2_U; + +/* ** +* Union name : SMXT_CNT3 +* @brief SMXT physical counter 3.software can enable which events to be counted into it via field +<SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> . + +* Description: +*/ +typedef union tagUnSmxtCnt3 { + struct tagStSmxtCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxtCnt3 : 32; /* * [31:0]SMXT physical counter 3.software can enable which events to be counted + * into it via field <SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> . + */ +#else + unsigned int smxtCnt3 : 32; /* * [31:0]SMXT physical counter 3.software can enable which events to be counted + * into it via field <SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> . + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CNT3_U; + +/* ** + * Union name : SMXT_CRDT_CNT + * @brief smxt credit counter CTP registers + * Description: + */ +typedef union tagUnSmxtCrdtCnt { + struct tagStSmxtCrdtCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int ringRqstCtp : 3; /* * [15:13]SMXT credit counter CTP registers for ring request channel*NOTE: the + * default value is 0 in SML + */ + unsigned int ringRespCtp : 3; /* * [12:10]SMXT credit counter CTP registers for ring response channel*NOTE: the + * default value is 0 in SML + */ + unsigned int tl0Ctp : 5; /* * [9:5]SMXT credit counter CTP registers for tile0*NOTE: the default value is 0 in + SML */ + unsigned int tl1Ctp : 5; /* * [4:0]SMXT credit counter CTP registers for tile1*NOTE: the default value is 0 in + SML */ +#else + unsigned int tl1Ctp : 5; /* * [4:0]SMXT credit counter CTP registers for tile1*NOTE: the default value is 0 in + SML */ + unsigned int tl0Ctp : 5; /* * [9:5]SMXT credit counter CTP registers for tile0*NOTE: the default value is 0 in + SML */ + unsigned int ringRespCtp : 3; /* * [12:10]SMXT credit counter CTP registers for ring response channel*NOTE: the + * default value is 0 in SML + */ + unsigned int ringRqstCtp : 3; /* * [15:13]SMXT credit counter CTP registers for ring request channel*NOTE: the + * default value is 0 in SML + */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CRDT_CNT_U; + +/* ** + * Union name : SMXT_FIFO_DEPTH0 + * @brief FIFO depth CTP registers for SMXT FIFOs for SMF infra1 and infra0 + * Description: + */ +typedef union tagUnSmxtFifoDepth0 { + struct tagStSmxtFifoDepth0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 29; /* * [63:35]reserved. */ + unsigned long long mcCtp : 3; /* * [34:32]SMXT FIFO depth CTP registers for SMMC */ + unsigned long long if1RingRqstCtp : 4; /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */ + unsigned long long if1RingRespCtp : 4; /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */ + unsigned long long if1Tl0Ctp : 4; /* * [23:20]SMXT FIFO depth CTP registers for tile0 */ + unsigned long long if1Tl1Ctp : 4; /* * [19:16]SMXT FIFO depth CTP registers for tile1 */ + unsigned long long if0RingRqstCtp : 4; /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */ + unsigned long long if0RingRespCtp : 4; /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */ + unsigned long long if0Tl0Ctp : 4; /* * [7:4]SMXT FIFO depth CTP registers for tile0 */ + unsigned long long if0Tl1Ctp : 4; /* * [3:0]SMXT FIFO depth CTP registers for tile1 */ +#else + unsigned long long if0Tl1Ctp : 4; /* * [3:0]SMXT FIFO depth CTP registers for tile1 */ + unsigned long long if0Tl0Ctp : 4; /* * [7:4]SMXT FIFO depth CTP registers for tile0 */ + unsigned long long if0RingRespCtp : 4; /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */ + unsigned long long if0RingRqstCtp : 4; /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */ + unsigned long long if1Tl1Ctp : 4; /* * [19:16]SMXT FIFO depth CTP registers for tile1 */ + unsigned long long if1Tl0Ctp : 4; /* * [23:20]SMXT FIFO depth CTP registers for tile0 */ + unsigned long long if1RingRespCtp : 4; /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */ + unsigned long long if1RingRqstCtp : 4; /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */ + unsigned long long mcCtp : 3; /* * [34:32]SMXT FIFO depth CTP registers for SMMC */ + unsigned long long reserved : 29; /* * [63:35]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMXT_FIFO_DEPTH0_U; + +/* ** + * Union name : SMXT_FIFO_DEPTH1 + * @brief FIFO depth CTP registers for SMXT FIFOs for SMF infra3 and Infra2 + * Description: + */ +typedef union tagUnSmxtFifoDepth1 { + struct tagStSmxtFifoDepth1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int if3RingRqstCtp : 4; /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */ + unsigned int if3RingRespCtp : 4; /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */ + unsigned int if3Tl0Ctp : 4; /* * [23:20]SMXT FIFO depth CTP registers for tile0 */ + unsigned int if3Tl1Ctp : 4; /* * [19:16]SMXT FIFO depth CTP registers for tile1 */ + unsigned int if2RingRqstCtp : 4; /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */ + unsigned int if2RingRespCtp : 4; /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */ + unsigned int if2Tl0Ctp : 4; /* * [7:4]SMXT FIFO depth CTP registers for tile0 */ + unsigned int if2Tl1Ctp : 4; /* * [3:0]SMXT FIFO depth CTP registers for tile1 */ +#else + unsigned int if2Tl1Ctp : 4; /* * [3:0]SMXT FIFO depth CTP registers for tile1 */ + unsigned int if2Tl0Ctp : 4; /* * [7:4]SMXT FIFO depth CTP registers for tile0 */ + unsigned int if2RingRespCtp : 4; /* * [11:8]SMXT FIFO depth CTP registers for ring response channel */ + unsigned int if2RingRqstCtp : 4; /* * [15:12]SMXT FIFO depth CTP registers for ring request channel */ + unsigned int if3Tl1Ctp : 4; /* * [19:16]SMXT FIFO depth CTP registers for tile1 */ + unsigned int if3Tl0Ctp : 4; /* * [23:20]SMXT FIFO depth CTP registers for tile0 */ + unsigned int if3RingRespCtp : 4; /* * [27:24]SMXT FIFO depth CTP registers for ring response channel */ + unsigned int if3RingRqstCtp : 4; /* * [31:28]SMXT FIFO depth CTP registers for ring request channel */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_FIFO_DEPTH1_U; + +/* ** + * Union name : TL0_Q_DEP + * @brief queue depth for API from TILE0 in SMXR + * Description: + */ +typedef union tagUnTl0QDep { + struct tagStTl0QDep { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 2; /* * [31:30]reserved */ + unsigned int l3Ctp : 6; /* * [29:24]flit number in queue to smeg_core3 */ + unsigned int reserved1 : 2; /* * [23:22]reserved */ + unsigned int l2Ctp : 6; /* * [21:16]flit number in queue to smeg_core2 */ + unsigned int reserved2 : 2; /* * [15:14]reserved */ + unsigned int l1Ctp : 6; /* * [13:8]flit number in queue to smeg_core1 */ + unsigned int reserved3 : 2; /* * [7:6]reserved */ + unsigned int l0Ctp : 6; /* * [5:0]flit number in queue to smeg_core0 */ +#else + unsigned int l0Ctp : 6; /* * [5:0]flit number in queue to smeg_core0 */ + unsigned int reserved3 : 2; /* * [7:6]reserved */ + unsigned int l1Ctp : 6; /* * [13:8]flit number in queue to smeg_core1 */ + unsigned int reserved2 : 2; /* * [15:14]reserved */ + unsigned int l2Ctp : 6; /* * [21:16]flit number in queue to smeg_core2 */ + unsigned int reserved1 : 2; /* * [23:22]reserved */ + unsigned int l3Ctp : 6; /* * [29:24]flit number in queue to smeg_core3 */ + unsigned int reserved0 : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_TL0_Q_DEP_U; + +/* ** + * Union name : TL1_Q_DEP + * @brief queue depth for API from TILE1 in SMXR + * Description: + */ +typedef union tagUnTl1QDep { + struct tagStTl1QDep { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 2; /* * [31:30]reserved */ + unsigned int l3Ctp : 6; /* * [29:24]flit number in queue to smeg_core3 */ + unsigned int reserved1 : 2; /* * [23:22]reserved */ + unsigned int l2Ctp : 6; /* * [21:16]flit number in queue to smeg_core2 */ + unsigned int reserved2 : 2; /* * [15:14]reserved */ + unsigned int l1Ctp : 6; /* * [13:8]flit number in queue to smeg_core1 */ + unsigned int reserved3 : 2; /* * [7:6]reserved */ + unsigned int l0Ctp : 6; /* * [5:0]flit number in queue to smeg_core0 */ +#else + unsigned int l0Ctp : 6; /* * [5:0]flit number in queue to smeg_core0 */ + unsigned int reserved3 : 2; /* * [7:6]reserved */ + unsigned int l1Ctp : 6; /* * [13:8]flit number in queue to smeg_core1 */ + unsigned int reserved2 : 2; /* * [15:14]reserved */ + unsigned int l2Ctp : 6; /* * [21:16]flit number in queue to smeg_core2 */ + unsigned int reserved1 : 2; /* * [23:22]reserved */ + unsigned int l3Ctp : 6; /* * [29:24]flit number in queue to smeg_core3 */ + unsigned int reserved0 : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_TL1_Q_DEP_U; + +/* ** + * Union name : RQST_Q_DEP + * @brief queue depth for API from RING request channel in SMXR + * Description: + */ +typedef union tagUnRqstQDep { + struct tagStRqstQDep { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved */ + unsigned int l3Ctp : 4; /* * [15:12]flit number in queue to smeg_core3 */ + unsigned int l2Ctp : 4; /* * [11:8]flit number in queue to smeg_core2 */ + unsigned int l1Ctp : 4; /* * [7:4]flit number in queue to smeg_core1 */ + unsigned int l0Ctp : 4; /* * [3:0]flit number in queue to smeg_core0 */ +#else + unsigned int l0Ctp : 4; /* * [3:0]flit number in queue to smeg_core0 */ + unsigned int l1Ctp : 4; /* * [7:4]flit number in queue to smeg_core1 */ + unsigned int l2Ctp : 4; /* * [11:8]flit number in queue to smeg_core2 */ + unsigned int l3Ctp : 4; /* * [15:12]flit number in queue to smeg_core3 */ + unsigned int reserved : 16; /* * [31:16]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_RQST_Q_DEP_U; + +/* ** + * Union name : RSP_Q_DEP + * @brief queue depth for API from RING request channel in SMXR + * Description: + */ +typedef union tagUnRspQDep { + struct tagStRspQDep { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20]reserved */ + unsigned int l4Ctp : 4; /* * [19:16]flit number in queue to SMMC */ + unsigned int l3Ctp : 4; /* * [15:12]flit number in queue to smeg_core3 */ + unsigned int l2Ctp : 4; /* * [11:8]flit number in queue to smeg_core2 */ + unsigned int l1Ctp : 4; /* * [7:4]flit number in queue to smeg_core1 */ + unsigned int l0Ctp : 4; /* * [3:0]flit number in queue to smeg_core0 */ +#else + unsigned int l0Ctp : 4; /* * [3:0]flit number in queue to smeg_core0 */ + unsigned int l1Ctp : 4; /* * [7:4]flit number in queue to smeg_core1 */ + unsigned int l2Ctp : 4; /* * [11:8]flit number in queue to smeg_core2 */ + unsigned int l3Ctp : 4; /* * [15:12]flit number in queue to smeg_core3 */ + unsigned int l4Ctp : 4; /* * [19:16]flit number in queue to SMMC */ + unsigned int reserved : 12; /* * [31:20]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_RSP_Q_DEP_U; + +/* ** + * Union name : RQST_CRDT_CNT + * @brief rqst channel credit counter in SMXR + * Description: + */ +typedef union tagUnRqstCrdtCnt { + struct tagStRqstCrdtCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20]reserved */ + unsigned int sm3Ctp : 5; /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm2Ctp : 5; /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm1Ctp : 5; /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm0Ctp : 5; /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ +#else + unsigned int sm0Ctp : 5; /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm1Ctp : 5; /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm2Ctp : 5; /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm3Ctp : 5; /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int reserved : 12; /* * [31:20]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_RQST_CRDT_CNT_U; + +/* ** + * Union name : RESP_CRDT_CNT + * @brief rsponse channel credit counter in SMXR + * Description: + */ +typedef union tagUnRespCrdtCnt { + struct tagStRespCrdtCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 7; /* * [31:25]reserved */ + unsigned int smmcCtp : 5; /* * [24:20]credit counter of smmcbinary format *NOTE: the default value is 0 in SML + */ + unsigned int sm3Ctp : 5; /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm2Ctp : 5; /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm1Ctp : 5; /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm0Ctp : 5; /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ +#else + unsigned int sm0Ctp : 5; /* * [4:0]credit counter of smeg_core0bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm1Ctp : 5; /* * [9:5]credit counter of smeg_core1bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm2Ctp : 5; /* * [14:10]credit counter of smeg_core2bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int sm3Ctp : 5; /* * [19:15]credit counter of smeg_core3bitmap format: number of 1 in bitmap is the + * credit number *NOTE: the default value is 0 in SML + */ + unsigned int smmcCtp : 5; /* * [24:20]credit counter of smmcbinary format *NOTE: the default value is 0 in SML + */ + unsigned int reserved : 7; /* * [31:25]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_RESP_CRDT_CNT_U; + +/* ** + * Union name : SMXR_CNT0 + * @brief Cnt for tile0 direct channel + * Description: + */ +typedef union tagUnSmxrCnt0 { + struct tagStSmxrCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrCnt0 : 32; /* * [31:0]Cnt for tile0 direct channel */ +#else + unsigned int smxrCnt0 : 32; /* * [31:0]Cnt for tile0 direct channel */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CNT0_U; + +/* ** + * Union name : SMXR_CNT1 + * @brief Cnt for tile1 direct channel + * Description: + */ +typedef union tagUnSmxrCnt1 { + struct tagStSmxrCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrCnt1 : 32; /* * [31:0]Cnt for tile1 direct channel */ +#else + unsigned int smxrCnt1 : 32; /* * [31:0]Cnt for tile1 direct channel */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CNT1_U; + +/* ** + * Union name : SMXR_CNT2 + * @brief Cnt for ring request channel + * Description: + */ +typedef union tagUnSmxrCnt2 { + struct tagStSmxrCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrCnt2 : 32; /* * [31:0]Cnt for ring request channel */ +#else + unsigned int smxrCnt2 : 32; /* * [31:0]Cnt for ring request channel */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CNT2_U; + +/* ** + * Union name : SMXR_CNT3 + * @brief Cnt for ring rsponse channel + * Description: + */ +typedef union tagUnSmxrCnt3 { + struct tagStSmxrCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smxrCnt3 : 32; /* * [31:0]Cnt for ring rsponse channel */ +#else + unsigned int smxrCnt3 : 32; /* * [31:0]Cnt for ring rsponse channel */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXR_CNT3_U; + +/* ** + * Union name : SMXT_CTP + * @brief SMXT CTP registers + * Description: + */ +typedef union tagUnSmxtCtp { + struct tagStSmxtCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved */ + unsigned int apiCapDone : 1; /* * [0:0]0: API capture not success1: API capture successed */ +#else + unsigned int apiCapDone : 1; /* * [0:0]0: API capture not success1: API capture successed */ + unsigned int reserved : 31; /* * [31:1]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMXT_CTP_U; + + +/* ** + * Union name : SMIR_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmirVersion { + struct tagStSmirVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smirVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_VERSION_U; + +/* ** +* Union name : SMIR_CFG +* @brief This is the Smart Memory Infra Receive (SMIR) module configuration register. Use this register +for debug. + +* Description: +*/ +typedef union tagUnSmirCfg { + struct tagStSmirCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 6; /* * [31:26]reserved */ + unsigned int rpUncrtErrInjReq : 1; /* * [25:25]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory. Enable memory check, when use this err + inection function. */ + unsigned int rpCrtErrInjReq : 1; /* * [24:24]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int reserved1 : 9; /* * [15:7]reserved */ + unsigned int rpL2nicDbPseudoApiEn : 1; /* * [6:6]L2NIC DB pseudo API enable:1'b1: judge the API TYPE (pseudo or + * not) according to the "pseudo" bit in API;1'b0: All L2NIC DB API is + * regarded as non-pseudo API. + */ + unsigned int memChkEn : 1; /* * [5:5]memory parity check enable.1'b0:disable all memories err check.1'b1:enable + * all memories err check. + */ + unsigned int msbThreadCfg : 1; /* * [4:4]0:msb thread is used as special thread only used in response + channel;1:msb thread is used as normal thread only used in request channel;*NOTE: + This bit and smeg 1.smeg1_cfg0.msb_thread_cfg should be configure the same value */ + unsigned int regCapChSel : 1; /* * [3:3]capture data selection,used to choose a channel data into + SMIR_CAP_DATA.0: put the caputured data from request channel into SMIR_CAP_DATA. 1: + put the caputured data from response channel into SMIR_CAP_DATA. Note:both request + channel and response channel have capture logic,they can capture message at same + time. The chan + nel selection is used to decide which channel to be displayed to uers. */ + unsigned int simpleHash : 1; /* * [2:2]simple hash computaion select.This bit is used for vefication Verfication + can simulate hash collsion easily via this mode .0: default hardware hash computation. + 1 : select lower 64bits of hash key as hash result instead of standard hardware hash + computation.FHT Engine: select first 32bit of hash key (sop[63:32] as hash result; + Stateless Hash:If key size is 10B: select first 64bit of hash key (sop[103:40] as hash + result;if key size is 4B：select all 32bit key：sop [95:64], then u se { key[23:16], + key[31:24], key[7:0], key[15:8], key[31:0]} as hash result;else, select first 64bit of + hash key (sop[95:32] as hash result;Statefull Hash:If ke y size is 42B/26B/10B, select + first 64bit of hash key (sop[79:16] as hash result;If key size is 9B，select first + 64bit of hash key (sop[95:32] as hash result; + */ + unsigned int disRxResp : 1; /* * [1:1]disable receive message from response channel . This bit is used for + debug. Software can stop to receive message from response channel via set this + bit.1: d isable receive message from response channel.0: enable. */ + unsigned int disRxRqst : 1; /* * [0:0]disable request message from request channel . This bit is used for + debug. Software can stop to receive message from request channel via set this + bit.1: dis able receive message from request channel.0: enable.Note: This bit should + not be config to 1 as csr message cannot be delivered to cnb after request channel is + disabled. */ +#else + unsigned int disRxRqst : 1; /* * [0:0]disable request message from request channel . This bit is used for + debug. Software can stop to receive message from request channel via set this + bit.1: dis able receive message from request channel.0: enable.Note: This bit should + not be config to 1 as csr message cannot be delivered to cnb after request channel is + disabled. */ + unsigned int disRxResp : 1; /* * [1:1]disable receive message from response channel . This bit is used for + debug. Software can stop to receive message from response channel via set this + bit.1: d isable receive message from response channel.0: enable. */ + unsigned int simpleHash : 1; /* * [2:2]simple hash computaion select.This bit is used for vefication Verfication + can simulate hash collsion easily via this mode .0: default hardware hash computation. + 1 : select lower 64bits of hash key as hash result instead of standard hardware hash + computation.FHT Engine: select first 32bit of hash key (sop[63:32] as hash result; + Stateless Hash:If key size is 10B: select first 64bit of hash key (sop[103:40] as hash + result;if key size is 4B：select all 32bit key：sop [95:64], then u se { key[23:16], + key[31:24], key[7:0], key[15:8], key[31:0]} as hash result;else, select first 64bit of + hash key (sop[95:32] as hash result;Statefull Hash:If ke y size is 42B/26B/10B, select + first 64bit of hash key (sop[79:16] as hash result;If key size is 9B，select first + 64bit of hash key (sop[95:32] as hash result; + */ + unsigned int regCapChSel : 1; /* * [3:3]capture data selection,used to choose a channel data into + SMIR_CAP_DATA.0: put the caputured data from request channel into SMIR_CAP_DATA. 1: + put the caputured data from response channel into SMIR_CAP_DATA. Note:both request + channel and response channel have capture logic,they can capture message at same + time. The chan + nel selection is used to decide which channel to be displayed to uers. */ + unsigned int msbThreadCfg : 1; /* * [4:4]0:msb thread is used as special thread only used in response + channel;1:msb thread is used as normal thread only used in request channel;*NOTE: + This bit and smeg 1.smeg1_cfg0.msb_thread_cfg should be configure the same value */ + unsigned int memChkEn : 1; /* * [5:5]memory parity check enable.1'b0:disable all memories err check.1'b1:enable + * all memories err check. + */ + unsigned int rpL2nicDbPseudoApiEn : 1; /* * [6:6]L2NIC DB pseudo API enable:1'b1: judge the API TYPE (pseudo or + * not) according to the "pseudo" bit in API;1'b0: All L2NIC DB API is + * regarded as non-pseudo API. + */ + unsigned int reserved1 : 9; /* * [15:7]reserved */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int rpCrtErrInjReq : 1; /* * [24:24]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int rpUncrtErrInjReq : 1; /* * [25:25]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory. Enable memory check, when use this err + inection function. */ + unsigned int reserved0 : 6; /* * [31:26]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CFG_U; + +/* ** +* Union name : SMIR_HASH_SEED0 +* @brief Hash function seed conifg register. This register used to change the original seed of hash +function. + +* Description: +*/ +typedef union tagUnSmirHashSeed0 { + struct tagStSmirHashSeed0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int hashSeedCfg0 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the + * original seed[31:0] of hash function. + */ +#else + unsigned int hashSeedCfg0 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the + * original seed[31:0] of hash function. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_HASH_SEED0_U; + +/* ** +* Union name : SMIR_HASH_SEED1 +* @brief Hash function seed conifg register. This register used to change the original seed of hash +function. + +* Description: +*/ +typedef union tagUnSmirHashSeed1 { + struct tagStSmirHashSeed1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int hashSeedCfg1 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the + * original seed[63:32] of hash function. + */ +#else + unsigned int hashSeedCfg1 : 32; /* * [31:0]Hash function seed conifg register. This register used to change the + * original seed[63:32] of hash function. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_HASH_SEED1_U; + +/* ** + * Union name : SMIR_INT_VECTOR + * @brief + * Description: + */ +typedef union tagUnSmirIntVector { + struct tagStSmirIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INT_VECTOR_U; + +/* ** + * Union name : SMIR_INT + * @brief SMIR interrupt data + * Description: + */ +typedef union tagUnSmirInt { + struct tagStSmirInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 11; /* * [15:5]reserved */ + unsigned int intData : 5; /* * [4:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 5; /* * [4:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 11; /* * [15:5]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INT_U; + +/* ** + * Union name : SMIR_INT_MASK + * @brief SMIR interrupt mask configuration + * Description: + */ +typedef union tagUnSmirIntMask { + struct tagStSmirIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 11; /* * [15:5]reserved */ + unsigned int errMask : 5; /* * [4:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 5; /* * [4:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 11; /* * [15:5]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INT_MASK_U; + +/* ** + * Union name : SMIR_ERR_SPEC_TH + * @brief Int[0] :specital thread drop for busy. + * Description: + */ +typedef union tagUnSmirErrSpecTh { + struct tagStSmirErrSpecTh { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.Capture data format as following:31:25 - thread id;24:19 - src_tag_h;18:14 - src;13:8 + - in stance ID;7:2 - OP-CODE （include ACK bit） */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.Capture data format as following:31:25 - thread id;24:19 - src_tag_h;18:14 - src;13:8 + - in stance ID;7:2 - OP-CODE （include ACK bit） */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_ERR_SPEC_TH_U; + +/* ** + * Union name : SMIR_REQ_MSG_ERR + * @brief SMIR request channel message error register. + * Description: + */ +typedef union tagUnSmirReqMsgErr { + struct tagStSmirReqMsgErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4 + Error typeBit0:message with E0-bitbit1:mmessage with E1-bitbit2:message over length + bit3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of + error message.bit[9:8] : codebit[15:10] : op_id （include ACK bit）bit[ 21:16] : + instancebit[26:22] : srcBit27~29 RSV */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4 + Error typeBit0:message with E0-bitbit1:mmessage with E1-bitbit2:message over length + bit3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of + error message.bit[9:8] : codebit[15:10] : op_id （include ACK bit）bit[ 21:16] : + instancebit[26:22] : srcBit27~29 RSV */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_REQ_MSG_ERR_U; + +/* ** + * Union name : SMIR_RESP_MSG_ERR + * @brief SMIR response channel message error register. + * Description: + */ +typedef union tagUnSmirRespMsgErr { + struct tagStSmirRespMsgErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4 + Error typeBit0:message with E0-bitbit1:message with E1-bitbit2:message over lengthb + it3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of + error message.bit[9:8] : codebit[15:10] : op_idbit[21:16] : instancebit [26:22] : + srcBit27~29 RSV */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~4 + Error typeBit0:message with E0-bitbit1:message with E1-bitbit2:message over lengthb + it3:message without sopbit4:message without eopBit5~7 reserved.Bit8~26 capture data of + error message.bit[9:8] : codebit[15:10] : op_idbit[21:16] : instancebit [26:22] : + srcBit27~29 RSV */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_RESP_MSG_ERR_U; + +/* ** + * Union name : SMIR_MEM_ECC_CRT_ERR + * @brief smir memory ecc correctable error + * Description: + */ +typedef union tagUnSmirMemEccCrtErr { + struct tagStSmirMemEccCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error + is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error + address;Bit29:16 reserved. + */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error + is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error + address;Bit29:16 reserved. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_MEM_ECC_CRT_ERR_U; + +/* ** + * Union name : SMIR_MEM_ECC_UNCRT_ERR + * @brief smir memory ecc uncorrectable error + * Description: + */ +typedef union tagUnSmirMemEccUncrtErr { + struct tagStSmirMemEccUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error + is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error + address;Bit29:16 reserved. + */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off.Bit0~1 + Error typeBit0:ecc correctable error is dectected on VAT table bit1:ecc correctable error + is dectected on RSS template memoryBit11:2: VAT mem error addressbit15:12 RSS mem error + address;Bit29:16 reserved. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_MEM_ECC_UNCRT_ERR_U; + +/* ** + * Union name : SMIR_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmirIndrectCtrl { + struct tagStSmirIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smirIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smirIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smirIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: FIPR;4’b0001: RSS hash + memory4' b0010: VAT memory, only in SMF4' b0011: TPT(timer position table), only in + SMFother s:reserved */ + unsigned int smirIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.bit[13:5] memory address in SMF: + FIPR; only bi t8:4 is valid; RSS_Hash:only bit 7:4 is valid; VAT: bit 13:4 is + valid TPT: only bit 8:4 is valid in SML mode: FIPR; only bit9:4 is valid; + RSS_Hash:only bit 7:4 is valid;bit[3:0] word select for RSS MEM: 0~3 reserved, + 4:mem_dat[352:321] // ECC Code, read only for CSR 5:{31bit RSV, + mem_dat[320]} 6: mem_dat[319:288] 7:mem_dat[287:256] 8:mem_dat[255:224] + 9:mem_dat[223:192] 10:mem_dat[191:160] 11:mem_dat[159:128] 12:mem_dat[127:96] + 13:mem_dat[95 :64] 14:mem_dat[63:32] 15:mem_dat[31:0]bit[3:0] word select for + VAT MEM: 0~11 reserved, 12:{24Bit RSV, mem_data[84:77]} // ECC Code, read + only for CSR 13:{19Bit RSV, mem_dat[76:64]} 14:mem_dat[63:32] + 15:mem_dat[31:0]Note: for accessing FIPR/TPT,bit[3:0] should be 4'hf. + */ +#else + unsigned int smirIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.bit[13:5] memory address in SMF: + FIPR; only bi t8:4 is valid; RSS_Hash:only bit 7:4 is valid; VAT: bit 13:4 is + valid TPT: only bit 8:4 is valid in SML mode: FIPR; only bit9:4 is valid; + RSS_Hash:only bit 7:4 is valid;bit[3:0] word select for RSS MEM: 0~3 reserved, + 4:mem_dat[352:321] // ECC Code, read only for CSR 5:{31bit RSV, + mem_dat[320]} 6: mem_dat[319:288] 7:mem_dat[287:256] 8:mem_dat[255:224] + 9:mem_dat[223:192] 10:mem_dat[191:160] 11:mem_dat[159:128] 12:mem_dat[127:96] + 13:mem_dat[95 :64] 14:mem_dat[63:32] 15:mem_dat[31:0]bit[3:0] word select for + VAT MEM: 0~11 reserved, 12:{24Bit RSV, mem_data[84:77]} // ECC Code, read + only for CSR 13:{19Bit RSV, mem_dat[76:64]} 14:mem_dat[63:32] + 15:mem_dat[31:0]Note: for accessing FIPR/TPT,bit[3:0] should be 4'hf. + */ + unsigned int smirIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: FIPR;4’b0001: RSS hash + memory4' b0010: VAT memory, only in SMF4' b0011: TPT(timer position table), only in + SMFother s:reserved */ + unsigned int smirIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smirIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smirIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INDRECT_CTRL_U; + +/* ** + * Union name : SMIR_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmirIndrectTimeout { + struct tagStSmirIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smirIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMIR_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmirIndrectData { + struct tagStSmirIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smirIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_INDRECT_DATA_U; + +/* ** +* Union name : SMIR_CAP0_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per field via <cap_sel _en> +in <smir_en_cnt> ) +* Description: +*/ +typedef union tagUnSmirCap0Cfg { + struct tagStSmirCap0Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int capMode : 1; /* * [31:31]capture mode control register. 0:capture mode disable.smir will not + capture any message.1:capture mode enable.smir will compare the selected fields,only the + mes sages matched with all selected fields will be captured.Note：field match enable + config can be found in SMIR_EN_CNT register. + */ + unsigned int sE1Bit : 1; /* * [30:30]E1 field in first flit to capture . It can be enable via <cap_sel_en> field + in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users + may get information in Error register. */ + unsigned int sE0Bit : 1; /* * [29:29]E0 field in first flit to capture . It can be enable via <cap_sel_en> field + in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users + may get information in Error register. */ + unsigned int sCode : 2; /* * [28:27]code field to capture . It can be enable via <cap_sel_en> field in register + * <smir_en_cnt> . + */ + unsigned int sOpId : 6; /* * [26:21]opcode field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int sInstId : 6; /* * [20:15]inst_id field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int src : 5; /* * [14:10]src field to capture . It can be enable via <cap_sel_en> field in register + * <smir_en_cnt> . + */ + unsigned int reserved : 4; /* * [9:6]reserved */ + unsigned int stagH : 6; /* * [5:0]src_tag_h field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ +#else + unsigned int stagH : 6; /* * [5:0]src_tag_h field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int reserved : 4; /* * [9:6]reserved */ + unsigned int src : 5; /* * [14:10]src field to capture . It can be enable via <cap_sel_en> field in register + * <smir_en_cnt> . + */ + unsigned int sInstId : 6; /* * [20:15]inst_id field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int sOpId : 6; /* * [26:21]opcode field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int sCode : 2; /* * [28:27]code field to capture . It can be enable via <cap_sel_en> field in register + * <smir_en_cnt> . + */ + unsigned int sE0Bit : 1; /* * [29:29]E0 field in first flit to capture . It can be enable via <cap_sel_en> field + in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users + may get information in Error register. */ + unsigned int sE1Bit : 1; /* * [30:30]E1 field in first flit to capture . It can be enable via <cap_sel_en> field + in register <smir_en_cnt> . Note：the E-bit in other flits will not be captured,users + may get information in Error register. */ + unsigned int capMode : 1; /* * [31:31]capture mode control register. 0:capture mode disable.smir will not + capture any message.1:capture mode enable.smir will compare the selected fields,only the + mes sages matched with all selected fields will be captured.Note：field match enable + config can be found in SMIR_EN_CNT register. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP0_CFG_U; + +/* ** +* Union name : SMIR_CAP1_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here. + +* Description: +*/ +typedef union tagUnSmirCap1Cfg { + struct tagStSmirCap1Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int flit011196 : 16; /* * [31:16]flit0 bit111~bit96 field to capture . */ + unsigned int flit011196Msk : 16; /* * [15:0]flit0 bit111~bit96 capture mask. 1:corresponding bit must match when + * capture.0:don't care whether corresponding bit match when capture. + */ +#else + unsigned int flit011196Msk : 16; /* * [15:0]flit0 bit111~bit96 capture mask. 1:corresponding bit must match when + * capture.0:don't care whether corresponding bit match when capture. + */ + unsigned int flit011196 : 16; /* * [31:16]flit0 bit111~bit96 field to capture . */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP1_CFG_U; + +/* ** +* Union name : SMIR_CAP2_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here. + +* Description: +*/ +typedef union tagUnSmirCap2Cfg { + struct tagStSmirCap2Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int flit09564 : 32; /* * [31:0]flit0 bit95~bit64 field to capture . */ +#else + unsigned int flit09564 : 32; /* * [31:0]flit0 bit95~bit64 field to capture . */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP2_CFG_U; + +/* ** +* Union name : SMIR_CAP3_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here. + +* Description: +*/ +typedef union tagUnSmirCap3Cfg { + struct tagStSmirCap3Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int flit06332 : 32; /* * [31:0]flit0 bit63~bit32 field to capture . */ +#else + unsigned int flit06332 : 32; /* * [31:0]flit0 bit63~bit32 field to capture . */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP3_CFG_U; + +/* ** +* Union name : SMIR_CAP4_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here. + +* Description: +*/ +typedef union tagUnSmirCap4Cfg { + struct tagStSmirCap4Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int flit0310 : 32; /* * [31:0]flit0 bit31~bit0 field to capture . */ +#else + unsigned int flit0310 : 32; /* * [31:0]flit0 bit31~bit0 field to capture . */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP4_CFG_U; + +/* ** +* Union name : SMIR_CAP6_CFG +* @brief SMIR capture fields configuration register .This is used for debug . The software can +configure capture conditions here .For example ,the software want to c apture message and count matched message .The +software can enable <cap_mode> field and cofigure compare fields data here. + +* Description: +*/ +typedef union tagUnSmirCap6Cfg { + struct tagStSmirCap6Cfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 6; /* * [31:26]reserved */ + unsigned int flit0950Msk : 6; /* * [25:20]flit0 bit95~bit0 capture mask.1 mask bit is corresponding 16bit data. + 1:corresponding bit must match when capture.0:don't care whether corresponding bit + match w hen capture. . */ + unsigned int capThreadIdEn : 1; /* * [19:19]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + outband E bit field in message match according field in message. 0 ,No need to + match this field .This field's capture valid. + */ + unsigned int threadId : 7; /* * [18:12]thread_id field to capture . It can be enable via cap_thread_id_en . */ + unsigned int stagL : 12; /* * [11:0]src_tag_l field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ +#else + unsigned int stagL : 12; /* * [11:0]src_tag_l field to capture . It can be enable via <cap_sel_en> field in + * register <smir_en_cnt> . + */ + unsigned int threadId : 7; /* * [18:12]thread_id field to capture . It can be enable via cap_thread_id_en . */ + unsigned int capThreadIdEn : 1; /* * [19:19]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + outband E bit field in message match according field in message. 0 ,No need to + match this field .This field's capture valid. + */ + unsigned int flit0950Msk : 6; /* * [25:20]flit0 bit95~bit0 capture mask.1 mask bit is corresponding 16bit data. + 1:corresponding bit must match when capture.0:don't care whether corresponding bit + match w hen capture. . */ + unsigned int reserved : 6; /* * [31:26]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP6_CFG_U; + +/* ** +* Union name : SMIR_EN_CNT +* @brief SMIR mappable event counter controal . The software use this control to configure expected +counter mapping . + +* Description: +*/ +typedef union tagUnSmirEnCnt { + struct tagStSmirEnCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int capStagLEn : 1; /* * [31:31]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + src_tag_l field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ + unsigned int capErr1En : 1; /* * [30:30]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + E bit field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ + unsigned int capErr0En : 1; /* * [29:29]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + E bit field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ + unsigned int capCodeEn : 1; /* * [28:28]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + code field in message match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int capOpEn : 1; /* * [27:27]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when opcode + field in mes sage match according field in message. 0 ,No need to match this field .This + field's capture valid. + */ + unsigned int capInstEn : 1; /* * [26:26]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when inst_id + field in me ssage match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int capSrcEn : 1; /* * [25:25]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when src field + in messag e match according field in message. 0 ,No need to match this field .This + field's capture valid. + */ + unsigned int capStagHEn : 1; /* * [24:24]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when stag + field in messa ge match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int + smirEnCnt2 : 8; /* * [23:16]Couter source select vector for physical counter2. software can configure this + register to decide which counter should be counted into physical counter 2.bit_7: counter + enable1'b0:disable counting.1'b1:enable counting.bit_6: channel selection1'b0:this counter will + only count the request channel.1'b1:this counter will o nly count the response + channel.bit_5:capture Conditional count enable . This is used for debug .When Software + enable this field, then only messages matched with capture condition inside regiser < + smir_cap_cfg> will trigger counting. Otherwise ,counter will be triggerd for all kinds of + messages . 1 : count only wh en message match capture trigger condition.0 : count for all + messages.bit_4:reserved.bit[3:0]:counter input selection,config one value to choose which type + you want count:4'h0:received flits number4'h1:received messages number4'h2:received sop + number4'h3:received eop number4'h4:flits sent to smeg14'h5:messages sent to smeg14'h6:flits + sent to smeg04'h7:messages sent to smeg04'h8:RSV4'h9:RSV4'ha:RSV4'hb:RSV4'hc:flits dropped by + smir4'hd:messages dropped by smir4'he~4'hf:reserve d. */ + unsigned int smirEnCnt1 : 8; /* * [15:8]Counter configure register for SMIR_CNT1; Function is as same as + smir_en_cnt_2 */ + unsigned int smirEnCnt0 : 8; /* * [7:0]Counter configure register for SMIR_CNT0; Function is as same as + smir_en_cnt_2 */ +#else + unsigned int smirEnCnt0 : 8; /* * [7:0]Counter configure register for SMIR_CNT0; Function is as same as + smir_en_cnt_2 */ + unsigned int smirEnCnt1 : 8; /* * [15:8]Counter configure register for SMIR_CNT1; Function is as same as + smir_en_cnt_2 */ + unsigned int + smirEnCnt2 : 8; /* * [23:16]Couter source select vector for physical counter2. software can configure this + register to decide which counter should be counted into physical counter 2.bit_7: counter + enable1'b0:disable counting.1'b1:enable counting.bit_6: channel selection1'b0:this counter will + only count the request channel.1'b1:this counter will o nly count the response + channel.bit_5:capture Conditional count enable . This is used for debug .When Software + enable this field, then only messages matched with capture condition inside regiser < + smir_cap_cfg> will trigger counting. Otherwise ,counter will be triggerd for all kinds of + messages . 1 : count only wh en message match capture trigger condition.0 : count for all + messages.bit_4:reserved.bit[3:0]:counter input selection,config one value to choose which type + you want count:4'h0:received flits number4'h1:received messages number4'h2:received sop + number4'h3:received eop number4'h4:flits sent to smeg14'h5:messages sent to smeg14'h6:flits + sent to smeg04'h7:messages sent to smeg04'h8:RSV4'h9:RSV4'ha:RSV4'hb:RSV4'hc:flits dropped by + smir4'hd:messages dropped by smir4'he~4'hf:reserve d. */ + unsigned int capStagHEn : 1; /* * [24:24]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when stag + field in messa ge match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int capSrcEn : 1; /* * [25:25]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when src field + in messag e match according field in message. 0 ,No need to match this field .This + field's capture valid. + */ + unsigned int capInstEn : 1; /* * [26:26]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when inst_id + field in me ssage match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int capOpEn : 1; /* * [27:27]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when opcode + field in mes sage match according field in message. 0 ,No need to match this field .This + field's capture valid. + */ + unsigned int capCodeEn : 1; /* * [28:28]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + code field in message match according field in message. 0 ,No need to match this field + .This field's capture valid. + */ + unsigned int capErr0En : 1; /* * [29:29]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + E bit field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ + unsigned int capErr1En : 1; /* * [30:30]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when outband + E bit field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ + unsigned int capStagLEn : 1; /* * [31:31]Condition fields enable according to match fields in registers + <smir_cap_cfg> .When software enable <cap_mode> field : 1, Capture only when + src_tag_l field in message match according field in message. 0 ,No need to match this + field .This field's capture valid. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_EN_CNT_U; + +/* ** +* Union name : SMIR_CNT0 +* @brief SMIR physical counter 0.software can enable which events to be counted into it via field +<smir_en_cnt_0> in register <SMIR_EN_CNT> . + +* Description: +*/ +typedef union tagUnSmirCnt0 { + struct tagStSmirCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirCnt0 : 32; /* * [31:0] */ +#else + unsigned int smirCnt0 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CNT0_U; + +/* ** +* Union name : SMIR_CNT1 +* @brief SMIR physical counter 1.software can enable which events to be counted into it via field +<smir_en_cnt_1> in register <SMIR_EN_CNT> . + +* Description: +*/ +typedef union tagUnSmirCnt1 { + struct tagStSmirCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirCnt1 : 32; /* * [31:0] */ +#else + unsigned int smirCnt1 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CNT1_U; + +/* ** +* Union name : SMIR_CNT2 +* @brief SMIR physical counter 2.software can enable which events to be counted into it via field +<smir_en_cnt_2> in register <SMIR_EN_CNT> . + +* Description: +*/ +typedef union tagUnSmirCnt2 { + struct tagStSmirCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smirCnt2 : 32; /* * [31:0] */ +#else + unsigned int smirCnt2 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CNT2_U; + +/* ** + * Union name : SMIR_CRDT_CNT + * @brief SMIR credit counter CTP register + * Description: + */ +typedef union tagUnSmirCrdtCnt { + struct tagStSmirCrdtCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 18; /* * [31:14]reserved. */ + unsigned int smmcCtp : 5; /* * [13:9]RSV */ + unsigned int rqstCtp : 3; /* * [8:6]credit counter CTP registers for EG1 request channel; */ + unsigned int respCtp : 3; /* * [5:3]credit counter CTP registers for EG1 response channel; */ + unsigned int eg0Ctp : 3; /* * [2:0]smeg0 credit counter CTP registers for EG0; */ +#else + unsigned int eg0Ctp : 3; /* * [2:0]smeg0 credit counter CTP registers for EG0; */ + unsigned int respCtp : 3; /* * [5:3]credit counter CTP registers for EG1 response channel; */ + unsigned int rqstCtp : 3; /* * [8:6]credit counter CTP registers for EG1 request channel; */ + unsigned int smmcCtp : 5; /* * [13:9]RSV */ + unsigned int reserved : 18; /* * [31:14]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CRDT_CNT_U; + +/* ** +* Union name : SMIR_CAP_FLIT0_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit0Data0 { + struct tagStSmirCapFlit0Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT0_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT0_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit0Data1 { + struct tagStSmirCapFlit0Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT0_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT1_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit1Data0 { + struct tagStSmirCapFlit1Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT1_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT1_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit1Data1 { + struct tagStSmirCapFlit1Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT1_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT2_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit2Data0 { + struct tagStSmirCapFlit2Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT2_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT2_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit2Data1 { + struct tagStSmirCapFlit2Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT2_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT3_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit3Data0 { + struct tagStSmirCapFlit3Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT3_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT3_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit3Data1 { + struct tagStSmirCapFlit3Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT3_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT4_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit4Data0 { + struct tagStSmirCapFlit4Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT4_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT4_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit4Data1 { + struct tagStSmirCapFlit4Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT4_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT5_DATA0 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit5Data0 { + struct tagStSmirCapFlit5Data0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[127:65] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT5_DATA0_U; + +/* ** +* Union name : SMIR_CAP_FLIT5_DATA1 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit5Data1 { + struct tagStSmirCapFlit5Data1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ +#else + unsigned long long captureData0 : 63; /* * [62:0]record the flit[64:2] of capture message. */ + unsigned long long triggerEnable : 1; /* * [63:63]0:trigger is disable1:trigger enable */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMIR_CAP_FLIT5_DATA1_U; + +/* ** +* Union name : SMIR_CAP_FLIT0_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit0Data2 { + struct tagStSmirCapFlit0Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT0_DATA2_U; + +/* ** +* Union name : SMIR_CAP_FLIT1_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit1Data2 { + struct tagStSmirCapFlit1Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT1_DATA2_U; + +/* ** +* Union name : SMIR_CAP_FLIT2_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit2Data2 { + struct tagStSmirCapFlit2Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT2_DATA2_U; + +/* ** +* Union name : SMIR_CAP_FLIT3_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit3Data2 { + struct tagStSmirCapFlit3Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT3_DATA2_U; + +/* ** +* Union name : SMIR_CAP_FLIT4_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit4Data2 { + struct tagStSmirCapFlit4Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT4_DATA2_U; + +/* ** +* Union name : SMIR_CAP_FLIT5_DATA2 +* @brief SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first flit's lower +127bits of matched message;2) sample mode:first flit's lower 127b its of latest message.This is used for debug . +Software can configure capture condition in SMIR_CAP_CFG. And Read capture data here. + +* Description: +*/ +typedef union tagUnSmirCapFlit5Data2 { + struct tagStSmirCapFlit5Data2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ +#else + unsigned int captureData0 : 2; /* * [1:0]record the flit[1:0] of capture message. */ + unsigned int triggerEnable : 1; /* * [2:2]0:trigger is disable1:trigger enable */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIR_CAP_FLIT5_DATA2_U; + + +/* ** + * Union name : SMEG0_ABUF0_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmeg0Abuf0Version { + struct tagStSmeg0Abuf0Version { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0Abuf0Version : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smeg0Abuf0Version : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_ABUF0_VERSION_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_0 + * @brief This is the Sm Abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm0 { + struct tagStSmAbufThGrwWm0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow0 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFO.Bit[5:0] list0,Bit[11:6] list1,...Bit[29 :24] list4,<The + following statement can be changed for clarity.>Eg:For list0, th_grow_0[5:0] can indicate + 64 grow water-mark thresholds:6'd0: which means grow f lag will never generate.you can + say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current + free node number in free list is less than 1/64 of total free node number,abuf0 will set + grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ +#else + unsigned int thGrow0 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFO.Bit[5:0] list0,Bit[11:6] list1,...Bit[29 :24] list4,<The + following statement can be changed for clarity.>Eg:For list0, th_grow_0[5:0] can indicate + 64 grow water-mark thresholds:6'd0: which means grow f lag will never generate.you can + say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current + free node number in free list is less than 1/64 of total free node number,abuf0 will set + grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_0_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_1 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm1 { + struct tagStSmAbufThGrwWm1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow1 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29: 24] list9,<The + following statement can be changed for clarity.>Eg:For list5, th_grow_1[5:0] can indicate + 64 grow water-mark thresholds:6'd0: which means grow fl ag will never generate.you can + say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current + free node number in free list is less t han 1/64 of total free node number,abuf0 will set + grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ +#else + unsigned int thGrow1 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29: 24] list9,<The + following statement can be changed for clarity.>Eg:For list5, th_grow_1[5:0] can indicate + 64 grow water-mark thresholds:6'd0: which means grow fl ag will never generate.you can + say Disable grow water-mark generate.6'd1: 1/64*total_num,which means that if the current + free node number in free list is less t han 1/64 of total free node number,abuf0 will set + grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_1_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_2 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm2 { + struct tagStSmAbufThGrwWm2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow2 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[2 9:24] + list14,<The following statement can be changed for clarity.>Eg:For list10, th_grow_2[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ +#else + unsigned int thGrow2 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[2 9:24] + list14,<The following statement can be changed for clarity.>Eg:For list10, th_grow_2[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_2_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_3 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm3 { + struct tagStSmAbufThGrwWm3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow3 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[2 9:24] + list19,<The following statement can be changed for clarity.>Eg:For list15, th_grow_3[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ +#else + unsigned int thGrow3 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[2 9:24] + list19,<The following statement can be changed for clarity.>Eg:For list15, th_grow_3[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_3_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_4 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm4 { + struct tagStSmAbufThGrwWm4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow4 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[2 9:24] + list24,<The following statement can be changed for clarity.>Eg:For list20, th_grow_4[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ +#else + unsigned int thGrow4 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[2 9:24] + list24,<The following statement can be changed for clarity.>Eg:For list20, th_grow_4[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_4_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_5 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm5 { + struct tagStSmAbufThGrwWm5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thGrow5 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[2 9:24] + list29,<The following statement can be changed for clarity.>Eg:For list25, th_grow_4[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ +#else + unsigned int thGrow5 : 30; /* * [29:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[2 9:24] + list29,<The following statement can be changed for clarity.>Eg:For list25, th_grow_4[5:0] + can indicate 64 grow water-mark thresholds:6'd0: which means gro w flag will never + generate.you can say Disable grow water-mark generate.6'd1: 1/64*total_num,which means + that if the current free node number in free list is le ss than 1/64 of total free node + number,abuf0 will set grow flag and sent it to smeg1. 6'd2: 2/64*total_num…6'd63: + 63/64*total_num + */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_5_U; + +/* ** + * Union name : SM_ABUF_TH_GRW_WM_6 + * @brief This is the Sm abuf0 grow watermark config register. + * Description: + */ +typedef union tagUnSmAbufThGrwWm6 { + struct tagStSmAbufThGrwWm6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12]reserved */ + unsigned int thGrow6 : 12; /* * [11:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list30,Bit[11:6] list31<The foll owing statement + can be changed for clarity.>Eg:For list30, th_grow_5[5:0] can indicate 64 grow water-mark + thresholds:6'd0: which means grow flag will never gene rate.you can say Disable grow + water-mark generate.6'd1: 1/64*total_num,which means that if the current free node number + in free list is less than 1/64 of total free node number,abuf0 will set grow flag and + sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ +#else + unsigned int thGrow6 : 12; /* * [11:0]Hardware will inform the software to grow when the actual percentage of + free nodes (free node number/total free node number) is below this threshold.Notice: thi + s free node number is equal to the current counter in the list info but not include the + free nodes in the prefetch FIFOBit[5:0] list30,Bit[11:6] list31<The foll owing statement + can be changed for clarity.>Eg:For list30, th_grow_5[5:0] can indicate 64 grow water-mark + thresholds:6'd0: which means grow flag will never gene rate.you can say Disable grow + water-mark generate.6'd1: 1/64*total_num,which means that if the current free node number + in free list is less than 1/64 of total free node number,abuf0 will set grow flag and + sent it to smeg1. 6'd2: 2/64*total_num…6'd63: 63/64*total_num + */ + unsigned int reserved : 20; /* * [31:12]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_GRW_WM_6_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_0 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm0 { + struct tagStSmAbufThShkWm0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thShrink0 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list0,Bit[11:6] list1,...Bit[29:24] list4,Eg:Fo r list0, + th_shrink_0[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-mark g enerate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink0 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list0,Bit[11:6] list1,...Bit[29:24] list4,Eg:Fo r list0, + th_shrink_0[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-mark g enerate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_0_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_1 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm1 { + struct tagStSmAbufThShkWm1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thShrink1 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29:24] list9,Eg:Fo r list5, + th_shrink_1[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-mark g enerate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink1 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list5,Bit[11:6] list6,...Bit[29:24] list9,Eg:Fo r list5, + th_shrink_1[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-mark g enerate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shrink f lag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_1_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_2 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm2 { + struct tagStSmAbufThShkWm2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]reserved */ + unsigned int thShrink2 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[29:24] list14,Eg :For list10, + th_shrink_2[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink2 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list10,Bit[11:6] list11,...Bit[29:24] list14,Eg :For list10, + th_shrink_2[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_2_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_3 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm3 { + struct tagStSmAbufThShkWm3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]Reserved */ + unsigned int thShrink3 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[29:24] list19,Eg :For list15, + th_shrink_3[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink3 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list15,Bit[11:6] list16,...Bit[29:24] list19,Eg :For list15, + th_shrink_3[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_3_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_4 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm4 { + struct tagStSmAbufThShkWm4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]Reserved */ + unsigned int thShrink4 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[29:24] list24,Eg :For list20, + th_shrink_4[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink4 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list20,Bit[11:6] list21,...Bit[29:24] list24,Eg :For list20, + th_shrink_4[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_4_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_5 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm5 { + struct tagStSmAbufThShkWm5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30]Reserved */ + unsigned int thShrink5 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[29:24] list29,Eg :For list25, + th_shrink_5[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink5 : 30; /* * [29:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list25,Bit[11:6] list26,...Bit[29:24] list29,Eg :For list25, + th_shrink_5[5:0] can indicate 64 shrink water-mark thresholds:6'd0: which means shrink + flag will never generate.you can say Disable shrink water-ma rk generate.6'd1: + 1/64*total_num,which means that if the current free node number in free list is larger + than 1/64 of total free node number,abuf0 will set shri nk flag and sent it to smeg1. + 6'd2: 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 2; /* * [31:30]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_5_U; + +/* ** + * Union name : SM_ABUF_TH_SHK_WM_6 + * @brief This is the Sm abuf0 shrink watermark config register. + * Description: + */ +typedef union tagUnSmAbufThShkWm6 { + struct tagStSmAbufThShkWm6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12]Reserved */ + unsigned int thShrink6 : 12; /* * [11:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list30,Bit[11:6] list31Eg:For list30, th_shrink _6[5:0] can + indicate 64 shrink water-mark thresholds:6'd0: which means shrink flag will never + generate.you can say Disable shrink water-mark generate.6'd1: 1/64 *total_num,which + means that if the current free node number in free list is larger than 1/64 of total + free node number,abuf0 will set shrink flag and sent it to smeg1. 6'd2: + 2/64*total_num…6'd63: 63/64*total_num */ +#else + unsigned int thShrink6 : 12; /* * [11:0]Hw will indicate software to shrink when actual free nodes percent(free + node number/total free node number) is upper this threshold.Notice: this free node num + ber is equal to the current counter in the list info but not include the free nodes in + the prefetch FIFOBit[5:0] list30,Bit[11:6] list31Eg:For list30, th_shrink _6[5:0] can + indicate 64 shrink water-mark thresholds:6'd0: which means shrink flag will never + generate.you can say Disable shrink water-mark generate.6'd1: 1/64 *total_num,which + means that if the current free node number in free list is larger than 1/64 of total + free node number,abuf0 will set shrink flag and sent it to smeg1. 6'd2: + 2/64*total_num…6'd63: 63/64*total_num */ + unsigned int reserved : 20; /* * [31:12]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_TH_SHK_WM_6_U; + +/* ** +* Union name : SM_ABUF_FLRC_ATTR +* @brief This is the free list reclaim attribute config register.This is used to set up the reclaim +operation on one free list. + +* Description: +*/ +typedef union tagUnSmAbufFlrcAttr { + struct tagStSmAbufFlrcAttr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 22; /* * [31:10]reserved */ + unsigned int stopRclm : 1; /* * [9:9]If sw wants pause or stop reclaim operation while reclaim is running,setup + * this bit.1'b0:cancel stop reclaim.1'b1:stop reclaim. + */ + unsigned int enRclm : 1; /* * [8:8]reclaim start control bit.Sw can setup this bit after configuring upper + boundary,lower boundary,free list id to be reclaim and reclaim fn number.1'b0: reclaim d + isable;1'b1: reclaim enable. */ + unsigned int reserved1 : 3; /* * [7:5]reserved */ + unsigned int flidTorc : 5; /* * [4:0]Free list to be reclaimed (free list 1~31). */ +#else + unsigned int flidTorc : 5; /* * [4:0]Free list to be reclaimed (free list 1~31). */ + unsigned int reserved1 : 3; /* * [7:5]reserved */ + unsigned int enRclm : 1; /* * [8:8]reclaim start control bit.Sw can setup this bit after configuring upper + boundary,lower boundary,free list id to be reclaim and reclaim fn number.1'b0: reclaim d + isable;1'b1: reclaim enable. */ + unsigned int stopRclm : 1; /* * [9:9]If sw wants pause or stop reclaim operation while reclaim is running,setup + * this bit.1'b0:cancel stop reclaim.1'b1:stop reclaim. + */ + unsigned int reserved0 : 22; /* * [31:10]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FLRC_ATTR_U; + +/* ** +* Union name : SM_ABUF_FLRC_NUM +* @brief This is the Sm abuf0 free list reclaim number config register.This is used to set the total +number of free nodes that the software wants to get from the particu lar free list.This register must be set before the +reclaim operation is set up. +* Description: +*/ +typedef union tagUnSmAbufFlrcNum { + struct tagStSmAbufFlrcNum { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 4; /* * [31:28]Reserved */ + unsigned int numRclm : 28; /* * [27:0]Total number of free nodes to be reclaimed. */ +#else + unsigned int numRclm : 28; /* * [27:0]Total number of free nodes to be reclaimed. */ + unsigned int reserved : 4; /* * [31:28]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FLRC_NUM_U; + +/* ** +* Union name : SM_ABUF_FLRC_BOUND_U +* @brief This is the Sm abuf0 reclaim upper boundary config register.This is used to set the upper +boundary of the reclaim region. + +* Description: +*/ +typedef union tagUnSmAbufFlrcBoundU { + struct tagStSmAbufFlrcBoundU { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufFlrcBoundU : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper + free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id + <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */ +#else + unsigned int smAbufFlrcBoundU : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper + free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id + <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FLRC_BOUND_U_U; + +/* ** +* Union name : SM_ABUF_FLRC_BOUND_L +* @brief Sm abuf0 reclaim lower boundary config register. This register is used to set the lower boundary +of the reclaim region. + +* Description: +*/ +typedef union tagUnSmAbufFlrcBoundL { + struct tagStSmAbufFlrcBoundL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufFlrcBoundL : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper + free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id + <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */ +#else + unsigned int smAbufFlrcBoundL : 32; /* * [31:0]For shrink operation,sw config sm_abuf_flrc_bound_u to set upper + free node boundary of reclaim region.if sm_abuf_flrc_bound_l <= fn_id + <=sm_abuf_flrc_bound_uthe n fn_id will be reclaimed to rlist(0). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FLRC_BOUND_L_U; + +/* ** +* Union name : SM_ABUF_PF_LIFO_CLR +* @brief This is the Sm abuf0 pre-fetch lifo clear register.This is used to clear any pfetch lifos if +software wants.(here lifo means Last in first out) + +* Description: +*/ +typedef union tagUnSmAbufPfLifoClr { + struct tagStSmAbufPfLifoClr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufPfLifoClr : 32; /* * [31:0]Pre-fetch lifo clear register.Bit[0]:pre-fetch lifo of list + 0,Bit[1]:pre-fetch lifo of list 1,….Bit[31]:pre-fetch lifo of list 31,Single bit + description:1'b0:no rmal status,not clear the lifo.1'b1:clear status,clear the + lifo.Note: User must config the register to normal status if he wants regarding + list work as normal. */ +#else + unsigned int smAbufPfLifoClr : 32; /* * [31:0]Pre-fetch lifo clear register.Bit[0]:pre-fetch lifo of list + 0,Bit[1]:pre-fetch lifo of list 1,….Bit[31]:pre-fetch lifo of list 31,Single bit + description:1'b0:no rmal status,not clear the lifo.1'b1:clear status,clear the + lifo.Note: User must config the register to normal status if he wants regarding + list work as normal. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_PF_LIFO_CLR_U; + +/* ** + * Union name : SM_ABUF_MEM_CFG + * @brief This is the Sm abuf0 parity bit check enable config register. + * Description: + */ +typedef union tagUnSmAbufMemCfg { + struct tagStSmAbufMemCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 8; /* * [31:24]reserved */ + unsigned int tpRamTmod : 8; /* * [23:16]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int reserved1 : 3; /* * [7:5]reserved */ + unsigned int pbChkEn : 1; /* * [4:4]reserved */ + unsigned int ireqPberrGen : 1; /* * [3:3]reserved */ + unsigned int ibufPberrGen : 1; /* * [2:2]reserved */ + unsigned int infoPberrGen : 1; /* * [1:1]reserved */ + unsigned int lifoPberrGen : 1; /* * [0:0]reserved */ +#else + unsigned int lifoPberrGen : 1; /* * [0:0]reserved */ + unsigned int infoPberrGen : 1; /* * [1:1]reserved */ + unsigned int ibufPberrGen : 1; /* * [2:2]reserved */ + unsigned int ireqPberrGen : 1; /* * [3:3]reserved */ + unsigned int pbChkEn : 1; /* * [4:4]reserved */ + unsigned int reserved1 : 3; /* * [7:5]reserved */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int tpRamTmod : 8; /* * [23:16]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int reserved0 : 8; /* * [31:24]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_MEM_CFG_U; + +/* ** +* Union name : SM_ABUF_INT_VECTOR +* @brief This is the Smart Memory (SM) abuf0 interrupt vector register.This is used to determine the CP +interrupt address, disable and enable an interrupt report,and pr ovide the total status of an abuf0 interrupt. +* Description: +*/ +typedef union tagUnSmAbufIntVector { + struct tagStSmAbufIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]Reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0: No interrupt issued;1: Interrupt issued; CP + * needs to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag that enables all interrupts reported through this + * register. 0: Interrupt disable1: Interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag that enables all interrupts reported through this + * register. 0: Interrupt disable1: Interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0: No interrupt issued;1: Interrupt issued; CP + * needs to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_INT_VECTOR_U; + +/* ** +* Union name : SM_ABUF_INT +* @brief This is the SM abuf0 interrupt data register.This is used to record the history of the interrupt +status since the last clear operation. Software can use this re gister to let the CP know, which CSR module, or group of +CSR modules, requested the interrupt. + +* Description: +*/ +typedef union tagUnSmAbufInt { + struct tagStSmAbufInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID that indicates to the CP, which CSR module, or + group of CSR modules, asked for the interrupt.Eg:Config program_csr_id=8h3,if sw + access the c sr_node whose csr_id=8'h3,the csr_node is in abuf0.it is the member + description,so it is not neccessary to move it. + */ + unsigned int reserved : 10; /* * [15:6]reserved */ + unsigned int intData : 6; /* * [5:0]Interrupt masked field. It is a collection of the error bits from the + * corresponding error registers on the sheet. + */ +#else + unsigned int intData : 6; /* * [5:0]Interrupt masked field. It is a collection of the error bits from the + * corresponding error registers on the sheet. + */ + unsigned int reserved : 10; /* * [15:6]reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID that indicates to the CP, which CSR module, or + group of CSR modules, asked for the interrupt.Eg:Config program_csr_id=8h3,if sw + access the c sr_node whose csr_id=8'h3,the csr_node is in abuf0.it is the member + description,so it is not neccessary to move it. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_INT_U; + +/* ** +* Union name : SM_ABUF_INT_MASK +* @brief This is the SM abuf0 interrupt mask register.This is used to mask the bits of the interrupt +register that should not be reported to an upper level.Software can use this register to mask corresponding bits if they +do not want those bits reporting to an upper level. + +* Description: +*/ +typedef union tagUnSmAbufIntMask { + struct tagStSmAbufIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 10; /* * [15:6]reserved */ + unsigned int errMask : 6; /* * [5:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 6; /* * [5:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 10; /* * [15:6]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_INT_MASK_U; + +/* ** +* Union name : SM_ABUF_PBERR +* @brief This is the ireq_list's output data Parity Bit Error interrupt register.Software can get related +ireq_list information from this register. This register is used for debug. +* Description: +*/ +typedef union tagUnSmAbufPberr { + struct tagStSmAbufPberr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures ireq_list parity error state of the first error capture + even if the mask is off.Sticky[0]:ireq_list parity bit error;Sticky[1]:ireq_buf parit y + bit error;Sticky[3:2]:ReservedSticky[9:4]: address of ireq_list has parity + error.Sticky[15:10]: which address of ireq_buf has parity error.Sticky[29:16]: Res erved + When error_bit or multi_error_bit is set,software can use this register's member to record + the address that has the parity error. + */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures ireq_list parity error state of the first error capture + even if the mask is off.Sticky[0]:ireq_list parity bit error;Sticky[1]:ireq_buf parit y + bit error;Sticky[3:2]:ReservedSticky[9:4]: address of ireq_list has parity + error.Sticky[15:10]: which address of ireq_buf has parity error.Sticky[29:16]: Res erved + When error_bit or multi_error_bit is set,software can use this register's member to record + the address that has the parity error. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_PBERR_U; + +/* ** +* Union name : SM_ABUF_FL_UFLOW_ERR +* @brief This is the free list underflow error interrupt register.This register is used to record the +underflow status of 32 free lists.Any free lists are in underflow s tatus,this register will trigger.This register is +used for debug. Software can use this register to scan the status of 32 free lists. + +* Description: +*/ +typedef union tagUnSmAbufFlUflowErr { + struct tagStSmAbufFlUflowErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures the error state of the first error, capture even if mask + is off. Sticky[4:0]: The list ID that was in an underflow state.Stick[29]:0-underflo w + because get from uneable dis-allocate list 1-underflow because get from empty + list;Sticky[28:5]: Reserved.When the error_bit or even the multi_error _bit is + set,software can use this member of the register to record the list ID. For example, when + list 0 is empty, an allocate request will load list0 to be un derflow. */ + unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0: No error founded1: Error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0: No error founded1: Error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures the error state of the first error, capture even if mask + is off. Sticky[4:0]: The list ID that was in an underflow state.Stick[29]:0-underflo w + because get from uneable dis-allocate list 1-underflow because get from empty + list;Sticky[28:5]: Reserved.When the error_bit or even the multi_error _bit is + set,software can use this member of the register to record the list ID. For example, when + list 0 is empty, an allocate request will load list0 to be un derflow. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FL_UFLOW_ERR_U; + +/* ** +* Union name : SM_ABUF_FL_OFLOW_ERR +* @brief This is the free list overflow error interrupt register.This register is used to record the +overflow status of 32 free lists.If any free lists are in an overfl ow state,this register will trigger.This register +is used for debug. Software can use this register to scan the status of the 32 free lists. + +* Description: +*/ +typedef union tagUnSmAbufFlOflowErr { + struct tagStSmAbufFlOflowErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures the error state of the first error. It captures this + even if the mask is off.Sticky[4:0]: The list ID that was in an overflow state.Stick[2 + 9]:0-overflow because put into unenable allocate list 1-overflow because put into + a full list;Sticky[28:5]: Reserved.While the error_bit or even the m ulti_error_bit is + set,software can use this member of the register to record corresponding list ID. For + example, when list0 is full,an de-allocate request will load list0 to be overflow. */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures the error state of the first error. It captures this + even if the mask is off.Sticky[4:0]: The list ID that was in an overflow state.Stick[2 + 9]:0-overflow because put into unenable allocate list 1-overflow because put into + a full list;Sticky[28:5]: Reserved.While the error_bit or even the m ulti_error_bit is + set,software can use this member of the register to record corresponding list ID. For + example, when list0 is full,an de-allocate request will load list0 to be overflow. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FL_OFLOW_ERR_U; + +/* ** +* Union name : SM_ABUF_FL_TAIL_MISS_ERR +* @brief This is the tail missed error interrupt register.This is used to capture information of regarding +list whose tail pointer is not equal to the last pointer of th e link list,when the free node group(including the last +pointer) is load from outside DDR.This register is used for debug. + +* Description: +*/ +typedef union tagUnSmAbufFlTailMissErr { + struct tagStSmAbufFlTailMissErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures error state of the first error, capture even if mask is + off.Sticky[4:0]:the list id that was tail missed.Sticky[29:5] reserve.While error_bit or + even multi_error_bit was set,software can use this member of the register to record + corresponding list id. If error_bit or multi_error_bit is set,that means the free + list(sticy[4:0]) has been destroyed. */ + unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0: No error founded1: Error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0: No error founded1: Error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0: Not more than 1 error founded1: More than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]Abuf0 csr captures error state of the first error, capture even if mask is + off.Sticky[4:0]:the list id that was tail missed.Sticky[29:5] reserve.While error_bit or + even multi_error_bit was set,software can use this member of the register to record + corresponding list id. If error_bit or multi_error_bit is set,that means the free + list(sticy[4:0]) has been destroyed. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FL_TAIL_MISS_ERR_U; + +/* ** + * Union name : SMEG0_ABUF_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmeg0AbufIndrectCtrl { + struct tagStSmeg0AbufIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AbufIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect + access invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ + unsigned int smeg0AbufIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0AbufIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0AbufIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:ireq list0x1:ireq + * buffer0x2:list info0x3:pfetch lifoothers:reserved + */ + unsigned int + smeg0AbufIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in + one group or internal address of the table.Bit[9:2]memory block read/write + address.differe nt memory block has different address depth and data width. User should + operate on valid address.For SML:Mem_sel Mem_addr 2'b00 0~15 2'b01 0~152'b10 + 0~31 (DATA) 32~63 (ECC)2'b11 0~127 (DATA) 128~255(ECC)For SMF:Mem_sel + Mem_addr 2'b00 0~31 2'b01 0~312'b10 0~31 (DATA, Read a nd Write) 32~63 (ECC, + read only)2'b11 0~127 (DATA, read and write) 128~255(ECC read + only)-----------------------------bit[1:0]Memory entry Index.Access order:big endian + which LSB accessed by higher address.For ireq list access,0x0~0x2:reserved.0x3: + data[31:0]For ireq_buf access,the memory data widt h of ireq_buf is 38 bit.each entry + index can only access 32bit data. so user should access ireq_buf twice to get 38bit + data.the entry index should be:0x0~0x1:re served.0x2: data[37:32]0x3: data[31:0]For + list info and prefetch lifo,the memory width is 128 bits.each entry index can only + access 32bit data.so user should ac cess list info a four times to get 128 bit + data.0x0:data[127:96]0x1:data[95:64]0x2:data[63:32]0x3:data[31:0] 0x0: {25'd0,ECC[6:0]} + for data[127:96]0x1: {25'd0,E CC[6:0]} for data[95:64]0x2: {25'd0,ECC[6:0]} for + data[63:32]0x3: {25'd0,ECC[6:0]} for data[31:0]BTW: prefetch does not support dynamic + write and if S/W want to + write continous 128 bit, its write address[1:0] must guarantee from 0x3 to 0x0. */ +#else + unsigned int + smeg0AbufIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in + one group or internal address of the table.Bit[9:2]memory block read/write + address.differe nt memory block has different address depth and data width. User should + operate on valid address.For SML:Mem_sel Mem_addr 2'b00 0~15 2'b01 0~152'b10 + 0~31 (DATA) 32~63 (ECC)2'b11 0~127 (DATA) 128~255(ECC)For SMF:Mem_sel + Mem_addr 2'b00 0~31 2'b01 0~312'b10 0~31 (DATA, Read a nd Write) 32~63 (ECC, + read only)2'b11 0~127 (DATA, read and write) 128~255(ECC read + only)-----------------------------bit[1:0]Memory entry Index.Access order:big endian + which LSB accessed by higher address.For ireq list access,0x0~0x2:reserved.0x3: + data[31:0]For ireq_buf access,the memory data widt h of ireq_buf is 38 bit.each entry + index can only access 32bit data. so user should access ireq_buf twice to get 38bit + data.the entry index should be:0x0~0x1:re served.0x2: data[37:32]0x3: data[31:0]For + list info and prefetch lifo,the memory width is 128 bits.each entry index can only + access 32bit data.so user should ac cess list info a four times to get 128 bit + data.0x0:data[127:96]0x1:data[95:64]0x2:data[63:32]0x3:data[31:0] 0x0: {25'd0,ECC[6:0]} + for data[127:96]0x1: {25'd0,E CC[6:0]} for data[95:64]0x2: {25'd0,ECC[6:0]} for + data[63:32]0x3: {25'd0,ECC[6:0]} for data[31:0]BTW: prefetch does not support dynamic + write and if S/W want to + write continous 128 bit, its write address[1:0] must guarantee from 0x3 to 0x0. */ + unsigned int smeg0AbufIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:ireq list0x1:ireq + * buffer0x2:list info0x3:pfetch lifoothers:reserved + */ + unsigned int smeg0AbufIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0AbufIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0AbufIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect + access invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_ABUF_INDRECT_CTRL_U; + +/* ** + * Union name : SMEG0_ABUF_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmeg0AbufIndrectTimeout { + struct tagStSmeg0AbufIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AbufIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smeg0AbufIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_ABUF_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMEG0_ABUF_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmeg0AbufIndrectData { + struct tagStSmeg0AbufIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + smeg0AbufIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send these + data to target.When operation read: Logic write data to these registers and refresh + xxx_indir_stat, software will get these data from target.ireq list:bit[7] :even pa rity + check bit of bit[6:0]bit[6:0]: dataireq buffer:bit[37]:even parity check bit of + bit[36:32]bit[31]:even parity check bit of bit[31:0]bit[36:32],bit[30:0]: d atalist + info:bit[31],bit[63],bit[95],bit[127] : even parity check bits of + bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bit[126:96 + ] : data.pfetch lifo:bit[31],bit[63],bit[95],bit[127] : even parity check bits of + bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bi + t[126:96] : data. */ +#else + unsigned int + smeg0AbufIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send these + data to target.When operation read: Logic write data to these registers and refresh + xxx_indir_stat, software will get these data from target.ireq list:bit[7] :even pa rity + check bit of bit[6:0]bit[6:0]: dataireq buffer:bit[37]:even parity check bit of + bit[36:32]bit[31]:even parity check bit of bit[31:0]bit[36:32],bit[30:0]: d atalist + info:bit[31],bit[63],bit[95],bit[127] : even parity check bits of + bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bit[126:96 + ] : data.pfetch lifo:bit[31],bit[63],bit[95],bit[127] : even parity check bits of + bit[30:0],bit[62:32],bit[94:64],bit[126:96].bit[30:0],bit[62:32],bit[94:64],bi + t[126:96] : data. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_ABUF_INDRECT_DATA_U; + +/* ** +* Union name : SM_ABUF_DIS_ALLOC +* @brief This is the SM Abuf0 disable allocation config register.This is used by software to disable the +allocate operation if you do not want to release any free nodes from the particular list. +* Description: +*/ +typedef union tagUnSmAbufDisAlloc { + struct tagStSmAbufDisAlloc { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufDisAlloc : 32; /* * [31:0]SM Application Buffer's disable allocation.1'b0: Enable,1'b1: + * Disable.Bit[0] free list 0,Bit[1] free list 1,Bit[2] free list 2,...Bit[31] + * free list 31. + */ +#else + unsigned int smAbufDisAlloc : 32; /* * [31:0]SM Application Buffer's disable allocation.1'b0: Enable,1'b1: + * Disable.Bit[0] free list 0,Bit[1] free list 1,Bit[2] free list 2,...Bit[31] + * free list 31. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_DIS_ALLOC_U; + +/* ** +* Union name : SM_ABUF_DIS_DE_ALLOC +* @brief This is the SM Abuf0 de_allocate disable config register.This is used by software to disable the +de-allocate operation if you do not want to put any free nodes to the particular list. +* Description: +*/ +typedef union tagUnSmAbufDisDeAlloc { + struct tagStSmAbufDisDeAlloc { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufDisDeAlloc : 32; /* * [31:0]SM Application Buffer's disable + * de-allocation.1'b0:enable,1'b1:disable.Bit[0] free list 0,Bit[1] free + * list 1,Bit[2] free list 2,...Bit[31] free list 31. + */ +#else + unsigned int smAbufDisDeAlloc : 32; /* * [31:0]SM Application Buffer's disable + * de-allocation.1'b0:enable,1'b1:disable.Bit[0] free list 0,Bit[1] free + * list 1,Bit[2] free list 2,...Bit[31] free list 31. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_DIS_DE_ALLOC_U; + +/* ** +* Union name : SM_ABUF_FLRC_ST +* @brief This is the Sm abuf0 free list reclaim status register.This is used by the software to scan the +reclaimed working state. + +* Description: +*/ +typedef union tagUnSmAbufFlrcSt { + struct tagStSmAbufFlrcSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 28; /* * [31:4]This register is for reboundary function. It will be accessed by the software + during the re-boundary operation.bit[31:4] rclm_cnt:reclaim counter,this counter + compare with rclm_num, rclm_cnt=rclm_num means relcaim will be finished. */ + unsigned int reserved : 1; /* * [3:3]reserved */ + unsigned int wlistCleaning : 1; /* * [2:2]wlist clean status register.1'b0:wlist is not being clean.1'b1:wlist + * is being clean. + */ + unsigned int rlistCleaning : 1; /* * [1:1]reclaim list clean status register.1'b0: The reclaim list is not + * being clean.1'b1: The reclaim list is being clean. + */ + unsigned int doneRclm : 1; /* * [0:0]free list reclaim states.1'b0: Reclaim not done;1'b1: Reclaim done. */ +#else + unsigned int doneRclm : 1; /* * [0:0]free list reclaim states.1'b0: Reclaim not done;1'b1: Reclaim done. */ + unsigned int rlistCleaning : 1; /* * [1:1]reclaim list clean status register.1'b0: The reclaim list is not + * being clean.1'b1: The reclaim list is being clean. + */ + unsigned int wlistCleaning : 1; /* * [2:2]wlist clean status register.1'b0:wlist is not being clean.1'b1:wlist + * is being clean. + */ + unsigned int reserved : 1; /* * [3:3]reserved */ + unsigned int ctp : 28; /* * [31:4]This register is for reboundary function. It will be accessed by the software + during the re-boundary operation.bit[31:4] rclm_cnt:reclaim counter,this counter + compare with rclm_num, rclm_cnt=rclm_num means relcaim will be finished. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FLRC_ST_U; + +/* ** +* Union name : SM_ABUF_EMPTY_FL +* @brief This is the Sm abuf0 free list empty status register.This is used by software to scan whether +regarding list is empty or not. + +* Description: +*/ +typedef union tagUnSmAbufEmptyFl { + struct tagStSmAbufEmptyFl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]Free list empty bitmap,index with free list id: 1'b0: Not empty;1'b1: both + * pre-fetch lifo and external DDR is Empty. + */ +#else + unsigned int ctp : 32; /* * [31:0]Free list empty bitmap,index with free list id: 1'b0: Not empty;1'b1: both + * pre-fetch lifo and external DDR is Empty. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_EMPTY_FL_U; + +/* ** +* Union name : SM_ABUF_FULL_FL +* @brief This is the Sm abuf0 free list full/almost full status register.This is used by the software to +scan whether the list is full, almost full, or none of the above + . +* Description: +*/ +typedef union tagUnSmAbufFullFl { + struct tagStSmAbufFullFl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]Free list full status bitmap. Index with free list id: 1'b0: Not full;1'b1: + Full.Full means the total free nodes number in both pre-fetch lifo and external DD + R is equal or larger than the Total number configured in list info. */ +#else + unsigned int ctp : 32; /* * [31:0]Free list full status bitmap. Index with free list id: 1'b0: Not full;1'b1: + Full.Full means the total free nodes number in both pre-fetch lifo and external DD + R is equal or larger than the Total number configured in list info. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_FULL_FL_U; + +/* ** +* Union name : SM_ABUF_ST_WM_GROW +* @brief This is the Sm abuf0 free list grow watermark status register.This is used by the softeware to +scan whether the free list is in status that need to grow. + +* Description: +*/ +typedef union tagUnSmAbufStWmGrow { + struct tagStSmAbufStWmGrow { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for growth. Index with free list ID. 1'b0: Used + watermark is lower than the growth threshold;1'b1: Used watermark is more than the growth + threshold.NOTE:this state update when rtl or csr write list info,so if want to change new + watermark and total cnt,must change watermark first. + */ +#else + unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for growth. Index with free list ID. 1'b0: Used + watermark is lower than the growth threshold;1'b1: Used watermark is more than the growth + threshold.NOTE:this state update when rtl or csr write list info,so if want to change new + watermark and total cnt,must change watermark first. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_ST_WM_GROW_U; + +/* ** +* Union name : SM_ABUF_ST_WM_SHRINK +* @brief This is the Sm abuf0 free list shrink watermark status register.This is used by the softeware to +scan whether the free list is in a shrink status. + +* Description: +*/ +typedef union tagUnSmAbufStWmShrink { + struct tagStSmAbufStWmShrink { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for shrink. Index with free list ID. 1'b0: + Watermark is lower than the shrink threshold;1'b1: Watermark is more than the shrink thr + eshold.NOTE:this state update when rtl or csr write list info,so if want to change new + watermark and total cnt,must change watermark first. + */ +#else + unsigned int ctp : 32; /* * [31:0]Free list water mark bitmap for shrink. Index with free list ID. 1'b0: + Watermark is lower than the shrink threshold;1'b1: Watermark is more than the shrink thr + eshold.NOTE:this state update when rtl or csr write list info,so if want to change new + watermark and total cnt,must change watermark first. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_ST_WM_SHRINK_U; + +/* ** +* Union name : SM_ABUF_CNT_SEL0 +* @brief This is the Sm abuf0 csr counter select config register.This is used to select which free list +must be counted. + +* Description: +*/ +typedef union tagUnSmAbufCntSel0 { + struct tagStSmAbufCntSel0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int cnt3EventSel : 3; /* * [31:29]counter 3 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt3SrcSel : 5; /* * [28:24]counter 3 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt2EventSel : 3; /* * [23:21]counter 2 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt2SrcSel : 5; /* * [20:16]counter 2 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt1EventSel : 3; /* * [15:13]counter 1 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt1SrcSel : 5; /* * [12:8]counter 1 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt0EventSel : 3; /* * [7:5]counter 0 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt0SrcSel : 5; /* * [4:0]counter 5 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ +#else + unsigned int cnt0SrcSel : 5; /* * [4:0]counter 5 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt0EventSel : 3; /* * [7:5]counter 0 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt1SrcSel : 5; /* * [12:8]counter 1 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt1EventSel : 3; /* * [15:13]counter 1 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt2SrcSel : 5; /* * [20:16]counter 2 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt2EventSel : 3; /* * [23:21]counter 2 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt3SrcSel : 5; /* * [28:24]counter 3 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt3EventSel : 3; /* * [31:29]counter 3 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_CNT_SEL0_U; + +/* ** +* Union name : SM_ABUF_CNT_SEL1 +* @brief Sm abuf ireq list status register.Sw can use this register to judge if the request queue is empty +or not. + +* Description: +*/ +typedef union tagUnSmAbufCntSel1 { + struct tagStSmAbufCntSel1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved */ + unsigned int cntEnable : 6; /* * [21:16]counter enable/disable register.User can config this member to enable or + diable any counter.Cnt_en[0] counter 0 enable/disabale cfg bit.Cnt_en[1] counter 0 enab + le/disabale cfg bit.Cnt_en[2] counter 0 enable/disabale cfg bit.Cnt_en[3] counter 0 + enable/disabale cfg bit.Cnt_en[4] counter 0 enable/disabale cfg bit.Cnt_en[5 + ] counter 0 enable/disabale cfg bit. */ + unsigned int cnt5EventSel : 3; /* * [15:13]counter 5 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt5SrcSel : 5; /* * [12:8]counter 5 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt4EventSel : 3; /* * [7:5]counter 4 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt4SrcSel : 5; /* * [4:0]counter 4 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ +#else + unsigned int cnt4SrcSel : 5; /* * [4:0]counter 4 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt4EventSel : 3; /* * [7:5]counter 4 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cnt5SrcSel : 5; /* * [12:8]counter 5 source selection.5'h0:count free list0,5'h1:count free + * list1,....5'h31:count free list 31. + */ + unsigned int cnt5EventSel : 3; /* * [15:13]counter 5 event selection.3'b000:count get op.3'b001:count put + * op.3'b010:count get fail op.3'b011:count put fail op.3'b100:count ld + * op.3'b101:count st op. + */ + unsigned int cntEnable : 6; /* * [21:16]counter enable/disable register.User can config this member to enable or + diable any counter.Cnt_en[0] counter 0 enable/disabale cfg bit.Cnt_en[1] counter 0 enab + le/disabale cfg bit.Cnt_en[2] counter 0 enable/disabale cfg bit.Cnt_en[3] counter 0 + enable/disabale cfg bit.Cnt_en[4] counter 0 enable/disabale cfg bit.Cnt_en[5 + ] counter 0 enable/disabale cfg bit. */ + unsigned int reserved : 10; /* * [31:22]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_CNT_SEL1_U; + +/* ** +* Union name : SM_ABUF_COUNTER0 +* @brief This is the Sm abuf0 allocate free node count register.This is used to count the free nodes that +have been allocated successfully by abuf0. + +* Description: +*/ +typedef union tagUnSmAbufCounter0 { + struct tagStSmAbufCounter0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter0 : 32; /* * [31:0]Counter 0 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter0 : 32; /* * [31:0]Counter 0 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER0_U; + +/* ** +* Union name : SM_ABUF_COUNTER1 +* @brief This is the Sm abuf0 de-allocate free node count register.This is used to count the free nodes +that have been de-allocated successfully by abuf0. + +* Description: +*/ +typedef union tagUnSmAbufCounter1 { + struct tagStSmAbufCounter1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter1 : 32; /* * [31:0]Counter 1 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter1 : 32; /* * [31:0]Counter 1 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER1_U; + +/* ** +* Union name : SM_ABUF_COUNTER2 +* @brief This is the allocate failed operation count register.This is used to count the total number of +failed allocate operation attempts. + +* Description: +*/ +typedef union tagUnSmAbufCounter2 { + struct tagStSmAbufCounter2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter2 : 32; /* * [31:0]Counter 2 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter2 : 32; /* * [31:0]Counter 2 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER2_U; + +/* ** +* Union name : SM_ABUF_COUNTER3 +* @brief This is the Sm abuf0 de-allocate failed operation count register.This is used to count the total +number of failed de-allocate operation attempts. + +* Description: +*/ +typedef union tagUnSmAbufCounter3 { + struct tagStSmAbufCounter3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter3 : 32; /* * [31:0]Counter 3 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter3 : 32; /* * [31:0]Counter 3 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER3_U; + +/* ** +* Union name : SM_ABUF_COUNTER4 +* @brief This is the Sm abuf0 total pre-fetch load operation count register.This is used to count the +total number of pre-fetched load operations. + +* Description: +*/ +typedef union tagUnSmAbufCounter4 { + struct tagStSmAbufCounter4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter4 : 32; /* * [31:0]Counter 4 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter4 : 32; /* * [31:0]Counter 4 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER4_U; + +/* ** +* Union name : SM_ABUF_COUNTER5 +* @brief This is the Sm abuf0 total pre-fetch store operation count register.This is used to count the +total pre-fetched store operations. + +* Description: +*/ +typedef union tagUnSmAbufCounter5 { + struct tagStSmAbufCounter5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smAbufCounter5 : 32; /* * [31:0]Counter 5 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#else + unsigned int smAbufCounter5 : 32; /* * [31:0]Counter 5 used to count one event which configured in + SM_ABUF_CNT_SEL. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_COUNTER5_U; + +/* ** +* Union name : SM_ABUF_PFETCH_FLAG +* @brief Sm abuf pre-fetch load/store setup flag.This is used to record which free list has initiated +pre-fetch load/store operation. + +* Description: +*/ +typedef union tagUnSmAbufPfetchFlag { + struct tagStSmAbufPfetchFlag { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]record the pfe-fetch load/store status of 32 free lists.Bit[0]:list 0 + pre-fetch ld/st flag.Bit[1]:list 0 pre-fetch ld/st flag....Bit[31]:list 0 pre-fetch ld/st + flag.Corresponding bit will be set when one list has initiated pre-fetch load or store + operation to smmc.Corresponding bit will be clear when one list has recei ve pre-fetch load + reture or store grant from smmc. */ +#else + unsigned int ctp : 32; /* * [31:0]record the pfe-fetch load/store status of 32 free lists.Bit[0]:list 0 + pre-fetch ld/st flag.Bit[1]:list 0 pre-fetch ld/st flag....Bit[31]:list 0 pre-fetch ld/st + flag.Corresponding bit will be set when one list has initiated pre-fetch load or store + operation to smmc.Corresponding bit will be clear when one list has recei ve pre-fetch load + reture or store grant from smmc. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_PFETCH_FLAG_U; + +/* ** +* Union name : SM_ABUF_IREQ_LIST_STA +* @brief Sm abuf ireq list status register.Sw can use this register to judge if the request queue is empty +or not. + +* Description: +*/ +typedef union tagUnSmAbufIreqListSta { + struct tagStSmAbufIreqListSta { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]ctp[0]:request queue status of free list0,ctp[1]:request queue status of free + list1,...ctp[31]:request queue status of free list31.1'b0:request queue is empty,1 + 'b1:request queue is not empty. */ +#else + unsigned int ctp : 32; /* * [31:0]ctp[0]:request queue status of free list0,ctp[1]:request queue status of free + list1,...ctp[31]:request queue status of free list31.1'b0:request queue is empty,1 + 'b1:request queue is not empty. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_IREQ_LIST_STA_U; + +/* ** +* Union name : SM_ABUF_TAIL_MISS0 +* @brief This is the SM abuf0 tail miss capture register. This is used to capture the information of the +tail-missed free list. + +* Description: +*/ +typedef union tagUnSmAbufTailMiss0 { + struct tagStSmAbufTailMiss0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0: Trigger is disable1: Trigger enableAbuf0 compares tail + pointer in external DDR with tail pointer in internal list_info,if they are + mismatched,this bit will be set,and regarding information will be captured in + capture_data. */ + unsigned long long captureData : 63; /* * [62:0]Capture regarding information of the free list whose tail has + missed. capture low 64bit of the following information;bit[29:0] list old + tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list + counterbit[122:118] list id. */ +#else + unsigned long long captureData : 63; /* * [62:0]Capture regarding information of the free list whose tail has + missed. capture low 64bit of the following information;bit[29:0] list old + tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list + counterbit[122:118] list id. */ + unsigned long long triggerEnable : 1; /* * [63:63]0: Trigger is disable1: Trigger enableAbuf0 compares tail + pointer in external DDR with tail pointer in internal list_info,if they are + mismatched,this bit will be set,and regarding information will be captured in + capture_data. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SM_ABUF_TAIL_MISS0_U; + +/* ** +* Union name : SM_ABUF_TAIL_MISS1 +* @brief This is the SM abuf0 tail miss capture register. This is used to capture the information of the +tail-missed free list. + +* Description: +*/ +typedef union tagUnSmAbufTailMiss1 { + struct tagStSmAbufTailMiss1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long triggerEnable : 1; /* * [63:63]0: Trigger is disable1: Trigger enableAbuf0 compares tail + pointer in external DDR with tail pointer in internal list_info,if they are + mismatched,this bit will be set,and regarding information will be captured in + capture_data. */ + unsigned long long captureData : 63; /* * [62:0]Capture regarding information of the free list whose tail has + missed.capture high 64bit of the following information;bit[29:0] list old + tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list + counterbit[122:118] list id. */ +#else + unsigned long long captureData : 63; /* * [62:0]Capture regarding information of the free list whose tail has + missed.capture high 64bit of the following information;bit[29:0] list old + tailbit[59:30] list old headbit[89:60] list new tailbit[117:90] list + counterbit[122:118] list id. */ + unsigned long long triggerEnable : 1; /* * [63:63]0: Trigger is disable1: Trigger enableAbuf0 compares tail + pointer in external DDR with tail pointer in internal list_info,if they are + mismatched,this bit will be set,and regarding information will be captured in + capture_data. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SM_ABUF_TAIL_MISS1_U; + +/* ** +* Union name : SM_ABUF_CNT_LIFO_PFETCH_0 +* @brief This is the Sm abuf0 pfetch lifo node number register.This is used to record the free node number +in each pfetch lifo. + +* Description: +*/ +typedef union tagUnSmAbufCntLifoPfetch0 { + struct tagStSmAbufCntLifoPfetch0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to + free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre + -fetch lifo has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of free list + 0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of + free list 31, */ +#else + unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to + free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre + -fetch lifo has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of free list + 0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of + free list 31, */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SM_ABUF_CNT_LIFO_PFETCH_0_U; + +/* ** +* Union name : SM_ABUF_CNT_LIFO_PFETCH_1 +* @brief This is the Sm abuf0 pfetch lifo node number register.This is used to record the free node number +in each pfetch lifo. + +* Description: +*/ +typedef union tagUnSmAbufCntLifoPfetch1 { + struct tagStSmAbufCntLifoPfetch1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to + free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre + -fetch lifo has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of free list + 0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of + free list 31, */ +#else + unsigned long long ctp : 64; /* * [63:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to + free list 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre + -fetch lifo has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of free list + 0,Bit[7:4] pre-fetch lifo counter of free list 1,...Bit[127:124] pre-fe tch lifo counter of + free list 31, */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SM_ABUF_CNT_LIFO_PFETCH_1_U; + +/* ** +* Union name : SM_ABUF_CNT_LIFO_PFETCH_2 +* @brief This is the Sm abuf0 pfetch lifo node number register.This is used to record the free node number +in each pfetch lifo. + +* Description: +*/ +typedef union tagUnSmAbufCntLifoPfetch2 { + struct tagStSmAbufCntLifoPfetch2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int ctp : 4; /* * [3:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to free list + 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre -fetch lifo + has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of Rebounding free list. + */ +#else + unsigned int ctp : 4; /* * [3:0]There are 33 pre-fetch lifo in abuf0,lifo 0~lifo31 is corresponding to free list + 0~31,lifo32 is used for reboundary list to accelerate shrink operation.Each pre -fetch lifo + has a 4-bit free node counter. Bit[3:0] pre-fetch lifo counter of Rebounding free list. + */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_CNT_LIFO_PFETCH_2_U; + +/* ** + * Union name : SM_ABUF_ECC_CFG + * @brief SMEG0_ABUF ECC function configration register + * Description: + */ +typedef union tagUnSmAbufEccCfg { + struct tagStSmAbufEccCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 24; /* * [31:8]Reserved */ + unsigned int reserved1 : 1; /* * [7:7]Reserved */ + unsigned int lifoEccEn : 1; /* * [6:6]Bypass ECC function of lifo info memory1: enable ecc function0: bypass ecc + * function + */ + unsigned int lifo2bEccInjEn : 1; /* * [5:5]Enable to inject Dual ECC Error when read lifo memory0: disable1: + enable */ + unsigned int lifo1bEccInjEn : 1; /* * [4:4]Enable to inject Single ECC Error when read lifo memory0: disable1: + enable */ + unsigned int reserved2 : 1; /* * [3:3]Reserved */ + unsigned int listInfoEccEn : 1; /* * [2:2]Enable ECC function of list info memory1: enable ecc function0: bypass + * ecc function + */ + unsigned int listInfo2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read list info memory0: + disable1: enable */ + unsigned int listInfo1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read list info memory0: + disable1: enable */ +#else + unsigned int listInfo1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read list info memory0: + disable1: enable */ + unsigned int listInfo2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read list info memory0: + disable1: enable */ + unsigned int listInfoEccEn : 1; /* * [2:2]Enable ECC function of list info memory1: enable ecc function0: bypass + * ecc function + */ + unsigned int reserved2 : 1; /* * [3:3]Reserved */ + unsigned int lifo1bEccInjEn : 1; /* * [4:4]Enable to inject Single ECC Error when read lifo memory0: disable1: + enable */ + unsigned int lifo2bEccInjEn : 1; /* * [5:5]Enable to inject Dual ECC Error when read lifo memory0: disable1: + enable */ + unsigned int lifoEccEn : 1; /* * [6:6]Bypass ECC function of lifo info memory1: enable ecc function0: bypass ecc + * function + */ + unsigned int reserved1 : 1; /* * [7:7]Reserved */ + unsigned int reserved0 : 24; /* * [31:8]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_ECC_CFG_U; + +/* ** + * Union name : SM_ABUF_ECC_1B_ERR_INT + * @brief 1 bit error sticky register + * Description: + */ +typedef union tagUnSmAbufEcc1bErrInt { + struct tagStSmAbufEcc1bErrInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Sticky[0]:list info 1 bit ECC error;Sticky[1]:pfetch lifo 1 bit ECC + error;Sticky[6:2]: which address of list info has 1 bit error.Sticky[13:7] which address + of pfetch lifo has 1bit error.Sticky[29:14]: reserved */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int sticky : 30; /* * [31:2]Sticky[0]:list info 1 bit ECC error;Sticky[1]:pfetch lifo 1 bit ECC + error;Sticky[6:2]: which address of list info has 1 bit error.Sticky[13:7] which address + of pfetch lifo has 1bit error.Sticky[29:14]: reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_ECC_1B_ERR_INT_U; + +/* ** + * Union name : SM_ABUF_ECC_2B_ERR_INT + * @brief 2 bit error sticky register + * Description: + */ +typedef union tagUnSmAbufEcc2bErrInt { + struct tagStSmAbufEcc2bErrInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]Sticky[0]:list info 2 bit ECC error;Sticky[1]:pfetch lifo 2 bit ECC + error;Sticky[6:2]: which address of list info has 2 bit error.Sticky[13:7] which address + of pfetch lifo has 2 bit error.Sticky[29:14]: reserved */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]0: No error found. 1: Error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]0: No more than 1 error found.1: More than 1 error found. */ + unsigned int sticky : 30; /* * [31:2]Sticky[0]:list info 2 bit ECC error;Sticky[1]:pfetch lifo 2 bit ECC + error;Sticky[6:2]: which address of list info has 2 bit error.Sticky[13:7] which address + of pfetch lifo has 2 bit error.Sticky[29:14]: reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SM_ABUF_ECC_2B_ERR_INT_U; + + +/* ** + * Union name : SMEG0_AGET_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmeg0AgetVersion { + struct tagStSmeg0AgetVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AgetVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smeg0AgetVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_VERSION_U; + +/* ** + * Union name : SMEG0_AGET_CFG + * @brief age table configure registers + * Description: + */ +typedef union tagUnSmeg0AgetCfg { + struct tagStSmeg0AgetCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21]reserved */ + unsigned int smeg0Cnt1Cfg : 2; /* * [20:19]smeg0_cnt1 configure:bit0:enable, 1-enable, 0-disable;bit1:source + * select, 1-counter for smeg0_ALU 0-counter for smeg0_AGET + */ + unsigned int smeg0Cnt0Cfg : 2; /* * [18:17]smeg0_cnt0 configure:as same as the Comments of smeg0_cnt1_cfg */ + unsigned int smegCoreMemInitStart : 1; /* * [16:16]A posedge of this bit will triggle memory in smeg_core init + start. */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int reserved1 : 7; /* * [7:1]reserved */ + unsigned int memChkEn : 1; /* * [0:0]memory parity check enable.1'b0:disable all memories err check.1'b1:enable + * all memories err check. + */ +#else + unsigned int memChkEn : 1; /* * [0:0]memory parity check enable.1'b0:disable all memories err check.1'b1:enable + * all memories err check. + */ + unsigned int reserved1 : 7; /* * [7:1]reserved */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int smegCoreMemInitStart : 1; /* * [16:16]A posedge of this bit will triggle memory in smeg_core init + start. */ + unsigned int smeg0Cnt0Cfg : 2; /* * [18:17]smeg0_cnt0 configure:as same as the Comments of smeg0_cnt1_cfg */ + unsigned int smeg0Cnt1Cfg : 2; /* * [20:19]smeg0_cnt1 configure:bit0:enable, 1-enable, 0-disable;bit1:source + * select, 1-counter for smeg0_ALU 0-counter for smeg0_AGET + */ + unsigned int reserved0 : 11; /* * [31:21]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_CFG_U; + +/* ** + * Union name : SMEG0_AGET_INT_VECTOR + * @brief interrupt vector + * Description: + */ +typedef union tagUnSmeg0AgetIntVector { + struct tagStSmeg0AgetIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INT_VECTOR_U; + +/* ** + * Union name : SMEG0_AGET_INT + * @brief interrupt data + * Description: + */ +typedef union tagUnSmeg0AgetInt { + struct tagStSmeg0AgetInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int intData : 2; /* * [1:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 2; /* * [1:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INT_U; + +/* ** + * Union name : SMEG0_AGET_INT_MASK + * @brief interrupt mask + * Description: + */ +typedef union tagUnSmeg0AgetIntMask { + struct tagStSmeg0AgetIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INT_MASK_U; + +/* ** + * Union name : SMEG0_AGET_MEM_PRTY_ERR + * @brief SMEG0_AGET age flag memory parity error + * Description: + */ +typedef union tagUnSmeg0AgetMemPrtyErr { + struct tagStSmeg0AgetMemPrtyErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:8]: reserved[7:0] memory index of parity error + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:8]: reserved[7:0] memory index of parity error + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_MEM_PRTY_ERR_U; + +/* ** + * Union name : SMEG0_AGET_BOUNDARY_ERR + * @brief SMEG0_AGET operation is out of the table boundary + * Description: + */ +typedef union tagUnSmeg0AgetBoundaryErr { + struct tagStSmeg0AgetBoundaryErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + others: reserved[13:8]:instance ID[7:0]: operation index of error (the original index rece + ived from SMEG1) */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + others: reserved[13:8]:instance ID[7:0]: operation index of error (the original index rece + ived from SMEG1) */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_BOUNDARY_ERR_U; + +/* ** + * Union name : SMEG0_AGET_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmeg0AgetIndrectCtrl { + struct tagStSmeg0AgetIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AgetIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect + access invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ + unsigned int smeg0AgetIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0AgetIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0AgetIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: base address + * table;4’b0001: age flag memory;others:reserved + */ + unsigned int smeg0AgetIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory + address in one group or internal address of the table.Base address table: + bit7:2: instance ID; bit7 is RSV in SMF Age flag MEM: bit9:2: memory + indexbit[1:0] word select: 0:reserved, 1:mem_dat[95:64] 2:mem_dat[63:32] + 3:mem_dat[31:0]Note: for accessing + base address table,bit[1:0] should be 2'h3. */ +#else + unsigned int smeg0AgetIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory + address in one group or internal address of the table.Base address table: + bit7:2: instance ID; bit7 is RSV in SMF Age flag MEM: bit9:2: memory + indexbit[1:0] word select: 0:reserved, 1:mem_dat[95:64] 2:mem_dat[63:32] + 3:mem_dat[31:0]Note: for accessing + base address table,bit[1:0] should be 2'h3. */ + unsigned int smeg0AgetIndirTab : 4; /* * [27:24]It specifies memory group or table. 4’b0000: base address + * table;4’b0001: age flag memory;others:reserved + */ + unsigned int smeg0AgetIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0AgetIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0AgetIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect + access invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INDRECT_CTRL_U; + +/* ** + * Union name : SMEG0_AGET_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmeg0AgetIndrectTimeout { + struct tagStSmeg0AgetIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AgetIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smeg0AgetIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMEG0_AGET_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmeg0AgetIndrectData { + struct tagStSmeg0AgetIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0AgetIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic + will send these data to target.When operation read: Logic write data to + these registers and refresh xxx_indir_stat, software will get these data from + target. + */ +#else + unsigned int smeg0AgetIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic + will send these data to target.When operation read: Logic write data to + these registers and refresh xxx_indir_stat, software will get these data from + target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_AGET_INDRECT_DATA_U; + +/* ** + * Union name : SMEG_CORE_MEM_INIT + * @brief smeg core memory init done flag + * Description: + */ +typedef union tagUnSmegCoreMemInit { + struct tagStSmegCoreMemInit { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved. */ + unsigned int done : 1; /* * [0:0]1'b1: indicate memory init done;1'b0: memory init not done */ +#else + unsigned int done : 1; /* * [0:0]1'b1: indicate memory init done;1'b0: memory init not done */ + unsigned int reserved : 31; /* * [31:1]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG_CORE_MEM_INIT_U; + +/* ** + * Union name : SMEG0_CNT0 + * @brief SMEG0 Counter 0 + * Description: + */ +typedef union tagUnSmeg0Cnt0 { + struct tagStSmeg0Cnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0Cnt0 : 32; /* * [31:0]SMEG0 received request numbers;Used to Counter the numbers of received + * request numbers of smeg0 age table or smeg0 ALU module + */ +#else + unsigned int smeg0Cnt0 : 32; /* * [31:0]SMEG0 received request numbers;Used to Counter the numbers of received + * request numbers of smeg0 age table or smeg0 ALU module + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_CNT0_U; + +/* ** + * Union name : SMEG0_CNT1 + * @brief SMEG0 Counter 1 + * Description: + */ +typedef union tagUnSmeg0Cnt1 { + struct tagStSmeg0Cnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0Cnt1 : 32; /* * [31:0]SMEG0 returned grant numbers;Used to Counter the numbers of grant + * numbers of smeg0 age table or smeg0 ALU module + */ +#else + unsigned int smeg0Cnt1 : 32; /* * [31:0]SMEG0 returned grant numbers;Used to Counter the numbers of grant + * numbers of smeg0 age table or smeg0 ALU module + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_CNT1_U; + + +/* ** + * Union name : SMEG0_LU_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmeg0LuVersion { + struct tagStSmeg0LuVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smeg0LuVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_VERSION_U; + +/* ** + * Union name : SMEG0_LU_CHK_ENABLE_CFG + * @brief configuration register for memory check enbale + * Description: + */ +typedef union tagUnSmeg0LuChkEnableCfg { + struct tagStSmeg0LuChkEnableCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 8; /* * [31:24]reserved */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int reserved1 : 4; /* * [7:4]reserved */ + unsigned int pipe0MemChkEnable : 1; /* * [3:3]0:disable1:enable */ + unsigned int pipe1MemChkEnable : 1; /* * [2:2]0:disable1:enable */ + unsigned int flitFifoChkEnable : 1; /* * [1:1]0:disable1:enable */ + unsigned int reserved2 : 1; /* * [0:0]reserved */ +#else + unsigned int reserved2 : 1; /* * [0:0]reserved */ + unsigned int flitFifoChkEnable : 1; /* * [1:1]0:disable1:enable */ + unsigned int pipe1MemChkEnable : 1; /* * [2:2]0:disable1:enable */ + unsigned int pipe0MemChkEnable : 1; /* * [3:3]0:disable1:enable */ + unsigned int reserved1 : 4; /* * [7:4]reserved */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int reserved0 : 8; /* * [31:24]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CHK_ENABLE_CFG_U; + +/* ** + * Union name : SMEG0_LU_INT_VECTOR + * @brief interrupt vector + * Description: + */ +typedef union tagUnSmeg0LuIntVector { + struct tagStSmeg0LuIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INT_VECTOR_U; + +/* ** + * Union name : SMEG0_LU_INT + * @brief interrupt data + * Description: + */ +typedef union tagUnSmeg0LuInt { + struct tagStSmeg0LuInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int intData : 7; /* * [6:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 7; /* * [6:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INT_U; + +/* ** + * Union name : SMEG0_LU_INT_MASK + * @brief interrupt mask + * Description: + */ +typedef union tagUnSmeg0LuIntMask { + struct tagStSmeg0LuIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INT_MASK_U; + +/* ** + * Union name : SMEG0_LU_PIPE0_MEM_ECC_CRT_ERR + * @brief SMEG0_LOOKUP_PIPE0MEM ECC 1bit error + * Description: + */ +typedef union tagUnSmeg0LuPipe0MemEccCrtErr { + struct tagStSmeg0LuPipe0MemEccCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:7]: reserved[6:0] pipe0_mem index of ecc error + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:7]: reserved[6:0] pipe0_mem index of ecc error + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR + * @brief SMEG0_LOOKUP_PIPE0MEM ECC multi-bit error + * Description: + */ +typedef union tagUnSmeg0LuPipe0MemEccUncrtErr { + struct tagStSmeg0LuPipe0MemEccUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:7]: reserved[6:0] pipe0_mem index of ecc error + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:7]: reserved[6:0] pipe0_mem index of ecc error + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_PIPE1_MEM_ECC_CRT_ERR + * @brief SMEG0_LOOKUP_PIPE1MEM ECC 1bit error + * Description: + */ +typedef union tagUnSmeg0LuPipe1MemEccCrtErr { + struct tagStSmeg0LuPipe1MemEccCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:9]: reserved[8:0] pipe0_mem index of ecc error + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:9]: reserved[8:0] pipe0_mem index of ecc error + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR + * @brief SMEG0_LOOKUP_PIPE1MEM ECC multi-bit error + * Description: + */ +typedef union tagUnSmeg0LuPipe1MemEccUncrtErr { + struct tagStSmeg0LuPipe1MemEccUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:9]: reserved[8:0] pipe0_mem index of ecc error + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + * [29:9]: reserved[8:0] pipe0_mem index of ecc error + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR + * @brief SMEG0_LU_FLITFIFO 1bit error + * Description: + */ +typedef union tagUnSmeg0LuFlitfifoMemEccCrtErr { + struct tagStSmeg0LuFlitfifoMemEccCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error + flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]: + ctrl_fifo mem check error flagIn flit,each 32bit generates a even parity error bit,i f + anyone happen parity error,will be triggered a flit error flag.15 bit ctrl_info generate a + even parity error flag. Any error flag will be triggered this inter rupt. */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error + flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]: + ctrl_fifo mem check error flagIn flit,each 32bit generates a even parity error bit,i f + anyone happen parity error,will be triggered a flit error flag.15 bit ctrl_info generate a + even parity error flag. Any error flag will be triggered this inter rupt. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR + * @brief SMEG0_LU_FLITFIFO multi-bit error + * Description: + */ +typedef union tagUnSmeg0LuFlitfifoMemEccUncrtErr { + struct tagStSmeg0LuFlitfifoMemEccUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error + flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]: + reservedIn flit,each 32bit generates a even parity error bit,if anyone happen parity + error,will be triggered a flit error flag.15 bit ctrl_info generate a even parity error + flag. Any error flag will be triggered this interrupt. + */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + off.[29:8]: reserved[7:4]: flit_fifo index of parity error[3]: flit2_fifo mem check error + flag[ 2]: flit1_fifo mem check error flag[1]: flit0_fifo mem check error flag[0]: + reservedIn flit,each 32bit generates a even parity error bit,if anyone happen parity + error,will be triggered a flit error flag.15 bit ctrl_info generate a even parity error + flag. Any error flag will be triggered this interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_U; + +/* ** + * Union name : SMEG0_LU_SW_ERR + * @brief BTREE engine detected software fatal error + * Description: + */ +typedef union tagUnSmeg0LuSwErr { + struct tagStSmeg0LuSwErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + [31:8]:engine result 29:6 bits.[7]: API length error;[6]: SW err[5:2]: SW error cause(Plea + se refer to SEMG0_lookup uArch spec) */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int err : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErr : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off. + [31:8]:engine result 29:6 bits.[7]: API length error;[6]: SW err[5:2]: SW error cause(Plea + se refer to SEMG0_lookup uArch spec) */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_SW_ERR_U; + +/* ** + * Union name : SMEG0_LU_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmeg0LuIndrectCtrl { + struct tagStSmeg0LuIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ + unsigned int smeg0LuIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0LuIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0LuIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:pipe0 memory 0x1:pipe1 + * memory others:reserved + */ + unsigned int smeg0LuIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory + address in one group or internal address of the table.index [12:4]: pipe1_mem + index for 390 entriesin dex [10:4]: pipe0_mem index for 118 entriesindex [3:0]: + offset of one entry0x0-0x6: reserved, no mapping0x7: data[287:256]0x8: + data[255:224]0x9: data[223:192]0x a: data[191:160]0xb: data[159:128]0xc: + data[127:96]0xd: data[95:64]0xe: data[63:32]0xf: data[31:0] + */ +#else + unsigned int smeg0LuIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory + address in one group or internal address of the table.index [12:4]: pipe1_mem + index for 390 entriesin dex [10:4]: pipe0_mem index for 118 entriesindex [3:0]: + offset of one entry0x0-0x6: reserved, no mapping0x7: data[287:256]0x8: + data[255:224]0x9: data[223:192]0x a: data[191:160]0xb: data[159:128]0xc: + data[127:96]0xd: data[95:64]0xe: data[63:32]0xf: data[31:0] + */ + unsigned int smeg0LuIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:pipe0 memory 0x1:pipe1 + * memory others:reserved + */ + unsigned int smeg0LuIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg0LuIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. + */ + unsigned int smeg0LuIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic + clear);1’b1: indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INDRECT_CTRL_U; + +/* ** + * Union name : SMEG0_LU_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmeg0LuIndrectTimeout { + struct tagStSmeg0LuIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smeg0LuIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMEG0_LU_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmeg0LuIndrectData { + struct tagStSmeg0LuIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic + will send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smeg0LuIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic + will send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_INDRECT_DATA_U; + +/* ** +* Union name : SMEG0_LU_ERR_INJ_CFG +* @brief configuration register for error injection of FIFO memories. FIFO doesn't support CSR access. +Software can set error inject enable bit to test error handling. + +* Description: +*/ +typedef union tagUnSmeg0LuErrInjCfg { + struct tagStSmeg0LuErrInjCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6]reserved */ + unsigned int flitfUncrtErrInjReq : 1; /* * [5:5]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int flitfCrtErrInjReq : 1; /* * [4:4]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int pipe1UncrtErrInjReq : 1; /* * [3:3]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int pipe1CrtErrInjReq : 1; /* * [2:2]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int pipe0UncrtErrInjReq : 1; /* * [1:1]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int pipe0CrtErrInjReq : 1; /* * [0:0]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ +#else + unsigned int pipe0CrtErrInjReq : 1; /* * [0:0]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int pipe0UncrtErrInjReq : 1; /* * [1:1]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int pipe1CrtErrInjReq : 1; /* * [2:2]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int pipe1UncrtErrInjReq : 1; /* * [3:3]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int flitfCrtErrInjReq : 1; /* * [4:4]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int flitfUncrtErrInjReq : 1; /* * [5:5]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int reserved : 26; /* * [31:6]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_ERR_INJ_CFG_U; + +/* ** + * Union name : SMEG0_LU_CNT_CFG + * @brief counter related configuration register + * Description: + */ +typedef union tagUnSmeg0LuCntCfg { + struct tagStSmeg0LuCntCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11]reserved */ + unsigned int engEventGrp : 3; /* * [10:8]engine enent group select;3'h0 : sel group 0 event to count;3'h1 : sel + group 1 event to count;3'h2 : sel group 2 event to count;3'h3 : sel group 3 event to + coun t;3'h4 : sel all group event to count;others: reserved */ + unsigned int cnt3EventSel : 1; /* * [7:7]0: engine_event[3];1: outgoing_msg */ + unsigned int cnt2EventSel : 1; /* * [6:6]0: engine_event[2]; 1: outgoing_flit */ + unsigned int cnt1EventSel : 1; /* * [5:5]0: engine_event[1];1: incoming msg */ + unsigned int cnt0EventSel : 1; /* * [4:4]0: engine_event[0];1: incoming flit. */ + unsigned int cntEnable : 4; /* * [3:0]each bit is mapping to one counter.setting 1 means enable, seeting 0 means + disable4'bxxx1: SMEG0_LU_CNT0_ENABLE4'bxx1x: SMEG0_LU_CNT1_ENABLE4'bx1xx: SMEG0_LU_CN + T2_ENABLE4'b1xxx: SMEG0_LU_CNT3_ENABLE */ +#else + unsigned int cntEnable : 4; /* * [3:0]each bit is mapping to one counter.setting 1 means enable, seeting 0 means + disable4'bxxx1: SMEG0_LU_CNT0_ENABLE4'bxx1x: SMEG0_LU_CNT1_ENABLE4'bx1xx: SMEG0_LU_CN + T2_ENABLE4'b1xxx: SMEG0_LU_CNT3_ENABLE */ + unsigned int cnt0EventSel : 1; /* * [4:4]0: engine_event[0];1: incoming flit. */ + unsigned int cnt1EventSel : 1; /* * [5:5]0: engine_event[1];1: incoming msg */ + unsigned int cnt2EventSel : 1; /* * [6:6]0: engine_event[2]; 1: outgoing_flit */ + unsigned int cnt3EventSel : 1; /* * [7:7]0: engine_event[3];1: outgoing_msg */ + unsigned int engEventGrp : 3; /* * [10:8]engine enent group select;3'h0 : sel group 0 event to count;3'h1 : sel + group 1 event to count;3'h2 : sel group 2 event to count;3'h3 : sel group 3 event to + coun t;3'h4 : sel all group event to count;others: reserved */ + unsigned int reserved : 21; /* * [31:11]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CNT_CFG_U; + +/* ** + * Union name : SMEG0_LU_CNT0 + * @brief counter0 + * Description: + */ +typedef union tagUnSmeg0LuCnt0 { + struct tagStSmeg0LuCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuCnt0 : 32; /* * [31:0] */ +#else + unsigned int smeg0LuCnt0 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CNT0_U; + +/* ** + * Union name : SMEG0_LU_CNT1 + * @brief counter1 + * Description: + */ +typedef union tagUnSmeg0LuCnt1 { + struct tagStSmeg0LuCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuCnt1 : 32; /* * [31:0] */ +#else + unsigned int smeg0LuCnt1 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CNT1_U; + +/* ** + * Union name : SMEG0_LU_CNT2 + * @brief counter2 + * Description: + */ +typedef union tagUnSmeg0LuCnt2 { + struct tagStSmeg0LuCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuCnt2 : 32; /* * [31:0] */ +#else + unsigned int smeg0LuCnt2 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CNT2_U; + +/* ** + * Union name : SMEG0_LU_CNT3 + * @brief counter3 + * Description: + */ +typedef union tagUnSmeg0LuCnt3 { + struct tagStSmeg0LuCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg0LuCnt3 : 32; /* * [31:0] */ +#else + unsigned int smeg0LuCnt3 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CNT3_U; + +/* ** + * Union name : SMEG0_LU_CTP + * @brief SMEG0 Profile Register for performance monitor. + * Description: + */ +typedef union tagUnSmeg0LuCtp { + struct tagStSmeg0LuCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10]reserved */ + unsigned int numInOriginalFifo : 5; /* * [9:5]number of APIs in original_fifo. */ + unsigned int numInResultFifo : 5; /* * [4:0]number of commands in result_fifo. Those commands are completed in + * smeg0, and waits for forwarding to smeg1 + */ +#else + unsigned int numInResultFifo : 5; /* * [4:0]number of commands in result_fifo. Those commands are completed in + * smeg0, and waits for forwarding to smeg1 + */ + unsigned int numInOriginalFifo : 5; /* * [9:5]number of APIs in original_fifo. */ + unsigned int reserved : 22; /* * [31:10]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG0_LU_CTP_U; + + +/* ** + * Union name : SMEG1_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmeg1Version { + struct tagStSmeg1Version { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1Version : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smeg1Version : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_VERSION_U; + +/* ** +* Union name : SMEG1_CFG0 +* @brief Smart Memory Infra Engine Group1 (SMEG1) configuration register . This is used to configure +additional features, and for debug. + +* Description: +*/ +typedef union tagUnSmeg1Cfg0 { + struct tagStSmeg1Cfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int rpHaltThreadMaxNum : 6; /* * [31:26]maximus halted threads number, 0 - halt 1 thread at most;1 - + halt 2 thread at most;……;N - halt N+1 thread at most;Notes: Make sure N < 16 + in SML and N < 32 in S MF; */ + unsigned int btInstId : 6; /* * [25:20]Btree instance ID, all btree API use the same instance ID to access + memory, including Btree node/LT/AGE table; The base address of these table should be + configu re use this instance ID, not instance ID from API */ + unsigned int rpInlldLlIvldEn : 1; /* * [19:19]Configure for MISC_F engine RDMA inline load API. last cache line + cache invalid enable control:1'b1 - send cache invalid command for the last cache + line access by the current API;1'b0 - only when all the data of the last cache + line is load to cpi, send cache invalid command for the cache line, else dont + send cache inva lid command for the last cache line */ + unsigned int memChkEn : 1; /* * [18:18]memory check enable.1'b0:disable all memories err check.1'b1:enable all + * memories err check. + */ + unsigned int msbThreadCfg : 1; /* * [17:17]0:msb thread is used as special thread only used in response + channel;1:msb thread is used as normal thread only used in request channel;*NOTE: + This bit and smir .smir_cfg.msb_thread_cfg should be configure the same value */ + unsigned int tcdThdId : 6; /* * [16:11]which thread's tcd map to tcd ctp */ + unsigned int haltOnRunawayErr : 1; /* * [10:10]halt thread on runaway error 1: halt the thread in smeg1 0: + no halt */ + unsigned int ctpActiveBits : 1; /* * [9:9]1: runaway ctp transmits thread active bits 0: runaway ctp transmits + * runaway threads + */ + unsigned int haltSwErr1 : 1; /* * [8:8]halt thread on software error1. 1: halt the thread in smeg1 when + engine detected sw_err1;Send message for the thread and SR if LL is issued ever. 0: no + h alt, no SEND/SR operation; */ + unsigned int haltOnEbit : 1; /* * [7:7]halt thread on ebit with load return, store return,get put return or + * wakeup. 1: halt the thread in smeg1 0: no halt + */ + unsigned int haltSwErr : 1; /* * [6:6]halt thread on software error. 1: halt the thread in smeg1 0: + * no halt + */ + unsigned int prememCount : 4; /* * [5:2]This is the number of allowed preload or prestore operations before + * issuing a thread from the install issue queue + */ + unsigned int preloadFairness : 1; /* * [1:1]1: turn on preload fairness0: do not use preload fairness */ + unsigned int detectRunawayThread : 1; /* * [0:0]1: detect runaway thread 0: do not detect any runaway + * thread.Attention:before turn on this bit, should configure + * smeg1_runaway_cfg first. + */ +#else + unsigned int detectRunawayThread : 1; /* * [0:0]1: detect runaway thread 0: do not detect any runaway + * thread.Attention:before turn on this bit, should configure + * smeg1_runaway_cfg first. + */ + unsigned int preloadFairness : 1; /* * [1:1]1: turn on preload fairness0: do not use preload fairness */ + unsigned int prememCount : 4; /* * [5:2]This is the number of allowed preload or prestore operations before + * issuing a thread from the install issue queue + */ + unsigned int haltSwErr : 1; /* * [6:6]halt thread on software error. 1: halt the thread in smeg1 0: + * no halt + */ + unsigned int haltOnEbit : 1; /* * [7:7]halt thread on ebit with load return, store return,get put return or + * wakeup. 1: halt the thread in smeg1 0: no halt + */ + unsigned int haltSwErr1 : 1; /* * [8:8]halt thread on software error1. 1: halt the thread in smeg1 when + engine detected sw_err1;Send message for the thread and SR if LL is issued ever. 0: no + h alt, no SEND/SR operation; */ + unsigned int ctpActiveBits : 1; /* * [9:9]1: runaway ctp transmits thread active bits 0: runaway ctp transmits + * runaway threads + */ + unsigned int haltOnRunawayErr : 1; /* * [10:10]halt thread on runaway error 1: halt the thread in smeg1 0: + no halt */ + unsigned int tcdThdId : 6; /* * [16:11]which thread's tcd map to tcd ctp */ + unsigned int msbThreadCfg : 1; /* * [17:17]0:msb thread is used as special thread only used in response + channel;1:msb thread is used as normal thread only used in request channel;*NOTE: + This bit and smir .smir_cfg.msb_thread_cfg should be configure the same value */ + unsigned int memChkEn : 1; /* * [18:18]memory check enable.1'b0:disable all memories err check.1'b1:enable all + * memories err check. + */ + unsigned int rpInlldLlIvldEn : 1; /* * [19:19]Configure for MISC_F engine RDMA inline load API. last cache line + cache invalid enable control:1'b1 - send cache invalid command for the last cache + line access by the current API;1'b0 - only when all the data of the last cache + line is load to cpi, send cache invalid command for the cache line, else dont + send cache inva lid command for the last cache line */ + unsigned int btInstId : 6; /* * [25:20]Btree instance ID, all btree API use the same instance ID to access + memory, including Btree node/LT/AGE table; The base address of these table should be + configu re use this instance ID, not instance ID from API */ + unsigned int rpHaltThreadMaxNum : 6; /* * [31:26]maximus halted threads number, 0 - halt 1 thread at most;1 - + halt 2 thread at most;……;N - halt N+1 thread at most;Notes: Make sure N < 16 + in SML and N < 32 in S MF; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_CFG0_U; + +/* ** + * Union name : SMEG1_CFG1 + * @brief Smart Memory Infra Engine Group1 (SMEG1) configuration register . + * Description: + */ +typedef union tagUnSmeg1Cfg1 { + struct tagStSmeg1Cfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20]Software can use this register to do memory power and timing configure; + */ + unsigned int fidrUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int fidrCrtErrInjReq : 1; /* * [18:18]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int rpUncrtErrInjReq : 1; /* * [17:17]as same as fidr_uncrt_err_inj_req; only for the ECC protected + * memory in SMEG1 excepted FIDR + */ + unsigned int rpCrtErrInjReq : 1; /* * [16:16]as same as fidr_crt_err_inj_req; only for the ECC protected memory + * in SMEG1 excepted FIDR + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int tpRamTmod : 8; /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ +#else + unsigned int tpRamTmod : 8; /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int rpCrtErrInjReq : 1; /* * [16:16]as same as fidr_crt_err_inj_req; only for the ECC protected memory + * in SMEG1 excepted FIDR + */ + unsigned int rpUncrtErrInjReq : 1; /* * [17:17]as same as fidr_uncrt_err_inj_req; only for the ECC protected + * memory in SMEG1 excepted FIDR + */ + unsigned int fidrCrtErrInjReq : 1; /* * [18:18]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a + memory read is issu ed to the memory.Enable memory check, when use this err + inection function. */ + unsigned int fidrUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected + when a memory read is is sued to the memory. Enable memory check, when use + this err inection function. */ + unsigned int reserved : 12; /* * [31:20]Software can use this register to do memory power and timing configure; + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_CFG1_U; + +/* ** +* Union name : SMEG1_RUNAWAY_CFG +* @brief Smart Memory Infra Engine Group1 (SMEG1) Runaway sampling count configuration register. In the +normal operation, this can be used as a watch dog timer for 16 or 64 threads in a smart memory tile. +* Description: +*/ +typedef union tagUnSmeg1RunawayCfg { + struct tagStSmeg1RunawayCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1RunawayCfg : 32; /* * [31:0]The value programmed in this register is used to measure the life + span of an active thread. The maximum value of this watch dog timer is 4s. Once a + thread is ca ught as a runaway, the kill pending bit in the scoreboard is + asserted and the thread is prohibited from reissuing until software clears the + bit.*NOTE: 1. If you want to change the default runaway time, please close the + runaway detect function, update the ruaway time, then re-open the runaway + detected operation.2. the D efault value is 200ms @1GHz clock */ +#else + unsigned int smeg1RunawayCfg : 32; /* * [31:0]The value programmed in this register is used to measure the life + span of an active thread. The maximum value of this watch dog timer is 4s. Once a + thread is ca ught as a runaway, the kill pending bit in the scoreboard is + asserted and the thread is prohibited from reissuing until software clears the + bit.*NOTE: 1. If you want to change the default runaway time, please close the + runaway detect function, update the ruaway time, then re-open the runaway + detected operation.2. the D efault value is 200ms @1GHz clock */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_RUNAWAY_CFG_U; + +/* ** + * Union name : SMEG1_THREAD_ENABLE_CFG + * @brief Thread enable configure; bitmap for 16/32 thread in smeg1 + * Description: + */ +typedef union tagUnSmeg1ThreadEnableCfg { + struct tagStSmeg1ThreadEnableCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1ThreadEnableCfg : 32; /* * [31:0]thread disable configure; bitmap for 16/32 thread in smeg1; + bit0 is for thread0, bit1 is for thread 1, and so on; (bit31:16 is reserved + in SML)1'b1: thread is e nable1'b0: thread is disable, this thread will be + not allocated;*NOTE: if msb_thread_cfg is configured to allocate the MSB + thread to response channel, then the MSB (bit15 in SML/bit31 in SMF) of this + field should be enable*NOTE: not configure all 0's to this field.(when MSB + is allocated to response channel, not configu + re all 0's to the other valid fields) */ +#else + unsigned int smeg1ThreadEnableCfg : 32; /* * [31:0]thread disable configure; bitmap for 16/32 thread in smeg1; + bit0 is for thread0, bit1 is for thread 1, and so on; (bit31:16 is reserved + in SML)1'b1: thread is e nable1'b0: thread is disable, this thread will be + not allocated;*NOTE: if msb_thread_cfg is configured to allocate the MSB + thread to response channel, then the MSB (bit15 in SML/bit31 in SMF) of this + field should be enable*NOTE: not configure all 0's to this field.(when MSB + is allocated to response channel, not configu + re all 0's to the other valid fields) */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_THREAD_ENABLE_CFG_U; + +/* ** + * Union name : SMEG1_TM_TS_FAST2 + * @brief timer wheel control info + * Description: + */ +typedef union tagUnSmeg1TmTsFast2 { + struct tagStSmeg1TmTsFast2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTsFast2 : 32; /* * [31:0]This register Includes fast timer wheel 0~3, {Timer wheel 0, Timer + wheel 1,Timer wheel 2, Timer wheel 3}One timer wheel's info:bit[7] :Valid, + Indicate this timi ng wheel is validbit[6:5] Spoke Mode, 00: 256 spokes 01: + 512 spokes 10: 1024 spokes 11: 2048 spokes bit[4:0] Spoke Tick Scale, + Indicate s how many ticks this timing wheel’s spoke takes, one tick time is equal + to based unit tick time, 1us.one spoke tick = 2^spoke tick scale + */ +#else + unsigned int smeg1TmTsFast2 : 32; /* * [31:0]This register Includes fast timer wheel 0~3, {Timer wheel 0, Timer + wheel 1,Timer wheel 2, Timer wheel 3}One timer wheel's info:bit[7] :Valid, + Indicate this timi ng wheel is validbit[6:5] Spoke Mode, 00: 256 spokes 01: + 512 spokes 10: 1024 spokes 11: 2048 spokes bit[4:0] Spoke Tick Scale, + Indicate s how many ticks this timing wheel’s spoke takes, one tick time is equal + to based unit tick time, 1us.one spoke tick = 2^spoke tick scale + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TS_FAST2_U; + +/* ** + * Union name : SMEG1_TM_TS_FAST3 + * @brief TIMER engine wheel control info + * Description: + */ +typedef union tagUnSmeg1TmTsFast3 { + struct tagStSmeg1TmTsFast3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTsFast3 : 32; /* * [31:0]This register Includes slow timer wheel 4~5, {Timer wheel 4, Timer + * wheel 5,Reserved 16 bit}timer wheel info data structure is same with fast + * timer wheel info. + */ +#else + unsigned int smeg1TmTsFast3 : 32; /* * [31:0]This register Includes slow timer wheel 4~5, {Timer wheel 4, Timer + * wheel 5,Reserved 16 bit}timer wheel info data structure is same with fast + * timer wheel info. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TS_FAST3_U; + +/* ** + * Union name : SMEG1_TM_TS_SLOW0 + * @brief TIMER engine control info + * Description: + */ +typedef union tagUnSmeg1TmTsSlow0 { + struct tagStSmeg1TmTsSlow0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTsSlow0 : 32; /* * [31:0][31:2]: reserved[1]: indicate core clock's frequency0: 900MHz1: + 600MHz[0]: CAR engine use type of timestamp. If chip support DFS, select global + timestamp.0: use local timestamp1: use global timestamp */ +#else + unsigned int smeg1TmTsSlow0 : 32; /* * [31:0][31:2]: reserved[1]: indicate core clock's frequency0: 900MHz1: + 600MHz[0]: CAR engine use type of timestamp. If chip support DFS, select global + timestamp.0: use local timestamp1: use global timestamp */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TS_SLOW0_U; + +/* ** + * Union name : SMEG1_TM_TS_SLOW1 + * @brief TIMER engine control info + * Description: + */ +typedef union tagUnSmeg1TmTsSlow1 { + struct tagStSmeg1TmTsSlow1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTsSlow1 : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual + entry size and cache line size.value indcates:00: actual size/cache line szie = + 1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11: + actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 15Bit [29:28]: entry + 14Bit [27: 26]: entry 13Bit [25:24]: entry 12Bit [23:22]: entry 11Bit [21:20]: + entry 10Bit [19:18]: entry 9Bit [17:16]: entry 8Bit [15:14]: entry 7Bit [13:12]: + entry 6Bit [11:10]: entry 5Bit [9:8] : entry 4Bit [7:6] : entry 3Bit [5:4] : + entry 2Bit [3:2] : entry 1Bit [1:0] : entry 0 + */ +#else + unsigned int smeg1TmTsSlow1 : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual + entry size and cache line size.value indcates:00: actual size/cache line szie = + 1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11: + actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 15Bit [29:28]: entry + 14Bit [27: 26]: entry 13Bit [25:24]: entry 12Bit [23:22]: entry 11Bit [21:20]: + entry 10Bit [19:18]: entry 9Bit [17:16]: entry 8Bit [15:14]: entry 7Bit [13:12]: + entry 6Bit [11:10]: entry 5Bit [9:8] : entry 4Bit [7:6] : entry 3Bit [5:4] : + entry 2Bit [3:2] : entry 1Bit [1:0] : entry 0 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TS_SLOW1_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG7 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg7 { + struct tagStSmeg1TmTmtCfg7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt31 : 8; /* * [31:24]timer engine memory type config for APIs whose service type is + 31:bit[7]: valid flag, 1: valid; 0: invalid;bit[6:4] Vcache index: + Virtual cache Ind ex for context in FIARbit[3:0] Tag_type,Memory Tag Type, which is + used to access context, and definitions are referred in stateful SM FS. + */ + unsigned int smeg1TmTmt30 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 30 + */ + unsigned int smeg1TmTmt29 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 29 + */ + unsigned int smeg1TmTmt28 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 28 + */ +#else + unsigned int smeg1TmTmt28 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 28 + */ + unsigned int smeg1TmTmt29 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 29 + */ + unsigned int smeg1TmTmt30 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 30 + */ + unsigned int smeg1TmTmt31 : 8; /* * [31:24]timer engine memory type config for APIs whose service type is + 31:bit[7]: valid flag, 1: valid; 0: invalid;bit[6:4] Vcache index: + Virtual cache Ind ex for context in FIARbit[3:0] Tag_type,Memory Tag Type, which is + used to access context, and definitions are referred in stateful SM FS. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG7_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG6 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg6 { + struct tagStSmeg1TmTmtCfg6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt27 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 27 + */ + unsigned int smeg1TmTmt26 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 26 + */ + unsigned int smeg1TmTmt25 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 25 + */ + unsigned int smeg1TmTmt24 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 24 + */ +#else + unsigned int smeg1TmTmt24 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 24 + */ + unsigned int smeg1TmTmt25 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 25 + */ + unsigned int smeg1TmTmt26 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 26 + */ + unsigned int smeg1TmTmt27 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 27 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG6_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG5 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg5 { + struct tagStSmeg1TmTmtCfg5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt23 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 23 + */ + unsigned int smeg1TmTmt22 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 22 + */ + unsigned int smeg1TmTmt21 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 21 + */ + unsigned int smeg1TmTmt20 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 20 + */ +#else + unsigned int smeg1TmTmt20 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 20 + */ + unsigned int smeg1TmTmt21 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 21 + */ + unsigned int smeg1TmTmt22 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 22 + */ + unsigned int smeg1TmTmt23 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 23 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG5_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG4 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg4 { + struct tagStSmeg1TmTmtCfg4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt19 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 19 + */ + unsigned int smeg1TmTmt18 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 18 + */ + unsigned int smeg1TmTmt17 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 17 + */ + unsigned int smeg1TmTmt16 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 16 + */ +#else + unsigned int smeg1TmTmt16 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 16 + */ + unsigned int smeg1TmTmt17 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 17 + */ + unsigned int smeg1TmTmt18 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 18 + */ + unsigned int smeg1TmTmt19 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 19 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG4_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG3 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg3 { + struct tagStSmeg1TmTmtCfg3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt15 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 15 + */ + unsigned int smeg1TmTmt14 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 14 + */ + unsigned int smeg1TmTmt13 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 13 + */ + unsigned int smeg1TmTmt12 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 12 + */ +#else + unsigned int smeg1TmTmt12 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 12 + */ + unsigned int smeg1TmTmt13 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 13 + */ + unsigned int smeg1TmTmt14 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 14 + */ + unsigned int smeg1TmTmt15 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 15 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG3_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG2 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg2 { + struct tagStSmeg1TmTmtCfg2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt11 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 11 + */ + unsigned int smeg1TmTmt10 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 10 + */ + unsigned int smeg1TmTmt9 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 9 + */ + unsigned int smeg1TmTmt8 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 8 + */ +#else + unsigned int smeg1TmTmt8 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 8 + */ + unsigned int smeg1TmTmt9 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 9 + */ + unsigned int smeg1TmTmt10 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 10 + */ + unsigned int smeg1TmTmt11 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 11 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG2_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG1 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg1 { + struct tagStSmeg1TmTmtCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt7 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 7 + */ + unsigned int smeg1TmTmt6 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 6 + */ + unsigned int smeg1TmTmt5 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 5 + */ + unsigned int smeg1TmTmt4 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 4 + */ +#else + unsigned int smeg1TmTmt4 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 4 + */ + unsigned int smeg1TmTmt5 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 5 + */ + unsigned int smeg1TmTmt6 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 6 + */ + unsigned int smeg1TmTmt7 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 7 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG1_U; + +/* ** + * Union name : SMEG1_TM_TMT_CFG0 + * @brief TIMER engine type cfg + * Description: + */ +typedef union tagUnSmeg1TmTmtCfg0 { + struct tagStSmeg1TmTmtCfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmTmt3 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 3 + */ + unsigned int smeg1TmTmt2 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 2 + */ + unsigned int smeg1TmTmt1 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 1 + */ + unsigned int smeg1TmTmt0 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 0 + */ +#else + unsigned int smeg1TmTmt0 : 8; /* * [7:0]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 0 + */ + unsigned int smeg1TmTmt1 : 8; /* * [15:8]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 1 + */ + unsigned int smeg1TmTmt2 : 8; /* * [23:16]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 2 + */ + unsigned int smeg1TmTmt3 : 8; /* * [31:24]Fields define is as same as smeg1_tm_tmt31;And this is for APIs whose + * service type is 3 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TM_TMT_CFG0_U; + +/* ** + * Union name : SMEG1_INT_VECTOR + * @brief + * Description: + */ +typedef union tagUnSmeg1IntVector { + struct tagStSmeg1IntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes + * 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes + * 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INT_VECTOR_U; + +/* ** + * Union name : SMEG1_INT + * @brief + * Description: + */ +typedef union tagUnSmeg1Int { + struct tagStSmeg1Int { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3] */ + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 13; /* * [15:3] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INT_U; + +/* ** + * Union name : SMEG1_INT_MASK + * @brief + * Description: + */ +typedef union tagUnSmeg1IntMask { + struct tagStSmeg1IntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3] */ + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 13; /* * [15:3] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INT_MASK_U; + +/* ** +* Union name : SMEG1_ENGINE_SW_ERR +* @brief This is Smart Memory Infra Engine Group1 (SMEG1) engine software error log register. + +* Description: +*/ +typedef union tagUnSmeg1EngineSwErr { + struct tagStSmeg1EngineSwErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off It + logs thread id, opcode of the failed API and instance id.Bi t[31]:sw_err1 is + detectedBit[30]:sw_err0 is detectedBit[29:26]:sw error codeBit[25:20]:RSVBit[19:14]:thread + id.Bit[13:8]:opcode.Bit[7:2]:instance id. + */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is off It + logs thread id, opcode of the failed API and instance id.Bi t[31]:sw_err1 is + detectedBit[30]:sw_err0 is detectedBit[29:26]:sw error codeBit[25:20]:RSVBit[19:14]:thread + id.Bit[13:8]:opcode.Bit[7:2]:instance id. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_ENGINE_SW_ERR_U; + +/* ** + * Union name : SMEG1_ERR0 + * @brief error register 0 + * Description: + */ +typedef union tagUnSmeg1Err0 { + struct tagStSmeg1Err0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 14; /* * [31:18]reserved. */ + unsigned int runawayMerr : 1; /* * [17:17] */ + unsigned int runawayErr : 1; /* * [16:16]runaway error */ + unsigned int eccCrtMerr7 : 1; /* * [15:15] */ + unsigned int eccCrtErr7 : 1; /* * [14:14]ecc correctable error is detected on memory ARR */ + unsigned int eccCrtMerr6 : 1; /* * [13:13] */ + unsigned int eccCrtErr6 : 1; /* * [12:12]ecc correctable error is detected on memory tdr */ + unsigned int eccCrtMerr5 : 1; /* * [11:11] */ + unsigned int eccCrtErr5 : 1; /* * [10:10]ecc correctable error is detected on memory etr1 */ + unsigned int eccCrtMerr4 : 1; /* * [9:9] */ + unsigned int eccCrtErr4 : 1; /* * [8:8]ecc correctable error is detected on memory etr0 */ + unsigned int eccCrtMerr3 : 1; /* * [7:7] */ + unsigned int eccCrtErr3 : 1; /* * [6:6]ecc correctable error is detected on memory esr */ + unsigned int eccCrtMerr2 : 1; /* * [5:5] */ + unsigned int eccCrtErr2 : 1; /* * [4:4]ecc correctable error is detected on memory fidr */ + unsigned int eccCrtMerr1 : 1; /* * [3:3] */ + unsigned int eccCrtErr1 : 1; /* * [2:2]ecc correctable error is detected on memory gpr1 */ + unsigned int eccCrtMerr0 : 1; /* * [1:1] */ + unsigned int eccCrtErr0 : 1; /* * [0:0]ecc correctable error is detected on memory gpr0 */ +#else + unsigned int eccCrtErr0 : 1; /* * [0:0]ecc correctable error is detected on memory gpr0 */ + unsigned int eccCrtMerr0 : 1; /* * [1:1] */ + unsigned int eccCrtErr1 : 1; /* * [2:2]ecc correctable error is detected on memory gpr1 */ + unsigned int eccCrtMerr1 : 1; /* * [3:3] */ + unsigned int eccCrtErr2 : 1; /* * [4:4]ecc correctable error is detected on memory fidr */ + unsigned int eccCrtMerr2 : 1; /* * [5:5] */ + unsigned int eccCrtErr3 : 1; /* * [6:6]ecc correctable error is detected on memory esr */ + unsigned int eccCrtMerr3 : 1; /* * [7:7] */ + unsigned int eccCrtErr4 : 1; /* * [8:8]ecc correctable error is detected on memory etr0 */ + unsigned int eccCrtMerr4 : 1; /* * [9:9] */ + unsigned int eccCrtErr5 : 1; /* * [10:10]ecc correctable error is detected on memory etr1 */ + unsigned int eccCrtMerr5 : 1; /* * [11:11] */ + unsigned int eccCrtErr6 : 1; /* * [12:12]ecc correctable error is detected on memory tdr */ + unsigned int eccCrtMerr6 : 1; /* * [13:13] */ + unsigned int eccCrtErr7 : 1; /* * [14:14]ecc correctable error is detected on memory ARR */ + unsigned int eccCrtMerr7 : 1; /* * [15:15] */ + unsigned int runawayErr : 1; /* * [16:16]runaway error */ + unsigned int runawayMerr : 1; /* * [17:17] */ + unsigned int reserved : 14; /* * [31:18]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_ERR0_U; + +/* ** + * Union name : SMEG1_ERR0_MASK + * @brief error register 1 + * Description: + */ +typedef union tagUnSmeg1Err0Mask { + struct tagStSmeg1Err0Mask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9]reserved. */ + unsigned int runawayErrMask : 1; /* * [8:8]err mask of runaway error */ + unsigned int eccCrtErrMask7 : 1; /* * [7:7]err mask of ECC correctable error 7 */ + unsigned int eccCrtErrMask6 : 1; /* * [6:6]err mask of ECC correctable error 6 */ + unsigned int eccCrtErrMask5 : 1; /* * [5:5]err mask of ECC correctable error 5 */ + unsigned int eccCrtErrMask4 : 1; /* * [4:4]err mask of ECC correctable error 4 */ + unsigned int eccCrtErrMask3 : 1; /* * [3:3]err mask of ECC correctable error 3 */ + unsigned int eccCrtErrMask2 : 1; /* * [2:2]err mask of ECC correctable error 2 */ + unsigned int eccCrtErrMask1 : 1; /* * [1:1]err mask of ECC correctable error 1 */ + unsigned int eccCrtErrMask0 : 1; /* * [0:0]err mask of ECC correctable error 0 */ +#else + unsigned int eccCrtErrMask0 : 1; /* * [0:0]err mask of ECC correctable error 0 */ + unsigned int eccCrtErrMask1 : 1; /* * [1:1]err mask of ECC correctable error 1 */ + unsigned int eccCrtErrMask2 : 1; /* * [2:2]err mask of ECC correctable error 2 */ + unsigned int eccCrtErrMask3 : 1; /* * [3:3]err mask of ECC correctable error 3 */ + unsigned int eccCrtErrMask4 : 1; /* * [4:4]err mask of ECC correctable error 4 */ + unsigned int eccCrtErrMask5 : 1; /* * [5:5]err mask of ECC correctable error 5 */ + unsigned int eccCrtErrMask6 : 1; /* * [6:6]err mask of ECC correctable error 6 */ + unsigned int eccCrtErrMask7 : 1; /* * [7:7]err mask of ECC correctable error 7 */ + unsigned int runawayErrMask : 1; /* * [8:8]err mask of runaway error */ + unsigned int reserved : 23; /* * [31:9]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_ERR0_MASK_U; + +/* ** + * Union name : SMEG1_ERR1 + * @brief + * Description: + */ +typedef union tagUnSmeg1Err1 { + struct tagStSmeg1Err1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int eccUncrtMerr7 : 1; /* * [15:15] */ + unsigned int eccUncrtErr7 : 1; /* * [14:14]ECC uncorrectable error is detected on memory ARR */ + unsigned int eccUncrtMerr6 : 1; /* * [13:13] */ + unsigned int eccUncrtErr6 : 1; /* * [12:12]ECC uncorrectable error is detected on memory tdr */ + unsigned int eccUncrtMerr5 : 1; /* * [11:11] */ + unsigned int eccUncrtErr5 : 1; /* * [10:10]ECC uncorrectable error is detected on memory etr1 */ + unsigned int eccUncrtMerr4 : 1; /* * [9:9] */ + unsigned int eccUncrtErr4 : 1; /* * [8:8]ECC uncorrectable error is detected on memory etr0 */ + unsigned int eccUncrtMerr3 : 1; /* * [7:7] */ + unsigned int eccUncrtErr3 : 1; /* * [6:6]ECC uncorrectable error is detected on memory esr */ + unsigned int eccUncrtMerr2 : 1; /* * [5:5] */ + unsigned int eccUncrtErr2 : 1; /* * [4:4]ECC uncorrectable error is detected on memory fidr */ + unsigned int eccUncrtMerr1 : 1; /* * [3:3] */ + unsigned int eccUncrtErr1 : 1; /* * [2:2]ECC uncorrectable error is detected on memory gpr1 */ + unsigned int eccUncrtMerr0 : 1; /* * [1:1] */ + unsigned int eccUncrtErr0 : 1; /* * [0:0]ECC uncorrectable error is detected on memory gpr0 */ +#else + unsigned int eccUncrtErr0 : 1; /* * [0:0]ECC uncorrectable error is detected on memory gpr0 */ + unsigned int eccUncrtMerr0 : 1; /* * [1:1] */ + unsigned int eccUncrtErr1 : 1; /* * [2:2]ECC uncorrectable error is detected on memory gpr1 */ + unsigned int eccUncrtMerr1 : 1; /* * [3:3] */ + unsigned int eccUncrtErr2 : 1; /* * [4:4]ECC uncorrectable error is detected on memory fidr */ + unsigned int eccUncrtMerr2 : 1; /* * [5:5] */ + unsigned int eccUncrtErr3 : 1; /* * [6:6]ECC uncorrectable error is detected on memory esr */ + unsigned int eccUncrtMerr3 : 1; /* * [7:7] */ + unsigned int eccUncrtErr4 : 1; /* * [8:8]ECC uncorrectable error is detected on memory etr0 */ + unsigned int eccUncrtMerr4 : 1; /* * [9:9] */ + unsigned int eccUncrtErr5 : 1; /* * [10:10]ECC uncorrectable error is detected on memory etr1 */ + unsigned int eccUncrtMerr5 : 1; /* * [11:11] */ + unsigned int eccUncrtErr6 : 1; /* * [12:12]ECC uncorrectable error is detected on memory tdr */ + unsigned int eccUncrtMerr6 : 1; /* * [13:13] */ + unsigned int eccUncrtErr7 : 1; /* * [14:14]ECC uncorrectable error is detected on memory ARR */ + unsigned int eccUncrtMerr7 : 1; /* * [15:15] */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_ERR1_U; + +/* ** + * Union name : SMEG1_ERR1_MASK + * @brief + * Description: + */ +typedef union tagUnSmeg1Err1Mask { + struct tagStSmeg1Err1Mask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 24; /* * [31:8]reserved. */ + unsigned int eccUncrtErrMask7 : 1; /* * [7:7]err mask of ECC uncorrectable error 7 */ + unsigned int eccUncrtErrMask6 : 1; /* * [6:6]err mask of ECC uncorrectable error 6 */ + unsigned int eccUncrtErrMask5 : 1; /* * [5:5]err mask of ECC uncorrectable error 5 */ + unsigned int eccUncrtErrMask4 : 1; /* * [4:4]err mask of ECC uncorrectable error 4 */ + unsigned int eccUncrtErrMask3 : 1; /* * [3:3]err mask of ECC uncorrectable error 3 */ + unsigned int eccUncrtErrMask2 : 1; /* * [2:2]err mask of ECC uncorrectable error 2 */ + unsigned int eccUncrtErrMask1 : 1; /* * [1:1]err mask of ECC uncorrectable error 1 */ + unsigned int eccUncrtErrMask0 : 1; /* * [0:0]err mask of ECC uncorrectable error 0 */ +#else + unsigned int eccUncrtErrMask0 : 1; /* * [0:0]err mask of ECC uncorrectable error 0 */ + unsigned int eccUncrtErrMask1 : 1; /* * [1:1]err mask of ECC uncorrectable error 1 */ + unsigned int eccUncrtErrMask2 : 1; /* * [2:2]err mask of ECC uncorrectable error 2 */ + unsigned int eccUncrtErrMask3 : 1; /* * [3:3]err mask of ECC uncorrectable error 3 */ + unsigned int eccUncrtErrMask4 : 1; /* * [4:4]err mask of ECC uncorrectable error 4 */ + unsigned int eccUncrtErrMask5 : 1; /* * [5:5]err mask of ECC uncorrectable error 5 */ + unsigned int eccUncrtErrMask6 : 1; /* * [6:6]err mask of ECC uncorrectable error 6 */ + unsigned int eccUncrtErrMask7 : 1; /* * [7:7]err mask of ECC uncorrectable error 7 */ + unsigned int reserved : 24; /* * [31:8]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_ERR1_MASK_U; + +/* ** + * Union name : SMEG1_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmeg1IndrectCtrl { + struct tagStSmeg1IndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1IndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smeg1IndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smeg1IndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg1IndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:GPR0 0x1:GPR1 0x2:ESR + 0x3:FIDR 0x4:FICR 0x5:Scoreboard （read to get data for debug,and write to + clear halt thread) 0x6:TDR (only in SMF) 0x7:ETR0(only in SMF) 0x8:ETR1(only + in SMF) 0x9:ARR (only in SMF) others:reservedNOTE：memory not support CSR write + oper ation when the thread is running */ + unsigned int + smeg1IndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.****** Comments for bit 9:3 - memory index **** + **For FICR: 8:3 instance ID, bit8 is RSV in SMFFor ScoreBoard: 7:3 thread ID, bit7 is + RSV in SMLFor fidr, 8:3 is instance id., bit8 is RSV in SMFFor gpr0/ gpr1,in SML: 9:8 + reserved, 7:4 is thread id; in SMF, 9 reserved, 8:4 is thread id. Bit3 is logic + flit id. For read gpr0, if bit3 is 0, read Flit0 ; if bit3 is 1, read flit2. For + read gpr1, if bit3 is 0, read flit1; if bit3 is 1, read flit3.For ETR0/ETR1, 9 + reserved, 8:4 is thread id. Bit3 is ETR id. For read ETR0, if bit3 is 0, read ID0 of + ETR0; if bit3 is 1, read ID1 of ETR0. For read ETR1, if bit3 is 0, read ID0 of + ETR1; if bit 3 is 1, read ID1 of ETR1.For esr, in SMF, 9 reserved, if bit8 is + 0,access normal esr0, if bit8 is 1,access esr1. (RSV in 1822) 7:3 is thread id.in SML + , bit9:7 reserved, 6:3 is thread id. For TDR: (only in SMF)bit7:3 is thread ID****** + Comments for bit 2:0 - word sel ******1. refer to FS AS for the detail data structure, and + ECC bit is read only2. DO NOT read write the word out of the MSB of the corresponding MEM + 0x0:0x2 + - reserved 0x3: data[159:128] 0x4: data[127:96] 0x5: + data[95:64] 0x6: data[63:32] 0x7: data[31:0] + */ +#else + unsigned int + smeg1IndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.****** Comments for bit 9:3 - memory index **** + **For FICR: 8:3 instance ID, bit8 is RSV in SMFFor ScoreBoard: 7:3 thread ID, bit7 is + RSV in SMLFor fidr, 8:3 is instance id., bit8 is RSV in SMFFor gpr0/ gpr1,in SML: 9:8 + reserved, 7:4 is thread id; in SMF, 9 reserved, 8:4 is thread id. Bit3 is logic + flit id. For read gpr0, if bit3 is 0, read Flit0 ; if bit3 is 1, read flit2. For + read gpr1, if bit3 is 0, read flit1; if bit3 is 1, read flit3.For ETR0/ETR1, 9 + reserved, 8:4 is thread id. Bit3 is ETR id. For read ETR0, if bit3 is 0, read ID0 of + ETR0; if bit3 is 1, read ID1 of ETR0. For read ETR1, if bit3 is 0, read ID0 of + ETR1; if bit 3 is 1, read ID1 of ETR1.For esr, in SMF, 9 reserved, if bit8 is + 0,access normal esr0, if bit8 is 1,access esr1. (RSV in 1822) 7:3 is thread id.in SML + , bit9:7 reserved, 6:3 is thread id. For TDR: (only in SMF)bit7:3 is thread ID****** + Comments for bit 2:0 - word sel ******1. refer to FS AS for the detail data structure, and + ECC bit is read only2. DO NOT read write the word out of the MSB of the corresponding MEM + 0x0:0x2 + - reserved 0x3: data[159:128] 0x4: data[127:96] 0x5: + data[95:64] 0x6: data[63:32] 0x7: data[31:0] + */ + unsigned int smeg1IndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:GPR0 0x1:GPR1 0x2:ESR + 0x3:FIDR 0x4:FICR 0x5:Scoreboard （read to get data for debug,and write to + clear halt thread) 0x6:TDR (only in SMF) 0x7:ETR0(only in SMF) 0x8:ETR1(only + in SMF) 0x9:ARR (only in SMF) others:reservedNOTE：memory not support CSR write + oper ation when the thread is running */ + unsigned int smeg1IndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smeg1IndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smeg1IndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INDRECT_CTRL_U; + +/* ** + * Union name : SMEG1_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmeg1IndrectTimeout { + struct tagStSmeg1IndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1IndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smeg1IndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMEG1_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmeg1IndrectData { + struct tagStSmeg1IndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1IndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smeg1IndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_INDRECT_DATA_U; + +/* ** +* Union name : SMEG1_CNT_CFG +* @brief SMEG1 counter configuration register. This register is used for debug or for statistics +collection + +* Description: +*/ +typedef union tagUnSmeg1CntCfg { + struct tagStSmeg1CntCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]SMEG1 has four counters to count various events generated in the + infrastructure or in the engines. For the engines, the events can also be counted for a + specif ic instance, as programmed in the smeg1_cnt_match_id register. */ + unsigned int cnt3Sel : 1; /* * [12:12]0: SEND1:ENGINE_EVENT[3] */ + unsigned int cnt2Sel : 1; /* * [11:11]0:FINISH1:ENGINE_EVENT[2] */ + unsigned int cnt1Sel : 2; /* * [10:9]00:WAKEUP01:SLEEP10:ENGINE_LD_ST11:ENGINE_EVENT[1] */ + unsigned int cnt0Sel : 1; /* * [8:8]0:INSTALL1:ENGINE_EVENT[0] */ + unsigned int cnt3MatchEn : 1; /* * [7:7]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt2MatchEn : 1; /* * [6:6]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt1MatchEn : 1; /* * [5:5]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt0MatchEn : 1; /* * [4:4]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt3Enable : 1; /* * [3:3]1: counter3 is enabled 0: counter3 is disabled */ + unsigned int cnt2Enable : 1; /* * [2:2]1: counter2 is enabled 0: counter2 is disabled */ + unsigned int cnt1Enable : 1; /* * [1:1]1: counter1 is enabled 0: counter1 is disabled */ + unsigned int cnt0Enable : 1; /* * [0:0]1: counter0 is enabled 0: counter0 is disabled */ +#else + unsigned int cnt0Enable : 1; /* * [0:0]1: counter0 is enabled 0: counter0 is disabled */ + unsigned int cnt1Enable : 1; /* * [1:1]1: counter1 is enabled 0: counter1 is disabled */ + unsigned int cnt2Enable : 1; /* * [2:2]1: counter2 is enabled 0: counter2 is disabled */ + unsigned int cnt3Enable : 1; /* * [3:3]1: counter3 is enabled 0: counter3 is disabled */ + unsigned int cnt0MatchEn : 1; /* * [4:4]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt1MatchEn : 1; /* * [5:5]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt2MatchEn : 1; /* * [6:6]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt3MatchEn : 1; /* * [7:7]Count for a 'specific Instance ID'. if this bit is not enabled, the + counter will count the event for every instance. 1: count for specific + instanc e only 0: count for every instance */ + unsigned int cnt0Sel : 1; /* * [8:8]0:INSTALL1:ENGINE_EVENT[0] */ + unsigned int cnt1Sel : 2; /* * [10:9]00:WAKEUP01:SLEEP10:ENGINE_LD_ST11:ENGINE_EVENT[1] */ + unsigned int cnt2Sel : 1; /* * [11:11]0:FINISH1:ENGINE_EVENT[2] */ + unsigned int cnt3Sel : 1; /* * [12:12]0: SEND1:ENGINE_EVENT[3] */ + unsigned int reserved : 19; /* * [31:13]SMEG1 has four counters to count various events generated in the + infrastructure or in the engines. For the engines, the events can also be counted for a + specif ic instance, as programmed in the smeg1_cnt_match_id register. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_CNT_CFG_U; + +/* ** +* Union name : SMEG1_CNT_MATCH_ID +* @brief This register is used to configure Instance IDs for all four counters. This can be used for +debug or for performance analysis. + +* Description: +*/ +typedef union tagUnSmeg1CntMatchId { + struct tagStSmeg1CntMatchId { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 8; /* * [31:24]reserved */ + unsigned int cnt3MatchId : 6; /* * [23:18]Instance ID for counter 3 */ + unsigned int cnt2MatchId : 6; /* * [17:12]Instance ID for counter 2 */ + unsigned int cnt1MatchId : 6; /* * [11:6]Instance ID for counter 1 */ + unsigned int cnt0MatchId : 6; /* * [5:0]Instance ID for counter 0 */ +#else + unsigned int cnt0MatchId : 6; /* * [5:0]Instance ID for counter 0 */ + unsigned int cnt1MatchId : 6; /* * [11:6]Instance ID for counter 1 */ + unsigned int cnt2MatchId : 6; /* * [17:12]Instance ID for counter 2 */ + unsigned int cnt3MatchId : 6; /* * [23:18]Instance ID for counter 3 */ + unsigned int reserved : 8; /* * [31:24]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_CNT_MATCH_ID_U; + +/* ** +* Union name : SMEG1_CNT0 +* @brief This smmeg1 counter0 register is a statistics counter that counts API install and engine event0 + +* Description: +*/ +typedef union tagUnSmeg1Cnt0 { + struct tagStSmeg1Cnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smeg1Cnt0 : 48; /* * [47:0]depending on the configuration this counter counts command + * install, or engine event 0. This can also be programmed to count only for + * a specific instance + */ +#else + unsigned long long smeg1Cnt0 : 48; /* * [47:0]depending on the configuration this counter counts command + * install, or engine event 0. This can also be programmed to count only for + * a specific instance + */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CNT0_U; + +/* ** +* Union name : SMEG1_CNT1 +* @brief This smeg1 counter1 register is a statistics counter that counts load, store, sleep, wakeup, and +engine event 1 + +* Description: +*/ +typedef union tagUnSmeg1Cnt1 { + struct tagStSmeg1Cnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smeg1Cnt1 : 48; /* * [47:0]depending on the configuration this counter counts thread + prel-oadstore, sleep, wakeup, or engine event 1. This can also be programmed to count + only for a spec ific instance */ +#else + unsigned long long smeg1Cnt1 : 48; /* * [47:0]depending on the configuration this counter counts thread + prel-oadstore, sleep, wakeup, or engine event 1. This can also be programmed to count + only for a spec ific instance */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CNT1_U; + +/* ** +* Union name : SMEG1_CNT2 +* @brief This smeg1 counter1 register is a statistics counter that counts 'finish' or engine event 2 + +* Description: +*/ +typedef union tagUnSmeg1Cnt2 { + struct tagStSmeg1Cnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smeg1Cnt2 : 48; /* * [47:0]depending on the configuration this counter counts thread + * terminate, or engine event 2. This can also be programmed to count only + * for a specific instance + */ +#else + unsigned long long smeg1Cnt2 : 48; /* * [47:0]depending on the configuration this counter counts thread + * terminate, or engine event 2. This can also be programmed to count only + * for a specific instance + */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CNT2_U; + +/* ** +* Union name : SMEG1_CNT3 +* @brief This smeg1 counter3 register is a statistics counter that counts 'send' and engine event 3 + +* Description: +*/ +typedef union tagUnSmeg1Cnt3 { + struct tagStSmeg1Cnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smeg1Cnt3 : 48; /* * [47:0]depending on the configuration this counter counts message send to + * smit , or engine event 3. This can also be programmed to count only for a + * specific instance + */ +#else + unsigned long long smeg1Cnt3 : 48; /* * [47:0]depending on the configuration this counter counts message send to + * smit , or engine event 3. This can also be programmed to count only for a + * specific instance + */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CNT3_U; + +/* ** +* Union name : SMEG1_TCD_CTP +* @brief This is the SMEG1 thread TCD register. This register contains the read data that comes from +the TCD. + +* Description: +*/ +typedef union tagUnSmeg1TcdCtp { + struct tagStSmeg1TcdCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 8; /* * [31:24]reserved. */ + unsigned int ctp : 24; /* * [23:0][23:18] : instance id [17:15]: error response type[14] : rd2_etr1_id[13] : + rd2_etr0_id[12] : rd1_etr1_id[11] : rd1_etr0_id [10] : o-bit [9:5] : engine id[4] : gpr1 id + in second issue[3] : gpr0 id in second issue[2] : dual issue [1] : gpr1 id in first issue [0] + : gpr0 id in first issue + */ +#else + unsigned int ctp : 24; /* * [23:0][23:18] : instance id [17:15]: error response type[14] : rd2_etr1_id[13] : + rd2_etr0_id[12] : rd1_etr1_id[11] : rd1_etr0_id [10] : o-bit [9:5] : engine id[4] : gpr1 id + in second issue[3] : gpr0 id in second issue[2] : dual issue [1] : gpr1 id in first issue [0] + : gpr0 id in first issue + */ + unsigned int reserved : 8; /* * [31:24]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TCD_CTP_U; + +/* ** +* Union name : SMEG1_RUNAWAY_THD_CTP +* @brief Each bit represents a runaway thread. When a thread runs for more than a sampling time, it is +considered a runaway thread. Bit63 logs runaway errors for the t hread 63, and bit0 logs the error for the thread 0 +respectively. +* Description: +*/ +typedef union tagUnSmeg1RunawayThdCtp { + struct tagStSmeg1RunawayThdCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ctp : 32; /* * [31:0]1: This thread is active for a very long time (>sample period). No new issue + for this thread. 0: nor mal + operation If configured, this register also can be + used for active thread ctp. + */ +#else + unsigned int ctp : 32; /* * [31:0]1: This thread is active for a very long time (>sample period). No new issue + for this thread. 0: nor mal + operation If configured, this register also can be + used for active thread ctp. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_RUNAWAY_THD_CTP_U; + +/* ** + * Union name : SMEG1_CTP0 + * @brief This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. + * Description: + */ +typedef union tagUnSmeg1Ctp0 { + struct tagStSmeg1Ctp0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 8; /* * [63:56]reserved. */ + unsigned long long tcd : 24; /* * [55:32]TCD ctp registers */ + unsigned long long activeRunawayThd : 32; /* * [31:0]32thread scoreboard active */ +#else + unsigned long long activeRunawayThd : 32; /* * [31:0]32thread scoreboard active */ + unsigned long long tcd : 24; /* * [55:32]TCD ctp registers */ + unsigned long long reserved : 8; /* * [63:56]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CTP0_U; + +/* ** + * Union name : SMEG1_CTP1 + * @brief This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. + * Description: + */ +typedef union tagUnSmeg1Ctp1 { + struct tagStSmeg1Ctp1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 20; /* * [63:44]reserved */ + unsigned long long smeg1Internal : 44; /* * [43:0][43:41] fifoD_ctl_credit(6), [40:38] fifoD_data_credit(6) + [37] fifo a_sop(0) [36] fifob_sop(0) + [35] fifoc_sop(0) [34] fifoa_eop(0) [33] fifob_eop(0) [32] + fifoc_eop(0) [31] + riq_valid(0), [30] iiq_valid(0), [29] + fifoa_allocated(0), [28] fifob_allocated(0), [27] + fifoc_allocated(0), [26] abuf_afifo_valid(0), + [25] fifob_prestore(0), [24] fifoc_prestore(0), + [23:20] fairness_count(0), [19:17] reserved (0)[16] fifoe_empty(1)[15] + fifoe_full (0) [14] fifoa_empty(1) + [13] fifoa_full (0) [12] fifob_empty(1) + [11] fifob_full(0) [10] fifoC_empty(1), [9] + fifoc_full(0) [8:2] + available_thd_id The default value of availble_thd_id in SML and SMF is dif + ferent, SML is 14 in Dec; SMF is 30 in Dec. [1] allocate_available(1) [0] + resp_thd_free (0)The default value of smeg1_internal in SMF is 0x0d800001547a; in + SML is :0x0d800001543a; + */ +#else + unsigned long long smeg1Internal : 44; /* * [43:0][43:41] fifoD_ctl_credit(6), [40:38] fifoD_data_credit(6) + [37] fifo a_sop(0) [36] fifob_sop(0) + [35] fifoc_sop(0) [34] fifoa_eop(0) [33] fifob_eop(0) [32] + fifoc_eop(0) [31] + riq_valid(0), [30] iiq_valid(0), [29] + fifoa_allocated(0), [28] fifob_allocated(0), [27] + fifoc_allocated(0), [26] abuf_afifo_valid(0), + [25] fifob_prestore(0), [24] fifoc_prestore(0), + [23:20] fairness_count(0), [19:17] reserved (0)[16] fifoe_empty(1)[15] + fifoe_full (0) [14] fifoa_empty(1) + [13] fifoa_full (0) [12] fifob_empty(1) + [11] fifob_full(0) [10] fifoC_empty(1), [9] + fifoc_full(0) [8:2] + available_thd_id The default value of availble_thd_id in SML and SMF is dif + ferent, SML is 14 in Dec; SMF is 30 in Dec. [1] allocate_available(1) [0] + resp_thd_free (0)The default value of smeg1_internal in SMF is 0x0d800001547a; in + SML is :0x0d800001543a; + */ + unsigned long long reserved : 20; /* * [63:44]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CTP1_U; + +/* ** + * Union name : SMEG1_CTP2 + * @brief This is Smart Memory Infra Engine Group1 (SMEG1)snapshot register. + * Description: + */ +typedef union tagUnSmeg1Ctp2 { + struct tagStSmeg1Ctp2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int wtRunaway : 32; /* * [31:0]thread runaway counter has overflow, and thread is in the status of + * waiting new issued of this thread or terminate of this thread; + */ +#else + unsigned int wtRunaway : 32; /* * [31:0]thread runaway counter has overflow, and thread is in the status of + * waiting new issued of this thread or terminate of this thread; + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_CTP2_U; + +/* ** + * Union name : SMEG1_TMT_EXT_CFG + * @brief TIMER engine control info + * Description: + */ +typedef union tagUnSmeg1TmtExtCfg { + struct tagStSmeg1TmtExtCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smeg1TmtExtCfg : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual + entry size and cache line size.value indcates:00: actual size/cache line szie = + 1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11: + actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 31Bit [29:28]: entry + 30Bit [27: 26]: entry 29Bit [25:24]: entry 28Bit [23:22]: entry 27Bit [21:20]: + entry 26Bit [19:18]: entry 25Bit [17:16]: entry 24Bit [15:14]: entry 23Bit + [13:12]: entry 22 Bit [11:10]: entry 21Bit [9:8] : entry 20Bit [7:6] : entry + 19Bit [5:4] : entry 18Bit [3:2] : entry 17Bit [1:0] : entry 16 + */ +#else + unsigned int smeg1TmtExtCfg : 32; /* * [31:0]Timer Memory Type extend table. Indicate relationship with actual + entry size and cache line size.value indcates:00: actual size/cache line szie = + 1;01: actual s ize/cache line szie = 1/2;10: actual size/cache line szie = 1/4;11: + actual size/cache line szie = 1/8;Address:Bit [31:30]: entry 31Bit [29:28]: entry + 30Bit [27: 26]: entry 29Bit [25:24]: entry 28Bit [23:22]: entry 27Bit [21:20]: + entry 26Bit [19:18]: entry 25Bit [17:16]: entry 24Bit [15:14]: entry 23Bit + [13:12]: entry 22 Bit [11:10]: entry 21Bit [9:8] : entry 20Bit [7:6] : entry + 19Bit [5:4] : entry 18Bit [3:2] : entry 17Bit [1:0] : entry 16 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_TMT_EXT_CFG_U; + +/* ** +* Union name : SMEG1_MEM_ECC_ERR_CTP +* @brief ecc ERR ADDR; CAPTURE the last err addr;only valid when the ECC interrupt is reported; + +* Description: +*/ +typedef union tagUnSmeg1MemEccErrCtp { + struct tagStSmeg1MemEccErrCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 18; /* * [31:14]reserved */ + unsigned int addr : 6; /* * [13:8]err_addr:for fidr: err instance ID;for other mem: [13:9]-error thread ID, + * bit[8]-err mem ID; + */ + unsigned int flag : 8; /* * [7:0]flag to indicate which memory the err_addr is:7 - fidr6 - gpr05 - gpr14 - etr03 + * - etr12 - esr1 - tdr0 - arr + */ +#else + unsigned int flag : 8; /* * [7:0]flag to indicate which memory the err_addr is:7 - fidr6 - gpr05 - gpr14 - etr03 + * - etr12 - esr1 - tdr0 - arr + */ + unsigned int addr : 6; /* * [13:8]err_addr:for fidr: err instance ID;for other mem: [13:9]-error thread ID, + * bit[8]-err mem ID; + */ + unsigned int reserved : 18; /* * [31:14]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_MEM_ECC_ERR_CTP_U; + +/* ** + * Union name : SMMC_CACHE_RESOURCE_CTP + * @brief SMMC WQE Cache resource counter + * Description: + */ +typedef union tagUnSmmcCacheResourceCtp { + struct tagStSmmcCacheResourceCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 2; /* * [31:30]reserved */ + unsigned int rqCnt : 14; /* * [29:16]SMMC RQ WQE Cache resource counter, This field indicate cache line number + * has been used. + */ + unsigned int reserved1 : 2; /* * [15:14]reserved */ + unsigned int sqCnt : 14; /* * [13:0]SMMC SQ WQE Cache resource counter, This field indicate cache line number + * has been used. + */ +#else + unsigned int sqCnt : 14; /* * [13:0]SMMC SQ WQE Cache resource counter, This field indicate cache line number + * has been used. + */ + unsigned int reserved1 : 2; /* * [15:14]reserved */ + unsigned int rqCnt : 14; /* * [29:16]SMMC RQ WQE Cache resource counter, This field indicate cache line number + * has been used. + */ + unsigned int reserved0 : 2; /* * [31:30]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_CACHE_RESOURCE_CTP_U; + +/* ** + * Union name : SMEG1_SYNC_API_CFG + * @brief SYNC_API configuration register + * Description: + */ +typedef union tagUnSmeg1SyncApiCfg { + struct tagStSmeg1SyncApiCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 22; /* * [31:10]reserved */ + unsigned int syncCntThreshold : 2; /* * [9:8]The number of sync API allowed to waiting for getting lock must be + * equal or less than this threshold.0: max number is 4;1~3: max number; + */ + unsigned int reserved1 : 2; /* * [7:6]reserved */ + unsigned int snapshotEngEn : 1; /* * [5:5]enable snapshot based engine ID0: disable1: enable */ + unsigned int snapshotEngId : 5; /* * [4:0]SYNC_API snapshot engine IDdefault to timer engine ID. */ +#else + unsigned int snapshotEngId : 5; /* * [4:0]SYNC_API snapshot engine IDdefault to timer engine ID. */ + unsigned int snapshotEngEn : 1; /* * [5:5]enable snapshot based engine ID0: disable1: enable */ + unsigned int reserved1 : 2; /* * [7:6]reserved */ + unsigned int syncCntThreshold : 2; /* * [9:8]The number of sync API allowed to waiting for getting lock must be + * equal or less than this threshold.0: max number is 4;1~3: max number; + */ + unsigned int reserved0 : 22; /* * [31:10]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMEG1_SYNC_API_CFG_U; + +/* ** + * Union name : SMEG1_CUR_TIMESTAMP_US + * @brief Current timestamp (us) + * Description: + */ +typedef union tagUnSmeg1CurTimestampUs { + struct tagStSmeg1CurTimestampUs { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 15; /* * [63:49]reserved. */ + unsigned long long ctp : 49; /* * [48:0]Current timestamp (us) */ +#else + unsigned long long ctp : 49; /* * [48:0]Current timestamp (us) */ + unsigned long long reserved : 15; /* * [63:49]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMEG1_CUR_TIMESTAMP_US_U; + + +/* ** + * Union name : SMIT_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmitVersion { + struct tagStSmitVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smitVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smitVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_VERSION_U; + +/* ** +* Union name : SMIT_CFG +* @brief This is the Smart Memory Infra Transmission (SMIT) module configuration register. The software +use this register for debug. + +* Description: +*/ +typedef union tagUnSmitCfg { + struct tagStSmitCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 12; /* * [31:20]reserved */ + unsigned int rpUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory. Enable memory check, when use this err + inection function. */ + unsigned int rpCrtErrInjReq : 1; /* * [18:18]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int memPbChkEn : 1; /* * [17:17]memory check enable.1'b0:disable all memories check.1'b1:enable all + * memories check. + */ + unsigned int memRet1n : 1; /* * [16:16]control of memory pin RET1N */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int reserved1 : 7; /* * [7:1] */ + unsigned int disOder : 1; /* * [0:0]Ordering queue enable configuration.this is for debug . Software can + disable SMIT ordering queue function via this field . Hw will ignore O-bit inside API w + hen software set this field. 1 : disable ordering transmission .0: enable ordering + transmission.Note:only used for debug,users should know the api counts before + config this bit. */ +#else + unsigned int disOder : 1; /* * [0:0]Ordering queue enable configuration.this is for debug . Software can + disable SMIT ordering queue function via this field . Hw will ignore O-bit inside API w + hen software set this field. 1 : disable ordering transmission .0: enable ordering + transmission.Note:only used for debug,users should know the api counts before + config this bit. */ + unsigned int reserved1 : 7; /* * [7:1] */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [16:16]control of memory pin RET1N */ + unsigned int memPbChkEn : 1; /* * [17:17]memory check enable.1'b0:disable all memories check.1'b1:enable all + * memories check. + */ + unsigned int rpCrtErrInjReq : 1; /* * [18:18]ECC crt err injection requestion;err injection start when posedge + of this bit is detected; After Err injection start, err is injected when a memory + read is issu ed to the memory.Enable memory check, when use this err inection + function. */ + unsigned int rpUncrtErrInjReq : 1; /* * [19:19]ECC uncrt err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when + a memory read is is sued to the memory. Enable memory check, when use this err + inection function. */ + unsigned int reserved0 : 12; /* * [31:20]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_CFG_U; + +/* ** + * Union name : SMIT_INT_VECTOR + * @brief SMIT interrupt vector + * Description: + */ +typedef union tagUnSmitIntVector { + struct tagStSmitIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INT_VECTOR_U; + +/* ** + * Union name : SMIT_INT + * @brief SMIT interrupt status vector + * Description: + */ +typedef union tagUnSmitInt { + struct tagStSmitInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + corresponding error registers on the sheet1 : SMIT memory (TMDR/TMHR/TMNHR) parity error + deteced . 0 : No SMIT memory parity error deteced. */ +#else + unsigned int intData : 3; /* * [2:0]interrupt masked field,it is the collection of the error bits from the + corresponding error registers on the sheet1 : SMIT memory (TMDR/TMHR/TMNHR) parity error + deteced . 0 : No SMIT memory parity error deteced. */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INT_U; + +/* ** + * Union name : SMIT_INT_MASK + * @brief SMIT interrupt mask vector + * Description: + */ +typedef union tagUnSmitIntMask { + struct tagStSmitIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 3; /* * [2:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INT_MASK_U; + +/* ** + * Union name : SMIT_ERR_PRTY + * @brief RSV + * Description: + */ +typedef union tagUnSmitErrPrty { + struct tagStSmitErrPrty { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]RSV */ + unsigned int multiErrorBit : 1; /* * [1:1]RSV */ + unsigned int errorBit : 1; /* * [0:0]RSV */ +#else + unsigned int errorBit : 1; /* * [0:0]RSV */ + unsigned int multiErrorBit : 1; /* * [1:1]RSV */ + unsigned int sticky : 30; /* * [31:2]RSV */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_ERR_PRTY_U; + +/* ** + * Union name : SMIT_MEM_ECC_CRT_ERR + * @brief tmdr ecc correctable err + * Description: + */ +typedef union tagUnSmitMemEccCrtErr { + struct tagStSmitMemEccCrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + offbit11:4: err tmdr addressbit3:0: err_tmdr_id bit3 - tmdr3 error detected bit2 - + tmdr2 error detected bit1 - tmdr1 error detected bit0 - tmdr0 error detected */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + offbit11:4: err tmdr addressbit3:0: err_tmdr_id bit3 - tmdr3 error detected bit2 - + tmdr2 error detected bit1 - tmdr1 error detected bit0 - tmdr0 error detected */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_MEM_ECC_CRT_ERR_U; + +/* ** + * Union name : SMIT_MEM_ECC_UNCRT_ERR + * @brief tmdr ecc uncorrectable err + * Description: + */ +typedef union tagUnSmitMemEccUncrtErr { + struct tagStSmitMemEccUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + offbit11:4: err tmdr addressbit3:0: err_tmdr_id bit3 - tmdr3 error detected bit2 - + tmdr2 error detected bit1 - tmdr1 error detected bit0 - tmdr0 error detected */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of the first error, capture even if mask is + offbit11:4: err tmdr addressbit3:0: err_tmdr_id bit3 - tmdr3 error detected bit2 - + tmdr2 error detected bit1 - tmdr1 error detected bit0 - tmdr0 error detected */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_MEM_ECC_UNCRT_ERR_U; + +/* ** + * Union name : SMIT_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmitIndrectCtrl { + struct tagStSmitIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smitIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smitIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smitIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smitIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:TMHR 0x1:TMNHR + 0x2:TMLIST (only support read op) 0x3:TMCD (only support read op) 0x4:TMDR0 + 0x5:TMDR1 0x6: TMDR2 0x7:TMDR3 others:reserved */ + unsigned int smitIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.1.bit[11:3] memory address in SML: + TMDR bit[10:3] valid TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid in SMF: TMDR + bit[11:3] valid TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid2.bit[2:0] word select: + 0~3: reserved, 0x4:mem_dat[127:96] 0x5:mem_dat[95:64] 0x6:mem_dat[63:32] + 0x7:mem_dat[31:0]Note 1: for accessing tmhr/ tmnhr/ tmlist/ tmcd,bit[2:0] shoul d + be 0x7.; */ +#else + unsigned int smitIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address + in one group or internal address of the table.1.bit[11:3] memory address in SML: + TMDR bit[10:3] valid TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid in SMF: TMDR + bit[11:3] valid TMHR/TMNHR/TMLIST/TMCD bit[8:3] valid2.bit[2:0] word select: + 0~3: reserved, 0x4:mem_dat[127:96] 0x5:mem_dat[95:64] 0x6:mem_dat[63:32] + 0x7:mem_dat[31:0]Note 1: for accessing tmhr/ tmnhr/ tmlist/ tmcd,bit[2:0] shoul d + be 0x7.; */ + unsigned int smitIndirTab : 4; /* * [27:24]It specifies memory group or table. 0x0:TMHR 0x1:TMNHR + 0x2:TMLIST (only support read op) 0x3:TMCD (only support read op) 0x4:TMDR0 + 0x5:TMDR1 0x6: TMDR2 0x7:TMDR3 others:reserved */ + unsigned int smitIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smitIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smitIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INDRECT_CTRL_U; + +/* ** + * Union name : SMIT_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmitIndrectTimeout { + struct tagStSmitIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smitIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smitIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMIT_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmitIndrectData { + struct tagStSmitIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smitIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smitIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMIT_INDRECT_DATA_U; + + +/* ** + * Union name : SMLC_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmlcVersion { + struct tagStSmlcVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smlcVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smlcVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_VERSION_U; + +/* ** + * Union name : SMLC_CFG0 + * @brief Smart Memory Lock Cache Controller (SMLC) configuration 0. + * Description: + */ +typedef union tagUnSmlcCfg0 { + struct tagStSmlcCfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 8; /* * [31:24]reserved */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int reserved1 : 5; /* * [7:3]reserved */ + unsigned int smlcUncrtErrInj : 1; /* * [2:2]smlc ECC un-corrected err injection requestion;err injection start + when posedge of this bit is detected; After Err injection start, err is injected + when a memor y read is issued to the memory. */ + unsigned int smlcCrtErrInj : 1; /* * [1:1]smlc ECC corrected err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when a + memory r ead is issued to the memory. */ + unsigned int smlcEccChkEn : 1; /* * [0:0]whether enable ECC check.0:disable;1:enable. */ +#else + unsigned int smlcEccChkEn : 1; /* * [0:0]whether enable ECC check.0:disable;1:enable. */ + unsigned int smlcCrtErrInj : 1; /* * [1:1]smlc ECC corrected err injection requestion;err injection start when + posedge of this bit is detected; After Err injection start, err is injected when a + memory r ead is issued to the memory. */ + unsigned int smlcUncrtErrInj : 1; /* * [2:2]smlc ECC un-corrected err injection requestion;err injection start + when posedge of this bit is detected; After Err injection start, err is injected + when a memor y read is issued to the memory. */ + unsigned int reserved1 : 5; /* * [7:3]reserved */ + unsigned int tpRamTmod : 8; /* * [15:8]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int reserved0 : 8; /* * [31:24]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CFG0_U; + +/* ** + * Union name : SMLC_CFG1 + * @brief Smart Memory Lock Cache Controller (SMLC) configuration 1. + * Description: + */ +typedef union tagUnSmlcCfg1 { + struct tagStSmlcCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int bypassCd310 : 32; /* * [31:0]whether bypass cache data.Bit31~bit0:cache data31~cache data0.0:not + * bypass;1:bypass.In this situation, the cache data is always invalid. + */ +#else + unsigned int bypassCd310 : 32; /* * [31:0]whether bypass cache data.Bit31~bit0:cache data31~cache data0.0:not + * bypass;1:bypass.In this situation, the cache data is always invalid. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CFG1_U; + +/* ** + * Union name : SMLC_CFG2 + * @brief Smart Memory Lock Cache Controller (SMLC) configuration 2. + * Description: + */ +typedef union tagUnSmlcCfg2 { + struct tagStSmlcCfg2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int bypassCd6332 : 32; /* * [31:0]whether bypass cache data.Bit31~bit0:cache data63~cache data32.0:not + * bypass;1:bypass.In this situation, the cache data is always invalid. + */ +#else + unsigned int bypassCd6332 : 32; /* * [31:0]whether bypass cache data.Bit31~bit0:cache data63~cache data32.0:not + * bypass;1:bypass.In this situation, the cache data is always invalid. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CFG2_U; + +/* ** + * Union name : SMLC_INT_VECTOR + * @brief Smart Memory Lock Cache Controller (SMLC) interrupt vector register + * Description: + */ +typedef union tagUnSmlcIntVector { + struct tagStSmlcIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29] */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INT_VECTOR_U; + +/* ** + * Union name : SMLC_INT + * @brief Smart Memory Lock Cache Controller (SMLC) interrupt data register + * Description: + */ +typedef union tagUnSmlcInt { + struct tagStSmlcInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ + unsigned int reserved : 14; /* * [15:2]reserved */ + unsigned int intData : 2; /* * [1:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 2; /* * [1:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 14; /* * [15:2]reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INT_U; + +/* ** + * Union name : SMLC_INT_MASK + * @brief Smart Memory Lock Cache Controller (SMLC) interrupt mask register. + * Description: + */ +typedef union tagUnSmlcIntMask { + struct tagStSmlcIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + of CSR modules) asked for the interrupt.This register is used to mask any bits of + the interru pt register. Software engineers can use this register to mask + corresponding bits if they don not want these bits reporting to upper level. + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 2; /* * [1:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 14; /* * [15:2] */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + of CSR modules) asked for the interrupt.This register is used to mask any bits of + the interru pt register. Software engineers can use this register to mask + corresponding bits if they don not want these bits reporting to upper level. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INT_MASK_U; + +/* ** + * Union name : SMLC_SRF_OV_ERR + * @brief srf fifo overflow error. + * Description: + */ +typedef union tagUnSmlcSrfOvErr { + struct tagStSmlcSrfOvErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int sticky : 1; /* * [2:2]This field is fixed to be 0. */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 1; /* * [2:2]This field is fixed to be 0. */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_SRF_OV_ERR_U; + +/* ** + * Union name : SMLC_ECC_ERR + * @brief memory ecc error. + * Description: + */ +typedef union tagUnSmlcEccErr { + struct tagStSmlcEccErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 8; /* * [31:24]reserved. */ + unsigned int pab2bEccMerr : 1; /* * [23:23]pab memory 2bit ECC multi error; */ + unsigned int pab2bEccErr : 1; /* * [22:22]pab memory 2bit ECC error; */ + unsigned int pab1bEccMerr : 1; /* * [21:21]pab memory 1bit ECC multi error; */ + unsigned int pab1bEccErr : 1; /* * [20:20]pab memory 1bit ECC error; */ + unsigned int cdb12bEccMerr : 1; /* * [19:19]cdb1 memory 2bit ECC multi error; */ + unsigned int cdb12bEccErr : 1; /* * [18:18]cdb1 memory 2bit ECC error; */ + unsigned int cdb11bEccMerr : 1; /* * [17:17]cdb1 memory 1bit ECC multi error; */ + unsigned int cdb11bEccErr : 1; /* * [16:16]cdb1 memory 1bit ECC error; */ + unsigned int cdb02bEccMerr : 1; /* * [15:15]cdb0 memory 2bit ECC multi error; */ + unsigned int cdb02bEccErr : 1; /* * [14:14]cdb0 memory 2bit ECC error; */ + unsigned int cdb01bEccMerr : 1; /* * [13:13]cdb0 memory 1bit ECC multi error; */ + unsigned int cdb01bEccErr : 1; /* * [12:12]cdb0 memory 1bit ECC error; */ + unsigned int stb2bEccMerr : 1; /* * [11:11]stb memory 2bit ECC multi error; */ + unsigned int stb2bEccErr : 1; /* * [10:10]stb memory 2bit ECC error; */ + unsigned int stb1bEccMerr : 1; /* * [9:9]stb memory 1bit ECC multi error; */ + unsigned int stb1bEccErr : 1; /* * [8:8]stb memory 1bit ECC error; */ + unsigned int bat2bEccMerr : 1; /* * [7:7]bat memory 2bit ECC multi error; */ + unsigned int bat2bEccErr : 1; /* * [6:6]bat memory 2bit ECC error; */ + unsigned int bat1bEccMerr : 1; /* * [5:5]bat memory 1bit ECC multi error; */ + unsigned int bat1bEccErr : 1; /* * [4:4]bat memory 1bit ECC error; */ + unsigned int fiar2bEccMerr : 1; /* * [3:3]fiar memory 2bit ECC multi error; */ + unsigned int fiar2bEccErr : 1; /* * [2:2]fiar memory 2bit ECC error; */ + unsigned int fiar1bEccMerr : 1; /* * [1:1]fiar memory 1bit ECC multi error; */ + unsigned int fiar1bEccErr : 1; /* * [0:0]fiar memory 1bit ECC error; */ +#else + unsigned int fiar1bEccErr : 1; /* * [0:0]fiar memory 1bit ECC error; */ + unsigned int fiar1bEccMerr : 1; /* * [1:1]fiar memory 1bit ECC multi error; */ + unsigned int fiar2bEccErr : 1; /* * [2:2]fiar memory 2bit ECC error; */ + unsigned int fiar2bEccMerr : 1; /* * [3:3]fiar memory 2bit ECC multi error; */ + unsigned int bat1bEccErr : 1; /* * [4:4]bat memory 1bit ECC error; */ + unsigned int bat1bEccMerr : 1; /* * [5:5]bat memory 1bit ECC multi error; */ + unsigned int bat2bEccErr : 1; /* * [6:6]bat memory 2bit ECC error; */ + unsigned int bat2bEccMerr : 1; /* * [7:7]bat memory 2bit ECC multi error; */ + unsigned int stb1bEccErr : 1; /* * [8:8]stb memory 1bit ECC error; */ + unsigned int stb1bEccMerr : 1; /* * [9:9]stb memory 1bit ECC multi error; */ + unsigned int stb2bEccErr : 1; /* * [10:10]stb memory 2bit ECC error; */ + unsigned int stb2bEccMerr : 1; /* * [11:11]stb memory 2bit ECC multi error; */ + unsigned int cdb01bEccErr : 1; /* * [12:12]cdb0 memory 1bit ECC error; */ + unsigned int cdb01bEccMerr : 1; /* * [13:13]cdb0 memory 1bit ECC multi error; */ + unsigned int cdb02bEccErr : 1; /* * [14:14]cdb0 memory 2bit ECC error; */ + unsigned int cdb02bEccMerr : 1; /* * [15:15]cdb0 memory 2bit ECC multi error; */ + unsigned int cdb11bEccErr : 1; /* * [16:16]cdb1 memory 1bit ECC error; */ + unsigned int cdb11bEccMerr : 1; /* * [17:17]cdb1 memory 1bit ECC multi error; */ + unsigned int cdb12bEccErr : 1; /* * [18:18]cdb1 memory 2bit ECC error; */ + unsigned int cdb12bEccMerr : 1; /* * [19:19]cdb1 memory 2bit ECC multi error; */ + unsigned int pab1bEccErr : 1; /* * [20:20]pab memory 1bit ECC error; */ + unsigned int pab1bEccMerr : 1; /* * [21:21]pab memory 1bit ECC multi error; */ + unsigned int pab2bEccErr : 1; /* * [22:22]pab memory 2bit ECC error; */ + unsigned int pab2bEccMerr : 1; /* * [23:23]pab memory 2bit ECC multi error; */ + unsigned int reserved : 8; /* * [31:24]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_ECC_ERR_U; + +/* ** + * Union name : SMLC_ECC_ERRPR_MASK + * @brief + * Description: + */ +typedef union tagUnSmlcEccErrprMask { + struct tagStSmlcEccErrprMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12]reserved. */ + unsigned int pab2bEccErrMask : 1; /* * [11:11] */ + unsigned int pab1bEccErrMask : 1; /* * [10:10] */ + unsigned int cdb12bEccErrMask : 1; /* * [9:9] */ + unsigned int cdb11bEccErrMask : 1; /* * [8:8] */ + unsigned int cdb02bEccErrMask : 1; /* * [7:7] */ + unsigned int cdb01bEccErrMask : 1; /* * [6:6] */ + unsigned int stb2bEccErrMask : 1; /* * [5:5] */ + unsigned int stb1bEccErrMask : 1; /* * [4:4] */ + unsigned int bat2bEccErrMask : 1; /* * [3:3] */ + unsigned int bat1bEccErrMask : 1; /* * [2:2] */ + unsigned int fiar2bEccErrMask : 1; /* * [1:1] */ + unsigned int fiar1bEccErrMask : 1; /* * [0:0] */ +#else + unsigned int fiar1bEccErrMask : 1; /* * [0:0] */ + unsigned int fiar2bEccErrMask : 1; /* * [1:1] */ + unsigned int bat1bEccErrMask : 1; /* * [2:2] */ + unsigned int bat2bEccErrMask : 1; /* * [3:3] */ + unsigned int stb1bEccErrMask : 1; /* * [4:4] */ + unsigned int stb2bEccErrMask : 1; /* * [5:5] */ + unsigned int cdb01bEccErrMask : 1; /* * [6:6] */ + unsigned int cdb02bEccErrMask : 1; /* * [7:7] */ + unsigned int cdb11bEccErrMask : 1; /* * [8:8] */ + unsigned int cdb12bEccErrMask : 1; /* * [9:9] */ + unsigned int pab1bEccErrMask : 1; /* * [10:10] */ + unsigned int pab2bEccErrMask : 1; /* * [11:11] */ + unsigned int reserved : 20; /* * [31:12]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_ECC_ERRPR_MASK_U; + +/* ** + * Union name : SMLC_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmlcIndrectCtrl { + struct tagStSmlcIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smlcIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smlcIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smlcIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int + smlcIndirTab : 7; /* * [27:21]It specifies memory group or table. 0:fiar;1:pab; SML:mem_index(18). + SMF:stateless and memory mode: bankid(2),mem_index(19),reserved(88). statefull mode + : bankid(2), + cid0(10),cid1(10),base_addr(56),pcie_template(6),host_id(2),base_addr_type(1),refill_len(6),refill_len_valid(1),o_bit(1),csize(2),vcache_base(10),b + size(2).2:stb;3:cdb0; 4:cdb1;5:rsv;6:rsv;7:rsv.8:req_list_info_0; SML: + thread_id(4),base_sel(1),instance(6),mem_index(18),valid_cache_data(1),valid_list(1),hol + ding(1),sa_req(1),lha_req(1),28'b0. + SMF:thread_id(5),mem_index(56),valid_cache_data(1),valid_list(1),holding(1),sa_req(1),lha_req(1).mode(1),misc(1),mem(1),bat + _type(2),bpc(1),index_type(4),index_subtype(2),vf(10),ofst(6).9:req_list_info_1;…… + SML时，只有 req_list_info_0~31有效。71:req_list_info_63;72:BAT pointer table.other value: + reserved. */ + unsigned int + smlcIndirAddr : 21; /* * [20:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.14:5 - memory indexFor FIAR: 14:13 reserved, In + SMF: 12:8 is instance id; 7:5 is entry number in instance. In SML: 12:7 is + instance id; bit6 is entry number in instance.bit5 is RSV.For pab:(o nly support for CSR + read) 14:11 reserved, 10:6 thread ID, bit10 is RSV in SML. 5:3 reserved. 1个pab + entry的109bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个109bit，后续读此1 + 09bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先读地址bit[2:0]=7。 [2:0] word + select field.0x0:0x3 - reserved 0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: + data [31:0] For stb,(only support for CSR read) 14:11 reserved, 10:6 thread ID, bit10 is + RSV in SML. [5:3] 16Byte data entry index in an entry; When 0x0, indi cate to read byte + enable. [2:0] word select field.0x0:0x2 - reserved 0x3: data[159:128]0x4: + data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0]F or cdb0,(only support for + CSR read) 14:12 reserved, 11:6 list ID, bit11 is RSV in SML. [5:3] 16Byte data entry + index in an entry; [2:0] word select f ield.0x0:0x2 - reserved0x3: data[159:128](ECC + bit of 16B)0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] For + cdb1,(only support for CSR re ad) 14:12 reserved, 11:6 list ID, bit11 is RSV in SML. + [5:3] 16Byte data entry index in an entry; When 0x0, indicate to read byte enable. [2:0] + word s elect field.0x0: - reserved0x1: data[223:192] 0x2: data[191:160] 0x3: + data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] For r + eq_list_info,(only support for CSR read) 14:3 reserved, 1个req_list_info + 的94bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个94bit，后续读此94bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先 + 读地址bit[2:0]=7。 [2:0] word select field.0x0:0x4 - reserved 0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0]For BAT pointer table, 14:5 vf index. + */ +#else + unsigned int + smlcIndirAddr : 21; /* * [20:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.14:5 - memory indexFor FIAR: 14:13 reserved, In + SMF: 12:8 is instance id; 7:5 is entry number in instance. In SML: 12:7 is + instance id; bit6 is entry number in instance.bit5 is RSV.For pab:(o nly support for CSR + read) 14:11 reserved, 10:6 thread ID, bit10 is RSV in SML. 5:3 reserved. 1个pab + entry的109bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个109bit，后续读此1 + 09bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先读地址bit[2:0]=7。 [2:0] word + select field.0x0:0x3 - reserved 0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: + data [31:0] For stb,(only support for CSR read) 14:11 reserved, 10:6 thread ID, bit10 is + RSV in SML. [5:3] 16Byte data entry index in an entry; When 0x0, indi cate to read byte + enable. [2:0] word select field.0x0:0x2 - reserved 0x3: data[159:128]0x4: + data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0]F or cdb0,(only support for + CSR read) 14:12 reserved, 11:6 list ID, bit11 is RSV in SML. [5:3] 16Byte data entry + index in an entry; [2:0] word select f ield.0x0:0x2 - reserved0x3: data[159:128](ECC + bit of 16B)0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] For + cdb1,(only support for CSR re ad) 14:12 reserved, 11:6 list ID, bit11 is RSV in SML. + [5:3] 16Byte data entry index in an entry; When 0x0, indicate to read byte enable. [2:0] + word s elect field.0x0: - reserved0x1: data[223:192] 0x2: data[191:160] 0x3: + data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] For r + eq_list_info,(only support for CSR read) 14:3 reserved, 1个req_list_info + 的94bit对应一个完整的意义，当软件读地址[2:0]=7时，硬件锁存整个94bit，后续读此94bit时，从锁存寄存器中取。所以软件读pab的一个entry时，必须先 + 读地址bit[2:0]=7。 [2:0] word select field.0x0:0x4 - reserved 0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0]For BAT pointer table, 14:5 vf index. + */ + unsigned int + smlcIndirTab : 7; /* * [27:21]It specifies memory group or table. 0:fiar;1:pab; SML:mem_index(18). + SMF:stateless and memory mode: bankid(2),mem_index(19),reserved(88). statefull mode + : bankid(2), + cid0(10),cid1(10),base_addr(56),pcie_template(6),host_id(2),base_addr_type(1),refill_len(6),refill_len_valid(1),o_bit(1),csize(2),vcache_base(10),b + size(2).2:stb;3:cdb0; 4:cdb1;5:rsv;6:rsv;7:rsv.8:req_list_info_0; SML: + thread_id(4),base_sel(1),instance(6),mem_index(18),valid_cache_data(1),valid_list(1),hol + ding(1),sa_req(1),lha_req(1),28'b0. + SMF:thread_id(5),mem_index(56),valid_cache_data(1),valid_list(1),holding(1),sa_req(1),lha_req(1).mode(1),misc(1),mem(1),bat + _type(2),bpc(1),index_type(4),index_subtype(2),vf(10),ofst(6).9:req_list_info_1;…… + SML时，只有 req_list_info_0~31有效。71:req_list_info_63;72:BAT pointer table.other value: + reserved. */ + unsigned int smlcIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smlcIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smlcIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INDRECT_CTRL_U; + +/* ** + * Union name : SMLC_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmlcIndrectTimeout { + struct tagStSmlcIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smlcIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smlcIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMLC_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmlcIndrectData { + struct tagStSmlcIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smlcIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smlcIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: Software + write data to these registes and then enable indirect access, logic will send + these data to target.When operation read: Logic write data to these registers and + refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_INDRECT_DATA_U; + +/* ** + * Union name : SMLC_CNT0 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter0 + * Description: + */ +typedef union tagUnSmlcCnt0 { + struct tagStSmlcCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smlcCnt0 : 48; /* * [47:0]Event counter 0, count SMLC event from cnt_cfg */ +#else + unsigned long long smlcCnt0 : 48; /* * [47:0]Event counter 0, count SMLC event from cnt_cfg */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMLC_CNT0_U; + +/* ** + * Union name : SMLC_CNT1 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter1 + * Description: + */ +typedef union tagUnSmlcCnt1 { + struct tagStSmlcCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smlcCnt1 : 48; /* * [47:0]Event counter 1, count SMLC event from cnt_cfg */ +#else + unsigned long long smlcCnt1 : 48; /* * [47:0]Event counter 1, count SMLC event from cnt_cfg */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMLC_CNT1_U; + +/* ** + * Union name : SMLC_CNT2 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter2 + * Description: + */ +typedef union tagUnSmlcCnt2 { + struct tagStSmlcCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smlcCnt2 : 48; /* * [47:0]Event counter 2, count SMLC event from cnt_cfg */ +#else + unsigned long long smlcCnt2 : 48; /* * [47:0]Event counter 2, count SMLC event from cnt_cfg */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMLC_CNT2_U; + +/* ** + * Union name : SMLC_CNT3 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter3 + * Description: + */ +typedef union tagUnSmlcCnt3 { + struct tagStSmlcCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smlcCnt3 : 48; /* * [47:0]Event counter 3, count SMLC event from cnt_cfg */ +#else + unsigned long long smlcCnt3 : 48; /* * [47:0]Event counter 3, count SMLC event from cnt_cfg */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMLC_CNT3_U; + +/* ** + * Union name : SMLC_CNT_CFG0 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter configuration 0 + * Description: + */ +typedef union tagUnSmlcCntCfg0 { + struct tagStSmlcCntCfg0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int cnt3MatchInstId : 6; /* * [31:26]Counter 3 match instance ID */ + unsigned int cnt2MatchInstId : 6; /* * [25:20]Counter 2 match instance ID */ + unsigned int cnt1MatchInstId : 6; /* * [19:14]Counter 1 match instance ID */ + unsigned int cnt0MatchInstId : 6; /* * [13:8]Counter 0 match instance ID */ + unsigned int cnt3InstMatchEnable : 1; /* * [7:7]Counter 3 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt3_match_inst_id + */ + unsigned int cnt2InstMatchEnable : 1; /* * [6:6]Counter 2 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt2_match_inst_id + */ + unsigned int cnt1InstMatchEnable : 1; /* * [5:5]Counter 1 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt1_match_inst_id + */ + unsigned int cnt0InstMatchEnable : 1; /* * [4:4]Counter 0 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt0_match_inst_id + */ + unsigned int cntEnable : 4; /* * [3:0]Event counter enable for each counter */ +#else + unsigned int cntEnable : 4; /* * [3:0]Event counter enable for each counter */ + unsigned int cnt0InstMatchEnable : 1; /* * [4:4]Counter 0 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt0_match_inst_id + */ + unsigned int cnt1InstMatchEnable : 1; /* * [5:5]Counter 1 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt1_match_inst_id + */ + unsigned int cnt2InstMatchEnable : 1; /* * [6:6]Counter 2 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt2_match_inst_id + */ + unsigned int cnt3InstMatchEnable : 1; /* * [7:7]Counter 3 match instance ID enable,if enable, event counter only + * monitor instance event that match with cnt3_match_inst_id + */ + unsigned int cnt0MatchInstId : 6; /* * [13:8]Counter 0 match instance ID */ + unsigned int cnt1MatchInstId : 6; /* * [19:14]Counter 1 match instance ID */ + unsigned int cnt2MatchInstId : 6; /* * [25:20]Counter 2 match instance ID */ + unsigned int cnt3MatchInstId : 6; /* * [31:26]Counter 3 match instance ID */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CNT_CFG0_U; + +/* ** + * Union name : SMLC_CNT_CFG1 + * @brief Smart Memory Lock Cache Controller (SMLC) event counter configuration 1 + * Description: + */ +typedef union tagUnSmlcCntCfg1 { + struct tagStSmlcCntCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int cnt3EventSel : 4; /* * [15:12]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt2EventSel : 4; /* * [11:8]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt1EventSel : 4; /* * [7:4]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt0EventSel : 4; /* * [3:0]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ +#else + unsigned int cnt0EventSel : 4; /* * [3:0]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt1EventSel : 4; /* * [7:4]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt2EventSel : 4; /* * [11:8]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int cnt3EventSel : 4; /* * [15:12]0:load hit;(all load hit,include load no refill hit,load bpc + hit, etc.)1:load miss;(all load hit,include load no refill miss,load bpc miss, + etc.)2 :load lock hit;(all load lock hit, include load lock bpc hit, etc.)3:load + lock miss;(all load lock miss, include load lock bpc miss, etc.)4:load bpc;5:l + oad lock bpc;6:load_no_return;7:load_no_refill;8:store;(not include + bpc)9:store_release;(not include bpc)10:store_bpc;11:store release bpc;12:WQE cache + invalid; 13:non-WQE cache invalid;14:cache_out_mc;15:cache_out_vc; */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CNT_CFG1_U; + +/* ** + * Union name : SMLC_CREDIT_CTP + * @brief Smart Memory Lock Cache Controller (SMLC)credit snapshot register. + * Description: + */ +typedef union tagUnSmlcCreditCtp { + struct tagStSmlcCreditCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved. */ + unsigned int vcCredit : 2; /* * [6:5]bpc data credit value from Victim Cache.In SMF, the initial value is 0x1. + */ + unsigned int smmcCredit : 5; /* * [4:0]credit value from SMMC.In SMF, the initial value is 0x4. In SML, the + * initial value is 0x10. + */ +#else + unsigned int smmcCredit : 5; /* * [4:0]credit value from SMMC.In SMF, the initial value is 0x4. In SML, the + * initial value is 0x10. + */ + unsigned int vcCredit : 2; /* * [6:5]bpc data credit value from Victim Cache.In SMF, the initial value is 0x1. + */ + unsigned int reserved : 25; /* * [31:7]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_CREDIT_CTP_U; + +/* ** + * Union name : SMLC_FIFO_DEPTH_CTP + * @brief Smart Memory Lock Cache Controller (SMLC)fifo depth snapshot register. + * Description: + */ +typedef union tagUnSmlcFifoDepthCtp { + struct tagStSmlcFifoDepthCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 22; /* * [31:10]reserved. */ + unsigned int reserved1 : 5; /* * [9:5]reserved */ + unsigned int srfFifoDepth : 5; /* * [4:0]srf fifo real depth. */ +#else + unsigned int srfFifoDepth : 5; /* * [4:0]srf fifo real depth. */ + unsigned int reserved1 : 5; /* * [9:5]reserved */ + unsigned int reserved0 : 22; /* * [31:10]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_FIFO_DEPTH_CTP_U; + +/* ** + * Union name : SMLC_ECC_ERR_CTP + * @brief Smart Memory Lock Cache Controller (SMLC)parity error snapshot register. + * Description: + */ +typedef union tagUnSmlcEccErrCtp { + struct tagStSmlcEccErrCtp { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int eccErrorInfo : 32; /* * [31:0]This field will capture the information when main cache ECC error + occur.Note: this field only capture the onformation of the last error.[31:16] + reserved.[15:13] : information type. indicate which memory has ECC error. 0:fiar; + 1:pab; 2:stb; 3:cdb0; 4:cdb1; 5:bat; other value:reserved.For fiar memory + error:[12:8] reserved.[7:0] memory index;For pab memory error:[12:5] reserved.[4:0] + memory index;For stb memory error:[12:8] reserved.[7:3] memory index;[2:0] index + number o f error occured 16byte in a entry of data memory;For cdb0 memory + error:[12:9] reserved.[8:3] memory index;[2:0] index number of error occured 16byte + in a entry of data memory;For cdb1 memory error:[12:7] memory index;[6:0] index + number of error occured byte in a entry of data memory;For bat memory error:[12:10] + reserve d.[9:0] memory index; */ +#else + unsigned int eccErrorInfo : 32; /* * [31:0]This field will capture the information when main cache ECC error + occur.Note: this field only capture the onformation of the last error.[31:16] + reserved.[15:13] : information type. indicate which memory has ECC error. 0:fiar; + 1:pab; 2:stb; 3:cdb0; 4:cdb1; 5:bat; other value:reserved.For fiar memory + error:[12:8] reserved.[7:0] memory index;For pab memory error:[12:5] reserved.[4:0] + memory index;For stb memory error:[12:8] reserved.[7:3] memory index;[2:0] index + number o f error occured 16byte in a entry of data memory;For cdb0 memory + error:[12:9] reserved.[8:3] memory index;[2:0] index number of error occured 16byte + in a entry of data memory;For cdb1 memory error:[12:7] memory index;[6:0] index + number of error occured byte in a entry of data memory;For bat memory error:[12:10] + reserve d.[9:0] memory index; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMLC_ECC_ERR_CTP_U; + + +/* ** + * Union name : SMMC_F_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmmcFVersion { + struct tagStSmmcFVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smmcFVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VERSION_U; + +/* ** + * Union name : SMMC_F_MC_CFG + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCfg { + struct tagStSmmcFMcCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30] */ + unsigned int readSoRo : 2; /* * [29:28]so_ro configure for read operation.so_ro: 2 bits, it specifies the + ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict + Ordering; 2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed + Ordering and ID Based Ordering. + */ + unsigned int writeSoRo : 2; /* * [27:26]so_ro configure for write operation.so_ro: 2 bits, it specifies the + ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict + Ordering ;2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed + Ordering and ID Based Ordering. + */ + unsigned int memBankIdPst : 2; /* * [25:24]Bank id position in mem_index in memory mode, or stateless + mode.0:bank_id = mem_index[3:2];1:bank_id = mem_index[4:3];2:bank_id = + mem_index[5:4];3:bank_id = mem _index[6:5]; */ + unsigned int smmcQuStoreBpThd : 8; /* * [23:16]Qu store buffer backpressure threshold, in unit of 64Byte. If + * available space in qu store buffer is less than this value,qu store API + * will be blocked. + */ + unsigned int smmcQuReturnFifoBp0ffThd : 6; /* * [15:10]Qu return fifo release backpressure threshold. If used + * space in qu return fifo is less than this value, the backpressure + * will be released. + */ + unsigned int smmcQuReturnFifoBponThd : 6; /* * [9:4]Qu return fifo backpressure threshold. If used space in qu + return fifo is no less than this value, the backpressure will be set, and + qu load API will be blocked + . */ + unsigned int smmcMcEccParityEnable : 1; /* * [3:3]1'b1:enable ecc/parity check with memory read + * data;1'b0:disable ecc/parity check with memory read data; + */ + unsigned int smmcMcClaChkEnb : 1; /* * [2:2]1'b1:enable to check validation of CLA GPA.GPA[0] =1 means this GPA + * is valid, GPA[0]=0 means this GPA is invalid.1'b0:disable to check + * validation of CLA GPA. + */ + unsigned int + smmcFQuRxCtpEnb : 1; /* * [1:1]when this signal is enable, SMMC will capture first flit that received from + QU side.1'b1: enable;1'b0: + disable;注意：SMMC只抓该信号有效后从QU侧过来的第一个flit，抓住后保持不变；如果要重新抓新的fli + t，需要先把该信号拉低再拉高。 */ + unsigned int + smmcFQuTxCtpEnb : 1; /* * [0:0]when this signal is enable, SMMC will capture first flit that sent to QU + side.1'b1: enable;1'b0: + disable;注意：SMMC只抓该信号有效后SMMC发给QU的第一个flit，抓住后保持不变；如果要重新抓新的flit，需要 + 先把该信号拉低再拉高。 */ +#else + unsigned int + smmcFQuTxCtpEnb : 1; /* * [0:0]when this signal is enable, SMMC will capture first flit that sent to QU + side.1'b1: enable;1'b0: + disable;注意：SMMC只抓该信号有效后SMMC发给QU的第一个flit，抓住后保持不变；如果要重新抓新的flit，需要 + 先把该信号拉低再拉高。 */ + unsigned int + smmcFQuRxCtpEnb : 1; /* * [1:1]when this signal is enable, SMMC will capture first flit that received from + QU side.1'b1: enable;1'b0: + disable;注意：SMMC只抓该信号有效后从QU侧过来的第一个flit，抓住后保持不变；如果要重新抓新的fli + t，需要先把该信号拉低再拉高。 */ + unsigned int smmcMcClaChkEnb : 1; /* * [2:2]1'b1:enable to check validation of CLA GPA.GPA[0] =1 means this GPA + * is valid, GPA[0]=0 means this GPA is invalid.1'b0:disable to check + * validation of CLA GPA. + */ + unsigned int smmcMcEccParityEnable : 1; /* * [3:3]1'b1:enable ecc/parity check with memory read + * data;1'b0:disable ecc/parity check with memory read data; + */ + unsigned int smmcQuReturnFifoBponThd : 6; /* * [9:4]Qu return fifo backpressure threshold. If used space in qu + return fifo is no less than this value, the backpressure will be set, and + qu load API will be blocked + . */ + unsigned int smmcQuReturnFifoBp0ffThd : 6; /* * [15:10]Qu return fifo release backpressure threshold. If used + * space in qu return fifo is less than this value, the backpressure + * will be released. + */ + unsigned int smmcQuStoreBpThd : 8; /* * [23:16]Qu store buffer backpressure threshold, in unit of 64Byte. If + * available space in qu store buffer is less than this value,qu store API + * will be blocked. + */ + unsigned int memBankIdPst : 2; /* * [25:24]Bank id position in mem_index in memory mode, or stateless + mode.0:bank_id = mem_index[3:2];1:bank_id = mem_index[4:3];2:bank_id = + mem_index[5:4];3:bank_id = mem _index[6:5]; */ + unsigned int writeSoRo : 2; /* * [27:26]so_ro configure for write operation.so_ro: 2 bits, it specifies the + ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict + Ordering ;2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed + Ordering and ID Based Ordering. + */ + unsigned int readSoRo : 2; /* * [29:28]so_ro configure for read operation.so_ro: 2 bits, it specifies the + ATTR[1:0] bits in the outbound PCIe TLP headers of the DMA operation: 2’b00: Strict + Ordering; 2’b01: Relaxed Ordering;2’b10: ID Based Ordering;2’b11: Both Relaxed + Ordering and ID Based Ordering. + */ + unsigned int reserved : 2; /* * [31:30] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CFG_U; + +/* ** + * Union name : SMMC_F_MC_CFG1 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCfg1 { + struct tagStSmmcFMcCfg1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 2; /* * [31:30] */ + unsigned int bankidSrc : 15; /* * [29:15]For cache mode, where bankid come from.0:bank id = hash + value[4:3].1:bank id = smeg1_smlc_mem_index[4:3].Each bit is corresponding to each type + configuration.Ba nkid_src[0] is corresponding to type1=p_cxt2.…Bankid_src[14] is + corresponding to type15=others(GPA). + */ + unsigned int cidSrc : 15; /* * [14:0]For cache mode, where CID0/CID1 come from.0: CID0=hash value[22:14], + CID1=hash value[13:5].1: CID0=CID1=smeg1_smlc_mem_index[13:5].Each bit is corresponding to + each type configuration.cid_src[0] is corresponding to type1=p_cxt2.…cid_src[14] is + corresponding to type15=others(GPA). + */ +#else + unsigned int cidSrc : 15; /* * [14:0]For cache mode, where CID0/CID1 come from.0: CID0=hash value[22:14], + CID1=hash value[13:5].1: CID0=CID1=smeg1_smlc_mem_index[13:5].Each bit is corresponding to + each type configuration.cid_src[0] is corresponding to type1=p_cxt2.…cid_src[14] is + corresponding to type15=others(GPA). + */ + unsigned int bankidSrc : 15; /* * [29:15]For cache mode, where bankid come from.0:bank id = hash + value[4:3].1:bank id = smeg1_smlc_mem_index[4:3].Each bit is corresponding to each type + configuration.Ba nkid_src[0] is corresponding to type1=p_cxt2.…Bankid_src[14] is + corresponding to type15=others(GPA). + */ + unsigned int reserved : 2; /* * [31:30] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CFG1_U; + +/* ** +* Union name : SMMC_HASH_SEED0 +* @brief Hash function seed conifg register. This register used to change the original seed of hash +function. + +* Description: +*/ +typedef union tagUnSmmcHashSeed0 { + struct tagStSmmcHashSeed0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int hashSeedCfg0 : 32; /* * [31:0] */ +#else + unsigned int hashSeedCfg0 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_HASH_SEED0_U; + +/* ** +* Union name : SMMC_HASH_SEED1 +* @brief Hash function seed conifg register. This register used to change the original seed of hash +function. + +* Description: +*/ +typedef union tagUnSmmcHashSeed1 { + struct tagStSmmcHashSeed1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int hashSeedCfg1 : 32; /* * [31:0] */ +#else + unsigned int hashSeedCfg1 : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_HASH_SEED1_U; + +/* ** + * Union name : SMMC_F_CFG + * @brief SMMF_F configuration register . + * Description: + */ +typedef union tagUnSmmcFCfg { + struct tagStSmmcFCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int memRet1nDiv2 : 1; /* * [31:31]control of memory pin RET1N */ + unsigned int spRamTmodDiv2 : 7; /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int reserved : 2; /* * [23:22]reserved */ + unsigned int smmcFBankVldId : 4; /* * [21:18]indicate which bank is + valid,1'b1:valid;1'b0:invalid.Bit[0]:correspond to bank0;Bit[1]:correspond to + bank1;Bit[2]:correspond to bank2;Bit[3]:correspond to bank3 + ; */ + unsigned int smmcFBankVldNum : 2; /* * [17:16]indicate how many banks are valid:2'b00: 4 banks are valid;2'b01: + 1 bank is valid;2'b10: 2 banks are valid;2'b11: reserved;Note: this signal only + configure how many banks are valid, which bank is valid is cofigured by + smmc_f_bank_vld_id. */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int tpRamTmod : 8; /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ +#else + unsigned int tpRamTmod : 8; /* * [7:0]16FF+GL TP RF Memorybit[1:0]：WCT，2'b01bit[3:2]：RCT, + * 2'b01bit[6:4]：KP，3'b011bit[7]：floating，fixed 0 + */ + unsigned int spRamTmod : 7; /* * [14:8]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< 256), + * 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [15:15]control of memory pin RET1N */ + unsigned int smmcFBankVldNum : 2; /* * [17:16]indicate how many banks are valid:2'b00: 4 banks are valid;2'b01: + 1 bank is valid;2'b10: 2 banks are valid;2'b11: reserved;Note: this signal only + configure how many banks are valid, which bank is valid is cofigured by + smmc_f_bank_vld_id. */ + unsigned int smmcFBankVldId : 4; /* * [21:18]indicate which bank is + valid,1'b1:valid;1'b0:invalid.Bit[0]:correspond to bank0;Bit[1]:correspond to + bank1;Bit[2]:correspond to bank2;Bit[3]:correspond to bank3 + ; */ + unsigned int reserved : 2; /* * [23:22]reserved */ + unsigned int spRamTmodDiv2 : 7; /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1nDiv2 : 1; /* * [31:31]control of memory pin RET1N */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_CFG_U; + +/* ** + * Union name : SMMC_F_MC_INIT + * @brief SMMC_F main cache initialization + * Description: + */ +typedef union tagUnSmmcFMcInit { + struct tagStSmmcFMcInit { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 3; /* * [31:29] */ + unsigned int smmcMcInitEndAddr : 14; /* * [28:15]The end address in data memory to stop processing + initialization. */ + unsigned int smmcMcInitStartAddr : 14; /* * [14:1]The start address in data memory to begin processing + initialization. The initialization only process in the region from the start + address to the end address in four banks.Basically, only the memory mode + region in data memory needs to initializing. + */ + unsigned int smmcMcInit : 1; /* * [0:0]Write 1 to register will trigger one cycle pulse to start harware inital + * invalidate all cache line entries(include tag memory and data memory) in main + * cache. + */ +#else + unsigned int smmcMcInit : 1; /* * [0:0]Write 1 to register will trigger one cycle pulse to start harware inital + * invalidate all cache line entries(include tag memory and data memory) in main + * cache. + */ + unsigned int smmcMcInitStartAddr : 14; /* * [14:1]The start address in data memory to begin processing + initialization. The initialization only process in the region from the start + address to the end address in four banks.Basically, only the memory mode + region in data memory needs to initializing. + */ + unsigned int smmcMcInitEndAddr : 14; /* * [28:15]The end address in data memory to stop processing + initialization. */ + unsigned int reserved : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_INIT_U; + +/* ** + * Union name : SMMC_F_MC_RF_TIMEOUT_INTERVAL + * @brief + * Description: + */ +typedef union tagUnSmmcFMcRfTimeoutInterval { + struct tagStSmmcFMcRfTimeoutInterval { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcRefillTimeoutInterval : 32; /* * [31:0]the max interval for SMMC to refill data from host. if a + * refill operation interval exceed the configured interval, SMMC + * will report a timeout error to SW. + */ +#else + unsigned int mcRefillTimeoutInterval : 32; /* * [31:0]the max interval for SMMC to refill data from host. if a + * refill operation interval exceed the configured interval, SMMC + * will report a timeout error to SW. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_RF_TIMEOUT_INTERVAL_U; + +/* ** + * Union name : SMMC_F_INT_VECTOR + * @brief Statefull Smart Memory Memory Controller (SMMC_F) interrupt vector register + * Description: + */ +typedef union tagUnSmmcFIntVector { + struct tagStSmmcFIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29] */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP need + * to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INT_VECTOR_U; + +/* ** + * Union name : SMMC_F_INT + * @brief Smart Memory Memory Controller (SMMC) interrupt data register + * Description: + */ +typedef union tagUnSmmcFInt { + struct tagStSmmcFInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ + unsigned int reserved : 9; /* * [15:7]reserved */ + unsigned int intData : 7; /* * [6:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 7; /* * [6:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 9; /* * [15:7]reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INT_U; + +/* ** + * Union name : SMMC_F_INT_MASK + * @brief Statefull Smart Memory Memory Controller (SMMC_F) interrupt mask register. + * Description: + */ +typedef union tagUnSmmcFIntMask { + struct tagStSmmcFIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + of CSR modules) asked for the interrupt.This register is used to mask any bits of + the interru pt register. Software engineers can use this register to mask + corresponding bits if they don not want these bits reporting to upper level. + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 7; /* * [6:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 9; /* * [15:7] */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID,indicates to the CP which CSR module (or group + of CSR modules) asked for the interrupt.This register is used to mask any bits of + the interru pt register. Software engineers can use this register to mask + corresponding bits if they don not want these bits reporting to upper level. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INT_MASK_U; + +/* ** + * Union name : SMMC_F_MC_CACHE_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCacheErr { + struct tagStSmmcFMcCacheErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcData32bEccMerr : 1; /* * [31:31]main cache bank3 data memory 2bit ECC multi error; */ + unsigned int mcData32bEccErr : 1; /* * [30:30]main cache bank3 data memory 2bit ECC error; */ + unsigned int mcData31bEccMerr : 1; /* * [29:29]main cache bank3 data memory 1bit ECC multi error; */ + unsigned int mcData31bEccErr : 1; /* * [28:28]main cache bank3 data memory 1bit ECC error; */ + unsigned int mcData22bEccMerr : 1; /* * [27:27]main cache bank2 data memory 2bit ECC multi error; */ + unsigned int mcData22bEccErr : 1; /* * [26:26]main cache bank2 data memory 2bit ECC error; */ + unsigned int mcData21bEccMerr : 1; /* * [25:25]main cache bank2 data memory 1bit ECC multi error; */ + unsigned int mcData21bEccErr : 1; /* * [24:24]main cache bank2 data memory 1bit ECC error; */ + unsigned int mcData12bEccMerr : 1; /* * [23:23]main cache bank1 data memory 2bit ECC multi error; */ + unsigned int mcData12bEccErr : 1; /* * [22:22]main cache bank1 data memory 2bit ECC error; */ + unsigned int mcData11bEccMerr : 1; /* * [21:21]main cache bank1 data memory 1bit ECC multi error; */ + unsigned int mcData11bEccErr : 1; /* * [20:20]main cache bank1 data memory 1bit ECC error; */ + unsigned int mcData02bEccMerr : 1; /* * [19:19]main cache bank0 data memory 2bit ECC multi error; */ + unsigned int mcData02bEccErr : 1; /* * [18:18]main cache bank0 data memory 2bit ECC error; */ + unsigned int mcData01bEccMerr : 1; /* * [17:17]main cache bank0 data memory 1bit ECC multi error; */ + unsigned int mcData01bEccErr : 1; /* * [16:16]main cache bank0 data memory 1bit ECC error; */ + unsigned int mcTag32bEccMerr : 1; /* * [15:15]main cache bank3 tag memory 2bit ECC multi error; */ + unsigned int mcTag32bEccErr : 1; /* * [14:14]main cache bank3 tag memory 2bit ECC error; */ + unsigned int mcTag31bEccMerr : 1; /* * [13:13]main cache bank3 tag memory 1bit ECC multi error; */ + unsigned int mcTag31bEccErr : 1; /* * [12:12]main cache bank3 tag memory 1bit ECC error; */ + unsigned int mcTag22bEccMerr : 1; /* * [11:11]main cache bank2 tag memory 2bit ECC multi error; */ + unsigned int mcTag22bEccErr : 1; /* * [10:10]main cache bank2 tag memory 2bit ECC error; */ + unsigned int mcTag21bEccMerr : 1; /* * [9:9]main cache bank2 tag memory 1bit ECC multi error; */ + unsigned int mcTag21bEccErr : 1; /* * [8:8]main cache bank2 tag memory 1bit ECC error; */ + unsigned int mcTag12bEccMerr : 1; /* * [7:7]main cache bank1 tag memory 2bit ECC multi error; */ + unsigned int mcTag12bEccErr : 1; /* * [6:6]main cache bank1 tag memory 2bit ECC error; */ + unsigned int mcTag11bEccMerr : 1; /* * [5:5]main cache bank1 tag memory 1bit ECC multi error; */ + unsigned int mcTag11bEccErr : 1; /* * [4:4]main cache bank1 tag memory 1bit ECC error; */ + unsigned int mcTag02bEccMerr : 1; /* * [3:3]main cache bank0 tag memory 2bit ECC multi error; */ + unsigned int mcTag02bEccErr : 1; /* * [2:2]main cache bank0 tag memory 2bit ECC error; */ + unsigned int mcTag01bEccMerr : 1; /* * [1:1]main cache bank0 tag memory 1bit ECC multi error; */ + unsigned int mcTag01bEccErr : 1; /* * [0:0]main cache bank0 tag memory 1bit ECC error; */ +#else + unsigned int mcTag01bEccErr : 1; /* * [0:0]main cache bank0 tag memory 1bit ECC error; */ + unsigned int mcTag01bEccMerr : 1; /* * [1:1]main cache bank0 tag memory 1bit ECC multi error; */ + unsigned int mcTag02bEccErr : 1; /* * [2:2]main cache bank0 tag memory 2bit ECC error; */ + unsigned int mcTag02bEccMerr : 1; /* * [3:3]main cache bank0 tag memory 2bit ECC multi error; */ + unsigned int mcTag11bEccErr : 1; /* * [4:4]main cache bank1 tag memory 1bit ECC error; */ + unsigned int mcTag11bEccMerr : 1; /* * [5:5]main cache bank1 tag memory 1bit ECC multi error; */ + unsigned int mcTag12bEccErr : 1; /* * [6:6]main cache bank1 tag memory 2bit ECC error; */ + unsigned int mcTag12bEccMerr : 1; /* * [7:7]main cache bank1 tag memory 2bit ECC multi error; */ + unsigned int mcTag21bEccErr : 1; /* * [8:8]main cache bank2 tag memory 1bit ECC error; */ + unsigned int mcTag21bEccMerr : 1; /* * [9:9]main cache bank2 tag memory 1bit ECC multi error; */ + unsigned int mcTag22bEccErr : 1; /* * [10:10]main cache bank2 tag memory 2bit ECC error; */ + unsigned int mcTag22bEccMerr : 1; /* * [11:11]main cache bank2 tag memory 2bit ECC multi error; */ + unsigned int mcTag31bEccErr : 1; /* * [12:12]main cache bank3 tag memory 1bit ECC error; */ + unsigned int mcTag31bEccMerr : 1; /* * [13:13]main cache bank3 tag memory 1bit ECC multi error; */ + unsigned int mcTag32bEccErr : 1; /* * [14:14]main cache bank3 tag memory 2bit ECC error; */ + unsigned int mcTag32bEccMerr : 1; /* * [15:15]main cache bank3 tag memory 2bit ECC multi error; */ + unsigned int mcData01bEccErr : 1; /* * [16:16]main cache bank0 data memory 1bit ECC error; */ + unsigned int mcData01bEccMerr : 1; /* * [17:17]main cache bank0 data memory 1bit ECC multi error; */ + unsigned int mcData02bEccErr : 1; /* * [18:18]main cache bank0 data memory 2bit ECC error; */ + unsigned int mcData02bEccMerr : 1; /* * [19:19]main cache bank0 data memory 2bit ECC multi error; */ + unsigned int mcData11bEccErr : 1; /* * [20:20]main cache bank1 data memory 1bit ECC error; */ + unsigned int mcData11bEccMerr : 1; /* * [21:21]main cache bank1 data memory 1bit ECC multi error; */ + unsigned int mcData12bEccErr : 1; /* * [22:22]main cache bank1 data memory 2bit ECC error; */ + unsigned int mcData12bEccMerr : 1; /* * [23:23]main cache bank1 data memory 2bit ECC multi error; */ + unsigned int mcData21bEccErr : 1; /* * [24:24]main cache bank2 data memory 1bit ECC error; */ + unsigned int mcData21bEccMerr : 1; /* * [25:25]main cache bank2 data memory 1bit ECC multi error; */ + unsigned int mcData22bEccErr : 1; /* * [26:26]main cache bank2 data memory 2bit ECC error; */ + unsigned int mcData22bEccMerr : 1; /* * [27:27]main cache bank2 data memory 2bit ECC multi error; */ + unsigned int mcData31bEccErr : 1; /* * [28:28]main cache bank3 data memory 1bit ECC error; */ + unsigned int mcData31bEccMerr : 1; /* * [29:29]main cache bank3 data memory 1bit ECC multi error; */ + unsigned int mcData32bEccErr : 1; /* * [30:30]main cache bank3 data memory 2bit ECC error; */ + unsigned int mcData32bEccMerr : 1; /* * [31:31]main cache bank3 data memory 2bit ECC multi error; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CACHE_ERR_U; + +/* ** + * Union name : SMMC_F_MC_CACHE_MASK + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCacheMask { + struct tagStSmmcFMcCacheMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int mcData32bEccErrMask : 1; /* * [15:15] */ + unsigned int mcData31bEccErrMask : 1; /* * [14:14] */ + unsigned int mcData22bEccErrMask : 1; /* * [13:13] */ + unsigned int mcData21bEccErrMask : 1; /* * [12:12] */ + unsigned int mcData12bEccErrMask : 1; /* * [11:11] */ + unsigned int mcData11bEccErrMask : 1; /* * [10:10] */ + unsigned int mcData02bEccErrMask : 1; /* * [9:9] */ + unsigned int mcData01bEccErrMask : 1; /* * [8:8] */ + unsigned int mcTag32bEccErrMask : 1; /* * [7:7] */ + unsigned int mcTag31bEccErrMask : 1; /* * [6:6] */ + unsigned int mcTag22bEccErrMask : 1; /* * [5:5] */ + unsigned int mcTag21bEccErrMask : 1; /* * [4:4] */ + unsigned int mcTag12bEccErrMask : 1; /* * [3:3] */ + unsigned int mcTag11bEccErrMask : 1; /* * [2:2] */ + unsigned int mcTag02bEccErrMask : 1; /* * [1:1] */ + unsigned int mcTag01bEccErrMask : 1; /* * [0:0] */ +#else + unsigned int mcTag01bEccErrMask : 1; /* * [0:0] */ + unsigned int mcTag02bEccErrMask : 1; /* * [1:1] */ + unsigned int mcTag11bEccErrMask : 1; /* * [2:2] */ + unsigned int mcTag12bEccErrMask : 1; /* * [3:3] */ + unsigned int mcTag21bEccErrMask : 1; /* * [4:4] */ + unsigned int mcTag22bEccErrMask : 1; /* * [5:5] */ + unsigned int mcTag31bEccErrMask : 1; /* * [6:6] */ + unsigned int mcTag32bEccErrMask : 1; /* * [7:7] */ + unsigned int mcData01bEccErrMask : 1; /* * [8:8] */ + unsigned int mcData02bEccErrMask : 1; /* * [9:9] */ + unsigned int mcData11bEccErrMask : 1; /* * [10:10] */ + unsigned int mcData12bEccErrMask : 1; /* * [11:11] */ + unsigned int mcData21bEccErrMask : 1; /* * [12:12] */ + unsigned int mcData22bEccErrMask : 1; /* * [13:13] */ + unsigned int mcData31bEccErrMask : 1; /* * [14:14] */ + unsigned int mcData32bEccErrMask : 1; /* * [15:15] */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CACHE_MASK_U; + +/* ** + * Union name : SMMC_F_MC_CACHE_ERR_INFO + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCacheErrInfo { + struct tagStSmmcFMcCacheErrInfo { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + mcCacheErrInfo : 32; /* * [31:0]This field will capture the information when main cache ECC error + occur(corresponding to "SMMC_F_MC_CACHE_ERR").Note: this field only capture the onformation + of the last error.[31]: information valid flag. once there is ECC error occurs to any main + cache memory(tag memory or data memory),the bit will set valid.[30:28]: information type. + indicate which memory has ECC error. 3'b000: tag memory in bank0; 3'b001: tag memory in + bank1; 3'b010: tag memory in bank2; 3'b011: tag m emory in bank3; 3'b100: data memory in + bank0; 3'b101: data memory in bank1; 3'b110: data memory in bank2; 3'b111: data memory + in bank3;For main cache tag me mory error:[27:14] reserved.[13] error type: 1'b0: 1-bit + ECC error. 1'b1: 2-bit ECC error.[12] tag memory way number in a bank(corresponding to + CID0 or CID1);[11:2] memory address;[1:0] indicate which 16Byte has ECC error;For main + cache data memory error:[27:18] reserved.[17] error type: 1'b0: 1-bit ECC err or. 1'b1: + 2-bit ECC error.[16:2] memory address;[1:0] indicate which 16Byte has ECC error; + */ +#else + unsigned int + mcCacheErrInfo : 32; /* * [31:0]This field will capture the information when main cache ECC error + occur(corresponding to "SMMC_F_MC_CACHE_ERR").Note: this field only capture the onformation + of the last error.[31]: information valid flag. once there is ECC error occurs to any main + cache memory(tag memory or data memory),the bit will set valid.[30:28]: information type. + indicate which memory has ECC error. 3'b000: tag memory in bank0; 3'b001: tag memory in + bank1; 3'b010: tag memory in bank2; 3'b011: tag m emory in bank3; 3'b100: data memory in + bank0; 3'b101: data memory in bank1; 3'b110: data memory in bank2; 3'b111: data memory + in bank3;For main cache tag me mory error:[27:14] reserved.[13] error type: 1'b0: 1-bit + ECC error. 1'b1: 2-bit ECC error.[12] tag memory way number in a bank(corresponding to + CID0 or CID1);[11:2] memory address;[1:0] indicate which 16Byte has ECC error;For main + cache data memory error:[27:18] reserved.[17] error type: 1'b0: 1-bit ECC err or. 1'b1: + 2-bit ECC error.[16:2] memory address;[1:0] indicate which 16Byte has ECC error; + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CACHE_ERR_INFO_U; + +/* ** + * Union name : SMMC_F_BUFFER_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFBufferErr { + struct tagStSmmcFBufferErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int fifoOvfMerr : 1; /* * [31:31]fifo overflow multi error in main cache or victim cache. */ + unsigned int fifoOvfErr : 1; /* * [30:30]fifo overflow error in main cache or victim cache. */ + unsigned int directwqeMerr : 1; /* * [29:29]direct WQE e0/e1 multi error. */ + unsigned int directwqeErr : 1; /* * [28:28]direct WQE e0/e1 error. */ + unsigned int vcSmxtfBuf2bEccMerr : 1; /* * [27:27]victim cache smxt interface output fifo 2bit ECC multi error. + */ + unsigned int vcSmxtfBuf2bEccErr : 1; /* * [26:26]victim cache smxt interface output fifo 2bit ECC error. */ + unsigned int vcSmxtfBuf1bEccMerr : 1; /* * [25:25]victim cache smxt interface output fifo 1bit ECC multi error. + */ + unsigned int vcSmxtfBuf1bEccErr : 1; /* * [24:24]victim cache smxt interface output fifo 1bit ECC error. */ + unsigned int mcRfbuf2bEccMerr : 1; /* * [23:23]main cache refill data buffer 2bit ECC multi error. */ + unsigned int mcRfbuf2bEccErr : 1; /* * [22:22]main cache refill data buffer 2bit ECC error. */ + unsigned int mcRfbuf1bEccMerr : 1; /* * [21:21]main cache refill data buffer 1bit ECC multi error. */ + unsigned int mcRfbuf1bEccErr : 1; /* * [20:20]main cache refill data buffer 1bit ECC error. */ + unsigned int mcQuDatafifo2bEccMerr : 1; /* * [19:19]main cache qu data fifo 2bit ECC multi error. */ + unsigned int mcQuDatafifo2bEccErr : 1; /* * [18:18]main cache qu data fifo 2bit ECC error. */ + unsigned int mcQuDatafifo1bEccMerr : 1; /* * [17:17]main cache qu data fifo 1bit ECC multi error. */ + unsigned int mcQuDatafifo1bEccErr : 1; /* * [16:16]main cache qu data fifo 1bit ECC error. */ + unsigned int mcQuLrn2bEccMerr : 1; /* * [15:15]main cache qu lrn data buffer 2bit ECC multi error. */ + unsigned int mcQuLrn2bEccErr : 1; /* * [14:14]main cache qu lrn data buffer 2bit ECC error. */ + unsigned int mcQuLrn1bEccMerr : 1; /* * [13:13]main cache qu lrn data buffer 1bit ECC multi error. */ + unsigned int mcQuLrn1bEccErr : 1; /* * [12:12]main cache qu lrn data buffer 1bit ECC error. */ + unsigned int mcQuStbuf2bEccMerr : 1; /* * [11:11]main cache qu store data buffer 2bit ECC multi error. */ + unsigned int mcQuStbuf2bEccErr : 1; /* * [10:10]main cache qu store data buffer 2bit ECC error. */ + unsigned int mcQuStbuf1bEccMerr : 1; /* * [9:9]main cache qu store data buffer 1bit ECC multi error. */ + unsigned int mcQuStbuf1bEccErr : 1; /* * [8:8]main cache qu store data buffer 1bit ECC error. */ + unsigned int mcEngStbuf2bEccMerr : 1; /* * [7:7]main cache engine store data buffer 2bit ECC multi error. */ + unsigned int mcEngStbuf2bEccErr : 1; /* * [6:6]main cache engine store data buffer 2bit ECC error. */ + unsigned int mcEngStbuf1bEccMerr : 1; /* * [5:5]main cache engine store data buffer 1bit ECC multi error. */ + unsigned int mcEngStbuf1bEccErr : 1; /* * [4:4]main cache engine store data buffer 1bit ECC error. */ + unsigned int mcQuVfa2bEccMerr : 1; /* * [3:3]main cache VFA table 2bit ECC multi error. */ + unsigned int mcQuVfa2bEccErr : 1; /* * [2:2]main cache VFA table 2bit ECC error. */ + unsigned int mcQuVfa1bEccMerr : 1; /* * [1:1]main cache VFA table 1bit ECC multi error. */ + unsigned int mcQuVfa1bEccErr : 1; /* * [0:0]main cache VFA table 1bit ECC error. */ +#else + unsigned int mcQuVfa1bEccErr : 1; /* * [0:0]main cache VFA table 1bit ECC error. */ + unsigned int mcQuVfa1bEccMerr : 1; /* * [1:1]main cache VFA table 1bit ECC multi error. */ + unsigned int mcQuVfa2bEccErr : 1; /* * [2:2]main cache VFA table 2bit ECC error. */ + unsigned int mcQuVfa2bEccMerr : 1; /* * [3:3]main cache VFA table 2bit ECC multi error. */ + unsigned int mcEngStbuf1bEccErr : 1; /* * [4:4]main cache engine store data buffer 1bit ECC error. */ + unsigned int mcEngStbuf1bEccMerr : 1; /* * [5:5]main cache engine store data buffer 1bit ECC multi error. */ + unsigned int mcEngStbuf2bEccErr : 1; /* * [6:6]main cache engine store data buffer 2bit ECC error. */ + unsigned int mcEngStbuf2bEccMerr : 1; /* * [7:7]main cache engine store data buffer 2bit ECC multi error. */ + unsigned int mcQuStbuf1bEccErr : 1; /* * [8:8]main cache qu store data buffer 1bit ECC error. */ + unsigned int mcQuStbuf1bEccMerr : 1; /* * [9:9]main cache qu store data buffer 1bit ECC multi error. */ + unsigned int mcQuStbuf2bEccErr : 1; /* * [10:10]main cache qu store data buffer 2bit ECC error. */ + unsigned int mcQuStbuf2bEccMerr : 1; /* * [11:11]main cache qu store data buffer 2bit ECC multi error. */ + unsigned int mcQuLrn1bEccErr : 1; /* * [12:12]main cache qu lrn data buffer 1bit ECC error. */ + unsigned int mcQuLrn1bEccMerr : 1; /* * [13:13]main cache qu lrn data buffer 1bit ECC multi error. */ + unsigned int mcQuLrn2bEccErr : 1; /* * [14:14]main cache qu lrn data buffer 2bit ECC error. */ + unsigned int mcQuLrn2bEccMerr : 1; /* * [15:15]main cache qu lrn data buffer 2bit ECC multi error. */ + unsigned int mcQuDatafifo1bEccErr : 1; /* * [16:16]main cache qu data fifo 1bit ECC error. */ + unsigned int mcQuDatafifo1bEccMerr : 1; /* * [17:17]main cache qu data fifo 1bit ECC multi error. */ + unsigned int mcQuDatafifo2bEccErr : 1; /* * [18:18]main cache qu data fifo 2bit ECC error. */ + unsigned int mcQuDatafifo2bEccMerr : 1; /* * [19:19]main cache qu data fifo 2bit ECC multi error. */ + unsigned int mcRfbuf1bEccErr : 1; /* * [20:20]main cache refill data buffer 1bit ECC error. */ + unsigned int mcRfbuf1bEccMerr : 1; /* * [21:21]main cache refill data buffer 1bit ECC multi error. */ + unsigned int mcRfbuf2bEccErr : 1; /* * [22:22]main cache refill data buffer 2bit ECC error. */ + unsigned int mcRfbuf2bEccMerr : 1; /* * [23:23]main cache refill data buffer 2bit ECC multi error. */ + unsigned int vcSmxtfBuf1bEccErr : 1; /* * [24:24]victim cache smxt interface output fifo 1bit ECC error. */ + unsigned int vcSmxtfBuf1bEccMerr : 1; /* * [25:25]victim cache smxt interface output fifo 1bit ECC multi error. + */ + unsigned int vcSmxtfBuf2bEccErr : 1; /* * [26:26]victim cache smxt interface output fifo 2bit ECC error. */ + unsigned int vcSmxtfBuf2bEccMerr : 1; /* * [27:27]victim cache smxt interface output fifo 2bit ECC multi error. + */ + unsigned int directwqeErr : 1; /* * [28:28]direct WQE e0/e1 error. */ + unsigned int directwqeMerr : 1; /* * [29:29]direct WQE e0/e1 multi error. */ + unsigned int fifoOvfErr : 1; /* * [30:30]fifo overflow error in main cache or victim cache. */ + unsigned int fifoOvfMerr : 1; /* * [31:31]fifo overflow multi error in main cache or victim cache. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_BUFFER_ERR_U; + +/* ** + * Union name : SMMC_F_BUFFER_MASK + * @brief + * Description: + */ +typedef union tagUnSmmcFBufferMask { + struct tagStSmmcFBufferMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int fifoOvfErrMask : 1; /* * [15:15] */ + unsigned int directwqeErrMask : 1; /* * [14:14] */ + unsigned int vcSmxtfBuf2bEccErrMask : 1; /* * [13:13] */ + unsigned int vcSmxtfBuf1bEccErrMask : 1; /* * [12:12] */ + unsigned int mcRfbuf2bEccErrMask : 1; /* * [11:11] */ + unsigned int mcRfbuf1bEccErrMask : 1; /* * [10:10] */ + unsigned int mcQuDatafifo2bEccErrMask : 1; /* * [9:9] */ + unsigned int mcQuDatafifo1bEccErrMask : 1; /* * [8:8] */ + unsigned int mcQuLrn2bEccErrMask : 1; /* * [7:7] */ + unsigned int mcQuLrn1bEccErrMask : 1; /* * [6:6] */ + unsigned int mcQuStbuf2bEccErrMask : 1; /* * [5:5] */ + unsigned int mcQuStbuf1bEccErrMask : 1; /* * [4:4] */ + unsigned int mcEngStbuf2bEccErrMask : 1; /* * [3:3] */ + unsigned int mcEngStbuf1bEccErrMask : 1; /* * [2:2] */ + unsigned int mcQuVfa2bEccErrMask : 1; /* * [1:1] */ + unsigned int mcQuVfa1bEccErrMask : 1; /* * [0:0] */ +#else + unsigned int mcQuVfa1bEccErrMask : 1; /* * [0:0] */ + unsigned int mcQuVfa2bEccErrMask : 1; /* * [1:1] */ + unsigned int mcEngStbuf1bEccErrMask : 1; /* * [2:2] */ + unsigned int mcEngStbuf2bEccErrMask : 1; /* * [3:3] */ + unsigned int mcQuStbuf1bEccErrMask : 1; /* * [4:4] */ + unsigned int mcQuStbuf2bEccErrMask : 1; /* * [5:5] */ + unsigned int mcQuLrn1bEccErrMask : 1; /* * [6:6] */ + unsigned int mcQuLrn2bEccErrMask : 1; /* * [7:7] */ + unsigned int mcQuDatafifo1bEccErrMask : 1; /* * [8:8] */ + unsigned int mcQuDatafifo2bEccErrMask : 1; /* * [9:9] */ + unsigned int mcRfbuf1bEccErrMask : 1; /* * [10:10] */ + unsigned int mcRfbuf2bEccErrMask : 1; /* * [11:11] */ + unsigned int vcSmxtfBuf1bEccErrMask : 1; /* * [12:12] */ + unsigned int vcSmxtfBuf2bEccErrMask : 1; /* * [13:13] */ + unsigned int directwqeErrMask : 1; /* * [14:14] */ + unsigned int fifoOvfErrMask : 1; /* * [15:15] */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_BUFFER_MASK_U; + +/* ** + * Union name : SMMC_F_BUFFER_ERR_INFO + * @brief + * Description: + */ +typedef union tagUnSmmcFBufferErrInfo { + struct tagStSmmcFBufferErrInfo { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + mcBufferErrInfo : 32; /* * [31:0]This field will capture the information when other buffer memory ECC error + occur(corresponding to "SMMC_F_BUFFER_ERR").Note: this field only capture the informa tion + of the last error.[31]: information valid flag. once there is ECC error occurs to any + buffer memory,this bit will set valid.[30:28]: information type. indi cate which buffer + memory has ECC error. 3'b000: VFA table; 3'b001: engine store data buffer; 3'b010: qu + store data buffer; 3'b011: qu lrn data buffer; 3'b1 00: qu data fifo; 3'b101: refill + data buffer; 3'b110: vc smxtf buffer; 3'b111: fifo overflow;For VFA table:[27:11] + reserved.[10] error type: 1'b0: 1-bit ECC error. 1'b1: 2-bit ECC error.[9:0] + memory address. For engine store data buffer:[27:11] reserved.[10] error type: 1'b0: + 1-bit ECC error. 1'b1: 2 -bit ECC error.[9] buffer number: 1'b0: buffer0; 1'b1: + buffer1;[8:3] memory access index (SMMC outstanding tag).[2:0] The error 16B position in + 64B. For qu store data buffer:[27:9] reserved.[8] error type: 1'b0: 1-bit ECC error. + 1'b1: 2-bit ECC error.[7:0] memory access address.For qu lrn data buffer:[27 :7] + reserved.[6] error type: 1'b0: 1-bit ECC error. 1'b1: 2-bit ECC error.[5:0] memory + access address.For qu data fifo:[27:6] reserved.[5] error type: 1'b0: 1-bit ECC error. + 1'b1: 2-bit ECC error.[4:0] memory access address.For refill data buffer:[27:9] + reserved.[8] error type: 1'b0: 1-bit ECC error . 1'b1: 2-bit ECC error.[7:0] + memory access address. For VC smxtf buffer:[27:6] reserved[5] error type: 1'b0: 1-bit + ECC error. 1'b1: 2-bit ECC error + .[4:0] memory access address.For fifo overflow, indicate which fifo is overflow:[15]:qu + command bimap error;[14]:qu command csize error;[13]:qu command tag type error;[12]:victim + cache3 write back fifo overflow;[11]:victim cache2 write back fifo overflow;[10]:victim + cache1 write back fifo overflow;[9]:victim cache0 wri te back fifo overflow;[8]:bank3 rcb + refill response fifo overflow;[7]:bank2 rcb refill response fifo overflow;[6]:bank1 rcb + refill response fifo overflow;[5]:ba nk0 rcb refill response fifo overflow;[4]:smxr refill + response fifo overflow;[3]:qu store ack fifo overflow;[2]:qu lrn fifo overflow;[1]:qu data + fifo overflow;[ 0]:qu command fifo overflow; */ +#else + unsigned int + mcBufferErrInfo : 32; /* * [31:0]This field will capture the information when other buffer memory ECC error + occur(corresponding to "SMMC_F_BUFFER_ERR").Note: this field only capture the informa tion + of the last error.[31]: information valid flag. once there is ECC error occurs to any + buffer memory,this bit will set valid.[30:28]: information type. indi cate which buffer + memory has ECC error. 3'b000: VFA table; 3'b001: engine store data buffer; 3'b010: qu + store data buffer; 3'b011: qu lrn data buffer; 3'b1 00: qu data fifo; 3'b101: refill + data buffer; 3'b110: vc smxtf buffer; 3'b111: fifo overflow;For VFA table:[27:11] + reserved.[10] error type: 1'b0: 1-bit ECC error. 1'b1: 2-bit ECC error.[9:0] + memory address. For engine store data buffer:[27:11] reserved.[10] error type: 1'b0: + 1-bit ECC error. 1'b1: 2 -bit ECC error.[9] buffer number: 1'b0: buffer0; 1'b1: + buffer1;[8:3] memory access index (SMMC outstanding tag).[2:0] The error 16B position in + 64B. For qu store data buffer:[27:9] reserved.[8] error type: 1'b0: 1-bit ECC error. + 1'b1: 2-bit ECC error.[7:0] memory access address.For qu lrn data buffer:[27 :7] + reserved.[6] error type: 1'b0: 1-bit ECC error. 1'b1: 2-bit ECC error.[5:0] memory + access address.For qu data fifo:[27:6] reserved.[5] error type: 1'b0: 1-bit ECC error. + 1'b1: 2-bit ECC error.[4:0] memory access address.For refill data buffer:[27:9] + reserved.[8] error type: 1'b0: 1-bit ECC error . 1'b1: 2-bit ECC error.[7:0] + memory access address. For VC smxtf buffer:[27:6] reserved[5] error type: 1'b0: 1-bit + ECC error. 1'b1: 2-bit ECC error + .[4:0] memory access address.For fifo overflow, indicate which fifo is overflow:[15]:qu + command bimap error;[14]:qu command csize error;[13]:qu command tag type error;[12]:victim + cache3 write back fifo overflow;[11]:victim cache2 write back fifo overflow;[10]:victim + cache1 write back fifo overflow;[9]:victim cache0 wri te back fifo overflow;[8]:bank3 rcb + refill response fifo overflow;[7]:bank2 rcb refill response fifo overflow;[6]:bank1 rcb + refill response fifo overflow;[5]:ba nk0 rcb refill response fifo overflow;[4]:smxr refill + response fifo overflow;[3]:qu store ack fifo overflow;[2]:qu lrn fifo overflow;[1]:qu data + fifo overflow;[ 0]:qu command fifo overflow; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_BUFFER_ERR_INFO_U; + +/* ** + * Union name : SMMC_F_MC_RF_RTN_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFMcRfRtnErr { + struct tagStSmmcFMcRfRtnErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2][31:2]:reserved;Note：the error information is captured in a proprietary + register, which could be read via indirect CSR access(via indirect memory/register group + "4'd14: qu interface capture data flit AND smf refill error captured information"). + */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int sticky : 30; /* * [31:2][31:2]:reserved;Note：the error information is captured in a proprietary + register, which could be read via indirect CSR access(via indirect memory/register group + "4'd14: qu interface capture data flit AND smf refill error captured information"). + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_RF_RTN_ERR_U; + +/* ** + * Union name : SMMC_F_MC_RF_TIMEOUT_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFMcRfTimeoutErr { + struct tagStSmmcFMcRfTimeoutErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2][31:2]:reserved; */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int sticky : 30; /* * [31:2][31:2]:reserved; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_RF_TIMEOUT_ERR_U; + +/* ** + * Union name : SMMC_F_MC_MULTI_HIT_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFMcMultiHitErr { + struct tagStSmmcFMcMultiHitErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2][31:30]: reserved;[29]: multiple hit both in main cache and victim + cache;[28]: multiple hit in main cache;[27:24]: tag type;[23:22]: BANK-ID;[21:12]: + CID1;[11:2 + ]: CID0; */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error found1:error found */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error found1:more than 1 errors found */ + unsigned int sticky : 30; /* * [31:2][31:30]: reserved;[29]: multiple hit both in main cache and victim + cache;[28]: multiple hit in main cache;[27:24]: tag type;[23:22]: BANK-ID;[21:12]: + CID1;[11:2 + ]: CID0; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_MULTI_HIT_ERR_U; + +/* ** + * Union name : SMMC_F_VC_CACHE_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFVcCacheErr { + struct tagStSmmcFVcCacheErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int vcData32bEccMerr : 1; /* * [31:31]victim cache bank3 data memory 2bit ECC multi error; */ + unsigned int vcData32bEccErr : 1; /* * [30:30]victim cache bank3 data memory 2bit ECC error; */ + unsigned int vcData31bEccMerr : 1; /* * [29:29]victim cache bank3 data memory 1bit ECC multi error; */ + unsigned int vcData31bEccErr : 1; /* * [28:28]victim cache bank3 data memory 1bit ECC error; */ + unsigned int vcData22bEccMerr : 1; /* * [27:27]victim cache bank2 data memory 2bit ECC multi error; */ + unsigned int vcData22bEccErr : 1; /* * [26:26]victim cache bank2 data memory 2bit ECC error; */ + unsigned int vcData21bEccMerr : 1; /* * [25:25]victim cache bank2 data memory 1bit ECC multi error; */ + unsigned int vcData21bEccErr : 1; /* * [24:24]victim cache bank2 data memory 1bit ECC error; */ + unsigned int vcData12bEccMerr : 1; /* * [23:23]victim cache bank1 data memory 2bit ECC multi error; */ + unsigned int vcData12bEccErr : 1; /* * [22:22]victim cache bank1 data memory 2bit ECC error; */ + unsigned int vcData11bEccMerr : 1; /* * [21:21]victim cache bank1 data memory 1bit ECC multi error; */ + unsigned int vcData11bEccErr : 1; /* * [20:20]victim cache bank1 data memory 1bit ECC error; */ + unsigned int vcData02bEccMerr : 1; /* * [19:19]victim cache bank0 data memory 2bit ECC multi error; */ + unsigned int vcData02bEccErr : 1; /* * [18:18]victim cache bank0 data memory 2bit ECC error; */ + unsigned int vcData01bEccMerr : 1; /* * [17:17]victim cache bank0 data memory 1bit ECC multi error; */ + unsigned int vcData01bEccErr : 1; /* * [16:16]victim cache bank0 data memory 1bit ECC error; */ + unsigned int vcWb32bEccMerr : 1; /* * [15:15]victim cache bank3 write back memory 2bit ECC multi error; */ + unsigned int vcWb32bEccErr : 1; /* * [14:14]victim cache bank3 write back memory 2bit ECC error; */ + unsigned int vcWb31bEccMerr : 1; /* * [13:13]victim cache bank3 write back memory 1bit ECC multi error; */ + unsigned int vcWb31bEccErr : 1; /* * [12:12]victim cache bank3 write back memory 1bit ECC error; */ + unsigned int vcWb22bEccMerr : 1; /* * [11:11]victim cache bank2 write back memory 2bit ECC multi error; */ + unsigned int vcWb22bEccErr : 1; /* * [10:10]victim cache bank2 write back memory 2bit ECC error; */ + unsigned int vcWb21bEccMerr : 1; /* * [9:9]victim cache bank2 write back memory 1bit ECC multi error; */ + unsigned int vcWb21bEccErr : 1; /* * [8:8]victim cache bank2 write back memory 1bit ECC error; */ + unsigned int vcWb12bEccMerr : 1; /* * [7:7]victim cache bank1 write back memory 2bit ECC multi error; */ + unsigned int vcWb12bEccErr : 1; /* * [6:6]victim cache bank1 write back memory 2bit ECC error; */ + unsigned int vcWb11bEccMerr : 1; /* * [5:5]victim cache bank1 write back memory 1bit ECC multi error; */ + unsigned int vcWb11bEccErr : 1; /* * [4:4]victim cache bank1 write back memory 1bit ECC error; */ + unsigned int vcWb02bEccMerr : 1; /* * [3:3]victim cache bank0 write back memory 2bit ECC multi error; */ + unsigned int vcWb02bEccErr : 1; /* * [2:2]victim cache bank0 write back memory 2bit ECC error; */ + unsigned int vcWb01bEccMerr : 1; /* * [1:1]victim cache bank0 write back memory 1bit ECC multi error; */ + unsigned int vcWb01bEccErr : 1; /* * [0:0]victim cache bank0 write back memory 1bit ECC error; */ +#else + unsigned int vcWb01bEccErr : 1; /* * [0:0]victim cache bank0 write back memory 1bit ECC error; */ + unsigned int vcWb01bEccMerr : 1; /* * [1:1]victim cache bank0 write back memory 1bit ECC multi error; */ + unsigned int vcWb02bEccErr : 1; /* * [2:2]victim cache bank0 write back memory 2bit ECC error; */ + unsigned int vcWb02bEccMerr : 1; /* * [3:3]victim cache bank0 write back memory 2bit ECC multi error; */ + unsigned int vcWb11bEccErr : 1; /* * [4:4]victim cache bank1 write back memory 1bit ECC error; */ + unsigned int vcWb11bEccMerr : 1; /* * [5:5]victim cache bank1 write back memory 1bit ECC multi error; */ + unsigned int vcWb12bEccErr : 1; /* * [6:6]victim cache bank1 write back memory 2bit ECC error; */ + unsigned int vcWb12bEccMerr : 1; /* * [7:7]victim cache bank1 write back memory 2bit ECC multi error; */ + unsigned int vcWb21bEccErr : 1; /* * [8:8]victim cache bank2 write back memory 1bit ECC error; */ + unsigned int vcWb21bEccMerr : 1; /* * [9:9]victim cache bank2 write back memory 1bit ECC multi error; */ + unsigned int vcWb22bEccErr : 1; /* * [10:10]victim cache bank2 write back memory 2bit ECC error; */ + unsigned int vcWb22bEccMerr : 1; /* * [11:11]victim cache bank2 write back memory 2bit ECC multi error; */ + unsigned int vcWb31bEccErr : 1; /* * [12:12]victim cache bank3 write back memory 1bit ECC error; */ + unsigned int vcWb31bEccMerr : 1; /* * [13:13]victim cache bank3 write back memory 1bit ECC multi error; */ + unsigned int vcWb32bEccErr : 1; /* * [14:14]victim cache bank3 write back memory 2bit ECC error; */ + unsigned int vcWb32bEccMerr : 1; /* * [15:15]victim cache bank3 write back memory 2bit ECC multi error; */ + unsigned int vcData01bEccErr : 1; /* * [16:16]victim cache bank0 data memory 1bit ECC error; */ + unsigned int vcData01bEccMerr : 1; /* * [17:17]victim cache bank0 data memory 1bit ECC multi error; */ + unsigned int vcData02bEccErr : 1; /* * [18:18]victim cache bank0 data memory 2bit ECC error; */ + unsigned int vcData02bEccMerr : 1; /* * [19:19]victim cache bank0 data memory 2bit ECC multi error; */ + unsigned int vcData11bEccErr : 1; /* * [20:20]victim cache bank1 data memory 1bit ECC error; */ + unsigned int vcData11bEccMerr : 1; /* * [21:21]victim cache bank1 data memory 1bit ECC multi error; */ + unsigned int vcData12bEccErr : 1; /* * [22:22]victim cache bank1 data memory 2bit ECC error; */ + unsigned int vcData12bEccMerr : 1; /* * [23:23]victim cache bank1 data memory 2bit ECC multi error; */ + unsigned int vcData21bEccErr : 1; /* * [24:24]victim cache bank2 data memory 1bit ECC error; */ + unsigned int vcData21bEccMerr : 1; /* * [25:25]victim cache bank2 data memory 1bit ECC multi error; */ + unsigned int vcData22bEccErr : 1; /* * [26:26]victim cache bank2 data memory 2bit ECC error; */ + unsigned int vcData22bEccMerr : 1; /* * [27:27]victim cache bank2 data memory 2bit ECC multi error; */ + unsigned int vcData31bEccErr : 1; /* * [28:28]victim cache bank3 data memory 1bit ECC error; */ + unsigned int vcData31bEccMerr : 1; /* * [29:29]victim cache bank3 data memory 1bit ECC multi error; */ + unsigned int vcData32bEccErr : 1; /* * [30:30]victim cache bank3 data memory 2bit ECC error; */ + unsigned int vcData32bEccMerr : 1; /* * [31:31]victim cache bank3 data memory 2bit ECC multi error; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VC_CACHE_ERR_U; + +/* ** + * Union name : SMMC_F_VC_CACHE_MASK + * @brief + * Description: + */ +typedef union tagUnSmmcFVcCacheMask { + struct tagStSmmcFVcCacheMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int vcData32bEccErrMask : 1; /* * [15:15] */ + unsigned int vcData31bEccErrMask : 1; /* * [14:14] */ + unsigned int vcData22bEccErrMask : 1; /* * [13:13] */ + unsigned int vcData21bEccErrMask : 1; /* * [12:12] */ + unsigned int vcData12bEccErrMask : 1; /* * [11:11] */ + unsigned int vcData11bEccErrMask : 1; /* * [10:10] */ + unsigned int vcData02bEccErrMask : 1; /* * [9:9] */ + unsigned int vcData01bEccErrMask : 1; /* * [8:8] */ + unsigned int vcWb32bEccErrMask : 1; /* * [7:7] */ + unsigned int vcWb31bEccErrMask : 1; /* * [6:6] */ + unsigned int vcWb22bEccErrMask : 1; /* * [5:5] */ + unsigned int vcWb21bEccErrMask : 1; /* * [4:4] */ + unsigned int vcWb12bEccErrMask : 1; /* * [3:3] */ + unsigned int vcWb11bEccErrMask : 1; /* * [2:2] */ + unsigned int vcWb02bEccErrMask : 1; /* * [1:1] */ + unsigned int vcWb01bEccErrMask : 1; /* * [0:0] */ +#else + unsigned int vcWb01bEccErrMask : 1; /* * [0:0] */ + unsigned int vcWb02bEccErrMask : 1; /* * [1:1] */ + unsigned int vcWb11bEccErrMask : 1; /* * [2:2] */ + unsigned int vcWb12bEccErrMask : 1; /* * [3:3] */ + unsigned int vcWb21bEccErrMask : 1; /* * [4:4] */ + unsigned int vcWb22bEccErrMask : 1; /* * [5:5] */ + unsigned int vcWb31bEccErrMask : 1; /* * [6:6] */ + unsigned int vcWb32bEccErrMask : 1; /* * [7:7] */ + unsigned int vcData01bEccErrMask : 1; /* * [8:8] */ + unsigned int vcData02bEccErrMask : 1; /* * [9:9] */ + unsigned int vcData11bEccErrMask : 1; /* * [10:10] */ + unsigned int vcData12bEccErrMask : 1; /* * [11:11] */ + unsigned int vcData21bEccErrMask : 1; /* * [12:12] */ + unsigned int vcData22bEccErrMask : 1; /* * [13:13] */ + unsigned int vcData31bEccErrMask : 1; /* * [14:14] */ + unsigned int vcData32bEccErrMask : 1; /* * [15:15] */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VC_CACHE_MASK_U; + +/* ** + * Union name : SMMC_F_VC_CACHE_ERR_INFO + * @brief + * Description: + */ +typedef union tagUnSmmcFVcCacheErrInfo { + struct tagStSmmcFVcCacheErrInfo { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int vcCacheErrInfo : 32; /* * [31:0][31:14]:reserved.If write back memory and data memory ECC error at + the same time, here capture write back memory.If multi bank memory ECC error, here + capture th e lowest bank.[13:12]: bank id. 2'b00: bank 0, 2'b01: bank 1, 2'b10: + bank 2, 2'b11: bank 3. [11]: information type. indicate which buffer memory has + ECC err or. 1'b0: write back memory; 1'b1: vc data memory; For victim cache wb + memory error:[10:8] reserved.[7] error type: 1'b0: 1-bit ECC error. 1'b1: + 2-bit ECC error.[6:2] memory access index;[1:0] The error 16B position in 64B. For + victim cache data memory error:[10] error type: 1'b0: 1-bit ECC error. 1' + b1: 2-bit ECC error.[9:2] memory access index;[1:0] The error 16B position in 64B. + */ +#else + unsigned int vcCacheErrInfo : 32; /* * [31:0][31:14]:reserved.If write back memory and data memory ECC error at + the same time, here capture write back memory.If multi bank memory ECC error, here + capture th e lowest bank.[13:12]: bank id. 2'b00: bank 0, 2'b01: bank 1, 2'b10: + bank 2, 2'b11: bank 3. [11]: information type. indicate which buffer memory has + ECC err or. 1'b0: write back memory; 1'b1: vc data memory; For victim cache wb + memory error:[10:8] reserved.[7] error type: 1'b0: 1-bit ECC error. 1'b1: + 2-bit ECC error.[6:2] memory access index;[1:0] The error 16B position in 64B. For + victim cache data memory error:[10] error type: 1'b0: 1-bit ECC error. 1' + b1: 2-bit ECC error.[9:2] memory access index;[1:0] The error 16B position in 64B. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VC_CACHE_ERR_INFO_U; + +/* ** + * Union name : SMMC_F_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmmcFIndrectCtrl { + struct tagStSmmcFIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smmcFIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smmcFIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int + smmcFIndirTab : 4; /* * [27:24]It specifies memory group or table. 4'd0: main cache tag memory;data + structure:{ecc_bit(9bit),occupy(1bit),valid_bit(8bit),dirty_bit(4bit),stick_bit(1bit),host_ + id(2bit),vf_id(10bit),gpa (56bit),o_bit(1bit),csize(2bit),tag_type(4bit),xid(40bit)}4'd1: + main cache data cache memory;4'd2: main cache VFA table;data structure + :{ecc_bit(7bit),pf_id(4bit),ft_enb(1bit),ft_pf_enb(1bit),rdma_enb(1bit),rdma_pf_enb(1bit),bat_ptr(18bit)}4'd3: + main cache recycle buffer;recycle buffer data str + ucture:{valid(1bit),head(1bit),tail(1bit),nxt_ptr(6),ready(1bit),early_retire(1bit),rf_done(1bit),cout_done(1bit),cla_bpc_flag(1bit),cla_entry_size(2bit),cla_xy + z(15bit),gpa_trans_flag(1bit),gpa_trans_lev(2bit),action_type(4),gpa_entry_idx(3),offset(6),tag_type(4bit),mem_idx_type(2bit),mem_idx(56bit),bank_id(2bit),cid0( + 10bit),cid1(10bit),acc_size(5bit),error_flag(1bit),cache_line_size(2bit),base_cache_line_size(2bit),original_offset(6bit),api_src(3bit),opcode(4bit),api_token(3 + 8bit),cache_base_addr(10bit),qu_st_ack(1bit)}4'd4: main cache miss cam;miss cam data + structure: {occp_cid_idx(1bit),occp_way_idx(4bit),evt_way_idx(4bit),mem_idx + _type(2bit),mem_idx(56bit),offset(6bit),tag_type(4bit),original_tag_type(4bit),host_id(2bit),vf_id(10bit),xid(40bit),original_bank_id(2bit),original_cid0(10bit) + ,original_cid1(10bit),cla_lev(2bit),tail(1bit)};4'd5: main cache engine store data + buffer;4'd6: main cache QU store data buffer;4'd7: main cache QU store data b uffer free + list; data structure:{tag_head_address, tag_tail_address,tag_used_addr_num}.4'd8: main cache + refill data buffer; data structure:{control information( 3bit),refill data(128)}.4'd9: + victim cache request information;data + structure:{req_vld(1),req_otstag(6),pcie_template(6),req_type(3),req_size(6),host_id(2),vf_i + d(10),gpa_ofst(64),lcid(2),rsv(2)}4'd10: victim cache tag memory;data + structure:{tag_vld(1),dirty(4),host_id(2),vf_id(10),gpa(56),xid(40),type(4),csize(2)}4'd11 + : victim cache data cache memory;4'd12: RTT latency counter;4'd13: virtual cache + configuration entries;4'd14: qu interface capture data flit AND smf refill erro r captured + information;refill error captured information data structure(83 bits in + total):{api_src(3),vf_id(10),api_opcode(4),api_tag_type(4),api_tag_sub_type(2 + bit，如果是qu的请求，不需要看sub_type),gpa_translation_flag(1), + gpa_translation_lev(2),api_mem_index(56),captured_info_valid(1)};4'd15:direct wqe service + type mapping table AND refill timeout otstanding tag index.data structure:1)the mapping + table are total 64bits. each 2bit are a group, bit[1:0] is corresponding to service type 0 + ,......bit[63:62] is corresponding to service type 31.bit[n+1 : n] = 2'b00, the service type + is L2NIC.bit[n+1 : n] = 2'b01, the service type is ROCE.bit[n+1 : n ] = 2'b10, the service + type is IWARP.2)refill timeout otstanding tag index:64bit, one bit corresponding to an + outstanding tag(bit0 corresponding to tag0; bit63 corresponding to tag63). when a tag is + timeout, the corresponding tag will be set, to inform SW which tag has encountered refill + timeout. The timeout tag will b e hanged up until the refill response return from host. */ + unsigned int + smmcFIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote + 0;以下软件间接访问的数据entry有些是大于32bit。软件写这些数据entry的时候需要发多次写操作，拼成一个完整的entry，然后由硬件一次写入memory中。硬件默认由entry的LSB开始写起（对应地址[2:0]=7）。软件读大于32b + it的entry时，对于一些较重要的控制信息在软件读地址[2:0]=7时，硬件锁存整个entry，后续读该entry时，从锁存寄存器中取。所以，综上所述，要求软件读/写以下数据时，地址[2:0]应该统一从7开始，由高到低依次操作。以下列出的memory的数据格式包含了ECC + bit，对于ECC bit，只可通过CSR间 接读；不可通过CSR间接写。It specifies memory address in one + group or internal address of the table.[20:3] memory access index field0) for main cache + tag memory[17:16] bank -ID[15] CID0/CID1 index type:1'b0:CID0;1'b1:CID1;[14:5] TAG memory + access index. In SMF mode,[14:5] is tag group (include 4 tags) index in a memory + way.[4 :3] tag num in a tag group0x0:0x2 - reserved 0x3: + data[159:128]([159:138]:reserved,[137:129]:ECC bit;[128]:tag data)0x4: data[127:96]0x5: + data[95:64]0x6: d ata[63:32]0x7: data[31:0] 1) for main cache data cache memory:[21:20] + bank-ID[19] data memory coreesponding to CID0/CID1:1'b0:corresponding to CID0;1'b1:corres + ponding to CID1;[18:7] memory access index. In SMF mode,[18:7] is 256Byte basic cache + line.[6:3] 16Byte data entry.0x0:0x2 - reserved 0x3: data[159:128] + ([159:137]:reserved,[136:128]:ECC bit)0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 2) for main cache VFA table memory[12:3] memory index [2:0] + word select field0x0:0x6 - reserved 0x7: data[31:0] ([31:26]:ECC bit;[25:0]:vfa data)3) + for main cache recycle buffer(only support for CSR read)[8:3] me mory access index.In SMF + mode, it's corresponding to 64 outstandings;[2:0] word select field0x0: reserved 0x1: + data[223:192]0x2: data[191:160]0x3: data[159 :128]0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 4) for main cache miss cam(only support for CSR read)[8:3] + memory access index.In SMF mode, it's corresponding to 64 outstandings;[2:0] word select + field0x0:0x2 - reserved 0x3: data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x 7: data[31:0] 5) for main cache engine store data buffer(only support for + CSR read)[12] memory id: 0:stb0; 1:stb1;[11:6] memory access index.In SMF mod e, + it's in the unit of 64Byte, and corresponding to 64 outstandings;[5:3] 16Byte data entry + index in a 64Byte store data; When 0x4, indicate to access 1bit dir ty and 64bit byte + enable.[2:0] word select field0x0:0x2 - reserved0x3: data[159:128] 0x4: data[127:96]0x5: + data[95:64]0x6: data[63:32]0x7: data[31:0] 6) f or main cache QU store data buffer(only + support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte, + and includes 256 of 64byte; [4: 3] 16Byte data entry index in a 64Byte data.[2:0] word + select field0x0:0x2 - reserved 0x3: data[159:128]([159:137]:reserved,[136:128]:ECC + bit)0x4: data[127: 96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0]7) for mainc cache + QU store data buffer list(only support for CSR read)[8:3] memory access index.[2:0] wor d + select field0x0:0x6 - reserved 0x7: data[31:0] 8) for main cache refill data buffer(only + support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte, + and includes 256 of 64byte; [4:3] 16Byte data entry index in a 64Byte data.[2:0] word + select field0x0:0x2 - reserved 0x3: data[159:128]( [159:140]:reserved,[139:131]:ECC + bit,[130:129]:refill buffer entry control data)0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 9) victim c ache request information (only support for CSR + read)[4:3] victim cache bank ID;[2:0] word select field0x0:0x3 - reserved 0x4: + data[127:96]0x5: data[95:64]0x6 : data[63:32]0x7: data[31:0] 10) victim cache tag + memory(only support for CSR read,and CSR write + clear.注意CSR写清时，要没有writeback流量，否则可能造成错误。例如1KB的cacheline占4个256B + ，当逻辑写了2个256B时，CSR发起清操作，前面2个256B会被清掉，但后面2个256B不清。)[10:9] + victim cache bank ID.[8:3] memory access index.In SMF mode, there are 32 tags in each + victim cache.[2:0] word select field0x0:0x3 - reserved 0x4: data[127:96]0x5: + data[95:64]0x6: data[63:32]0x7: data[31:0] 11) victim cache data cache memory(only + support for C SR read)[14:13] victim cache bank ID.[12:7] the memory access index. In SMF + mode, the victim cache is 256Byte in width.[6:3] the index number of eache 16Byte in + 256Byte of cache line.[2:0] word select field0x0:0x2 - reserved 0x3: data[159:128] 0x4: + data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] 12) R TT latency + counter(only support for CSR read)[3] select which counter to read:1'b1: longest letency + counter. 1'b0: shortest letency counter. [2:0] word select field0x0~5: reserved.0x6: + counter[47:32].0x7: counter[31:0].13) virtual cache configuration entries[5:3] virtual + cache configuration entry number:3'd0: QU virtu al configure entry 0(RDMA parent + context).3'd1: QU virtual configure entry 1(flow based parent context).3'd2: QU virtual + configure entry 2(child context).3'd3: Direct WQE virtual configure entry 0(L2 NIC direct + WQE).3'd4: Direct WQE virtual configure entry 1(ROCE direct WQE).3'd5: Direct WQE virtual + configure entry 2(I WARP direct WQE).3'd6: CLA virtual configure entry.3'd7: MBaseAddr + configure [2:0] word select field0x0~6: reserved.0x7: entry data[31:0].14) qu interface + capt ure data flit[4:3]: qu interface capture data entry number 2'b00: first captured + data flit sent from QU to SMMC_F; 2'b01: first captured data flit sent from SMMC_F to + QU; 2'b10: refill error captured information;[2:0] word select field(Note:for refill + error captured information, word select field ONLY use 0x5~0x7,0x0~0x4 is reserved)0x0:0x2 + - reserved 0x3: data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: + data[31:0] 15) service type mapping table AND refill timeout outstanding tag index.[3]: + register entry select field1'b0: service type mapping table;1'b1: refill timeout + outstanding tag index (only support for CSR read).[2:0] word select field0x0:0x5 - + reserved 0x6: data[63:32]0x7: data[31:0] + */ +#else + unsigned int + smmcFIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote + 0;以下软件间接访问的数据entry有些是大于32bit。软件写这些数据entry的时候需要发多次写操作，拼成一个完整的entry，然后由硬件一次写入memory中。硬件默认由entry的LSB开始写起（对应地址[2:0]=7）。软件读大于32b + it的entry时，对于一些较重要的控制信息在软件读地址[2:0]=7时，硬件锁存整个entry，后续读该entry时，从锁存寄存器中取。所以，综上所述，要求软件读/写以下数据时，地址[2:0]应该统一从7开始，由高到低依次操作。以下列出的memory的数据格式包含了ECC + bit，对于ECC bit，只可通过CSR间 接读；不可通过CSR间接写。It specifies memory address in one + group or internal address of the table.[20:3] memory access index field0) for main cache + tag memory[17:16] bank -ID[15] CID0/CID1 index type:1'b0:CID0;1'b1:CID1;[14:5] TAG memory + access index. In SMF mode,[14:5] is tag group (include 4 tags) index in a memory + way.[4 :3] tag num in a tag group0x0:0x2 - reserved 0x3: + data[159:128]([159:138]:reserved,[137:129]:ECC bit;[128]:tag data)0x4: data[127:96]0x5: + data[95:64]0x6: d ata[63:32]0x7: data[31:0] 1) for main cache data cache memory:[21:20] + bank-ID[19] data memory coreesponding to CID0/CID1:1'b0:corresponding to CID0;1'b1:corres + ponding to CID1;[18:7] memory access index. In SMF mode,[18:7] is 256Byte basic cache + line.[6:3] 16Byte data entry.0x0:0x2 - reserved 0x3: data[159:128] + ([159:137]:reserved,[136:128]:ECC bit)0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 2) for main cache VFA table memory[12:3] memory index [2:0] + word select field0x0:0x6 - reserved 0x7: data[31:0] ([31:26]:ECC bit;[25:0]:vfa data)3) + for main cache recycle buffer(only support for CSR read)[8:3] me mory access index.In SMF + mode, it's corresponding to 64 outstandings;[2:0] word select field0x0: reserved 0x1: + data[223:192]0x2: data[191:160]0x3: data[159 :128]0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 4) for main cache miss cam(only support for CSR read)[8:3] + memory access index.In SMF mode, it's corresponding to 64 outstandings;[2:0] word select + field0x0:0x2 - reserved 0x3: data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x 7: data[31:0] 5) for main cache engine store data buffer(only support for + CSR read)[12] memory id: 0:stb0; 1:stb1;[11:6] memory access index.In SMF mod e, + it's in the unit of 64Byte, and corresponding to 64 outstandings;[5:3] 16Byte data entry + index in a 64Byte store data; When 0x4, indicate to access 1bit dir ty and 64bit byte + enable.[2:0] word select field0x0:0x2 - reserved0x3: data[159:128] 0x4: data[127:96]0x5: + data[95:64]0x6: data[63:32]0x7: data[31:0] 6) f or main cache QU store data buffer(only + support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte, + and includes 256 of 64byte; [4: 3] 16Byte data entry index in a 64Byte data.[2:0] word + select field0x0:0x2 - reserved 0x3: data[159:128]([159:137]:reserved,[136:128]:ECC + bit)0x4: data[127: 96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0]7) for mainc cache + QU store data buffer list(only support for CSR read)[8:3] memory access index.[2:0] wor d + select field0x0:0x6 - reserved 0x7: data[31:0] 8) for main cache refill data buffer(only + support for CSR read)[12:5] memory access index.In SMF mode, it's in the unit of 64Byte, + and includes 256 of 64byte; [4:3] 16Byte data entry index in a 64Byte data.[2:0] word + select field0x0:0x2 - reserved 0x3: data[159:128]( [159:140]:reserved,[139:131]:ECC + bit,[130:129]:refill buffer entry control data)0x4: data[127:96]0x5: data[95:64]0x6: + data[63:32]0x7: data[31:0] 9) victim c ache request information (only support for CSR + read)[4:3] victim cache bank ID;[2:0] word select field0x0:0x3 - reserved 0x4: + data[127:96]0x5: data[95:64]0x6 : data[63:32]0x7: data[31:0] 10) victim cache tag + memory(only support for CSR read,and CSR write + clear.注意CSR写清时，要没有writeback流量，否则可能造成错误。例如1KB的cacheline占4个256B + ，当逻辑写了2个256B时，CSR发起清操作，前面2个256B会被清掉，但后面2个256B不清。)[10:9] + victim cache bank ID.[8:3] memory access index.In SMF mode, there are 32 tags in each + victim cache.[2:0] word select field0x0:0x3 - reserved 0x4: data[127:96]0x5: + data[95:64]0x6: data[63:32]0x7: data[31:0] 11) victim cache data cache memory(only + support for C SR read)[14:13] victim cache bank ID.[12:7] the memory access index. In SMF + mode, the victim cache is 256Byte in width.[6:3] the index number of eache 16Byte in + 256Byte of cache line.[2:0] word select field0x0:0x2 - reserved 0x3: data[159:128] 0x4: + data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: data[31:0] 12) R TT latency + counter(only support for CSR read)[3] select which counter to read:1'b1: longest letency + counter. 1'b0: shortest letency counter. [2:0] word select field0x0~5: reserved.0x6: + counter[47:32].0x7: counter[31:0].13) virtual cache configuration entries[5:3] virtual + cache configuration entry number:3'd0: QU virtu al configure entry 0(RDMA parent + context).3'd1: QU virtual configure entry 1(flow based parent context).3'd2: QU virtual + configure entry 2(child context).3'd3: Direct WQE virtual configure entry 0(L2 NIC direct + WQE).3'd4: Direct WQE virtual configure entry 1(ROCE direct WQE).3'd5: Direct WQE virtual + configure entry 2(I WARP direct WQE).3'd6: CLA virtual configure entry.3'd7: MBaseAddr + configure [2:0] word select field0x0~6: reserved.0x7: entry data[31:0].14) qu interface + capt ure data flit[4:3]: qu interface capture data entry number 2'b00: first captured + data flit sent from QU to SMMC_F; 2'b01: first captured data flit sent from SMMC_F to + QU; 2'b10: refill error captured information;[2:0] word select field(Note:for refill + error captured information, word select field ONLY use 0x5~0x7,0x0~0x4 is reserved)0x0:0x2 + - reserved 0x3: data[159:128]0x4: data[127:96]0x5: data[95:64]0x6: data[63:32]0x7: + data[31:0] 15) service type mapping table AND refill timeout outstanding tag index.[3]: + register entry select field1'b0: service type mapping table;1'b1: refill timeout + outstanding tag index (only support for CSR read).[2:0] word select field0x0:0x5 - + reserved 0x6: data[63:32]0x7: data[31:0] + */ + unsigned int + smmcFIndirTab : 4; /* * [27:24]It specifies memory group or table. 4'd0: main cache tag memory;data + structure:{ecc_bit(9bit),occupy(1bit),valid_bit(8bit),dirty_bit(4bit),stick_bit(1bit),host_ + id(2bit),vf_id(10bit),gpa (56bit),o_bit(1bit),csize(2bit),tag_type(4bit),xid(40bit)}4'd1: + main cache data cache memory;4'd2: main cache VFA table;data structure + :{ecc_bit(7bit),pf_id(4bit),ft_enb(1bit),ft_pf_enb(1bit),rdma_enb(1bit),rdma_pf_enb(1bit),bat_ptr(18bit)}4'd3: + main cache recycle buffer;recycle buffer data str + ucture:{valid(1bit),head(1bit),tail(1bit),nxt_ptr(6),ready(1bit),early_retire(1bit),rf_done(1bit),cout_done(1bit),cla_bpc_flag(1bit),cla_entry_size(2bit),cla_xy + z(15bit),gpa_trans_flag(1bit),gpa_trans_lev(2bit),action_type(4),gpa_entry_idx(3),offset(6),tag_type(4bit),mem_idx_type(2bit),mem_idx(56bit),bank_id(2bit),cid0( + 10bit),cid1(10bit),acc_size(5bit),error_flag(1bit),cache_line_size(2bit),base_cache_line_size(2bit),original_offset(6bit),api_src(3bit),opcode(4bit),api_token(3 + 8bit),cache_base_addr(10bit),qu_st_ack(1bit)}4'd4: main cache miss cam;miss cam data + structure: {occp_cid_idx(1bit),occp_way_idx(4bit),evt_way_idx(4bit),mem_idx + _type(2bit),mem_idx(56bit),offset(6bit),tag_type(4bit),original_tag_type(4bit),host_id(2bit),vf_id(10bit),xid(40bit),original_bank_id(2bit),original_cid0(10bit) + ,original_cid1(10bit),cla_lev(2bit),tail(1bit)};4'd5: main cache engine store data + buffer;4'd6: main cache QU store data buffer;4'd7: main cache QU store data b uffer free + list; data structure:{tag_head_address, tag_tail_address,tag_used_addr_num}.4'd8: main cache + refill data buffer; data structure:{control information( 3bit),refill data(128)}.4'd9: + victim cache request information;data + structure:{req_vld(1),req_otstag(6),pcie_template(6),req_type(3),req_size(6),host_id(2),vf_i + d(10),gpa_ofst(64),lcid(2),rsv(2)}4'd10: victim cache tag memory;data + structure:{tag_vld(1),dirty(4),host_id(2),vf_id(10),gpa(56),xid(40),type(4),csize(2)}4'd11 + : victim cache data cache memory;4'd12: RTT latency counter;4'd13: virtual cache + configuration entries;4'd14: qu interface capture data flit AND smf refill erro r captured + information;refill error captured information data structure(83 bits in + total):{api_src(3),vf_id(10),api_opcode(4),api_tag_type(4),api_tag_sub_type(2 + bit，如果是qu的请求，不需要看sub_type),gpa_translation_flag(1), + gpa_translation_lev(2),api_mem_index(56),captured_info_valid(1)};4'd15:direct wqe service + type mapping table AND refill timeout otstanding tag index.data structure:1)the mapping + table are total 64bits. each 2bit are a group, bit[1:0] is corresponding to service type 0 + ,......bit[63:62] is corresponding to service type 31.bit[n+1 : n] = 2'b00, the service type + is L2NIC.bit[n+1 : n] = 2'b01, the service type is ROCE.bit[n+1 : n ] = 2'b10, the service + type is IWARP.2)refill timeout otstanding tag index:64bit, one bit corresponding to an + outstanding tag(bit0 corresponding to tag0; bit63 corresponding to tag63). when a tag is + timeout, the corresponding tag will be set, to inform SW which tag has encountered refill + timeout. The timeout tag will b e hanged up until the refill response return from host. */ + unsigned int smmcFIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smmcFIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smmcFIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INDRECT_CTRL_U; + +/* ** + * Union name : SMMC_F_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmmcFIndrectTimeout { + struct tagStSmmcFIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smmcFIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMMC_F_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmmcFIndrectData { + struct tagStSmmcFIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smmcFIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_INDRECT_DATA_U; + +/* ** + * Union name : SMMC_F_MC_CNT_ENB + * @brief counter enable + * Description: + */ +typedef union tagUnSmmcFMcCntEnb { + struct tagStSmmcFMcCntEnb { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 24; /* * [31:8]reserved. */ + unsigned int smmcFMcCntEnb : 8; /* * [7:0]SMMC main cache counter enable.1'b0: disable SMMC counter.1'b1: enable + * SMMC counter. + */ +#else + unsigned int smmcFMcCntEnb : 8; /* * [7:0]SMMC main cache counter enable.1'b0: disable SMMC counter.1'b1: enable + * SMMC counter. + */ + unsigned int reserved : 24; /* * [31:8]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_ENB_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0 + * @brief counter event selection enable + * Description: + */ +typedef union tagUnSmmcFMcCntEventSelEnbGrp0 { + struct tagStSmmcFMcCntEventSelEnbGrp0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFMcCntEventSelEnb3 : 8; /* * [31:24]SMMC counter3 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb2 : 8; /* * [23:16]SMMC counter2 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb1 : 8; /* * [15:8]SMMC counter1 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb0 : 8; /* * [7:0]SMMC counter0 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ +#else + unsigned int smmcFMcCntEventSelEnb0 : 8; /* * [7:0]SMMC counter0 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb1 : 8; /* * [15:8]SMMC counter1 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb2 : 8; /* * [23:16]SMMC counter2 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb3 : 8; /* * [31:24]SMMC counter3 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1 + * @brief counter event selection enable + * Description: + */ +typedef union tagUnSmmcFMcCntEventSelEnbGrp1 { + struct tagStSmmcFMcCntEventSelEnbGrp1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFMcCntEventSelEnb7 : 8; /* * [31:24]SMMC counter7 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb6 : 8; /* * [23:16]SMMC counter6 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb5 : 8; /* * [15:8]SMMC counter5 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb4 : 8; /* * [7:0]SMMC counter4 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ +#else + unsigned int smmcFMcCntEventSelEnb4 : 8; /* * [7:0]SMMC counter4 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb5 : 8; /* * [15:8]SMMC counter5 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb6 : 8; /* * [23:16]SMMC counter6 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ + unsigned int smmcFMcCntEventSelEnb7 : 8; /* * [31:24]SMMC counter7 event configuration enable.If one bit of this + signal is valid, the corresponding event is valid. And counter0 is + configured to counter these corre ponding events.A counter can be + configured by 8 events at most:7: reserved;6: reserved;5: reserved;4: API + type;3: command source;2: bank-ID;1: tag type;0: VF-ID + ; */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL0 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel0 { + struct tagStSmmcFMcCntEventSel0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel0UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel0EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel0ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel0ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel0BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel0TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel0VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel0VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel0TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel0BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel0ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel0ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel0EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel0UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL0_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL1 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel1 { + struct tagStSmmcFMcCntEventSel1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel1UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel1EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel1ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel1ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel1BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel1TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel1VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel1VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel1TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel1BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel1ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel1ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel1EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel1UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL1_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL2 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel2 { + struct tagStSmmcFMcCntEventSel2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel2UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel2EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel2ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel2ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel2BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel2TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel2VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel2VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel2TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel2BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel2ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel2ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel2EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel2UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL2_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL3 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel3 { + struct tagStSmmcFMcCntEventSel3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel3UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel3EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel3ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel3ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel3BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel3TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel3VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel3VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel3TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel3BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel3ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel3ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel3EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel3UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL3_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL4 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel4 { + struct tagStSmmcFMcCntEventSel4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel4UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel4EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel4ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel4ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel4BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel4TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel4VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel4VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel4TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel4BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel4ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel4ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel4EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel4UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL4_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL5 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel5 { + struct tagStSmmcFMcCntEventSel5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel5UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel5EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel5ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel5ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel5BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel5TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel5VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel5VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel5TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel5BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel5ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel5ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel5EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel5UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL5_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL6 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel6 { + struct tagStSmmcFMcCntEventSel6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel6UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel6EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel6ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel6ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel6BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel6TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel6VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel6VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel6TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel6BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel6ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel6ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel6EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel6UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL6_U; + +/* ** + * Union name : SMMC_F_MC_CNT_EVENT_SEL7 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCntEventSel7 { + struct tagStSmmcFMcCntEventSel7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int mcCntEventSel7UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ + unsigned int + mcCntEventSel7EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel7ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int mcCntEventSel7ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel7BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel7TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel7VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ +#else + unsigned int mcCntEventSel7VfId : 10; /* * [9:0]VF-IDConfigure which VF to count for. If enabled, the counter + * only counts for requests belong to a specific VF_ID. + */ + unsigned int reserved : 5; /* * [14:10]reserved */ + unsigned int mcCntEventSel7TagType : 4; /* * [18:15]tag typeConfigure which types of table in cache to count + * for. If enabled, the counter only counts for requests that accessing + * a specific type of table. + */ + unsigned int mcCntEventSel7BankId : 2; /* * [20:19]bank-ID.Configure which bank of cache to count for. If + enabled, the counter only counts for requests in a specific bank.2’b00: + bank0;2’b01: bank1;2’b10: bank2;2 ’b11: bank3; */ + unsigned int mcCntEventSel7ReqSrc : 3; /* * [23:21]Configure which source of requests to count for. If enabled, + the counter only counts for requests that come from a specific + source.3’b000: SMLC0;3’b001: SMLC1;3 + ’b010: SMLC2;3’b011: SMLC3;3’b100: QU;3’b101: direct WQE; */ + unsigned int mcCntEventSel7ApiType : 4; /* * [27:24]Configure which type of request to count for. If enabled, + the counter only counts for a specific type of request.4'b0000 normal + load4'b0001 normal store4'b0010 load no return4'b0011 load no refill4'b0100 + store no refill4'b0101 cache invalid4'b0110 cache out4'b0111 load + memory4'b1000 store memory4'b1001 load bpc4'b1010 store bpc */ + unsigned int + mcCntEventSel7EventType : 3; /* * [30:28]Configure which type of event to count for. If enable, the counter + only counts for a specific type of event. This field must be configured enable, + when a counte r is enabled. 3’b000: 统计SMMC收到的API个数Count for requests number + that SMMC receives.3’b001: 统计API在SMMC中处理的圈数，每圈14~16个cycle。Count for + the times of requests (from QU /engine/CPI/RCB) scheduled into the main cache + pipeline. For a whole request from engine or QU, it may be scheduled into the main + cache pipeline for several tim es, until it is done.3’b010: 统计SMMC中cache + miss的API个数（只要在API处理过程中有一次从CPI回来的refill操作，就认为cache + miss）。Count for how many requests have encounter cache miss.3’b011: 统计main + cache向victim cache发起refill请求的次数（包括GPA转换过程中refill CLA表）。Count for + the number that main cache issues refill requests to victim cache.3’b100: 统计main + cache从C PI收到refill response的次数（默认），或者统计refill data + size（以64Byte为单位）。Count for the number of refill response from CPI to SMMC. + It can be counted in the unit of times or in the unit of (64byte).3’b101: 统计main + cache向victim cache发起write back操作的次数（默认以cache line + 为单位），或者统计write back data size（以64Byte为单位）。Count for the number of + evict ing from main cache to victim cache. It can be counted in the unit of times + or in the unit of (64byte).3’b110: 统计cache miss后在main + cache中占不到way的次数（包括GPA转换过程中占不到w ay）。Count for the number when a + request encounter cache miss, but can't occupy a cache way.3’b111: 统计在main + cache中first issue就Hit的API个数。Counter for the number of + requests that cache hit and finish in the first issue loop. */ + unsigned int mcCntEventSel7UnitType : 1; /* * [31:31]The unit of the counter. This field must be configured to + enable.1’b0: in the unit of times;1’b1: in the unit of 64Byte(Note:only + used to count refill or write back data size); */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CNT_EVENT_SEL7_U; + +/* ** + * Union name : SMMC_F_MC_STATUS + * @brief + * Description: + */ +typedef union tagUnSmmcFMcStatus { + struct tagStSmmcFMcStatus { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11] */ + unsigned int smmcRfTimeout : 1; /* * [10:10]indicate there is outstanding tag timeout in SMMC, when refill data + from CPI. This signal could not tell which outstanding tag is timeout in SMMC. SW + should rea d RCB of each outstanding tag to check out which outstanding tag is + timeout. */ + unsigned int quTxFlitCtpDone : 1; /* * [9:9]QU transmit data flit capture done. When this signal is valid, SW + * can read captured data flit via CSR.1: capture done;0: capturing; + */ + unsigned int quRxFlitCtpDone : 1; /* * [8:8]QU received data flit capture done. When this signal is valid, SW + * can read captured data flit via CSR.1: capture done;0: capturing; + */ + unsigned int mcFreeTagNum : 7; /* * [7:1]the free outstanding tag number in SMMC */ + unsigned int mcInitDone : 1; /* * [0:0]smmc initial done signal.1: initial done;0: in initial processing or have + * not started initial processing. + */ +#else + unsigned int mcInitDone : 1; /* * [0:0]smmc initial done signal.1: initial done;0: in initial processing or have + * not started initial processing. + */ + unsigned int mcFreeTagNum : 7; /* * [7:1]the free outstanding tag number in SMMC */ + unsigned int quRxFlitCtpDone : 1; /* * [8:8]QU received data flit capture done. When this signal is valid, SW + * can read captured data flit via CSR.1: capture done;0: capturing; + */ + unsigned int quTxFlitCtpDone : 1; /* * [9:9]QU transmit data flit capture done. When this signal is valid, SW + * can read captured data flit via CSR.1: capture done;0: capturing; + */ + unsigned int smmcRfTimeout : 1; /* * [10:10]indicate there is outstanding tag timeout in SMMC, when refill data + from CPI. This signal could not tell which outstanding tag is timeout in SMMC. SW + should rea d RCB of each outstanding tag to check out which outstanding tag is + timeout. */ + unsigned int reserved : 21; /* * [31:11] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_STATUS_U; + +/* ** +* Union name : SMMC_F_MC_CNT0 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB0 and SMMC_F_MC_CNT_EVENT_SEL0. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt0 { + struct tagStSmmcFMcCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt0 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt0 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT0_U; + +/* ** +* Union name : SMMC_F_MC_CNT1 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB1 and SMMC_F_MC_CNT_EVENT_SEL1. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt1 { + struct tagStSmmcFMcCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt1 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt1 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT1_U; + +/* ** +* Union name : SMMC_F_MC_CNT2 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB2 and SMMC_F_MC_CNT_EVENT_SEL2. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt2 { + struct tagStSmmcFMcCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt2 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt2 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT2_U; + +/* ** +* Union name : SMMC_F_MC_CNT3 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB3 and SMMC_F_MC_CNT_EVENT_SEL3. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt3 { + struct tagStSmmcFMcCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt3 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt3 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT3_U; + +/* ** +* Union name : SMMC_F_MC_CNT4 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB4 and SMMC_F_MC_CNT_EVENT_SEL4. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt4 { + struct tagStSmmcFMcCnt4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt4 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt4 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT4_U; + +/* ** +* Union name : SMMC_F_MC_CNT5 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB5 and SMMC_F_MC_CNT_EVENT_SEL5. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt5 { + struct tagStSmmcFMcCnt5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt5 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt5 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT5_U; + +/* ** +* Union name : SMMC_F_MC_CNT6 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB6 and SMMC_F_MC_CNT_EVENT_SEL6. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt6 { + struct tagStSmmcFMcCnt6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt6 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt6 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT6_U; + +/* ** +* Union name : SMMC_F_MC_CNT7 +* @brief This SMMC main cache counter0 register is a dynamic counter to count any event that is configured +by SMMC_F_MC_CNT_EVENT_SEL_ENB7 and SMMC_F_MC_CNT_EVENT_SEL7. + +* Description: +*/ +typedef union tagUnSmmcFMcCnt7 { + struct tagStSmmcFMcCnt7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long smmcFMcCnt7 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ +#else + unsigned long long smmcFMcCnt7 : 48; /* * [47:0]This can be programmed to count any event depeding on the + configuration. */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_SMMC_F_MC_CNT7_U; + +/* ** + * Union name : SMMC_F_VC_FIFO_DEPTH0 + * @brief SMMC_F victim cache FIFO depth or credit + * Description: + */ +typedef union tagUnSmmcFVcFifoDepth0 { + struct tagStSmmcFVcFifoDepth0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int vc3WbCtrlFifoDepth : 3; /* * [31:29]Bank3 victim cache write back control fifo real depth. */ + unsigned int vc2WbCtrlFifoDepth : 3; /* * [28:26]Bank2 victim cache write back control fifo real depth. */ + unsigned int vc1WbCtrlFifoDepth : 3; /* * [25:23]Bank1 victim cache write back control fifo real depth. */ + unsigned int vc0WbCtrlFifoDepth : 3; /* * [22:20]Bank0 victim cache write back control fifo real depth.The write + * back control fifo is between MC and VC, the total depth is 6. + */ + unsigned int vc3WbDataFifoDepth : 5; /* * [19:15]Bank3 victim cache write back data fifo real depth. */ + unsigned int vc2WbDataFifoDepth : 5; /* * [14:10]Bank2 victim cache write back data fifo real depth. */ + unsigned int vc1WbDataFifoDepth : 5; /* * [9:5]Bank1 victim cache write back data fifo real depth. */ + unsigned int vc0WbDataFifoDepth : 5; /* * [4:0]Bank0 victim cache write back data fifo real depth.The write back + * data fifo is between MC and VC, the total depth is 24. The data fifo + * contain 24 x64B. + */ +#else + unsigned int vc0WbDataFifoDepth : 5; /* * [4:0]Bank0 victim cache write back data fifo real depth.The write back + * data fifo is between MC and VC, the total depth is 24. The data fifo + * contain 24 x64B. + */ + unsigned int vc1WbDataFifoDepth : 5; /* * [9:5]Bank1 victim cache write back data fifo real depth. */ + unsigned int vc2WbDataFifoDepth : 5; /* * [14:10]Bank2 victim cache write back data fifo real depth. */ + unsigned int vc3WbDataFifoDepth : 5; /* * [19:15]Bank3 victim cache write back data fifo real depth. */ + unsigned int vc0WbCtrlFifoDepth : 3; /* * [22:20]Bank0 victim cache write back control fifo real depth.The write + * back control fifo is between MC and VC, the total depth is 6. + */ + unsigned int vc1WbCtrlFifoDepth : 3; /* * [25:23]Bank1 victim cache write back control fifo real depth. */ + unsigned int vc2WbCtrlFifoDepth : 3; /* * [28:26]Bank2 victim cache write back control fifo real depth. */ + unsigned int vc3WbCtrlFifoDepth : 3; /* * [31:29]Bank3 victim cache write back control fifo real depth. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VC_FIFO_DEPTH0_U; + +/* ** + * Union name : SMMC_F_VC_FIFO_DEPTH1 + * @brief SMMC_F victim cache FIFO depth or credit + * Description: + */ +typedef union tagUnSmmcFVcFifoDepth1 { + struct tagStSmmcFVcFifoDepth1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 7; /* * [31:25] */ + unsigned int vcCrdtFromSmit : 3; /* * [24:22]credit counter from SMIT.The initial value is 6. */ + unsigned int smxtfFifoDepth : 6; /* * [21:16]smxt interface fifo.The fifo total depth is 32. */ + unsigned int vc3DataFifoDepth : 2; /* * [15:14]Bank3 victim cache data fifo real depth. */ + unsigned int vc2DataFifoDepth : 2; /* * [13:12]Bank2 victim cache data fifo real depth. */ + unsigned int vc1DataFifoDepth : 2; /* * [11:10]Bank1 victim cache data fifo real depth. */ + unsigned int vc0DataFifoDepth : 2; /* * [9:8]Bank0 victim cache data fifo real depth.This fifo is between each + vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are + muxed to 1 input i nto smxt_intf. */ + unsigned int vc3CtrlFifoDepth : 2; /* * [7:6]Bank3 victim cache control fifo real depth. */ + unsigned int vc2CtrlFifoDepth : 2; /* * [5:4]Bank2 victim cache control fifo real depth. */ + unsigned int vc1CtrlFifoDepth : 2; /* * [3:2]Bank1 victim cache control fifo real depth. */ + unsigned int vc0CtrlFifoDepth : 2; /* * [1:0]Bank0 victim cache control fifo real depth.This fifo is between + each vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are + muxed to 1 inpu t into smxt_intf. */ +#else + unsigned int vc0CtrlFifoDepth : 2; /* * [1:0]Bank0 victim cache control fifo real depth.This fifo is between + each vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are + muxed to 1 inpu t into smxt_intf. */ + unsigned int vc1CtrlFifoDepth : 2; /* * [3:2]Bank1 victim cache control fifo real depth. */ + unsigned int vc2CtrlFifoDepth : 2; /* * [5:4]Bank2 victim cache control fifo real depth. */ + unsigned int vc3CtrlFifoDepth : 2; /* * [7:6]Bank3 victim cache control fifo real depth. */ + unsigned int vc0DataFifoDepth : 2; /* * [9:8]Bank0 victim cache data fifo real depth.This fifo is between each + vc and smxt_intf. The fifo total depth is 2. vc0/1/2/3 ctrl_fifo output are + muxed to 1 input i nto smxt_intf. */ + unsigned int vc1DataFifoDepth : 2; /* * [11:10]Bank1 victim cache data fifo real depth. */ + unsigned int vc2DataFifoDepth : 2; /* * [13:12]Bank2 victim cache data fifo real depth. */ + unsigned int vc3DataFifoDepth : 2; /* * [15:14]Bank3 victim cache data fifo real depth. */ + unsigned int smxtfFifoDepth : 6; /* * [21:16]smxt interface fifo.The fifo total depth is 32. */ + unsigned int vcCrdtFromSmit : 3; /* * [24:22]credit counter from SMIT.The initial value is 6. */ + unsigned int reserved : 7; /* * [31:25] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_VC_FIFO_DEPTH1_U; + +/* ** + * Union name : SMMC_F_MC_FIFO1_DEPTH + * @brief SMMC_F main cache FIFO depth or credit + * Description: + */ +typedef union tagUnSmmcFMcFifo1Depth { + struct tagStSmmcFMcFifo1Depth { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 3; /* * [31:29] */ + unsigned int lrb2FifoDepth : 5; /* * [28:24]lrb2 fifo real depth. */ + unsigned int lrb1FifoDepth : 5; /* * [23:19]lrb1 fifo real depth. */ + unsigned int lrb0FifoDepth : 5; /* * [18:14]lrb0 fifo real depth. */ + unsigned int quDataFifoDepth : 6; /* * [13:8]QU data fifo real depth. */ + unsigned int quCmdFifoDepth : 4; /* * [7:4]QU command fifo real depth. */ + unsigned int dataCreditFromQu : 4; /* * [3:0]data credit from QU. */ +#else + unsigned int dataCreditFromQu : 4; /* * [3:0]data credit from QU. */ + unsigned int quCmdFifoDepth : 4; /* * [7:4]QU command fifo real depth. */ + unsigned int quDataFifoDepth : 6; /* * [13:8]QU data fifo real depth. */ + unsigned int lrb0FifoDepth : 5; /* * [18:14]lrb0 fifo real depth. */ + unsigned int lrb1FifoDepth : 5; /* * [23:19]lrb1 fifo real depth. */ + unsigned int lrb2FifoDepth : 5; /* * [28:24]lrb2 fifo real depth. */ + unsigned int reserved : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_FIFO1_DEPTH_U; + +/* ** + * Union name : SMMC_F_MC_FIFO2_DEPTH + * @brief SMMC_F main cache FIFO depth + * Description: + */ +typedef union tagUnSmmcFMcFifo2Depth { + struct tagStSmmcFMcFifo2Depth { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 1; /* * [31:31] */ + unsigned int quStoreBufferDepth : 9; /* * [30:22]QU store buffer real depth. */ + unsigned int rfbufCredit : 9; /* * [21:13]refill buffer credit.The initial value is 0x100, indicate 256 64B + credit. */ + unsigned int lrb3FifoDepth : 5; /* * [12:8]lrb3 fifo real depth. */ + unsigned int quStoreBufferBp : 1; /* * [7:7]QU store buffer backpressure. */ + unsigned int quReturnFifoBp : 1; /* * [6:6]QU return fifo backpressure. */ + unsigned int quReturnFifoDepth : 6; /* * [5:0]QU return fifo real depth. */ +#else + unsigned int quReturnFifoDepth : 6; /* * [5:0]QU return fifo real depth. */ + unsigned int quReturnFifoBp : 1; /* * [6:6]QU return fifo backpressure. */ + unsigned int quStoreBufferBp : 1; /* * [7:7]QU store buffer backpressure. */ + unsigned int lrb3FifoDepth : 5; /* * [12:8]lrb3 fifo real depth. */ + unsigned int rfbufCredit : 9; /* * [21:13]refill buffer credit.The initial value is 0x100, indicate 256 64B + credit. */ + unsigned int quStoreBufferDepth : 9; /* * [30:22]QU store buffer real depth. */ + unsigned int reserved : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_FIFO2_DEPTH_U; + +/* ** + * Union name : SMMC_F_ERR_INJ + * @brief + * Description: + */ +typedef union tagUnSmmcFErrInj { + struct tagStSmmcFErrInj { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 6; /* * [31:26]reserved */ + unsigned int smmcSmxtfbUncrtErrInj : 1; /* * [25:25]smxt interface buffer ECC un-corrected err injection + requestion;err injection start when posedge of this bit is detected; After + Err injection start, err is inje cted when a memory read is issued to the + memory. */ + unsigned int smmcSmxtfbCrtErrInj : 1; /* * [24:24]smxt interface buffer ECC corrected err injection + requestion;err injection start when posedge of this bit is detected; After + Err injection start, err is injecte d when a memory read is issued to the + memory. */ + unsigned int smmcStbUncrtErrInj : 1; /* * [23:23]engine store buffer ECC un-corrected err injection + requestion;err injection start when posedge of this bit is detected; After Err + injection start, err is inject + ed when a memory read is issued to the memory. */ + unsigned int smmcStbCrtErrInj : 1; /* * [22:22]Engine store buffer ECC corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection start, + err is injected when a memory read is issued to the memory. */ + unsigned int smmcVfaUncrtErrInj : 1; /* * [21:21]VFA table ECC un-corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. */ + unsigned int smmcVfaCrtErrInj : 1; /* * [20:20]VFA table ECC corrected err injection requestion;err injection + start when posedge of this bit is detected; After Err injection start, err is + injected when a mem ory read is issued to the memory. */ + unsigned int smmcRfBufUncrtErrInj : 1; /* * [19:19]refill buffer ECC un-corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected whe n a memory read is issued to the memory. */ + unsigned int smmcRfBufCrtErrInj : 1; /* * [18:18]refill buffer ECC corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. */ + unsigned int smmcQuIntfUncrtErrInj : 1; /* * [17:17]QU interface buffer(include qu_data buffer, qu_lrn buffer + and qu_store_data buffer) ECC un-corrected err injection requestion;err + injection start when posedge o f this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. + */ + unsigned int smmcQuIntfCrtErrInj : 1; /* * [16:16]QU interface buffer(include qu_data buffer, qu_lrn buffer and + qu_store_data buffer) ECC corrected err injection requestion;err injection + start when posedge of t his bit is detected; After Err injection start, err + is injected when a memory read is issued to the memory. + */ + unsigned int smmcMc3UncrtErrInj : 1; /* * [15:15]main cache bank3 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc3CrtErrInj : 1; /* * [14:14]main cache bank3 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc2UncrtErrInj : 1; /* * [13:13]main cache bank2 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc2CrtErrInj : 1; /* * [12:12]main cache bank2 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc1UncrtErrInj : 1; /* * [11:11]main cache bank1 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc1CrtErrInj : 1; /* * [10:10]main cache bank1 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc0UncrtErrInj : 1; /* * [9:9]main cache bank0 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc0CrtErrInj : 1; /* * [8:8]main cache bank0 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcVc3UncrtErrInj : 1; /* * [7:7]victim cache bank3 memory(include all memory in victim cache + bank3) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc3CrtErrInj : 1; /* * [6:6]victim cache bank3 memory(include all memory in victim cache bank3) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc2UncrtErrInj : 1; /* * [5:5]victim cache bank2 memory(include all memory in victim cache + bank2) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc2CrtErrInj : 1; /* * [4:4]victim cache bank2 memory(include all memory in victim cache bank2) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc1UncrtErrInj : 1; /* * [3:3]victim cache bank1 memory(include all memory in victim cache + bank1) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc1CrtErrInj : 1; /* * [2:2]victim cache bank1 memory(include all memory in victim cache bank1) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc0UncrtErrInj : 1; /* * [1:1]victim cache bank0 memory(include all memory in victim cache + bank0) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc0CrtErrInj : 1; /* * [0:0]victim cache bank0 memory(include all memory in victim cache bank0) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ +#else + unsigned int smmcVc0CrtErrInj : 1; /* * [0:0]victim cache bank0 memory(include all memory in victim cache bank0) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc0UncrtErrInj : 1; /* * [1:1]victim cache bank0 memory(include all memory in victim cache + bank0) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc1CrtErrInj : 1; /* * [2:2]victim cache bank1 memory(include all memory in victim cache bank1) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc1UncrtErrInj : 1; /* * [3:3]victim cache bank1 memory(include all memory in victim cache + bank1) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc2CrtErrInj : 1; /* * [4:4]victim cache bank2 memory(include all memory in victim cache bank2) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc2UncrtErrInj : 1; /* * [5:5]victim cache bank2 memory(include all memory in victim cache + bank2) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcVc3CrtErrInj : 1; /* * [6:6]victim cache bank3 memory(include all memory in victim cache bank3) + ECC corrected err injection requestion;err injection start when posedge of this + bit is detec ted; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcVc3UncrtErrInj : 1; /* * [7:7]victim cache bank3 memory(include all memory in victim cache + bank3) ECC un-corrected err injection requestion;err injection start when + posedge of this bit is de tected; After Err injection start, err is injected + when a memory read is issued to the memory. + */ + unsigned int smmcMc0CrtErrInj : 1; /* * [8:8]main cache bank0 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc0UncrtErrInj : 1; /* * [9:9]main cache bank0 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc1CrtErrInj : 1; /* * [10:10]main cache bank1 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc1UncrtErrInj : 1; /* * [11:11]main cache bank1 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc2CrtErrInj : 1; /* * [12:12]main cache bank2 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc2UncrtErrInj : 1; /* * [13:13]main cache bank2 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcMc3CrtErrInj : 1; /* * [14:14]main cache bank3 memory(include tag memory and data memory) ECC + corrected err injection requestion;err injection start when posedge of this bit + is detected; Aft er Err injection start, err is injected when a memory read is + issued to the memory. + */ + unsigned int smmcMc3UncrtErrInj : 1; /* * [15:15]main cache bank3 memory(include tag memory and data memory) ECC + un-corrected err injection requestion;err injection start when posedge of this + bit is detected; After Err injection start, err is injected when a memory read + is issued to the memory. + */ + unsigned int smmcQuIntfCrtErrInj : 1; /* * [16:16]QU interface buffer(include qu_data buffer, qu_lrn buffer and + qu_store_data buffer) ECC corrected err injection requestion;err injection + start when posedge of t his bit is detected; After Err injection start, err + is injected when a memory read is issued to the memory. + */ + unsigned int smmcQuIntfUncrtErrInj : 1; /* * [17:17]QU interface buffer(include qu_data buffer, qu_lrn buffer + and qu_store_data buffer) ECC un-corrected err injection requestion;err + injection start when posedge o f this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. + */ + unsigned int smmcRfBufCrtErrInj : 1; /* * [18:18]refill buffer ECC corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. */ + unsigned int smmcRfBufUncrtErrInj : 1; /* * [19:19]refill buffer ECC un-corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected whe n a memory read is issued to the memory. */ + unsigned int smmcVfaCrtErrInj : 1; /* * [20:20]VFA table ECC corrected err injection requestion;err injection + start when posedge of this bit is detected; After Err injection start, err is + injected when a mem ory read is issued to the memory. */ + unsigned int smmcVfaUncrtErrInj : 1; /* * [21:21]VFA table ECC un-corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection + start, err is injected when a memory read is issued to the memory. */ + unsigned int smmcStbCrtErrInj : 1; /* * [22:22]Engine store buffer ECC corrected err injection requestion;err + injection start when posedge of this bit is detected; After Err injection start, + err is injected when a memory read is issued to the memory. */ + unsigned int smmcStbUncrtErrInj : 1; /* * [23:23]engine store buffer ECC un-corrected err injection + requestion;err injection start when posedge of this bit is detected; After Err + injection start, err is inject + ed when a memory read is issued to the memory. */ + unsigned int smmcSmxtfbCrtErrInj : 1; /* * [24:24]smxt interface buffer ECC corrected err injection + requestion;err injection start when posedge of this bit is detected; After + Err injection start, err is injecte d when a memory read is issued to the + memory. */ + unsigned int smmcSmxtfbUncrtErrInj : 1; /* * [25:25]smxt interface buffer ECC un-corrected err injection + requestion;err injection start when posedge of this bit is detected; After + Err injection start, err is inje cted when a memory read is issued to the + memory. */ + unsigned int reserved : 6; /* * [31:26]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_ERR_INJ_U; + +/* ** + * Union name : SMMC_F_GPA_TRANS_ERR + * @brief + * Description: + */ +typedef union tagUnSmmcFGpaTransErr { + struct tagStSmmcFGpaTransErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]captures error state of BAT or CLA GPA.[31:21]:reserved;[20]:error type. + 1:memory index error; 0:GPA is invalid;[19:10]:VF-ID;[9:6]:tag_type;[5:4]:current CLA l + ev: 2'b00:0 level CLA; 2'b01:1 level CLA; 2'B10:2 level CLA;[3:2]:total CLA + lev: 2'b00:0 level; 2'b01:1 level; 2'b10:2 level; + */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ +#else + unsigned int errorBit : 1; /* * [0:0]0:no error founded1:error founded */ + unsigned int multiErrorBit : 1; /* * [1:1]0:not more than 1 error founded1:more than 1 errors founded */ + unsigned int sticky : 30; /* * [31:2]captures error state of BAT or CLA GPA.[31:21]:reserved;[20]:error type. + 1:memory index error; 0:GPA is invalid;[19:10]:VF-ID;[9:6]:tag_type;[5:4]:current CLA l + ev: 2'b00:0 level CLA; 2'b01:1 level CLA; 2'B10:2 level CLA;[3:2]:total CLA + lev: 2'b00:0 level; 2'b01:1 level; 2'b10:2 level; + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_GPA_TRANS_ERR_U; + +/* ** + * Union name : SMMC_F_QU_INTF_CNT_CFG + * @brief + * Description: + */ +typedef union tagUnSmmcFQuIntfCntCfg { + struct tagStSmmcFQuIntfCntCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + smmcFQuIntfRxCntCfg : 16; /* * [31:16]qu_interface API received counter configuration, API received counter + is used to count for API request that sent from QU to + SMMC_F:qu_intf_rx_cnt和qu_rx_flit_ctp + 共用该寄存器的配置参数。qu_intf_rx_cnt要计数的API类型，qu_rx_flit_ctp要抓的数据类型，都由该寄存器的bit【30:16】决定。[31]:counter + enable. 1'b0: disable counter; 1'b1: enable coutner;[30]:VF_ ID configuration + enable. If this bit is valid, counter will count for API by the VF_ID configured by + CSR.[29]:TAG_TYPE configuration enable. If this bit is vali d, counter will count for + API by the tag_type configured by CSR.[28]:OPCODE configuration enable. If this bit is + valid, counter will count for API by the opcode configured by CSR.[27:19]:VF_ID. If + bit[30] is valid, counter will count for API by this + field.(NOTE:当该参数用来配置qu_intf_rx_cnt时，配的是映射后的VF_ID.当该参数用来配置qu_rx_flit_ct + p时，配的是映射之前的VF_ID.)[18:17]:TAG_TYPE. If bit[29] is valid, counter will count + for API by this field. 2'b00: flow table parent context; 2'b01: RDMA parent cont + ext; 2'b10: child context; 2'b11: reserved;[16]:OPCODE. If bit[28] is valid, + counter will count for API by this field. 1'b0: load; 1'b1: store;Note:bit[ 30:28] + could be configured to enable or disable independently. If bit[30:28] are all valid, + counter will count for API by VF_ID and TAG_TYPE and OPCODE at the s ame time. If none + of bit[30:28] is valid, counter will count for any API received. + */ + unsigned int + smmcFQuIntfTxCntCfg : 16; /* * [15:0]qu_interface API transmited counter configuration, API transmit + counter is used to count for API response that sent from SMMC_F to + QU:qu_intf_tx_cnt和qu_tx_flit_ + ctp共用该寄存器的配置参数。qu_intf_tx_cnt要计数的API类型，qu_tx_flit_ctp要抓的数据类型，都由该寄存器的bit【14:0】决定。[15]:counter + enable. 1'b0: disable counter; 1'b1: enable coutner;[14]:V F_ID + configuration enable. If this bit is valid, counter will count for API by the + VF_ID configured by CSR.[13]:TAG_TYPE configuration enable. If this bit is va + lid, counter will count for API by the tag_type configured by CSR.[12]:OPCODE + configuration enable. If this bit is valid, counter will count for API by the + opco de configured by CSR.[11:3]:VF_ID. If bit[14] is valid, counter will + count for API by this field.(NOTE:该参数配的是映射后的VF_ID.)[2:1]:TAG_TYPE. + If bit[13] is valid, cou nter will count for API by this field. 2'b00: flow + table parent context; 2'b01: RDMA parent context; 2'b10: child context; + 2'b11: reserved;[0]:OPCODE. I f bit[12] is valid, counter will count for API + by this field. 1'b0: load; 1'b1: store;Note:bit[14:12] could be + configured to enable or disable independently . If bit[14:12] are all valid, + counter will count for API by VF_ID and TAG_TYPE and OPCODE at the same time. + If none of bit[14:12] is valid, counter will count for any API sent. */ +#else + unsigned int + smmcFQuIntfTxCntCfg : 16; /* * [15:0]qu_interface API transmited counter configuration, API transmit + counter is used to count for API response that sent from SMMC_F to + QU:qu_intf_tx_cnt和qu_tx_flit_ + ctp共用该寄存器的配置参数。qu_intf_tx_cnt要计数的API类型，qu_tx_flit_ctp要抓的数据类型，都由该寄存器的bit【14:0】决定。[15]:counter + enable. 1'b0: disable counter; 1'b1: enable coutner;[14]:V F_ID + configuration enable. If this bit is valid, counter will count for API by the + VF_ID configured by CSR.[13]:TAG_TYPE configuration enable. If this bit is va + lid, counter will count for API by the tag_type configured by CSR.[12]:OPCODE + configuration enable. If this bit is valid, counter will count for API by the + opco de configured by CSR.[11:3]:VF_ID. If bit[14] is valid, counter will + count for API by this field.(NOTE:该参数配的是映射后的VF_ID.)[2:1]:TAG_TYPE. + If bit[13] is valid, cou nter will count for API by this field. 2'b00: flow + table parent context; 2'b01: RDMA parent context; 2'b10: child context; + 2'b11: reserved;[0]:OPCODE. I f bit[12] is valid, counter will count for API + by this field. 1'b0: load; 1'b1: store;Note:bit[14:12] could be + configured to enable or disable independently . If bit[14:12] are all valid, + counter will count for API by VF_ID and TAG_TYPE and OPCODE at the same time. + If none of bit[14:12] is valid, counter will count for any API sent. */ + unsigned int + smmcFQuIntfRxCntCfg : 16; /* * [31:16]qu_interface API received counter configuration, API received counter + is used to count for API request that sent from QU to + SMMC_F:qu_intf_rx_cnt和qu_rx_flit_ctp + 共用该寄存器的配置参数。qu_intf_rx_cnt要计数的API类型，qu_rx_flit_ctp要抓的数据类型，都由该寄存器的bit【30:16】决定。[31]:counter + enable. 1'b0: disable counter; 1'b1: enable coutner;[30]:VF_ ID configuration + enable. If this bit is valid, counter will count for API by the VF_ID configured by + CSR.[29]:TAG_TYPE configuration enable. If this bit is vali d, counter will count for + API by the tag_type configured by CSR.[28]:OPCODE configuration enable. If this bit is + valid, counter will count for API by the opcode configured by CSR.[27:19]:VF_ID. If + bit[30] is valid, counter will count for API by this + field.(NOTE:当该参数用来配置qu_intf_rx_cnt时，配的是映射后的VF_ID.当该参数用来配置qu_rx_flit_ct + p时，配的是映射之前的VF_ID.)[18:17]:TAG_TYPE. If bit[29] is valid, counter will count + for API by this field. 2'b00: flow table parent context; 2'b01: RDMA parent cont + ext; 2'b10: child context; 2'b11: reserved;[16]:OPCODE. If bit[28] is valid, + counter will count for API by this field. 1'b0: load; 1'b1: store;Note:bit[ 30:28] + could be configured to enable or disable independently. If bit[30:28] are all valid, + counter will count for API by VF_ID and TAG_TYPE and OPCODE at the s ame time. If none + of bit[30:28] is valid, counter will count for any API received. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_QU_INTF_CNT_CFG_U; + +/* ** + * Union name : SMMC_F_QU_INTF_RX_CNT + * @brief + * Description: + */ +typedef union tagUnSmmcFQuIntfRxCnt { + struct tagStSmmcFQuIntfRxCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFQuIntfRxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the + configuration. */ +#else + unsigned int smmcFQuIntfRxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the + configuration. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_QU_INTF_RX_CNT_U; + +/* ** + * Union name : SMMC_F_QU_INTF_TX_CNT + * @brief + * Description: + */ +typedef union tagUnSmmcFQuIntfTxCnt { + struct tagStSmmcFQuIntfTxCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFQuIntfTxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the + configuration. */ +#else + unsigned int smmcFQuIntfTxCnt : 32; /* * [31:0]This can be programmed to count any kind of API depeding on the + configuration. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_QU_INTF_TX_CNT_U; + +/* ** + * Union name : SMMC_F_MC_CFG2 + * @brief + * Description: + */ +typedef union tagUnSmmcFMcCfg2 { + struct tagStSmmcFMcCfg2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11] */ + unsigned int mcRefillTimeoutEnb : 1; /* * [10:10]enable SMMC to monitor and check if a refill request to CPI is + timeout. */ + unsigned int smfCommonMemPowerMode : 6; /* * [9:4]memory power mode control, this signal is used to control + * memory in SMXR,and SMMC(except tag memory and data memory in main + * cache and victim cache) + */ + unsigned int + smmcFRfErrCtpClr : 1; /* * [3:3]clear the refill error information and restart to capture next refill error + information. The refill error information could be read via CSR indirect access.Note + :该信号是用来清除refill error捕抓的信息,并且重新开始捕抓下一个refill + error的信息的。正常的流程应该是，refill + error报中断后，软件通过CSR间接读写接口去读取捕抓的错误信息（捕抓信息的bit0等于时表示捕抓的信息有效），读取分析完后再通过该信号去清除捕抓的信息。该信号是上升沿触发清零 + 操作，如果多次清零，需要先把该信号写成零，再写成一，这样SMMC会产生一个上升沿脉冲信号，并用该脉冲信号清零。 + */ + unsigned int smmcFRttCntEnb : 1; /* * [2:2]SMMC_F support to record the longest/shortest latency of refilling + from CPI, or record the longest/shortest operating latency in SMMC_F.If this + signal is enable , SMMC_F issue a counter to record the latency, and capture the + latency in two register:rtt_ctp_short and rtt_ctp_long. these two register can be + read by SW via CSR indirect access. */ + unsigned int smmcFRttCntType : 1; /* * [1:1]SW can configure this signal to indicate SMMC_F which type of + * latency to record:0:record API operating latency in SMMC_F.1:record refill + * latency from CPI. + */ + unsigned int smmcFRscCntMixEn : 1; /* * [0:0]If rsc_cnt_mix_en=1, SQ WQE and RQ WQE and other data structures + share the same virtual cache.SMMC doesn't differentiate WQE type (SQ WQE and RQ + WQE) in this ca se, SMMC just maintains one resource counter.If + rsc_cnt_mix_en=0, SQ WQE uses a separate virtual cache (only SQ WQE in this + virtual cache). RQ WQE uses another separate virtual cache (only RQ WQE in this + virtual cache).SQ resource counter and RQ resource counter are counted + independently. + */ +#else + unsigned int smmcFRscCntMixEn : 1; /* * [0:0]If rsc_cnt_mix_en=1, SQ WQE and RQ WQE and other data structures + share the same virtual cache.SMMC doesn't differentiate WQE type (SQ WQE and RQ + WQE) in this ca se, SMMC just maintains one resource counter.If + rsc_cnt_mix_en=0, SQ WQE uses a separate virtual cache (only SQ WQE in this + virtual cache). RQ WQE uses another separate virtual cache (only RQ WQE in this + virtual cache).SQ resource counter and RQ resource counter are counted + independently. + */ + unsigned int smmcFRttCntType : 1; /* * [1:1]SW can configure this signal to indicate SMMC_F which type of + * latency to record:0:record API operating latency in SMMC_F.1:record refill + * latency from CPI. + */ + unsigned int smmcFRttCntEnb : 1; /* * [2:2]SMMC_F support to record the longest/shortest latency of refilling + from CPI, or record the longest/shortest operating latency in SMMC_F.If this + signal is enable , SMMC_F issue a counter to record the latency, and capture the + latency in two register:rtt_ctp_short and rtt_ctp_long. these two register can be + read by SW via CSR indirect access. */ + unsigned int + smmcFRfErrCtpClr : 1; /* * [3:3]clear the refill error information and restart to capture next refill error + information. The refill error information could be read via CSR indirect access.Note + :该信号是用来清除refill error捕抓的信息,并且重新开始捕抓下一个refill + error的信息的。正常的流程应该是，refill + error报中断后，软件通过CSR间接读写接口去读取捕抓的错误信息（捕抓信息的bit0等于时表示捕抓的信息有效），读取分析完后再通过该信号去清除捕抓的信息。该信号是上升沿触发清零 + 操作，如果多次清零，需要先把该信号写成零，再写成一，这样SMMC会产生一个上升沿脉冲信号，并用该脉冲信号清零。 + */ + unsigned int smfCommonMemPowerMode : 6; /* * [9:4]memory power mode control, this signal is used to control + * memory in SMXR,and SMMC(except tag memory and data memory in main + * cache and victim cache) + */ + unsigned int mcRefillTimeoutEnb : 1; /* * [10:10]enable SMMC to monitor and check if a refill request to CPI is + timeout. */ + unsigned int reserved : 21; /* * [31:11] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_F_MC_CFG2_U; + + +/* ** + * Union name : SMMC_L_VERSION + * @brief reserved for ECO + * Description: + */ +typedef union tagUnSmmcLVersion { + struct tagStSmmcLVersion { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLVersion : 32; /* * [31:0]reserved for ECO */ +#else + unsigned int smmcLVersion : 32; /* * [31:0]reserved for ECO */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_VERSION_U; + +/* ** + * Union name : SMMC_L_CFG + * @brief SMMC_L configure register + * Description: + */ +typedef union tagUnSmmcLCfg { + struct tagStSmmcLCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int memRet1nDiv2 : 1; /* * [31:31]control of memory pin RET1N */ + unsigned int spRamTmodDiv2 : 7; /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int memIniEn : 1; /* * [2:2]Enable to initialize internal memory1: enable;0: disable */ + unsigned int smmcLEccChk : 1; /* * [1:1]ECC error check enable */ + unsigned int smmcLParityChk : 1; /* * [0:0]reserved */ +#else + unsigned int smmcLParityChk : 1; /* * [0:0]reserved */ + unsigned int smmcLEccChk : 1; /* * [1:1]ECC error check enable */ + unsigned int memIniEn : 1; /* * [2:2]Enable to initialize internal memory1: enable;0: disable */ + unsigned int reserved : 13; /* * [15:3]reserved */ + unsigned int spRamTmod : 7; /* * [22:16]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1n : 1; /* * [23:23]control of memory pin RET1N */ + unsigned int spRamTmodDiv2 : 7; /* * [30:24]16FF+GL SP SRAM Memorybit[1:0]：RTSEL，2'b01bit[3:2]：WTSEL(W/CM =< + * 256), 2'b01bit[5:4]：WTSEL(W/CM > 256), 2'b00bit[6]：floating，fixed 0 + */ + unsigned int memRet1nDiv2 : 1; /* * [31:31]control of memory pin RET1N */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CFG_U; + +/* ** + * Union name : SMMC_L_STAT + * @brief SMMC_L status register + * Description: + */ +typedef union tagUnSmmcLStat { + struct tagStSmmcLStat { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1] */ + unsigned int memIniDone : 1; /* * [0:0]Indicate whether memory initialization done or not1: Done0: not complete + */ +#else + unsigned int memIniDone : 1; /* * [0:0]Indicate whether memory initialization done or not1: Done0: not complete + */ + unsigned int reserved : 31; /* * [31:1] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_STAT_U; + +/* ** + * Union name : SMMC_L_INT_VECTOR + * @brief SMMC_L interrupt vector register + * Description: + */ +typedef union tagUnSmmcLIntVector { + struct tagStSmmcLIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes + * 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]CPI destination PFs and MSI-X Table Index. Software should guarantee + that the format of the 24-bit vector is: {rsvd[4:0], dest_pf[16:0],aeq_offset[1:0]}, + dest_ pf[16] is for the uP; */ + unsigned int reserved1 : 3; /* * [26:24]reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag,enables all interrupts reported thru this + * register0:interrupt disable1:interrupt enable + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.0:no interrupt issued;1:interrupt issued, CP writes + * 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INT_VECTOR_U; + +/* ** + * Union name : SMMC_L_INT + * @brief SMMC_L interrupt register + * Description: + */ +typedef union tagUnSmmcLInt { + struct tagStSmmcLInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 15; /* * [15:1] */ + unsigned int intData : 1; /* * [0:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ +#else + unsigned int intData : 1; /* * [0:0]interrupt masked field,it is the collection of the error bits from the + * corresponding error registers on the sheet + */ + unsigned int reserved : 15; /* * [15:1] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INT_U; + +/* ** + * Union name : SMMC_L_INT_MASK + * @brief SMMC_L interrupt mask register + * Description: + */ +typedef union tagUnSmmcLIntMask { + struct tagStSmmcLIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ + unsigned int reserved : 15; /* * [15:1] */ + unsigned int errMask : 1; /* * [0:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ +#else + unsigned int errMask : 1; /* * [0:0]error register mask flag, it is the same mapping from the interrupt register + * int_mask field. Mask bit 0:interrupt is disabled; Mask bit 1:interrupt enable + */ + unsigned int reserved : 15; /* * [15:1] */ + unsigned int programCsrId : 16; /* * [31:16]programmable CSR ID,indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INT_MASK_U; + +/* ** + * Union name : SMMC_L_MEM_ERR + * @brief SMMC_L MEM error register + * Description: + */ +typedef union tagUnSmmcLMemErr { + struct tagStSmmcLMemErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int mainMem1bEccMerr : 1; /* * [3:3] */ + unsigned int mainMem1bEccErr : 1; /* * [2:2]main memory 1 bit ECC error */ + unsigned int mainMem2bEccMerr : 1; /* * [1:1]multi times of main memory 2 bit ECC error */ + unsigned int mainMem2bEccErr : 1; /* * [0:0]main memory 2 bit ECC error */ +#else + unsigned int mainMem2bEccErr : 1; /* * [0:0]main memory 2 bit ECC error */ + unsigned int mainMem2bEccMerr : 1; /* * [1:1]multi times of main memory 2 bit ECC error */ + unsigned int mainMem1bEccErr : 1; /* * [2:2]main memory 1 bit ECC error */ + unsigned int mainMem1bEccMerr : 1; /* * [3:3] */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_MEM_ERR_U; + +/* ** + * Union name : SMMC_L_MEM_ERR_MASK + * @brief SMMC_L MEM error mask register + * Description: + */ +typedef union tagUnSmmcLMemErrMask { + struct tagStSmmcLMemErrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 30; /* * [31:2]reserved. */ + unsigned int mainMem1bEccErrMask : 1; /* * [1:1]main memory 1 bit ECC error mask */ + unsigned int mainMem2bEccErrMask : 1; /* * [0:0]main memory 2 bit ECC error mask */ +#else + unsigned int mainMem2bEccErrMask : 1; /* * [0:0]main memory 2 bit ECC error mask */ + unsigned int mainMem1bEccErrMask : 1; /* * [1:1]main memory 1 bit ECC error mask */ + unsigned int reserved : 30; /* * [31:2]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_MEM_ERR_MASK_U; + +/* ** + * Union name : SMMC_L_MEM_ERR_INFO + * @brief SMMC_L MEM error info register + * Description: + */ +typedef union tagUnSmmcLMemErrInfo { + struct tagStSmmcLMemErrInfo { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 14; /* * [31:18]reserved. */ + unsigned int memErrInfoType : 2; /* * [17:16]Indicate which error's info is captured:00: main memory has 1 bit + * ECC error;01: main memory has 2 bit ECC error;10~11: reserved + */ + unsigned int reserved1 : 1; /* * [15:15]reserved bit */ + unsigned int memErrIndex : 15; /* * [14:0]Indicate the address of entry meeting error.For main memory, + * index[14:0] is usage for 32 K entries of 32 byte. + */ +#else + unsigned int memErrIndex : 15; /* * [14:0]Indicate the address of entry meeting error.For main memory, + * index[14:0] is usage for 32 K entries of 32 byte. + */ + unsigned int reserved1 : 1; /* * [15:15]reserved bit */ + unsigned int memErrInfoType : 2; /* * [17:16]Indicate which error's info is captured:00: main memory has 1 bit + * ECC error;01: main memory has 2 bit ECC error;10~11: reserved + */ + unsigned int reserved0 : 14; /* * [31:18]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_MEM_ERR_INFO_U; + +/* ** + * Union name : SMMC_L_INDRECT_CTRL + * @brief indirect access address registers + * Description: + */ +typedef union tagUnSmmcLIndrectCtrl { + struct tagStSmmcLIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ + unsigned int smmcLIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smmcLIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smmcLIndirTab : 4; /* * [27:24]It specifies memory group or table. 4'h0: main memory;4'h1: ECC + memory.ECC memory only can rightly read or write in debug mode without normal + datapath stream.4' h2: loopback CAM request info and link info.It only support to + read and not to write;4'h3: slot ring.It only support to read and not to + write;4'h4: bank queue i nfo.It only support to read and not to write;4'h5: + reserved;4'h6: reserved4'h7~4'hf: reserved + */ + unsigned int + smmcLIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.(1) Main memory:Total size is 1M byte and one e ntry + is 32 byte.Index[17:0] is usage for access main memory.Index[17:3] address to one entry, + and index[2:0] address to one 4 byte in one entry.index[2:0]000: e ntry[255:224];001: + entry[223:192];010: entry[191:160];011: entry[159:128];100: entry[127:96];101: + entry[95:64];110: entry[63:32];111: entry[31:0];(2) ECC memory One 10 bit ECC protects one + entry of main memory.16 ECC of 10 bits is grouped as one entry of ECC memory and total + number of entries is 2 K. Index[14:0] address one entry of 10 bit ECC. One entry + is{22'd0,EEC[9:0]};(3) Loopback CAM and Request info and Link infoThese are addressed by + request ID.Total number of request ID is 16. Index[3:0] address one entry of one request + ID. One entry's datastructre:entry[31:24]: loopback CAM[7:0];entry[23:21]: reserved 3 + bit;entry[20:4]: req uest info[16:0];entry[3:0]: link info[3:0]; (4) Slot ringSlot ring + only has 8 bits, index is unused.(5) Bank queue list info;Bank queue list info is addressed + b y bank ID, and total number of bank in SMMC_L is 16 banks. Once CSR can access 2 bank + queue list infos as an entry. Its datastructure isEntry[31:26]: reserved 6 + bits;Entry[25:16]: bank queue list info[9:0]Entry[15:10]: reserved 6 bits;Entry[9:0]: bank + queue list info[9:0]Index[2:0] address one entry;000: bank 0 and ban k 1's list info001: + bank 2 and bank 3's list info010: bank 4 and bank 5's list info011: bank 6 and bank 7's + list info100: bank 8 and bank 9's list info101: bank 10 and bank 11's list info110: bank 12 + and bank 13's list info111: bank 14 and bank 15's list info(6) reserved + */ +#else + unsigned int + smmcLIndirAddr : 24; /* * [23:0]The RSV or invalid bit must be wrote 0;It specifies memory address in one + group or internal address of the table.(1) Main memory:Total size is 1M byte and one e ntry + is 32 byte.Index[17:0] is usage for access main memory.Index[17:3] address to one entry, + and index[2:0] address to one 4 byte in one entry.index[2:0]000: e ntry[255:224];001: + entry[223:192];010: entry[191:160];011: entry[159:128];100: entry[127:96];101: + entry[95:64];110: entry[63:32];111: entry[31:0];(2) ECC memory One 10 bit ECC protects one + entry of main memory.16 ECC of 10 bits is grouped as one entry of ECC memory and total + number of entries is 2 K. Index[14:0] address one entry of 10 bit ECC. One entry + is{22'd0,EEC[9:0]};(3) Loopback CAM and Request info and Link infoThese are addressed by + request ID.Total number of request ID is 16. Index[3:0] address one entry of one request + ID. One entry's datastructre:entry[31:24]: loopback CAM[7:0];entry[23:21]: reserved 3 + bit;entry[20:4]: req uest info[16:0];entry[3:0]: link info[3:0]; (4) Slot ringSlot ring + only has 8 bits, index is unused.(5) Bank queue list info;Bank queue list info is addressed + b y bank ID, and total number of bank in SMMC_L is 16 banks. Once CSR can access 2 bank + queue list infos as an entry. Its datastructure isEntry[31:26]: reserved 6 + bits;Entry[25:16]: bank queue list info[9:0]Entry[15:10]: reserved 6 bits;Entry[9:0]: bank + queue list info[9:0]Index[2:0] address one entry;000: bank 0 and ban k 1's list info001: + bank 2 and bank 3's list info010: bank 4 and bank 5's list info011: bank 6 and bank 7's + list info100: bank 8 and bank 9's list info101: bank 10 and bank 11's list info110: bank 12 + and bank 13's list info111: bank 14 and bank 15's list info(6) reserved + */ + unsigned int smmcLIndirTab : 4; /* * [27:24]It specifies memory group or table. 4'h0: main memory;4'h1: ECC + memory.ECC memory only can rightly read or write in debug mode without normal + datapath stream.4' h2: loopback CAM request info and link info.It only support to + read and not to write;4'h3: slot ring.It only support to read and not to + write;4'h4: bank queue i nfo.It only support to read and not to write;4'h5: + reserved;4'h6: reserved4'h7~4'hf: reserved + */ + unsigned int smmcLIndirStat : 2; /* * [29:28]It specifies the indirect access status:2’b00: indirect access + * done;2’b01: indirect access timeout;Others: reserved. + */ + unsigned int smmcLIndirMode : 1; /* * [30:30]It specifies the indirect access mode:1’b0: write;1’b1: read. */ + unsigned int smmcLIndirVld : 1; /* * [31:31]It specifies the indirect access validation:1’b0: indirect access + invalid, including operation done and timeout (initial value or logic clear);1’b1: + indirect ac cess valid (software set). */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INDRECT_CTRL_U; + +/* ** + * Union name : SMMC_L_INDRECT_TIMEOUT + * @brief memory access timeout configure + * Description: + */ +typedef union tagUnSmmcLIndrectTimeout { + struct tagStSmmcLIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#else + unsigned int smmcLIndirTimeout : 32; /* * [31:0]memory access timeout configure */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INDRECT_TIMEOUT_U; + +/* ** + * Union name : SMMC_L_INDRECT_DATA + * @brief indirect access data registers + * Description: + */ +typedef union tagUnSmmcLIndrectData { + struct tagStSmmcLIndrectData { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcFIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#else + unsigned int smmcFIndirData : 32; /* * [31:0]It specifies the indirect access data:When operation write: + Software write data to these registes and then enable indirect access, logic will + send these data to target.When operation read: Logic write data to these + registers and refresh xxx_indir_stat, software will get these data from target. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_INDRECT_DATA_U; + +/* ** + * Union name : SMMC_L_CNT_CFG + * @brief SMMC_L counter configure register + * Description: + */ +typedef union tagUnSmmcLCntCfg { + struct tagStSmmcLCntCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20] */ + unsigned int cnt3Sel : 2; /* * [19:18]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt2Sel : 2; /* * [17:16]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt1Sel : 2; /* * [15:14]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt0Sel : 2; /* * [13:12]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt3MatchEn : 2; /* * [11:10]00: count for all types01: reserved 10: counter for matched bank + * ID;11: reserved; + */ + unsigned int cnt2MatchEn : 2; /* * [9:8]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt1MatchEn : 2; /* * [7:6]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt0MatchEn : 2; /* * [5:4]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt3Enable : 1; /* * [3:3]1: counter3 is enabled 0: counter3 is disabled */ + unsigned int cnt2Enable : 1; /* * [2:2]1: counter2 is enabled 0: counter2 is disabled */ + unsigned int cnt1Enable : 1; /* * [1:1]1: counter1 is enabled 0: counter1 is disabled */ + unsigned int cnt0Enable : 1; /* * [0:0]1: counter0 is enabled 0: counter0 is disabled */ +#else + unsigned int cnt0Enable : 1; /* * [0:0]1: counter0 is enabled 0: counter0 is disabled */ + unsigned int cnt1Enable : 1; /* * [1:1]1: counter1 is enabled 0: counter1 is disabled */ + unsigned int cnt2Enable : 1; /* * [2:2]1: counter2 is enabled 0: counter2 is disabled */ + unsigned int cnt3Enable : 1; /* * [3:3]1: counter3 is enabled 0: counter3 is disabled */ + unsigned int cnt0MatchEn : 2; /* * [5:4]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt1MatchEn : 2; /* * [7:6]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt2MatchEn : 2; /* * [9:8]00: count for all types01: reserved 10: counter for matched bank ID;11: + * reserved; + */ + unsigned int cnt3MatchEn : 2; /* * [11:10]00: count for all types01: reserved 10: counter for matched bank + * ID;11: reserved; + */ + unsigned int cnt0Sel : 2; /* * [13:12]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt1Sel : 2; /* * [15:14]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt2Sel : 2; /* * [17:16]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int cnt3Sel : 2; /* * [19:18]00: load reqeust;01: store request;10: partial store request;11: load + response; */ + unsigned int reserved : 12; /* * [31:20] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT_CFG_U; + +/* ** + * Union name : SMMC_L_CNT_MATCH_BANK + * @brief SMMC_L counter configure register for matching instance ID + * Description: + */ +typedef union tagUnSmmcLCntMatchBank { + struct tagStSmmcLCntMatchBank { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int cnt3MatchBank : 4; /* * [15:12]Bank ID for counter 3 */ + unsigned int cnt2MatchBank : 4; /* * [11:8]Bank ID for counter 2 */ + unsigned int cnt1MatchBank : 4; /* * [7:4]Bank ID for counter 1 */ + unsigned int cnt0MatchBank : 4; /* * [3:0]Bank ID for counter 0 */ +#else + unsigned int cnt0MatchBank : 4; /* * [3:0]Bank ID for counter 0 */ + unsigned int cnt1MatchBank : 4; /* * [7:4]Bank ID for counter 1 */ + unsigned int cnt2MatchBank : 4; /* * [11:8]Bank ID for counter 2 */ + unsigned int cnt3MatchBank : 4; /* * [15:12]Bank ID for counter 3 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT_MATCH_BANK_U; + +/* ** + * Union name : SMMC_L_CNT_MATCH_INSTANCE + * @brief SMMC_L counter configure register for matching instance ID + * Description: + */ +typedef union tagUnSmmcLCntMatchInstance { + struct tagStSmmcLCntMatchInstance { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20]SMMC_L does not see instance ID, so that this configuration is not used + */ + unsigned int cnt3MatchInst : 5; /* * [19:15]Reserved */ + unsigned int cnt2MatchInst : 5; /* * [14:10]Reserved */ + unsigned int cnt1MatchInst : 5; /* * [9:5]Reserved */ + unsigned int cnt0MatchInst : 5; /* * [4:0]Reserved */ +#else + unsigned int cnt0MatchInst : 5; /* * [4:0]Reserved */ + unsigned int cnt1MatchInst : 5; /* * [9:5]Reserved */ + unsigned int cnt2MatchInst : 5; /* * [14:10]Reserved */ + unsigned int cnt3MatchInst : 5; /* * [19:15]Reserved */ + unsigned int reserved : 12; /* * [31:20]SMMC_L does not see instance ID, so that this configuration is not used + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT_MATCH_INSTANCE_U; + +/* ** + * Union name : SMMC_L_CNT0 + * @brief SMMC_L counter 0 register + * Description: + */ +typedef union tagUnSmmcLCnt0 { + struct tagStSmmcLCnt0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLCnt0 : 32; /* * [31:0]Couner 0 accroding to counter configure register. */ +#else + unsigned int smmcLCnt0 : 32; /* * [31:0]Couner 0 accroding to counter configure register. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT0_U; + +/* ** + * Union name : SMMC_L_CNT1 + * @brief SMMC_L counter 1 register + * Description: + */ +typedef union tagUnSmmcLCnt1 { + struct tagStSmmcLCnt1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLCnt1 : 32; /* * [31:0]Couner 1 accroding to counter configure register. */ +#else + unsigned int smmcLCnt1 : 32; /* * [31:0]Couner 1 accroding to counter configure register. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT1_U; + +/* ** + * Union name : SMMC_L_CNT2 + * @brief SMMC_L counter 2 register + * Description: + */ +typedef union tagUnSmmcLCnt2 { + struct tagStSmmcLCnt2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLCnt2 : 32; /* * [31:0]Couner 2 accroding to counter configure register. */ +#else + unsigned int smmcLCnt2 : 32; /* * [31:0]Couner 2 accroding to counter configure register. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT2_U; + +/* ** + * Union name : SMMC_L_CNT3 + * @brief SMMC_L counter 3 register + * Description: + */ +typedef union tagUnSmmcLCnt3 { + struct tagStSmmcLCnt3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int smmcLCnt3 : 32; /* * [31:0]Couner 3 accroding to counter configure register. */ +#else + unsigned int smmcLCnt3 : 32; /* * [31:0]Couner 3 accroding to counter configure register. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_CNT3_U; + +/* ** + * Union name : SMMC_L_BANK_QUEUE_DEPTH_CTP0 + * @brief SMMC_L bank queue's depth register 0 + * Description: + */ +typedef union tagUnSmmcLBankQueueDepthCtp0 { + struct tagStSmmcLBankQueueDepthCtp0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int curDepthBank7 : 4; /* * [31:28]Current depth of bank 7 queue.Notice that depth of bank is up to 15, + because only 15 threads of SMEG1 are active in normal mode, and 1 thread is + reserved for de bug mode. */ + unsigned int curDepthBank6 : 4; /* * [27:24]Current depth of bank 6 queue. */ + unsigned int curDepthBank5 : 4; /* * [23:20]Current depth of bank 5 queue. */ + unsigned int curDepthBank4 : 4; /* * [19:16]Current depth of bank 4 queue. */ + unsigned int curDepthBank3 : 4; /* * [15:12]Current depth of bank 3 queue. */ + unsigned int curDepthBank2 : 4; /* * [11:8]Current depth of bank 2 queue. */ + unsigned int curDepthBank1 : 4; /* * [7:4]Current depth of bank 1 queue. */ + unsigned int curDepthBank0 : 4; /* * [3:0]Current depth of bank 0 queue. */ +#else + unsigned int curDepthBank0 : 4; /* * [3:0]Current depth of bank 0 queue. */ + unsigned int curDepthBank1 : 4; /* * [7:4]Current depth of bank 1 queue. */ + unsigned int curDepthBank2 : 4; /* * [11:8]Current depth of bank 2 queue. */ + unsigned int curDepthBank3 : 4; /* * [15:12]Current depth of bank 3 queue. */ + unsigned int curDepthBank4 : 4; /* * [19:16]Current depth of bank 4 queue. */ + unsigned int curDepthBank5 : 4; /* * [23:20]Current depth of bank 5 queue. */ + unsigned int curDepthBank6 : 4; /* * [27:24]Current depth of bank 6 queue. */ + unsigned int curDepthBank7 : 4; /* * [31:28]Current depth of bank 7 queue.Notice that depth of bank is up to 15, + because only 15 threads of SMEG1 are active in normal mode, and 1 thread is + reserved for de bug mode. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP0_U; + +/* ** + * Union name : SMMC_L_BANK_QUEUE_DEPTH_CTP1 + * @brief SMMC_L bank queue's depth register 1 + * Description: + */ +typedef union tagUnSmmcLBankQueueDepthCtp1 { + struct tagStSmmcLBankQueueDepthCtp1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int curDepthBank15 : 4; /* * [31:28]Current depth of bank 15 queue.Notice that depth of bank is up to + 15, because only 15 threads of SMEG1 are active in normal mode, and 1 thread is + reserved for d ebug mode. */ + unsigned int curDepthBank14 : 4; /* * [27:24]Current depth of bank 14 queue. */ + unsigned int curDepthBank13 : 4; /* * [23:20]Current depth of bank 13 queue. */ + unsigned int curDepthBank12 : 4; /* * [19:16]Current depth of bank 12 queue. */ + unsigned int curDepthBank11 : 4; /* * [15:12]Current depth of bank 11 queue. */ + unsigned int curDepthBank10 : 4; /* * [11:8]Current depth of bank 10 queue. */ + unsigned int curDepthBank9 : 4; /* * [7:4]Current depth of bank 9 queue. */ + unsigned int curDepthBank8 : 4; /* * [3:0]Current depth of bank 8 queue. */ +#else + unsigned int curDepthBank8 : 4; /* * [3:0]Current depth of bank 8 queue. */ + unsigned int curDepthBank9 : 4; /* * [7:4]Current depth of bank 9 queue. */ + unsigned int curDepthBank10 : 4; /* * [11:8]Current depth of bank 10 queue. */ + unsigned int curDepthBank11 : 4; /* * [15:12]Current depth of bank 11 queue. */ + unsigned int curDepthBank12 : 4; /* * [19:16]Current depth of bank 12 queue. */ + unsigned int curDepthBank13 : 4; /* * [23:20]Current depth of bank 13 queue. */ + unsigned int curDepthBank14 : 4; /* * [27:24]Current depth of bank 14 queue. */ + unsigned int curDepthBank15 : 4; /* * [31:28]Current depth of bank 15 queue.Notice that depth of bank is up to + 15, because only 15 threads of SMEG1 are active in normal mode, and 1 thread is + reserved for d ebug mode. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_BANK_QUEUE_DEPTH_CTP1_U; + +/* ** + * Union name : SMMC_L_ECC_INJ_CFG + * @brief SMMC_L ECC inject register + * Description: + */ +typedef union tagUnSmmcLEccInjCfg { + struct tagStSmmcLEccInjCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 30; /* * [31:2]Reserved */ + unsigned int smmcL2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read Data memory0: disable1: + enable */ + unsigned int smmcL1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read Data memory0: disable1: + enable */ +#else + unsigned int smmcL1bEccInjEn : 1; /* * [0:0]Enable to inject Single ECC Error when read Data memory0: disable1: + enable */ + unsigned int smmcL2bEccInjEn : 1; /* * [1:1]Enable to inject Dual ECC Error when read Data memory0: disable1: + enable */ + unsigned int reserved : 30; /* * [31:2]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_ECC_INJ_CFG_U; + +/* ** + * Union name : SMMC_L_PG_CFG + * @brief SMMC_L Partial Good register + * Description: + */ +typedef union tagUnSmmcLPgCfg { + struct tagStSmmcLPgCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 27; /* * [31:5]Reserved */ + unsigned int smmcLPgGrpNum : 1; /* * [4:4]If any group has uncorrected error, SMMC_L can support 2 groups in + paritial good mode.The number of bank group in paritial good mode:0: 4 groups/16 + banks is ena ble;1: 2 groups/8 banks is enable */ + unsigned int smmcLPgGrp0Id : 2; /* * [3:2]This field is valid only if smmc_l_pg_grp_num is configured to 2 group + mode.The 1st group ID of PG.Group 0: bank 0~3Group 1: bank 4~7Group 2: bank + 8~11Group 3: bank 12~15.For example, if only support group 1 and group 2, + pg_grp0_id must set to 1 and pg_grp1_id must set to 2. + */ + unsigned int smmcLPgGrp1Id : 2; /* * [1:0]This field is valid only if smmc_l_pg_grp_num is configured to 2 group + mode.The 2nd group ID of PGGroup 0: bank 0~3Group 1: bank 4~7Group 2: bank + 8~11Group 3: b ank 12~15 */ +#else + unsigned int smmcLPgGrp1Id : 2; /* * [1:0]This field is valid only if smmc_l_pg_grp_num is configured to 2 group + mode.The 2nd group ID of PGGroup 0: bank 0~3Group 1: bank 4~7Group 2: bank + 8~11Group 3: b ank 12~15 */ + unsigned int smmcLPgGrp0Id : 2; /* * [3:2]This field is valid only if smmc_l_pg_grp_num is configured to 2 group + mode.The 1st group ID of PG.Group 0: bank 0~3Group 1: bank 4~7Group 2: bank + 8~11Group 3: bank 12~15.For example, if only support group 1 and group 2, + pg_grp0_id must set to 1 and pg_grp1_id must set to 2. + */ + unsigned int smmcLPgGrpNum : 1; /* * [4:4]If any group has uncorrected error, SMMC_L can support 2 groups in + paritial good mode.The number of bank group in paritial good mode:0: 4 groups/16 + banks is ena ble;1: 2 groups/8 banks is enable */ + unsigned int reserved : 27; /* * [31:5]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_SMMC_L_PG_CFG_U; + + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* * __cplusplus */ + +#endif /* * HI1823_CSR_SM_TYPEDEF_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hinic3_csr_addr_common.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hinic3_csr_addr_common.h new file mode 100644 index 000000000..d9ccef586 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/hinic3_csr_addr_common.h @@ -0,0 +1,254 @@ +#ifndef HINIC3_CSR_ADDR_COMMON_H +#define HINIC3_CSR_ADDR_COMMON_H + + +#include "infra_pub.h" +#include "node_id.h" + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* __cplusplus */ + +#define CSR_PHY_ADDR_GEN_CPB(addr) CSR_PHY_ADDR_GEN(NODE_ID_CPB, addr) +#define CSR_PHY_ADDR_GEN_QUL(addr) CSR_PHY_ADDR_GEN(NODE_ID_QUL, addr) +#define CSR_PHY_ADDR_GEN_QUF(addr) CSR_PHY_ADDR_GEN(NODE_ID_QUF, addr) +#define CSR_PHY_ADDR_GEN_ISCH(addr) CSR_PHY_ADDR_GEN(NODE_ID_QUL, addr) /* iSCH use QU's Node id */ +#define CSR_PHY_ADDR_GEN_ESCH(addr) CSR_PHY_ADDR_GEN(NODE_ID_QUL, addr) +#define CSR_PHY_ADDR_GEN_MQM(addr) CSR_PHY_ADDR_GEN(NODE_ID_MQM, addr) +#define CSR_PHY_ADDR_GEN_LCAM(addr) CSR_PHY_ADDR_GEN(NODE_ID_LCAM, addr) + +#define CSR_PHY_ADDR_GEN_TILE_L0(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_L0, addr) +#define CSR_PHY_ADDR_GEN_TILE_L1(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_L1, addr) +#define CSR_PHY_ADDR_GEN_TILE_L2(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_L2, addr) +#define CSR_PHY_ADDR_GEN_TILE_L3(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_L3, addr) + +#define CSR_PHY_ADDR_GEN_TILE_F0(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_F0, addr) +#define CSR_PHY_ADDR_GEN_TILE_F1(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_F1, addr) +#define CSR_PHY_ADDR_GEN_TILE_F2(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_F2, addr) +#define CSR_PHY_ADDR_GEN_TILE_F3(addr) CSR_PHY_ADDR_GEN(NODE_ID_TILE_F3, addr) + +#define CSR_PHY_ADDR_GEN_PETX(addr) CSR_PHY_ADDR_GEN(NODE_ID_DP_NETWORK, addr) +#define CSR_PHY_ADDR_GEN_PERX(addr) CSR_PHY_ADDR_GEN(NODE_ID_DP_HOST, addr) + +#define CSR_PHY_ADDR_GEN_IPSUTX(addr) CSR_PHY_ADDR_GEN(NODE_ID_DP_HOST, addr) +#define CSR_PHY_ADDR_GEN_IPSURX(addr) CSR_PHY_ADDR_GEN(NODE_ID_DP_NETWORK, addr) + +#define CSR_PHY_ADDR_GEN_SML0(addr) CSR_PHY_ADDR_GEN(NODE_ID_SML0, addr) +#define CSR_PHY_ADDR_GEN_SML1(addr) CSR_PHY_ADDR_GEN(NODE_ID_SML1, addr) +#define CSR_PHY_ADDR_GEN_SML2(addr) CSR_PHY_ADDR_GEN(NODE_ID_SML2, addr) +#define CSR_PHY_ADDR_GEN_SML3(addr) CSR_PHY_ADDR_GEN(NODE_ID_SML3, addr) + +#define CSR_PHY_ADDR_GEN_SMF0(addr) CSR_PHY_ADDR_GEN(NODE_ID_SMF0, addr) +#define CSR_PHY_ADDR_GEN_SMF1(addr) CSR_PHY_ADDR_GEN(NODE_ID_SMF1, addr) +#define CSR_PHY_ADDR_GEN_SMF2(addr) CSR_PHY_ADDR_GEN(NODE_ID_SMF2, addr) +#define CSR_PHY_ADDR_GEN_SMF3(addr) CSR_PHY_ADDR_GEN(NODE_ID_SMF3, addr) + +#define CSR_PHY_ADDR_GEN_CRYPT(addr) CSR_PHY_ADDR_GEN(NODE_ID_CRYPTO, addr) + +#define CSR_PHY_ADDR_GEN_ROB(addr) CSR_PHY_ADDR_GEN(NODE_ID_TS, addr) +#define CSR_PHY_ADDR_GEN_ISC(addr) CSR_PHY_ADDR_GEN(NODE_ID_TS, addr) +#define CSR_PHY_ADDR_GEN_ESC(addr) CSR_PHY_ADDR_GEN(NODE_ID_TS, addr) +#define CSR_PHY_ADDR_GEN_TS_TOP(addr) CSR_PHY_ADDR_GEN(NODE_ID_TS, addr) + +#define CSR_PHY_ADDR_GEN_SM(sm_id, addr) CSR_PHY_ADDR_GEN(tool_sm_get_nodeid(sm_id), (addr)) + +/* STLIQ */ +#define IND_STLIQ_MEM_PREALLOC (6) +#define IND_STLIQ_MEM_OQID (7) +#define IND_STLIQ_MEM_PRO_TYPE (9) +#define IND_STLIQ_MEM_ICHANNEL (10) +#define IND_STLIQ_MEM_PCPTR (11) +#define IND_STLIQ_MEM_STL_EVT_ICHNL (14) +#define IND_STLIQ_MEM_STF_EVT_ICHNL (15) + +/* STFIQ */ +#define IND_STFIQ_MEM_MSG_SRV (1) +#define IND_STFIQ_MEM_ICHANNEL (3) +#define IND_STFIQ_MEM_PREALLOC (15) +#define IND_STFIQ_MEM_PCPTR (16) +#define IND_STFIQ_MEM_PCOFFSET (17) + +/* PRMTX & PRMRX */ +#define IND_PRM_G_COS_TH (0) +#define IND_PRM_G_P_TH (1) +#define IND_PRM_G_SRV_TH (2) +#define IND_PRM_Y_STF_P_TH (3) +#define IND_PRM_Y_STF_SRV_TH (4) +#define IND_PRM_R_STF_P_TH (5) +#define IND_PRM_R_STF_SRV_TH (6) +#define IND_PRM_Y_STL_P_TH (7) +#define IND_PRM_Y_STL_SRV_TH (8) +#define IND_PRM_R_STL_P_TH (9) +#define IND_PRM_R_STL_SRV_TH (10) + +/* +(Configurations) +0x0: port group threshold configure table. +0x1:red zone port configure threshold table. +0x2:yellow zone port configure threshold table. +0x3:network side port configure threshold table. +0x4:network side cos configure threshold table. +0x5 : host side EP group configure threshold table. +0x6 : host side srv group (per service) configure threshold table. +0x7 : host side port group(per host per service) configure threshold table. +0x8 : host side pri group (per cos per host per service) configure threshold table. +0x9 : host side queue group (per cos per ep for normal queues) configure threshold table. +*/ +#define IND_MEM_QU_PDM_PORT_GRP_THD_CFG_TBL (0x0) +#define IND_MEM_QU_PDM_RED_ZONE_PORT_CFG_THD_TBL (0x1) +#define IND_MEM_QU_PDM_YELLOW_ZONE_PORT_CFG_THD_TBL (0x2) +#define IND_MEM_QU_PDM_NETWORK_SIDE_PORT_CFG_THD_TBL (0x3) +#define IND_MEM_QU_PDM_NETWORK_SIDE_COS_CFG_THD_TBL (0x4) +#define IND_MEM_QU_PDM_HOST_SIDE_EP_GRP_CFG_THD_TBL (0x5) +#define IND_MEM_QU_PDM_HOST_SIDE_SRV_GRP_CFG_THD_TBL (0x6) +#define IND_MEM_QU_PDM_HOST_SIDE_PORT_GRP_CFG_THD_TBL (0x7) +#define IND_MEM_QU_PDM_HOST_SIDE_PRI_GRP_CFG_THD_TBL (0x8) +#define IND_MEM_QU_PDM_HOST_SIDE_QUE_GRP_CFG_THD_TBL (0x9) + +typedef union { + struct { + unsigned long long pg_fc_th_dif2 : 8; // [71:64] + unsigned long long pg_rsvd_th : 16; // [87:72] + unsigned long long pg_drp_th_on : 16; // [103:88] + unsigned long long pg_drp_th_dif : 8; // [111:104] + unsigned long long pg_max_sh_th : 15; // [126:112] + unsigned long long pg_sh_fc_dyn : 1; // [127] + + unsigned long long pg_fc_th_on0 : 16; // [15:0] + unsigned long long pg_fc_th_on1 : 16; // [31:16] + unsigned long long pg_fc_th_on2 : 16; // [47:32] + unsigned long long pg_fc_th_dif0 : 8; // [55:48] + unsigned long long pg_fc_th_dif1 : 8; // [63:56] + } bs; + + unsigned long long val64[2]; +} u_qu_pdm_port_grp_thd_cfg; + +/* +Red cell occupied threshold table +Yellow cell occupied threshold table +*/ +typedef union { + struct { + unsigned long long port_rsvd_th : 16; // [15:0] + unsigned long long port_bp_th_dif : 8; // [23:16] + unsigned long long port_bp_th : 16; // [39:24] + unsigned long long resv0 : 24; // [63:40] + } bs; + unsigned long long val64; +} u_qu_pdm_color_zone_cfg; + +/* + Network Port cell occupied threshold table Fields Definition + This table was indexed with : +" TP/Mac : {1'b0,port [3:0]}. +" Mc : 16. + +*/ +typedef union { + struct { + unsigned long long port_fc_th_dif2 : 8; // [71:64] + unsigned long long port_rsvd_th : 16; // [87:72] + unsigned long long port_drp_th_on : 16; // [103:88] + unsigned long long port_drp_th_dif : 8; // [111:104] + unsigned long long port_max_sh : 15; // [126:112] + unsigned long long port_sh_fc_dyn : 1; // [127] + + unsigned long long port_fc_th_on0 : 16; // [15:0] + unsigned long long port_fc_th_on1 : 16; // [31:16] + unsigned long long port_fc_th_on2 : 16; // [47:32] + unsigned long long port_fc_th_dif0 : 8; // [55:48] + unsigned long long port_fc_th_dif1 : 8; // [63:56] + } bs; + unsigned long long val64[2]; +} u_qu_pdm_nw_port_thd_cfg; + + +/* + Network Cos cell occupied threshold table Fields Definition + Total number : 128+2 . +" Unicast : {1'b0, port/tp[3:0], cos[2:0]} . +" Multicast(FIC): {5'h10, cos[0]}. +*/ +typedef union { + struct { + unsigned long long cos_rsvd_th : 16; // [15:0] + unsigned long long cos_sh_fc_th_dif : 8; // [23:16] + unsigned long long cos_sh_fc_th_on : 16; // [39:24] + unsigned long long cos_drp_th_dif : 8; // [47:40] + unsigned long long cos_drp_th_on : 16; // [63:48] + } bs; + unsigned long long val64; +} u_qu_pdm_nw_cos_thd_cfg; + + +/* + */ +typedef union { + struct { + unsigned long long cos_rsvd_th : 16; // [15:0] + unsigned long long cos_sh_fc_th_dif : 8; // [23:16] + unsigned long long cos_sh_fc_th_on : 16; // [39:24] + unsigned long long cos_sh_bp_th_dif : 8; // [47:40] + unsigned long long cos_sh_bp_th_on : 16; // [63:48] + } bs; + unsigned long long val64; +} u_qu_pdm_host_que_thd_cfg; + + +/* + */ +typedef union { + struct { + unsigned long long sp_rsvd_th : 16; // [15:0] + unsigned long long sp_fc_th_dif : 8; // [23:16] + unsigned long long sp_fc_th_on : 16; // [39:24] + unsigned long long resv0 : 24; // [63:40] + } bs; + unsigned long long val64; +} u_qu_pdm_host_pri_thd_cfg; + + +/* + */ +typedef union { + struct { + unsigned long long port_rsvd_th : 16; // [15:0] + unsigned long long port_fc_th_dif : 8; // [23:16] + unsigned long long port_fc_th_on : 16; // [39:24] + unsigned long long resv0 : 24; // [63:40] + } bs; + unsigned long long val64; +} u_qu_pdm_host_port_thd_cfg; + +/* + */ +typedef union { + struct { + unsigned long long sg_rsvd_th : 16; // [15:0] + unsigned long long sg_fc_th_dif : 8; // [23:16] + unsigned long long sg_fc_th_on : 16; // [39:24] + unsigned long long resv0 : 24; // [63:40] + } bs; + unsigned long long val64; +} u_qu_pdm_host_srv_grp_thd_cfg; + +typedef union { + struct { + unsigned int ep_bp_th_dif : 8; // [7:0] + unsigned int ep_bp_th_on : 16; // [23:8] + unsigned int rsv : 8; // [31:24] + } bs; + + unsigned int val32; +} u_qu_pdm_host_ep_grp_thd_cfg; + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* __cplusplus */ + +#endif /* HINIC3_CSR_ADDR_COMMON_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_c_union_define.h new file mode 100644 index 000000000..c07c6d582 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_c_union_define.h @@ -0,0 +1,1062 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : icdq_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/01/20 15:06:21 Create file +// ****************************************************************************** + +#ifndef ICDQ_C_UNION_DEFINE_H +#define ICDQ_C_UNION_DEFINE_H + +/* Define the union csr_icdq_mode0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 8; /* [7:0] */ + u32 rsv_1 : 8; /* [15:8] */ + u32 rsv_2 : 3; /* [18:16] */ + u32 rsv_3 : 3; /* [21:19] */ + u32 csr_icdq_mem_init_start : 1; /* [22] */ + u32 csr_icdq_pru_alter_time : 1; /* [23] */ + u32 csr_icdq_mem_ecc_bypass : 1; /* [24] */ + u32 csr_icdq_ram_uncrt_err2itf_en : 1; /* [25] */ + u32 csr_icdq_other_uncrt_err2itf_en : 1; /* [26] */ + u32 csr_icdq_mem_ecc_req : 2; /* [28:27] */ + u32 csr_icdq_fqid_vf : 1; /* [29] */ + u32 csr_icdq_partial_col_max_num : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_mode0_u; + +/* Define the union csr_icdq_mode1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_strong_col_max_num : 4; /* [3:0] */ + u32 csr_icdq_real_dpl_pcnum_ctrl : 1; /* [4] */ + u32 csr_icdq_fqid_0 : 1; /* [5] */ + u32 csr_icdq_lbf_mode_sel : 2; /* [7:6] */ + u32 csr_icdq_quf_pg_cfg : 2; /* [9:8] */ + u32 csr_icdq_2k_vf_mode : 1; /* [10] */ + u32 csr_icdq_wred_pps_mode : 1; /* [11] */ + u32 csr_icdq_wred_plen : 16; /* [27:12] */ + u32 rsv_4 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_mode1_u; + +/* Define the union csr_icdq_wrr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_dsp_weight : 8; /* [7:0] */ + u32 csr_icdq_rxf_weight : 8; /* [15:8] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_wrr_u; + +/* Define the union csr_icdq_cfp_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_cfp_num : 12; /* [11:0] */ + u32 csr_icdq_nreal_dpl_pcnum : 4; /* [15:12] */ + u32 csr_icdq_nreal_dpl_plen : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_cfp_num_u; + +/* Define the union csr_icdq_pqm_ep_bitmap0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_port0_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_port1_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_port2_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_port3_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap0_u; + +/* Define the union csr_icdq_pqm_ep_bitmap1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_port4_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_port5_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_port6_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_port7_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap1_u; + +/* Define the union csr_icdq_pqm_ep_bitmap2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_port8_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_port9_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_port10_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_port11_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap2_u; + +/* Define the union csr_icdq_pqm_ep_bitmap3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_port12_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_port13_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_port14_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_port15_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap3_u; + +/* Define the union csr_icdq_pqm_ep_bitmap4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_ep0_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_ep1_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_ep2_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_ep3_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap4_u; + +/* Define the union csr_icdq_pqm_ep_bitmap5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_ep4_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_ep5_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_ep6_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_ep7_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap5_u; + +/* Define the union csr_icdq_pqm_ep_bitmap6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_ep8_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_ep9_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_ep10_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_ep11_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap6_u; + +/* Define the union csr_icdq_pqm_ep_bitmap7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_ep12_2_ep_bm : 8; /* [7:0] */ + u32 csr_icdq_ep13_2_ep_bm : 8; /* [15:8] */ + u32 csr_icdq_ep14_2_ep_bm : 8; /* [23:16] */ + u32 csr_icdq_ep15_2_ep_bm : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_ep_bitmap7_u; + +/* Define the union csr_icdq_fc_pro_typ_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_fc_pro_typ : 7; /* [6:0] */ + u32 rsv_6 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_fc_pro_typ_u; + +/* Define the union csr_icdq_sfifo_af0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_stffq0_opn_af_th : 8; /* [7:0] */ + u32 sfifo_stffq1_opn_af_th : 8; /* [15:8] */ + u32 sfifo_stffq0_rls_af_th : 8; /* [23:16] */ + u32 sfifo_stffq1_rls_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_af0_u; + +/* Define the union csr_icdq_sfifo_af1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_pru_af_th : 8; /* [7:0] */ + u32 sfifo_icq_af_th : 8; /* [15:8] */ + u32 sfifo_idq_af_th : 8; /* [23:16] */ + u32 sfifo_dsp_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_af1_u; + +/* Define the union csr_icdq_sfifo_af2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_rxf_af_th : 8; /* [7:0] */ + u32 sfifo_rul_mem_cflict_af_th : 8; /* [15:8] */ + u32 sfifo_drp_af_th : 8; /* [23:16] */ + u32 sfifo_cpd_af_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_af2_u; + +/* Define the union csr_icdq_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_init_done : 1; /* [0] */ + u32 rsv_7 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_mem_init_done_u; + +/* Define the union csr_icdq_wred_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_wred_drp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_wred_drop_cnt_u; + +/* Define the union csr_icdq_dsp_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_dsp_drp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_dsp_drop_cnt_u; + +/* Define the union csr_icdq_dsp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_dsp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_dsp_cnt_u; + +/* Define the union csr_icdq_rxf_sop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_rxf_sop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_rxf_sop_cnt_u; + +/* Define the union csr_icdq_rxf_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_rxf_eop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_rxf_eop_cnt_u; + +/* Define the union csr_icdq_pthru_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_pthru : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pthru_cnt_u; + +/* Define the union csr_icdq_mem_ecc_1bit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_mem_1bit_ecc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_mem_ecc_1bit_cnt_u; + +/* Define the union csr_icdq_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_8 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_9 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int_vector_u; + +/* Define the union csr_icdq_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_10 : 10; /* [15:6] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int_u; + +/* Define the union csr_icdq_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 6; /* [5:0] */ + u32 rsv_11 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int_en_u; + +/* Define the union csr_icdq_int0_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_deq_abnml : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 icdq_int0_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int0_sticky_u; + +/* Define the union csr_icdq_int1_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_fifo_overflow : 1; /* [0] */ + u32 int_insrt1 : 1; /* [1] */ + u32 icdq_int1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int1_sticky_u; + +/* Define the union csr_icdq_int2_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_fifo_underflow : 1; /* [0] */ + u32 int_insrt2 : 1; /* [1] */ + u32 icdq_int2_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int2_sticky_u; + +/* Define the union csr_icdq_int3_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_2bit : 1; /* [0] */ + u32 int_insrt3 : 1; /* [1] */ + u32 icdq_int3_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int3_sticky_u; + +/* Define the union csr_icdq_int4_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_1bit : 1; /* [0] */ + u32 int_insrt4 : 1; /* [1] */ + u32 icdq_int4_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_int4_sticky_u; + +/* Define the union csr_icdq_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_ctrl_u; + +/* Define the union csr_icdq_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_timeout_u; + +/* Define the union csr_icdq_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat0_u; + +/* Define the union csr_icdq_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat1_u; + +/* Define the union csr_icdq_indrect_dat2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat2_u; + +/* Define the union csr_icdq_indrect_dat3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat3_u; + +/* Define the union csr_icdq_indrect_dat4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat4_u; + +/* Define the union csr_icdq_indrect_dat5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat5_u; + +/* Define the union csr_icdq_indrect_dat6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat6_u; + +/* Define the union csr_icdq_indrect_dat7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat7_u; + +/* Define the union csr_icdq_indrect_dat8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat8_u; + +/* Define the union csr_icdq_indrect_dat9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat9_u; + +/* Define the union csr_icdq_indrect_dat10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat10_u; + +/* Define the union csr_icdq_indrect_dat11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat11_u; + +/* Define the union csr_icdq_indrect_dat12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat12_u; + +/* Define the union csr_icdq_indrect_dat13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat13_u; + +/* Define the union csr_icdq_indrect_dat14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat14_u; + +/* Define the union csr_icdq_indrect_dat15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_indrect_data15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_indrect_dat15_u; + +/* Define the union csr_icdq_sfifo_fill0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_stffq0_opn_fill : 8; /* [7:0] */ + u32 sfifo_stffq1_opn_fill : 8; /* [15:8] */ + u32 sfifo_stffq0_rls_fill : 8; /* [23:16] */ + u32 sfifo_stffq1_rls_fill : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_fill0_u; + +/* Define the union csr_icdq_sfifo_fill1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_pru_fill : 8; /* [7:0] */ + u32 sfifo_icq_fill : 8; /* [15:8] */ + u32 sfifo_idq_fill : 8; /* [23:16] */ + u32 sfifo_dsp_fill : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_fill1_u; + +/* Define the union csr_icdq_sfifo_fill2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sfifo_rxf_fill : 8; /* [7:0] */ + u32 sfifo_rul_mem_cflict_fill : 8; /* [15:8] */ + u32 sfifo_drp_fill : 8; /* [23:16] */ + u32 sfifo_cpd_fill : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sfifo_fill2_u; + +/* Define the union csr_icdq_latency_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_icdq_sample_mode : 1; /* [0] */ + u32 csr_icdq_spec_port_en : 1; /* [1] */ + u32 csr_icdq_done_clr : 1; /* [2] */ + u32 rsv_12 : 1; /* [3] */ + u32 csr_icdq_spec_port_num : 4; /* [7:4] */ + u32 csr_icdq_spec_pptr_typ : 8; /* [15:8] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_latency_cfg_u; + +/* Define the union csr_icdq_latency_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_sample_done : 1; /* [0] */ + u32 rsv_14 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_latency_sta_u; + +/* Define the union csr_icdq_sample_tmr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_sample_tmr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_sample_tmr_u; + +/* Define the union csr_icdq_bp0_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_stlfq_dsp_bp : 1; /* [0] */ + u32 icdq_stffq0_opn_bp : 1; /* [1] */ + u32 icdq_stffq1_opn_bp : 1; /* [2] */ + u32 icdq_stffq0_rls_bp : 1; /* [3] */ + u32 icdq_stffq1_rls_bp : 1; /* [4] */ + u32 stfiq_icdq_sqr_bp : 1; /* [5] */ + u32 icdq_csr_opn_icq_bp : 1; /* [6] */ + u32 icdq_csr_opn_idq_bp : 1; /* [7] */ + u32 icdq_csr_ele_icq_bp : 1; /* [8] */ + u32 rsv_15 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_bp0_sta_u; + +/* Define the union csr_icdq_bp1_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_sqd_ep_bp : 16; /* [15:0] */ + u32 icdq_csr_sqd_port_bp : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_bp1_sta_u; + +/* Define the union csr_icdq_pqm_eqs_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_pqm_eqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_eqs_num_u; + +/* Define the union csr_icdq_pqm_dqr_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_pqm_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_dqr_num_u; + +/* Define the union csr_icdq_pqm_dqs_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_pqm_dqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_dqs_num_u; + +/* Define the union csr_icdq_pqm_dpl_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_pqm_dpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_pqm_dpl_num_u; + +/* Define the union csr_icdq_stfiq_enqx_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_stfiq_enqx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_stfiq_enqx_num_u; + +/* Define the union csr_icdq_stfiq_enqy_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_stfiq_enqy_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_stfiq_enqy_num_u; + +/* Define the union csr_icdq_cfp_dqr_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icdq_csr_cfp_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icdq_cfp_dqr_num_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_icdq_mode0_u icdq_mode0; /* 0 */ + volatile csr_icdq_mode1_u icdq_mode1; /* 4 */ + volatile csr_icdq_wrr_u icdq_wrr; /* 8 */ + volatile csr_icdq_cfp_num_u icdq_cfp_num; /* C */ + volatile csr_icdq_pqm_ep_bitmap0_u icdq_pqm_ep_bitmap0; /* 10 */ + volatile csr_icdq_pqm_ep_bitmap1_u icdq_pqm_ep_bitmap1; /* 14 */ + volatile csr_icdq_pqm_ep_bitmap2_u icdq_pqm_ep_bitmap2; /* 18 */ + volatile csr_icdq_pqm_ep_bitmap3_u icdq_pqm_ep_bitmap3; /* 1C */ + volatile csr_icdq_pqm_ep_bitmap4_u icdq_pqm_ep_bitmap4; /* 20 */ + volatile csr_icdq_pqm_ep_bitmap5_u icdq_pqm_ep_bitmap5; /* 24 */ + volatile csr_icdq_pqm_ep_bitmap6_u icdq_pqm_ep_bitmap6; /* 28 */ + volatile csr_icdq_pqm_ep_bitmap7_u icdq_pqm_ep_bitmap7; /* 2C */ + volatile csr_icdq_fc_pro_typ_u icdq_fc_pro_typ; /* 30 */ + volatile csr_icdq_sfifo_af0_u icdq_sfifo_af0; /* 34 */ + volatile csr_icdq_sfifo_af1_u icdq_sfifo_af1; /* 38 */ + volatile csr_icdq_sfifo_af2_u icdq_sfifo_af2; /* 3C */ + volatile csr_icdq_mem_init_done_u icdq_mem_init_done; /* 40 */ + volatile csr_icdq_wred_drop_cnt_u icdq_wred_drop_cnt; /* 44 */ + volatile csr_icdq_dsp_drop_cnt_u icdq_dsp_drop_cnt; /* 48 */ + volatile csr_icdq_dsp_cnt_u icdq_dsp_cnt; /* 4C */ + volatile csr_icdq_rxf_sop_cnt_u icdq_rxf_sop_cnt; /* 50 */ + volatile csr_icdq_rxf_eop_cnt_u icdq_rxf_eop_cnt; /* 54 */ + volatile csr_icdq_pthru_cnt_u icdq_pthru_cnt; /* 58 */ + volatile csr_icdq_mem_ecc_1bit_cnt_u icdq_mem_ecc_1bit_cnt; /* 5C */ + volatile csr_icdq_int_vector_u icdq_int_vector; /* 60 */ + volatile csr_icdq_int_u icdq_int; /* 64 */ + volatile csr_icdq_int_en_u icdq_int_en; /* 68 */ + volatile csr_icdq_int0_sticky_u icdq_int0_sticky; /* 6C */ + volatile csr_icdq_int1_sticky_u icdq_int1_sticky; /* 70 */ + volatile csr_icdq_int2_sticky_u icdq_int2_sticky; /* 74 */ + volatile csr_icdq_int3_sticky_u icdq_int3_sticky; /* 78 */ + volatile csr_icdq_int4_sticky_u icdq_int4_sticky; /* 7C */ + volatile csr_icdq_indrect_ctrl_u icdq_indrect_ctrl; /* 80 */ + volatile csr_icdq_indrect_timeout_u icdq_indrect_timeout; /* 84 */ + volatile csr_icdq_indrect_dat0_u icdq_indrect_dat0; /* 88 */ + volatile csr_icdq_indrect_dat1_u icdq_indrect_dat1; /* 8C */ + volatile csr_icdq_indrect_dat2_u icdq_indrect_dat2; /* 90 */ + volatile csr_icdq_indrect_dat3_u icdq_indrect_dat3; /* 94 */ + volatile csr_icdq_indrect_dat4_u icdq_indrect_dat4; /* 98 */ + volatile csr_icdq_indrect_dat5_u icdq_indrect_dat5; /* 9C */ + volatile csr_icdq_indrect_dat6_u icdq_indrect_dat6; /* A0 */ + volatile csr_icdq_indrect_dat7_u icdq_indrect_dat7; /* A4 */ + volatile csr_icdq_indrect_dat8_u icdq_indrect_dat8; /* A8 */ + volatile csr_icdq_indrect_dat9_u icdq_indrect_dat9; /* AC */ + volatile csr_icdq_indrect_dat10_u icdq_indrect_dat10; /* B0 */ + volatile csr_icdq_indrect_dat11_u icdq_indrect_dat11; /* B4 */ + volatile csr_icdq_indrect_dat12_u icdq_indrect_dat12; /* B8 */ + volatile csr_icdq_indrect_dat13_u icdq_indrect_dat13; /* BC */ + volatile csr_icdq_indrect_dat14_u icdq_indrect_dat14; /* C0 */ + volatile csr_icdq_indrect_dat15_u icdq_indrect_dat15; /* C4 */ + volatile csr_icdq_sfifo_fill0_u icdq_sfifo_fill0; /* C8 */ + volatile csr_icdq_sfifo_fill1_u icdq_sfifo_fill1; /* CC */ + volatile csr_icdq_sfifo_fill2_u icdq_sfifo_fill2; /* D0 */ + volatile csr_icdq_latency_cfg_u icdq_latency_cfg; /* D4 */ + volatile csr_icdq_latency_sta_u icdq_latency_sta; /* D8 */ + volatile csr_icdq_sample_tmr_u icdq_sample_tmr; /* DC */ + volatile csr_icdq_bp0_sta_u icdq_bp0_sta; /* E0 */ + volatile csr_icdq_bp1_sta_u icdq_bp1_sta; /* E4 */ + volatile csr_icdq_pqm_eqs_num_u icdq_pqm_eqs_num; /* E8 */ + volatile csr_icdq_pqm_dqr_num_u icdq_pqm_dqr_num; /* EC */ + volatile csr_icdq_pqm_dqs_num_u icdq_pqm_dqs_num; /* F0 */ + volatile csr_icdq_pqm_dpl_num_u icdq_pqm_dpl_num; /* F4 */ + volatile csr_icdq_stfiq_enqx_num_u icdq_stfiq_enqx_num; /* F8 */ + volatile csr_icdq_stfiq_enqy_num_u icdq_stfiq_enqy_num; /* FC */ + volatile csr_icdq_cfp_dqr_num_u icdq_cfp_dqr_num; /* 100 */ +} S_qu_icdq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_icdq_csr */ +extern volatile S_qu_icdq_csr_REGS_TYPE *gopqu_icdq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetICDQ_MODE0_csr_icdq_mem_init_start(unsigned int ucsr_icdq_mem_init_start); +int iSetICDQ_MODE0_csr_icdq_pru_alter_time(unsigned int ucsr_icdq_pru_alter_time); +int iSetICDQ_MODE0_csr_icdq_mem_ecc_bypass(unsigned int ucsr_icdq_mem_ecc_bypass); +int iSetICDQ_MODE0_csr_icdq_ram_uncrt_err2itf_en(unsigned int ucsr_icdq_ram_uncrt_err2itf_en); +int iSetICDQ_MODE0_csr_icdq_other_uncrt_err2itf_en(unsigned int ucsr_icdq_other_uncrt_err2itf_en); +int iSetICDQ_MODE0_csr_icdq_mem_ecc_req(unsigned int ucsr_icdq_mem_ecc_req); +int iSetICDQ_MODE0_csr_icdq_fqid_vf(unsigned int ucsr_icdq_fqid_vf); +int iSetICDQ_MODE0_csr_icdq_partial_col_max_num(unsigned int ucsr_icdq_partial_col_max_num); +int iSetICDQ_MODE1_csr_icdq_strong_col_max_num(unsigned int ucsr_icdq_strong_col_max_num); +int iSetICDQ_MODE1_csr_icdq_real_dpl_pcnum_ctrl(unsigned int ucsr_icdq_real_dpl_pcnum_ctrl); +int iSetICDQ_MODE1_csr_icdq_fqid_0(unsigned int ucsr_icdq_fqid_0); +int iSetICDQ_MODE1_csr_icdq_lbf_mode_sel(unsigned int ucsr_icdq_lbf_mode_sel); +int iSetICDQ_MODE1_csr_icdq_quf_pg_cfg(unsigned int ucsr_icdq_quf_pg_cfg); +int iSetICDQ_MODE1_csr_icdq_2k_vf_mode(unsigned int ucsr_icdq_2k_vf_mode); +int iSetICDQ_MODE1_csr_icdq_wred_pps_mode(unsigned int ucsr_icdq_wred_pps_mode); +int iSetICDQ_MODE1_csr_icdq_wred_plen(unsigned int ucsr_icdq_wred_plen); +int iSetICDQ_WRR_csr_icdq_dsp_weight(unsigned int ucsr_icdq_dsp_weight); +int iSetICDQ_WRR_csr_icdq_rxf_weight(unsigned int ucsr_icdq_rxf_weight); +int iSetICDQ_CFP_NUM_csr_icdq_cfp_num(unsigned int ucsr_icdq_cfp_num); +int iSetICDQ_CFP_NUM_csr_icdq_nreal_dpl_pcnum(unsigned int ucsr_icdq_nreal_dpl_pcnum); +int iSetICDQ_CFP_NUM_csr_icdq_nreal_dpl_plen(unsigned int ucsr_icdq_nreal_dpl_plen); +int iSetICDQ_PQM_EP_BITMAP0_csr_icdq_port0_2_ep_bm(unsigned int ucsr_icdq_port0_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP0_csr_icdq_port1_2_ep_bm(unsigned int ucsr_icdq_port1_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP0_csr_icdq_port2_2_ep_bm(unsigned int ucsr_icdq_port2_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP0_csr_icdq_port3_2_ep_bm(unsigned int ucsr_icdq_port3_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP1_csr_icdq_port4_2_ep_bm(unsigned int ucsr_icdq_port4_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP1_csr_icdq_port5_2_ep_bm(unsigned int ucsr_icdq_port5_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP1_csr_icdq_port6_2_ep_bm(unsigned int ucsr_icdq_port6_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP1_csr_icdq_port7_2_ep_bm(unsigned int ucsr_icdq_port7_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP2_csr_icdq_port8_2_ep_bm(unsigned int ucsr_icdq_port8_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP2_csr_icdq_port9_2_ep_bm(unsigned int ucsr_icdq_port9_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP2_csr_icdq_port10_2_ep_bm(unsigned int ucsr_icdq_port10_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP2_csr_icdq_port11_2_ep_bm(unsigned int ucsr_icdq_port11_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP3_csr_icdq_port12_2_ep_bm(unsigned int ucsr_icdq_port12_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP3_csr_icdq_port13_2_ep_bm(unsigned int ucsr_icdq_port13_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP3_csr_icdq_port14_2_ep_bm(unsigned int ucsr_icdq_port14_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP3_csr_icdq_port15_2_ep_bm(unsigned int ucsr_icdq_port15_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP4_csr_icdq_ep0_2_ep_bm(unsigned int ucsr_icdq_ep0_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP4_csr_icdq_ep1_2_ep_bm(unsigned int ucsr_icdq_ep1_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP4_csr_icdq_ep2_2_ep_bm(unsigned int ucsr_icdq_ep2_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP4_csr_icdq_ep3_2_ep_bm(unsigned int ucsr_icdq_ep3_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP5_csr_icdq_ep4_2_ep_bm(unsigned int ucsr_icdq_ep4_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP5_csr_icdq_ep5_2_ep_bm(unsigned int ucsr_icdq_ep5_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP5_csr_icdq_ep6_2_ep_bm(unsigned int ucsr_icdq_ep6_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP5_csr_icdq_ep7_2_ep_bm(unsigned int ucsr_icdq_ep7_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP6_csr_icdq_ep8_2_ep_bm(unsigned int ucsr_icdq_ep8_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP6_csr_icdq_ep9_2_ep_bm(unsigned int ucsr_icdq_ep9_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP6_csr_icdq_ep10_2_ep_bm(unsigned int ucsr_icdq_ep10_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP6_csr_icdq_ep11_2_ep_bm(unsigned int ucsr_icdq_ep11_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP7_csr_icdq_ep12_2_ep_bm(unsigned int ucsr_icdq_ep12_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP7_csr_icdq_ep13_2_ep_bm(unsigned int ucsr_icdq_ep13_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP7_csr_icdq_ep14_2_ep_bm(unsigned int ucsr_icdq_ep14_2_ep_bm); +int iSetICDQ_PQM_EP_BITMAP7_csr_icdq_ep15_2_ep_bm(unsigned int ucsr_icdq_ep15_2_ep_bm); +int iSetICDQ_FC_PRO_TYP_csr_icdq_fc_pro_typ(unsigned int ucsr_icdq_fc_pro_typ); +int iSetICDQ_SFIFO_AF0_sfifo_stffq0_opn_af_th(unsigned int usfifo_stffq0_opn_af_th); +int iSetICDQ_SFIFO_AF0_sfifo_stffq1_opn_af_th(unsigned int usfifo_stffq1_opn_af_th); +int iSetICDQ_SFIFO_AF0_sfifo_stffq0_rls_af_th(unsigned int usfifo_stffq0_rls_af_th); +int iSetICDQ_SFIFO_AF0_sfifo_stffq1_rls_af_th(unsigned int usfifo_stffq1_rls_af_th); +int iSetICDQ_SFIFO_AF1_sfifo_pru_af_th(unsigned int usfifo_pru_af_th); +int iSetICDQ_SFIFO_AF1_sfifo_icq_af_th(unsigned int usfifo_icq_af_th); +int iSetICDQ_SFIFO_AF1_sfifo_idq_af_th(unsigned int usfifo_idq_af_th); +int iSetICDQ_SFIFO_AF1_sfifo_dsp_af_th(unsigned int usfifo_dsp_af_th); +int iSetICDQ_SFIFO_AF2_sfifo_rxf_af_th(unsigned int usfifo_rxf_af_th); +int iSetICDQ_SFIFO_AF2_sfifo_rul_mem_cflict_af_th(unsigned int usfifo_rul_mem_cflict_af_th); +int iSetICDQ_SFIFO_AF2_sfifo_drp_af_th(unsigned int usfifo_drp_af_th); +int iSetICDQ_SFIFO_AF2_sfifo_cpd_af_th(unsigned int usfifo_cpd_af_th); +int iSetICDQ_MEM_INIT_DONE_mem_init_done(unsigned int umem_init_done); +int iSetICDQ_WRED_DROP_CNT_icdq_csr_wred_drp(unsigned int uicdq_csr_wred_drp); +int iSetICDQ_DSP_DROP_CNT_icdq_csr_dsp_drp(unsigned int uicdq_csr_dsp_drp); +int iSetICDQ_DSP_CNT_icdq_csr_dsp(unsigned int uicdq_csr_dsp); +int iSetICDQ_RXF_SOP_CNT_icdq_csr_rxf_sop(unsigned int uicdq_csr_rxf_sop); +int iSetICDQ_RXF_EOP_CNT_icdq_csr_rxf_eop(unsigned int uicdq_csr_rxf_eop); +int iSetICDQ_PTHRU_CNT_icdq_csr_pthru(unsigned int uicdq_csr_pthru); +int iSetICDQ_MEM_ECC_1BIT_CNT_icdq_csr_mem_1bit_ecc(unsigned int uicdq_csr_mem_1bit_ecc); +int iSetICDQ_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetICDQ_INT_VECTOR_enable(unsigned int uenable); +int iSetICDQ_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetICDQ_INT_int_data(unsigned int uint_data); +int iSetICDQ_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetICDQ_INT_EN_int_en(unsigned int uint_en); +int iSetICDQ_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetICDQ_INT0_STICKY_icdq_deq_abnml(unsigned int uicdq_deq_abnml); +int iSetICDQ_INT0_STICKY_int_insrt0(unsigned int uint_insrt0); +int iSetICDQ_INT0_STICKY_icdq_int0_sticky(unsigned int uicdq_int0_sticky); +int iSetICDQ_INT1_STICKY_icdq_fifo_overflow(unsigned int uicdq_fifo_overflow); +int iSetICDQ_INT1_STICKY_int_insrt1(unsigned int uint_insrt1); +int iSetICDQ_INT1_STICKY_icdq_int1_sticky(unsigned int uicdq_int1_sticky); +int iSetICDQ_INT2_STICKY_icdq_fifo_underflow(unsigned int uicdq_fifo_underflow); +int iSetICDQ_INT2_STICKY_int_insrt2(unsigned int uint_insrt2); +int iSetICDQ_INT2_STICKY_icdq_int2_sticky(unsigned int uicdq_int2_sticky); +int iSetICDQ_INT3_STICKY_mem_ecc_2bit(unsigned int umem_ecc_2bit); +int iSetICDQ_INT3_STICKY_int_insrt3(unsigned int uint_insrt3); +int iSetICDQ_INT3_STICKY_icdq_int3_sticky(unsigned int uicdq_int3_sticky); +int iSetICDQ_INT4_STICKY_mem_ecc_1bit(unsigned int umem_ecc_1bit); +int iSetICDQ_INT4_STICKY_int_insrt4(unsigned int uint_insrt4); +int iSetICDQ_INT4_STICKY_icdq_int4_sticky(unsigned int uicdq_int4_sticky); +int iSetICDQ_INDRECT_CTRL_csr_icdq_indrect_ctrl(unsigned int ucsr_icdq_indrect_ctrl); +int iSetICDQ_INDRECT_TIMEOUT_csr_icdq_indrect_timeout(unsigned int ucsr_icdq_indrect_timeout); +int iSetICDQ_INDRECT_DAT0_csr_icdq_indrect_data0(unsigned int ucsr_icdq_indrect_data0); +int iSetICDQ_INDRECT_DAT1_csr_icdq_indrect_data1(unsigned int ucsr_icdq_indrect_data1); +int iSetICDQ_INDRECT_DAT2_csr_icdq_indrect_data2(unsigned int ucsr_icdq_indrect_data2); +int iSetICDQ_INDRECT_DAT3_csr_icdq_indrect_data3(unsigned int ucsr_icdq_indrect_data3); +int iSetICDQ_INDRECT_DAT4_csr_icdq_indrect_data4(unsigned int ucsr_icdq_indrect_data4); +int iSetICDQ_INDRECT_DAT5_csr_icdq_indrect_data5(unsigned int ucsr_icdq_indrect_data5); +int iSetICDQ_INDRECT_DAT6_csr_icdq_indrect_data6(unsigned int ucsr_icdq_indrect_data6); +int iSetICDQ_INDRECT_DAT7_csr_icdq_indrect_data7(unsigned int ucsr_icdq_indrect_data7); +int iSetICDQ_INDRECT_DAT8_csr_icdq_indrect_data8(unsigned int ucsr_icdq_indrect_data8); +int iSetICDQ_INDRECT_DAT9_csr_icdq_indrect_data9(unsigned int ucsr_icdq_indrect_data9); +int iSetICDQ_INDRECT_DAT10_csr_icdq_indrect_data10(unsigned int ucsr_icdq_indrect_data10); +int iSetICDQ_INDRECT_DAT11_csr_icdq_indrect_data11(unsigned int ucsr_icdq_indrect_data11); +int iSetICDQ_INDRECT_DAT12_csr_icdq_indrect_data12(unsigned int ucsr_icdq_indrect_data12); +int iSetICDQ_INDRECT_DAT13_csr_icdq_indrect_data13(unsigned int ucsr_icdq_indrect_data13); +int iSetICDQ_INDRECT_DAT14_csr_icdq_indrect_data14(unsigned int ucsr_icdq_indrect_data14); +int iSetICDQ_INDRECT_DAT15_csr_icdq_indrect_data15(unsigned int ucsr_icdq_indrect_data15); +int iSetICDQ_SFIFO_FILL0_sfifo_stffq0_opn_fill(unsigned int usfifo_stffq0_opn_fill); +int iSetICDQ_SFIFO_FILL0_sfifo_stffq1_opn_fill(unsigned int usfifo_stffq1_opn_fill); +int iSetICDQ_SFIFO_FILL0_sfifo_stffq0_rls_fill(unsigned int usfifo_stffq0_rls_fill); +int iSetICDQ_SFIFO_FILL0_sfifo_stffq1_rls_fill(unsigned int usfifo_stffq1_rls_fill); +int iSetICDQ_SFIFO_FILL1_sfifo_pru_fill(unsigned int usfifo_pru_fill); +int iSetICDQ_SFIFO_FILL1_sfifo_icq_fill(unsigned int usfifo_icq_fill); +int iSetICDQ_SFIFO_FILL1_sfifo_idq_fill(unsigned int usfifo_idq_fill); +int iSetICDQ_SFIFO_FILL1_sfifo_dsp_fill(unsigned int usfifo_dsp_fill); +int iSetICDQ_SFIFO_FILL2_sfifo_rxf_fill(unsigned int usfifo_rxf_fill); +int iSetICDQ_SFIFO_FILL2_sfifo_rul_mem_cflict_fill(unsigned int usfifo_rul_mem_cflict_fill); +int iSetICDQ_SFIFO_FILL2_sfifo_drp_fill(unsigned int usfifo_drp_fill); +int iSetICDQ_SFIFO_FILL2_sfifo_cpd_fill(unsigned int usfifo_cpd_fill); +int iSetICDQ_LATENCY_CFG_csr_icdq_sample_mode(unsigned int ucsr_icdq_sample_mode); +int iSetICDQ_LATENCY_CFG_csr_icdq_spec_port_en(unsigned int ucsr_icdq_spec_port_en); +int iSetICDQ_LATENCY_CFG_csr_icdq_done_clr(unsigned int ucsr_icdq_done_clr); +int iSetICDQ_LATENCY_CFG_csr_icdq_spec_port_num(unsigned int ucsr_icdq_spec_port_num); +int iSetICDQ_LATENCY_CFG_csr_icdq_spec_pptr_typ(unsigned int ucsr_icdq_spec_pptr_typ); +int iSetICDQ_LATENCY_STA_icdq_csr_sample_done(unsigned int uicdq_csr_sample_done); +int iSetICDQ_SAMPLE_TMR_icdq_csr_sample_tmr(unsigned int uicdq_csr_sample_tmr); +int iSetICDQ_BP0_STA_icdq_stlfq_dsp_bp(unsigned int uicdq_stlfq_dsp_bp); +int iSetICDQ_BP0_STA_icdq_stffq0_opn_bp(unsigned int uicdq_stffq0_opn_bp); +int iSetICDQ_BP0_STA_icdq_stffq1_opn_bp(unsigned int uicdq_stffq1_opn_bp); +int iSetICDQ_BP0_STA_icdq_stffq0_rls_bp(unsigned int uicdq_stffq0_rls_bp); +int iSetICDQ_BP0_STA_icdq_stffq1_rls_bp(unsigned int uicdq_stffq1_rls_bp); +int iSetICDQ_BP0_STA_stfiq_icdq_sqr_bp(unsigned int ustfiq_icdq_sqr_bp); +int iSetICDQ_BP0_STA_icdq_csr_opn_icq_bp(unsigned int uicdq_csr_opn_icq_bp); +int iSetICDQ_BP0_STA_icdq_csr_opn_idq_bp(unsigned int uicdq_csr_opn_idq_bp); +int iSetICDQ_BP0_STA_icdq_csr_ele_icq_bp(unsigned int uicdq_csr_ele_icq_bp); +int iSetICDQ_BP1_STA_icdq_csr_sqd_ep_bp(unsigned int uicdq_csr_sqd_ep_bp); +int iSetICDQ_BP1_STA_icdq_csr_sqd_port_bp(unsigned int uicdq_csr_sqd_port_bp); +int iSetICDQ_PQM_EQS_NUM_icdq_csr_pqm_eqs_cnt(unsigned int uicdq_csr_pqm_eqs_cnt); +int iSetICDQ_PQM_DQR_NUM_icdq_csr_pqm_dqr_cnt(unsigned int uicdq_csr_pqm_dqr_cnt); +int iSetICDQ_PQM_DQS_NUM_icdq_csr_pqm_dqs_cnt(unsigned int uicdq_csr_pqm_dqs_cnt); +int iSetICDQ_PQM_DPL_NUM_icdq_csr_pqm_dpl_cnt(unsigned int uicdq_csr_pqm_dpl_cnt); +int iSetICDQ_STFIQ_ENQX_NUM_icdq_csr_stfiq_enqx_cnt(unsigned int uicdq_csr_stfiq_enqx_cnt); +int iSetICDQ_STFIQ_ENQY_NUM_icdq_csr_stfiq_enqy_cnt(unsigned int uicdq_csr_stfiq_enqy_cnt); +int iSetICDQ_CFP_DQR_NUM_icdq_csr_cfp_dqr_cnt(unsigned int uicdq_csr_cfp_dqr_cnt); + + +#endif // ICDQ_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_reg_offset.h new file mode 100644 index 000000000..cf46fb517 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/icdq_reg_offset.h @@ -0,0 +1,114 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : icdq_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/01/20 15:06:21 Create file +// ****************************************************************************** + +#ifndef ICDQ_REG_OFFSET_H +#define ICDQ_REG_OFFSET_H + +/* QU_ICDQ_CSR Base address of Module's Register */ +#define CSR_QU_ICDQ_CSR_BASE (0xA000) + +/* **************************************************************************** */ +/* QU_ICDQ_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_ICDQ_CSR_ICDQ_MODE0_REG (CSR_QU_ICDQ_CSR_BASE + 0x0) /* 模式配置寄存器 */ +#define CSR_QU_ICDQ_CSR_ICDQ_MODE1_REG (CSR_QU_ICDQ_CSR_BASE + 0x4) /* 模式配置寄存器 */ +#define CSR_QU_ICDQ_CSR_ICDQ_WRR_REG (CSR_QU_ICDQ_CSR_BASE + 0x8) /* rx fastpath与stl tile normalpath的权重配置 */ +#define CSR_QU_ICDQ_CSR_ICDQ_CFP_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xC) /* 发往网络侧或不需要PQM调度的ICQ的个数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP0_REG (CSR_QU_ICDQ_CSR_BASE + 0x10) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP1_REG (CSR_QU_ICDQ_CSR_BASE + 0x14) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP2_REG (CSR_QU_ICDQ_CSR_BASE + 0x18) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP3_REG (CSR_QU_ICDQ_CSR_BASE + 0x1C) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP4_REG (CSR_QU_ICDQ_CSR_BASE + 0x20) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP5_REG (CSR_QU_ICDQ_CSR_BASE + 0x24) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP6_REG (CSR_QU_ICDQ_CSR_BASE + 0x28) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EP_BITMAP7_REG (CSR_QU_ICDQ_CSR_BASE + 0x2C) /* 源EP/PORT到主机侧目的EP的bitmap映射 \ + */ +#define CSR_QU_ICDQ_CSR_ICDQ_FC_PRO_TYP_REG (CSR_QU_ICDQ_CSR_BASE + 0x30) /* fc协议的Pro_typ值 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_AF0_REG (CSR_QU_ICDQ_CSR_BASE + 0x34) /* FIFO几乎满配置。 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_AF1_REG (CSR_QU_ICDQ_CSR_BASE + 0x38) /* FIFO几乎满配置。 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_AF2_REG (CSR_QU_ICDQ_CSR_BASE + 0x3C) /* FIFO几乎满配置。 */ +#define CSR_QU_ICDQ_CSR_ICDQ_MEM_INIT_DONE_REG (CSR_QU_ICDQ_CSR_BASE + 0x40) /* 表项初始化完成。 */ +#define CSR_QU_ICDQ_CSR_ICDQ_WRED_DROP_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x44) /* 源网络侧报文WRED丢弃次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_DSP_DROP_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x48) /* 微码DSP时丢弃报文次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_DSP_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x4C) /* 微码DSP报文次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_RXF_SOP_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x50) /* 源网络侧报文SOP次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_RXF_EOP_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x54) /* 源网络侧报文EOP次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PTHRU_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x58) /* 被ICDQ PTHRU的报文个数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_MEM_ECC_1BIT_CNT_REG (CSR_QU_ICDQ_CSR_BASE + 0x5C) /* ICDQ内部RAM发生1BIT ECC的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT_VECTOR_REG (CSR_QU_ICDQ_CSR_BASE + 0x60) /* 中断向量 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT_REG (CSR_QU_ICDQ_CSR_BASE + 0x64) /* 中断状态 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT_EN_REG (CSR_QU_ICDQ_CSR_BASE + 0x68) /* 中断屏蔽 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT0_STICKY_REG (CSR_QU_ICDQ_CSR_BASE + 0x6C) /* 中断0的sticky信息 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT1_STICKY_REG (CSR_QU_ICDQ_CSR_BASE + 0x70) /* 中断1的sticky信息 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT2_STICKY_REG (CSR_QU_ICDQ_CSR_BASE + 0x74) /* 中断2的sticky信息 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT3_STICKY_REG (CSR_QU_ICDQ_CSR_BASE + 0x78) /* 中断3的sticky信息 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INT4_STICKY_REG (CSR_QU_ICDQ_CSR_BASE + 0x7C) /* 中断4的sticky信息 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_CTRL_REG (CSR_QU_ICDQ_CSR_BASE + 0x80) /* ICDQ间接寻址控制寄存器 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_TIMEOUT_REG (CSR_QU_ICDQ_CSR_BASE + 0x84) /* IQ间接寻址Timeout水线配置 */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT0_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x88) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT1_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x8C) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT2_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x90) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT3_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x94) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT4_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x98) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT5_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0x9C) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT6_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xA0) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT7_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xA4) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT8_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xA8) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT9_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xAC) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT10_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xB0) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT11_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xB4) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT12_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xB8) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT13_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xBC) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT14_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xC0) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_INDRECT_DAT15_REG \ + (CSR_QU_ICDQ_CSR_BASE + 0xC4) /* IQ memory indirect access write data or read data. */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_FILL0_REG (CSR_QU_ICDQ_CSR_BASE + 0xC8) /* FIFO内数据个数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_FILL1_REG (CSR_QU_ICDQ_CSR_BASE + 0xCC) /* FIFO内数据个数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SFIFO_FILL2_REG (CSR_QU_ICDQ_CSR_BASE + 0xD0) /* FIFO内数据个数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_LATENCY_CFG_REG (CSR_QU_ICDQ_CSR_BASE + 0xD4) /* ICDQ的时延采样DFX配置 */ +#define CSR_QU_ICDQ_CSR_ICDQ_LATENCY_STA_REG (CSR_QU_ICDQ_CSR_BASE + 0xD8) /* icdq的时延采样DFX状态 */ +#define CSR_QU_ICDQ_CSR_ICDQ_SAMPLE_TMR_REG (CSR_QU_ICDQ_CSR_BASE + 0xDC) /* icdq的时延采样DFX时间 */ +#define CSR_QU_ICDQ_CSR_ICDQ_BP0_STA_REG (CSR_QU_ICDQ_CSR_BASE + 0xE0) /* icdq外围接口反压状态 */ +#define CSR_QU_ICDQ_CSR_ICDQ_BP1_STA_REG (CSR_QU_ICDQ_CSR_BASE + 0xE4) /* icdq外围接口反压状态 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_EQS_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xE8) /* icdq向PQM提调度请求的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_DQR_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xEC) /* PQM向icdq发起调度的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_DQS_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xF0) /* icdq向PQM返回队列状态的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_PQM_DPL_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xF4) /* icdq向PQM返回队列状态的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_STFIQ_ENQX_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xF8) /* icdq向STFIQ入队X链的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_STFIQ_ENQY_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0xFC) /* icdq向STFIQ入队Y链的次数 */ +#define CSR_QU_ICDQ_CSR_ICDQ_CFP_DQR_NUM_REG (CSR_QU_ICDQ_CSR_BASE + 0x100) /* CFP调度器(非PQM)向icdq发起调度的次数 */ + +#endif // ICDQ_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_c_union_define.h new file mode 100644 index 000000000..af82b16ce --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_c_union_define.h @@ -0,0 +1,4805 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : Hi1823_hi1823_typedef.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2020/01/20 11:20:16 Create file +// ****************************************************************************** + +#ifndef IPSURX_C_UNION_DEFINE_H +#define IPSURX_C_UNION_DEFINE_H + +/* Define the union csr_ipsurx_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fpga_ver_u; + +/* Define the union csr_ipsurx_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_emu_ver_u; + +/* Define the union csr_ipsurx_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_init_start : 1; /* [0] */ + u32 rsv_0 : 2; /* [2:1] */ + u32 ipsurx_roceop_init_start : 1; /* [3] */ + u32 rsv_1 : 2; /* [5:4] */ + u32 ipsurx_vfidx_init_start : 1; /* [6] */ + u32 ipsurx_vftb_init_start : 1; /* [7] */ + u32 rsv_2 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_initctab_start_u; + +/* Define the union csr_ipsurx_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_init_done : 1; /* [0] */ + u32 rsv_3 : 2; /* [2:1] */ + u32 ipsurx_roceop_init_done : 1; /* [3] */ + u32 rsv_4 : 2; /* [5:4] */ + u32 ipsurx_vfidx_init_done : 1; /* [6] */ + u32 ipsurx_vftb_init_done : 1; /* [7] */ + u32 rsv_5 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_initctab_done_u; + +/* Define the union csr_ipsurx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_6 : 3; /* [26:24] */ + u32 ipsurx_int_enable : 1; /* [27] */ + u32 ipsurx_int_issue : 1; /* [28] */ + u32 rsv_7 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_int_vector_u; + +/* Define the union csr_ipsurx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_int_data : 6; /* [5:0] */ + u32 rsv_8 : 10; /* [15:6] */ + u32 ipsurx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_int_u; + +/* Define the union csr_ipsurx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_int_en : 6; /* [5:0] */ + u32 rsv_9 : 10; /* [15:6] */ + u32 ipsurx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_int_en_u; + +/* Define the union csr_ipsurx_ch_invld_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_invld_err : 1; /* [0] */ + u32 ipsurx_ch_invld_err_insrt : 1; /* [1] */ + u32 ipsurx_ch_invld_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ch_invld_err_u; + +/* Define the union csr_ipsurx_ram_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ucerr : 1; /* [0] */ + u32 ipsurx_ram_ucerr_insrt : 1; /* [1] */ + u32 ipsurx_ram_ucerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ucerr_u; + +/* Define the union csr_ipsurx_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_cerr : 1; /* [0] */ + u32 ipsurx_ram_cerr_insrt : 1; /* [1] */ + u32 ipsurx_ram_cerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_cerr_u; + +/* Define the union csr_ipsurx_fifo_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fifo_of_err : 1; /* [0] */ + u32 ipsurx_fifo_of_err_insrt : 1; /* [1] */ + u32 ipsurx_fifo_of_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fifo_of_err_u; + +/* Define the union csr_ipsurx_sop_eop_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_sop_eop_err : 1; /* [0] */ + u32 ipsurx_sop_eop_err_insrt : 1; /* [1] */ + u32 ipsurx_sop_eop_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_sop_eop_err_u; + +/* Define the union csr_ipsurx_parse_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_parse_err : 1; /* [0] */ + u32 ipsurx_parse_err_insrt : 1; /* [1] */ + u32 ipsurx_parse_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_parse_err_u; + +/* Define the union csr_ipsurx_err_type_int_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_err_type_int_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_err_type_int_mask_dw3_u; + +/* Define the union csr_ipsurx_err_type_int_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_err_type_int_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_err_type_int_mask_dw2_u; + +/* Define the union csr_ipsurx_err_type_int_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_err_type_int_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_err_type_int_mask_dw1_u; + +/* Define the union csr_ipsurx_err_type_int_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_err_type_int_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_err_type_int_mask_dw0_u; + +/* Define the union csr_ipsurx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_indrect_addr : 24; /* [23:0] */ + u32 ipsurx_indrect_tab : 4; /* [27:24] */ + u32 ipsurx_indrect_stat : 2; /* [29:28] */ + u32 ipsurx_indrect_mode : 1; /* [30] */ + u32 ipsurx_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_indrect_ctrl_u; + +/* Define the union csr_ipsurx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_indrect_timeout_u; + +/* Define the union csr_ipsurx_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_indrect_data_u; + +/* Define the union csr_ipsurx_cat_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_cvlan_tpid_sel : 5; /* [4:0] */ + u32 ipsurx_ch_cvlan : 1; /* [5] */ + u32 rsv_10 : 1; /* [6] */ + u32 ipsurx_ch_svlan_tpid_sel : 5; /* [11:7] */ + u32 ipsurx_ch_svlan : 1; /* [12] */ + u32 ipsurx_ch_dflt_vlan_ins : 1; /* [13] */ + u32 rsv_11 : 1; /* [14] */ + u32 ipsurx_ch_dsatag : 1; /* [15] */ + u32 ipsurx_ch_evtag_tpid_sel : 4; /* [19:16] */ + u32 ipsurx_ch_evtag : 2; /* [21:20] */ + u32 rsv_12 : 2; /* [23:22] */ + u32 ipsurx_ch_cpt_port_ctrl : 1; /* [24] */ + u32 ipsurx_ch_unknown_tag_en : 1; /* [25] */ + u32 ipsurx_ch_telemetry_en : 1; /* [26] */ + u32 ipsurx_ch_hcap_en : 1; /* [27] */ + u32 ipsurx_ch_1588v2_en : 1; /* [28] */ + u32 ipsurx_ch_type : 2; /* [30:29] */ + u32 ipsurx_ch_valid : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw0_u; + +/* Define the union csr_ipsurx_cat_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_ipv4_blindcs_en : 1; /* [0] */ + u32 ipsurx_ch_ipv4_nvme_rocev2_verify_en : 1; /* [1] */ + u32 ipsurx_ch_ipv4_nvme_rocev2_en : 1; /* [2] */ + u32 ipsurx_ch_nvme_sector_size : 1; /* [3] */ + u32 ipsurx_ch_ipv4_udp_len_chk_en : 1; /* [4] */ + u32 ipsurx_ch_ipv4_tcp_cs_chk_en : 1; /* [5] */ + u32 ipsurx_ch_ipv4_tcp_syn_chk_en : 1; /* [6] */ + u32 ipsurx_ch_ipv4_sctp_cs_chk_en : 1; /* [7] */ + u32 ipsurx_ch_ipv4_icmp_cs_chk_en : 1; /* [8] */ + u32 ipsurx_ch_ipv4_igmp_cs_chk_en : 1; /* [9] */ + u32 ipsurx_ch_rocev2_ipv4_udp_cs_chk_en : 1; /* [10] */ + u32 ipsurx_ch_rocev2_ipv4_fra_chk_en : 1; /* [11] */ + u32 ipsurx_ch_ipv4_udp_cs_chk_en : 1; /* [12] */ + u32 ipsurx_ch_natt_ipv4_udpcs_zero_chk_en : 1; /* [13] */ + u32 ipsurx_ch_ipv4_ip_cs_chk_en : 1; /* [14] */ + u32 ipsurx_ch_ipv4_dip_rsv_addr_chk_en : 1; /* [15] */ + u32 ipsurx_ch_ipv4_dip_zero_chk_en : 1; /* [16] */ + u32 ipsurx_ch_ipv4_dip_lb_chk_en : 1; /* [17] */ + u32 ipsurx_ch_ipv4_sip_lb_chk_en : 1; /* [18] */ + u32 ipsurx_ch_ipv4_sip_mc_chk_en : 1; /* [19] */ + u32 ipsurx_ch_ipv4_sip_dip_chk_en : 1; /* [20] */ + u32 ipsurx_ch_ipv4_ihl_chk_en : 1; /* [21] */ + u32 ipsurx_ch_ipv4_ver_chk_en : 1; /* [22] */ + u32 ipsurx_ch_ipv4_len_chk_en : 1; /* [23] */ + u32 rsv_13 : 4; /* [27:24] */ + u32 ipsurx_ch_8023_len_chk_en : 1; /* [28] */ + u32 ipsurx_ch_da_sa_equal_chk_en : 1; /* [29] */ + u32 ipsurx_ch_smac_chk_en : 1; /* [30] */ + u32 ipsurx_ch_dmac_zero_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw1_u; + +/* Define the union csr_ipsurx_cat_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_fc_crc_chk_en : 1; /* [0] */ + u32 ipsurx_ch_roce_pkey_chk_en : 1; /* [1] */ + u32 ipsurx_ch_roce_tver_chk_en : 1; /* [2] */ + u32 ipsurx_ch_roce_icrc_chk_en : 1; /* [3] */ + u32 ipsurx_ch_roce_dqp_chk_en : 1; /* [4] */ + u32 ipsurx_ch_rocev1_len_chk_en : 1; /* [5] */ + u32 ipsurx_ch_rocev1_sgid_chk_en : 1; /* [6] */ + u32 ipsurx_ch_rocev1_dgid_chk_en : 1; /* [7] */ + u32 ipsurx_ch_rocev1_nxhdr_chk_en : 1; /* [8] */ + u32 ipsurx_ch_rocev1_ipver_chk_en : 1; /* [9] */ + u32 ipsurx_ch_roce_ext_len_exc_chk_en : 1; /* [10] */ + u32 ipsurx_ch_tcp_ack_rst_syn_chk_en : 1; /* [11] */ + u32 ipsurx_ch_tcp_fin_ack_chk_en : 1; /* [12] */ + u32 ipsurx_ch_tcp_no_flag_chk_en : 1; /* [13] */ + u32 ipsurx_ch_tcp_syn_fin_chk_en : 1; /* [14] */ + u32 ipsurx_ch_tcp_do_chk_en : 1; /* [15] */ + u32 ipsurx_ch_ipv6_blindcs_en : 1; /* [16] */ + u32 ipsurx_ch_ipv6_nvme_rocev2_verify_en : 1; /* [17] */ + u32 ipsurx_ch_ipv6_nvme_rocev2_en : 1; /* [18] */ + u32 ipsurx_ch_nvme_rocev1_verify_en : 1; /* [19] */ + u32 ipsurx_ch_nvme_rocev1_en : 1; /* [20] */ + u32 ipsurx_ch_ipv6_tcp_cs_chk_en : 1; /* [21] */ + u32 ipsurx_ch_ipv6_tcp_syn_chk_en : 1; /* [22] */ + u32 ipsurx_ch_ipv6_sctp_cs_chk_en : 1; /* [23] */ + u32 ipsurx_ch_ipv6_icmp_cs_chk_en : 1; /* [24] */ + u32 ipsurx_ch_rocev2_ipv6_udp_cs_chk_en : 1; /* [25] */ + u32 ipsurx_ch_ipv6_udp_cs_chk_en : 1; /* [26] */ + u32 ipsurx_ch_ipv6_udpcs_zero_chk_en : 1; /* [27] */ + u32 ipsurx_ch_ipv6_dip_chk_en : 1; /* [28] */ + u32 ipsurx_ch_ipv6_sip_chk_en : 1; /* [29] */ + u32 ipsurx_ch_ipv6_ver_chk_en : 1; /* [30] */ + u32 ipsurx_ch_ipv6_len_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw2_u; + +/* Define the union csr_ipsurx_cat_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_pkt_len_chk_en : 1; /* [0] */ + u32 ipsurx_ch_min_pkt_len : 7; /* [7:1] */ + u32 ipsurx_ch_max_pkt_len : 14; /* [21:8] */ + u32 rsv_14 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw3_u; + +/* Define the union csr_ipsurx_cat_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_tunnel_da_sa_equal_chk_en : 1; /* [0] */ + u32 ipsurx_ch_tunnel_smac_chk_en : 1; /* [1] */ + u32 ipsurx_ch_tunnel_dmac_zero_chk_en : 1; /* [2] */ + u32 ipsurx_ch_tunnel_nvgre_cvlan_chk_en : 1; /* [3] */ + u32 rsv_15 : 4; /* [7:4] */ + u32 ipsurx_ch_tunnel_cvlan_tpid_sel : 5; /* [12:8] */ + u32 ipsurx_ch_tunnel_cvlan : 1; /* [13] */ + u32 ipsurx_ch_tunnel_svlan_tpid_sel : 5; /* [18:14] */ + u32 ipsurx_ch_tunnel_svlan : 1; /* [19] */ + u32 ipsurx_ch_tunnel_vni_chk_en : 1; /* [20] */ + u32 ipsurx_ch_nvgre_crks_chk_en : 1; /* [21] */ + u32 rsv_16 : 2; /* [23:22] */ + u32 ipsurx_ch_dflt_fwd_act : 3; /* [26:24] */ + u32 rsv_17 : 1; /* [27] */ + u32 ipsurx_ch_dflt_pkt_pri : 3; /* [30:28] */ + u32 rsv_18 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw4_u; + +/* Define the union csr_ipsurx_cat_dw5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_vf_key_sel : 1; /* [0] */ + u32 ipsurx_ch_tcam_key_sel : 1; /* [1] */ + u32 ipsurx_ch_pri_dflt_sel : 1; /* [2] */ + u32 ipsurx_ch_ncsi_key_sel : 1; /* [3] */ + u32 ipsurx_ch_pri_sel : 4; /* [7:4] */ + u32 ipsurx_ch_pri_key_sel : 1; /* [8] */ + u32 ipsurx_ch_pri_sel_en : 1; /* [9] */ + u32 ipsurx_ch_tunnel_ipv6_blindcs_en : 1; /* [10] */ + u32 ipsurx_ch_tunnel_ipv6_udp_cs_chk_en : 1; /* [11] */ + u32 ipsurx_ch_tunnel_ipv6_udpcs_zero_chk_en : 1; /* [12] */ + u32 ipsurx_ch_tunnel_ipv6_dip_chk_en : 1; /* [13] */ + u32 ipsurx_ch_tunnel_ipv6_sip_chk_en : 1; /* [14] */ + u32 ipsurx_ch_tunnel_ipv6_ver_chk_en : 1; /* [15] */ + u32 ipsurx_ch_tunnel_ipv6_len_chk_en : 1; /* [16] */ + u32 ipsurx_ch_cn_pri_sel : 1; /* [17] */ + u32 ipsurx_ch_tunnel_ipv4_udp_len_chk_en : 1; /* [18] */ + u32 ipsurx_ch_tunnel_ipv4_blindcs_en : 1; /* [19] */ + u32 ipsurx_ch_tunnel_ipv4_udp_cs_chk_en : 1; /* [20] */ + u32 ipsurx_ch_tunnel_ipv4_ip_cs_chk_en : 1; /* [21] */ + u32 ipsurx_ch_tunnel_ipv4_dip_rsv_addr_chk_en : 1; /* [22] */ + u32 ipsurx_ch_tunnel_ipv4_dip_zero_chk_en : 1; /* [23] */ + u32 ipsurx_ch_tunnel_ipv4_dip_lb_chk_en : 1; /* [24] */ + u32 ipsurx_ch_tunnel_ipv4_sip_lb_chk_en : 1; /* [25] */ + u32 ipsurx_ch_tunnel_ipv4_sip_mc_chk_en : 1; /* [26] */ + u32 ipsurx_ch_tunnel_ipv4_sip_dip_chk_en : 1; /* [27] */ + u32 ipsurx_ch_tunnel_ipv4_ihl_chk_en : 1; /* [28] */ + u32 ipsurx_ch_tunnel_ipv4_ver_chk_en : 1; /* [29] */ + u32 ipsurx_ch_tunnel_ipv4_len_chk_en : 1; /* [30] */ + u32 ipsurx_ch_tunnel_8023_len_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cat_dw5_u; + +/* Define the union csr_ipsurx_ch_invld_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ch_invld_sts : 9; /* [8:0] */ + u32 rsv_19 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ch_invld_sts_u; + +/* Define the union csr_ipsurx_sop_eop_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_sop_eop_st : 11; /* [10:0] */ + u32 rsv_20 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_sop_eop_st_u; + +/* Define the union csr_ipsurx_mfs_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mfs_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mfs_sop_with_err_cnt_u; + +/* Define the union csr_ipsurx_mfs_abort_bf_ipsurx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mfs_abort_bf_ipsurx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mfs_abort_bf_ipsurx_cnt_u; + +/* Define the union csr_ipsurx_mfs_cut_by_ipsurx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mfs_cut_by_ipsurx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mfs_cut_by_ipsurx_cnt_u; + +/* Define the union csr_ipsurx_mfs_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mfs_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mfs_sop_sop_err_cnt_u; + +/* Define the union csr_ipsurx_perx_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_perx_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_perx_sop_with_err_cnt_u; + +/* Define the union csr_ipsurx_perx_abort_bf_ipsurx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_perx_abort_bf_ipsurx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_perx_abort_bf_ipsurx_cnt_u; + +/* Define the union csr_ipsurx_perx_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_perx_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_perx_sop_sop_err_cnt_u; + +/* Define the union csr_ipsurx_pkt_min_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pkt_min_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_pkt_min_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_pkt_max_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pkt_max_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_pkt_max_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_hg2hdr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_hg2hdr_ehv_loc : 7; /* [6:0] */ + u32 rsv_21 : 1; /* [7] */ + u32 ipsurx_hg2hdr_ehv_0_hlen : 5; /* [12:8] */ + u32 rsv_22 : 3; /* [15:13] */ + u32 ipsurx_hg2hdr_ehv_1_hlen : 5; /* [20:16] */ + u32 rsv_23 : 3; /* [23:21] */ + u32 ipsurx_hg2hdr_vld : 1; /* [24] */ + u32 rsv_24 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_hg2hdr_cfg_u; + +/* Define the union csr_ipsurx_unknown_tag_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_unknown_tag_ofs : 6; /* [5:0] */ + u32 rsv_25 : 2; /* [7:6] */ + u32 ipsurx_unknown_tag_len : 5; /* [12:8] */ + u32 rsv_26 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_unknown_tag_cfg_u; + +/* Define the union csr_ipsurx_evtag_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_evtag_tpid2 : 16; /* [15:0] */ + u32 ipsurx_evtag_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_evtag_tpid1_u; + +/* Define the union csr_ipsurx_evtag_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_evtag_tpid0 : 16; /* [15:0] */ + u32 ipsurx_evtag_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_evtag_tpid0_u; + +/* Define the union csr_ipsurx_svlan_tpid2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_svlan_tpid4 : 16; /* [15:0] */ + u32 ipsurx_svlan_private0 : 1; /* [16] */ + u32 ipsurx_svlan_private1 : 1; /* [17] */ + u32 ipsurx_svlan_private2 : 1; /* [18] */ + u32 ipsurx_svlan_private3 : 1; /* [19] */ + u32 ipsurx_svlan_private4 : 1; /* [20] */ + u32 ipsurx_hcap_svlan0 : 1; /* [21] */ + u32 ipsurx_hcap_svlan1 : 1; /* [22] */ + u32 ipsurx_hcap_svlan2 : 1; /* [23] */ + u32 ipsurx_hcap_svlan3 : 1; /* [24] */ + u32 ipsurx_hcap_svlan4 : 1; /* [25] */ + u32 rsv_27 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_svlan_tpid2_u; + +/* Define the union csr_ipsurx_svlan_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_svlan_tpid2 : 16; /* [15:0] */ + u32 ipsurx_svlan_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_svlan_tpid1_u; + +/* Define the union csr_ipsurx_svlan_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_svlan_tpid0 : 16; /* [15:0] */ + u32 ipsurx_svlan_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_svlan_tpid0_u; + +/* Define the union csr_ipsurx_cvlan_tpid2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cvlan_tpid4 : 16; /* [15:0] */ + u32 rsv_28 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cvlan_tpid2_u; + +/* Define the union csr_ipsurx_cvlan_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cvlan_tpid2 : 16; /* [15:0] */ + u32 ipsurx_cvlan_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cvlan_tpid1_u; + +/* Define the union csr_ipsurx_cvlan_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cvlan_tpid0 : 16; /* [15:0] */ + u32 ipsurx_cvlan_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cvlan_tpid0_u; + +/* Define the union csr_ipsurx_p8021_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_p8021_pri : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_p8021_pri_u; + +/* Define the union csr_ipsurx_8023_max_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_8023_max_len : 16; /* [15:0] */ + u32 rsv_29 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_8023_max_len_u; + +/* Define the union csr_ipsurx_8023_jumbo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_8023_jumbo_tpid : 16; /* [15:0] */ + u32 ipsurx_8023_jumbo_chk_en : 1; /* [16] */ + u32 rsv_30 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_8023_jumbo_cfg_u; + +/* Define the union csr_ipsurx_l2_dmac_eth_chk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_lldp_dmac_chk_en : 1; /* [0] */ + u32 ipsurx_lacp_dmac_chk_en : 1; /* [1] */ + u32 ipsurx_pfc_dmac_chk_en : 1; /* [2] */ + u32 ipsurx_pause_dmac_chk_en : 1; /* [3] */ + u32 ipsurx_tunnel_lldp_dmac_chk_en : 1; /* [4] */ + u32 ipsurx_tunnel_lacp_dmac_chk_en : 1; /* [5] */ + u32 ipsurx_tunnel_pfc_dmac_chk_en : 1; /* [6] */ + u32 ipsurx_tunnel_pause_dmac_chk_en : 1; /* [7] */ + u32 rsv_31 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_l2_dmac_eth_chk_en_u; + +/* Define the union csr_ipsurx_rtn_ts_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rtn_ts_en : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rtn_ts_en_u; + +/* Define the union csr_ipsurx_rtn_ts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rtn_ts : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rtn_ts_u; + +/* Define the union csr_ipsurx_ipv4_dscp_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_dscp_pri : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_dscp_pri_u; + +/* Define the union csr_ipsurx_igmpv4_dip_chk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_igmpv4_dip_chk_en : 1; /* [0] */ + u32 rsv_33 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_igmpv4_dip_chk_en_u; + +/* Define the union csr_ipsurx_ipv6_dscp_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_dscp_pri : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_dscp_pri_u; + +/* Define the union csr_ipsurx_fc_csctl_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fc_csctl_pri : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fc_csctl_pri_u; + +/* Define the union csr_ipsurx_fc_priority_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fc_priority_pri : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fc_priority_pri_u; + +/* Define the union csr_ipsurx_ipv6_spec_mc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_spec_mcast : 16; /* [15:0] */ + u32 ipsurx_ipv6_spec_mcast_mask : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_spec_mc_u; + +/* Define the union csr_ipsurx_roce_bth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_pkey : 16; /* [15:0] */ + u32 ipsurx_roce_tver : 4; /* [19:16] */ + u32 rsv_34 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_bth_u; + +/* Define the union csr_ipsurx_rocev2_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_dport : 16; /* [15:0] */ + u32 rsv_35 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_dport_u; + +/* Define the union csr_ipsurx_natt_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_natt_dport : 16; /* [15:0] */ + u32 rsv_36 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_natt_dport_u; + +/* Define the union csr_ipsurx_vxlan_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vxlan_dport : 16; /* [15:0] */ + u32 rsv_37 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vxlan_dport_u; + +/* Define the union csr_ipsurx_vxlan_gpe_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vxlan_gpe_dport : 16; /* [15:0] */ + u32 rsv_38 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vxlan_gpe_dport_u; + +/* Define the union csr_ipsurx_geneve_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_geneve_dport : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_geneve_dport_u; + +/* Define the union csr_ipsurx_ipv4_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_np : 8; /* [7:0] */ + u32 rsv_40 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_np_u; + +/* Define the union csr_ipsurx_ipv6_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_np : 8; /* [7:0] */ + u32 rsv_41 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_np_u; + +/* Define the union csr_ipsurx_ethernet_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ethernet_np : 8; /* [7:0] */ + u32 rsv_42 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ethernet_np_u; + +/* Define the union csr_ipsurx_ioam_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ioam_np : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ioam_np_u; + +/* Define the union csr_ipsurx_int_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_int_np : 8; /* [7:0] */ + u32 rsv_44 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_int_np_u; + +/* Define the union csr_ipsurx_nsh_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_nsh_np : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_nsh_np_u; + +/* Define the union csr_ipsurx_ah_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ah_np : 8; /* [7:0] */ + u32 rsv_46 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ah_np_u; + +/* Define the union csr_ipsurx_esp_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_esp_np : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_esp_np_u; + +/* Define the union csr_ipsurx_rob_opt_class_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rob_opt_class : 16; /* [15:0] */ + u32 rsv_48 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rob_opt_class_u; + +/* Define the union csr_ipsurx_ppop_opt_class_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ppop_opt_class : 16; /* [15:0] */ + u32 rsv_49 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ppop_opt_class_u; + +/* Define the union csr_ipsurx_telemetry_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tele_geneve_en : 1; /* [0] */ + u32 ipsurx_tele_tcp_en : 1; /* [1] */ + u32 ipsurx_tele_udp_en : 1; /* [2] */ + u32 rsv_50 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_telemetry_en_u; + +/* Define the union csr_ipsurx_tcp_coco_with_ts_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_coco_with_ts_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_coco_with_ts_dw0_u; + +/* Define the union csr_ipsurx_tcp_coco_without_ts_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_coco_without_ts_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_coco_without_ts_dw0_u; + +/* Define the union csr_ipsurx_tcp_coco_dw0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_coco_dw0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_coco_dw0_mask_u; + +/* Define the union csr_ipsurx_coalesce_pkt_fwd_act_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_coco_fwd_act_ctrl : 1; /* [0] */ + u32 ipsurx_rocev2_fwd_act_ctrl : 1; /* [1] */ + u32 ipsurx_fc_fwd_act_ctrl : 1; /* [2] */ + u32 ipsurx_cn_rocev2_fwd_act_ctrl : 1; /* [3] */ + u32 ipsurx_lb_tcp_coco_fwd_act_ctrl : 1; /* [4] */ + u32 ipsurx_lb_rocev2_fwd_act_ctrl : 1; /* [5] */ + u32 ipsurx_lb_cn_rocev2_fwd_act_ctrl : 1; /* [6] */ + u32 rsv_51 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_coalesce_pkt_fwd_act_ctrl_u; + +/* Define the union csr_ipsurx_hcap_val_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_hcap_val1 : 16; /* [15:0] */ + u32 ipsurx_hcap_val2 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_hcap_val_u; + +/* Define the union csr_ipsurx_hcap_pri_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_hcap_pri : 3; /* [2:0] */ + u32 rsv_52 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_hcap_pri_u; + +/* Define the union csr_ipsurx_ctrl_pkt_dmac_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_dmac_h : 16; /* [15:0] */ + u32 ipsurx_ctrl_pkt_dmac_en : 1; /* [16] */ + u32 rsv_53 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_dmac_h_u; + +/* Define the union csr_ipsurx_ctrl_pkt_dmac_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_dmac_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_dmac_l_u; + +/* Define the union csr_ipsurx_ipv6_ext_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_ext_nh : 8; /* [7:0] */ + u32 ipsurx_ipv6_ext_vld : 1; /* [8] */ + u32 rsv_54 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_ext_ctrl_u; + +/* Define the union csr_ipsurx_bgp_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_bgp_dport : 16; /* [15:0] */ + u32 rsv_55 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_bgp_dport_u; + +/* Define the union csr_ipsurx_tcp_opt_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_opt_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_opt_dw0_u; + +/* Define the union csr_ipsurx_esp_prtl_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_esp_prtl_type : 16; /* [15:0] */ + u32 rsv_56 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_esp_prtl_type_u; + +/* Define the union csr_ipsurx_rocev1_crc_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_crc_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_crc_mask_dw0_u; + +/* Define the union csr_ipsurx_rocev1_crc_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_crc_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_crc_mask_dw1_u; + +/* Define the union csr_ipsurx_rocev1_crc_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_crc_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_crc_mask_dw2_u; + +/* Define the union csr_ipsurx_rocev1_crc_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_crc_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_crc_mask_dw3_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_crc_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_crc_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_crc_mask_dw0_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_crc_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_crc_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_crc_mask_dw1_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_crc_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_crc_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_crc_mask_dw2_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_crc_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_crc_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_crc_mask_dw3_u; + +/* Define the union csr_ipsurx_rocev2_ipv6_crc_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv6_crc_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv6_crc_mask_dw0_u; + +/* Define the union csr_ipsurx_rocev2_ipv6_crc_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv6_crc_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv6_crc_mask_dw1_u; + +/* Define the union csr_ipsurx_rocev2_ipv6_crc_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv6_crc_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv6_crc_mask_dw2_u; + +/* Define the union csr_ipsurx_rocev2_ipv6_crc_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv6_crc_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv6_crc_mask_dw3_u; + +/* Define the union csr_ipsurx_crc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_difx_crc_dat_bit_rev : 1; /* [0] */ + u32 ipsurx_difx_crc_rslt_bit_rev : 1; /* [1] */ + u32 ipsurx_difx_crc_rslt_inv : 1; /* [2] */ + u32 rsv_57 : 1; /* [3] */ + u32 ipsurx_fc_crc_dat_bit_rev : 1; /* [4] */ + u32 ipsurx_fc_crc_rslt_bit_rev : 1; /* [5] */ + u32 ipsurx_fc_crc_rslt_inv : 1; /* [6] */ + u32 rsv_58 : 1; /* [7] */ + u32 ipsurx_sctp_crc_dat_bit_rev : 1; /* [8] */ + u32 ipsurx_sctp_crc_rslt_bit_rev : 1; /* [9] */ + u32 ipsurx_sctp_crc_rslt_inv : 1; /* [10] */ + u32 rsv_59 : 5; /* [15:11] */ + u32 ipsurx_roce_icrc_dat_bit_rev : 1; /* [16] */ + u32 ipsurx_roce_icrc_rslt_bit_rev : 1; /* [17] */ + u32 ipsurx_roce_icrc_rslt_inv : 1; /* [18] */ + u32 rsv_60 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_crc_ctrl_u; + +/* Define the union csr_ipsurx_roce_icrc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_icrc_ini : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_icrc_ini_u; + +/* Define the union csr_ipsurx_roce_icrc_mn_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_icrc_mn : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_icrc_mn_u; + +/* Define the union csr_ipsurx_fc_crc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fc_crc_ini : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fc_crc_ini_u; + +/* Define the union csr_ipsurx_fc_crc_mn_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fc_crc_mn : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fc_crc_mn_u; + +/* Define the union csr_ipsurx_sctp_crc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_sctp_crc_ini : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_sctp_crc_ini_u; + +/* Define the union csr_ipsurx_difx_crc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_difx_crc_ini : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_difx_crc_ini_u; + +/* Define the union csr_ipsurx_mag_drop_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mag_drop_ctrl : 2; /* [1:0] */ + u32 rsv_61 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mag_drop_ctrl_u; + +/* Define the union csr_ipsurx_rob_ppop_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ppop_en : 1; /* [0] */ + u32 ipsurx_rob_en : 1; /* [1] */ + u32 ipsurx_ppop_ctrl_en : 1; /* [2] */ + u32 rsv_62 : 1; /* [3] */ + u32 ipsurx_fwd_to_rob_en : 1; /* [4] */ + u32 rsv_63 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rob_ppop_en_u; + +/* Define the union csr_ipsurx_ctrl_pkt_port_map_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_port_map_en : 1; /* [0] */ + u32 rsv_64 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_port_map_en_u; + +/* Define the union csr_ipsurx_ctrl_pkt_port_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_port_map : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_port_map_u; + +/* Define the union csr_ipsurx_push_len_l2f_oth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_push_len_l2f_none : 4; /* [3:0] */ + u32 ipsurx_push_len_l2f_hcap : 4; /* [7:4] */ + u32 ipsurx_push_len_err : 4; /* [11:8] */ + u32 ipsurx_push_len_l2f_ppop : 4; /* [15:12] */ + u32 ipsurx_push_len_max : 4; /* [19:16] */ + u32 rsv_65 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_push_len_l2f_oth_u; + +/* Define the union csr_ipsurx_push_len_l3f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_push_len_l3f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_push_len_l3f_u; + +/* Define the union csr_ipsurx_push_len_l45f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_push_len_l45f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_push_len_l45f_u; + +/* Define the union csr_ipsurx_push_len_fc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_push_len_fc : 4; /* [3:0] */ + u32 rsv_66 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_push_len_fc_u; + +/* Define the union csr_ipsurx_roce_ext_sumop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_ext_sumop : 6; /* [5:0] */ + u32 rsv_67 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_ext_sumop_u; + +/* Define the union csr_ipsurx_sr_sumop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_reroute_sumop : 6; /* [5:0] */ + u32 rsv_68 : 2; /* [7:6] */ + u32 ipsurx_other_reroute_sumop : 6; /* [13:8] */ + u32 rsv_69 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_sr_sumop_u; + +/* Define the union csr_ipsurx_ctrl_pkt_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_en_arp : 1; /* [0] */ + u32 ipsurx_ctrl_pkt_en_rarp : 1; /* [1] */ + u32 ipsurx_ctrl_pkt_en_pause : 1; /* [2] */ + u32 ipsurx_ctrl_pkt_en_pfc : 1; /* [3] */ + u32 ipsurx_ctrl_pkt_en_lacp : 1; /* [4] */ + u32 ipsurx_ctrl_pkt_en_marker : 1; /* [5] */ + u32 ipsurx_ctrl_pkt_en_oam : 1; /* [6] */ + u32 ipsurx_ctrl_pkt_en_slow_prtl : 1; /* [7] */ + u32 ipsurx_ctrl_pkt_en_lldp : 1; /* [8] */ + u32 ipsurx_ctrl_pkt_en_cdcp : 1; /* [9] */ + u32 ipsurx_ctrl_pkt_en_cnm : 1; /* [10] */ + u32 ipsurx_ctrl_pkt_en_ecp : 1; /* [11] */ + u32 ipsurx_ctrl_pkt_en_vdp : 1; /* [12] */ + u32 ipsurx_ctrl_pkt_en_mpls : 1; /* [13] */ + u32 ipsurx_ctrl_pkt_en_vrrp : 1; /* [14] */ + u32 ipsurx_ctrl_pkt_en_ospf : 1; /* [15] */ + u32 ipsurx_ctrl_pkt_en_bgp : 1; /* [16] */ + u32 rsv_70 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_en_u; + +/* Define the union csr_ipsurx_roce_ext_len_exc_sumop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_ext_len_exc_sumop : 6; /* [5:0] */ + u32 rsv_71 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_ext_len_exc_sumop_u; + +/* Define the union csr_ipsurx_roce_drc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_drc_op : 3; /* [2:0] */ + u32 ipsurx_roce_dqp_allf_chk_en : 1; /* [3] */ + u32 rsv_72 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_drc_ctrl_u; + +/* Define the union csr_ipsurx_dmac_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_dmac_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_dmac_zero_cnt_u; + +/* Define the union csr_ipsurx_smac_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_smac_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_smac_ilgl_cnt_u; + +/* Define the union csr_ipsurx_da_sa_equal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_da_sa_equal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_da_sa_equal_cnt_u; + +/* Define the union csr_ipsurx_eth_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_eth_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_eth_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_dmac_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_dmac_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_dmac_zero_cnt_u; + +/* Define the union csr_ipsurx_tunnel_smac_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_smac_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_smac_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_da_sa_equal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_da_sa_equal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_da_sa_equal_cnt_u; + +/* Define the union csr_ipsurx_tunnel_eth_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_eth_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_eth_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_ver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_ihl_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_ihl_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_ihl_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_sip_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_sip_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_sip_dip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_sip_mc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_sip_mc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_sip_mc_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_sip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_sip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_sip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_dip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_dip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_dip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_dip_zero_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_dip_zero_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_dip_zero_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_dip_rsv_addr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_dip_rsv_addr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_dip_rsv_addr_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_udp_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_udp_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_udp_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv4_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv4_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv4_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv6_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_ver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv6_sip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_sip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_sip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv6_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_dip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv6_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_ver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_ihl_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_ihl_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_ihl_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_sip_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_sip_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_sip_dip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_sip_mc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_sip_mc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_sip_mc_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_sip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_sip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_sip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_dip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_dip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_dip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_dip_zero_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_dip_zero_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_dip_zero_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_udp_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_udp_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_udp_len_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv4_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv4_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv4_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv6_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv6_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv6_ver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv6_sip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv6_sip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv6_sip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv6_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv6_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv6_dip_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv6_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv6_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv6_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_land_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_land_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_land_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_do_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_do_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_do_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_syn_fin_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_syn_fin_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_syn_fin_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_no_flag_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_no_flag_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_no_flag_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_fin_ack_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_fin_ack_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_fin_ack_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_ack_rst_syn_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_ack_rst_syn_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_ack_rst_syn_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tcp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ipv6_udp_cs_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipv6_udp_cs_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipv6_udp_cs_zero_cnt_u; + +/* Define the union csr_ipsurx_tunnel_ipv6_udp_cs_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_ipv6_udp_cs_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_ipv6_udp_cs_zero_cnt_u; + +/* Define the union csr_ipsurx_udp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_udp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_udp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_igmp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_igmp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_igmp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_icmpv4_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_icmpv4_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_icmpv4_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_icmpv6_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_icmpv6_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_icmpv6_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_sctp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_sctp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_sctp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev1_dgid_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_dgid_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_dgid_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev1_sgid_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_sgid_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_sgid_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev1_ipver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_ipver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_ipver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev1_nxhdr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_nxhdr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_nxhdr_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev1_paylen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev1_paylen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev1_paylen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_frag_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_frag_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_frag_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev2_ipv4_udp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv4_udp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv4_udp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_rocev2_ipv6_udp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rocev2_ipv6_udp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rocev2_ipv6_udp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_tver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_tver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_tver_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_pkey_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_pkey_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_pkey_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_dqp_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_dqp_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_dqp_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_padcnt_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_padcnt_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_padcnt_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_va_8b_align_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_va_8b_align_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_va_8b_align_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_dmalen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_dmalen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_dmalen_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_opcode_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_opcode_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_opcode_ilgl_cnt_u; + +/* Define the union csr_ipsurx_ib_icrc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ib_icrc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ib_icrc_ilgl_cnt_u; + +/* Define the union csr_ipsurx_fc_crc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fc_crc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fc_crc_ilgl_cnt_u; + +/* Define the union csr_ipsurx_to_up_pkt_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_to_up_pkt_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_to_up_pkt_ilgl_cnt_u; + +/* Define the union csr_ipsurx_to_bmc_only_pkt_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_to_bmc_only_pkt_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_to_bmc_only_pkt_ilgl_cnt_u; + +/* Define the union csr_ipsurx_llc_snap_enc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_llc_snap_enc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_llc_snap_enc_ilgl_cnt_u; + +/* Define the union csr_ipsurx_eth_type_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_eth_type_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_eth_type_ilgl_cnt_u; + +/* Define the union csr_ipsurx_vxlan_gpe_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vxlan_gpe_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vxlan_gpe_other_ver_cnt_u; + +/* Define the union csr_ipsurx_geneve_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_geneve_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_geneve_other_ver_cnt_u; + +/* Define the union csr_ipsurx_nsh_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_nsh_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_nsh_other_ver_cnt_u; + +/* Define the union csr_ipsurx_nsh_len_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_nsh_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_nsh_len_cnt_u; + +/* Define the union csr_ipsurx_tunnel_nvgre_cvlan_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_nvgre_cvlan_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_nvgre_cvlan_ilgl_cnt_u; + +/* Define the union csr_ipsurx_hcap_md_size_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_hcap_md_size_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_hcap_md_size_ilgl_cnt_u; + +/* Define the union csr_ipsurx_drop_mfs_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_drop_mfs_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_drop_mfs_pkt_cnt_u; + +/* Define the union csr_ipsurx_len_4b_align_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_len_4b_align_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_len_4b_align_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tunnel_udp_cs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tunnel_udp_cs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tunnel_udp_cs_ilgl_cnt_u; + +/* Define the union csr_ipsurx_nvgre_crks_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_nvgre_crks_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_nvgre_crks_ilgl_cnt_u; + +/* Define the union csr_ipsurx_hdr_len_min_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_hdr_len_min_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_hdr_len_min_ilgl_cnt_u; + +/* Define the union csr_ipsurx_pause_pkt_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pause_pkt_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_pause_pkt_ilgl_cnt_u; + +/* Define the union csr_ipsurx_pfc_pkt_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pfc_pkt_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_pfc_pkt_ilgl_cnt_u; + +/* Define the union csr_ipsurx_roce_ext_len_exc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_roce_ext_len_exc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_roce_ext_len_exc_cnt_u; + +/* Define the union csr_ipsurx_ipsec_auth_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ipsec_auth_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ipsec_auth_ilgl_cnt_u; + +/* Define the union csr_ipsurx_natt_ipv4_udp_cs_zero_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_natt_ipv4_udp_cs_zero_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_natt_ipv4_udp_cs_zero_ilgl_cnt_u; + +/* Define the union csr_ipsurx_tx_cpt_pkt_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tx_cpt_pkt_drop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tx_cpt_pkt_drop_cnt_u; + +/* Define the union csr_ipsurx_ncsi_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_pkt_pri : 3; /* [2:0] */ + u32 ipsurx_ncsi_ctrl_pkt_en : 1; /* [3] */ + u32 ipsurx_mac_ncsi_en : 1; /* [4] */ + u32 ipsurx_hg2_ncsi_en : 1; /* [5] */ + u32 rsv_73 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_filter_mng_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_rule0_en : 1; /* [0] */ + u32 ipsurx_ncsi_flt_rule0_fwd_act : 1; /* [1] */ + u32 rsv_74 : 2; /* [3:2] */ + u32 ipsurx_ncsi_flt_rule0_mac_port : 4; /* [7:4] */ + u32 ipsurx_ncsi_flt_rule1_en : 1; /* [8] */ + u32 ipsurx_ncsi_flt_rule1_fwd_act : 1; /* [9] */ + u32 rsv_75 : 2; /* [11:10] */ + u32 ipsurx_ncsi_flt_rule1_mac_port : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_rule2_en : 1; /* [16] */ + u32 ipsurx_ncsi_flt_rule2_fwd_act : 1; /* [17] */ + u32 rsv_76 : 2; /* [19:18] */ + u32 ipsurx_ncsi_flt_rule2_mac_port : 4; /* [23:20] */ + u32 ipsurx_ncsi_flt_rule3_en : 1; /* [24] */ + u32 ipsurx_ncsi_flt_rule3_fwd_act : 1; /* [25] */ + u32 rsv_77 : 2; /* [27:26] */ + u32 ipsurx_ncsi_flt_rule3_mac_port : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_filter_mng_u; + +/* Define the union csr_ipsurx_ncsi_mac3_h_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac3_h : 16; /* [15:0] */ + u32 ipsurx_ncsi_flt_dmac3_vld : 1; /* [16] */ + u32 rsv_78 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac3_h_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac3_l_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac3_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac3_l_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac2_h_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac2_h : 16; /* [15:0] */ + u32 ipsurx_ncsi_flt_dmac2_vld : 1; /* [16] */ + u32 rsv_79 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac2_h_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac2_l_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac2_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac2_l_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac1_h_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac1_h : 16; /* [15:0] */ + u32 ipsurx_ncsi_flt_dmac1_vld : 1; /* [16] */ + u32 rsv_80 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac1_h_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac1_l_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac1_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac1_l_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac0_h_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac0_h : 16; /* [15:0] */ + u32 ipsurx_ncsi_flt_dmac0_vld : 1; /* [16] */ + u32 rsv_81 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac0_h_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_mac0_l_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_dmac0_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mac0_l_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_vlan_en : 4; /* [3:0] */ + u32 rsv_82 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan_en_u; + +/* Define the union csr_ipsurx_ncsi_vlan7_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan7_id : 12; /* [11:0] */ + u32 rsv_83 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan7_id_vld : 1; /* [16] */ + u32 rsv_84 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan7_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan6_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan6_id : 12; /* [11:0] */ + u32 rsv_85 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan6_id_vld : 1; /* [16] */ + u32 rsv_86 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan6_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan5_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan5_id : 12; /* [11:0] */ + u32 rsv_87 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan5_id_vld : 1; /* [16] */ + u32 rsv_88 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan5_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan4_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan4_id : 12; /* [11:0] */ + u32 rsv_89 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan4_id_vld : 1; /* [16] */ + u32 rsv_90 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan4_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan3_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan3_id : 12; /* [11:0] */ + u32 rsv_91 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan3_id_vld : 1; /* [16] */ + u32 rsv_92 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan3_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan2_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan2_id : 12; /* [11:0] */ + u32 rsv_93 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan2_id_vld : 1; /* [16] */ + u32 rsv_94 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan2_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan1_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan1_id : 12; /* [11:0] */ + u32 rsv_95 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan1_id_vld : 1; /* [16] */ + u32 rsv_96 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan1_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vlan0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vlan0_id : 12; /* [11:0] */ + u32 rsv_97 : 4; /* [15:12] */ + u32 ipsurx_ncsi_flt_vlan0_id_vld : 1; /* [16] */ + u32 rsv_98 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vlan0_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_bc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_bc_dmac_en : 1; /* [0] */ + u32 ipsurx_ncsi_flt_bc_arp_en : 1; /* [1] */ + u32 ipsurx_ncsi_flt_bc_ipv4_en : 1; /* [2] */ + u32 ipsurx_ncsi_flt_bc_ip_udp_en : 1; /* [3] */ + u32 ipsurx_ncsi_flt_bc_udp_prt68_en : 1; /* [4] */ + u32 ipsurx_ncsi_flt_bc_udp_prt67_en : 1; /* [5] */ + u32 ipsurx_ncsi_flt_bc_udp_prt137_en : 1; /* [6] */ + u32 ipsurx_ncsi_flt_bc_udp_prt138_en : 1; /* [7] */ + u32 ipsurx_ncsi_flt_bc_arp_tipv4_addr_en : 1; /* [8] */ + u32 ipsurx_ncsi_flt_bc_dhcpv4_cmac_en : 1; /* [9] */ + u32 rsv_99 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_bc_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_bc_arp_tipv4_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_bc_arp_tipv4_addr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_bc_arp_tipv4_addr_u; + +/* Define the union csr_ipsurx_ncsi_bc_dhcpv4_cmac_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_bc_dhcpv4_cmac_h : 16; /* [15:0] */ + u32 rsv_100 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_bc_dhcpv4_cmac_h_u; + +/* Define the union csr_ipsurx_ncsi_bc_dhcpv4_cmac_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_bc_dhcpv4_cmac_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_bc_dhcpv4_cmac_l_u; + +/* Define the union csr_ipsurx_ncsi_mc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_mc_dmac0_en : 1; /* [0] */ + u32 ipsurx_ncsi_flt_mc_dmac1_en : 1; /* [1] */ + u32 ipsurx_ncsi_flt_mc_dmac2_en : 1; /* [2] */ + u32 ipsurx_ncsi_flt_mc_dmac3_en : 1; /* [3] */ + u32 ipsurx_ncsi_flt_mc_ipv6_en : 1; /* [4] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_en : 1; /* [5] */ + u32 ipsurx_ncsi_flt_mc_udp_en : 1; /* [6] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt136_en : 1; /* [7] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt135_en : 1; /* [8] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt134_en : 1; /* [9] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt132_en : 1; /* [10] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt131_en : 1; /* [11] */ + u32 ipsurx_ncsi_flt_mc_icmpv6_mt130_en : 1; /* [12] */ + u32 ipsurx_ncsi_flt_mc_udp_prt547_en : 1; /* [13] */ + u32 ipsurx_ncsi_flt_mc_udp_prt546_en : 1; /* [14] */ + u32 rsv_101 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_mc_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_rule_vxlan_en : 4; /* [3:0] */ + u32 rsv_102 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_en_u; + +/* Define the union csr_ipsurx_ncsi_vxlan1_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan1_vni : 24; /* [23:0] */ + u32 ipsurx_ncsi_flt_vxlan1_vld : 1; /* [24] */ + u32 rsv_103 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan1_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vxlan0_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan0_vni : 24; /* [23:0] */ + u32 ipsurx_ncsi_flt_vxlan0_vld : 1; /* [24] */ + u32 rsv_104 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan0_ctrl_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_dipv4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan_dipv4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_dipv4_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_dipv6_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan_dipv6_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_dipv6_dw3_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_dipv6_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan_dipv6_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_dipv6_dw2_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_dipv6_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan_dipv6_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_dipv6_dw1_u; + +/* Define the union csr_ipsurx_ncsi_vxlan_dipv6_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_flt_vxlan_dipv6_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_vxlan_dipv6_dw0_u; + +/* Define the union csr_ipsurx_ncsi_hit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ncsi_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ncsi_hit_cnt_u; + +/* Define the union csr_ipsurx_lli_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_lli_type : 16; /* [15:0] */ + u32 ipsurx_lli_type_vld : 1; /* [16] */ + u32 rsv_105 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_lli_type_u; + +/* Define the union csr_ipsurx_tcam_key_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_key_sel : 1; /* [0] */ + u32 rsv_106 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_key_sel_u; + +/* Define the union csr_ipsurx_tcam_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_bk_scan_period : 8; /* [7:0] */ + u32 ipsurx_tcam_bk_scan_interval_unit : 8; /* [15:8] */ + u32 ipsurx_tcam_lkup_en : 1; /* [16] */ + u32 rsv_107 : 10; /* [26:17] */ + u32 ipsurx_tcam_mbist_en : 1; /* [27] */ + u32 ipsurx_tcam_mbist_test : 2; /* [29:28] */ + u32 ipsurx_tcam_mbist_t_sel : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_ctrl_u; + +/* Define the union csr_ipsurx_tcam_mbist_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_mbist_done : 1; /* [0] */ + u32 rsv_108 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_mbist_done_u; + +/* Define the union csr_ipsurx_vf_tb_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vf_tb_vlanid_mask : 1; /* [0] */ + u32 ipsurx_vf_tb_dmac_mask : 1; /* [1] */ + u32 ipsurx_vf_tb_erid_mask : 1; /* [2] */ + u32 ipsurx_vf_tb_lb_vlanid_mask : 1; /* [3] */ + u32 ipsurx_vf_tb_lb_dmac_mask : 1; /* [4] */ + u32 ipsurx_vf_tb_lb_erid_mask : 1; /* [5] */ + u32 rsv_109 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vf_tb_mask_u; + +/* Define the union csr_ipsurx_vf_tb_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mac_vf_tb_en : 1; /* [0] */ + u32 ipsurx_hg2_vf_tb_en : 1; /* [1] */ + u32 rsv_110 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vf_tb_ctrl_u; + +/* Define the union csr_ipsurx_port_erid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_port_erid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_port_erid_u; + +/* Define the union csr_ipsurx_tcp_opcd_tb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcp_opcd0 : 8; /* [7:0] */ + u32 ipsurx_tcp_opcd0_hdr_len : 5; /* [12:8] */ + u32 rsv_111 : 3; /* [15:13] */ + u32 ipsurx_tcp_opcd1 : 8; /* [23:16] */ + u32 ipsurx_tcp_opcd1_hdr_len : 5; /* [28:24] */ + u32 rsv_112 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcp_opcd_tb_u; + +/* Define the union csr_ipsurx_tcam_mbist_mem_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_mbist_mem_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_mbist_mem_err_cnt_u; + +/* Define the union csr_ipsurx_tcam_mbist_cmp_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_mbist_cmp_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_mbist_cmp_err_cnt_u; + +/* Define the union csr_ipsurx_lb_port_erid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_lb_port_erid : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_lb_port_erid_u; + +/* Define the union csr_ipsurx_tcam_hit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_hit_cnt_u; + +/* Define the union csr_ipsurx_fwd_act_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_fwd_act_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fwd_act_cnt_u; + +/* Define the union csr_ipsurx_ctrl_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ctrl_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ctrl_pkt_cnt_u; + +/* Define the union csr_ipsurx_vf_hit_sel_vf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vf_hit_sel_vf_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vf_hit_sel_vf_cnt_u; + +/* Define the union csr_ipsurx_vf_hit_sel_out_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vf_hit_sel_out_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vf_hit_sel_out_cnt_u; + +/* Define the union csr_ipsurx_wol_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol_wkup_ctrl : 4; /* [3:0] */ + u32 ipsurx_mac_wol_en : 1; /* [4] */ + u32 ipsurx_hg2_wol_en : 1; /* [5] */ + u32 ipsurx_wol_mod_en : 1; /* [6] */ + u32 rsv_113 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol_ctrl_u; + +/* Define the union csr_ipsurx_wol1_chk_ctrl1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_rule4_wk_host : 2; /* [1:0] */ + u32 rsv_114 : 2; /* [3:2] */ + u32 ipsurx_wol1_chk_rule4_opcode : 3; /* [6:4] */ + u32 rsv_115 : 1; /* [7] */ + u32 ipsurx_wol1_rule5_wk_host : 2; /* [9:8] */ + u32 rsv_116 : 2; /* [11:10] */ + u32 ipsurx_wol1_chk_rule5_opcode : 3; /* [14:12] */ + u32 rsv_117 : 1; /* [15] */ + u32 ipsurx_wol1_rule6_wk_host : 2; /* [17:16] */ + u32 rsv_118 : 2; /* [19:18] */ + u32 ipsurx_wol1_chk_rule6_opcode : 3; /* [22:20] */ + u32 rsv_119 : 1; /* [23] */ + u32 ipsurx_wol1_rule7_wk_host : 2; /* [25:24] */ + u32 rsv_120 : 2; /* [27:26] */ + u32 ipsurx_wol1_chk_rule7_opcode : 3; /* [30:28] */ + u32 rsv_121 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ctrl1_u; + +/* Define the union csr_ipsurx_wol1_chk_ctrl0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_rule0_wk_host : 2; /* [1:0] */ + u32 rsv_122 : 2; /* [3:2] */ + u32 ipsurx_wol1_chk_rule0_opcode : 3; /* [6:4] */ + u32 rsv_123 : 1; /* [7] */ + u32 ipsurx_wol1_rule1_wk_host : 2; /* [9:8] */ + u32 rsv_124 : 2; /* [11:10] */ + u32 ipsurx_wol1_chk_rule1_opcode : 3; /* [14:12] */ + u32 rsv_125 : 1; /* [15] */ + u32 ipsurx_wol1_rule2_wk_host : 2; /* [17:16] */ + u32 rsv_126 : 2; /* [19:18] */ + u32 ipsurx_wol1_chk_rule2_opcode : 3; /* [22:20] */ + u32 rsv_127 : 1; /* [23] */ + u32 ipsurx_wol1_rule3_wk_host : 2; /* [25:24] */ + u32 rsv_128 : 2; /* [27:26] */ + u32 ipsurx_wol1_chk_rule3_opcode : 3; /* [30:28] */ + u32 rsv_129 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ctrl0_u; + +/* Define the union csr_ipsurx_wol1_chk_mac_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_macaddr_h : 16; /* [15:0] */ + u32 rsv_130 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_mac_h_u; + +/* Define the union csr_ipsurx_wol1_chk_mac_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_macaddr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_mac_l_u; + +/* Define the union csr_ipsurx_wol1_chk_vlanid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_vlanid : 12; /* [11:0] */ + u32 ipsurx_wol1_chk_vlanen : 1; /* [12] */ + u32 rsv_131 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_vlanid_u; + +/* Define the union csr_ipsurx_wol1_chk_ip_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_ip_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ip_dw0_u; + +/* Define the union csr_ipsurx_wol1_chk_ip_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_ip_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ip_dw1_u; + +/* Define the union csr_ipsurx_wol1_chk_ip_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_ip_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ip_dw2_u; + +/* Define the union csr_ipsurx_wol1_chk_ip_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_ip_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_ip_dw3_u; + +/* Define the union csr_ipsurx_wol1_chk_node_addr_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_node_addr_h : 16; /* [15:0] */ + u32 rsv_132 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_node_addr_h_u; + +/* Define the union csr_ipsurx_wol1_chk_node_addr_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol1_chk_node_addr_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol1_chk_node_addr_l_u; + +/* Define the union csr_ipsurx_wol2_chk_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_chk_rule0_wk_host : 2; /* [1:0] */ + u32 ipsurx_wol2_chk_rule0_valid : 1; /* [2] */ + u32 rsv_133 : 1; /* [3] */ + u32 ipsurx_wol2_chk_rule1_wk_host : 2; /* [5:4] */ + u32 ipsurx_wol2_chk_rule1_valid : 1; /* [6] */ + u32 rsv_134 : 1; /* [7] */ + u32 ipsurx_wol2_chk_rule2_wk_host : 2; /* [9:8] */ + u32 ipsurx_wol2_chk_rule2_valid : 1; /* [10] */ + u32 rsv_135 : 1; /* [11] */ + u32 ipsurx_wol2_chk_rule3_wk_host : 2; /* [13:12] */ + u32 ipsurx_wol2_chk_rule3_valid : 1; /* [14] */ + u32 rsv_136 : 1; /* [15] */ + u32 ipsurx_wol2_chk_rule4_wk_host : 2; /* [17:16] */ + u32 ipsurx_wol2_chk_rule4_valid : 1; /* [18] */ + u32 rsv_137 : 1; /* [19] */ + u32 ipsurx_wol2_chk_rule5_wk_host : 2; /* [21:20] */ + u32 ipsurx_wol2_chk_rule5_valid : 1; /* [22] */ + u32 rsv_138 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_chk_ctrl_u; + +/* Define the union csr_ipsurx_wol2_chk_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_chk_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_chk_mask_dw0_u; + +/* Define the union csr_ipsurx_wol2_chk_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_chk_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_chk_mask_dw1_u; + +/* Define the union csr_ipsurx_wol2_chk_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_chk_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_chk_mask_dw2_u; + +/* Define the union csr_ipsurx_wol2_chk_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_chk_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_chk_mask_dw3_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw00_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw00 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw00_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw01 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw01_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw02_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw02 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw02_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw03_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw03 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw03_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw04_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw04 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw04_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw05_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw05 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw05_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw06_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw06 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw06_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw07_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw07 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw07_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw08_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw08 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw08_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw09_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw09 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw09_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw10_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw11_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw12_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw13 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw13_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw14 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw14_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw15 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw15_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw16 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw16_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw17_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw17 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw17_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw18_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw18 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw18_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw19_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw19 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw19_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw20_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw20 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw20_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw21_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw21 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw21_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw22_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw22 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw22_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw23 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw23_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw24_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw24 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw24_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw25_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw25 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw25_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw26_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw26 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw26_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw27_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw27 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw27_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw28_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw28 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw28_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw29_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw29 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw29_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw30_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw30 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw30_u; + +/* Define the union csr_ipsurx_wol2_pkt_dw31_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol2_pkt_dw31 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol2_pkt_dw31_u; + +/* Define the union csr_ipsurx_wol_hit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_wol_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_wol_hit_cnt_u; + +/* Define the union csr_ipsurx_cpt_ofs_ctrl_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ofs : 6; /* [5:0] */ + u32 rsv_139 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ofs_ctrl_dw0_u; + +/* Define the union csr_ipsurx_cpt_ofs_ctrl_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ofs_value : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ofs_ctrl_dw1_u; + +/* Define the union csr_ipsurx_cpt_com_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_mac_port : 3; /* [2:0] */ + u32 ipsurx_cpt_sel : 1; /* [3] */ + u32 ipsurx_cpt_ofs_vld : 1; /* [4] */ + u32 ipsurx_cpt_en : 1; /* [5] */ + u32 rsv_140 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_com_ctrl_u; + +/* Define the union csr_ipsurx_cpt_mac_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_mac_etype : 16; /* [15:0] */ + u32 ipsurx_cpt_mac_etype_vld : 1; /* [16] */ + u32 ipsurx_cpt_smac_vld : 1; /* [17] */ + u32 ipsurx_cpt_dmac_vld : 1; /* [18] */ + u32 rsv_141 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_mac_dw0_u; + +/* Define the union csr_ipsurx_cpt_mac_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_dmac_l32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_mac_dw1_u; + +/* Define the union csr_ipsurx_cpt_mac_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_smac_h16 : 16; /* [15:0] */ + u32 ipsurx_cpt_dmac_h16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_mac_dw2_u; + +/* Define the union csr_ipsurx_cpt_mac_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_smac_l32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_mac_dw3_u; + +/* Define the union csr_ipsurx_cpt_vlan_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_vlanid : 12; /* [11:0] */ + u32 ipsurx_cpt_vlanid_vld : 1; /* [12] */ + u32 rsv_142 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_vlan_ctrl_u; + +/* Define the union csr_ipsurx_cpt_ip_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_prtl : 8; /* [7:0] */ + u32 ipsurx_cpt_ip_prtl_vld : 1; /* [8] */ + u32 ipsurx_cpt_ip_hip_vld : 1; /* [9] */ + u32 ipsurx_cpt_ip_sip_vld : 1; /* [10] */ + u32 ipsurx_cpt_ip_dip_vld : 1; /* [11] */ + u32 rsv_143 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw0_u; + +/* Define the union csr_ipsurx_cpt_ip_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw1_u; + +/* Define the union csr_ipsurx_cpt_ip_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw2_u; + +/* Define the union csr_ipsurx_cpt_ip_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw3_u; + +/* Define the union csr_ipsurx_cpt_ip_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw4_u; + +/* Define the union csr_ipsurx_cpt_ip_dw5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_msk_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw5_u; + +/* Define the union csr_ipsurx_cpt_ip_dw6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_msk_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw6_u; + +/* Define the union csr_ipsurx_cpt_ip_dw7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_msk_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw7_u; + +/* Define the union csr_ipsurx_cpt_ip_dw8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_dip_msk_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw8_u; + +/* Define the union csr_ipsurx_cpt_ip_dw9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw9_u; + +/* Define the union csr_ipsurx_cpt_ip_dw10_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw10_u; + +/* Define the union csr_ipsurx_cpt_ip_dw11_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw11_u; + +/* Define the union csr_ipsurx_cpt_ip_dw12_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw12_u; + +/* Define the union csr_ipsurx_cpt_ip_dw13_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_msk_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw13_u; + +/* Define the union csr_ipsurx_cpt_ip_dw14_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_msk_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw14_u; + +/* Define the union csr_ipsurx_cpt_ip_dw15_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_msk_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw15_u; + +/* Define the union csr_ipsurx_cpt_ip_dw16_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_ip_sip_msk_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_ip_dw16_u; + +/* Define the union csr_ipsurx_cpt_l4_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_l4_hport_vld : 1; /* [0] */ + u32 ipsurx_cpt_l4_sport_vld : 1; /* [1] */ + u32 ipsurx_cpt_l4_dport_vld : 1; /* [2] */ + u32 rsv_144 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_l4_dw0_u; + +/* Define the union csr_ipsurx_cpt_l4_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_l4_sport : 16; /* [15:0] */ + u32 ipsurx_cpt_l4_dport : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_l4_dw1_u; + +/* Define the union csr_ipsurx_cpt_vxlan_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_vxlan_vni : 24; /* [23:0] */ + u32 ipsurx_cpt_vxlan_vni_vld : 1; /* [24] */ + u32 rsv_145 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_vxlan_ctrl_u; + +/* Define the union csr_ipsurx_cpt_tx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_tx_sumop : 8; /* [7:0] */ + u32 ipsurx_cpt_tx_push_len : 4; /* [11:8] */ + u32 rsv_146 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_tx_ctrl_u; + +/* Define the union csr_ipsurx_cpt_hit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cpt_hit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cpt_hit_cnt_u; + +/* Define the union csr_ipsurx_uncrt_err_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pif_ovfl_ctrl : 1; /* [0] */ + u32 ipsurx_hdrf_ovfl_ctrl : 1; /* [1] */ + u32 ipsurx_datf_ovfl_ctrl : 1; /* [2] */ + u32 ipsurx_emdf0_ovfl_ctrl : 1; /* [3] */ + u32 ipsurx_emdf1_ovfl_ctrl : 1; /* [4] */ + u32 ipsurx_renqf_ovfl_ctrl : 1; /* [5] */ + u32 ipsurx_rof_ovfl_ctrl : 1; /* [6] */ + u32 ipsurx_lb_crdtf_ovfl_ctrl : 1; /* [7] */ + u32 rsv_147 : 1; /* [8] */ + u32 ipsurx_hdrf_ram_uncrt_ctrl : 1; /* [9] */ + u32 ipsurx_datf_ram_uncrt_ctrl : 1; /* [10] */ + u32 ipsurx_renqf_uncrt_ctrl : 1; /* [11] */ + u32 ipsurx_renqof_uncrt_ctrl : 1; /* [12] */ + u32 ipsurx_vf_idx_ram_uncrt_ctrl : 1; /* [13] */ + u32 ipsurx_vf_ram_uncrt_ctrl : 1; /* [14] */ + u32 ipsurx_emd_ram_uncrt_ctrl : 1; /* [15] */ + u32 ipsurx_roce_opcd_uncrt_ctrl : 1; /* [16] */ + u32 ipsurx_tcam_art_uncrt_ctrl : 1; /* [17] */ + u32 ipsurx_tcam_uncrt_ctrl : 1; /* [18] */ + u32 ipsurx_mag_cut_by_ipsurx_err_ctrl : 1; /* [19] */ + u32 ipsurx_mag_sop_with_err_ctrl : 1; /* [20] */ + u32 ipsurx_mag_sop_sop_err_ctrl : 1; /* [21] */ + u32 ipsurx_perx_sop_with_err_ctrl : 1; /* [22] */ + u32 ipsurx_perx_sop_sop_err_ctrl : 1; /* [23] */ + u32 ipsurx_fatal_err_ctrl : 1; /* [24] */ + u32 rsv_148 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_uncrt_err_ctrl_u; + +/* Define the union csr_ipsurx_fifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_renqf_af_th : 7; /* [6:0] */ + u32 rsv_149 : 1; /* [7] */ + u32 ipsurx_emdf0_af_th : 4; /* [11:8] */ + u32 ipsurx_emdf1_af_th : 4; /* [15:12] */ + u32 ipsurx_rof_af_th : 6; /* [21:16] */ + u32 rsv_150 : 2; /* [23:22] */ + u32 ipsurx_hdrf_af_th : 7; /* [30:24] */ + u32 rsv_151 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fifo_th_u; + +/* Define the union csr_ipsurx_rammod_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tp_ram_tmod_ctrl : 8; /* [7:0] */ + u32 ipsurx_sp_ram_tmod_ctrl : 7; /* [14:8] */ + u32 ipsurx_mem_power_mode_ctrl : 6; /* [20:15] */ + u32 rsv_152 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rammod_ctrl_u; + +/* Define the union csr_ipsurx_ram_err_chk_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_err_chk_bypass : 1; /* [0] */ + u32 rsv_153 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_err_chk_bypass_u; + +/* Define the union csr_ipsurx_ram_err_inj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_crt_err_inj : 1; /* [0] */ + u32 ipsurx_tcam_uncrt_err_inj : 1; /* [1] */ + u32 ipsurx_tcam_art_crt_err_inj : 1; /* [2] */ + u32 ipsurx_tcam_art_uncrt_err_inj : 1; /* [3] */ + u32 rsv_154 : 4; /* [7:4] */ + u32 ipsurx_roce_opcd_crt_err_inj : 1; /* [8] */ + u32 ipsurx_roce_opcd_uncrt_err_inj : 1; /* [9] */ + u32 rsv_155 : 2; /* [11:10] */ + u32 ipsurx_vf_ram_crt_err_inj : 1; /* [12] */ + u32 ipsurx_vf_ram_uncrt_err_inj : 1; /* [13] */ + u32 ipsurx_vf_idx_ram_crt_err_inj : 1; /* [14] */ + u32 ipsurx_vf_idx_ram_uncrt_err_inj : 1; /* [15] */ + u32 ipsurx_hdrf_ram_crt_err_inj : 1; /* [16] */ + u32 ipsurx_hdrf_ram_uncrt_err_inj : 1; /* [17] */ + u32 ipsurx_datf_ram_crt_err_inj : 1; /* [18] */ + u32 ipsurx_datf_ram_uncrt_err_inj : 1; /* [19] */ + u32 ipsurx_emd_ram_crt_err_inj : 1; /* [20] */ + u32 ipsurx_emd_ram_uncrt_err_inj : 1; /* [21] */ + u32 ipsurx_renqf_ram_crt_err_inj : 1; /* [22] */ + u32 ipsurx_renqf_ram_uncrt_err_inj : 1; /* [23] */ + u32 ipsurx_rof_ram_crt_err_inj : 1; /* [24] */ + u32 ipsurx_rof_ram_uncrt_err_inj : 1; /* [25] */ + u32 rsv_156 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_err_inj_u; + +/* Define the union csr_ipsurx_fifo_sts2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rof_cnt : 6; /* [5:0] */ + u32 ipsurx_rof_empty : 1; /* [6] */ + u32 ipsurx_rof_full : 1; /* [7] */ + u32 ipsurx_rof_af : 1; /* [8] */ + u32 ipsurx_rof_of : 1; /* [9] */ + u32 rsv_157 : 2; /* [11:10] */ + u32 ipsurx_lb_crdtf_cnt : 5; /* [16:12] */ + u32 ipsurx_lb_crdtf_empty : 1; /* [17] */ + u32 ipsurx_lb_crdtf_full : 1; /* [18] */ + u32 ipsurx_lb_crdtf_af : 1; /* [19] */ + u32 ipsurx_lb_crdtf_uf : 1; /* [20] */ + u32 ipsurx_lb_crdtf_of : 1; /* [21] */ + u32 rsv_158 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fifo_sts2_u; + +/* Define the union csr_ipsurx_fifo_sts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_renqf_cnt : 7; /* [6:0] */ + u32 ipsurx_renqf_empty : 1; /* [7] */ + u32 ipsurx_renqf_full : 1; /* [8] */ + u32 ipsurx_renqf_af : 1; /* [9] */ + u32 ipsurx_renqf_of : 1; /* [10] */ + u32 rsv_159 : 1; /* [11] */ + u32 ipsurx_emdf0_cnt : 5; /* [16:12] */ + u32 ipsurx_emdf0_empty : 1; /* [17] */ + u32 ipsurx_emdf0_full : 1; /* [18] */ + u32 ipsurx_emdf0_af : 1; /* [19] */ + u32 ipsurx_emdf0_uf : 1; /* [20] */ + u32 ipsurx_emdf0_of : 1; /* [21] */ + u32 ipsurx_emdf1_cnt : 5; /* [26:22] */ + u32 ipsurx_emdf1_empty : 1; /* [27] */ + u32 ipsurx_emdf1_full : 1; /* [28] */ + u32 ipsurx_emdf1_af : 1; /* [29] */ + u32 ipsurx_emdf1_uf : 1; /* [30] */ + u32 ipsurx_emdf1_of : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fifo_sts1_u; + +/* Define the union csr_ipsurx_fifo_sts0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_pif_cnt : 4; /* [3:0] */ + u32 ipsurx_pif_empty : 1; /* [4] */ + u32 ipsurx_pif_full : 1; /* [5] */ + u32 ipsurx_pif_uf : 1; /* [6] */ + u32 ipsurx_pif_of : 1; /* [7] */ + u32 ipsurx_hdrf_cnt : 7; /* [14:8] */ + u32 ipsurx_hdrf_empty : 1; /* [15] */ + u32 ipsurx_hdrf_full : 1; /* [16] */ + u32 ipsurx_hdrf_af : 1; /* [17] */ + u32 ipsurx_hdrf_of : 1; /* [18] */ + u32 rsv_160 : 1; /* [19] */ + u32 ipsurx_datf_cnt : 6; /* [25:20] */ + u32 ipsurx_datf_empty : 1; /* [26] */ + u32 ipsurx_datf_full : 1; /* [27] */ + u32 ipsurx_datf_of : 1; /* [28] */ + u32 rsv_161 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_fifo_sts0_u; + +/* Define the union csr_ipsurx_ram_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ucerr_cnt_u; + +/* Define the union csr_ipsurx_ram_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_cerr_cnt_u; + +/* Define the union csr_ipsurx_rcv_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rcv_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rcv_bp_cnt_u; + +/* Define the union csr_ipsurx_mfs_gen_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_mfs_gen_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_mfs_gen_bp_cnt_u; + +/* Define the union csr_ipsurx_renqf_mfs_perx_th_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_renqf_mfs_perx_th_gap : 7; /* [6:0] */ + u32 rsv_162 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_renqf_mfs_perx_th_gap_u; + +/* Define the union csr_ipsurx_lb_rts_crdt_sts_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_lb_crdt_sts : 6; /* [5:0] */ + u32 rsv_163 : 2; /* [7:6] */ + u32 ipsurx_rts_crdt_sts : 4; /* [11:8] */ + u32 rsv_164 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_lb_rts_crdt_sts_u; + +/* Define the union csr_ipsurx_prm_bp_rand_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_prm_bp_rand_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_prm_bp_rand_cnt_u; + +/* Define the union csr_ipsurx_prm_bp_all_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_prm_bp_all_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_prm_bp_all_cnt_u; + +/* Define the union csr_ipsurx_ram_ctrl_bus_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ctrl_bus_dw0 : 6; /* [5:0] */ + u32 rsv_165 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ctrl_bus_dw0_u; + +/* Define the union csr_ipsurx_ram_ctrl_bus_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ctrl_bus_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ctrl_bus_dw1_u; + +/* Define the union csr_ipsurx_ram_ctrl_bus_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ctrl_bus_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ctrl_bus_dw2_u; + +/* Define the union csr_ipsurx_ram_ctrl_bus_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ctrl_bus_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ctrl_bus_dw3_u; + +/* Define the union csr_ipsurx_ram_ctrl_bus_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ram_ctrl_bus_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ram_ctrl_bus_dw4_u; + +/* Define the union csr_ipsurx_tcam_ctrl_bus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tcam_ctrl_bus : 10; /* [9:0] */ + u32 rsv_166 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tcam_ctrl_bus_u; + +/* Define the union csr_ipsurx_lb_crdtf_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_lb_crdtf_af_th : 4; /* [3:0] */ + u32 rsv_167 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_lb_crdtf_th_u; + +/* Define the union csr_ipsurx_rx_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_rx_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_rx_pkt_cnt_u; + +/* Define the union csr_ipsurx_tx_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_tx_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_tx_pkt_cnt_u; + +/* Define the union csr_ipsurx_cnp_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_cnp_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_cnp_pkt_cnt_u; + +/* Define the union csr_ipsurx_ecn_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_ecn_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_ecn_pkt_cnt_u; + +/* Define the union csr_ipsurx_port_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_port_cnt_port0 : 3; /* [2:0] */ + u32 rsv_168 : 1; /* [3] */ + u32 ipsurx_port_cnt_port1 : 3; /* [6:4] */ + u32 rsv_169 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_port_cnt_cfg_u; + +/* Define the union csr_ipsurx_port1_cos_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_port1_cos_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_port1_cos_cnt_u; + +/* Define the union csr_ipsurx_port0_cos_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_port0_cos_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_port0_cos_cnt_u; + +/* Define the union csr_ipsurx_vtep_ip_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_dw0_u; + +/* Define the union csr_ipsurx_vtep_ip_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_dw1_u; + +/* Define the union csr_ipsurx_vtep_ip_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_dw2_u; + +/* Define the union csr_ipsurx_vtep_ip_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_dw3_u; + +/* Define the union csr_ipsurx_vtep_ip_port_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip0_port : 4; /* [3:0] */ + u32 ipsurx_vtep_ip1_port : 4; /* [7:4] */ + u32 ipsurx_vtep_ip2_port : 4; /* [11:8] */ + u32 ipsurx_vtep_ip3_port : 4; /* [15:12] */ + u32 ipsurx_vtep_ip4_port : 4; /* [19:16] */ + u32 ipsurx_vtep_ip5_port : 4; /* [23:20] */ + u32 ipsurx_vtep_ip6_port : 4; /* [27:24] */ + u32 ipsurx_vtep_ip7_port : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_port_u; + +/* Define the union csr_ipsurx_vtep_ip_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_vtep_ip0_vld : 1; /* [0] */ + u32 ipsurx_vtep_ip1_vld : 1; /* [1] */ + u32 ipsurx_vtep_ip2_vld : 1; /* [2] */ + u32 ipsurx_vtep_ip3_vld : 1; /* [3] */ + u32 ipsurx_vtep_ip4_vld : 1; /* [4] */ + u32 ipsurx_vtep_ip5_vld : 1; /* [5] */ + u32 ipsurx_vtep_ip6_vld : 1; /* [6] */ + u32 ipsurx_vtep_ip7_vld : 1; /* [7] */ + u32 ipsurx_vtep_ip0_port_en : 1; /* [8] */ + u32 ipsurx_vtep_ip1_port_en : 1; /* [9] */ + u32 ipsurx_vtep_ip2_port_en : 1; /* [10] */ + u32 ipsurx_vtep_ip3_port_en : 1; /* [11] */ + u32 ipsurx_vtep_ip4_port_en : 1; /* [12] */ + u32 ipsurx_vtep_ip5_port_en : 1; /* [13] */ + u32 ipsurx_vtep_ip6_port_en : 1; /* [14] */ + u32 ipsurx_vtep_ip7_port_en : 1; /* [15] */ + u32 ipsurx_vtep_ip0_tp : 1; /* [16] */ + u32 ipsurx_vtep_ip1_tp : 1; /* [17] */ + u32 ipsurx_vtep_ip2_tp : 1; /* [18] */ + u32 ipsurx_vtep_ip3_tp : 1; /* [19] */ + u32 ipsurx_vtep_ip4_tp : 1; /* [20] */ + u32 ipsurx_vtep_ip5_tp : 1; /* [21] */ + u32 ipsurx_vtep_ip6_tp : 1; /* [22] */ + u32 ipsurx_vtep_ip7_tp : 1; /* [23] */ + u32 rsv_170 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_vtep_ip_ctrl_u; + +/* Define the union csr_ipsurx_patn_id_ext_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_patn_id_ext : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_patn_id_ext_u; + +/* Define the union csr_ipsurx_patn_id_ofs_idx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_patn_id_ofs_idx : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_patn_id_ofs_idx_u; + +/* Define the union csr_ipsurx_patn_id_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_patn_id_int : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_patn_id_int_u; + +/* Define the union csr_ipsurx_err_patn_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_err_patn_id : 4; /* [3:0] */ + u32 rsv_171 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsurx_err_patn_id_u; + + +#endif // IPSURX_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_reg_offset.h new file mode 100644 index 000000000..74df5ca5c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_reg_offset.h @@ -0,0 +1,1469 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : Hi1823_hi1823_addr_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2019/09/06 10:44:42 Create file +// ****************************************************************************** + +#ifndef IPSURX_REG_OFFSET_H +#define IPSURX_REG_OFFSET_H + +/* IPSURX_CSR Base address of Module's Register */ +#define CSR_IPSURX_CSR_BASE (0x2000) + +/* **************************************************************************** */ +/* IPSURX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_IPSURX_CSR_IPSURX_FPGA_VER_REG (CSR_IPSURX_CSR_BASE + 0x0) /* �汾�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_EMU_VER_REG (CSR_IPSURX_CSR_BASE + 0x4) /* �汾�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_INITCTAB_START_REG (CSR_IPSURX_CSR_BASE + 0x8) /* ���ñ���ʼ��ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INITCTAB_DONE_REG (CSR_IPSURX_CSR_BASE + 0xC) /* ���ñ���ʼ��״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_INT_VECTOR_REG (CSR_IPSURX_CSR_BASE + 0x10) /* Interrupt Vector Register */ +#define CSR_IPSURX_CSR_IPSURX_INT_REG (CSR_IPSURX_CSR_BASE + 0x14) /* Interrupt Data Register */ +#define CSR_IPSURX_CSR_IPSURX_INT_EN_REG (CSR_IPSURX_CSR_BASE + 0x18) /* Interrupt Mask Register */ +#define CSR_IPSURX_CSR_IPSURX_CH_INVLD_ERR_REG (CSR_IPSURX_CSR_BASE + 0x1C) /* ͨ��δʹ�ܵ��յ����ݴ����жϴ���Ĵ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_RAM_UCERR_REG (CSR_IPSURX_CSR_BASE + 0x20) /* RAM���ɾ������жϴ���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CERR_REG (CSR_IPSURX_CSR_BASE + 0x24) /* RAM�ɾ������жϴ���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FIFO_OF_ERR_REG (CSR_IPSURX_CSR_BASE + 0x28) /* FIFO��������жϴ���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_SOP_EOP_ERR_REG (CSR_IPSURX_CSR_BASE + 0x2C) /* SOP/EOP�������жϴ���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_PARSE_ERR_REG (CSR_IPSURX_CSR_BASE + 0x30) /* ���Ľ����������жϴ���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ERR_TYPE_INT_MASK_DW3_REG (CSR_IPSURX_CSR_BASE + 0x50) /* Error_type�ж�ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ERR_TYPE_INT_MASK_DW2_REG (CSR_IPSURX_CSR_BASE + 0x54) /* Error_type�ж�ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ERR_TYPE_INT_MASK_DW1_REG (CSR_IPSURX_CSR_BASE + 0x58) /* Error_type�ж�ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ERR_TYPE_INT_MASK_DW0_REG (CSR_IPSURX_CSR_BASE + 0x5C) /* Error_type�ж�ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x80) /* ���Ѱַ���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_TIMEOUT_REG (CSR_IPSURX_CSR_BASE + 0x84) /* ���ѰַTIMEOUT���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_0_REG (CSR_IPSURX_CSR_BASE + 0x88) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_1_REG (CSR_IPSURX_CSR_BASE + 0x8C) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_2_REG (CSR_IPSURX_CSR_BASE + 0x90) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_3_REG (CSR_IPSURX_CSR_BASE + 0x94) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_4_REG (CSR_IPSURX_CSR_BASE + 0x98) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_5_REG (CSR_IPSURX_CSR_BASE + 0x9C) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_6_REG (CSR_IPSURX_CSR_BASE + 0xA0) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_7_REG (CSR_IPSURX_CSR_BASE + 0xA4) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_8_REG (CSR_IPSURX_CSR_BASE + 0xA8) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_9_REG (CSR_IPSURX_CSR_BASE + 0xAC) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_10_REG (CSR_IPSURX_CSR_BASE + 0xB0) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_11_REG (CSR_IPSURX_CSR_BASE + 0xB4) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_12_REG (CSR_IPSURX_CSR_BASE + 0xB8) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_13_REG (CSR_IPSURX_CSR_BASE + 0xBC) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_14_REG (CSR_IPSURX_CSR_BASE + 0xC0) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_INDRECT_DATA_15_REG (CSR_IPSURX_CSR_BASE + 0xC4) /* ���Ѱַ���ݼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_0_REG (CSR_IPSURX_CSR_BASE + 0x100) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_1_REG (CSR_IPSURX_CSR_BASE + 0x104) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_2_REG (CSR_IPSURX_CSR_BASE + 0x108) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_3_REG (CSR_IPSURX_CSR_BASE + 0x10C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_4_REG (CSR_IPSURX_CSR_BASE + 0x110) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_5_REG (CSR_IPSURX_CSR_BASE + 0x114) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_6_REG (CSR_IPSURX_CSR_BASE + 0x118) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_7_REG (CSR_IPSURX_CSR_BASE + 0x11C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_8_REG (CSR_IPSURX_CSR_BASE + 0x120) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_9_REG (CSR_IPSURX_CSR_BASE + 0x124) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW0_10_REG (CSR_IPSURX_CSR_BASE + 0x128) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_0_REG (CSR_IPSURX_CSR_BASE + 0x12C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_1_REG (CSR_IPSURX_CSR_BASE + 0x130) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_2_REG (CSR_IPSURX_CSR_BASE + 0x134) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_3_REG (CSR_IPSURX_CSR_BASE + 0x138) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_4_REG (CSR_IPSURX_CSR_BASE + 0x13C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_5_REG (CSR_IPSURX_CSR_BASE + 0x140) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_6_REG (CSR_IPSURX_CSR_BASE + 0x144) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_7_REG (CSR_IPSURX_CSR_BASE + 0x148) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_8_REG (CSR_IPSURX_CSR_BASE + 0x14C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_9_REG (CSR_IPSURX_CSR_BASE + 0x150) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW1_10_REG (CSR_IPSURX_CSR_BASE + 0x154) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_0_REG (CSR_IPSURX_CSR_BASE + 0x158) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_1_REG (CSR_IPSURX_CSR_BASE + 0x15C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_2_REG (CSR_IPSURX_CSR_BASE + 0x160) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_3_REG (CSR_IPSURX_CSR_BASE + 0x164) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_4_REG (CSR_IPSURX_CSR_BASE + 0x168) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_5_REG (CSR_IPSURX_CSR_BASE + 0x16C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_6_REG (CSR_IPSURX_CSR_BASE + 0x170) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_7_REG (CSR_IPSURX_CSR_BASE + 0x174) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_8_REG (CSR_IPSURX_CSR_BASE + 0x178) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_9_REG (CSR_IPSURX_CSR_BASE + 0x17C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW2_10_REG (CSR_IPSURX_CSR_BASE + 0x180) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_0_REG (CSR_IPSURX_CSR_BASE + 0x184) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_1_REG (CSR_IPSURX_CSR_BASE + 0x188) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_2_REG (CSR_IPSURX_CSR_BASE + 0x18C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_3_REG (CSR_IPSURX_CSR_BASE + 0x190) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_4_REG (CSR_IPSURX_CSR_BASE + 0x194) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_5_REG (CSR_IPSURX_CSR_BASE + 0x198) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_6_REG (CSR_IPSURX_CSR_BASE + 0x19C) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_7_REG (CSR_IPSURX_CSR_BASE + 0x1A0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_8_REG (CSR_IPSURX_CSR_BASE + 0x1A4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_9_REG (CSR_IPSURX_CSR_BASE + 0x1A8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW3_10_REG (CSR_IPSURX_CSR_BASE + 0x1AC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_0_REG (CSR_IPSURX_CSR_BASE + 0x1B0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_1_REG (CSR_IPSURX_CSR_BASE + 0x1B4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_2_REG (CSR_IPSURX_CSR_BASE + 0x1B8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_3_REG (CSR_IPSURX_CSR_BASE + 0x1BC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_4_REG (CSR_IPSURX_CSR_BASE + 0x1C0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_5_REG (CSR_IPSURX_CSR_BASE + 0x1C4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_6_REG (CSR_IPSURX_CSR_BASE + 0x1C8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_7_REG (CSR_IPSURX_CSR_BASE + 0x1CC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_8_REG (CSR_IPSURX_CSR_BASE + 0x1D0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_9_REG (CSR_IPSURX_CSR_BASE + 0x1D4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW4_10_REG (CSR_IPSURX_CSR_BASE + 0x1D8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_0_REG (CSR_IPSURX_CSR_BASE + 0x1DC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_1_REG (CSR_IPSURX_CSR_BASE + 0x1E0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_2_REG (CSR_IPSURX_CSR_BASE + 0x1E4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_3_REG (CSR_IPSURX_CSR_BASE + 0x1E8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_4_REG (CSR_IPSURX_CSR_BASE + 0x1EC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_5_REG (CSR_IPSURX_CSR_BASE + 0x1F0) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_6_REG (CSR_IPSURX_CSR_BASE + 0x1F4) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_7_REG (CSR_IPSURX_CSR_BASE + 0x1F8) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_8_REG (CSR_IPSURX_CSR_BASE + 0x1FC) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_9_REG (CSR_IPSURX_CSR_BASE + 0x200) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CAT_DW5_10_REG (CSR_IPSURX_CSR_BASE + 0x204) /* IPSURXͨ���������ñ� */ +#define CSR_IPSURX_CSR_IPSURX_CH_INVLD_STS_REG (CSR_IPSURX_CSR_BASE + 0x280) /* ͨ����Ч״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_SOP_EOP_ST_REG (CSR_IPSURX_CSR_BASE + 0x284) /* SOP/EOP���״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_MFS_SOP_WITH_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x288) /* SOP_WITH_ERR��������� */ +#define CSR_IPSURX_CSR_IPSURX_MFS_ABORT_BF_IPSURX_CNT_REG (CSR_IPSURX_CSR_BASE + 0x28C) /* ABORT_BF_IPSURX��������� \ + */ +#define CSR_IPSURX_CSR_IPSURX_MFS_CUT_BY_IPSURX_CNT_REG (CSR_IPSURX_CSR_BASE + 0x290) /* CUT_BY_IPSURX��������� */ +#define CSR_IPSURX_CSR_IPSURX_MFS_SOP_SOP_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x294) /* SOP_SOP��������� */ +#define CSR_IPSURX_CSR_IPSURX_PERX_SOP_WITH_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x298) /* SOP_WITH_ERR��������� */ +#define CSR_IPSURX_CSR_IPSURX_PERX_ABORT_BF_IPSURX_CNT_REG (CSR_IPSURX_CSR_BASE + 0x29C) /* ABORT_BF_IPSURX��������� \ + */ +#define CSR_IPSURX_CSR_IPSURX_PERX_SOP_SOP_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x2A0) /* SOP_SOP��������� */ +#define CSR_IPSURX_CSR_IPSURX_PKT_MIN_LEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x2A4) /* ���ճ��̱������������� */ +#define CSR_IPSURX_CSR_IPSURX_PKT_MAX_LEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x2A8) /* ���ճ����������������� */ +#define CSR_IPSURX_CSR_IPSURX_HG2HDR_CFG_REG (CSR_IPSURX_CSR_BASE + 0x300) /* HG2 header���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_0_REG (CSR_IPSURX_CSR_BASE + 0x304) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_1_REG (CSR_IPSURX_CSR_BASE + 0x308) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_2_REG (CSR_IPSURX_CSR_BASE + 0x30C) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_3_REG (CSR_IPSURX_CSR_BASE + 0x310) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_4_REG (CSR_IPSURX_CSR_BASE + 0x314) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_5_REG (CSR_IPSURX_CSR_BASE + 0x318) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_6_REG (CSR_IPSURX_CSR_BASE + 0x31C) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_UNKNOWN_TAG_CFG_7_REG (CSR_IPSURX_CSR_BASE + 0x320) /* δ֪TAG���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_EVTAG_TPID1_REG (CSR_IPSURX_CSR_BASE + 0x324) /* ETAG/VNTAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_EVTAG_TPID0_REG (CSR_IPSURX_CSR_BASE + 0x328) /* ETAG/VNTAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_SVLAN_TPID2_REG (CSR_IPSURX_CSR_BASE + 0x32C) /* SVLAN TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_SVLAN_TPID1_REG (CSR_IPSURX_CSR_BASE + 0x330) /* SVLAN TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_SVLAN_TPID0_REG (CSR_IPSURX_CSR_BASE + 0x334) /* SVLAN TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CVLAN_TPID2_REG (CSR_IPSURX_CSR_BASE + 0x338) /* CVLAN-TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CVLAN_TPID1_REG (CSR_IPSURX_CSR_BASE + 0x33C) /* CVLAN-TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CVLAN_TPID0_REG (CSR_IPSURX_CSR_BASE + 0x340) /* CVLAN-TAG TPID���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_P8021_PRI_REG (CSR_IPSURX_CSR_BASE + 0x344) /* 802.1���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_0_REG (CSR_IPSURX_CSR_BASE + 0x348) /* 802.3������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_1_REG (CSR_IPSURX_CSR_BASE + 0x34C) /* 802.3������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_2_REG (CSR_IPSURX_CSR_BASE + 0x350) /* 802.3������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_3_REG (CSR_IPSURX_CSR_BASE + 0x354) /* 802.3������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_4_REG (CSR_IPSURX_CSR_BASE + 0x358) /* 802.3������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_5_REG (CSR_IPSURX_CSR_BASE + 0x35C) /* 802.3������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_6_REG (CSR_IPSURX_CSR_BASE + 0x360) /* 802.3������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_7_REG (CSR_IPSURX_CSR_BASE + 0x364) /* 802.3������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_8_REG (CSR_IPSURX_CSR_BASE + 0x368) /* 802.3������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_9_REG (CSR_IPSURX_CSR_BASE + 0x36C) /* 802.3������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_MAX_LEN_10_REG (CSR_IPSURX_CSR_BASE + 0x370) /* 802.3������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_8023_JUMBO_CFG_REG (CSR_IPSURX_CSR_BASE + 0x374) /* 802.3Jumbo֡���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_L2_DMAC_ETH_CHK_EN_REG \ + (CSR_IPSURX_CSR_BASE + 0x378) /* L2����DMAC/ETH���ʹ�����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RTN_TS_EN_REG (CSR_IPSURX_CSR_BASE + 0x37C) /* �ش�ʱ�����ļĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RTN_TS_REG (CSR_IPSURX_CSR_BASE + 0x380) /* �ش�ʱ�����ļĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_0_REG (CSR_IPSURX_CSR_BASE + 0x384) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_1_REG (CSR_IPSURX_CSR_BASE + 0x388) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_2_REG (CSR_IPSURX_CSR_BASE + 0x38C) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_3_REG (CSR_IPSURX_CSR_BASE + 0x390) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_4_REG (CSR_IPSURX_CSR_BASE + 0x394) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_5_REG (CSR_IPSURX_CSR_BASE + 0x398) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_6_REG (CSR_IPSURX_CSR_BASE + 0x39C) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DSCP_PRI_7_REG (CSR_IPSURX_CSR_BASE + 0x3A0) /* IPv4 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IGMPV4_DIP_CHK_EN_REG (CSR_IPSURX_CSR_BASE + 0x3A4) /* IGMPv4 DIP�����ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_0_REG (CSR_IPSURX_CSR_BASE + 0x3A8) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_1_REG (CSR_IPSURX_CSR_BASE + 0x3AC) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_2_REG (CSR_IPSURX_CSR_BASE + 0x3B0) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_3_REG (CSR_IPSURX_CSR_BASE + 0x3B4) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_4_REG (CSR_IPSURX_CSR_BASE + 0x3B8) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_5_REG (CSR_IPSURX_CSR_BASE + 0x3BC) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_6_REG (CSR_IPSURX_CSR_BASE + 0x3C0) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DSCP_PRI_7_REG (CSR_IPSURX_CSR_BASE + 0x3C4) /* IPv6 DSCP���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_0_REG (CSR_IPSURX_CSR_BASE + 0x3C8) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_1_REG (CSR_IPSURX_CSR_BASE + 0x3CC) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_2_REG (CSR_IPSURX_CSR_BASE + 0x3D0) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_3_REG (CSR_IPSURX_CSR_BASE + 0x3D4) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_4_REG (CSR_IPSURX_CSR_BASE + 0x3D8) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_5_REG (CSR_IPSURX_CSR_BASE + 0x3DC) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_6_REG (CSR_IPSURX_CSR_BASE + 0x3E0) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CSCTL_PRI_7_REG (CSR_IPSURX_CSR_BASE + 0x3E4) /* FC CSCTL���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_0_REG (CSR_IPSURX_CSR_BASE + 0x3E8) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_1_REG (CSR_IPSURX_CSR_BASE + 0x3EC) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_2_REG (CSR_IPSURX_CSR_BASE + 0x3F0) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_3_REG (CSR_IPSURX_CSR_BASE + 0x3F4) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_4_REG (CSR_IPSURX_CSR_BASE + 0x3F8) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_5_REG (CSR_IPSURX_CSR_BASE + 0x3FC) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_6_REG (CSR_IPSURX_CSR_BASE + 0x400) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_7_REG (CSR_IPSURX_CSR_BASE + 0x404) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_8_REG (CSR_IPSURX_CSR_BASE + 0x408) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_9_REG (CSR_IPSURX_CSR_BASE + 0x40C) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_10_REG (CSR_IPSURX_CSR_BASE + 0x410) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_11_REG (CSR_IPSURX_CSR_BASE + 0x414) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_12_REG (CSR_IPSURX_CSR_BASE + 0x418) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_13_REG (CSR_IPSURX_CSR_BASE + 0x41C) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_14_REG (CSR_IPSURX_CSR_BASE + 0x420) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_PRIORITY_PRI_15_REG (CSR_IPSURX_CSR_BASE + 0x424) /* FC PRIORITY���ȼ�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_SPEC_MC_REG (CSR_IPSURX_CSR_BASE + 0x428) /* IPv6ָ���ಥ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_BTH_REG (CSR_IPSURX_CSR_BASE + 0x42C) /* RoCE����BTHͷ���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x430) /* RoCEV2Ŀ��UDP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_NATT_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x434) /* NATTĿ��UDP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_VXLAN_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x438) /* VXLANĿ��UDP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_VXLAN_GPE_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x43C) /* VXLAN GPEĿ��UDP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_GENEVE_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x440) /* GENEVEĿ��UDP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_NP_REG (CSR_IPSURX_CSR_BASE + 0x444) /* IPv4 Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_NP_REG (CSR_IPSURX_CSR_BASE + 0x448) /* IPv6 Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_ETHERNET_NP_REG (CSR_IPSURX_CSR_BASE + 0x44C) /* Ethernet Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_IOAM_NP_REG (CSR_IPSURX_CSR_BASE + 0x450) /* IOAM Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_INT_NP_REG (CSR_IPSURX_CSR_BASE + 0x454) /* INT Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_NSH_NP_REG (CSR_IPSURX_CSR_BASE + 0x458) /* NSH Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_AH_NP_REG (CSR_IPSURX_CSR_BASE + 0x45C) /* AH Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_ESP_NP_REG (CSR_IPSURX_CSR_BASE + 0x460) /* ESP Next Protocol�� */ +#define CSR_IPSURX_CSR_IPSURX_ROB_OPT_CLASS_REG (CSR_IPSURX_CSR_BASE + 0x464) /* ROB���������ĵ�Option Class */ +#define CSR_IPSURX_CSR_IPSURX_PPOP_OPT_CLASS_REG (CSR_IPSURX_CSR_BASE + 0x468) /* PPOP���ĵ�Option Class */ +#define CSR_IPSURX_CSR_IPSURX_TELEMETRY_EN_REG (CSR_IPSURX_CSR_BASE + 0x470) /* Telemetry����ʹ�� */ +#define CSR_IPSURX_CSR_IPSURX_TCP_COCO_WITH_TS_DW0_REG \ + (CSR_IPSURX_CSR_BASE + 0x474) /* ��ʱ����TCP COCO DW0���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCP_COCO_WITHOUT_TS_DW0_REG \ + (CSR_IPSURX_CSR_BASE + 0x478) /* ����ʱ����TCP COCO DW0���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCP_COCO_DW0_MASK_REG (CSR_IPSURX_CSR_BASE + 0x47C) /* TCP COCO DW0�������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_COALESCE_PKT_FWD_ACT_CTRL_REG \ + (CSR_IPSURX_CSR_BASE + 0x480) /* �ۺϱ���ת����Ϊ���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_HCAP_VAL_REG (CSR_IPSURX_CSR_BASE + 0x484) /* HCAP����VAL���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_HCAP_PRI_REG (CSR_IPSURX_CSR_BASE + 0x488) /* HCAP�������ȼ����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_0_REG (CSR_IPSURX_CSR_BASE + 0x48C) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_1_REG (CSR_IPSURX_CSR_BASE + 0x490) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_2_REG (CSR_IPSURX_CSR_BASE + 0x494) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_3_REG (CSR_IPSURX_CSR_BASE + 0x498) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_4_REG (CSR_IPSURX_CSR_BASE + 0x49C) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_5_REG (CSR_IPSURX_CSR_BASE + 0x4A0) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_6_REG (CSR_IPSURX_CSR_BASE + 0x4A4) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_7_REG (CSR_IPSURX_CSR_BASE + 0x4A8) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_8_REG (CSR_IPSURX_CSR_BASE + 0x4AC) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_9_REG (CSR_IPSURX_CSR_BASE + 0x4B0) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_H_10_REG (CSR_IPSURX_CSR_BASE + 0x4B4) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_0_REG (CSR_IPSURX_CSR_BASE + 0x4B8) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_1_REG (CSR_IPSURX_CSR_BASE + 0x4BC) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_2_REG (CSR_IPSURX_CSR_BASE + 0x4C0) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_3_REG (CSR_IPSURX_CSR_BASE + 0x4C4) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_4_REG (CSR_IPSURX_CSR_BASE + 0x4C8) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_5_REG (CSR_IPSURX_CSR_BASE + 0x4CC) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_6_REG (CSR_IPSURX_CSR_BASE + 0x4D0) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_7_REG (CSR_IPSURX_CSR_BASE + 0x4D4) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_8_REG (CSR_IPSURX_CSR_BASE + 0x4D8) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_9_REG (CSR_IPSURX_CSR_BASE + 0x4DC) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_DMAC_L_10_REG (CSR_IPSURX_CSR_BASE + 0x4E0) /* ���Ʊ���DMAC���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_EXT_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x4E4) /* IPv6��չͷ���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_BGP_DPORT_REG (CSR_IPSURX_CSR_BASE + 0x4E8) /* BGPĿ��TCP PORT�� */ +#define CSR_IPSURX_CSR_IPSURX_TCP_OPT_DW0_REG (CSR_IPSURX_CSR_BASE + 0x4EC) /* TCP����option��һ��DW�ȶ�����ֵ */ +#define CSR_IPSURX_CSR_IPSURX_ESP_PRTL_TYPE_REG (CSR_IPSURX_CSR_BASE + 0x4F0) /* ESP Protocol Type�� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_CRC_MASK_DW0_REG (CSR_IPSURX_CSR_BASE + 0x500) /* RoCEv1���ļ���CRC������Ĵ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_CRC_MASK_DW1_REG (CSR_IPSURX_CSR_BASE + 0x504) /* RoCEv1���ļ���CRC������Ĵ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_CRC_MASK_DW2_REG (CSR_IPSURX_CSR_BASE + 0x508) /* RoCEv1���ļ���CRC������Ĵ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_CRC_MASK_DW3_REG (CSR_IPSURX_CSR_BASE + 0x50C) /* RoCEv1���ļ���CRC������Ĵ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_CRC_MASK_DW0_REG \ + (CSR_IPSURX_CSR_BASE + 0x510) /* RoCEv2/IPv4���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_CRC_MASK_DW1_REG \ + (CSR_IPSURX_CSR_BASE + 0x514) /* RoCEv2/IPv4���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_CRC_MASK_DW2_REG \ + (CSR_IPSURX_CSR_BASE + 0x518) /* RoCEv2/IPv4���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_CRC_MASK_DW3_REG \ + (CSR_IPSURX_CSR_BASE + 0x51C) /* RoCEv2/IPv4���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV6_CRC_MASK_DW0_REG \ + (CSR_IPSURX_CSR_BASE + 0x520) /* RoCEv2/IPv6���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV6_CRC_MASK_DW1_REG \ + (CSR_IPSURX_CSR_BASE + 0x524) /* RoCEv2/IPv6���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV6_CRC_MASK_DW2_REG \ + (CSR_IPSURX_CSR_BASE + 0x528) /* RoCEv2/IPv6���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV6_CRC_MASK_DW3_REG \ + (CSR_IPSURX_CSR_BASE + 0x52C) /* RoCEv2/IPv6���ļ���CRC������Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_CRC_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x530) /* IPSURX CRC���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_ICRC_INI_REG (CSR_IPSURX_CSR_BASE + 0x534) /* RoCE ICRC��ʼֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_ICRC_MN_REG (CSR_IPSURX_CSR_BASE + 0x538) /* RoCE����ICRC Magic Numberֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CRC_INI_REG (CSR_IPSURX_CSR_BASE + 0x53C) /* FCoE����CRC ��ʼֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FC_CRC_MN_REG (CSR_IPSURX_CSR_BASE + 0x540) /* FCoE����CRC Magic Numberֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_SCTP_CRC_INI_REG (CSR_IPSURX_CSR_BASE + 0x544) /* SCTP����CRC ��ʼֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_DIFX_CRC_INI_REG (CSR_IPSURX_CSR_BASE + 0x548) /* DIF/DIX CRC16 ��ʼֵ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_MAG_DROP_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x54C) /* MAG������������������ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROB_PPOP_EN_REG (CSR_IPSURX_CSR_BASE + 0x550) /* ROB/PPOP����ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_PORT_MAP_EN_REG (CSR_IPSURX_CSR_BASE + 0x554) /* ���Ķ˿�ӳ��ʹ�ܼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_PORT_MAP_REG (CSR_IPSURX_CSR_BASE + 0x558) /* ���Ķ˿�ӳ��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L2F_OTH_REG \ + (CSR_IPSURX_CSR_BASE + 0x55C) /* L2 Final�������������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L3F_0_REG (CSR_IPSURX_CSR_BASE + 0x560) /* L3 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L3F_1_REG (CSR_IPSURX_CSR_BASE + 0x564) /* L3 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L3F_2_REG (CSR_IPSURX_CSR_BASE + 0x568) /* L3 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L3F_3_REG (CSR_IPSURX_CSR_BASE + 0x56C) /* L3 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L45F_0_REG (CSR_IPSURX_CSR_BASE + 0x570) /* L4-5 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L45F_1_REG (CSR_IPSURX_CSR_BASE + 0x574) /* L4-5 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L45F_2_REG (CSR_IPSURX_CSR_BASE + 0x578) /* L4-5 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_L45F_3_REG (CSR_IPSURX_CSR_BASE + 0x57C) /* L4-5 Final�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PUSH_LEN_FC_REG (CSR_IPSURX_CSR_BASE + 0x580) /* FC�������ͳ������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_EXT_SUMOP_REG (CSR_IPSURX_CSR_BASE + 0x584) /* ROCE��չЭ��SUMOP���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_SR_SUMOP_REG (CSR_IPSURX_CSR_BASE + 0x588) /* Դ·�ɹ�����·��SUMOP���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_EN_REG (CSR_IPSURX_CSR_BASE + 0x58C) /* ���Ʊ���ʶ��ʹ�����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_EXT_LEN_EXC_SUMOP_REG \ + (CSR_IPSURX_CSR_BASE + 0x590) /* ROCE��չЭ�鳬�������SUMOP���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_DRC_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x594) /* ROCE DRC������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_DMAC_ZERO_CNT_REG (CSR_IPSURX_CSR_BASE + 0x600) /* Ŀ��MACΪ0�����ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_SMAC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x604) /* ԴMAC�����ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_DA_SA_EQUAL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x608) /* ԴĿ��MAC��ȱ��ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_ETH_LEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x60C) /* ETH_LEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_DMAC_ZERO_CNT_REG (CSR_IPSURX_CSR_BASE + 0x610) /* Ŀ��MACΪ0�����ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_SMAC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x614) /* ԴMAC�����ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_DA_SA_EQUAL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x618) /* ԴĿ��MAC��ȱ��ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_ETH_LEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x61C) /* ETH_LEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_VER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x620) /* IPV4_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_IHL_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x624) /* IPV4_IHL_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_SIP_DIP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x628) /* IPV4_SIP_DIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_SIP_MC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x62C) /* IPV4_SIP_MC_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_SIP_LB_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x630) /* IPV4_SIP_LB_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DIP_LB_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x634) /* IPV4_DIP_LB_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DIP_ZERO_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x638) /* IPV4_DIP_ZERO_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_DIP_RSV_ADDR_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x63C) /* IPV4_DIP_RSV_ADDR_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x640) /* IPV4_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_UDP_LEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x644) /* IPV4_UDP_LEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV4_TLEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x648) /* IPV4_TLEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_VER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x64C) /* IPV6_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_SIP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x650) /* IPV6_SIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_DIP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x654) /* IPV6_DIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_TLEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x658) /* IPV6_TLEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_VER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x65C) /* IPV4_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_IHL_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x660) /* IPV4_IHL_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_SIP_DIP_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x664) /* IPV4_SIP_DIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_SIP_MC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x668) /* IPV4_SIP_MC_ILGL������ \ + */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_SIP_LB_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x66C) /* IPV4_SIP_LB_ILGL������ \ + */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_DIP_LB_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x670) /* IPV4_DIP_LB_ILGL������ \ + */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_DIP_ZERO_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x674) /* IPV4_DIP_ZERO_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_DIP_RSV_ADDR_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x678) /* IPV4_DIP_RSV_ADDR_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x67C) /* IPV4_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_UDP_LEN_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x680) /* IPV4_UDP_LEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV4_TLEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x684) /* IPV4_TLEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV6_VER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x688) /* IPV6_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV6_SIP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x68C) /* IPV6_SIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV6_DIP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x690) /* IPV6_DIP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV6_TLEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x694) /* IPV6_TLEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_LAND_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x698) /* TCP_LAND_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_DO_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x69C) /* TCP_DO_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_SYN_FIN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6A0) /* TCP_SYN_FIN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_NO_FLAG_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6A4) /* TCP_NO_FLAG_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_FIN_ACK_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6A8) /* TCP_FIN_ACK_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_ACK_RST_SYN_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x6AC) /* TCP_ACK_RST_SYN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TCP_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6B0) /* TCP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IPV6_UDP_CS_ZERO_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6B4) /* IPv6 UDP_CS_ZERO������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_IPV6_UDP_CS_ZERO_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6B8) /* IPv6 UDP_CS_ZERO������ \ + */ +#define CSR_IPSURX_CSR_IPSURX_UDP_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6BC) /* UDP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IGMP_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6C0) /* IGMP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ICMPV4_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6C4) /* ICMPV4_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ICMPV6_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6C8) /* ICMPV6_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_SCTP_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6CC) /* SCTP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_DGID_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6D0) /* ROCEV1_DGID_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_SGID_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6D4) /* ROCEV1_SGID_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_IPVER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6D8) /* ROCEV1_IPVER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_NXHDR_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6DC) /* ROCEV1_NXHDR_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV1_PAYLEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6E0) /* ROCEV1_PAYLEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_FRAG_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x6E4) /* ROCEV2_IPV4_FRAG_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV4_UDP_CS_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x6E8) /* ROCEV2_IPV4_UDP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCEV2_IPV6_UDP_CS_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x6EC) /* ROCEV2_IPV6_UDP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_TVER_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6F0) /* ROCE_TVER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_PKEY_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6F4) /* ROCE_PKEY_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_DQP_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6F8) /* ROCE_DQP_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_PADCNT_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x6FC) /* ROCE_PADCNT_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_VA_8B_ALIGN_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x700) /* ROCE_VA_8B_ALIGN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_DMALEN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x704) /* ROCE_DMALEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_OPCODE_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x708) /* ROCE_OPCODE_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_IB_ICRC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x70C) /* IB_ICRC_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_FC_CRC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x710) /* FC_CRC_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TO_UP_PKT_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x714) /* TO UP����У���������� */ +#define CSR_IPSURX_CSR_IPSURX_TO_BMC_ONLY_PKT_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x718) /* TO BMC ONLY����У���������� */ +#define CSR_IPSURX_CSR_IPSURX_LLC_SNAP_ENC_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x71C) /* LLC_SNAP_ENC_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ETH_TYPE_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x720) /* ETH_TYPE_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_VXLAN_GPE_OTHER_VER_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x724) /* VXLAN_GPE_OTHER_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_GENEVE_OTHER_VER_CNT_REG (CSR_IPSURX_CSR_BASE + 0x728) /* GENEVE_OTHER_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_NSH_OTHER_VER_CNT_REG (CSR_IPSURX_CSR_BASE + 0x72C) /* NSH_OTHER_VER_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_NSH_LEN_CNT_REG (CSR_IPSURX_CSR_BASE + 0x730) /* NSH_LEN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_NVGRE_CVLAN_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x734) /* nvGRE�����ڲ�CVLAN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_HCAP_MD_SIZE_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x738) /* HCAP����MD_SIZE_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_DROP_MFS_PKT_CNT_REG (CSR_IPSURX_CSR_BASE + 0x73C) /* IPSURX��ڶ���MFS���ļ����� */ +#define CSR_IPSURX_CSR_IPSURX_LEN_4B_ALIGN_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x740) /* ROCE/FC/SCTP����payload���ȷ�4B��������� */ +#define CSR_IPSURX_CSR_IPSURX_TUNNEL_UDP_CS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x744) /* UDP_CS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_NVGRE_CRKS_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x748) /* NVGRE_CRKS_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_HDR_LEN_MIN_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x74C) /* PKT_HDR_LEN_MIN_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_PAUSE_PKT_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x750) /* PAUSE_PKT_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_PFC_PKT_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x754) /* PFC_PKT_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_ROCE_EXT_LEN_EXC_CNT_REG (CSR_IPSURX_CSR_BASE + 0x758) /* ROCE_EXT_LEN_EXC������ */ +#define CSR_IPSURX_CSR_IPSURX_IPSEC_AUTH_ILGL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x75C) /* IPSEC_AUTH_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_NATT_IPV4_UDP_CS_ZERO_ILGL_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0x760) /* NATT_IPV4_UDP_CS_ZERO_ILGL������ */ +#define CSR_IPSURX_CSR_IPSURX_TX_CPT_PKT_DROP_CNT_REG (CSR_IPSURX_CSR_BASE + 0x764) /* TX_CPT_PKT_DROP������ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x800) /* NCSI���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_FILTER_MNG_REG (CSR_IPSURX_CSR_BASE + 0x804) /* NCSI FILTER�����Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_H_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x808) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_H_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x80C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_H_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x810) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_H_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x814) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_L_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x818) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_L_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x81C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_L_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x820) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC3_L_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x824) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_H_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x828) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_H_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x82C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_H_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x830) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_H_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x834) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_L_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x838) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_L_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x83C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_L_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x840) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC2_L_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x844) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_H_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x848) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_H_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x84C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_H_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x850) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_H_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x854) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_L_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x858) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_L_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x85C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_L_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x860) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC1_L_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x864) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_H_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x868) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_H_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x86C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_H_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x870) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_H_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x874) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_L_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x878) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_L_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x87C) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_L_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x880) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MAC0_L_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x884) /* NCSI FILTER ��MAC��ַ���ƼĴ��� \ + */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN_EN_REG (CSR_IPSURX_CSR_BASE + 0x888) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN7_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x88C) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN7_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x890) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN7_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x894) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN7_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x898) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN6_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x89C) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN6_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8A0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN6_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8A4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN6_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8A8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN5_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8AC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN5_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8B0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN5_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8B4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN5_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8B8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN4_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8BC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN4_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8C0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN4_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8C4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN4_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8C8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN3_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8CC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN3_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8D0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN3_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8D4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN3_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8D8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN2_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8DC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN2_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8E0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN2_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8E4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN2_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8E8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN1_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8EC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN1_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x8F0) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN1_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x8F4) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN1_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x8F8) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN0_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x8FC) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN0_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x900) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN0_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x904) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VLAN0_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x908) /* NCSI FILTER ��VLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x90C) /* NCSI FILTER �Ĺ㲥���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x910) /* NCSI FILTER �Ĺ㲥���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x914) /* NCSI FILTER �Ĺ㲥���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x918) /* NCSI FILTER �Ĺ㲥���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_ARP_TIPV4_ADDR_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x91C) /* NCSI FILTER��ARP/IPv4���ĵ�Ŀ��IPv4��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_ARP_TIPV4_ADDR_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x920) /* NCSI FILTER��ARP/IPv4���ĵ�Ŀ��IPv4��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_ARP_TIPV4_ADDR_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x924) /* NCSI FILTER��ARP/IPv4���ĵ�Ŀ��IPv4��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_ARP_TIPV4_ADDR_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x928) /* NCSI FILTER��ARP/IPv4���ĵ�Ŀ��IPv4��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_H_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x92C) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_H_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x930) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_H_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x934) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_H_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x938) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_L_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x93C) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_L_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x940) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_L_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x944) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_BC_DHCPV4_CMAC_L_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x948) /* NCSI FILTER��DHCPV4���ĵ�CHADDR��ַ */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MC_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x94C) /* NCSI FILTER �Ķಥ���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MC_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x950) /* NCSI FILTER �Ķಥ���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MC_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x954) /* NCSI FILTER �Ķಥ���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_MC_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x958) /* NCSI FILTER �Ķಥ���Ŀ��ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_EN_REG (CSR_IPSURX_CSR_BASE + 0x95C) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN1_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x960) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN1_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x964) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN1_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x968) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN1_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x96C) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN0_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x970) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN0_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x974) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN0_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x978) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN0_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x97C) /* NCSI FILTER ��VXLAN���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV4_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x980) /* NCSI FILTER ��VXLAN���ĵ�IPv4 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV4_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x984) /* NCSI FILTER ��VXLAN���ĵ�IPv4 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV4_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x988) /* NCSI FILTER ��VXLAN���ĵ�IPv4 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV4_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x98C) /* NCSI FILTER ��VXLAN���ĵ�IPv4 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW3_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x990) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW3_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x994) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW3_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x998) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW3_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x99C) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW2_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x9A0) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW2_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x9A4) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW2_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x9A8) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW2_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x9AC) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW1_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x9B0) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW1_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x9B4) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW1_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x9B8) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW1_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x9BC) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW0_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x9C0) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW0_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x9C4) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW0_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x9C8) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_NCSI_VXLAN_DIPV6_DW0_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x9CC) /* NCSI FILTER ��VXLAN���ĵ�IPv6 DIP */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_0_REG (CSR_IPSURX_CSR_BASE + 0xA00) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_1_REG (CSR_IPSURX_CSR_BASE + 0xA04) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_2_REG (CSR_IPSURX_CSR_BASE + 0xA08) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_3_REG (CSR_IPSURX_CSR_BASE + 0xA0C) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_4_REG (CSR_IPSURX_CSR_BASE + 0xA10) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_5_REG (CSR_IPSURX_CSR_BASE + 0xA14) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_6_REG (CSR_IPSURX_CSR_BASE + 0xA18) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_LLI_TYPE_7_REG (CSR_IPSURX_CSR_BASE + 0xA1C) /* LLI����TYPE�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_KEY_SEL_REG (CSR_IPSURX_CSR_BASE + 0xA20) /* TCAM KEYѡ�����üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_CTRL_REG (CSR_IPSURX_CSR_BASE + 0xA24) /* TCAM���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_MBIST_DONE_REG (CSR_IPSURX_CSR_BASE + 0xA28) /* TCAM MBIST���״̬�ź� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_0_REG (CSR_IPSURX_CSR_BASE + 0xA2C) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_1_REG (CSR_IPSURX_CSR_BASE + 0xA30) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_2_REG (CSR_IPSURX_CSR_BASE + 0xA34) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_3_REG (CSR_IPSURX_CSR_BASE + 0xA38) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_4_REG (CSR_IPSURX_CSR_BASE + 0xA3C) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_5_REG (CSR_IPSURX_CSR_BASE + 0xA40) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_6_REG (CSR_IPSURX_CSR_BASE + 0xA44) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_MASK_7_REG (CSR_IPSURX_CSR_BASE + 0xA48) /* VF������mask���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_VF_TB_CTRL_REG (CSR_IPSURX_CSR_BASE + 0xA4C) /* VF Table���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PORT_ERID_REG (CSR_IPSURX_CSR_BASE + 0xA50) /* PORT->ERID����Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCP_OPCD_TB_REG (CSR_IPSURX_CSR_BASE + 0xA54) /* TCP OPCODE�������üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_MBIST_MEM_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0xA58) /* TCAM MBIST MEM��������� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_MBIST_CMP_ERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0xA5C) /* TCAM MBISTƥ���������� */ +#define CSR_IPSURX_CSR_IPSURX_LB_PORT_ERID_REG (CSR_IPSURX_CSR_BASE + 0xA60) /* ��������PORT->ERID����Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_HIT_CNT_REG (CSR_IPSURX_CSR_BASE + 0xA64) /* Ӳ��TCAM�������м����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xA68) /* ����CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xA6C) /* ����CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xA70) /* ����CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xA74) /* ����CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xA78) /* ����CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xA7C) /* ����CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xA80) /* ����CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_FWD_ACT_CNT_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xA84) /* ����CPB�ı��ĸ���ת����Ϊͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xA88) /* ����CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xA8C) /* ����CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xA90) /* ����CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xA94) /* ����CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xA98) /* ����CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xA9C) /* ����CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xAA0) /* ����CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_CTRL_PKT_CNT_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xAA4) /* ����CPB�ı��Ĵ�CTRL_PKT��ʶͳ�Ƽ����� */ +#define CSR_IPSURX_CSR_IPSURX_VF_HIT_SEL_VF_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0xAA8) /* Ӳ��VF������к�SELΪVF�Ĵ��������� */ +#define CSR_IPSURX_CSR_IPSURX_VF_HIT_SEL_OUT_CNT_REG \ + (CSR_IPSURX_CSR_BASE + 0xAAC) /* Ӳ��VF������к�SELΪOUTPUT PORT�Ĵ��������� */ +#define CSR_IPSURX_CSR_IPSURX_WOL_CTRL_REG (CSR_IPSURX_CSR_BASE + 0xB00) /* WOL���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_CTRL1_REG (CSR_IPSURX_CSR_BASE + 0xB04) /* WOL TYPE1���ļ��RULE���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_CTRL0_REG (CSR_IPSURX_CSR_BASE + 0xB08) /* WOL TYPE1���ļ��RULE���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xB0C) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xB10) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xB14) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xB18) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xB1C) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xB20) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xB24) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_H_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xB28) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xB2C) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xB30) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xB34) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xB38) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xB3C) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xB40) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xB44) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_MAC_L_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xB48) /* WOL TYPE1���ļ��RULE MAC ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xB4C) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xB50) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xB54) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xB58) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xB5C) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xB60) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xB64) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_VLANID_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xB68) /* WOL TYPE1���ļ��RULE VLAN ID�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xB6C) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xB70) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xB74) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xB78) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xB7C) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xB80) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xB84) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW0_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xB88) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xB8C) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xB90) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xB94) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xB98) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xB9C) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xBA0) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xBA4) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW1_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xBA8) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xBAC) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xBB0) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xBB4) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xBB8) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xBBC) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xBC0) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xBC4) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW2_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xBC8) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xBCC) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xBD0) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xBD4) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xBD8) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xBDC) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xBE0) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xBE4) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_IP_DW3_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xBE8) /* WOL TYPE1���ļ��RULE IP��ַ�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xBEC) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xBF0) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xBF4) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xBF8) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xBFC) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC00) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xC04) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_H_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xC08) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xC0C) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xC10) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xC14) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xC18) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xC1C) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC20) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_6_REG \ + (CSR_IPSURX_CSR_BASE + 0xC24) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL1_CHK_NODE_ADDR_L_7_REG \ + (CSR_IPSURX_CSR_BASE + 0xC28) /* MAGIC���ļ��RULE NODE ADDR�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_CTRL_REG (CSR_IPSURX_CSR_BASE + 0xC2C) /* WOL TYPE2���ļ����ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xC30) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xC34) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xC38) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xC3C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xC40) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW0_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC44) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xC48) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xC4C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xC50) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xC54) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xC58) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW1_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC5C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xC60) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xC64) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xC68) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xC6C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xC70) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW2_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC74) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_0_REG \ + (CSR_IPSURX_CSR_BASE + 0xC78) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_1_REG \ + (CSR_IPSURX_CSR_BASE + 0xC7C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_2_REG \ + (CSR_IPSURX_CSR_BASE + 0xC80) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_3_REG \ + (CSR_IPSURX_CSR_BASE + 0xC84) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_4_REG \ + (CSR_IPSURX_CSR_BASE + 0xC88) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_CHK_MASK_DW3_5_REG \ + (CSR_IPSURX_CSR_BASE + 0xC8C) /* WOL TYPE2���ļ��RULE���μĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_0_REG (CSR_IPSURX_CSR_BASE + 0xC90) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_1_REG (CSR_IPSURX_CSR_BASE + 0xC94) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_2_REG (CSR_IPSURX_CSR_BASE + 0xC98) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_3_REG (CSR_IPSURX_CSR_BASE + 0xC9C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_4_REG (CSR_IPSURX_CSR_BASE + 0xCA0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW00_5_REG (CSR_IPSURX_CSR_BASE + 0xCA4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_0_REG (CSR_IPSURX_CSR_BASE + 0xCA8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_1_REG (CSR_IPSURX_CSR_BASE + 0xCAC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_2_REG (CSR_IPSURX_CSR_BASE + 0xCB0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_3_REG (CSR_IPSURX_CSR_BASE + 0xCB4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_4_REG (CSR_IPSURX_CSR_BASE + 0xCB8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW01_5_REG (CSR_IPSURX_CSR_BASE + 0xCBC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_0_REG (CSR_IPSURX_CSR_BASE + 0xCC0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_1_REG (CSR_IPSURX_CSR_BASE + 0xCC4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_2_REG (CSR_IPSURX_CSR_BASE + 0xCC8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_3_REG (CSR_IPSURX_CSR_BASE + 0xCCC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_4_REG (CSR_IPSURX_CSR_BASE + 0xCD0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW02_5_REG (CSR_IPSURX_CSR_BASE + 0xCD4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_0_REG (CSR_IPSURX_CSR_BASE + 0xCD8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_1_REG (CSR_IPSURX_CSR_BASE + 0xCDC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_2_REG (CSR_IPSURX_CSR_BASE + 0xCE0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_3_REG (CSR_IPSURX_CSR_BASE + 0xCE4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_4_REG (CSR_IPSURX_CSR_BASE + 0xCE8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW03_5_REG (CSR_IPSURX_CSR_BASE + 0xCEC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_0_REG (CSR_IPSURX_CSR_BASE + 0xCF0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_1_REG (CSR_IPSURX_CSR_BASE + 0xCF4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_2_REG (CSR_IPSURX_CSR_BASE + 0xCF8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_3_REG (CSR_IPSURX_CSR_BASE + 0xCFC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_4_REG (CSR_IPSURX_CSR_BASE + 0xD00) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW04_5_REG (CSR_IPSURX_CSR_BASE + 0xD04) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_0_REG (CSR_IPSURX_CSR_BASE + 0xD08) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_1_REG (CSR_IPSURX_CSR_BASE + 0xD0C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_2_REG (CSR_IPSURX_CSR_BASE + 0xD10) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_3_REG (CSR_IPSURX_CSR_BASE + 0xD14) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_4_REG (CSR_IPSURX_CSR_BASE + 0xD18) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW05_5_REG (CSR_IPSURX_CSR_BASE + 0xD1C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_0_REG (CSR_IPSURX_CSR_BASE + 0xD20) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_1_REG (CSR_IPSURX_CSR_BASE + 0xD24) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_2_REG (CSR_IPSURX_CSR_BASE + 0xD28) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_3_REG (CSR_IPSURX_CSR_BASE + 0xD2C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_4_REG (CSR_IPSURX_CSR_BASE + 0xD30) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW06_5_REG (CSR_IPSURX_CSR_BASE + 0xD34) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_0_REG (CSR_IPSURX_CSR_BASE + 0xD38) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_1_REG (CSR_IPSURX_CSR_BASE + 0xD3C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_2_REG (CSR_IPSURX_CSR_BASE + 0xD40) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_3_REG (CSR_IPSURX_CSR_BASE + 0xD44) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_4_REG (CSR_IPSURX_CSR_BASE + 0xD48) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW07_5_REG (CSR_IPSURX_CSR_BASE + 0xD4C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_0_REG (CSR_IPSURX_CSR_BASE + 0xD50) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_1_REG (CSR_IPSURX_CSR_BASE + 0xD54) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_2_REG (CSR_IPSURX_CSR_BASE + 0xD58) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_3_REG (CSR_IPSURX_CSR_BASE + 0xD5C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_4_REG (CSR_IPSURX_CSR_BASE + 0xD60) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW08_5_REG (CSR_IPSURX_CSR_BASE + 0xD64) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_0_REG (CSR_IPSURX_CSR_BASE + 0xD68) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_1_REG (CSR_IPSURX_CSR_BASE + 0xD6C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_2_REG (CSR_IPSURX_CSR_BASE + 0xD70) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_3_REG (CSR_IPSURX_CSR_BASE + 0xD74) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_4_REG (CSR_IPSURX_CSR_BASE + 0xD78) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW09_5_REG (CSR_IPSURX_CSR_BASE + 0xD7C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_0_REG (CSR_IPSURX_CSR_BASE + 0xD80) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_1_REG (CSR_IPSURX_CSR_BASE + 0xD84) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_2_REG (CSR_IPSURX_CSR_BASE + 0xD88) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_3_REG (CSR_IPSURX_CSR_BASE + 0xD8C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_4_REG (CSR_IPSURX_CSR_BASE + 0xD90) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW10_5_REG (CSR_IPSURX_CSR_BASE + 0xD94) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_0_REG (CSR_IPSURX_CSR_BASE + 0xD98) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_1_REG (CSR_IPSURX_CSR_BASE + 0xD9C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_2_REG (CSR_IPSURX_CSR_BASE + 0xDA0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_3_REG (CSR_IPSURX_CSR_BASE + 0xDA4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_4_REG (CSR_IPSURX_CSR_BASE + 0xDA8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW11_5_REG (CSR_IPSURX_CSR_BASE + 0xDAC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_0_REG (CSR_IPSURX_CSR_BASE + 0xDB0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_1_REG (CSR_IPSURX_CSR_BASE + 0xDB4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_2_REG (CSR_IPSURX_CSR_BASE + 0xDB8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_3_REG (CSR_IPSURX_CSR_BASE + 0xDBC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_4_REG (CSR_IPSURX_CSR_BASE + 0xDC0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW12_5_REG (CSR_IPSURX_CSR_BASE + 0xDC4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_0_REG (CSR_IPSURX_CSR_BASE + 0xDC8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_1_REG (CSR_IPSURX_CSR_BASE + 0xDCC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_2_REG (CSR_IPSURX_CSR_BASE + 0xDD0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_3_REG (CSR_IPSURX_CSR_BASE + 0xDD4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_4_REG (CSR_IPSURX_CSR_BASE + 0xDD8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW13_5_REG (CSR_IPSURX_CSR_BASE + 0xDDC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_0_REG (CSR_IPSURX_CSR_BASE + 0xDE0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_1_REG (CSR_IPSURX_CSR_BASE + 0xDE4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_2_REG (CSR_IPSURX_CSR_BASE + 0xDE8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_3_REG (CSR_IPSURX_CSR_BASE + 0xDEC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_4_REG (CSR_IPSURX_CSR_BASE + 0xDF0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW14_5_REG (CSR_IPSURX_CSR_BASE + 0xDF4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_0_REG (CSR_IPSURX_CSR_BASE + 0xDF8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_1_REG (CSR_IPSURX_CSR_BASE + 0xDFC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_2_REG (CSR_IPSURX_CSR_BASE + 0xE00) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_3_REG (CSR_IPSURX_CSR_BASE + 0xE04) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_4_REG (CSR_IPSURX_CSR_BASE + 0xE08) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW15_5_REG (CSR_IPSURX_CSR_BASE + 0xE0C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_0_REG (CSR_IPSURX_CSR_BASE + 0xE10) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_1_REG (CSR_IPSURX_CSR_BASE + 0xE14) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_2_REG (CSR_IPSURX_CSR_BASE + 0xE18) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_3_REG (CSR_IPSURX_CSR_BASE + 0xE1C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_4_REG (CSR_IPSURX_CSR_BASE + 0xE20) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW16_5_REG (CSR_IPSURX_CSR_BASE + 0xE24) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_0_REG (CSR_IPSURX_CSR_BASE + 0xE28) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_1_REG (CSR_IPSURX_CSR_BASE + 0xE2C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_2_REG (CSR_IPSURX_CSR_BASE + 0xE30) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_3_REG (CSR_IPSURX_CSR_BASE + 0xE34) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_4_REG (CSR_IPSURX_CSR_BASE + 0xE38) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW17_5_REG (CSR_IPSURX_CSR_BASE + 0xE3C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_0_REG (CSR_IPSURX_CSR_BASE + 0xE40) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_1_REG (CSR_IPSURX_CSR_BASE + 0xE44) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_2_REG (CSR_IPSURX_CSR_BASE + 0xE48) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_3_REG (CSR_IPSURX_CSR_BASE + 0xE4C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_4_REG (CSR_IPSURX_CSR_BASE + 0xE50) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW18_5_REG (CSR_IPSURX_CSR_BASE + 0xE54) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_0_REG (CSR_IPSURX_CSR_BASE + 0xE58) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_1_REG (CSR_IPSURX_CSR_BASE + 0xE5C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_2_REG (CSR_IPSURX_CSR_BASE + 0xE60) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_3_REG (CSR_IPSURX_CSR_BASE + 0xE64) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_4_REG (CSR_IPSURX_CSR_BASE + 0xE68) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW19_5_REG (CSR_IPSURX_CSR_BASE + 0xE6C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_0_REG (CSR_IPSURX_CSR_BASE + 0xE70) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_1_REG (CSR_IPSURX_CSR_BASE + 0xE74) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_2_REG (CSR_IPSURX_CSR_BASE + 0xE78) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_3_REG (CSR_IPSURX_CSR_BASE + 0xE7C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_4_REG (CSR_IPSURX_CSR_BASE + 0xE80) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW20_5_REG (CSR_IPSURX_CSR_BASE + 0xE84) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_0_REG (CSR_IPSURX_CSR_BASE + 0xE88) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_1_REG (CSR_IPSURX_CSR_BASE + 0xE8C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_2_REG (CSR_IPSURX_CSR_BASE + 0xE90) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_3_REG (CSR_IPSURX_CSR_BASE + 0xE94) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_4_REG (CSR_IPSURX_CSR_BASE + 0xE98) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW21_5_REG (CSR_IPSURX_CSR_BASE + 0xE9C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_0_REG (CSR_IPSURX_CSR_BASE + 0xEA0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_1_REG (CSR_IPSURX_CSR_BASE + 0xEA4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_2_REG (CSR_IPSURX_CSR_BASE + 0xEA8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_3_REG (CSR_IPSURX_CSR_BASE + 0xEAC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_4_REG (CSR_IPSURX_CSR_BASE + 0xEB0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW22_5_REG (CSR_IPSURX_CSR_BASE + 0xEB4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_0_REG (CSR_IPSURX_CSR_BASE + 0xEB8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_1_REG (CSR_IPSURX_CSR_BASE + 0xEBC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_2_REG (CSR_IPSURX_CSR_BASE + 0xEC0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_3_REG (CSR_IPSURX_CSR_BASE + 0xEC4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_4_REG (CSR_IPSURX_CSR_BASE + 0xEC8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW23_5_REG (CSR_IPSURX_CSR_BASE + 0xECC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_0_REG (CSR_IPSURX_CSR_BASE + 0xED0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_1_REG (CSR_IPSURX_CSR_BASE + 0xED4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_2_REG (CSR_IPSURX_CSR_BASE + 0xED8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_3_REG (CSR_IPSURX_CSR_BASE + 0xEDC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_4_REG (CSR_IPSURX_CSR_BASE + 0xEE0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW24_5_REG (CSR_IPSURX_CSR_BASE + 0xEE4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_0_REG (CSR_IPSURX_CSR_BASE + 0xEE8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_1_REG (CSR_IPSURX_CSR_BASE + 0xEEC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_2_REG (CSR_IPSURX_CSR_BASE + 0xEF0) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_3_REG (CSR_IPSURX_CSR_BASE + 0xEF4) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_4_REG (CSR_IPSURX_CSR_BASE + 0xEF8) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW25_5_REG (CSR_IPSURX_CSR_BASE + 0xEFC) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_0_REG (CSR_IPSURX_CSR_BASE + 0xF00) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_1_REG (CSR_IPSURX_CSR_BASE + 0xF04) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_2_REG (CSR_IPSURX_CSR_BASE + 0xF08) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_3_REG (CSR_IPSURX_CSR_BASE + 0xF0C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_4_REG (CSR_IPSURX_CSR_BASE + 0xF10) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW26_5_REG (CSR_IPSURX_CSR_BASE + 0xF14) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_0_REG (CSR_IPSURX_CSR_BASE + 0xF18) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_1_REG (CSR_IPSURX_CSR_BASE + 0xF1C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_2_REG (CSR_IPSURX_CSR_BASE + 0xF20) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_3_REG (CSR_IPSURX_CSR_BASE + 0xF24) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_4_REG (CSR_IPSURX_CSR_BASE + 0xF28) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW27_5_REG (CSR_IPSURX_CSR_BASE + 0xF2C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_0_REG (CSR_IPSURX_CSR_BASE + 0xF30) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_1_REG (CSR_IPSURX_CSR_BASE + 0xF34) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_2_REG (CSR_IPSURX_CSR_BASE + 0xF38) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_3_REG (CSR_IPSURX_CSR_BASE + 0xF3C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_4_REG (CSR_IPSURX_CSR_BASE + 0xF40) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW28_5_REG (CSR_IPSURX_CSR_BASE + 0xF44) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_0_REG (CSR_IPSURX_CSR_BASE + 0xF48) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_1_REG (CSR_IPSURX_CSR_BASE + 0xF4C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_2_REG (CSR_IPSURX_CSR_BASE + 0xF50) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_3_REG (CSR_IPSURX_CSR_BASE + 0xF54) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_4_REG (CSR_IPSURX_CSR_BASE + 0xF58) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW29_5_REG (CSR_IPSURX_CSR_BASE + 0xF5C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_0_REG (CSR_IPSURX_CSR_BASE + 0xF60) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_1_REG (CSR_IPSURX_CSR_BASE + 0xF64) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_2_REG (CSR_IPSURX_CSR_BASE + 0xF68) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_3_REG (CSR_IPSURX_CSR_BASE + 0xF6C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_4_REG (CSR_IPSURX_CSR_BASE + 0xF70) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW30_5_REG (CSR_IPSURX_CSR_BASE + 0xF74) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_0_REG (CSR_IPSURX_CSR_BASE + 0xF78) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_1_REG (CSR_IPSURX_CSR_BASE + 0xF7C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_2_REG (CSR_IPSURX_CSR_BASE + 0xF80) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_3_REG (CSR_IPSURX_CSR_BASE + 0xF84) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_4_REG (CSR_IPSURX_CSR_BASE + 0xF88) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL2_PKT_DW31_5_REG (CSR_IPSURX_CSR_BASE + 0xF8C) /* WOL TYPE2 RULE�û��Զ��屨�� */ +#define CSR_IPSURX_CSR_IPSURX_WOL_HIT_CNT_REG (CSR_IPSURX_CSR_BASE + 0xF90) /* WOL�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_OFS_CTRL_DW0_REG (CSR_IPSURX_CSR_BASE + 0x1000) /* ����ƥ��DFXƫ������ */ +#define CSR_IPSURX_CSR_IPSURX_CPT_OFS_CTRL_DW1_REG (CSR_IPSURX_CSR_BASE + 0x1004) /* ����ƥ��DFXƫ������ */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x1008) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x100C) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x1010) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x1014) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_4_REG (CSR_IPSURX_CSR_BASE + 0x1018) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_5_REG (CSR_IPSURX_CSR_BASE + 0x101C) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_6_REG (CSR_IPSURX_CSR_BASE + 0x1020) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_COM_CTRL_7_REG (CSR_IPSURX_CSR_BASE + 0x1024) /* ����ƥ��DFX�������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_0_REG (CSR_IPSURX_CSR_BASE + 0x1028) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_1_REG (CSR_IPSURX_CSR_BASE + 0x102C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_2_REG (CSR_IPSURX_CSR_BASE + 0x1030) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_3_REG (CSR_IPSURX_CSR_BASE + 0x1034) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_4_REG (CSR_IPSURX_CSR_BASE + 0x1038) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_5_REG (CSR_IPSURX_CSR_BASE + 0x103C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_6_REG (CSR_IPSURX_CSR_BASE + 0x1040) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW0_7_REG (CSR_IPSURX_CSR_BASE + 0x1044) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_0_REG (CSR_IPSURX_CSR_BASE + 0x1048) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_1_REG (CSR_IPSURX_CSR_BASE + 0x104C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_2_REG (CSR_IPSURX_CSR_BASE + 0x1050) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_3_REG (CSR_IPSURX_CSR_BASE + 0x1054) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_4_REG (CSR_IPSURX_CSR_BASE + 0x1058) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_5_REG (CSR_IPSURX_CSR_BASE + 0x105C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_6_REG (CSR_IPSURX_CSR_BASE + 0x1060) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW1_7_REG (CSR_IPSURX_CSR_BASE + 0x1064) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_0_REG (CSR_IPSURX_CSR_BASE + 0x1068) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_1_REG (CSR_IPSURX_CSR_BASE + 0x106C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_2_REG (CSR_IPSURX_CSR_BASE + 0x1070) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_3_REG (CSR_IPSURX_CSR_BASE + 0x1074) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_4_REG (CSR_IPSURX_CSR_BASE + 0x1078) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_5_REG (CSR_IPSURX_CSR_BASE + 0x107C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_6_REG (CSR_IPSURX_CSR_BASE + 0x1080) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW2_7_REG (CSR_IPSURX_CSR_BASE + 0x1084) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_0_REG (CSR_IPSURX_CSR_BASE + 0x1088) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_1_REG (CSR_IPSURX_CSR_BASE + 0x108C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_2_REG (CSR_IPSURX_CSR_BASE + 0x1090) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_3_REG (CSR_IPSURX_CSR_BASE + 0x1094) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_4_REG (CSR_IPSURX_CSR_BASE + 0x1098) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_5_REG (CSR_IPSURX_CSR_BASE + 0x109C) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_6_REG (CSR_IPSURX_CSR_BASE + 0x10A0) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_MAC_DW3_7_REG (CSR_IPSURX_CSR_BASE + 0x10A4) /* ����ƥ��DFX MAC���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x10A8) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x10AC) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x10B0) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x10B4) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_4_REG (CSR_IPSURX_CSR_BASE + 0x10B8) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_5_REG (CSR_IPSURX_CSR_BASE + 0x10BC) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_6_REG (CSR_IPSURX_CSR_BASE + 0x10C0) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VLAN_CTRL_7_REG (CSR_IPSURX_CSR_BASE + 0x10C4) /* ����ƥ��DFX VLAN���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_0_REG (CSR_IPSURX_CSR_BASE + 0x10C8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_1_REG (CSR_IPSURX_CSR_BASE + 0x10CC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_2_REG (CSR_IPSURX_CSR_BASE + 0x10D0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_3_REG (CSR_IPSURX_CSR_BASE + 0x10D4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_4_REG (CSR_IPSURX_CSR_BASE + 0x10D8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_5_REG (CSR_IPSURX_CSR_BASE + 0x10DC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_6_REG (CSR_IPSURX_CSR_BASE + 0x10E0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW0_7_REG (CSR_IPSURX_CSR_BASE + 0x10E4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_0_REG (CSR_IPSURX_CSR_BASE + 0x10E8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_1_REG (CSR_IPSURX_CSR_BASE + 0x10EC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_2_REG (CSR_IPSURX_CSR_BASE + 0x10F0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_3_REG (CSR_IPSURX_CSR_BASE + 0x10F4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_4_REG (CSR_IPSURX_CSR_BASE + 0x10F8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_5_REG (CSR_IPSURX_CSR_BASE + 0x10FC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_6_REG (CSR_IPSURX_CSR_BASE + 0x1100) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW1_7_REG (CSR_IPSURX_CSR_BASE + 0x1104) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_0_REG (CSR_IPSURX_CSR_BASE + 0x1108) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_1_REG (CSR_IPSURX_CSR_BASE + 0x110C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_2_REG (CSR_IPSURX_CSR_BASE + 0x1110) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_3_REG (CSR_IPSURX_CSR_BASE + 0x1114) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_4_REG (CSR_IPSURX_CSR_BASE + 0x1118) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_5_REG (CSR_IPSURX_CSR_BASE + 0x111C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_6_REG (CSR_IPSURX_CSR_BASE + 0x1120) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW2_7_REG (CSR_IPSURX_CSR_BASE + 0x1124) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_0_REG (CSR_IPSURX_CSR_BASE + 0x1128) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_1_REG (CSR_IPSURX_CSR_BASE + 0x112C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_2_REG (CSR_IPSURX_CSR_BASE + 0x1130) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_3_REG (CSR_IPSURX_CSR_BASE + 0x1134) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_4_REG (CSR_IPSURX_CSR_BASE + 0x1138) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_5_REG (CSR_IPSURX_CSR_BASE + 0x113C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_6_REG (CSR_IPSURX_CSR_BASE + 0x1140) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW3_7_REG (CSR_IPSURX_CSR_BASE + 0x1144) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_0_REG (CSR_IPSURX_CSR_BASE + 0x1148) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_1_REG (CSR_IPSURX_CSR_BASE + 0x114C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_2_REG (CSR_IPSURX_CSR_BASE + 0x1150) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_3_REG (CSR_IPSURX_CSR_BASE + 0x1154) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_4_REG (CSR_IPSURX_CSR_BASE + 0x1158) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_5_REG (CSR_IPSURX_CSR_BASE + 0x115C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_6_REG (CSR_IPSURX_CSR_BASE + 0x1160) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW4_7_REG (CSR_IPSURX_CSR_BASE + 0x1164) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_0_REG (CSR_IPSURX_CSR_BASE + 0x1168) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_1_REG (CSR_IPSURX_CSR_BASE + 0x116C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_2_REG (CSR_IPSURX_CSR_BASE + 0x1170) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_3_REG (CSR_IPSURX_CSR_BASE + 0x1174) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_4_REG (CSR_IPSURX_CSR_BASE + 0x1178) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_5_REG (CSR_IPSURX_CSR_BASE + 0x117C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_6_REG (CSR_IPSURX_CSR_BASE + 0x1180) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW5_7_REG (CSR_IPSURX_CSR_BASE + 0x1184) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_0_REG (CSR_IPSURX_CSR_BASE + 0x1188) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_1_REG (CSR_IPSURX_CSR_BASE + 0x118C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_2_REG (CSR_IPSURX_CSR_BASE + 0x1190) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_3_REG (CSR_IPSURX_CSR_BASE + 0x1194) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_4_REG (CSR_IPSURX_CSR_BASE + 0x1198) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_5_REG (CSR_IPSURX_CSR_BASE + 0x119C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_6_REG (CSR_IPSURX_CSR_BASE + 0x11A0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW6_7_REG (CSR_IPSURX_CSR_BASE + 0x11A4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_0_REG (CSR_IPSURX_CSR_BASE + 0x11A8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_1_REG (CSR_IPSURX_CSR_BASE + 0x11AC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_2_REG (CSR_IPSURX_CSR_BASE + 0x11B0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_3_REG (CSR_IPSURX_CSR_BASE + 0x11B4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_4_REG (CSR_IPSURX_CSR_BASE + 0x11B8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_5_REG (CSR_IPSURX_CSR_BASE + 0x11BC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_6_REG (CSR_IPSURX_CSR_BASE + 0x11C0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW7_7_REG (CSR_IPSURX_CSR_BASE + 0x11C4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_0_REG (CSR_IPSURX_CSR_BASE + 0x11C8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_1_REG (CSR_IPSURX_CSR_BASE + 0x11CC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_2_REG (CSR_IPSURX_CSR_BASE + 0x11D0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_3_REG (CSR_IPSURX_CSR_BASE + 0x11D4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_4_REG (CSR_IPSURX_CSR_BASE + 0x11D8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_5_REG (CSR_IPSURX_CSR_BASE + 0x11DC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_6_REG (CSR_IPSURX_CSR_BASE + 0x11E0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW8_7_REG (CSR_IPSURX_CSR_BASE + 0x11E4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_0_REG (CSR_IPSURX_CSR_BASE + 0x11E8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_1_REG (CSR_IPSURX_CSR_BASE + 0x11EC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_2_REG (CSR_IPSURX_CSR_BASE + 0x11F0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_3_REG (CSR_IPSURX_CSR_BASE + 0x11F4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_4_REG (CSR_IPSURX_CSR_BASE + 0x11F8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_5_REG (CSR_IPSURX_CSR_BASE + 0x11FC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_6_REG (CSR_IPSURX_CSR_BASE + 0x1200) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW9_7_REG (CSR_IPSURX_CSR_BASE + 0x1204) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_0_REG (CSR_IPSURX_CSR_BASE + 0x1208) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_1_REG (CSR_IPSURX_CSR_BASE + 0x120C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_2_REG (CSR_IPSURX_CSR_BASE + 0x1210) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_3_REG (CSR_IPSURX_CSR_BASE + 0x1214) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_4_REG (CSR_IPSURX_CSR_BASE + 0x1218) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_5_REG (CSR_IPSURX_CSR_BASE + 0x121C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_6_REG (CSR_IPSURX_CSR_BASE + 0x1220) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW10_7_REG (CSR_IPSURX_CSR_BASE + 0x1224) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_0_REG (CSR_IPSURX_CSR_BASE + 0x1228) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_1_REG (CSR_IPSURX_CSR_BASE + 0x122C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_2_REG (CSR_IPSURX_CSR_BASE + 0x1230) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_3_REG (CSR_IPSURX_CSR_BASE + 0x1234) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_4_REG (CSR_IPSURX_CSR_BASE + 0x1238) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_5_REG (CSR_IPSURX_CSR_BASE + 0x123C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_6_REG (CSR_IPSURX_CSR_BASE + 0x1240) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW11_7_REG (CSR_IPSURX_CSR_BASE + 0x1244) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_0_REG (CSR_IPSURX_CSR_BASE + 0x1248) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_1_REG (CSR_IPSURX_CSR_BASE + 0x124C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_2_REG (CSR_IPSURX_CSR_BASE + 0x1250) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_3_REG (CSR_IPSURX_CSR_BASE + 0x1254) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_4_REG (CSR_IPSURX_CSR_BASE + 0x1258) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_5_REG (CSR_IPSURX_CSR_BASE + 0x125C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_6_REG (CSR_IPSURX_CSR_BASE + 0x1260) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW12_7_REG (CSR_IPSURX_CSR_BASE + 0x1264) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_0_REG (CSR_IPSURX_CSR_BASE + 0x1268) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_1_REG (CSR_IPSURX_CSR_BASE + 0x126C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_2_REG (CSR_IPSURX_CSR_BASE + 0x1270) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_3_REG (CSR_IPSURX_CSR_BASE + 0x1274) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_4_REG (CSR_IPSURX_CSR_BASE + 0x1278) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_5_REG (CSR_IPSURX_CSR_BASE + 0x127C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_6_REG (CSR_IPSURX_CSR_BASE + 0x1280) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW13_7_REG (CSR_IPSURX_CSR_BASE + 0x1284) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_0_REG (CSR_IPSURX_CSR_BASE + 0x1288) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_1_REG (CSR_IPSURX_CSR_BASE + 0x128C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_2_REG (CSR_IPSURX_CSR_BASE + 0x1290) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_3_REG (CSR_IPSURX_CSR_BASE + 0x1294) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_4_REG (CSR_IPSURX_CSR_BASE + 0x1298) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_5_REG (CSR_IPSURX_CSR_BASE + 0x129C) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_6_REG (CSR_IPSURX_CSR_BASE + 0x12A0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW14_7_REG (CSR_IPSURX_CSR_BASE + 0x12A4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_0_REG (CSR_IPSURX_CSR_BASE + 0x12A8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_1_REG (CSR_IPSURX_CSR_BASE + 0x12AC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_2_REG (CSR_IPSURX_CSR_BASE + 0x12B0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_3_REG (CSR_IPSURX_CSR_BASE + 0x12B4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_4_REG (CSR_IPSURX_CSR_BASE + 0x12B8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_5_REG (CSR_IPSURX_CSR_BASE + 0x12BC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_6_REG (CSR_IPSURX_CSR_BASE + 0x12C0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW15_7_REG (CSR_IPSURX_CSR_BASE + 0x12C4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_0_REG (CSR_IPSURX_CSR_BASE + 0x12C8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_1_REG (CSR_IPSURX_CSR_BASE + 0x12CC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_2_REG (CSR_IPSURX_CSR_BASE + 0x12D0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_3_REG (CSR_IPSURX_CSR_BASE + 0x12D4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_4_REG (CSR_IPSURX_CSR_BASE + 0x12D8) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_5_REG (CSR_IPSURX_CSR_BASE + 0x12DC) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_6_REG (CSR_IPSURX_CSR_BASE + 0x12E0) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_IP_DW16_7_REG (CSR_IPSURX_CSR_BASE + 0x12E4) /* ����ƥ��DFX IP���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_0_REG (CSR_IPSURX_CSR_BASE + 0x12E8) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_1_REG (CSR_IPSURX_CSR_BASE + 0x12EC) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_2_REG (CSR_IPSURX_CSR_BASE + 0x12F0) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_3_REG (CSR_IPSURX_CSR_BASE + 0x12F4) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_4_REG (CSR_IPSURX_CSR_BASE + 0x12F8) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_5_REG (CSR_IPSURX_CSR_BASE + 0x12FC) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_6_REG (CSR_IPSURX_CSR_BASE + 0x1300) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW0_7_REG (CSR_IPSURX_CSR_BASE + 0x1304) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_0_REG (CSR_IPSURX_CSR_BASE + 0x1308) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_1_REG (CSR_IPSURX_CSR_BASE + 0x130C) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_2_REG (CSR_IPSURX_CSR_BASE + 0x1310) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_3_REG (CSR_IPSURX_CSR_BASE + 0x1314) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_4_REG (CSR_IPSURX_CSR_BASE + 0x1318) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_5_REG (CSR_IPSURX_CSR_BASE + 0x131C) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_6_REG (CSR_IPSURX_CSR_BASE + 0x1320) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_L4_DW1_7_REG (CSR_IPSURX_CSR_BASE + 0x1324) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_0_REG (CSR_IPSURX_CSR_BASE + 0x1328) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_1_REG (CSR_IPSURX_CSR_BASE + 0x132C) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_2_REG (CSR_IPSURX_CSR_BASE + 0x1330) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_3_REG (CSR_IPSURX_CSR_BASE + 0x1334) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_4_REG (CSR_IPSURX_CSR_BASE + 0x1338) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_5_REG (CSR_IPSURX_CSR_BASE + 0x133C) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_6_REG (CSR_IPSURX_CSR_BASE + 0x1340) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_VXLAN_CTRL_7_REG (CSR_IPSURX_CSR_BASE + 0x1344) /* ����ƥ��DFX L4���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_TX_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x1348) /* TX����ƥ��DFX���� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_0_REG (CSR_IPSURX_CSR_BASE + 0x134C) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_1_REG (CSR_IPSURX_CSR_BASE + 0x1350) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_2_REG (CSR_IPSURX_CSR_BASE + 0x1354) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_3_REG (CSR_IPSURX_CSR_BASE + 0x1358) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_4_REG (CSR_IPSURX_CSR_BASE + 0x135C) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_5_REG (CSR_IPSURX_CSR_BASE + 0x1360) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_6_REG (CSR_IPSURX_CSR_BASE + 0x1364) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_CPT_HIT_CNT_7_REG (CSR_IPSURX_CSR_BASE + 0x1368) /* ����ƥ��DFX�������еĴ��������� */ +#define CSR_IPSURX_CSR_IPSURX_UNCRT_ERR_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x1400) /* IPSURX����������ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_FIFO_TH_REG (CSR_IPSURX_CSR_BASE + 0x1404) /* IPSURX FIFO���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAMMOD_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x1408) /* IPSURXģ��RAM MOD���ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_ERR_CHK_BYPASS_REG \ + (CSR_IPSURX_CSR_BASE + 0x140C) /* IPSURXģ��RAM������BYPASS�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_ERR_INJ_REG (CSR_IPSURX_CSR_BASE + 0x1410) /* IPSURXģ��RAM����ע��Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FIFO_STS2_REG (CSR_IPSURX_CSR_BASE + 0x1414) /* IPSURX FIFO��ǰ״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FIFO_STS1_REG (CSR_IPSURX_CSR_BASE + 0x1418) /* IPSURX FIFO��ǰ״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_FIFO_STS0_REG (CSR_IPSURX_CSR_BASE + 0x141C) /* IPSURX FIFO��ǰ״̬�Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_UCERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x1420) /* IPSURX RAM���ɾ���������� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CERR_CNT_REG (CSR_IPSURX_CSR_BASE + 0x1424) /* IPSURX RAM�ɾ���������� */ +#define CSR_IPSURX_CSR_IPSURX_RCV_BP_CNT_REG (CSR_IPSURX_CSR_BASE + 0x1428) /* IPSURX���շ�ѹ���������� */ +#define CSR_IPSURX_CSR_IPSURX_MFS_GEN_BP_CNT_REG (CSR_IPSURX_CSR_BASE + 0x142C) /* IPSURX������ѹ���������� */ +#define CSR_IPSURX_CSR_IPSURX_RENQF_MFS_PERX_TH_GAP_REG \ + (CSR_IPSURX_CSR_BASE + 0x1430) /* IPSURX RENQ FIFO��MFS��PERX���ĵ�ˮ��GAP���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_LB_RTS_CRDT_STS_REG (CSR_IPSURX_CSR_BASE + 0x1434) /* ���ؼ��ش�ʱ��ͨ������״̬ */ +#define CSR_IPSURX_CSR_IPSURX_PRM_BP_RAND_CNT_REG (CSR_IPSURX_CSR_BASE + 0x1438) /* PRM�������������������������� */ +#define CSR_IPSURX_CSR_IPSURX_PRM_BP_ALL_CNT_REG (CSR_IPSURX_CSR_BASE + 0x143C) /* PRM���������ȫ���������������� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CTRL_BUS_DW0_REG (CSR_IPSURX_CSR_BASE + 0x1440) /* IPSURX RAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CTRL_BUS_DW1_REG (CSR_IPSURX_CSR_BASE + 0x1444) /* IPSURX RAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CTRL_BUS_DW2_REG (CSR_IPSURX_CSR_BASE + 0x1448) /* IPSURX RAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CTRL_BUS_DW3_REG (CSR_IPSURX_CSR_BASE + 0x144C) /* IPSURX RAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_RAM_CTRL_BUS_DW4_REG (CSR_IPSURX_CSR_BASE + 0x1450) /* IPSURX RAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_TCAM_CTRL_BUS_REG (CSR_IPSURX_CSR_BASE + 0x1454) /* IPSURX TCAM CTRL_BUS���üĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_LB_CRDTF_TH_REG (CSR_IPSURX_CSR_BASE + 0x1458) /* IPSURX LB CRDT FIFO���Ĵ��� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_0_REG (CSR_IPSURX_CSR_BASE + 0x1500) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_1_REG (CSR_IPSURX_CSR_BASE + 0x1504) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_2_REG (CSR_IPSURX_CSR_BASE + 0x1508) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_3_REG (CSR_IPSURX_CSR_BASE + 0x150C) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_4_REG (CSR_IPSURX_CSR_BASE + 0x1510) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_5_REG (CSR_IPSURX_CSR_BASE + 0x1514) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_6_REG (CSR_IPSURX_CSR_BASE + 0x1518) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_7_REG (CSR_IPSURX_CSR_BASE + 0x151C) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_8_REG (CSR_IPSURX_CSR_BASE + 0x1520) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_9_REG (CSR_IPSURX_CSR_BASE + 0x1524) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_RX_PKT_CNT_10_REG (CSR_IPSURX_CSR_BASE + 0x1528) /* ͨ�����ձ������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_0_REG (CSR_IPSURX_CSR_BASE + 0x152C) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_1_REG (CSR_IPSURX_CSR_BASE + 0x1530) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_2_REG (CSR_IPSURX_CSR_BASE + 0x1534) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_3_REG (CSR_IPSURX_CSR_BASE + 0x1538) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_4_REG (CSR_IPSURX_CSR_BASE + 0x153C) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_5_REG (CSR_IPSURX_CSR_BASE + 0x1540) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_6_REG (CSR_IPSURX_CSR_BASE + 0x1544) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_7_REG (CSR_IPSURX_CSR_BASE + 0x1548) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_8_REG (CSR_IPSURX_CSR_BASE + 0x154C) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_9_REG (CSR_IPSURX_CSR_BASE + 0x1550) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_TX_PKT_CNT_10_REG (CSR_IPSURX_CSR_BASE + 0x1554) /* ͨ�����͵�CPB�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_0_REG (CSR_IPSURX_CSR_BASE + 0x1558) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_1_REG (CSR_IPSURX_CSR_BASE + 0x155C) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_2_REG (CSR_IPSURX_CSR_BASE + 0x1560) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_3_REG (CSR_IPSURX_CSR_BASE + 0x1564) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_4_REG (CSR_IPSURX_CSR_BASE + 0x1568) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_5_REG (CSR_IPSURX_CSR_BASE + 0x156C) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_6_REG (CSR_IPSURX_CSR_BASE + 0x1570) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_7_REG (CSR_IPSURX_CSR_BASE + 0x1574) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_8_REG (CSR_IPSURX_CSR_BASE + 0x1578) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_9_REG (CSR_IPSURX_CSR_BASE + 0x157C) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_CNP_PKT_CNT_10_REG (CSR_IPSURX_CSR_BASE + 0x1580) /* ͨ������CNP�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_0_REG (CSR_IPSURX_CSR_BASE + 0x1584) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_1_REG (CSR_IPSURX_CSR_BASE + 0x1588) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_2_REG (CSR_IPSURX_CSR_BASE + 0x158C) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_3_REG (CSR_IPSURX_CSR_BASE + 0x1590) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_4_REG (CSR_IPSURX_CSR_BASE + 0x1594) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_5_REG (CSR_IPSURX_CSR_BASE + 0x1598) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_6_REG (CSR_IPSURX_CSR_BASE + 0x159C) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_7_REG (CSR_IPSURX_CSR_BASE + 0x15A0) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_8_REG (CSR_IPSURX_CSR_BASE + 0x15A4) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_9_REG (CSR_IPSURX_CSR_BASE + 0x15A8) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_ECN_PKT_CNT_10_REG (CSR_IPSURX_CSR_BASE + 0x15AC) /* ͨ������ECN�������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT_CNT_CFG_REG \ + (CSR_IPSURX_CSR_BASE + 0x15B0) /* ����COS�ı���������������Ӧ��PORT���� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x15B4) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x15B8) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x15BC) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x15C0) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_4_REG \ + (CSR_IPSURX_CSR_BASE + 0x15C4) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_5_REG \ + (CSR_IPSURX_CSR_BASE + 0x15C8) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_6_REG \ + (CSR_IPSURX_CSR_BASE + 0x15CC) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT1_COS_CNT_7_REG \ + (CSR_IPSURX_CSR_BASE + 0x15D0) /* ���õ�PORT1��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x15D4) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x15D8) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x15DC) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x15E0) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_4_REG \ + (CSR_IPSURX_CSR_BASE + 0x15E4) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_5_REG \ + (CSR_IPSURX_CSR_BASE + 0x15E8) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_6_REG \ + (CSR_IPSURX_CSR_BASE + 0x15EC) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_PORT0_COS_CNT_7_REG \ + (CSR_IPSURX_CSR_BASE + 0x15F0) /* ���õ�PORT0��Ӧ����COS�ı������������� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_0_REG (CSR_IPSURX_CSR_BASE + 0x1600) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_1_REG (CSR_IPSURX_CSR_BASE + 0x1604) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_2_REG (CSR_IPSURX_CSR_BASE + 0x1608) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_3_REG (CSR_IPSURX_CSR_BASE + 0x160C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_4_REG (CSR_IPSURX_CSR_BASE + 0x1610) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_5_REG (CSR_IPSURX_CSR_BASE + 0x1614) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_6_REG (CSR_IPSURX_CSR_BASE + 0x1618) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW0_7_REG (CSR_IPSURX_CSR_BASE + 0x161C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_0_REG (CSR_IPSURX_CSR_BASE + 0x1620) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_1_REG (CSR_IPSURX_CSR_BASE + 0x1624) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_2_REG (CSR_IPSURX_CSR_BASE + 0x1628) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_3_REG (CSR_IPSURX_CSR_BASE + 0x162C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_4_REG (CSR_IPSURX_CSR_BASE + 0x1630) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_5_REG (CSR_IPSURX_CSR_BASE + 0x1634) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_6_REG (CSR_IPSURX_CSR_BASE + 0x1638) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW1_7_REG (CSR_IPSURX_CSR_BASE + 0x163C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_0_REG (CSR_IPSURX_CSR_BASE + 0x1640) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_1_REG (CSR_IPSURX_CSR_BASE + 0x1644) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_2_REG (CSR_IPSURX_CSR_BASE + 0x1648) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_3_REG (CSR_IPSURX_CSR_BASE + 0x164C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_4_REG (CSR_IPSURX_CSR_BASE + 0x1650) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_5_REG (CSR_IPSURX_CSR_BASE + 0x1654) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_6_REG (CSR_IPSURX_CSR_BASE + 0x1658) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW2_7_REG (CSR_IPSURX_CSR_BASE + 0x165C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_0_REG (CSR_IPSURX_CSR_BASE + 0x1660) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_1_REG (CSR_IPSURX_CSR_BASE + 0x1664) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_2_REG (CSR_IPSURX_CSR_BASE + 0x1668) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_3_REG (CSR_IPSURX_CSR_BASE + 0x166C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_4_REG (CSR_IPSURX_CSR_BASE + 0x1670) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_5_REG (CSR_IPSURX_CSR_BASE + 0x1674) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_6_REG (CSR_IPSURX_CSR_BASE + 0x1678) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_DW3_7_REG (CSR_IPSURX_CSR_BASE + 0x167C) /* VTEP IPƥ��IP���� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_PORT_REG (CSR_IPSURX_CSR_BASE + 0x1680) /* VTEP IPƥ��˿����� */ +#define CSR_IPSURX_CSR_IPSURX_VTEP_IP_CTRL_REG (CSR_IPSURX_CSR_BASE + 0x1684) /* VTEP IPƥ����ƼĴ��� */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_0_REG (CSR_IPSURX_CSR_BASE + 0x1700) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_1_REG (CSR_IPSURX_CSR_BASE + 0x1704) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_2_REG (CSR_IPSURX_CSR_BASE + 0x1708) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_3_REG (CSR_IPSURX_CSR_BASE + 0x170C) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_4_REG (CSR_IPSURX_CSR_BASE + 0x1710) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_5_REG (CSR_IPSURX_CSR_BASE + 0x1714) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_6_REG (CSR_IPSURX_CSR_BASE + 0x1718) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_7_REG (CSR_IPSURX_CSR_BASE + 0x171C) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_8_REG (CSR_IPSURX_CSR_BASE + 0x1720) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_9_REG (CSR_IPSURX_CSR_BASE + 0x1724) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_10_REG (CSR_IPSURX_CSR_BASE + 0x1728) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_11_REG (CSR_IPSURX_CSR_BASE + 0x172C) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_12_REG (CSR_IPSURX_CSR_BASE + 0x1730) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_13_REG (CSR_IPSURX_CSR_BASE + 0x1734) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_14_REG (CSR_IPSURX_CSR_BASE + 0x1738) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_EXT_15_REG (CSR_IPSURX_CSR_BASE + 0x173C) /* �������PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_0_REG \ + (CSR_IPSURX_CSR_BASE + 0x1740) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_1_REG \ + (CSR_IPSURX_CSR_BASE + 0x1744) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_2_REG \ + (CSR_IPSURX_CSR_BASE + 0x1748) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_3_REG \ + (CSR_IPSURX_CSR_BASE + 0x174C) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_4_REG \ + (CSR_IPSURX_CSR_BASE + 0x1750) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_5_REG \ + (CSR_IPSURX_CSR_BASE + 0x1754) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_6_REG \ + (CSR_IPSURX_CSR_BASE + 0x1758) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_7_REG \ + (CSR_IPSURX_CSR_BASE + 0x175C) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_8_REG \ + (CSR_IPSURX_CSR_BASE + 0x1760) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_9_REG \ + (CSR_IPSURX_CSR_BASE + 0x1764) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_10_REG \ + (CSR_IPSURX_CSR_BASE + 0x1768) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_11_REG \ + (CSR_IPSURX_CSR_BASE + 0x176C) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_12_REG \ + (CSR_IPSURX_CSR_BASE + 0x1770) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_13_REG \ + (CSR_IPSURX_CSR_BASE + 0x1774) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_14_REG \ + (CSR_IPSURX_CSR_BASE + 0x1778) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_OFS_IDX_15_REG \ + (CSR_IPSURX_CSR_BASE + 0x177C) /* �������PATTERN ID��Ӧ��OFFSET INDEX */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_INT_0_REG (CSR_IPSURX_CSR_BASE + 0x1780) /* �����ڲ�PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_INT_1_REG (CSR_IPSURX_CSR_BASE + 0x1784) /* �����ڲ�PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_INT_2_REG (CSR_IPSURX_CSR_BASE + 0x1788) /* �����ڲ�PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_PATN_ID_INT_3_REG (CSR_IPSURX_CSR_BASE + 0x178C) /* �����ڲ�PATTERN ID */ +#define CSR_IPSURX_CSR_IPSURX_ERR_PATN_ID_REG (CSR_IPSURX_CSR_BASE + 0x1790) /* ���Ľ�������ʱ�����PATTERN ID */ + + +#endif // IPSURX_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_typedef.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_typedef.h new file mode 100644 index 000000000..e4b24c217 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsurx_typedef.h @@ -0,0 +1,30688 @@ +/* ** + * @file hi1823_csr_ipsurx_typedef.h + * @brief struct of ipsurx module defination + * + * Copyright (c) 2011 + * Huawei Tech.Co.,Ltd + * + * @author Huawei + * @date 2016-08-17 + * @version + * @nManager version:2015-06-12 + * + * + */ + +#ifndef HI1822_CSR_IPSURX_TYPEDEF_H +#define HI1822_CSR_IPSURX_TYPEDEF_H + +#ifdef __cplusplus +#if __cplusplus +extern "C" { +#endif +#endif /* * __cplusplus */ + +/* ** + * Union name : IPSURX_FPGA_VER + * @brief + * Description: + */ +typedef union tagUnIpsurxFpgaVer { + struct tagStIpsurxFpgaVer { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxFpgaVer : 32; /* * [31:0]版本寄存器，或保留用于ECO。 */ +#else + unsigned int ipsurxFpgaVer : 32; /* * [31:0]版本寄存器，或保留用于ECO。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FPGA_VER_U; + +/* ** + * Union name : IPSURX_EMU_VER + * @brief + * Description: + */ +typedef union tagUnIpsurxEmuVer { + struct tagStIpsurxEmuVer { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxEmuVer : 32; /* * [31:0]版本寄存器，或保留用于ECO。 */ +#else + unsigned int ipsurxEmuVer : 32; /* * [31:0]版本寄存器，或保留用于ECO。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_EMU_VER_U; + +/* ** + * Union name : IPSURX_INITCTAB_START + * @brief 配置表初始化使能寄存器 + * Description: + */ +typedef union tagUnIpsurxInitctabStart { + struct tagStIpsurxInitctabStart { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 30; /* * [31:2]保留。 */ + unsigned int + ipsurxTptInitStart : 1; /* * [1:1]TPT(TCP PORT + TABLE)初始化指示。软件初始化时，先写1，然后写0，产生一个脉冲，表示启动软件初始化。 + */ + unsigned int ipsurxTcamInitStart : 1; /* * + [0:0]TCAM配置表初始化指示。软件初始化时，先写1，然后写0，产生一个脉冲，表示启动软件初始化。 + */ +#else + unsigned int ipsurxTcamInitStart : 1; /* * + [0:0]TCAM配置表初始化指示。软件初始化时，先写1，然后写0，产生一个脉冲，表示启动软件初始化。 + */ + unsigned int + ipsurxTptInitStart : 1; /* * [1:1]TPT(TCP PORT + TABLE)初始化指示。软件初始化时，先写1，然后写0，产生一个脉冲，表示启动软件初始化。 + */ + unsigned int reserved : 30; /* * [31:2]保留。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INITCTAB_START_U; + +/* ** + * Union name : IPSURX_INITCTAB_DONE + * @brief 配置表初始化状态寄存器 + * Description: + */ +typedef union tagUnIpsurxInitctabDone { + struct tagStIpsurxInitctabDone { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 30; /* * [31:2]保留。 */ + unsigned int ipsurxTptInitDone : 1; /* * [1:1]TCP Port + Table初始化完成状态指示。1'b0：初始化未完成；1'b1：初始化完成。 */ + unsigned int ipsurxTcamInitDone : 1; /* * [0:0]TCAM初始化完成状态指示。1'b0：初始化未完成；1'b1：初始化完成。 */ +#else + unsigned int ipsurxTcamInitDone : 1; /* * [0:0]TCAM初始化完成状态指示。1'b0：初始化未完成；1'b1：初始化完成。 */ + unsigned int ipsurxTptInitDone : 1; /* * [1:1]TCP Port + Table初始化完成状态指示。1'b0：初始化未完成；1'b1：初始化完成。 */ + unsigned int reserved : 30; /* * [31:2]保留。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INITCTAB_DONE_U; + +/* ** + * Union name : IPSURX_ERR_INT_VECTOR + * @brief Interrupt Vector Register + * Description: + */ +typedef union tagUnIpsurxErrIntVector { + struct tagStIpsurxErrIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]Reserved. */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported through this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + and MSI-X table index. The detail of the 24-bit register is defined by CPI in + Hi1822V100 FS. */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + and MSI-X table index. The detail of the 24-bit register is defined by CPI in + Hi1822V100 FS. */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported through this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]Reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ERR_INT_VECTOR_U; + +/* ** + * Union name : IPSURX_ERR_INT + * @brief Interrupt Data Register + * Description: + */ +typedef union tagUnIpsurxErrInt { + struct tagStIpsurxErrInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_ERR_INT_MASK. + */ + unsigned int reserved : 3; /* * [15:13]Reserved */ + unsigned int intData : 13; /* * [12:0]These 13 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ +#else + unsigned int intData : 13; /* * [12:0]These 13 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ + unsigned int reserved : 3; /* * [15:13]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_ERR_INT_MASK. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ERR_INT_U; + +/* ** + * Union name : IPSURX_ERR_INT_MASK + * @brief Interrupt Mask Register + * Description: + */ +typedef union tagUnIpsurxErrIntMask { + struct tagStIpsurxErrIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ + unsigned int reserved : 3; /* * [15:13]Reserved */ + unsigned int + errMask : 13; /* * + [12:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[12:6]和bit[1]对应IPSURX数据路径上的FIFO溢出事件或者RAM的多比特不可纠错误。作为致命中断，建议芯片初始化完成后打开该比特。其余比特对应非致命中断，用户可以根据自 + 己需要处理。 */ +#else + unsigned int + errMask : 13; /* * + [12:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[12:6]和bit[1]对应IPSURX数据路径上的FIFO溢出事件或者RAM的多比特不可纠错误。作为致命中断，建议芯片初始化完成后打开该比特。其余比特对应非致命中断，用户可以根据自 + 己需要处理。 */ + unsigned int reserved : 3; /* * [15:13]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ERR_INT_MASK_U; + +/* ** + * Union name : IPSURX_CH_INVLD_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxChInvldErr { + struct tagStIpsurxChInvldErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 13; /* * [31:19]reserved. */ + unsigned int sticky : 17; /* * [18:2]Bit vector to indicate received data from disabled channel.Bit + * i(i=0~16)为高表示通道i未使能但收到数据。 + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 17; /* * [18:2]Bit vector to indicate received data from disabled channel.Bit + * i(i=0~16)为高表示通道i未使能但收到数据。 + */ + unsigned int reserved : 13; /* * [31:19]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH_INVLD_ERR_U; + +/* ** + * Union name : IPSURX_PPC_DRAM_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxPpcDramUncrtErr { + struct tagStIpsurxPpcDramUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6]reserved. */ + unsigned int sticky : 4; /* * [5:2]Data RAM address in IPSURX PPC module. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 4; /* * [5:2]Data RAM address in IPSURX PPC module. */ + unsigned int reserved : 26; /* * [31:6]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PPC_DRAM_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_TCAM_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxTcamUncrtErr { + struct tagStIpsurxTcamUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12]reserved. */ + unsigned int sticky : 10; /* * [11:2]TCAM ENTRY address when uncorrectable error + * occurs.Sticky[9:1]表示TCAM地址。Sticky[0]=0表示Y ENTRY；为1表示X ENTRY。 + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 10; /* * [11:2]TCAM ENTRY address when uncorrectable error + * occurs.Sticky[9:1]表示TCAM地址。Sticky[0]=0表示Y ENTRY；为1表示X ENTRY。 + */ + unsigned int reserved : 20; /* * [31:12]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_TCAM_ART_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxTcamArtUncrtErr { + struct tagStIpsurxTcamArtUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11]reserved. */ + unsigned int sticky : 9; /* * [10:2]TCAM ART ENTRY address when uncorrectable error occurs. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 9; /* * [10:2]TCAM ART ENTRY address when uncorrectable error occurs. */ + unsigned int reserved : 21; /* * [31:11]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_ART_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_SFT_TCAM_LOOK_RSLT + * @brief + * Description: + */ +typedef union tagUnIpsurxSftTcamLookRslt { + struct tagStIpsurxSftTcamLookRslt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int sticky : 30; /* * [31:2]When ipsurx_tcam_cfg_search_ctrl = 1'b0, Sticky[29:0] return hitted TCAM + entry index.sticky[29:10] Reserved.sticky[9:1] TCAM key address.sticky[0] VALID, high a + ctive.when ipsurx_tcam_cfg_search_ctrl = 1'b1, Sticky[29:0] return hitted ART + results.sticky[29:21] Packet Type.sticky[20:18] Reserved.sticky[17:12] ERR Type. s + ticky[11:8] Priority.sticky[7:4] PUSH_LEN.sticky[3:1] Forwarding Action.sticky[0] VALID, + high active. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 30; /* * [31:2]When ipsurx_tcam_cfg_search_ctrl = 1'b0, Sticky[29:0] return hitted TCAM + entry index.sticky[29:10] Reserved.sticky[9:1] TCAM key address.sticky[0] VALID, high a + ctive.when ipsurx_tcam_cfg_search_ctrl = 1'b1, Sticky[29:0] return hitted ART + results.sticky[29:21] Packet Type.sticky[20:18] Reserved.sticky[17:12] ERR Type. s + ticky[11:8] Priority.sticky[7:4] PUSH_LEN.sticky[3:1] Forwarding Action.sticky[0] VALID, + high active. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SFT_TCAM_LOOK_RSLT_U; + +/* ** + * Union name : IPSURX_TPT_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxTptUncrtErr { + struct tagStIpsurxTptUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int sticky : 11; /* * [12:2]TCP port table entry address when uncorrectable error occurs. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 11; /* * [12:2]TCP port table entry address when uncorrectable error occurs. */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TPT_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_LCVPP_CONTEXT_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxLcvppContextUncrtErr { + struct tagStIpsurxLcvppContextUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 27; /* * [31:5]reserved. */ + unsigned int sticky : 3; /* * [4:2]Context RAM address when uncorrectable error occurs in IPSURX LCVPP module. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 3; /* * [4:2]Context RAM address when uncorrectable error occurs in IPSURX LCVPP module. + */ + unsigned int reserved : 27; /* * [31:5]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCVPP_CONTEXT_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_LCV_FIFO_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxLcvFifoUncrtErr { + struct tagStIpsurxLcvFifoUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9]reserved. */ + unsigned int sticky : 7; /* * [8:2]FIFO address when uncorrectable error occurs in LCVPP module. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 7; /* * [8:2]FIFO address when uncorrectable error occurs in LCVPP module. */ + unsigned int reserved : 23; /* * [31:9]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCV_FIFO_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_RENQ_IF_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxRenqIfUncrtErr { + struct tagStIpsurxRenqIfUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved. */ + unsigned int sticky : 5; /* * [6:2]Input FIFO RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 5; /* * [6:2]Input FIFO RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int reserved : 25; /* * [31:7]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_IF_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT0_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxRenqContext0UncrtErr { + struct tagStIpsurxRenqContext0UncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 27; /* * [31:5]reserved. */ + unsigned int sticky : 3; /* * [4:2]Context0 RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 3; /* * [4:2]Context0 RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int reserved : 27; /* * [31:5]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT0_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT1_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxRenqContext1UncrtErr { + struct tagStIpsurxRenqContext1UncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 27; /* * [31:5]reserved. */ + unsigned int sticky : 3; /* * [4:2]Context1 RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 3; /* * [4:2]Context1 RAM address when uncorrectable error occurs in IPSURX RENQ module. + */ + unsigned int reserved : 27; /* * [31:5]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT1_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_RENQ_OF_UNCRT_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxRenqOfUncrtErr { + struct tagStIpsurxRenqOfUncrtErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved. */ + unsigned int sticky : 5; /* * [6:2]Output FIFO RAM address when uncorrectable error occurs in IPSURX RENQ + * module. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 5; /* * [6:2]Output FIFO RAM address when uncorrectable error occurs in IPSURX RENQ + * module. + */ + unsigned int reserved : 25; /* * [31:7]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_OF_UNCRT_ERR_U; + +/* ** + * Union name : IPSURX_FIFO_OVFL + * @brief + * Description: + */ +typedef union tagUnIpsurxFifoOvfl { + struct tagStIpsurxFifoOvfl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int sticky : 2; /* * [3:2]溢出FIFO编号。2'b00: LCV FIFO overflow;2'b01: RENQ input FIFO overflow;2'b10: + * RENQ output FIFO overflow;2'b11: Reserved. + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 2; /* * [3:2]溢出FIFO编号。2'b00: LCV FIFO overflow;2'b01: RENQ input FIFO overflow;2'b10: + * RENQ output FIFO overflow;2'b11: Reserved. + */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIFO_OVFL_U; + +/* ** + * Union name : IPSURX_MERR_INT_VECTOR + * @brief + * Description: + */ +typedef union tagUnIpsurxMerrIntVector { + struct tagStIpsurxMerrIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]Reserved. */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported through this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + and MSI-X table index. The detail of the 24-bit register is defined by CPI in + Hi1822V100 FS. */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + and MSI-X table index. The detail of the 24-bit register is defined by CPI in + Hi1822V100 FS. */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported through this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]Reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MERR_INT_VECTOR_U; + +/* ** + * Union name : IPSURX_MERR_INT + * @brief + * Description: + */ +typedef union tagUnIpsurxMerrInt { + struct tagStIpsurxMerrInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_MERR_INT_MASK register. + */ + unsigned int reserved : 11; /* * [15:5]Reserved */ + unsigned int intData : 5; /* * [4:0]These 5 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ +#else + unsigned int intData : 5; /* * [4:0]These 5 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ + unsigned int reserved : 11; /* * [15:5]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_MERR_INT_MASK register. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MERR_INT_U; + +/* ** + * Union name : IPSURX_MERR_INT_MASK + * @brief + * Description: + */ +typedef union tagUnIpsurxMerrIntMask { + struct tagStIpsurxMerrIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ + unsigned int reserved : 11; /* * [15:5]Reserved */ + unsigned int + errMask : 5; /* * + [4:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[4]对应CSR路径上，IPSUTX时钟域到IPSURX时钟域的异步FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。Bit[3:0]对应非致命中断，用户可以根据自己需要 + 处理。 */ +#else + unsigned int + errMask : 5; /* * + [4:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[4]对应CSR路径上，IPSUTX时钟域到IPSURX时钟域的异步FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。Bit[3:0]对应非致命中断，用户可以根据自己需要 + 处理。 */ + unsigned int reserved : 11; /* * [15:5]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MERR_INT_MASK_U; + +/* ** + * Union name : IPSURX_SOP_EOP_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxSopEopErr { + struct tagStIpsurxSopEopErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6]reserved. */ + unsigned int sopSopMerr : 1; /* * [5:5]1'b1: 发生多次SOP_SOP错误。1'b0：未发生多次SOP_SOP错误。 */ + unsigned int sopSopErr : 1; /* * [4:4]1'b1: 发生SOP_SOP错误。1'b0：未发生SOP_SOP错误。 */ + unsigned int abortBfIpsurxMerr : 1; /* * [3:3]1'b1: 发生多次ABORT_BF_IPSURX + 错误。1'b0：未发生多次ABORT_BF_IPSURX 错误。 */ + unsigned int abortBfIpsurxErr : 1; /* * [2:2]1'b1: 发生ABORT_BF_IPSURX 错误。1'b0：未发生ABORT_BF_IPSURX 错误。 + */ + unsigned int sopWithMerr : 1; /* * [1:1]1'b1: 发生多次SOP_WITH_ERR 错误。1'b0：未发生多次SOP_WITH_ERR 错误。 */ + unsigned int sopWithErr : 1; /* * [0:0]1'b1: 发生SOP_WITH_ERR 错误。1'b0：未发生SOP_WITH_ERR 错误。 */ +#else + unsigned int sopWithErr : 1; /* * [0:0]1'b1: 发生SOP_WITH_ERR 错误。1'b0：未发生SOP_WITH_ERR 错误。 */ + unsigned int sopWithMerr : 1; /* * [1:1]1'b1: 发生多次SOP_WITH_ERR 错误。1'b0：未发生多次SOP_WITH_ERR 错误。 */ + unsigned int abortBfIpsurxErr : 1; /* * [2:2]1'b1: 发生ABORT_BF_IPSURX 错误。1'b0：未发生ABORT_BF_IPSURX 错误。 + */ + unsigned int abortBfIpsurxMerr : 1; /* * [3:3]1'b1: 发生多次ABORT_BF_IPSURX + 错误。1'b0：未发生多次ABORT_BF_IPSURX 错误。 */ + unsigned int sopSopErr : 1; /* * [4:4]1'b1: 发生SOP_SOP错误。1'b0：未发生SOP_SOP错误。 */ + unsigned int sopSopMerr : 1; /* * [5:5]1'b1: 发生多次SOP_SOP错误。1'b0：未发生多次SOP_SOP错误。 */ + unsigned int reserved : 26; /* * [31:6]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SOP_EOP_ERR_U; + +/* ** + * Union name : IPSURX_SOP_EOP_ERR_MASK + * @brief + * Description: + */ +typedef union tagUnIpsurxSopEopErrMask { + struct tagStIpsurxSopEopErrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int sopSopErrMask : 1; /* * [2:2]1'b1：允许上报SOP_SOP错误中断；1'b0：不允许上报SOP_SOP错误中断。 */ + unsigned int abortBfIpsurxMask : 1; /* * [1:1]1'b1：允许上报ABORT_BF_IPSURX + 中断；1'b0：不允许上报ABORT_BF_IPSURX 中断。 */ + unsigned int sopWithErrMask : 1; /* * [0:0]1'b1：允许上报SOP_WITH_ERR 中断；1'b0：不允许上报SOP_WITH_ERR 中断。 + */ +#else + unsigned int sopWithErrMask : 1; /* * [0:0]1'b1：允许上报SOP_WITH_ERR 中断；1'b0：不允许上报SOP_WITH_ERR 中断。 + */ + unsigned int abortBfIpsurxMask : 1; /* * [1:1]1'b1：允许上报ABORT_BF_IPSURX + 中断；1'b0：不允许上报ABORT_BF_IPSURX 中断。 */ + unsigned int sopSopErrMask : 1; /* * [2:2]1'b1：允许上报SOP_SOP错误中断；1'b0：不允许上报SOP_SOP错误中断。 */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SOP_EOP_ERR_MASK_U; + +/* ** + * Union name : IPSURX_IP_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxIpErr { + struct tagStIpsurxIpErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipv4VerMerr : 1; /* * [31:31]1'b1: 发生多次IPv4 Version错误。1'b0：未发生多次IPv4 Version错误。 */ + unsigned int ipv4VerErr : 1; /* * [30:30]1'b1: 发生IPv4 Version错误。1'b0：未发生IPv4 Version错误。 */ + unsigned int ipv4IhlMerr : 1; /* * [29:29]1'b1: 发生多次IPv4头部长度错误。1'b0：未发生多次IPv4头部长度错误。 */ + unsigned int ipv4IhlErr : 1; /* * [28:28]1'b1: 发生IPv4头部长度错误。1'b0：未发生IPv4头部长度错误。 */ + unsigned int ipv4SipMerr : 1; /* * [27:27]1'b1: 发生多次IPv4源IP地址错误。1'b0：未发生多次IPv4源IP地址错误。 */ + unsigned int ipv4SipErr : 1; /* * [26:26]1'b1: 发生IPv4源IP地址错误。1'b0：未发生IPv4源IP地址错误。 */ + unsigned int ipv4DipMerr : 1; /* * [25:25]1'b1: 发生多次IPv4目的IP地址错误。1'b0：未发生多次IPv4目的IP地址错误。 + */ + unsigned int ipv4DipErr : 1; /* * [24:24]1'b1: 发生IPv4目的IP地址错误。1'b0：未发生IPv4目的IP地址错误。 */ + unsigned int ipv4CsMerr : 1; /* * [23:23]1'b1: + * 发生多次IPv4头部CS校验错误。1'b0：未发生多次IPv4头部CS校校验错误。 + */ + unsigned int ipv4CsErr : 1; /* * [22:22]1'b1: 发生IPv4头部CS校验错误。1'b0：未发生IPv4头部CS校验错误。 */ + unsigned int ipv6VerMerr : 1; /* * [21:21]1'b1: 发生多次IPv6 Version错误。1'b0：未发生多次IPv6 Version错误。 */ + unsigned int ipv6VerErr : 1; /* * [20:20]1'b1: 发生IPv6 Version 错误。1'b0：未发生IPv6 Version 错误。 */ + unsigned int ipv6SipMerr : 1; /* * [19:19]1'b1: 发生多次IPv6源IP地址错误。1'b0：未发生多次IPv6源IP地址错误。 */ + unsigned int ipv6SipErr : 1; /* * [18:18]1'b1: 发生IPv6源IP地址错误。1'b0：未发生IPv6源IP地址错误。 */ + unsigned int ipv6DipMerr : 1; /* * [17:17]1'b1: 发生多次IPv6目的IP地址错误。1'b0：未发生多次IPv6目的IP地址错误。 + */ + unsigned int ipv6DipErr : 1; /* * [16:16]1'b1: 发生IPv6目的IP地址错误。1'b0：未发生IPv6目的IP地址错误。 */ + unsigned int tcpLandMerr : 1; /* * [15:15]1'b1: 发生多次TCP LAND错误。1'b0：未发生多次TCP LAND错误。 */ + unsigned int tcpLandErr : 1; /* * [14:14]1'b1: 发生TCP LAND错误。1'b0：未发生TCP LAND错误。 */ + unsigned int tcpCsMerr : 1; /* * [13:13]1'b1: 发生多次TCP CS校验错误。1'b0：未发生多次TCP CS校验错误。 */ + unsigned int tcpCsErr : 1; /* * [12:12]1'b1: 发生TCP CS校验错误。1'b0：未发生TCP CS校验错误。 */ + unsigned int ipv6UdpCsZeroMerr : 1; /* * [11:11]1'b1: 发生多次IPv6 UDP CS为0校验错误。1'b0：未发生多次IPv6 UDP + CS为0校验错误。 */ + unsigned int ipv6UdpCsZeroErr : 1; /* * [10:10]1'b1: 发生IPv6 UDP CS为0校验错误。1'b0：未发生IPv6 UDP + CS为0校验错误。 */ + unsigned int udpCsMerr : 1; /* * [9:9]1'b1: 发生多次UDP CS校验错误。1'b0：未发生多次UDP CS校验错误。 */ + unsigned int udpCsErr : 1; /* * [8:8]1'b1: 发生UDP CS校验错误。1'b0：未发生UDP CS校验错误。 */ + unsigned int igmpCsMerr : 1; /* * [7:7]1'b1: 发生多次IGMP CS校验错误。1'b0：未发生多次IGMP CS校验错误。 */ + unsigned int igmpCsErr : 1; /* * [6:6]1'b1: 发生IGMP CS校验错误。1'b0：未发生IGMP CS校验错误。 */ + unsigned int icmpv4CsMerr : 1; /* * [5:5]1'b1: 发生多次ICMPv4 CS校验错误。1'b0：未发生多次ICMPv4 CS校验错误。 */ + unsigned int icmpv4CsErr : 1; /* * [4:4]1'b1: 发生ICMPv4 CS校验错误。1'b0：未发生ICMPv4 CS校验错误。 */ + unsigned int icmpv6CsMerr : 1; /* * [3:3]1'b1: 发生多次ICMPv6 CS校验错误。1'b0：未发生多次ICMPv6 CS校验错误。 */ + unsigned int icmpv6CsErr : 1; /* * [2:2]1'b1: 发生ICMPv6 CS校验错误。1'b0：未发生ICMPv6 CS校验错误。 */ + unsigned int sctpCsMerr : 1; /* * [1:1]1'b1: 发生多次SCTP CS校验错误。1'b0：未发生多次SCTP CS校验错误。 */ + unsigned int sctpCsErr : 1; /* * [0:0]1'b1: 发生SCTP CS校验错误。1'b0：未发生SCTP CS校验错误。 */ +#else + unsigned int sctpCsErr : 1; /* * [0:0]1'b1: 发生SCTP CS校验错误。1'b0：未发生SCTP CS校验错误。 */ + unsigned int sctpCsMerr : 1; /* * [1:1]1'b1: 发生多次SCTP CS校验错误。1'b0：未发生多次SCTP CS校验错误。 */ + unsigned int icmpv6CsErr : 1; /* * [2:2]1'b1: 发生ICMPv6 CS校验错误。1'b0：未发生ICMPv6 CS校验错误。 */ + unsigned int icmpv6CsMerr : 1; /* * [3:3]1'b1: 发生多次ICMPv6 CS校验错误。1'b0：未发生多次ICMPv6 CS校验错误。 */ + unsigned int icmpv4CsErr : 1; /* * [4:4]1'b1: 发生ICMPv4 CS校验错误。1'b0：未发生ICMPv4 CS校验错误。 */ + unsigned int icmpv4CsMerr : 1; /* * [5:5]1'b1: 发生多次ICMPv4 CS校验错误。1'b0：未发生多次ICMPv4 CS校验错误。 */ + unsigned int igmpCsErr : 1; /* * [6:6]1'b1: 发生IGMP CS校验错误。1'b0：未发生IGMP CS校验错误。 */ + unsigned int igmpCsMerr : 1; /* * [7:7]1'b1: 发生多次IGMP CS校验错误。1'b0：未发生多次IGMP CS校验错误。 */ + unsigned int udpCsErr : 1; /* * [8:8]1'b1: 发生UDP CS校验错误。1'b0：未发生UDP CS校验错误。 */ + unsigned int udpCsMerr : 1; /* * [9:9]1'b1: 发生多次UDP CS校验错误。1'b0：未发生多次UDP CS校验错误。 */ + unsigned int ipv6UdpCsZeroErr : 1; /* * [10:10]1'b1: 发生IPv6 UDP CS为0校验错误。1'b0：未发生IPv6 UDP + CS为0校验错误。 */ + unsigned int ipv6UdpCsZeroMerr : 1; /* * [11:11]1'b1: 发生多次IPv6 UDP CS为0校验错误。1'b0：未发生多次IPv6 UDP + CS为0校验错误。 */ + unsigned int tcpCsErr : 1; /* * [12:12]1'b1: 发生TCP CS校验错误。1'b0：未发生TCP CS校验错误。 */ + unsigned int tcpCsMerr : 1; /* * [13:13]1'b1: 发生多次TCP CS校验错误。1'b0：未发生多次TCP CS校验错误。 */ + unsigned int tcpLandErr : 1; /* * [14:14]1'b1: 发生TCP LAND错误。1'b0：未发生TCP LAND错误。 */ + unsigned int tcpLandMerr : 1; /* * [15:15]1'b1: 发生多次TCP LAND错误。1'b0：未发生多次TCP LAND错误。 */ + unsigned int ipv6DipErr : 1; /* * [16:16]1'b1: 发生IPv6目的IP地址错误。1'b0：未发生IPv6目的IP地址错误。 */ + unsigned int ipv6DipMerr : 1; /* * [17:17]1'b1: 发生多次IPv6目的IP地址错误。1'b0：未发生多次IPv6目的IP地址错误。 + */ + unsigned int ipv6SipErr : 1; /* * [18:18]1'b1: 发生IPv6源IP地址错误。1'b0：未发生IPv6源IP地址错误。 */ + unsigned int ipv6SipMerr : 1; /* * [19:19]1'b1: 发生多次IPv6源IP地址错误。1'b0：未发生多次IPv6源IP地址错误。 */ + unsigned int ipv6VerErr : 1; /* * [20:20]1'b1: 发生IPv6 Version 错误。1'b0：未发生IPv6 Version 错误。 */ + unsigned int ipv6VerMerr : 1; /* * [21:21]1'b1: 发生多次IPv6 Version错误。1'b0：未发生多次IPv6 Version错误。 */ + unsigned int ipv4CsErr : 1; /* * [22:22]1'b1: 发生IPv4头部CS校验错误。1'b0：未发生IPv4头部CS校验错误。 */ + unsigned int ipv4CsMerr : 1; /* * [23:23]1'b1: + * 发生多次IPv4头部CS校验错误。1'b0：未发生多次IPv4头部CS校校验错误。 + */ + unsigned int ipv4DipErr : 1; /* * [24:24]1'b1: 发生IPv4目的IP地址错误。1'b0：未发生IPv4目的IP地址错误。 */ + unsigned int ipv4DipMerr : 1; /* * [25:25]1'b1: 发生多次IPv4目的IP地址错误。1'b0：未发生多次IPv4目的IP地址错误。 + */ + unsigned int ipv4SipErr : 1; /* * [26:26]1'b1: 发生IPv4源IP地址错误。1'b0：未发生IPv4源IP地址错误。 */ + unsigned int ipv4SipMerr : 1; /* * [27:27]1'b1: 发生多次IPv4源IP地址错误。1'b0：未发生多次IPv4源IP地址错误。 */ + unsigned int ipv4IhlErr : 1; /* * [28:28]1'b1: 发生IPv4头部长度错误。1'b0：未发生IPv4头部长度错误。 */ + unsigned int ipv4IhlMerr : 1; /* * [29:29]1'b1: 发生多次IPv4头部长度错误。1'b0：未发生多次IPv4头部长度错误。 */ + unsigned int ipv4VerErr : 1; /* * [30:30]1'b1: 发生IPv4 Version错误。1'b0：未发生IPv4 Version错误。 */ + unsigned int ipv4VerMerr : 1; /* * [31:31]1'b1: 发生多次IPv4 Version错误。1'b0：未发生多次IPv4 Version错误。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IP_ERR_U; + +/* ** + * Union name : IPSURX_IP_ERR_MASK + * @brief + * Description: + */ +typedef union tagUnIpsurxIpErrMask { + struct tagStIpsurxIpErrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int ipv4VerErrMask : 1; /* * [15:15]1'b1：允许上报IPv4 Version错误中断；1'b0：不允许上报IPv4 + Version错误中断。 */ + unsigned int ipv4IhlErrMask : 1; /* * [14:14]1'b1：允许上报IPv4 头部长度错误中断；1'b0：不允许上报IPv4 + 头部长度错误中断。 */ + unsigned int ipv4SipErrMask : 1; /* * [13:13]1'b1：允许上报IPv4 源IP错误中断；1'b0：不允许上报IPv4 + * 源IP错误中断。 + */ + unsigned int ipv4DipErrMask : 1; /* * [12:12]1'b1：允许上报IPv4 目的IP错误中断；1'b0：不允许上报IPv4 + 目的IP错误中断。 */ + unsigned int ipv4CsErrMask : 1; /* * [11:11]1'b1：允许上报IPv4 头部CS校验错误中断；1'b0：不允许上报IPv4 + 头部CS校验错误中断。 */ + unsigned int ipv6VerErrMask : 1; /* * [10:10]1'b1：允许上报IPv6 Version错误中断；1'b0：不允许上报IPv6 + Version错误中断。 */ + unsigned int ipv6SipErrMask : 1; /* * [9:9]1'b1：允许上报IPv6 源IP错误中断；1'b0：不允许上报IPv6 源IP错误中断。 + */ + unsigned int ipv6DipErrMask : 1; /* * [8:8]1'b1：允许上报IPv6 目的IP错误中断；1'b0：不允许上报IPv6 + 目的IP错误中断。 */ + unsigned int tcpLandErrMask : 1; /* * [7:7]1'b1：允许上报TCP LADN错误中断；1'b0：不允许上报TCP LADN错误中断。 */ + unsigned int tcpCsErrMask : 1; /* * [6:6]1'b1：允许上报TCP CS校验错误中断；1'b0：不允许上报TCP CS校验错误中断。 + */ + unsigned int ipv6UdpCsZeroErrMask : 1; /* * [5:5]1'b1：允许上报IPv6 UDP CS为0校验错误中断；1'b0：不允许上报IPv6 + UDP CS为0校验错误中断。 */ + unsigned int udpCsErrMask : 1; /* * [4:4]1'b1：允许上报UDP CS校验错误中断；1'b0：不允许上报UDP CS校验错误中断。 + */ + unsigned int igmpCsErrMask : 1; /* * [3:3]1'b1：允许上报IGMP CS校验错误中断；1'b0：不允许上报IGMP + CS校验错误中断。 */ + unsigned int icmpv4CsErrMask : 1; /* * [2:2]1'b1：允许上报ICMPv4 CS校验错误中断；1'b0：不允许上报ICMPv4 + CS校验错误中断。 */ + unsigned int icmpv6CsErrMask : 1; /* * [1:1]1'b1：允许上报ICMPv6 CS校验错误中断；1'b0：不允许上报ICMPv6 + CS校验错误中断。 */ + unsigned int sctpCsErrMask : 1; /* * [0:0]1'b1：允许上报SCTP CS校验错误中断；1'b0：不允许上报SCTP + CS校验错误中断。 */ +#else + unsigned int sctpCsErrMask : 1; /* * [0:0]1'b1：允许上报SCTP CS校验错误中断；1'b0：不允许上报SCTP + CS校验错误中断。 */ + unsigned int icmpv6CsErrMask : 1; /* * [1:1]1'b1：允许上报ICMPv6 CS校验错误中断；1'b0：不允许上报ICMPv6 + CS校验错误中断。 */ + unsigned int icmpv4CsErrMask : 1; /* * [2:2]1'b1：允许上报ICMPv4 CS校验错误中断；1'b0：不允许上报ICMPv4 + CS校验错误中断。 */ + unsigned int igmpCsErrMask : 1; /* * [3:3]1'b1：允许上报IGMP CS校验错误中断；1'b0：不允许上报IGMP + CS校验错误中断。 */ + unsigned int udpCsErrMask : 1; /* * [4:4]1'b1：允许上报UDP CS校验错误中断；1'b0：不允许上报UDP CS校验错误中断。 + */ + unsigned int ipv6UdpCsZeroErrMask : 1; /* * [5:5]1'b1：允许上报IPv6 UDP CS为0校验错误中断；1'b0：不允许上报IPv6 + UDP CS为0校验错误中断。 */ + unsigned int tcpCsErrMask : 1; /* * [6:6]1'b1：允许上报TCP CS校验错误中断；1'b0：不允许上报TCP CS校验错误中断。 + */ + unsigned int tcpLandErrMask : 1; /* * [7:7]1'b1：允许上报TCP LADN错误中断；1'b0：不允许上报TCP LADN错误中断。 */ + unsigned int ipv6DipErrMask : 1; /* * [8:8]1'b1：允许上报IPv6 目的IP错误中断；1'b0：不允许上报IPv6 + 目的IP错误中断。 */ + unsigned int ipv6SipErrMask : 1; /* * [9:9]1'b1：允许上报IPv6 源IP错误中断；1'b0：不允许上报IPv6 源IP错误中断。 + */ + unsigned int ipv6VerErrMask : 1; /* * [10:10]1'b1：允许上报IPv6 Version错误中断；1'b0：不允许上报IPv6 + Version错误中断。 */ + unsigned int ipv4CsErrMask : 1; /* * [11:11]1'b1：允许上报IPv4 头部CS校验错误中断；1'b0：不允许上报IPv4 + 头部CS校验错误中断。 */ + unsigned int ipv4DipErrMask : 1; /* * [12:12]1'b1：允许上报IPv4 目的IP错误中断；1'b0：不允许上报IPv4 + 目的IP错误中断。 */ + unsigned int ipv4SipErrMask : 1; /* * [13:13]1'b1：允许上报IPv4 源IP错误中断；1'b0：不允许上报IPv4 + * 源IP错误中断。 + */ + unsigned int ipv4IhlErrMask : 1; /* * [14:14]1'b1：允许上报IPv4 头部长度错误中断；1'b0：不允许上报IPv4 + 头部长度错误中断。 */ + unsigned int ipv4VerErrMask : 1; /* * [15:15]1'b1：允许上报IPv4 Version错误中断；1'b0：不允许上报IPv4 + Version错误中断。 */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IP_ERR_MASK_U; + +/* ** + * Union name : IPSURX_ROCE_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxRoceErr { + struct tagStIpsurxRoceErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 12; /* * [31:20]reserved. */ + unsigned int rocev1DgidMerr : 1; /* * [19:19]1'b1: 发生多次RoCEv1 DGID错误。1'b0：未发生多次RoCEv1 DGID错误。 */ + unsigned int rocev1DgidErr : 1; /* * [18:18]1'b1: 发生RoCEv1 DGID错误。1'b0：未发生RoCEv1 DGID错误。 */ + unsigned int rocev1SgidMerr : 1; /* * [17:17]1'b1: 发生多次RoCEv1 SGID错误。1'b0：未发生多次RoCEv1 SGID错误。 */ + unsigned int rocev1SgidErr : 1; /* * [16:16]1'b1: 发生RoCEv1 SGID错误。1'b0：未发生RoCEv1 SGID错误。 */ + unsigned int rocev1IpverMerr : 1; /* * [15:15]1'b1: 发生多次RoCEv1 IPVer错误。1'b0：未发生多次RoCEv1 IPVer错误。 + */ + unsigned int rocev1IpverErr : 1; /* * [14:14]1'b1: 发生RoCEv1 IPVer错误。1'b0：未发生RoCEv1 IPVer错误。 */ + unsigned int rocev1NxhdrMerr : 1; /* * [13:13]1'b1: 发生多次RoCEv1 NXHDR错误。1'b0：未发生多次RoCEv1 NXHDR错误。 + */ + unsigned int rocev1NxhdrErr : 1; /* * [12:12]1'b1: 发生RoCEv1 NXHDR错误。1'b0：未发生RoCEv1 NXHDR错误。 */ + unsigned int rocev1PlenMerr : 1; /* * [11:11]1'b1: 发生多次RoCEv1 PayLen错误。1'b0：未发生多次RoCEv1 + * PayLen错误。 + */ + unsigned int rocev1PlenErr : 1; /* * [10:10]1'b1: 发生RoCEv1 PayLen错误。1'b0：未发生RoCEv1 PayLen错误。 */ + unsigned int rocev2Ipv4FragMerr : 1; /* * [9:9]1'b1: 发生多次RoCEv2 IPv4分片错误。1'b0：未发生多次RoCEv2 + IPv4分片错误。 */ + unsigned int rocev2Ipv4FragErr : 1; /* * [8:8]1'b1: 发生RoCEv2 IPv4分片错误。1'b0：未发生RoCEv2 IPv4分片错误。 + */ + unsigned int rocev2Ipv4UdpCsMerr : 1; /* * [7:7]1'b1: 发生多次RoCEv2 IPv4 UDP CS校验错误。1'b0：未发生多次RoCEv2 + IPv4 UDP CS校验错误。 */ + unsigned int rocev2Ipv4UdpCsErr : 1; /* * [6:6]1'b1: 发生RoCEv2 IPv4 UDP CS校验错误。1'b0：未发生RoCEv2 IPv4 UDP + CS校验错误。 */ + unsigned int rocev2Ipv6UdpCsMerr : 1; /* * [5:5]1'b1: 发生多次RoCEv2 IPv6 UDP CS校验错误。1'b0：未发生多次RoCEv2 + IPv6 UDP CS校验错误。 */ + unsigned int rocev2Ipv6UdpCsErr : 1; /* * [4:4]1'b1: 发生RoCEv2 IPv6 UDP CS校验错误。1'b0：未发生RoCEv2 IPv6 UDP + CS校验错误。 */ + unsigned int roceDqpMerr : 1; /* * [3:3]1'b1: 发生多次RoCE DQP错误。1'b0：未发生多次RoCE DQP错误。 */ + unsigned int roceDqpErr : 1; /* * [2:2]1'b1: 发生RoCE DQP错误。1'b0：未发生RoCE DQP错误。 */ + unsigned int ibIcrcMerr : 1; /* * [1:1]1'b1: 发生多次RoCE ICRC校验错误。1'b0：未发生多次RoCE ICRC校验错误。 */ + unsigned int ibIcrcErr : 1; /* * [0:0]1'b1: 发生RoCE ICRC校验错误。1'b0：未发生RoCE ICRC校验错误。 */ +#else + unsigned int ibIcrcErr : 1; /* * [0:0]1'b1: 发生RoCE ICRC校验错误。1'b0：未发生RoCE ICRC校验错误。 */ + unsigned int ibIcrcMerr : 1; /* * [1:1]1'b1: 发生多次RoCE ICRC校验错误。1'b0：未发生多次RoCE ICRC校验错误。 */ + unsigned int roceDqpErr : 1; /* * [2:2]1'b1: 发生RoCE DQP错误。1'b0：未发生RoCE DQP错误。 */ + unsigned int roceDqpMerr : 1; /* * [3:3]1'b1: 发生多次RoCE DQP错误。1'b0：未发生多次RoCE DQP错误。 */ + unsigned int rocev2Ipv6UdpCsErr : 1; /* * [4:4]1'b1: 发生RoCEv2 IPv6 UDP CS校验错误。1'b0：未发生RoCEv2 IPv6 UDP + CS校验错误。 */ + unsigned int rocev2Ipv6UdpCsMerr : 1; /* * [5:5]1'b1: 发生多次RoCEv2 IPv6 UDP CS校验错误。1'b0：未发生多次RoCEv2 + IPv6 UDP CS校验错误。 */ + unsigned int rocev2Ipv4UdpCsErr : 1; /* * [6:6]1'b1: 发生RoCEv2 IPv4 UDP CS校验错误。1'b0：未发生RoCEv2 IPv4 UDP + CS校验错误。 */ + unsigned int rocev2Ipv4UdpCsMerr : 1; /* * [7:7]1'b1: 发生多次RoCEv2 IPv4 UDP CS校验错误。1'b0：未发生多次RoCEv2 + IPv4 UDP CS校验错误。 */ + unsigned int rocev2Ipv4FragErr : 1; /* * [8:8]1'b1: 发生RoCEv2 IPv4分片错误。1'b0：未发生RoCEv2 IPv4分片错误。 + */ + unsigned int rocev2Ipv4FragMerr : 1; /* * [9:9]1'b1: 发生多次RoCEv2 IPv4分片错误。1'b0：未发生多次RoCEv2 + IPv4分片错误。 */ + unsigned int rocev1PlenErr : 1; /* * [10:10]1'b1: 发生RoCEv1 PayLen错误。1'b0：未发生RoCEv1 PayLen错误。 */ + unsigned int rocev1PlenMerr : 1; /* * [11:11]1'b1: 发生多次RoCEv1 PayLen错误。1'b0：未发生多次RoCEv1 + * PayLen错误。 + */ + unsigned int rocev1NxhdrErr : 1; /* * [12:12]1'b1: 发生RoCEv1 NXHDR错误。1'b0：未发生RoCEv1 NXHDR错误。 */ + unsigned int rocev1NxhdrMerr : 1; /* * [13:13]1'b1: 发生多次RoCEv1 NXHDR错误。1'b0：未发生多次RoCEv1 NXHDR错误。 + */ + unsigned int rocev1IpverErr : 1; /* * [14:14]1'b1: 发生RoCEv1 IPVer错误。1'b0：未发生RoCEv1 IPVer错误。 */ + unsigned int rocev1IpverMerr : 1; /* * [15:15]1'b1: 发生多次RoCEv1 IPVer错误。1'b0：未发生多次RoCEv1 IPVer错误。 + */ + unsigned int rocev1SgidErr : 1; /* * [16:16]1'b1: 发生RoCEv1 SGID错误。1'b0：未发生RoCEv1 SGID错误。 */ + unsigned int rocev1SgidMerr : 1; /* * [17:17]1'b1: 发生多次RoCEv1 SGID错误。1'b0：未发生多次RoCEv1 SGID错误。 */ + unsigned int rocev1DgidErr : 1; /* * [18:18]1'b1: 发生RoCEv1 DGID错误。1'b0：未发生RoCEv1 DGID错误。 */ + unsigned int rocev1DgidMerr : 1; /* * [19:19]1'b1: 发生多次RoCEv1 DGID错误。1'b0：未发生多次RoCEv1 DGID错误。 */ + unsigned int reserved : 12; /* * [31:20]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCE_ERR_U; + +/* ** + * Union name : IPSURX_ROCE_ERR_MASK + * @brief + * Description: + */ +typedef union tagUnIpsurxRoceErrMask { + struct tagStIpsurxRoceErrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10]reserved. */ + unsigned int rocev1DgidErrMask : 1; /* * [9:9]1'b1：允许上报RoCEv1 DGID错误中断；1'b0：不允许上报RoCEv1 + DGID错误中断。 */ + unsigned int rocev1SgidErrMask : 1; /* * [8:8]1'b1：允许上报RoCEv1 SGID错误中断；1'b0：不允许上报RoCEv1 + SGID错误中断。 */ + unsigned int rocev1IpverErrMask : 1; /* * [7:7]1'b1：允许上报RoCEv1 IPVer错误中断；1'b0：不允许上报RoCEv1 + IPVer错误中断。 */ + unsigned int rocev1NxhdrErrMask : 1; /* * [6:6]1'b1：允许上报RoCEv1 NXHDR错误中断；1'b0：不允许上报RoCEv1 + NXHDR错误中断。 */ + unsigned int rocev1PlenErrMask : 1; /* * [5:5]1'b1：允许上报RoCEv1 PayLen错误中断；1'b0：不允许上报RoCEv1 + PayLen错误中断。 */ + unsigned int rocev2Ipv4FragErrMask : 1; /* * [4:4]1'b1：允许上报RoCEv2 IPv4分片错误中断；1'b0：不允许上报RoCEv2 + IPv4分片错误中断。 */ + unsigned int rocev2Ipv4UdpCsErrMask : 1; /* * [3:3]1'b1：允许上报RoCEv2 IPv4 UDP + CS校验错误中断；1'b0：不允许上报RoCEv2 IPv4 UDP CS校验错误中断。 */ + unsigned int rocev2Ipv6UdpCsErrMask : 1; /* * [2:2]1'b1：允许上报RoCEv2 IPv6 UDP + CS校验错误中断；1'b0：不允许上报RoCEv2 IPv6 UDP CS校验错误中断。 */ + unsigned int roceDqpErrMask : 1; /* * [1:1]1'b1：允许上报RoCE DQP错误中断；1'b0：不允许上报RoCE DQP错误中断。 */ + unsigned int ibIcrcErrMask : 1; /* * [0:0]1'b1：允许上报RoCE ICRC校验错误中断；1'b0：不允许上报RoCE + ICRC校验错误中断。 */ +#else + unsigned int ibIcrcErrMask : 1; /* * [0:0]1'b1：允许上报RoCE ICRC校验错误中断；1'b0：不允许上报RoCE + ICRC校验错误中断。 */ + unsigned int roceDqpErrMask : 1; /* * [1:1]1'b1：允许上报RoCE DQP错误中断；1'b0：不允许上报RoCE DQP错误中断。 */ + unsigned int rocev2Ipv6UdpCsErrMask : 1; /* * [2:2]1'b1：允许上报RoCEv2 IPv6 UDP + CS校验错误中断；1'b0：不允许上报RoCEv2 IPv6 UDP CS校验错误中断。 */ + unsigned int rocev2Ipv4UdpCsErrMask : 1; /* * [3:3]1'b1：允许上报RoCEv2 IPv4 UDP + CS校验错误中断；1'b0：不允许上报RoCEv2 IPv4 UDP CS校验错误中断。 */ + unsigned int rocev2Ipv4FragErrMask : 1; /* * [4:4]1'b1：允许上报RoCEv2 IPv4分片错误中断；1'b0：不允许上报RoCEv2 + IPv4分片错误中断。 */ + unsigned int rocev1PlenErrMask : 1; /* * [5:5]1'b1：允许上报RoCEv1 PayLen错误中断；1'b0：不允许上报RoCEv1 + PayLen错误中断。 */ + unsigned int rocev1NxhdrErrMask : 1; /* * [6:6]1'b1：允许上报RoCEv1 NXHDR错误中断；1'b0：不允许上报RoCEv1 + NXHDR错误中断。 */ + unsigned int rocev1IpverErrMask : 1; /* * [7:7]1'b1：允许上报RoCEv1 IPVer错误中断；1'b0：不允许上报RoCEv1 + IPVer错误中断。 */ + unsigned int rocev1SgidErrMask : 1; /* * [8:8]1'b1：允许上报RoCEv1 SGID错误中断；1'b0：不允许上报RoCEv1 + SGID错误中断。 */ + unsigned int rocev1DgidErrMask : 1; /* * [9:9]1'b1：允许上报RoCEv1 DGID错误中断；1'b0：不允许上报RoCEv1 + DGID错误中断。 */ + unsigned int reserved : 22; /* * [31:10]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCE_ERR_MASK_U; + +/* ** + * Union name : IPSURX_OTH_ERR + * @brief + * Description: + */ +typedef union tagUnIpsurxOthErr { + struct tagStIpsurxOthErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int dropByTcamMerr : 1; /* * [21:21]1'b1: + 发生多次TCAM查找结果指示丢弃报文。1'b0：未发生多次TCAM查找结果指示丢弃报文。 + */ + unsigned int dropByTcamErr : 1; /* * [20:20]1'b1: + 发生TCAM查找结果指示丢弃报文。1'b0：未发生TCAM查找结果指示丢弃报文。 */ + unsigned int + directToUpPktMerr : 1; /* * [19:19]1'b1: + 发生多次直接转发到UP的报文校验错误。1'b0：未发生多次直接转发到UP的报文校验错误。 + */ + unsigned int directToUpPktErr : 1; /* * [18:18]1'b1: + 发生直接转发到UP的报文校验错误。1'b0：未发生直接转发到UP的报文校验错误。 + */ + unsigned int dmacZeroMerr : 1; /* * [17:17]1'b1: 发生多次目的MAC为0错误。1'b0：未发生多次目的MAC为0错误。 */ + unsigned int dmacZeroErr : 1; /* * [16:16]1'b1: 发生目的MAC为0错误。1'b0：未发生目的MAC为0错误。 */ + unsigned int smacMerr : 1; /* * [15:15]1'b1: 发生多次源MAC错误。1'b0：未发生多次源MAC错误。 */ + unsigned int smacErr : 1; /* * [14:14]1'b1: 发生源MAC错误。1'b0：未发生源MAC错误。 */ + unsigned int dmacSmacEqualMerr : 1; /* * [13:13]1'b1: + 发生多次目的MAC等于源MAC错误。1'b0：未发生多次目的MAC等于源MAC错误。 */ + unsigned int dmacSmacEqualErr : 1; /* * [12:12]1'b1: + * 发生目的MAC等于源MAC错误。1'b0：未发生目的MAC等于源MAC错误。 + */ + unsigned int arpPosiMerr : 1; /* * [11:11]1'b1: 发生多次ARP DMAC为单播错误。1'b0：未发生多次ARP DMAC为单播错误。 + */ + unsigned int arpPosiErr : 1; /* * [10:10]1'b1: 发生ARP DMAC为单播错误。1'b0：未发生ARP DMAC为单播错误。 */ + unsigned int ethLlcLenMerr : 1; /* * [9:9]1'b1: 发生多次LLC/SNAP Length校验错误。1'b0：未发生多次LLC/SNAP + Length校验错误。 */ + unsigned int ethLlcLenErr : 1; /* * [8:8]1'b1: 发生LLC/SNAP Length校验错误。1'b0：未发生LLC/SNAP + * Length校验错误。 + */ + unsigned int pktLenMinMerr : 1; /* * [7:7]1'b1: 发生多次最小包长错误。1'b0：未发生多次最小包长错误。 */ + unsigned int pktLenMinErr : 1; /* * [6:6]1'b1: 发生最小包长错误。1'b0：未发生最小包长错误。 */ + unsigned int pktLenMaxMerr : 1; /* * [5:5]1'b1: 发生多次最长包长错误。1'b0：未发生多次最长包长错误。 */ + unsigned int pktLenMaxErr : 1; /* * [4:4]1'b1: 发生最长包长错误。1'b0：未发生最长包长错误。 */ + unsigned int fcCrcMerr : 1; /* * [3:3]1'b1: 发生多次FC CRC校验错误。1'b0：未发生多次FC CRC校验错误。 */ + unsigned int fcCrcErr : 1; /* * [2:2]1'b1: 发生FC CRC校验错误。1'b0：未发生FC CRC校验错误。 */ + unsigned int toBmcOnlyPktMerr : 1; /* * [1:1]1'b1: 发生多次TO BMC ONLY错误。1'b0：未发生多次TO BMC ONLY错误。 */ + unsigned int toBmcOnlyPktErr : 1; /* * [0:0]1'b1: 发生TO BMC ONLY校验错误。1'b0：未发生TO BMC ONLY校验错误。 */ +#else + unsigned int toBmcOnlyPktErr : 1; /* * [0:0]1'b1: 发生TO BMC ONLY校验错误。1'b0：未发生TO BMC ONLY校验错误。 */ + unsigned int toBmcOnlyPktMerr : 1; /* * [1:1]1'b1: 发生多次TO BMC ONLY错误。1'b0：未发生多次TO BMC ONLY错误。 */ + unsigned int fcCrcErr : 1; /* * [2:2]1'b1: 发生FC CRC校验错误。1'b0：未发生FC CRC校验错误。 */ + unsigned int fcCrcMerr : 1; /* * [3:3]1'b1: 发生多次FC CRC校验错误。1'b0：未发生多次FC CRC校验错误。 */ + unsigned int pktLenMaxErr : 1; /* * [4:4]1'b1: 发生最长包长错误。1'b0：未发生最长包长错误。 */ + unsigned int pktLenMaxMerr : 1; /* * [5:5]1'b1: 发生多次最长包长错误。1'b0：未发生多次最长包长错误。 */ + unsigned int pktLenMinErr : 1; /* * [6:6]1'b1: 发生最小包长错误。1'b0：未发生最小包长错误。 */ + unsigned int pktLenMinMerr : 1; /* * [7:7]1'b1: 发生多次最小包长错误。1'b0：未发生多次最小包长错误。 */ + unsigned int ethLlcLenErr : 1; /* * [8:8]1'b1: 发生LLC/SNAP Length校验错误。1'b0：未发生LLC/SNAP + * Length校验错误。 + */ + unsigned int ethLlcLenMerr : 1; /* * [9:9]1'b1: 发生多次LLC/SNAP Length校验错误。1'b0：未发生多次LLC/SNAP + Length校验错误。 */ + unsigned int arpPosiErr : 1; /* * [10:10]1'b1: 发生ARP DMAC为单播错误。1'b0：未发生ARP DMAC为单播错误。 */ + unsigned int arpPosiMerr : 1; /* * [11:11]1'b1: 发生多次ARP DMAC为单播错误。1'b0：未发生多次ARP DMAC为单播错误。 + */ + unsigned int dmacSmacEqualErr : 1; /* * [12:12]1'b1: + * 发生目的MAC等于源MAC错误。1'b0：未发生目的MAC等于源MAC错误。 + */ + unsigned int dmacSmacEqualMerr : 1; /* * [13:13]1'b1: + 发生多次目的MAC等于源MAC错误。1'b0：未发生多次目的MAC等于源MAC错误。 */ + unsigned int smacErr : 1; /* * [14:14]1'b1: 发生源MAC错误。1'b0：未发生源MAC错误。 */ + unsigned int smacMerr : 1; /* * [15:15]1'b1: 发生多次源MAC错误。1'b0：未发生多次源MAC错误。 */ + unsigned int dmacZeroErr : 1; /* * [16:16]1'b1: 发生目的MAC为0错误。1'b0：未发生目的MAC为0错误。 */ + unsigned int dmacZeroMerr : 1; /* * [17:17]1'b1: 发生多次目的MAC为0错误。1'b0：未发生多次目的MAC为0错误。 */ + unsigned int directToUpPktErr : 1; /* * [18:18]1'b1: + 发生直接转发到UP的报文校验错误。1'b0：未发生直接转发到UP的报文校验错误。 + */ + unsigned int + directToUpPktMerr : 1; /* * [19:19]1'b1: + 发生多次直接转发到UP的报文校验错误。1'b0：未发生多次直接转发到UP的报文校验错误。 + */ + unsigned int dropByTcamErr : 1; /* * [20:20]1'b1: + 发生TCAM查找结果指示丢弃报文。1'b0：未发生TCAM查找结果指示丢弃报文。 */ + unsigned int dropByTcamMerr : 1; /* * [21:21]1'b1: + 发生多次TCAM查找结果指示丢弃报文。1'b0：未发生多次TCAM查找结果指示丢弃报文。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_OTH_ERR_U; + +/* ** + * Union name : IPSURX_OTH_ERR_MASK + * @brief + * Description: + */ +typedef union tagUnIpsurxOthErrMask { + struct tagStIpsurxOthErrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11]reserved. */ + unsigned int + dropByTcamErrMask : 1; /* * [10:10]1'b1: + 允许上报TCAM查找结果指示丢弃报文。1'b0：不允许上报TCAM查找结果指示丢弃报文。 + */ + unsigned int + directToUpPktErrMask : 1; /* * [9:9]1'b1: + 允许上报直接转发到UP的报文校验错误。1'b0：不允许上报直接转发到UP的报文校验错误。 + */ + unsigned int + dmacZeroErrMask : 1; /* * [8:8]1'b1：允许上报目的MAC为0错误中断；1'b0：不允许上报目的MAC为0错误中断。 */ + unsigned int smacErrMask : 1; /* * [7:7]1'b1：允许上报源MAC错误中断；1'b0：不允许上报源MAC错误中断。 */ + unsigned int dmacSmacEqualErrMask : 1; /* * + [6:6]1'b1：允许上报源MAC等于目的MAC错误中断；1'b0：不允许上报MAC等于目的MAC错误中断。 + */ + unsigned int arpPosiErrMask : 1; /* * + [5:5]1'b1：允许上报ARP目的MAC为单播地址错误中断；1'b0：不允许上报ARP目的MAC为单播地址错误中断。 + */ + unsigned int ethLlcLenErrMask : 1; /* * [4:4]1'b1：允许上报LLC/SNAP Length校验错误中断；1'b0：不允许上报LLC/SNAP + Length校验错误中断。 */ + unsigned int pktLenMinErrMask : 1; /* * [3:3]1'b1：允许上报最小长度错误中断；1'b0：不允许上报最小长度错误中断。 + */ + unsigned int pktLenMaxErrMask : 1; /* * [2:2]1'b1：允许上报最大长度错误中断；1'b0：不允许上报最大长度错误中断。 + */ + unsigned int fcCrcErrMask : 1; /* * [1:1]1'b1：允许上报FC CRC校验错误中断；1'b0：不允许上报FC CRC校验错误中断。 + */ + unsigned int toBmcOnlyPktErrMask : 1; /* * [0:0]1'b1：允许上报TO BMC ONLY错误中断；1'b0：不允许上报TO BMC + ONLY错误中断。 */ +#else + unsigned int toBmcOnlyPktErrMask : 1; /* * [0:0]1'b1：允许上报TO BMC ONLY错误中断；1'b0：不允许上报TO BMC + ONLY错误中断。 */ + unsigned int fcCrcErrMask : 1; /* * [1:1]1'b1：允许上报FC CRC校验错误中断；1'b0：不允许上报FC CRC校验错误中断。 + */ + unsigned int pktLenMaxErrMask : 1; /* * [2:2]1'b1：允许上报最大长度错误中断；1'b0：不允许上报最大长度错误中断。 + */ + unsigned int pktLenMinErrMask : 1; /* * [3:3]1'b1：允许上报最小长度错误中断；1'b0：不允许上报最小长度错误中断。 + */ + unsigned int ethLlcLenErrMask : 1; /* * [4:4]1'b1：允许上报LLC/SNAP Length校验错误中断；1'b0：不允许上报LLC/SNAP + Length校验错误中断。 */ + unsigned int arpPosiErrMask : 1; /* * + [5:5]1'b1：允许上报ARP目的MAC为单播地址错误中断；1'b0：不允许上报ARP目的MAC为单播地址错误中断。 + */ + unsigned int dmacSmacEqualErrMask : 1; /* * + [6:6]1'b1：允许上报源MAC等于目的MAC错误中断；1'b0：不允许上报MAC等于目的MAC错误中断。 + */ + unsigned int smacErrMask : 1; /* * [7:7]1'b1：允许上报源MAC错误中断；1'b0：不允许上报源MAC错误中断。 */ + unsigned int + dmacZeroErrMask : 1; /* * [8:8]1'b1：允许上报目的MAC为0错误中断；1'b0：不允许上报目的MAC为0错误中断。 */ + unsigned int + directToUpPktErrMask : 1; /* * [9:9]1'b1: + 允许上报直接转发到UP的报文校验错误。1'b0：不允许上报直接转发到UP的报文校验错误。 + */ + unsigned int + dropByTcamErrMask : 1; /* * [10:10]1'b1: + 允许上报TCAM查找结果指示丢弃报文。1'b0：不允许上报TCAM查找结果指示丢弃报文。 + */ + unsigned int reserved : 21; /* * [31:11]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_OTH_ERR_MASK_U; + +/* ** + * Union name : IPSURX_IPSUTX_AFIFO_OVFL + * @brief + * Description: + */ +typedef union tagUnIpsurxIpsutxAfifoOvfl { + struct tagStIpsurxIpsutxAfifoOvfl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int sticky : 1; /* * [2:2]IPSUTX时钟域到IPSURX时钟域溢出异步FIFO编号。1'b0: IPSUTX到IPSURX + * CSR异步FIFO溢出；1'b1: IPSUTX到IPSURX 中断CSR异步FIFO溢出。 + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 1; /* * [2:2]IPSUTX时钟域到IPSURX时钟域溢出异步FIFO编号。1'b0: IPSUTX到IPSURX + * CSR异步FIFO溢出；1'b1: IPSUTX到IPSURX 中断CSR异步FIFO溢出。 + */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPSUTX_AFIFO_OVFL_U; + + +/* ** + * Union name : IPSURX_INDRECT_CTRL + * @brief 间接寻址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectCtrl { + struct tagStIpsurxIndrectCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxIndrectVld : 1; /* * + * [31:31]VALID：CPU发起读、写操作时将VALID域置1，内部一次操作完成后将VALID清零。具体为：内部成功写/读操作之后，将VALID清零，读操作TIMEOUT后也将VALID清零。 + */ + unsigned int ipsurxIndrectMode : 1; /* * [30:30]OPERATION_MODE.1'b1 : Read;1'b0 : Write. */ + unsigned int ipsurxIndrectStat : 2; /* * [29:28]STATUS :2'b00: OK;2'b01: Time out;Others: Reserved. */ + unsigned int ipsurxIndrectTab : 4; /* * [27:24]bit[3:2]保留未用，bit[1:0]表示间接寻址表编号： + 0x0：TCAM/ART表；0x1：TPT表；Others: 保留未用。 */ + unsigned int ipsurxIndrectAddr : 24; /* * [23:0]模块间接寻址MEM地址。TCAM + * TABLE：寻址范围为0~511，仅bit[8:0]有效；TPT + * TABLE：寻址范围为0~2047，仅bit[10:0]有效。 + */ +#else + unsigned int ipsurxIndrectAddr : 24; /* * [23:0]模块间接寻址MEM地址。TCAM + * TABLE：寻址范围为0~511，仅bit[8:0]有效；TPT + * TABLE：寻址范围为0~2047，仅bit[10:0]有效。 + */ + unsigned int ipsurxIndrectTab : 4; /* * [27:24]bit[3:2]保留未用，bit[1:0]表示间接寻址表编号： + 0x0：TCAM/ART表；0x1：TPT表；Others: 保留未用。 */ + unsigned int ipsurxIndrectStat : 2; /* * [29:28]STATUS :2'b00: OK;2'b01: Time out;Others: Reserved. */ + unsigned int ipsurxIndrectMode : 1; /* * [30:30]OPERATION_MODE.1'b1 : Read;1'b0 : Write. */ + unsigned int + ipsurxIndrectVld : 1; /* * + * [31:31]VALID：CPU发起读、写操作时将VALID域置1，内部一次操作完成后将VALID清零。具体为：内部成功写/读操作之后，将VALID清零，读操作TIMEOUT后也将VALID清零。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_CTRL_U; + +/* ** + * Union name : IPSURX_INDRECT_TIMEOUT + * @brief 间接寻址TIMEOUT配置寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectTimeout { + struct tagStIpsurxIndrectTimeout { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectTimeout : 32; /* * + [31:0]间接寻址TIMEOUT配置寄存器。发起的间接读/写没有返回时，不能改变该值。 + */ +#else + unsigned int ipsurxIndrectTimeout : 32; /* * + [31:0]间接寻址TIMEOUT配置寄存器。发起的间接读/写没有返回时，不能改变该值。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_TIMEOUT_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA0 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData0 { + struct tagStIpsurxIndrectData0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData0 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData0 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA0_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA1 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData1 { + struct tagStIpsurxIndrectData1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData1 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData1 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA1_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA2 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData2 { + struct tagStIpsurxIndrectData2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData2 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData2 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA2_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA3 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData3 { + struct tagStIpsurxIndrectData3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData3 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData3 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA3_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA4 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData4 { + struct tagStIpsurxIndrectData4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData4 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData4 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA4_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA5 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData5 { + struct tagStIpsurxIndrectData5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData5 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData5 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA5_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA6 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData6 { + struct tagStIpsurxIndrectData6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData6 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData6 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA6_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA7 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData7 { + struct tagStIpsurxIndrectData7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData7 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData7 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA7_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA8 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData8 { + struct tagStIpsurxIndrectData8 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData8 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData8 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA8_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA9 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData9 { + struct tagStIpsurxIndrectData9 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData9 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData9 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA9_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA10 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData10 { + struct tagStIpsurxIndrectData10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData10 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData10 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA10_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA11 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData11 { + struct tagStIpsurxIndrectData11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData11 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData11 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA11_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA12 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData12 { + struct tagStIpsurxIndrectData12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData12 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData12 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA12_U; + +/* ** + * Union name : IPSURX_INDRECT_DATA13 + * @brief 间接寻址数据寄存器 + * Description: + */ +typedef union tagUnIpsurxIndrectData13 { + struct tagStIpsurxIndrectData13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIndrectData13 : 32; /* * [31:0]间接寻址数据寄存器 */ +#else + unsigned int ipsurxIndrectData13 : 32; /* * [31:0]间接寻址数据寄存器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_INDRECT_DATA13_U; + + +/* ** + * Union name : IPSURX_CH16_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh16AtDw0 { + struct tagStIpsurxCh16AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh16Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh16Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh161588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh16Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh16EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh16Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh16CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh16SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh161588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh16Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh16Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH16_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH16_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh16AtDw1 { + struct tagStIpsurxCh16AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh16DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh168023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh16Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh16Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh16Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh16Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh16Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh16Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh16ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh168023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh16DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH16_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH16_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh16AtDw2 { + struct tagStIpsurxCh16AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh16Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh16Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh16FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh16FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh16RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh16Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh16Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh16Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh16Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH16_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH16_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh16AtDw3 { + struct tagStIpsurxCh16AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh16MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh16MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh16PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh16PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh16MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh16MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH16_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH16_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh16AtDw4 { + struct tagStIpsurxCh16AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh16DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh16DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh16DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh16DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh16DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh16DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh16DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh16DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH16_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH15_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh15AtDw0 { + struct tagStIpsurxCh15AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh15Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh15Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh151588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh15Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh15EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh15Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh15CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh15SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh151588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh15Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh15Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH15_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH15_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh15AtDw1 { + struct tagStIpsurxCh15AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh15DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh158023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh15Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh15Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh15Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh15Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh15Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh15Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh15ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh158023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh15DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH15_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH15_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh15AtDw2 { + struct tagStIpsurxCh15AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh15Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh15Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh15FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh15FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh15RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh15Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh15Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh15Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh15Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH15_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH15_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh15AtDw3 { + struct tagStIpsurxCh15AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh15MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh15MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh15PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh15PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh15MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh15MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH15_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH15_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh15AtDw4 { + struct tagStIpsurxCh15AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh15DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh15DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh15DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh15DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh15DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh15DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh15DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh15DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH15_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH14_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh14AtDw0 { + struct tagStIpsurxCh14AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh14Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh14Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh141588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh14Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh14EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh14Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh14CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh14SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh141588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh14Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh14Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH14_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH14_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh14AtDw1 { + struct tagStIpsurxCh14AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh14DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh148023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh14Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh14Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh14Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh14Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh14Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh14Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh14ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh148023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh14DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH14_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH14_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh14AtDw2 { + struct tagStIpsurxCh14AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh14Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh14Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh14FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh14FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh14RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh14Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh14Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh14Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh14Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH14_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH14_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh14AtDw3 { + struct tagStIpsurxCh14AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh14MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh14MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh14PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh14PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh14MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh14MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH14_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH14_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh14AtDw4 { + struct tagStIpsurxCh14AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh14DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh14DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh14DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh14DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh14DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh14DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh14DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh14DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH14_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH13_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh13AtDw0 { + struct tagStIpsurxCh13AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh13Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh13Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh131588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh13Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh13EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh13Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh13CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh13SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh131588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh13Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh13Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH13_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH13_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh13AtDw1 { + struct tagStIpsurxCh13AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh13DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh138023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh13Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh13Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh13Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh13Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh13Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh13Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh13ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh138023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh13DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH13_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH13_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh13AtDw2 { + struct tagStIpsurxCh13AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh13Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh13Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh13FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh13FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh13RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh13Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh13Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh13Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh13Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH13_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH13_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh13AtDw3 { + struct tagStIpsurxCh13AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh13MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh13MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh13PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh13PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh13MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh13MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH13_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH13_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh13AtDw4 { + struct tagStIpsurxCh13AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh13DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh13DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh13DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh13DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh13DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh13DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh13DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh13DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH13_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH12_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh12AtDw0 { + struct tagStIpsurxCh12AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh12Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh12Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh121588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh12Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh12EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh12Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh12CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh12SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh121588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh12Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh12Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH12_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH12_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh12AtDw1 { + struct tagStIpsurxCh12AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh12DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh128023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh12Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh12Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh12Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh12Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh12Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh12Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh12ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh128023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh12DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH12_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH12_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh12AtDw2 { + struct tagStIpsurxCh12AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh12Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh12Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh12FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh12FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh12RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh12Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh12Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh12Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh12Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH12_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH12_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh12AtDw3 { + struct tagStIpsurxCh12AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh12MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh12MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh12PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh12PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh12MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh12MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH12_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH12_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh12AtDw4 { + struct tagStIpsurxCh12AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh12DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh12DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh12DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh12DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh12DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh12DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh12DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh12DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH12_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH11_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh11AtDw0 { + struct tagStIpsurxCh11AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh11Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh11Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh111588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh11Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh11EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh11Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh11CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh11SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh111588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh11Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh11Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH11_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH11_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh11AtDw1 { + struct tagStIpsurxCh11AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh11DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh118023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh11Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh11Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh11Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh11Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh11Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh11Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh11ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh118023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh11DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH11_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH11_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh11AtDw2 { + struct tagStIpsurxCh11AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh11Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh11Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh11FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh11FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh11RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh11Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh11Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh11Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh11Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH11_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH11_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh11AtDw3 { + struct tagStIpsurxCh11AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh11MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh11MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh11PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh11PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh11MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh11MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH11_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH11_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh11AtDw4 { + struct tagStIpsurxCh11AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh11DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh11DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh11DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh11DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh11DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh11DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh11DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh11DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH11_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH10_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh10AtDw0 { + struct tagStIpsurxCh10AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh10Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh10Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh101588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh10Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh10EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh10Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh10CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh10SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh101588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh10Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh10Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH10_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH10_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh10AtDw1 { + struct tagStIpsurxCh10AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh10DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh108023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh10Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh10Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh10Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh10Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh10Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh10Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh10ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh108023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh10DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH10_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH10_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh10AtDw2 { + struct tagStIpsurxCh10AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh10Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh10Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh10FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh10FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh10RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh10Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh10Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh10Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh10Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH10_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH10_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh10AtDw3 { + struct tagStIpsurxCh10AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh10MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh10MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh10PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh10PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh10MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh10MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH10_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH10_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh10AtDw4 { + struct tagStIpsurxCh10AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh10DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh10DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh10DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh10DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh10DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh10DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh10DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh10DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH10_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH09_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh09AtDw0 { + struct tagStIpsurxCh09AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh09Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh09Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh091588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh09Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh09EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh09Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh09CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh09SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh091588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh09Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh09Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH09_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH09_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh09AtDw1 { + struct tagStIpsurxCh09AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh09DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh098023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh09Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh09Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh09Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh09Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh09Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh09Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh09ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh098023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh09DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH09_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH09_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh09AtDw2 { + struct tagStIpsurxCh09AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh09Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh09Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh09FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh09FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh09RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh09Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh09Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh09Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh09Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH09_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH09_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh09AtDw3 { + struct tagStIpsurxCh09AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh09MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh09MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh09PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh09PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh09MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh09MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH09_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH09_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh09AtDw4 { + struct tagStIpsurxCh09AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh09DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh09DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh09DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh09DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh09DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh09DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh09DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh09DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH09_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH08_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh08AtDw0 { + struct tagStIpsurxCh08AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh08Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh08Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh081588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh08Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh08EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh08Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh08CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh08SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh081588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh08Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh08Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH08_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH08_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh08AtDw1 { + struct tagStIpsurxCh08AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh08DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh088023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh08Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh08Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh08Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh08Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh08Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh08Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh08ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh088023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh08DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH08_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH08_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh08AtDw2 { + struct tagStIpsurxCh08AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh08Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh08Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh08FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh08FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh08RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh08Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh08Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh08Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh08Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH08_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH08_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh08AtDw3 { + struct tagStIpsurxCh08AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh08MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh08MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh08PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh08PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh08MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh08MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH08_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH08_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh08AtDw4 { + struct tagStIpsurxCh08AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh08DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh08DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh08DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh08DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh08DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh08DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh08DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh08DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH08_AT_DW4_U; + + +/* ** + * Union name : IPSURX_CH07_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh07AtDw0 { + struct tagStIpsurxCh07AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh07Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh07Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh071588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh07Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh07EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh07Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh07CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh07SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh071588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh07Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh07Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH07_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH07_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh07AtDw1 { + struct tagStIpsurxCh07AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh07DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh078023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh07Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh07Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh07Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh07Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh07Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh07Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh07ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh078023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh07DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH07_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH07_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh07AtDw2 { + struct tagStIpsurxCh07AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh07Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh07Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh07FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh07FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh07RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh07Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh07Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh07Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh07Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH07_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH07_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh07AtDw3 { + struct tagStIpsurxCh07AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh07MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh07MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh07PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh07PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh07MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh07MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH07_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH07_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh07AtDw4 { + struct tagStIpsurxCh07AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh07DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh07DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh07DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh07DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh07DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh07DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh07DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh07DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH07_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH06_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh06AtDw0 { + struct tagStIpsurxCh06AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh06Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh06Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh061588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh06Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh06EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh06Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh06CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh06SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh061588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh06Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh06Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH06_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH06_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh06AtDw1 { + struct tagStIpsurxCh06AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh06DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh068023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh06Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh06Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh06Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh06Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh06Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh06Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh06ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh068023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh06DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH06_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH06_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh06AtDw2 { + struct tagStIpsurxCh06AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh06Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh06Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh06FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh06FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh06RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh06Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh06Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh06Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh06Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH06_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH06_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh06AtDw3 { + struct tagStIpsurxCh06AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh06MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh06MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh06PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh06PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh06MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh06MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH06_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH06_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh06AtDw4 { + struct tagStIpsurxCh06AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh06DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh06DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh06DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh06DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh06DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh06DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh06DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh06DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH06_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH05_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh05AtDw0 { + struct tagStIpsurxCh05AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh05Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh05Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh051588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh05Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh05EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh05Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh05CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh05SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh051588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh05Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh05Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH05_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH05_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh05AtDw1 { + struct tagStIpsurxCh05AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh05DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh058023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh05Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh05Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh05Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh05Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh05Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh05Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh05ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh058023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh05DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH05_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH05_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh05AtDw2 { + struct tagStIpsurxCh05AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh05Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh05Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh05FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh05FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh05RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh05Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh05Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh05Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh05Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH05_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH05_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh05AtDw3 { + struct tagStIpsurxCh05AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh05MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh05MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh05PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh05PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh05MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh05MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH05_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH05_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh05AtDw4 { + struct tagStIpsurxCh05AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh05DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh05DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh05DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh05DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh05DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh05DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh05DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh05DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH05_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH04_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh04AtDw0 { + struct tagStIpsurxCh04AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh04Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh04Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh041588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh04Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh04EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh04Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh04CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh04SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh041588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh04Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh04Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH04_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH04_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh04AtDw1 { + struct tagStIpsurxCh04AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh04DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh048023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh04Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh04Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh04Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh04Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh04Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh04Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh04ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh048023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh04DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH04_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH04_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh04AtDw2 { + struct tagStIpsurxCh04AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh04Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh04Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh04FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh04FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh04RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh04Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh04Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh04Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh04Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH04_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH04_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh04AtDw3 { + struct tagStIpsurxCh04AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh04MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh04MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh04PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh04PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh04MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh04MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH04_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH04_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh04AtDw4 { + struct tagStIpsurxCh04AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh04DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh04DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh04DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh04DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh04DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh04DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh04DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh04DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH04_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH03_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh03AtDw0 { + struct tagStIpsurxCh03AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh03Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh03Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh031588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh03Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh03EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh03Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh03CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh03SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh031588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh03Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh03Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH03_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH03_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh03AtDw1 { + struct tagStIpsurxCh03AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh03DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh038023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh03Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh03Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh03Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh03Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh03Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh03Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh03ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh038023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh03DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH03_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH03_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh03AtDw2 { + struct tagStIpsurxCh03AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh03Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh03Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh03FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh03FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh03RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh03Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh03Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh03Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh03Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH03_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH03_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh03AtDw3 { + struct tagStIpsurxCh03AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh03MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh03MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh03PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh03PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh03MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh03MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH03_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH03_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh03AtDw4 { + struct tagStIpsurxCh03AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh03DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh03DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh03DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh03DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh03DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh03DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh03DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh03DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH03_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH02_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh02AtDw0 { + struct tagStIpsurxCh02AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh02Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh02Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh021588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh02Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh02EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh02Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh02CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh02SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh021588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh02Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh02Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH02_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH02_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh02AtDw1 { + struct tagStIpsurxCh02AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh02DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh028023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh02Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh02Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh02Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh02Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh02Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh02Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh02ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh028023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh02DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH02_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH02_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh02AtDw2 { + struct tagStIpsurxCh02AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh02Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh02Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh02FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh02FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh02RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh02Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh02Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh02Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh02Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH02_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH02_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh02AtDw3 { + struct tagStIpsurxCh02AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh02MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh02MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh02PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh02PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh02MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh02MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH02_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH02_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh02AtDw4 { + struct tagStIpsurxCh02AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh02DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh02DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh02DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh02DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh02DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh02DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh02DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh02DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH02_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH01_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh01AtDw0 { + struct tagStIpsurxCh01AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh01Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh01Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh011588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh01Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh01EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh01Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh01CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh01SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh011588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh01Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh01Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH01_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH01_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh01AtDw1 { + struct tagStIpsurxCh01AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh01DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh018023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh01Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh01Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh01Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh01Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh01Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh01Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh01ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh018023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh01DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH01_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH01_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh01AtDw2 { + struct tagStIpsurxCh01AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh01Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh01Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh01FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh01FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh01RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh01Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh01Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh01Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh01Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH01_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH01_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh01AtDw3 { + struct tagStIpsurxCh01AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh01MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh01MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh01PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh01PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh01MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh01MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH01_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH01_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh01AtDw4 { + struct tagStIpsurxCh01AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh01DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh01DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh01DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh01DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh01DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh01DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh01DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh01DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH01_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH00_AT_DW0 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh00AtDw0 { + struct tagStIpsurxCh00AtDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxCh00Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ + unsigned int ipsurxCh00Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh001588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh00Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int + ipsurxCh00EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh00Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ +#else + unsigned int + ipsurxCh00CntagTpidSel : 2; /* * [1:0]通道报文CNTAG的TPID选择。 + * Bit[i](i=0,1)为1，表示配置的ipsurx_cntag_tpid[i]（i=0,1)有效。特别地，2'b00表示不存在CN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00Cntag : 1; /* * [2:2]报文CNTAG存在标识。1'b0: + * 需要根据ipsurx_cntag_tpid_sel的值比较TPID，判断CNTAG是否存在；1'b1: + * 该通道所有报文均含有CNTAG。注意：如果不确定该通道所有报文都含有CNTAG，应配置为1'b0。比如，通道有IEEE + * 802.2 LLC封装的报文。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00CvlanTpidSel : 5; /* * [7:3]报文内层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_cvlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在内层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00Cvlan : 1; /* * [8:8]内层VLAN + * TAG存在标识。1'b0:需要根据ipsurx_cvlan_tpid_sel配置比较TPID确定是否存在内层VLAN；1'b1:该通道所有报文存在内层VLAN。该字段对FC通道无效。 + */ + unsigned int reserved1 : 1; /* * [9:9] */ + unsigned int + ipsurxCh00SvlanTpidSel : 5; /* * [14:10]报文外层VLAN + * TAG的TPID选择。Bit[i](i=0,1,2,3,4)为1，表示配置的ipsurx_svlan_tpid[i]（i=0,1,2,3,4)有效。特别地，5'b00000表示不存在外层VLAN + * TAG。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00Svlan : 1; /* * [15:15]外层VLAN + TAG存在标识。1'b0:需要比较TPID确定是否存在外层VLAN；1'b1:该通道所有报文存在外层VLAN。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00EvtagTpidSel : 4; /* * + * [19:16]报文E-Tag/VN-Tag的TPID选择。Bit[i](i=0,1,2,3)为1，表示配置的ipsurx_evtag_tpid[i]（i=0,1,2,3)有效。特别地，4'b0000表示不存在E-TAG/VN-TAG。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00EvtagLen : 2; /* * [21:20]E-Tag/VN-Tag长度。2'b00: 4 字节；2'b01: 6 字节；2'b10: 8 + 字节；2'b11: 保留。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Evtag : 2; /* * [23:22]E-Tag/VN-Tag存在标识. 2'b00: + * 需要比较TPID确定报文是否含有E-TAG；2'b01: 所有报文都含有E-Tag；2'b10: + * 需要比较TPID确定报文是否含有VN-TAG；2'b11: + * 所有报文都含有VN-Tag。该字段对FC通道无效。 + */ + unsigned int reserved0 : 4; /* * [27:24] */ + unsigned int ipsurxCh001588v2En : 1; /* * [28:28]1588v2使能标志。1'b0: 该通道未使能1588v2功能；1'b1: + 该通道使能了1588v2功能。该字段仅对标准MAC通道有效。 */ + unsigned int ipsurxCh00Type : 2; /* * [30:29]通道类型。2'b00: 标准MAC通道，报文不含HG2或者NP2NP头；2'b01: + HG2通道；2'b10: FC通道；2'b11: FIC通道。 */ + unsigned int ipsurxCh00Valid : 1; /* * [31:31]通道使能标志。1'b0：通道未使能；1'b1：通道使能。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH00_AT_DW0_U; + +/* ** + * Union name : IPSURX_CH00_AT_DW1 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh00AtDw1 { + struct tagStIpsurxCh00AtDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh00DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh008023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh00Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh00Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh00Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#else + unsigned int ipsurxCh00Ipv4BlandcsEn : 1; /* * [0:0]盲算 IPv4 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeRocev2Ipv4En : 1; /* * [1:1]DIFX CRC16 for NVMe over RoCEv2 over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeIwarpIpv4En : 1; /* * [2:2]DIFX CRC16 for NVMe over IWARP over + IPv4计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IwarpCrcEn : 1; /* * [3:3]IPv4 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4TcpCsChkEn : 1; /* * [4:4]IPv4 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4TcpSynChkEn : 1; /* * [5:5]IPv4/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4SctpCsChkEn : 1; /* * [6:6]IPv4 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IcmpCsChkEn : 1; /* * [7:7]IPv4 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IgmpCsChkEn : 1; /* * [8:8]IPv4 IGMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev2Ipv4UdpCsChkEn : 1; /* * [9:9]RoCEv2 over UDP/IPv4报文UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh00Rocev2Ipv4FraChkEn : 1; /* * [10:10]RoCEv2 over + UDP/IPv4报文IPv4分片校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Ipv4UdpCsChkEn : 1; /* * [11:11]通道IPv4 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IpCsChkEn : 1; /* * [12:12]IPv4 Header + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4DipChkEn : 1; /* * [13:13]IPv4报文Destination + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4SipChkEn : 1; /* * [14:14]IPv4报文Source + IP字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv4IhlChkEn : 1; /* * [15:15]IPv4报文IHL字段校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxCh00Ipv4VerChkEn : 1; /* * + * [16:16]IPv4报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved : 10; /* * [26:17] */ + unsigned int + ipsurxCh00ArpReqDmacChkEn : 1; /* * [27:27]ARP + REQUEST报文DMAC校验使能.1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh008023LenChkEn : 1; /* * + [28:28]使能校验LLC/SNAP封装的LENGTH。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00DaSaEqualChkEn : 1; /* * + [29:29]使能检查源MAC等于目的MAC。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00SmacChkEn : 1; /* * + [30:30]使能检查源MAC是否为单播MAC地址。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int + ipsurxCh00DmacZeroChkEn : 1; /* * [31:31]使能检查DMAC为0。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH00_AT_DW1_U; + +/* ** + * Union name : IPSURX_CH00_AT_DW2 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh00AtDw2 { + struct tagStIpsurxCh00AtDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxCh00Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh00Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh00FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh00FcCrcChkEn : 1; /* * [0:0]FC CRC校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved1 : 3; /* * [3:1] */ + unsigned int ipsurxCh00RoceIcrcChkEn : 1; /* * [4:4]RoCE + ICRC校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00RoceDqpChkEn : 1; /* * [5:5]RoCE BTH 头部header DQP + 字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev1DgidChkEn : 1; /* * + [6:6]RoCEv1报文DGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Rocev1SgidChkEn : 1; /* * + [7:7]RoCEv1报文SGID字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00NvmeRocev1En : 1; /* * [8:8]DIFX CRC16 for NVMe over + RoCEv1计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev1NxhdrChkEn : 1; /* * + [9:9]RoCEv1报文NXHDR字段校验使能。。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int ipsurxCh00Rocev1PlenChkEn : 1; /* * [10:10]RoCEv1报文GRH Payload + Length域校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev1IpverChkEn : 1; /* * + [11:11]RoCEv1报文IPVER字段校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ + unsigned int reserved0 : 6; /* * [17:12] */ + unsigned int ipsurxCh00Ipv6BlandcsEn : 1; /* * [18:18]盲算 IPv6 + CS使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeRocev2Ipv6En : 1; /* * [19:19]DIFX CRC16 for NVMe over RoCEv2 over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00NvmeIwarpIpv6En : 1; /* * [20:20]DIFX CRC16 for NVMe over IWARP over + IPv6计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6IwarpCrcEn : 1; /* * [21:21]IPv6 IWARP + CRC计算使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6TcpCsChkEn : 1; /* * [22:22]IPv6 TCP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6TcpSynChkEn : 1; /* * [23:23]IPv6/TCP报文SYN + LAND校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6SctpCsChkEn : 1; /* * [24:24]IPv6 SCTP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6IcmpCsChkEn : 1; /* * [25:25]IPv6 ICMP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Rocev2Ipv6UdpCsChkEn : 1; /* * [26:26]RoCEv2 over IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6UdpCsChkEn : 1; /* * [27:27]IPv6 UDP + CS校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6UdpcsZeroChkEn : 1; /* * [28:28]IPv6报文UDP + CS为0校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6DipChkEn : 1; /* * [29:29]IPv6报文Destination + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int ipsurxCh00Ipv6SipChkEn : 1; /* * [30:30]IPv6报文Source + IP校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 */ + unsigned int + ipsurxCh00Ipv6VerChkEn : 1; /* * + * [31:31]IPv6报文Version校验使能。1'b0：禁止；1'b1：使能。该字段对FC通道无效。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH00_AT_DW2_U; + +/* ** + * Union name : IPSURX_CH00_AT_DW3 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh00AtDw3 { + struct tagStIpsurxCh00AtDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 10; /* * [31:22]reserved. */ + unsigned int ipsurxCh00MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int ipsurxCh00MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh00PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ +#else + unsigned int ipsurxCh00PktLenChkEn : 1; /* * [0:0]报文长度校验使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxCh00MinPktLen : 7; /* * [7:1]最小报文长度配置。可配值范围：0x1E - 0x3F。 */ + unsigned int ipsurxCh00MaxPktLen : 14; /* * [21:8]最大报文长度配置。默认值：0x3E00。可配值范围：0x100 - 0x3F00。 + */ + unsigned int reserved : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH00_AT_DW3_U; + +/* ** + * Union name : IPSURX_CH00_AT_DW4 + * @brief IPSURX通道属性配置表 + * Description: + */ +typedef union tagUnIpsurxCh00AtDw4 { + struct tagStIpsurxCh00AtDw4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21] */ + unsigned int ipsurxCh00DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh00DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh00DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int ipsurxCh00DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ +#else + unsigned int ipsurxCh00DfltPushLen : 4; /* * [3:0]指示CPB缺省PUSH到TILE的报文字节数。4'hC：192字节；……4'h2：32 + * 字节；4'h1：16 字节；4'h0,4hD,4hE和4'hF不可使用。 + */ + unsigned int ipsurxCh00DfltFwdAct : 3; /* * + [6:4]缺省报文转发指示。3'b001：直接转发BMC；3'b010：直接转发UP；3'b100：转发TILE；其它值：不允许配置。 + */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxCh00DfltPktPri : 3; /* * [10:8]缺省报文优先级。3'b000，最高优先级；…3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [11:11] */ + unsigned int ipsurxCh00DfltPktType : 9; /* * [20:12]缺省报文类型。报文类型定义详见IPSURX FS。 */ + unsigned int reserved0 : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH00_AT_DW4_U; + +/* ** + * Union name : IPSURX_CH_INVLD_HST + * @brief 通道无效状态寄存器 + * Description: + */ +typedef union tagUnIpsurxChInvldHst { + struct tagStIpsurxChInvldHst { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17]reserved. */ + unsigned int + ipsurxCh16InvldHst : 1; /* * [16:16]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b0：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh15InvldHst : 1; /* * [15:15]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b0：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh14InvldHst : 1; /* * [14:14]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b1：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh13InvldHst : 1; /* * [13:13]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b2：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh12InvldHst : 1; /* * [12:12]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b3：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh11InvldHst : 1; /* * [11:11]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b4：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh10InvldHst : 1; /* * [10:10]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b5：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh9InvldHst : 1; /* * [9:9]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b6：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh8InvldHst : 1; /* * [8:8]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b7：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh7InvldHst : 1; /* * [7:7]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b8：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh6InvldHst : 1; /* * [6:6]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b9：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh5InvldHst : 1; /* * [5:5]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b10：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh4InvldHst : 1; /* * [4:4]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b11：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh3InvldHst : 1; /* * [3:3]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b12：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh2InvldHst : 1; /* * [2:2]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b13：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh1InvldHst : 1; /* * [1:1]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b14：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh0InvldHst : 1; /* * [0:0]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b15：未在通道未使能情况下收到数据。 + */ +#else + unsigned int + ipsurxCh0InvldHst : 1; /* * [0:0]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b15：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh1InvldHst : 1; /* * [1:1]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b14：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh2InvldHst : 1; /* * [2:2]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b13：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh3InvldHst : 1; /* * [3:3]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b12：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh4InvldHst : 1; /* * [4:4]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b11：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh5InvldHst : 1; /* * [5:5]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b10：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh6InvldHst : 1; /* * [6:6]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b9：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh7InvldHst : 1; /* * [7:7]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b8：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh8InvldHst : 1; /* * [8:8]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b7：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh9InvldHst : 1; /* * [9:9]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b6：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh10InvldHst : 1; /* * [10:10]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b5：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh11InvldHst : 1; /* * [11:11]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b4：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh12InvldHst : 1; /* * [12:12]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b3：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh13InvldHst : 1; /* * [13:13]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b2：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh14InvldHst : 1; /* * [14:14]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b1：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh15InvldHst : 1; /* * [15:15]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b0：未在通道未使能情况下收到数据。 + */ + unsigned int + ipsurxCh16InvldHst : 1; /* * [16:16]同时记录MAG PORT或者FIC + TP未使能但收到数据的情况。1'b1：在通道未使能情况下收到数据；1'b0：未在通道未使能情况下收到数据。 + */ + unsigned int reserved : 15; /* * [31:17]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CH_INVLD_HST_U; + +/* ** + * Union name : IPSURX_SOP_EOP_ST + * @brief SOP/EOP检测状态寄存器 + * Description: + */ +typedef union tagUnIpsurxSopEopSt { + struct tagStIpsurxSopEopSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10]reserved. */ + unsigned int ipsurxFicSopEopSt : 1; /* * [9:9]FIC端口输入报文的SOP/EOP检测状态1'b0：等待SOP1'b1：等待EOP */ + unsigned int ipsurxMagSopEopSt : 9; /* * [8:0]bit[0]：对应 MAG PORT0 输入数据的SOP/EOP状态。bit[1]：对应 MAG + PORT1 输入数据的SOP/EOP状态。……bit[7]：对应 MAG PORT7 + 输入数据的SOP/EOP状态。bit[8]：对应 MAG PORT16（回传时戳) + 输入数据的SOP/EOP状态。1'b0：等待SOP； 1'b1：等待EOP。 */ +#else + unsigned int ipsurxMagSopEopSt : 9; /* * [8:0]bit[0]：对应 MAG PORT0 输入数据的SOP/EOP状态。bit[1]：对应 MAG + PORT1 输入数据的SOP/EOP状态。……bit[7]：对应 MAG PORT7 + 输入数据的SOP/EOP状态。bit[8]：对应 MAG PORT16（回传时戳) + 输入数据的SOP/EOP状态。1'b0：等待SOP； 1'b1：等待EOP。 */ + unsigned int ipsurxFicSopEopSt : 1; /* * [9:9]FIC端口输入报文的SOP/EOP检测状态1'b0：等待SOP1'b1：等待EOP */ + unsigned int reserved : 22; /* * [31:10]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SOP_EOP_ST_U; + +/* ** + * Union name : IPSURX_SOP_WITH_ERR_CNT + * @brief SOP_WITH_ERR错误计数器 + * Description: + */ +typedef union tagUnIpsurxSopWithErrCnt { + struct tagStIpsurxSopWithErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxSopWithErrCnt : 32; /* * [31:0]统计当处于WSOP时，输入数据有效，但SOP无效的数据的拍数。 */ +#else + unsigned int ipsurxSopWithErrCnt : 32; /* * [31:0]统计当处于WSOP时，输入数据有效，但SOP无效的数据的拍数。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SOP_WITH_ERR_CNT_U; + +/* ** + * Union name : IPSURX_ABORT_BF_IPSURX_CNT + * @brief ABORT_BF_IPSURX错误计数器 + * Description: + */ +typedef union tagUnIpsurxAbortBfIpsurxCnt { + struct tagStIpsurxAbortBfIpsurxCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxAbortBfIpsurxCnt : 32; /* * [31:0]统计输入数据有效，前一级模块指示abort的数据。 */ +#else + unsigned int ipsurxAbortBfIpsurxCnt : 32; /* * [31:0]统计输入数据有效，前一级模块指示abort的数据。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ABORT_BF_IPSURX_CNT_U; + +/* ** + * Union name : IPSURX_SOP_SOP_ERR_CNT + * @brief SOP_SOP错误计数器 + * Description: + */ +typedef union tagUnIpsurxSopSopErrCnt { + struct tagStIpsurxSopSopErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxSopSopErrCnt : 32; /* * [31:0]统计当处于WEOP时，输入数据有效，SOP连续出现的错误。 */ +#else + unsigned int ipsurxSopSopErrCnt : 32; /* * [31:0]统计当处于WEOP时，输入数据有效，SOP连续出现的错误。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SOP_SOP_ERR_CNT_U; + +/* ** + * Union name : IPSURX_PKT_MIN_LEN_ILGL_CNT + * @brief 接收超短报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxPktMinLenIlglCnt { + struct tagStIpsurxPktMinLenIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxPktMinLenIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxPktMinLenIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PKT_MIN_LEN_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_PKT_MAX_LEN_ILGL_CNT + * @brief 接收超长报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxPktMaxLenIlglCnt { + struct tagStIpsurxPktMaxLenIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxPktMaxLenIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxPktMaxLenIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PKT_MAX_LEN_ILGL_CNT_U; + + +/* ** + * Union name : IPSURX_NP2NP_FIELD_LOC + * @brief NP2NP头字段位置配置寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npFieldLoc { + struct tagStIpsurxNp2npFieldLoc { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 2; /* * [31:30]reserved. */ + unsigned int ipsurxNp2npSbLoc : 6; /* * [29:24]NP2NP头SB字段的起始位置。建议不修改默认值。 */ + unsigned int reserved1 : 2; /* * [23:22] */ + unsigned int ipsurxNp2npColorLoc : 6; /* * [21:16]NP2NP头COLOR字段的起始位置。建议不修改默认值。 */ + unsigned int reserved2 : 2; /* * [15:14] */ + unsigned int ipsurxNp2npQindexLoc : 6; /* * [13:8]NP2NP头QINDEX字段的起始位置。建议不修改默认值。 */ + unsigned int ipsurxNp2npFhlLoc : 4; /* * [7:4]NP2NP头FHL字段的起始位置。建议不修改默认值。 */ + unsigned int ipsurxNp2npUcLoc : 4; /* * [3:0]NP2NP头UC比特位置。建议不修改默认值。 */ +#else + unsigned int ipsurxNp2npUcLoc : 4; /* * [3:0]NP2NP头UC比特位置。建议不修改默认值。 */ + unsigned int ipsurxNp2npFhlLoc : 4; /* * [7:4]NP2NP头FHL字段的起始位置。建议不修改默认值。 */ + unsigned int ipsurxNp2npQindexLoc : 6; /* * [13:8]NP2NP头QINDEX字段的起始位置。建议不修改默认值。 */ + unsigned int reserved2 : 2; /* * [15:14] */ + unsigned int ipsurxNp2npColorLoc : 6; /* * [21:16]NP2NP头COLOR字段的起始位置。建议不修改默认值。 */ + unsigned int reserved1 : 2; /* * [23:22] */ + unsigned int ipsurxNp2npSbLoc : 6; /* * [29:24]NP2NP头SB字段的起始位置。建议不修改默认值。 */ + unsigned int reserved0 : 2; /* * [31:30]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_FIELD_LOC_U; + +/* ** + * Union name : IPSURX_NP2NP_TP_LOC + * @brief NP2NP头TP字段位置配置寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npTpLoc { + struct tagStIpsurxNp2npTpLoc { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6]reserved. */ + unsigned int ipsurxNp2npTpLoc : 6; /* * [5:0]NP2NP头TP字段的起始位置。建议不修改默认值。 */ +#else + unsigned int ipsurxNp2npTpLoc : 6; /* * [5:0]NP2NP头TP字段的起始位置。建议不修改默认值。 */ + unsigned int reserved : 26; /* * [31:6]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_TP_LOC_U; + +/* ** + * Union name : IPSURX_NP2NP_MCTP_SEL + * @brief NP2NP报文，多播TP映射选择寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npMctpSel { + struct tagStIpsurxNp2npMctpSel { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1] */ + unsigned int ipsurxNp2npMctpSel : 1; /* * [0:0]NP2NP报文，多播TP映射选择。1'b0：根据FIC模块的输入UC/MC + * FLAG来映射多播报文TP。1'b1：根据NP2NP头里的UC/MC + * FLAG来映射多播报文TP。建议不修改默认值。 + */ +#else + unsigned int ipsurxNp2npMctpSel : 1; /* * [0:0]NP2NP报文，多播TP映射选择。1'b0：根据FIC模块的输入UC/MC + * FLAG来映射多播报文TP。1'b1：根据NP2NP头里的UC/MC + * FLAG来映射多播报文TP。建议不修改默认值。 + */ + unsigned int reserved : 31; /* * [31:1] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_MCTP_SEL_U; + +/* ** + * Union name : IPSURX_NP2NP_HLEN + * @brief NP2NP头长度配置寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npHlen { + struct tagStIpsurxNp2npHlen { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29] */ + unsigned int ipsurxNp2npFhl3Hlen : 5; /* * [28:24]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxNp2npFhl2Hlen : 5; /* * [20:16]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved2 : 3; /* * [15:13] */ + unsigned int ipsurxNp2npFhl1Hlen : 5; /* * [12:8]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxNp2npFhl0Hlen : 5; /* * [4:0]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ +#else + unsigned int ipsurxNp2npFhl0Hlen : 5; /* * [4:0]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxNp2npFhl1Hlen : 5; /* * [12:8]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved2 : 3; /* * [15:13] */ + unsigned int ipsurxNp2npFhl2Hlen : 5; /* * [20:16]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxNp2npFhl3Hlen : 5; /* * [28:24]FHL值为3时的NP2NP + HDR长度。有效值为0x0A，0x0E，0x12或者0x16。建议不修改默认值。 */ + unsigned int reserved0 : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_HLEN_U; + +/* ** + * Union name : IPSURX_NP2NP_QIDX_PRI1 + * @brief NP2NP头QINDEX优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npQidxPri1 { + struct tagStIpsurxNp2npQidxPri1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxQidxV15Pri : 3; /* * [30:28]NP2NP头 + QINDEX字段值15对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxQidxV14Pri : 3; /* * [26:24]NP2NP头 + QINDEX字段值14对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxQidxV13Pri : 3; /* * [22:20]NP2NP头 + QINDEX字段值13对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxQidxV12Pri : 3; /* * [18:16]NP2NP头 + QINDEX字段值12对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxQidxV11Pri : 3; /* * [14:12]NP2NP头 + QINDEX字段值11对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxQidxV10Pri : 3; /* * [10:8]NP2NP头 + QINDEX字段值10对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxQidxV9Pri : 3; /* * [6:4]NP2NP头 + QINDEX字段值9对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxQidxV8Pri : 3; /* * [2:0]NP2NP头 + QINDEX字段值8对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ +#else + unsigned int ipsurxQidxV8Pri : 3; /* * [2:0]NP2NP头 + QINDEX字段值8对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxQidxV9Pri : 3; /* * [6:4]NP2NP头 + QINDEX字段值9对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxQidxV10Pri : 3; /* * [10:8]NP2NP头 + QINDEX字段值10对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxQidxV11Pri : 3; /* * [14:12]NP2NP头 + QINDEX字段值11对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxQidxV12Pri : 3; /* * [18:16]NP2NP头 + QINDEX字段值12对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxQidxV13Pri : 3; /* * [22:20]NP2NP头 + QINDEX字段值13对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxQidxV14Pri : 3; /* * [26:24]NP2NP头 + QINDEX字段值14对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxQidxV15Pri : 3; /* * [30:28]NP2NP头 + QINDEX字段值15对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_QIDX_PRI1_U; + +/* ** + * Union name : IPSURX_NP2NP_QIDX_PRI0 + * @brief NP2NP头QINDEX优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxNp2npQidxPri0 { + struct tagStIpsurxNp2npQidxPri0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int ipsurxQidxV7Pri : 3; /* * [30:28]NP2NP头 + QINDEX字段值7对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxQidxV6Pri : 3; /* * [26:24]NP2NP头 + QINDEX字段值6对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxQidxV5Pri : 3; /* * [22:20]NP2NP头 + QINDEX字段值5对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxQidxV4Pri : 3; /* * [18:16]NP2NP头 + QINDEX字段值4对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxQidxV3Pri : 3; /* * [14:12]NP2NP头 + QINDEX字段值3对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxQidxV2Pri : 3; /* * [10:8]NP2NP头 + QINDEX字段值2对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxQidxV1Pri : 3; /* * [6:4]NP2NP头 + QINDEX字段值1对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxQidxV0Pri : 3; /* * [2:0]NP2NP头 + QINDEX字段值0对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ +#else + unsigned int ipsurxQidxV0Pri : 3; /* * [2:0]NP2NP头 + QINDEX字段值0对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxQidxV1Pri : 3; /* * [6:4]NP2NP头 + QINDEX字段值1对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxQidxV2Pri : 3; /* * [10:8]NP2NP头 + QINDEX字段值2对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxQidxV3Pri : 3; /* * [14:12]NP2NP头 + QINDEX字段值3对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxQidxV4Pri : 3; /* * [18:16]NP2NP头 + QINDEX字段值4对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxQidxV5Pri : 3; /* * [22:20]NP2NP头 + QINDEX字段值5对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxQidxV6Pri : 3; /* * [26:24]NP2NP头 + QINDEX字段值6对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxQidxV7Pri : 3; /* * [30:28]NP2NP头 + QINDEX字段值7对应优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NP2NP_QIDX_PRI0_U; + +/* ** + * Union name : IPSURX_HG2HDR_CFG + * @brief HG2 header配置寄存器 + * Description: + */ +typedef union tagUnIpsurxHg2hdrCfg { + struct tagStIpsurxHg2hdrCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 11; /* * [31:21]reserved. */ + unsigned int ipsurxHg2hdrEhv1Hlen : 5; /* * [20:16]EHV比特值为1时的HG2 + HDR长度。有效值为：0x10或者0x14。建议不修改默认值。 */ + unsigned int reserved1 : 3; /* * [15:13] */ + unsigned int ipsurxHg2hdrEhv0Hlen : 5; /* * [12:8]EHV比特值为0时的HG2 + HDR长度。有效值为：0x10或者0x14。建议不修改默认值。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxHg2hdrEhvLoc : 7; /* * [6:0]EHV比特的位置。建议不修改默认值。有效值范围:0x30 - 0x4F。 */ +#else + unsigned int ipsurxHg2hdrEhvLoc : 7; /* * [6:0]EHV比特的位置。建议不修改默认值。有效值范围:0x30 - 0x4F。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxHg2hdrEhv0Hlen : 5; /* * [12:8]EHV比特值为0时的HG2 + HDR长度。有效值为：0x10或者0x14。建议不修改默认值。 */ + unsigned int reserved1 : 3; /* * [15:13] */ + unsigned int ipsurxHg2hdrEhv1Hlen : 5; /* * [20:16]EHV比特值为1时的HG2 + HDR长度。有效值为：0x10或者0x14。建议不修改默认值。 */ + unsigned int reserved0 : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_HG2HDR_CFG_U; + +/* ** + * Union name : IPSURX_EVTAG_TPID3 + * @brief ETAG/VNTAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxEvtagTpid3 { + struct tagStIpsurxEvtagTpid3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxEvtagTpid3 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ +#else + unsigned int ipsurxEvtagTpid3 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_EVTAG_TPID3_U; + +/* ** + * Union name : IPSURX_EVTAG_TPID2 + * @brief ETAG/VNTAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxEvtagTpid2 { + struct tagStIpsurxEvtagTpid2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxEvtagTpid2 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ +#else + unsigned int ipsurxEvtagTpid2 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_EVTAG_TPID2_U; + +/* ** + * Union name : IPSURX_EVTAG_TPID1 + * @brief ETAG/VNTAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxEvtagTpid1 { + struct tagStIpsurxEvtagTpid1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxEvtagTpid1 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ +#else + unsigned int ipsurxEvtagTpid1 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_EVTAG_TPID1_U; + +/* ** + * Union name : IPSURX_EVTAG_TPID0 + * @brief ETAG/VNTAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxEvtagTpid0 { + struct tagStIpsurxEvtagTpid0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxEvtagTpid0 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ +#else + unsigned int ipsurxEvtagTpid0 : 16; /* * [15:0]软件配置E-TAG/VN-TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_EVTAG_TPID0_U; + +/* ** + * Union name : IPSURX_SVLAN_TPID4 + * @brief SVLAN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxSvlanTpid4 { + struct tagStIpsurxSvlanTpid4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxSvlanTpid4 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ +#else + unsigned int ipsurxSvlanTpid4 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SVLAN_TPID4_U; + +/* ** + * Union name : IPSURX_SVLAN_TPID3 + * @brief SVLAN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxSvlanTpid3 { + struct tagStIpsurxSvlanTpid3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxSvlanTpid3 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ +#else + unsigned int ipsurxSvlanTpid3 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SVLAN_TPID3_U; + +/* ** + * Union name : IPSURX_SVLAN_TPID2 + * @brief SVLAN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxSvlanTpid2 { + struct tagStIpsurxSvlanTpid2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxSvlanTpid2 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ +#else + unsigned int ipsurxSvlanTpid2 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SVLAN_TPID2_U; + +/* ** + * Union name : IPSURX_SVLAN_TPID1 + * @brief SVLAN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxSvlanTpid1 { + struct tagStIpsurxSvlanTpid1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxSvlanTpid1 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ +#else + unsigned int ipsurxSvlanTpid1 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SVLAN_TPID1_U; + +/* ** + * Union name : IPSURX_SVLAN_TPID0 + * @brief SVLAN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxSvlanTpid0 { + struct tagStIpsurxSvlanTpid0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxSvlanTpid0 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ +#else + unsigned int ipsurxSvlanTpid0 : 16; /* * [15:0]软件配置SVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SVLAN_TPID0_U; + +/* ** + * Union name : IPSURX_CVLAN_TPID4 + * @brief CVLAN-TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCvlanTpid4 { + struct tagStIpsurxCvlanTpid4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCvlanTpid4 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ +#else + unsigned int ipsurxCvlanTpid4 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CVLAN_TPID4_U; + +/* ** + * Union name : IPSURX_CVLAN_TPID3 + * @brief CVLAN-TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCvlanTpid3 { + struct tagStIpsurxCvlanTpid3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCvlanTpid3 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ +#else + unsigned int ipsurxCvlanTpid3 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CVLAN_TPID3_U; + +/* ** + * Union name : IPSURX_CVLAN_TPID2 + * @brief CVLAN-TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCvlanTpid2 { + struct tagStIpsurxCvlanTpid2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCvlanTpid2 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ +#else + unsigned int ipsurxCvlanTpid2 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CVLAN_TPID2_U; + +/* ** + * Union name : IPSURX_CVLAN_TPID1 + * @brief CVLAN-TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCvlanTpid1 { + struct tagStIpsurxCvlanTpid1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCvlanTpid1 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ +#else + unsigned int ipsurxCvlanTpid1 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CVLAN_TPID1_U; + +/* ** + * Union name : IPSURX_CVLAN_TPID0 + * @brief CVLAN-TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCvlanTpid0 { + struct tagStIpsurxCvlanTpid0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCvlanTpid0 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ +#else + unsigned int ipsurxCvlanTpid0 : 16; /* * [15:0]软件配置CVLAN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CVLAN_TPID0_U; + +/* ** + * Union name : IPSURX_P8021_PRI + * @brief 802.1优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxP8021Pri { + struct tagStIpsurxP8021Pri { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxP8021V7Pri : 3; /* * [30:28]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为7的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxP8021V6Pri : 3; /* * [26:24]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为6的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxP8021V5Pri : 3; /* * [22:20]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为5的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxP8021V4Pri : 3; /* * [18:16]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为4的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxP8021V3Pri : 3; /* * [14:12]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为3的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxP8021V2Pri : 3; /* * [10:8]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为2的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxP8021V1Pri : 3; /* * [6:4]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为1的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxP8021V0Pri : 3; /* * [2:0]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为0的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxP8021V0Pri : 3; /* * [2:0]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为0的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxP8021V1Pri : 3; /* * [6:4]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为1的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxP8021V2Pri : 3; /* * [10:8]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为2的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxP8021V3Pri : 3; /* * [14:12]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为3的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxP8021V4Pri : 3; /* * [18:16]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为4的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxP8021V5Pri : 3; /* * [22:20]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为5的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxP8021V6Pri : 3; /* * [26:24]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为6的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxP8021V7Pri : 3; /* * [30:28]E-TAG，VLAN TAG等802.1 + TAG优先级字段值为7的优先级寄存器。3'b000，最高优先级；...3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_P8021_PRI_U; + +/* ** + * Union name : IPSURX_CNTAG_TPID1 + * @brief CN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCntagTpid1 { + struct tagStIpsurxCntagTpid1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCntagTpid1 : 16; /* * [15:0]软件配置CN TAG TPID。 */ +#else + unsigned int ipsurxCntagTpid1 : 16; /* * [15:0]软件配置CN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CNTAG_TPID1_U; + +/* ** + * Union name : IPSURX_CNTAG_TPID0 + * @brief CN TAG TPID配置寄存器 + * Description: + */ +typedef union tagUnIpsurxCntagTpid0 { + struct tagStIpsurxCntagTpid0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxCntagTpid0 : 16; /* * [15:0]软件配置CN TAG TPID。 */ +#else + unsigned int ipsurxCntagTpid0 : 16; /* * [15:0]软件配置CN TAG TPID。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CNTAG_TPID0_U; + +/* ** + * Union name : IPSURX_8023_MAX_LEN + * @brief 802.3最大长度配置寄存器 + * Description: + */ +typedef union tagUnIpsurx8023MaxLen { + struct tagStIpsurx8023MaxLen { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 21; /* * [31:11] */ + unsigned int ipsurx8023MaxLen : 11; /* * [10:0]802.3封装的以太网帧，LENGTH域最大值。建议不修改默认值。 */ +#else + unsigned int ipsurx8023MaxLen : 11; /* * [10:0]802.3封装的以太网帧，LENGTH域最大值。建议不修改默认值。 */ + unsigned int reserved : 21; /* * [31:11] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_8023_MAX_LEN_U; + +/* ** + * Union name : IPSURX_8023_JUMBO_CFG + * @brief 802.3Jumbo帧配置寄存器 + * Description: + */ +typedef union tagUnIpsurx8023JumboCfg { + struct tagStIpsurx8023JumboCfg { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17]reserved. */ + unsigned int ipsurx8023JumboChkEn : 1; /* * [16:16]1'b1：使能802.3 JUMBO帧检测；1'b0：不使能802.3 JUMBO帧检测。 + */ + unsigned int ipsurx8023JumboTpid : 16; /* * [15:0]802.3封装的JUMBO帧TPID。建议不修改默认值。 */ +#else + unsigned int ipsurx8023JumboTpid : 16; /* * [15:0]802.3封装的JUMBO帧TPID。建议不修改默认值。 */ + unsigned int ipsurx8023JumboChkEn : 1; /* * [16:16]1'b1：使能802.3 JUMBO帧检测；1'b0：不使能802.3 JUMBO帧检测。 + */ + unsigned int reserved : 15; /* * [31:17]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_8023_JUMBO_CFG_U; + +/* ** + * Union name : IPSURX_L2_DMAC_CHK_EN + * @brief L2报文DMAC检测使能配置寄存器 + * Description: + */ +typedef union tagUnIpsurxL2DmacChkEn { + struct tagStIpsurxL2DmacChkEn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int + ipsurxPauseDmacChkEn : 1; /* * + * [3:3]Pause帧DMAC检测使能：1'b1：PAUSE报文识别需要检测DMAC地址01-80-C2-00-00-01；1'b0：PAUSE报文识别不检测DMAC地址。 + */ + unsigned int ipsurxPfcDmacChkEn : 1; /* * + [2:2]PFC帧DMAC检测使能：1'b1：PFC报文识别需要检测DMAC地址01-80-C2-00-00-01；1'b0：PFC报文识别不检测DMAC地址。 + */ + unsigned int ipsurxLacpDmacChkEn : 1; /* * + [1:1]LACP帧DMAC检测使能：1'b1：LACP报文识别需要检测DMAC地址01-80-C2-00-00-02；1'b0：LACP报文识别不检测DMAC地址。 + */ + unsigned int + ipsurxLldpDmacChkEn : 1; /* * + * [0:0]LLDP/CDCP报文DMAC检测使能：1'b1：LLDP/CDCP报文识别需要检测DMAC地址，DMAC地址为01-80-C2-00-00-{00,03,0E}之一；1'b0：LLDP/CDCP报文识别不检测DMAC地址。 + */ +#else + unsigned int + ipsurxLldpDmacChkEn : 1; /* * + * [0:0]LLDP/CDCP报文DMAC检测使能：1'b1：LLDP/CDCP报文识别需要检测DMAC地址，DMAC地址为01-80-C2-00-00-{00,03,0E}之一；1'b0：LLDP/CDCP报文识别不检测DMAC地址。 + */ + unsigned int ipsurxLacpDmacChkEn : 1; /* * + [1:1]LACP帧DMAC检测使能：1'b1：LACP报文识别需要检测DMAC地址01-80-C2-00-00-02；1'b0：LACP报文识别不检测DMAC地址。 + */ + unsigned int ipsurxPfcDmacChkEn : 1; /* * + [2:2]PFC帧DMAC检测使能：1'b1：PFC报文识别需要检测DMAC地址01-80-C2-00-00-01；1'b0：PFC报文识别不检测DMAC地址。 + */ + unsigned int + ipsurxPauseDmacChkEn : 1; /* * + * [3:3]Pause帧DMAC检测使能：1'b1：PAUSE报文识别需要检测DMAC地址01-80-C2-00-00-01；1'b0：PAUSE报文识别不检测DMAC地址。 + */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_L2_DMAC_CHK_EN_U; + +/* ** + * Union name : IPSURX_FIP_TO_UP_EN + * @brief IPSURX FIP控制寄存器 + * Description: + */ +typedef union tagUnIpsurxFipToUpEn { + struct tagStIpsurxFipToUpEn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved. */ + unsigned int ipsurxFipToUpEn : 1; /* * [0:0]1'b0：FIP报文转发到TILE；1'b1：FIP Protocol + Code不等于0x2的报文转发到UP。 */ +#else + unsigned int ipsurxFipToUpEn : 1; /* * [0:0]1'b0：FIP报文转发到TILE；1'b1：FIP Protocol + Code不等于0x2的报文转发到UP。 */ + unsigned int reserved : 31; /* * [31:1]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIP_TO_UP_EN_U; + +/* ** + * Union name : IPSURX_RTN_TS + * @brief 回传时戳报文寄存器 + * Description: + */ +typedef union tagUnIpsurxRtnTs { + struct tagStIpsurxRtnTs { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17]reserved. */ + unsigned int + ipsurxRtnTsEn : 1; /* * [16:16]1'b1：用户定义回传时戳报文类型有效。1'b0：用户定义回传时戳报文类型无效。 */ + unsigned int ipsurxRtnTs : 16; /* * + * [15:0]用户定义回传时戳报文类型。该寄存器的值必需与MAG的寄存器MAG_RXDP_RTS_TYPE的高16比特的值保持一致。其值要求大于0x600，并且不和知名的Ethernet + * TYPE类型值冲突。 + */ +#else + unsigned int ipsurxRtnTs : 16; /* * + * [15:0]用户定义回传时戳报文类型。该寄存器的值必需与MAG的寄存器MAG_RXDP_RTS_TYPE的高16比特的值保持一致。其值要求大于0x600，并且不和知名的Ethernet + * TYPE类型值冲突。 + */ + unsigned int + ipsurxRtnTsEn : 1; /* * [16:16]1'b1：用户定义回传时戳报文类型有效。1'b0：用户定义回传时戳报文类型无效。 */ + unsigned int reserved : 15; /* * [31:17]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RTN_TS_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI7 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri7 { + struct tagStIpsurxIpv4DscpPri7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV63Pri : 3; /* * [30:28]IPv4 + DSCP字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV62Pri : 3; /* * [26:24]IPv4 + DSCP字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV61Pri : 3; /* * [22:20]IPv4 + DSCP字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV60Pri : 3; /* * [18:16]IPv4 + DSCP字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV59Pri : 3; /* * [14:12]IPv4 + DSCP字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV58Pri : 3; /* * [10:8]IPv4 + DSCP字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV57Pri : 3; /* * [6:4]IPv4 + DSCP字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV56Pri : 3; /* * [2:0]IPv4 + DSCP字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV56Pri : 3; /* * [2:0]IPv4 + DSCP字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV57Pri : 3; /* * [6:4]IPv4 + DSCP字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV58Pri : 3; /* * [10:8]IPv4 + DSCP字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV59Pri : 3; /* * [14:12]IPv4 + DSCP字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV60Pri : 3; /* * [18:16]IPv4 + DSCP字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV61Pri : 3; /* * [22:20]IPv4 + DSCP字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV62Pri : 3; /* * [26:24]IPv4 + DSCP字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV63Pri : 3; /* * [30:28]IPv4 + DSCP字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI7_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI6 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri6 { + struct tagStIpsurxIpv4DscpPri6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV55Pri : 3; /* * [30:28]IPv4 + DSCP字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV54Pri : 3; /* * [26:24]IPv4 + DSCP字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV53Pri : 3; /* * [22:20]IPv4 + DSCP字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV52Pri : 3; /* * [18:16]IPv4 + DSCP字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV51Pri : 3; /* * [14:12]IPv4 + DSCP字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV50Pri : 3; /* * [10:8]IPv4 + DSCP字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV49Pri : 3; /* * [6:4]IPv4 + DSCP字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV48Pri : 3; /* * [2:0]IPv4 + DSCP字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV48Pri : 3; /* * [2:0]IPv4 + DSCP字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV49Pri : 3; /* * [6:4]IPv4 + DSCP字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV50Pri : 3; /* * [10:8]IPv4 + DSCP字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV51Pri : 3; /* * [14:12]IPv4 + DSCP字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV52Pri : 3; /* * [18:16]IPv4 + DSCP字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV53Pri : 3; /* * [22:20]IPv4 + DSCP字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV54Pri : 3; /* * [26:24]IPv4 + DSCP字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV55Pri : 3; /* * [30:28]IPv4 + DSCP字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI6_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI5 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri5 { + struct tagStIpsurxIpv4DscpPri5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV47Pri : 3; /* * [30:28]IPv4 + DSCP字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV46Pri : 3; /* * [26:24]IPv4 + DSCP字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV45Pri : 3; /* * [22:20]IPv4 + DSCP字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV44Pri : 3; /* * [18:16]IPv4 + DSCP字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV43Pri : 3; /* * [14:12]IPv4 + DSCP字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV42Pri : 3; /* * [10:8]IPv4 + DSCP字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV41Pri : 3; /* * [6:4]IPv4 + DSCP字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV40Pri : 3; /* * [2:0]IPv4 + DSCP字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV40Pri : 3; /* * [2:0]IPv4 + DSCP字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV41Pri : 3; /* * [6:4]IPv4 + DSCP字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV42Pri : 3; /* * [10:8]IPv4 + DSCP字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV43Pri : 3; /* * [14:12]IPv4 + DSCP字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV44Pri : 3; /* * [18:16]IPv4 + DSCP字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV45Pri : 3; /* * [22:20]IPv4 + DSCP字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV46Pri : 3; /* * [26:24]IPv4 + DSCP字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV47Pri : 3; /* * [30:28]IPv4 + DSCP字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI5_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI4 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri4 { + struct tagStIpsurxIpv4DscpPri4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV39Pri : 3; /* * [30:28]IPv4 + DSCP字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV38Pri : 3; /* * [26:24]IPv4 + DSCP字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV37Pri : 3; /* * [22:20]IPv4 + DSCP字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV36Pri : 3; /* * [18:16]IPv4 + DSCP字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV35Pri : 3; /* * [14:12]IPv4 + DSCP字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV34Pri : 3; /* * [10:8]IPv4 + DSCP字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV33Pri : 3; /* * [6:4]IPv4 + DSCP字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV32Pri : 3; /* * [2:0]IPv4 + DSCP字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV32Pri : 3; /* * [2:0]IPv4 + DSCP字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV33Pri : 3; /* * [6:4]IPv4 + DSCP字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV34Pri : 3; /* * [10:8]IPv4 + DSCP字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV35Pri : 3; /* * [14:12]IPv4 + DSCP字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV36Pri : 3; /* * [18:16]IPv4 + DSCP字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV37Pri : 3; /* * [22:20]IPv4 + DSCP字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV38Pri : 3; /* * [26:24]IPv4 + DSCP字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV39Pri : 3; /* * [30:28]IPv4 + DSCP字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI4_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI3 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri3 { + struct tagStIpsurxIpv4DscpPri3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV31Pri : 3; /* * [30:28]IPv4 + DSCP字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV30Pri : 3; /* * [26:24]IPv4 + DSCP字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV29Pri : 3; /* * [22:20]IPv4 + DSCP字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV28Pri : 3; /* * [18:16]IPv4 + DSCP字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV27Pri : 3; /* * [14:12]IPv4 + DSCP字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV26Pri : 3; /* * [10:8]IPv4 + DSCP字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV25Pri : 3; /* * [6:4]IPv4 + DSCP字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV24Pri : 3; /* * [2:0]IPv4 + DSCP字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV24Pri : 3; /* * [2:0]IPv4 + DSCP字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV25Pri : 3; /* * [6:4]IPv4 + DSCP字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV26Pri : 3; /* * [10:8]IPv4 + DSCP字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV27Pri : 3; /* * [14:12]IPv4 + DSCP字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV28Pri : 3; /* * [18:16]IPv4 + DSCP字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV29Pri : 3; /* * [22:20]IPv4 + DSCP字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV30Pri : 3; /* * [26:24]IPv4 + DSCP字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV31Pri : 3; /* * [30:28]IPv4 + DSCP字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI3_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI2 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri2 { + struct tagStIpsurxIpv4DscpPri2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV23Pri : 3; /* * [30:28]IPv4 + DSCP字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV22Pri : 3; /* * [26:24]IPv4 + DSCP字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV21Pri : 3; /* * [22:20]IPv4 + DSCP字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV20Pri : 3; /* * [18:16]IPv4 + DSCP字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV19Pri : 3; /* * [14:12]IPv4 + DSCP字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV18Pri : 3; /* * [10:8]IPv4 + DSCP字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV17Pri : 3; /* * [6:4]IPv4 + DSCP字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV16Pri : 3; /* * [2:0]IPv4 + DSCP字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv4DscpV16Pri : 3; /* * [2:0]IPv4 + DSCP字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv4DscpV17Pri : 3; /* * [6:4]IPv4 + DSCP字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV18Pri : 3; /* * [10:8]IPv4 + DSCP字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV19Pri : 3; /* * [14:12]IPv4 + DSCP字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV20Pri : 3; /* * [18:16]IPv4 + DSCP字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV21Pri : 3; /* * [22:20]IPv4 + DSCP字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV22Pri : 3; /* * [26:24]IPv4 + DSCP字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV23Pri : 3; /* * [30:28]IPv4 + DSCP字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI2_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI1 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri1 { + struct tagStIpsurxIpv4DscpPri1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv4DscpV15Pri : 3; /* * [30:28]IPv4 + DSCP字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV14Pri : 3; /* * [26:24]IPv4 + DSCP字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV13Pri : 3; /* * [22:20]IPv4 + DSCP字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV12Pri : 3; /* * [18:16]IPv4 + DSCP字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV11Pri : 3; /* * [14:12]IPv4 + DSCP字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV10Pri : 3; /* * [10:8]IPv4 + DSCP字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv4DscpV9Pri : 3; /* * [6:4]IPv4 + DSCP字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv4DscpV8Pri : 3; /* * [2:0]IPv4 + DSCP字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxIpv4DscpV8Pri : 3; /* * [2:0]IPv4 + DSCP字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv4DscpV9Pri : 3; /* * [6:4]IPv4 + DSCP字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv4DscpV10Pri : 3; /* * [10:8]IPv4 + DSCP字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv4DscpV11Pri : 3; /* * [14:12]IPv4 + DSCP字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv4DscpV12Pri : 3; /* * [18:16]IPv4 + DSCP字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv4DscpV13Pri : 3; /* * [22:20]IPv4 + DSCP字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv4DscpV14Pri : 3; /* * [26:24]IPv4 + DSCP字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv4DscpV15Pri : 3; /* * [30:28]IPv4 + DSCP字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI1_U; + +/* ** + * Union name : IPSURX_IPV4_DSCP_PRI0 + * @brief IPv4 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv4DscpPri0 { + struct tagStIpsurxIpv4DscpPri0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int ipsurxIpv4DscpV7Pri : 3; /* * [30:28]IPv4 + DSCP字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxIpv4DscpV6Pri : 3; /* * [26:24]IPv4 + DSCP字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxIpv4DscpV5Pri : 3; /* * [22:20]IPv4 + DSCP字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxIpv4DscpV4Pri : 3; /* * [18:16]IPv4 + DSCP字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxIpv4DscpV3Pri : 3; /* * [14:12]IPv4 + DSCP字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxIpv4DscpV2Pri : 3; /* * [10:8]IPv4 + DSCP字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv4DscpV1Pri : 3; /* * [6:4]IPv4 + DSCP字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv4DscpV0Pri : 3; /* * [2:0]IPv4 + DSCP字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxIpv4DscpV0Pri : 3; /* * [2:0]IPv4 + DSCP字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv4DscpV1Pri : 3; /* * [6:4]IPv4 + DSCP字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv4DscpV2Pri : 3; /* * [10:8]IPv4 + DSCP字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxIpv4DscpV3Pri : 3; /* * [14:12]IPv4 + DSCP字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxIpv4DscpV4Pri : 3; /* * [18:16]IPv4 + DSCP字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxIpv4DscpV5Pri : 3; /* * [22:20]IPv4 + DSCP字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxIpv4DscpV6Pri : 3; /* * [26:24]IPv4 + DSCP字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxIpv4DscpV7Pri : 3; /* * [30:28]IPv4 + DSCP字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DSCP_PRI0_U; + +/* ** + * Union name : IPSURX_IGMPV4_DIP_CHK_EN + * @brief IGMPv4 DIP检测控制寄存器 + * Description: + */ +typedef union tagUnIpsurxIgmpv4DipChkEn { + struct tagStIpsurxIgmpv4DipChkEn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved. */ + unsigned int ipsurxIgmpv4DipChkEn : 1; /* * + * [0:0]1'b0：不检测IGMPv4报文的DIP范围；1'b1：检测IGMPv4报文的DIP范围。 + */ +#else + unsigned int ipsurxIgmpv4DipChkEn : 1; /* * + * [0:0]1'b0：不检测IGMPv4报文的DIP范围；1'b1：检测IGMPv4报文的DIP范围。 + */ + unsigned int reserved : 31; /* * [31:1]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IGMPV4_DIP_CHK_EN_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI7 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri7 { + struct tagStIpsurxIpv6DscpPri7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV63Pri : 3; /* * [30:28]IPv6 + DSCP字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV62Pri : 3; /* * [26:24]IPv6 + DSCP字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV61Pri : 3; /* * [22:20]IPv6 + DSCP字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV60Pri : 3; /* * [18:16]IPv6 + DSCP字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV59Pri : 3; /* * [14:12]IPv6 + DSCP字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV58Pri : 3; /* * [10:8]IPv6 + DSCP字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV57Pri : 3; /* * [6:4]IPv6 + DSCP字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV56Pri : 3; /* * [2:0]IPv6 + DSCP字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV56Pri : 3; /* * [2:0]IPv6 + DSCP字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV57Pri : 3; /* * [6:4]IPv6 + DSCP字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV58Pri : 3; /* * [10:8]IPv6 + DSCP字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV59Pri : 3; /* * [14:12]IPv6 + DSCP字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV60Pri : 3; /* * [18:16]IPv6 + DSCP字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV61Pri : 3; /* * [22:20]IPv6 + DSCP字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV62Pri : 3; /* * [26:24]IPv6 + DSCP字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV63Pri : 3; /* * [30:28]IPv6 + DSCP字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI7_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI6 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri6 { + struct tagStIpsurxIpv6DscpPri6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV55Pri : 3; /* * [30:28]IPv6 + DSCP字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV54Pri : 3; /* * [26:24]IPv6 + DSCP字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV53Pri : 3; /* * [22:20]IPv6 + DSCP字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV52Pri : 3; /* * [18:16]IPv6 + DSCP字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV51Pri : 3; /* * [14:12]IPv6 + DSCP字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV50Pri : 3; /* * [10:8]IPv6 + DSCP字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV49Pri : 3; /* * [6:4]IPv6 + DSCP字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV48Pri : 3; /* * [2:0]IPv6 + DSCP字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV48Pri : 3; /* * [2:0]IPv6 + DSCP字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV49Pri : 3; /* * [6:4]IPv6 + DSCP字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV50Pri : 3; /* * [10:8]IPv6 + DSCP字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV51Pri : 3; /* * [14:12]IPv6 + DSCP字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV52Pri : 3; /* * [18:16]IPv6 + DSCP字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV53Pri : 3; /* * [22:20]IPv6 + DSCP字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV54Pri : 3; /* * [26:24]IPv6 + DSCP字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV55Pri : 3; /* * [30:28]IPv6 + DSCP字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI6_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI5 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri5 { + struct tagStIpsurxIpv6DscpPri5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV47Pri : 3; /* * [30:28]IPv6 + DSCP字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV46Pri : 3; /* * [26:24]IPv6 + DSCP字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV45Pri : 3; /* * [22:20]IPv6 + DSCP字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV44Pri : 3; /* * [18:16]IPv6 + DSCP字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV43Pri : 3; /* * [14:12]IPv6 + DSCP字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV42Pri : 3; /* * [10:8]IPv6 + DSCP字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV41Pri : 3; /* * [6:4]IPv6 + DSCP字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV40Pri : 3; /* * [2:0]IPv6 + DSCP字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV40Pri : 3; /* * [2:0]IPv6 + DSCP字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV41Pri : 3; /* * [6:4]IPv6 + DSCP字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV42Pri : 3; /* * [10:8]IPv6 + DSCP字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV43Pri : 3; /* * [14:12]IPv6 + DSCP字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV44Pri : 3; /* * [18:16]IPv6 + DSCP字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV45Pri : 3; /* * [22:20]IPv6 + DSCP字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV46Pri : 3; /* * [26:24]IPv6 + DSCP字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV47Pri : 3; /* * [30:28]IPv6 + DSCP字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI5_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI4 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri4 { + struct tagStIpsurxIpv6DscpPri4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV39Pri : 3; /* * [30:28]IPv6 + DSCP字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV38Pri : 3; /* * [26:24]IPv6 + DSCP字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV37Pri : 3; /* * [22:20]IPv6 + DSCP字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV36Pri : 3; /* * [18:16]IPv6 + DSCP字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV35Pri : 3; /* * [14:12]IPv6 + DSCP字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV34Pri : 3; /* * [10:8]IPv6 + DSCP字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV33Pri : 3; /* * [6:4]IPv6 + DSCP字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV32Pri : 3; /* * [2:0]IPv6 + DSCP字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV32Pri : 3; /* * [2:0]IPv6 + DSCP字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV33Pri : 3; /* * [6:4]IPv6 + DSCP字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV34Pri : 3; /* * [10:8]IPv6 + DSCP字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV35Pri : 3; /* * [14:12]IPv6 + DSCP字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV36Pri : 3; /* * [18:16]IPv6 + DSCP字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV37Pri : 3; /* * [22:20]IPv6 + DSCP字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV38Pri : 3; /* * [26:24]IPv6 + DSCP字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV39Pri : 3; /* * [30:28]IPv6 + DSCP字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI4_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI3 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri3 { + struct tagStIpsurxIpv6DscpPri3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV31Pri : 3; /* * [30:28]IPv6 + DSCP字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV30Pri : 3; /* * [26:24]IPv6 + DSCP字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV29Pri : 3; /* * [22:20]IPv6 + DSCP字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV28Pri : 3; /* * [18:16]IPv6 + DSCP字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV27Pri : 3; /* * [14:12]IPv6 + DSCP字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV26Pri : 3; /* * [10:8]IPv6 + DSCP字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV25Pri : 3; /* * [6:4]IPv6 + DSCP字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV24Pri : 3; /* * [2:0]IPv6 + DSCP字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV24Pri : 3; /* * [2:0]IPv6 + DSCP字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV25Pri : 3; /* * [6:4]IPv6 + DSCP字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV26Pri : 3; /* * [10:8]IPv6 + DSCP字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV27Pri : 3; /* * [14:12]IPv6 + DSCP字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV28Pri : 3; /* * [18:16]IPv6 + DSCP字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV29Pri : 3; /* * [22:20]IPv6 + DSCP字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV30Pri : 3; /* * [26:24]IPv6 + DSCP字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV31Pri : 3; /* * [30:28]IPv6 + DSCP字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI3_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI2 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri2 { + struct tagStIpsurxIpv6DscpPri2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV23Pri : 3; /* * [30:28]IPv6 + DSCP字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV22Pri : 3; /* * [26:24]IPv6 + DSCP字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV21Pri : 3; /* * [22:20]IPv6 + DSCP字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV20Pri : 3; /* * [18:16]IPv6 + DSCP字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV19Pri : 3; /* * [14:12]IPv6 + DSCP字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV18Pri : 3; /* * [10:8]IPv6 + DSCP字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV17Pri : 3; /* * [6:4]IPv6 + DSCP字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV16Pri : 3; /* * [2:0]IPv6 + DSCP字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxIpv6DscpV16Pri : 3; /* * [2:0]IPv6 + DSCP字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxIpv6DscpV17Pri : 3; /* * [6:4]IPv6 + DSCP字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV18Pri : 3; /* * [10:8]IPv6 + DSCP字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV19Pri : 3; /* * [14:12]IPv6 + DSCP字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV20Pri : 3; /* * [18:16]IPv6 + DSCP字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV21Pri : 3; /* * [22:20]IPv6 + DSCP字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV22Pri : 3; /* * [26:24]IPv6 + DSCP字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV23Pri : 3; /* * [30:28]IPv6 + DSCP字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI2_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI1 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri1 { + struct tagStIpsurxIpv6DscpPri1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxIpv6DscpV15Pri : 3; /* * [30:28]IPv6 + DSCP字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV14Pri : 3; /* * [26:24]IPv6 + DSCP字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV13Pri : 3; /* * [22:20]IPv6 + DSCP字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV12Pri : 3; /* * [18:16]IPv6 + DSCP字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV11Pri : 3; /* * [14:12]IPv6 + DSCP字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV10Pri : 3; /* * [10:8]IPv6 + DSCP字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv6DscpV9Pri : 3; /* * [6:4]IPv6 + DSCP字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv6DscpV8Pri : 3; /* * [2:0]IPv6 + DSCP字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxIpv6DscpV8Pri : 3; /* * [2:0]IPv6 + DSCP字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv6DscpV9Pri : 3; /* * [6:4]IPv6 + DSCP字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxIpv6DscpV10Pri : 3; /* * [10:8]IPv6 + DSCP字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxIpv6DscpV11Pri : 3; /* * [14:12]IPv6 + DSCP字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxIpv6DscpV12Pri : 3; /* * [18:16]IPv6 + DSCP字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxIpv6DscpV13Pri : 3; /* * [22:20]IPv6 + DSCP字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxIpv6DscpV14Pri : 3; /* * [26:24]IPv6 + DSCP字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxIpv6DscpV15Pri : 3; /* * [30:28]IPv6 + DSCP字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI1_U; + +/* ** + * Union name : IPSURX_IPV6_DSCP_PRI0 + * @brief IPv6 DSCP优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6DscpPri0 { + struct tagStIpsurxIpv6DscpPri0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int ipsurxIpv6DscpV7Pri : 3; /* * [30:28]IPv6 + DSCP字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxIpv6DscpV6Pri : 3; /* * [26:24]IPv6 + DSCP字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxIpv6DscpV5Pri : 3; /* * [22:20]IPv6 + DSCP字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxIpv6DscpV4Pri : 3; /* * [18:16]IPv6 + DSCP字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxIpv6DscpV3Pri : 3; /* * [14:12]IPv6 + DSCP字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxIpv6DscpV2Pri : 3; /* * [10:8]IPv6 + DSCP字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv6DscpV1Pri : 3; /* * [6:4]IPv6 + DSCP字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv6DscpV0Pri : 3; /* * [2:0]IPv6 + DSCP字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxIpv6DscpV0Pri : 3; /* * [2:0]IPv6 + DSCP字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxIpv6DscpV1Pri : 3; /* * [6:4]IPv6 + DSCP字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxIpv6DscpV2Pri : 3; /* * [10:8]IPv6 + DSCP字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxIpv6DscpV3Pri : 3; /* * [14:12]IPv6 + DSCP字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxIpv6DscpV4Pri : 3; /* * [18:16]IPv6 + DSCP字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxIpv6DscpV5Pri : 3; /* * [22:20]IPv6 + DSCP字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxIpv6DscpV6Pri : 3; /* * [26:24]IPv6 + DSCP字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxIpv6DscpV7Pri : 3; /* * [30:28]IPv6 + DSCP字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DSCP_PRI0_U; + +/* ** + * Union name : IPSURX_IPV6_SPEC_MC + * @brief IPv6指定多播寄存器 + * Description: + */ +typedef union tagUnIpsurxIpv6SpecMc { + struct tagStIpsurxIpv6SpecMc { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv6SpecMcastMask : 16; /* * [31:16]IPv6指定多播掩码。 */ + unsigned int ipsurxIpv6SpecMcast : 16; /* * [15:0]IPv6指定多播。 */ +#else + unsigned int ipsurxIpv6SpecMcast : 16; /* * [15:0]IPv6指定多播。 */ + unsigned int ipsurxIpv6SpecMcastMask : 16; /* * [31:16]IPv6指定多播掩码。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_SPEC_MC_U; + +/* ** + * Union name : IPSURX_VXLAN_DPORT + * @brief VXLAN目的UDP PORT号 + * Description: + */ +typedef union tagUnIpsurxVxlanDport { + struct tagStIpsurxVxlanDport { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxVxlanDport : 16; /* * [15:0]VXLAN目的UDP端口号 */ +#else + unsigned int ipsurxVxlanDport : 16; /* * [15:0]VXLAN目的UDP端口号 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_VXLAN_DPORT_U; + +/* ** + * Union name : IPSURX_ROCEV2_DPORT + * @brief RoCEV2目的UDP PORT号 + * Description: + */ +typedef union tagUnIpsurxRocev2Dport { + struct tagStIpsurxRocev2Dport { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxRocev2Dport : 16; /* * [15:0]RoCEV2目的UDP端口号 */ +#else + unsigned int ipsurxRocev2Dport : 16; /* * [15:0]RoCEV2目的UDP端口号 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV2_DPORT_U; + +/* ** + * Union name : IPSURX_TPT_CTRL + * @brief TCP PORT表控制寄存器 + * Description: + */ +typedef union tagUnIpsurxTptCtrl { + struct tagStIpsurxTptCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]保留 */ + unsigned int ipsurxTcpPortLkEn : 1; /* * [6:6]TCP DPORT表查找使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxTcpSampIterval : 6; /* * [5:0]控制TCP报文采样间隔，实际采样间隔为该值乘以64。可配值范围：6'd1 + - 6'd63。 */ +#else + unsigned int ipsurxTcpSampIterval : 6; /* * [5:0]控制TCP报文采样间隔，实际采样间隔为该值乘以64。可配值范围：6'd1 + - 6'd63。 */ + unsigned int ipsurxTcpPortLkEn : 1; /* * [6:6]TCP DPORT表查找使能。1'b0：禁止；1'b1：使能。 */ + unsigned int reserved : 25; /* * [31:7]保留 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TPT_CTRL_U; + +/* ** + * Union name : IPSURX_TPT_DROP_FOR_BUSY_CNT + * @brief TPT表项忙，丢弃反标TCP端口号计数器 + * Description: + */ +typedef union tagUnIpsurxTptDropForBusyCnt { + struct tagStIpsurxTptDropForBusyCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTptDropForBusyCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTptDropForBusyCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TPT_DROP_FOR_BUSY_CNT_U; + +/* ** + * Union name : IPSURX_DMAC_ZERO_CNT + * @brief 目的MAC为0错误报文计数器 + * Description: + */ +typedef union tagUnIpsurxDmacZeroCnt { + struct tagStIpsurxDmacZeroCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxDmacZeroCnt : 32; /* * [31:0]目的MAC为0的报文数量。 */ +#else + unsigned int ipsurxDmacZeroCnt : 32; /* * [31:0]目的MAC为0的报文数量。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_DMAC_ZERO_CNT_U; + +/* ** + * Union name : IPSURX_SMAC_ILGL_CNT + * @brief 源MAC错误报文计数器 + * Description: + */ +typedef union tagUnIpsurxSmacIlglCnt { + struct tagStIpsurxSmacIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxSmacIlglCnt : 32; /* * [31:0]源MAC错误的报文数量。 */ +#else + unsigned int ipsurxSmacIlglCnt : 32; /* * [31:0]源MAC错误的报文数量。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SMAC_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_DA_SA_EQUAL_CNT + * @brief 源目的MAC相等报文计数器 + * Description: + */ +typedef union tagUnIpsurxDaSaEqualCnt { + struct tagStIpsurxDaSaEqualCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxDaSaEqualCnt : 32; /* * [31:0]源目的MAC相等报文计数器。 */ +#else + unsigned int ipsurxDaSaEqualCnt : 32; /* * [31:0]源目的MAC相等报文计数器。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_DA_SA_EQUAL_CNT_U; + +/* ** + * Union name : IPSURX_ETH_LEN_ILGL_CNT + * @brief ETH_LEN_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxEthLenIlglCnt { + struct tagStIpsurxEthLenIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxEthLenIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxEthLenIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ETH_LEN_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ARP_POSI_ILGL_CNT + * @brief ARP_POSI_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxArpPosiIlglCnt { + struct tagStIpsurxArpPosiIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxArpPosiIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxArpPosiIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ARP_POSI_ILGL_CNT_U; + + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI7 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri7 { + struct tagStIpsurxFcCsctlPri7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV63Pri : 3; /* * [30:28]FC + CSCTL字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV62Pri : 3; /* * [26:24]FC + CSCTL字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV61Pri : 3; /* * [22:20]FC + CSCTL字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV60Pri : 3; /* * [18:16]FC + CSCTL字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV59Pri : 3; /* * [14:12]FC + CSCTL字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV58Pri : 3; /* * [10:8]FC + CSCTL字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV57Pri : 3; /* * [6:4]FC + CSCTL字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV56Pri : 3; /* * [2:0]FC + CSCTL字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV56Pri : 3; /* * [2:0]FC + CSCTL字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV57Pri : 3; /* * [6:4]FC + CSCTL字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV58Pri : 3; /* * [10:8]FC + CSCTL字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV59Pri : 3; /* * [14:12]FC + CSCTL字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV60Pri : 3; /* * [18:16]FC + CSCTL字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV61Pri : 3; /* * [22:20]FC + CSCTL字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV62Pri : 3; /* * [26:24]FC + CSCTL字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV63Pri : 3; /* * [30:28]FC + CSCTL字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI7_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI6 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri6 { + struct tagStIpsurxFcCsctlPri6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV55Pri : 3; /* * [30:28]FC + CSCTL字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV54Pri : 3; /* * [26:24]FC + CSCTL字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV53Pri : 3; /* * [22:20]FC + CSCTL字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV52Pri : 3; /* * [18:16]FC + CSCTL字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV51Pri : 3; /* * [14:12]FC + CSCTL字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV50Pri : 3; /* * [10:8]FC + CSCTL字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV49Pri : 3; /* * [6:4]FC + CSCTL字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV48Pri : 3; /* * [2:0]FC + CSCTL字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV48Pri : 3; /* * [2:0]FC + CSCTL字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV49Pri : 3; /* * [6:4]FC + CSCTL字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV50Pri : 3; /* * [10:8]FC + CSCTL字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV51Pri : 3; /* * [14:12]FC + CSCTL字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV52Pri : 3; /* * [18:16]FC + CSCTL字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV53Pri : 3; /* * [22:20]FC + CSCTL字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV54Pri : 3; /* * [26:24]FC + CSCTL字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV55Pri : 3; /* * [30:28]FC + CSCTL字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI6_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI5 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri5 { + struct tagStIpsurxFcCsctlPri5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV47Pri : 3; /* * [30:28]FC + CSCTL字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV46Pri : 3; /* * [26:24]FC + CSCTL字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV45Pri : 3; /* * [22:20]FC + CSCTL字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV44Pri : 3; /* * [18:16]FC + CSCTL字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV43Pri : 3; /* * [14:12]FC + CSCTL字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV42Pri : 3; /* * [10:8]FC + CSCTL字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV41Pri : 3; /* * [6:4]FC + CSCTL字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV40Pri : 3; /* * [2:0]FC + CSCTL字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV40Pri : 3; /* * [2:0]FC + CSCTL字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV41Pri : 3; /* * [6:4]FC + CSCTL字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV42Pri : 3; /* * [10:8]FC + CSCTL字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV43Pri : 3; /* * [14:12]FC + CSCTL字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV44Pri : 3; /* * [18:16]FC + CSCTL字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV45Pri : 3; /* * [22:20]FC + CSCTL字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV46Pri : 3; /* * [26:24]FC + CSCTL字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV47Pri : 3; /* * [30:28]FC + CSCTL字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI5_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI4 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri4 { + struct tagStIpsurxFcCsctlPri4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV39Pri : 3; /* * [30:28]FC + CSCTL字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV38Pri : 3; /* * [26:24]FC + CSCTL字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV37Pri : 3; /* * [22:20]FC + CSCTL字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV36Pri : 3; /* * [18:16]FC + CSCTL字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV35Pri : 3; /* * [14:12]FC + CSCTL字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV34Pri : 3; /* * [10:8]FC + CSCTL字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV33Pri : 3; /* * [6:4]FC + CSCTL字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV32Pri : 3; /* * [2:0]FC + CSCTL字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV32Pri : 3; /* * [2:0]FC + CSCTL字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV33Pri : 3; /* * [6:4]FC + CSCTL字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV34Pri : 3; /* * [10:8]FC + CSCTL字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV35Pri : 3; /* * [14:12]FC + CSCTL字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV36Pri : 3; /* * [18:16]FC + CSCTL字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV37Pri : 3; /* * [22:20]FC + CSCTL字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV38Pri : 3; /* * [26:24]FC + CSCTL字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV39Pri : 3; /* * [30:28]FC + CSCTL字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI4_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI3 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri3 { + struct tagStIpsurxFcCsctlPri3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV31Pri : 3; /* * [30:28]FC + CSCTL字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV30Pri : 3; /* * [26:24]FC + CSCTL字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV29Pri : 3; /* * [22:20]FC + CSCTL字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV28Pri : 3; /* * [18:16]FC + CSCTL字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV27Pri : 3; /* * [14:12]FC + CSCTL字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV26Pri : 3; /* * [10:8]FC + CSCTL字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV25Pri : 3; /* * [6:4]FC + CSCTL字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV24Pri : 3; /* * [2:0]FC + CSCTL字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV24Pri : 3; /* * [2:0]FC + CSCTL字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV25Pri : 3; /* * [6:4]FC + CSCTL字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV26Pri : 3; /* * [10:8]FC + CSCTL字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV27Pri : 3; /* * [14:12]FC + CSCTL字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV28Pri : 3; /* * [18:16]FC + CSCTL字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV29Pri : 3; /* * [22:20]FC + CSCTL字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV30Pri : 3; /* * [26:24]FC + CSCTL字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV31Pri : 3; /* * [30:28]FC + CSCTL字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI3_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI2 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri2 { + struct tagStIpsurxFcCsctlPri2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV23Pri : 3; /* * [30:28]FC + CSCTL字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV22Pri : 3; /* * [26:24]FC + CSCTL字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV21Pri : 3; /* * [22:20]FC + CSCTL字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV20Pri : 3; /* * [18:16]FC + CSCTL字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV19Pri : 3; /* * [14:12]FC + CSCTL字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV18Pri : 3; /* * [10:8]FC + CSCTL字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV17Pri : 3; /* * [6:4]FC + CSCTL字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV16Pri : 3; /* * [2:0]FC + CSCTL字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcCsctlV16Pri : 3; /* * [2:0]FC + CSCTL字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcCsctlV17Pri : 3; /* * [6:4]FC + CSCTL字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV18Pri : 3; /* * [10:8]FC + CSCTL字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV19Pri : 3; /* * [14:12]FC + CSCTL字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV20Pri : 3; /* * [18:16]FC + CSCTL字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV21Pri : 3; /* * [22:20]FC + CSCTL字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV22Pri : 3; /* * [26:24]FC + CSCTL字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV23Pri : 3; /* * [30:28]FC + CSCTL字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI2_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI1 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri1 { + struct tagStIpsurxFcCsctlPri1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcCsctlV15Pri : 3; /* * [30:28]FC + CSCTL字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV14Pri : 3; /* * [26:24]FC + CSCTL字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV13Pri : 3; /* * [22:20]FC + CSCTL字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV12Pri : 3; /* * [18:16]FC + CSCTL字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV11Pri : 3; /* * [14:12]FC + CSCTL字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV10Pri : 3; /* * [10:8]FC + CSCTL字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxFcCsctlV9Pri : 3; /* * [6:4]FC + CSCTL字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxFcCsctlV8Pri : 3; /* * [2:0]FC + CSCTL字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxFcCsctlV8Pri : 3; /* * [2:0]FC + CSCTL字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxFcCsctlV9Pri : 3; /* * [6:4]FC + CSCTL字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcCsctlV10Pri : 3; /* * [10:8]FC + CSCTL字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcCsctlV11Pri : 3; /* * [14:12]FC + CSCTL字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcCsctlV12Pri : 3; /* * [18:16]FC + CSCTL字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcCsctlV13Pri : 3; /* * [22:20]FC + CSCTL字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcCsctlV14Pri : 3; /* * [26:24]FC + CSCTL字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcCsctlV15Pri : 3; /* * [30:28]FC + CSCTL字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI1_U; + +/* ** + * Union name : IPSURX_FC_CSCTL_PRI0 + * @brief FC CSCTL优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCsctlPri0 { + struct tagStIpsurxFcCsctlPri0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int ipsurxFcCsctlV7Pri : 3; /* * [30:28]FC + CSCTL字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxFcCsctlV6Pri : 3; /* * [26:24]FC + CSCTL字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxFcCsctlV5Pri : 3; /* * [22:20]FC + CSCTL字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxFcCsctlV4Pri : 3; /* * [18:16]FC + CSCTL字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxFcCsctlV3Pri : 3; /* * [14:12]FC + CSCTL字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxFcCsctlV2Pri : 3; /* * [10:8]FC + CSCTL字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxFcCsctlV1Pri : 3; /* * [6:4]FC + CSCTL字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxFcCsctlV0Pri : 3; /* * [2:0]FC + CSCTL字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int ipsurxFcCsctlV0Pri : 3; /* * [2:0]FC + CSCTL字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int ipsurxFcCsctlV1Pri : 3; /* * [6:4]FC + CSCTL字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxFcCsctlV2Pri : 3; /* * [10:8]FC + CSCTL字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int ipsurxFcCsctlV3Pri : 3; /* * [14:12]FC + CSCTL字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxFcCsctlV4Pri : 3; /* * [18:16]FC + CSCTL字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int ipsurxFcCsctlV5Pri : 3; /* * [22:20]FC + CSCTL字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxFcCsctlV6Pri : 3; /* * [26:24]FC + CSCTL字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int ipsurxFcCsctlV7Pri : 3; /* * [30:28]FC + CSCTL字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CSCTL_PRI0_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI15 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri15 { + struct tagStIpsurxFcPriorityPri15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV127Pri : 3; /* * [30:28]FC + PRIORITY字段值127优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV126Pri : 3; /* * [26:24]FC + PRIORITY字段值126优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV125Pri : 3; /* * [22:20]FC + PRIORITY字段值125优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV124Pri : 3; /* * [18:16]FC + PRIORITY字段值124优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV123Pri : 3; /* * [14:12]FC + PRIORITY字段值123优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV122Pri : 3; /* * [10:8]FC + PRIORITY字段值122优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV121Pri : 3; /* * [6:4]FC + PRIORITY字段值121优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV120Pri : 3; /* * [2:0]FC + PRIORITY字段值120优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV120Pri : 3; /* * [2:0]FC + PRIORITY字段值120优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV121Pri : 3; /* * [6:4]FC + PRIORITY字段值121优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV122Pri : 3; /* * [10:8]FC + PRIORITY字段值122优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV123Pri : 3; /* * [14:12]FC + PRIORITY字段值123优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV124Pri : 3; /* * [18:16]FC + PRIORITY字段值124优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV125Pri : 3; /* * [22:20]FC + PRIORITY字段值125优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV126Pri : 3; /* * [26:24]FC + PRIORITY字段值126优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV127Pri : 3; /* * [30:28]FC + PRIORITY字段值127优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI15_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI14 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri14 { + struct tagStIpsurxFcPriorityPri14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV119Pri : 3; /* * [30:28]FC + PRIORITY字段值119优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV118Pri : 3; /* * [26:24]FC + PRIORITY字段值118优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV117Pri : 3; /* * [22:20]FC + PRIORITY字段值117优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV116Pri : 3; /* * [18:16]FC + PRIORITY字段值116优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV115Pri : 3; /* * [14:12]FC + PRIORITY字段值115优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV114Pri : 3; /* * [10:8]FC + PRIORITY字段值114优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV113Pri : 3; /* * [6:4]FC + PRIORITY字段值113优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV112Pri : 3; /* * [2:0]FC + PRIORITY字段值112优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV112Pri : 3; /* * [2:0]FC + PRIORITY字段值112优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV113Pri : 3; /* * [6:4]FC + PRIORITY字段值113优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV114Pri : 3; /* * [10:8]FC + PRIORITY字段值114优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV115Pri : 3; /* * [14:12]FC + PRIORITY字段值115优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV116Pri : 3; /* * [18:16]FC + PRIORITY字段值116优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV117Pri : 3; /* * [22:20]FC + PRIORITY字段值117优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV118Pri : 3; /* * [26:24]FC + PRIORITY字段值118优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV119Pri : 3; /* * [30:28]FC + PRIORITY字段值119优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI14_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI13 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri13 { + struct tagStIpsurxFcPriorityPri13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV111Pri : 3; /* * [30:28]FC + PRIORITY字段值111优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV110Pri : 3; /* * [26:24]FC + PRIORITY字段值110优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV109Pri : 3; /* * [22:20]FC + PRIORITY字段值109优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV108Pri : 3; /* * [18:16]FC + PRIORITY字段值108优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV107Pri : 3; /* * [14:12]FC + PRIORITY字段值107优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV106Pri : 3; /* * [10:8]FC + PRIORITY字段值106优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV105Pri : 3; /* * [6:4]FC + PRIORITY字段值105优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV104Pri : 3; /* * [2:0]FC + PRIORITY字段值104优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV104Pri : 3; /* * [2:0]FC + PRIORITY字段值104优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV105Pri : 3; /* * [6:4]FC + PRIORITY字段值105优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV106Pri : 3; /* * [10:8]FC + PRIORITY字段值106优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV107Pri : 3; /* * [14:12]FC + PRIORITY字段值107优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV108Pri : 3; /* * [18:16]FC + PRIORITY字段值108优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV109Pri : 3; /* * [22:20]FC + PRIORITY字段值109优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV110Pri : 3; /* * [26:24]FC + PRIORITY字段值110优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV111Pri : 3; /* * [30:28]FC + PRIORITY字段值111优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI13_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI12 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri12 { + struct tagStIpsurxFcPriorityPri12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV103Pri : 3; /* * [30:28]FC + PRIORITY字段值103优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV102Pri : 3; /* * [26:24]FC + PRIORITY字段值102优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV101Pri : 3; /* * [22:20]FC + PRIORITY字段值101优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV100Pri : 3; /* * [18:16]FC + PRIORITY字段值100优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV99Pri : 3; /* * [14:12]FC + PRIORITY字段值99优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV98Pri : 3; /* * [10:8]FC + PRIORITY字段值98优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV97Pri : 3; /* * [6:4]FC + PRIORITY字段值97优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV96Pri : 3; /* * [2:0]FC + PRIORITY字段值96优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV96Pri : 3; /* * [2:0]FC + PRIORITY字段值96优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV97Pri : 3; /* * [6:4]FC + PRIORITY字段值97优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV98Pri : 3; /* * [10:8]FC + PRIORITY字段值98优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV99Pri : 3; /* * [14:12]FC + PRIORITY字段值99优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV100Pri : 3; /* * [18:16]FC + PRIORITY字段值100优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV101Pri : 3; /* * [22:20]FC + PRIORITY字段值101优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV102Pri : 3; /* * [26:24]FC + PRIORITY字段值102优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV103Pri : 3; /* * [30:28]FC + PRIORITY字段值103优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI12_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI11 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri11 { + struct tagStIpsurxFcPriorityPri11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV95Pri : 3; /* * [30:28]FC + PRIORITY字段值95优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV94Pri : 3; /* * [26:24]FC + PRIORITY字段值94优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV93Pri : 3; /* * [22:20]FC + PRIORITY字段值93优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV92Pri : 3; /* * [18:16]FC + PRIORITY字段值92优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV91Pri : 3; /* * [14:12]FC + PRIORITY字段值91优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV90Pri : 3; /* * [10:8]FC + PRIORITY字段值90优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV89Pri : 3; /* * [6:4]FC + PRIORITY字段值89优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV88Pri : 3; /* * [2:0]FC + PRIORITY字段值88优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV88Pri : 3; /* * [2:0]FC + PRIORITY字段值88优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV89Pri : 3; /* * [6:4]FC + PRIORITY字段值89优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV90Pri : 3; /* * [10:8]FC + PRIORITY字段值90优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV91Pri : 3; /* * [14:12]FC + PRIORITY字段值91优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV92Pri : 3; /* * [18:16]FC + PRIORITY字段值92优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV93Pri : 3; /* * [22:20]FC + PRIORITY字段值93优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV94Pri : 3; /* * [26:24]FC + PRIORITY字段值94优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV95Pri : 3; /* * [30:28]FC + PRIORITY字段值95优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI11_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI10 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri10 { + struct tagStIpsurxFcPriorityPri10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV87Pri : 3; /* * [30:28]FC + PRIORITY字段值87优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV86Pri : 3; /* * [26:24]FC + PRIORITY字段值86优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV85Pri : 3; /* * [22:20]FC + PRIORITY字段值85优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV84Pri : 3; /* * [18:16]FC + PRIORITY字段值84优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV83Pri : 3; /* * [14:12]FC + PRIORITY字段值83优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV82Pri : 3; /* * [10:8]FC + PRIORITY字段值82优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV81Pri : 3; /* * [6:4]FC + PRIORITY字段值81优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV80Pri : 3; /* * [2:0]FC + PRIORITY字段值80优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV80Pri : 3; /* * [2:0]FC + PRIORITY字段值80优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV81Pri : 3; /* * [6:4]FC + PRIORITY字段值81优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV82Pri : 3; /* * [10:8]FC + PRIORITY字段值82优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV83Pri : 3; /* * [14:12]FC + PRIORITY字段值83优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV84Pri : 3; /* * [18:16]FC + PRIORITY字段值84优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV85Pri : 3; /* * [22:20]FC + PRIORITY字段值85优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV86Pri : 3; /* * [26:24]FC + PRIORITY字段值86优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV87Pri : 3; /* * [30:28]FC + PRIORITY字段值87优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI10_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI9 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri9 { + struct tagStIpsurxFcPriorityPri9 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV79Pri : 3; /* * [30:28]FC + PRIORITY字段值79优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV78Pri : 3; /* * [26:24]FC + PRIORITY字段值78优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV77Pri : 3; /* * [22:20]FC + PRIORITY字段值77优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV76Pri : 3; /* * [18:16]FC + PRIORITY字段值76优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV75Pri : 3; /* * [14:12]FC + PRIORITY字段值75优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV74Pri : 3; /* * [10:8]FC + PRIORITY字段值74优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV73Pri : 3; /* * [6:4]FC + PRIORITY字段值73优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV72Pri : 3; /* * [2:0]FC + PRIORITY字段值72优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV72Pri : 3; /* * [2:0]FC + PRIORITY字段值72优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV73Pri : 3; /* * [6:4]FC + PRIORITY字段值73优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV74Pri : 3; /* * [10:8]FC + PRIORITY字段值74优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV75Pri : 3; /* * [14:12]FC + PRIORITY字段值75优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV76Pri : 3; /* * [18:16]FC + PRIORITY字段值76优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV77Pri : 3; /* * [22:20]FC + PRIORITY字段值77优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV78Pri : 3; /* * [26:24]FC + PRIORITY字段值78优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV79Pri : 3; /* * [30:28]FC + PRIORITY字段值79优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI9_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI8 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri8 { + struct tagStIpsurxFcPriorityPri8 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV71Pri : 3; /* * [30:28]FC + PRIORITY字段值71优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV70Pri : 3; /* * [26:24]FC + PRIORITY字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV69Pri : 3; /* * [22:20]FC + PRIORITY字段值69优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV68Pri : 3; /* * [18:16]FC + PRIORITY字段值68优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV67Pri : 3; /* * [14:12]FC + PRIORITY字段值67优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV66Pri : 3; /* * [10:8]FC + PRIORITY字段值66优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV65Pri : 3; /* * [6:4]FC + PRIORITY字段值65优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV64Pri : 3; /* * [2:0]FC + PRIORITY字段值64优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV64Pri : 3; /* * [2:0]FC + PRIORITY字段值64优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV65Pri : 3; /* * [6:4]FC + PRIORITY字段值65优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV66Pri : 3; /* * [10:8]FC + PRIORITY字段值66优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV67Pri : 3; /* * [14:12]FC + PRIORITY字段值67优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV68Pri : 3; /* * [18:16]FC + PRIORITY字段值68优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV69Pri : 3; /* * [22:20]FC + PRIORITY字段值69优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV70Pri : 3; /* * [26:24]FC + PRIORITY字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV71Pri : 3; /* * [30:28]FC + PRIORITY字段值71优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI8_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI7 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri7 { + struct tagStIpsurxFcPriorityPri7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV63Pri : 3; /* * [30:28]FC + PRIORITY字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV62Pri : 3; /* * [26:24]FC + PRIORITY字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV61Pri : 3; /* * [22:20]FC + PRIORITY字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV60Pri : 3; /* * [18:16]FC + PRIORITY字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV59Pri : 3; /* * [14:12]FC + PRIORITY字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV58Pri : 3; /* * [10:8]FC + PRIORITY字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV57Pri : 3; /* * [6:4]FC + PRIORITY字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV56Pri : 3; /* * [2:0]FC + PRIORITY字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV56Pri : 3; /* * [2:0]FC + PRIORITY字段值56优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV57Pri : 3; /* * [6:4]FC + PRIORITY字段值57优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV58Pri : 3; /* * [10:8]FC + PRIORITY字段值58优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV59Pri : 3; /* * [14:12]FC + PRIORITY字段值59优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV60Pri : 3; /* * [18:16]FC + PRIORITY字段值60优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV61Pri : 3; /* * [22:20]FC + PRIORITY字段值61优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV62Pri : 3; /* * [26:24]FC + PRIORITY字段值62优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV63Pri : 3; /* * [30:28]FC + PRIORITY字段值63优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI7_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI6 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri6 { + struct tagStIpsurxFcPriorityPri6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV55Pri : 3; /* * [30:28]FC + PRIORITY字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV54Pri : 3; /* * [26:24]FC + PRIORITY字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV53Pri : 3; /* * [22:20]FC + PRIORITY字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV52Pri : 3; /* * [18:16]FC + PRIORITY字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV51Pri : 3; /* * [14:12]FC + PRIORITY字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV50Pri : 3; /* * [10:8]FC + PRIORITY字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV49Pri : 3; /* * [6:4]FC + PRIORITY字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV48Pri : 3; /* * [2:0]FC + PRIORITY字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV48Pri : 3; /* * [2:0]FC + PRIORITY字段值48优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV49Pri : 3; /* * [6:4]FC + PRIORITY字段值49优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV50Pri : 3; /* * [10:8]FC + PRIORITY字段值50优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV51Pri : 3; /* * [14:12]FC + PRIORITY字段值51优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV52Pri : 3; /* * [18:16]FC + PRIORITY字段值52优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV53Pri : 3; /* * [22:20]FC + PRIORITY字段值53优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV54Pri : 3; /* * [26:24]FC + PRIORITY字段值54优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV55Pri : 3; /* * [30:28]FC + PRIORITY字段值55优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI6_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI5 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri5 { + struct tagStIpsurxFcPriorityPri5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV47Pri : 3; /* * [30:28]FC + PRIORITY字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV46Pri : 3; /* * [26:24]FC + PRIORITY字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV45Pri : 3; /* * [22:20]FC + PRIORITY字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV44Pri : 3; /* * [18:16]FC + PRIORITY字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV43Pri : 3; /* * [14:12]FC + PRIORITY字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV42Pri : 3; /* * [10:8]FC + PRIORITY字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV41Pri : 3; /* * [6:4]FC + PRIORITY字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV40Pri : 3; /* * [2:0]FC + PRIORITY字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV40Pri : 3; /* * [2:0]FC + PRIORITY字段值40优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV41Pri : 3; /* * [6:4]FC + PRIORITY字段值41优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV42Pri : 3; /* * [10:8]FC + PRIORITY字段值42优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV43Pri : 3; /* * [14:12]FC + PRIORITY字段值43优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV44Pri : 3; /* * [18:16]FC + PRIORITY字段值44优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV45Pri : 3; /* * [22:20]FC + PRIORITY字段值45优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV46Pri : 3; /* * [26:24]FC + PRIORITY字段值46优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV47Pri : 3; /* * [30:28]FC + PRIORITY字段值47优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI5_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI4 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri4 { + struct tagStIpsurxFcPriorityPri4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV39Pri : 3; /* * [30:28]FC + PRIORITY字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV38Pri : 3; /* * [26:24]FC + PRIORITY字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV37Pri : 3; /* * [22:20]FC + PRIORITY字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV36Pri : 3; /* * [18:16]FC + PRIORITY字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV35Pri : 3; /* * [14:12]FC + PRIORITY字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV34Pri : 3; /* * [10:8]FC + PRIORITY字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV33Pri : 3; /* * [6:4]FC + PRIORITY字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV32Pri : 3; /* * [2:0]FC + PRIORITY字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV32Pri : 3; /* * [2:0]FC + PRIORITY字段值32优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV33Pri : 3; /* * [6:4]FC + PRIORITY字段值33优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV34Pri : 3; /* * [10:8]FC + PRIORITY字段值34优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV35Pri : 3; /* * [14:12]FC + PRIORITY字段值35优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV36Pri : 3; /* * [18:16]FC + PRIORITY字段值36优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV37Pri : 3; /* * [22:20]FC + PRIORITY字段值37优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV38Pri : 3; /* * [26:24]FC + PRIORITY字段值38优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV39Pri : 3; /* * [30:28]FC + PRIORITY字段值39优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI4_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI3 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri3 { + struct tagStIpsurxFcPriorityPri3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV31Pri : 3; /* * [30:28]FC + PRIORITY字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV30Pri : 3; /* * [26:24]FC + PRIORITY字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV29Pri : 3; /* * [22:20]FC + PRIORITY字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV28Pri : 3; /* * [18:16]FC + PRIORITY字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV27Pri : 3; /* * [14:12]FC + PRIORITY字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV26Pri : 3; /* * [10:8]FC + PRIORITY字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV25Pri : 3; /* * [6:4]FC + PRIORITY字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV24Pri : 3; /* * [2:0]FC + PRIORITY字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV24Pri : 3; /* * [2:0]FC + PRIORITY字段值24优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV25Pri : 3; /* * [6:4]FC + PRIORITY字段值25优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV26Pri : 3; /* * [10:8]FC + PRIORITY字段值26优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV27Pri : 3; /* * [14:12]FC + PRIORITY字段值27优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV28Pri : 3; /* * [18:16]FC + PRIORITY字段值28优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV29Pri : 3; /* * [22:20]FC + PRIORITY字段值29优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV30Pri : 3; /* * [26:24]FC + PRIORITY字段值30优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV31Pri : 3; /* * [30:28]FC + PRIORITY字段值31优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI3_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI2 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri2 { + struct tagStIpsurxFcPriorityPri2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV23Pri : 3; /* * [30:28]FC + PRIORITY字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV22Pri : 3; /* * [26:24]FC + PRIORITY字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV21Pri : 3; /* * [22:20]FC + PRIORITY字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV20Pri : 3; /* * [18:16]FC + PRIORITY字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV19Pri : 3; /* * [14:12]FC + PRIORITY字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV18Pri : 3; /* * [10:8]FC + PRIORITY字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV17Pri : 3; /* * [6:4]FC + PRIORITY字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV16Pri : 3; /* * [2:0]FC + PRIORITY字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV16Pri : 3; /* * [2:0]FC + PRIORITY字段值16优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV17Pri : 3; /* * [6:4]FC + PRIORITY字段值17优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV18Pri : 3; /* * [10:8]FC + PRIORITY字段值18优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV19Pri : 3; /* * [14:12]FC + PRIORITY字段值19优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV20Pri : 3; /* * [18:16]FC + PRIORITY字段值20优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV21Pri : 3; /* * [22:20]FC + PRIORITY字段值21优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV22Pri : 3; /* * [26:24]FC + PRIORITY字段值22优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV23Pri : 3; /* * [30:28]FC + PRIORITY字段值23优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI2_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI1 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri1 { + struct tagStIpsurxFcPriorityPri1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV15Pri : 3; /* * [30:28]FC + PRIORITY字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV14Pri : 3; /* * [26:24]FC + PRIORITY字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV13Pri : 3; /* * [22:20]FC + PRIORITY字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV12Pri : 3; /* * [18:16]FC + PRIORITY字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV11Pri : 3; /* * [14:12]FC + PRIORITY字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV10Pri : 3; /* * [10:8]FC + PRIORITY字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV9Pri : 3; /* * [6:4]FC + PRIORITY字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV8Pri : 3; /* * [2:0]FC + PRIORITY字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV8Pri : 3; /* * [2:0]FC + PRIORITY字段值8优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV9Pri : 3; /* * [6:4]FC + PRIORITY字段值9优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV10Pri : 3; /* * [10:8]FC + PRIORITY字段值10优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV11Pri : 3; /* * [14:12]FC + PRIORITY字段值11优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV12Pri : 3; /* * [18:16]FC + PRIORITY字段值12优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV13Pri : 3; /* * [22:20]FC + PRIORITY字段值13优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV14Pri : 3; /* * [26:24]FC + PRIORITY字段值14优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV15Pri : 3; /* * [30:28]FC + PRIORITY字段值15优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI1_U; + +/* ** + * Union name : IPSURX_FC_PRIORITY_PRI0 + * @brief FC PRIORITY优先级映射寄存器 + * Description: + */ +typedef union tagUnIpsurxFcPriorityPri0 { + struct tagStIpsurxFcPriorityPri0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxFcPriorityV7Pri : 3; /* * [30:28]FC + PRIORITY字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV6Pri : 3; /* * [26:24]FC + PRIORITY字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV5Pri : 3; /* * [22:20]FC + PRIORITY字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV4Pri : 3; /* * [18:16]FC + PRIORITY字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV3Pri : 3; /* * [14:12]FC + PRIORITY字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV2Pri : 3; /* * [10:8]FC + PRIORITY字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV1Pri : 3; /* * [6:4]FC + PRIORITY字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV0Pri : 3; /* * [2:0]FC + PRIORITY字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ +#else + unsigned int + ipsurxFcPriorityV0Pri : 3; /* * [2:0]FC + PRIORITY字段值0优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved7 : 1; /* * [3:3] */ + unsigned int + ipsurxFcPriorityV1Pri : 3; /* * [6:4]FC + PRIORITY字段值1优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxFcPriorityV2Pri : 3; /* * [10:8]FC + PRIORITY字段值2优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved5 : 1; /* * [11:11] */ + unsigned int + ipsurxFcPriorityV3Pri : 3; /* * [14:12]FC + PRIORITY字段值3优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxFcPriorityV4Pri : 3; /* * [18:16]FC + PRIORITY字段值4优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved3 : 1; /* * [19:19] */ + unsigned int + ipsurxFcPriorityV5Pri : 3; /* * [22:20]FC + PRIORITY字段值5优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxFcPriorityV6Pri : 3; /* * [26:24]FC + PRIORITY字段值6优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved1 : 1; /* * [27:27] */ + unsigned int + ipsurxFcPriorityV7Pri : 3; /* * [30:28]FC + PRIORITY字段值7优先级映射寄存器。3'b000，最高优先级；…3'b111，最低优先级。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_PRIORITY_PRI0_U; + +/* ** + * Union name : IPSURX_CRC_CTRL + * @brief IPSURX CRC控制寄存器 + * Description: + */ +typedef union tagUnIpsurxCrcCtrl { + struct tagStIpsurxCrcCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 13; /* * [31:19]建议不要修改bit[18:0]的默认值。 */ + unsigned int ipsurxRoceIcrcRsltInv : 1; /* * [18:18]RoCE ICRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int ipsurxRoceIcrcRsltBitRev : 1; /* * [17:17]RoCE + ICRC计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxRoceIcrcDatBitRev : 1; /* * [16:16]RoCE + ICRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int reserved1 : 1; /* * [15:15] */ + unsigned int ipsurxIwarpCrcRsltInv : 1; /* * [14:14]IWARP CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int ipsurxIwarpCrcRsltBitRev : 1; /* * [13:13]IWARP + CRC计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxIwarpCrcDatBitRev : 1; /* * [12:12]IWARP + CRC输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int reserved2 : 1; /* * [11:11] */ + unsigned int ipsurxSctpCrcRsltInv : 1; /* * [10:10]SCTP CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int ipsurxSctpCrcRsltBitRev : 1; /* * [9:9]SCTP + CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxSctpCrcDatBitRev : 1; /* * [8:8]SCTP + CRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int reserved3 : 1; /* * [7:7] */ + unsigned int ipsurxFcCrcRsltInv : 1; /* * [6:6]FC CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int ipsurxFcCrcRsltBitRev : 1; /* * [5:5]FC CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 + */ + unsigned int ipsurxFcCrcDatBitRev : 1; /* * [4:4]FC CRC校验输入数据Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int reserved4 : 1; /* * [3:3]保留。 */ + unsigned int ipsurxDifxCrcRsltInv : 1; /* * [2:2]DIFX CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int ipsurxDifxCrcRsltBitRev : 1; /* * [1:1]DIFX + CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxDifxCrcDatBitRev : 1; /* * [0:0]DIFX + CRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ +#else + unsigned int ipsurxDifxCrcDatBitRev : 1; /* * [0:0]DIFX + CRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxDifxCrcRsltBitRev : 1; /* * [1:1]DIFX + CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxDifxCrcRsltInv : 1; /* * [2:2]DIFX CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int reserved4 : 1; /* * [3:3]保留。 */ + unsigned int ipsurxFcCrcDatBitRev : 1; /* * [4:4]FC CRC校验输入数据Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxFcCrcRsltBitRev : 1; /* * [5:5]FC CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 + */ + unsigned int ipsurxFcCrcRsltInv : 1; /* * [6:6]FC CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int reserved3 : 1; /* * [7:7] */ + unsigned int ipsurxSctpCrcDatBitRev : 1; /* * [8:8]SCTP + CRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxSctpCrcRsltBitRev : 1; /* * [9:9]SCTP + CRC校验计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxSctpCrcRsltInv : 1; /* * [10:10]SCTP CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int reserved2 : 1; /* * [11:11] */ + unsigned int ipsurxIwarpCrcDatBitRev : 1; /* * [12:12]IWARP + CRC输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxIwarpCrcRsltBitRev : 1; /* * [13:13]IWARP + CRC计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxIwarpCrcRsltInv : 1; /* * [14:14]IWARP CRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int reserved1 : 1; /* * [15:15] */ + unsigned int ipsurxRoceIcrcDatBitRev : 1; /* * [16:16]RoCE + ICRC校验输入数据每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxRoceIcrcRsltBitRev : 1; /* * [17:17]RoCE + ICRC计算结果每Byte的bit倒序。1'b0：不倒序；1'b1：倒序。 */ + unsigned int ipsurxRoceIcrcRsltInv : 1; /* * [18:18]RoCE ICRC计算结果取反。1'b0：不取反；1'1：取反。 */ + unsigned int reserved0 : 13; /* * [31:19]建议不要修改bit[18:0]的默认值。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_CRC_CTRL_U; + +/* ** + * Union name : IPSURX_ROCE_ICRC_INI + * @brief RoCE ICRC初始值寄存器 + * Description: + */ +typedef union tagUnIpsurxRoceIcrcIni { + struct tagStIpsurxRoceIcrcIni { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxRoceIcrcIni : 32; /* * [31:0]RoCE + * ICRC校验时加载的ICRC计算初值。默认值：按照标准算法得到的0xC704DD7B。【注】：该默认值为算法本身初始值0xFFFFFFFF，计算8字节固定全1数据后的CRC值。建议不要修改默认值。 + */ +#else + unsigned int + ipsurxRoceIcrcIni : 32; /* * [31:0]RoCE + * ICRC校验时加载的ICRC计算初值。默认值：按照标准算法得到的0xC704DD7B。【注】：该默认值为算法本身初始值0xFFFFFFFF，计算8字节固定全1数据后的CRC值。建议不要修改默认值。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCE_ICRC_INI_U; + +/* ** + * Union name : IPSURX_ROCE_ICRC_MN + * @brief RoCE报文ICRC Magic Number值寄存器 + * Description: + */ +typedef union tagUnIpsurxRoceIcrcMn { + struct tagStIpsurxRoceIcrcMn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxRoceIcrcMn : 32; /* * [31:0]RoCE ICRC校验Magic + * Number配置值。默认值：按照标准算法得到的0x1CDF4421。【注】：该值与CRC算法的相关配置有关，需与之匹配。建议不要修改默认值。 + */ +#else + unsigned int + ipsurxRoceIcrcMn : 32; /* * [31:0]RoCE ICRC校验Magic + * Number配置值。默认值：按照标准算法得到的0x1CDF4421。【注】：该值与CRC算法的相关配置有关，需与之匹配。建议不要修改默认值。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCE_ICRC_MN_U; + +/* ** + * Union name : IPSURX_IWARP_CRC_INI + * @brief IWARP报文CRC 初始值寄存器 + * Description: + */ +typedef union tagUnIpsurxIwarpCrcIni { + struct tagStIpsurxIwarpCrcIni { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIwarpCrcIni : 32; /* * [31:0]计算TCP报文的IWARP CRC初始值。建议不要修改默认值。 */ +#else + unsigned int ipsurxIwarpCrcIni : 32; /* * [31:0]计算TCP报文的IWARP CRC初始值。建议不要修改默认值。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IWARP_CRC_INI_U; + +/* ** + * Union name : IPSURX_FC_CRC_INI + * @brief FCoE报文CRC 初始值寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCrcIni { + struct tagStIpsurxFcCrcIni { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxFcCrcIni : 32; /* * [31:0]FC CRC初始值。建议不要修改默认值。 */ +#else + unsigned int ipsurxFcCrcIni : 32; /* * [31:0]FC CRC初始值。建议不要修改默认值。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CRC_INI_U; + +/* ** + * Union name : IPSURX_FC_CRC_MN + * @brief FCoE报文CRC Magic Number值寄存器 + * Description: + */ +typedef union tagUnIpsurxFcCrcMn { + struct tagStIpsurxFcCrcMn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxFcCrcMn : 32; /* * [31:0]FC CRC校验Magic + Number配置值。默认值：0x1CDF4421。建议不要修改默认值。 */ +#else + unsigned int ipsurxFcCrcMn : 32; /* * [31:0]FC CRC校验Magic + Number配置值。默认值：0x1CDF4421。建议不要修改默认值。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CRC_MN_U; + +/* ** + * Union name : IPSURX_SCTP_CRC_INI + * @brief SCTP报文CRC 初始值寄存器 + * Description: + */ +typedef union tagUnIpsurxSctpCrcIni { + struct tagStIpsurxSctpCrcIni { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxSctpCrcIni : 32; /* * [31:0]SCTP CRC初始值。建议不要修改默认值。 */ +#else + unsigned int ipsurxSctpCrcIni : 32; /* * [31:0]SCTP CRC初始值。建议不要修改默认值。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SCTP_CRC_INI_U; + +/* ** + * Union name : IPSURX_DIFX_CRC_INI + * @brief DIF/DIX CRC16 初始值寄存器 + * Description: + */ +typedef union tagUnIpsurxDifxCrcIni { + struct tagStIpsurxDifxCrcIni { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16]reserved. */ + unsigned int ipsurxDifxCrcIni : 16; /* * [15:0]DIF/DIX CRC16 初始值建议不要修改默认值。 */ +#else + unsigned int ipsurxDifxCrcIni : 16; /* * [15:0]DIF/DIX CRC16 初始值建议不要修改默认值。 */ + unsigned int reserved : 16; /* * [31:16]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_DIFX_CRC_INI_U; + +/* ** + * Union name : IPSURX_IPV4_VER_ILGL_CNT + * @brief IPV4_VER_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv4VerIlglCnt { + struct tagStIpsurxIpv4VerIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv4VerIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv4VerIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_VER_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV4_IHL_ILGL_CNT + * @brief IPV4_IHL_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv4IhlIlglCnt { + struct tagStIpsurxIpv4IhlIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv4IhlIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv4IhlIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_IHL_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV4_SIP_ILGL_CNT + * @brief IPV4_SIP_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv4SipIlglCnt { + struct tagStIpsurxIpv4SipIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv4SipIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv4SipIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_SIP_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV4_DIP_ILGL_CNT + * @brief IPV4_DIP_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv4DipIlglCnt { + struct tagStIpsurxIpv4DipIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv4DipIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv4DipIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_DIP_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV4_CS_ILGL_CNT + * @brief IPV4_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv4CsIlglCnt { + struct tagStIpsurxIpv4CsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv4CsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv4CsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV4_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV6_VER_ILGL_CNT + * @brief IPV6_VER_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv6VerIlglCnt { + struct tagStIpsurxIpv6VerIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv6VerIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv6VerIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_VER_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV6_SIP_ILGL_CNT + * @brief IPV6_SIP_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv6SipIlglCnt { + struct tagStIpsurxIpv6SipIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv6SipIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv6SipIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_SIP_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV6_DIP_ILGL_CNT + * @brief IPV6_DIP_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIpv6DipIlglCnt { + struct tagStIpsurxIpv6DipIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv6DipIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv6DipIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_DIP_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_TCP_LAND_ILGL_CNT + * @brief TCP_LAND_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxTcpLandIlglCnt { + struct tagStIpsurxTcpLandIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcpLandIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcpLandIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCP_LAND_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_TCP_CS_ILGL_CNT + * @brief TCP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxTcpCsIlglCnt { + struct tagStIpsurxTcpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IPV6_UDP_CS_ZERO_CNT + * @brief IPv6 UDP_CS_ZERO计数器 + * Description: + */ +typedef union tagUnIpsurxIpv6UdpCsZeroCnt { + struct tagStIpsurxIpv6UdpCsZeroCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIpv6UdpCsZeroCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIpv6UdpCsZeroCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IPV6_UDP_CS_ZERO_CNT_U; + +/* ** + * Union name : IPSURX_UDP_CS_ILGL_CNT + * @brief UDP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxUdpCsIlglCnt { + struct tagStIpsurxUdpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxUdpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxUdpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_UDP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IGMP_CS_ILGL_CNT + * @brief IGMP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIgmpCsIlglCnt { + struct tagStIpsurxIgmpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIgmpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIgmpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IGMP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ICMPV4_CS_ILGL_CNT + * @brief ICMPV4_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIcmpv4CsIlglCnt { + struct tagStIpsurxIcmpv4CsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIcmpv4CsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIcmpv4CsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ICMPV4_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ICMPV6_CS_ILGL_CNT + * @brief ICMPV6_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIcmpv6CsIlglCnt { + struct tagStIpsurxIcmpv6CsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIcmpv6CsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIcmpv6CsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ICMPV6_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_SCTP_CS_ILGL_CNT + * @brief SCTP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxSctpCsIlglCnt { + struct tagStIpsurxSctpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxSctpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxSctpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_SCTP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV2_IPV4_FRAG_ILGL_CNT + * @brief ROCEV2_IPV4_FRAG_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev2Ipv4FragIlglCnt { + struct tagStIpsurxRocev2Ipv4FragIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev2Ipv4FragIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev2Ipv4FragIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV2_IPV4_FRAG_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV2_IPV4_UDP_CS_ILGL_CNT + * @brief ROCEV2_IPV4_UDP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev2Ipv4UdpCsIlglCnt { + struct tagStIpsurxRocev2Ipv4UdpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev2Ipv4UdpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev2Ipv4UdpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV2_IPV4_UDP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV2_IPV6_UDP_CS_ILGL_CNT + * @brief ROCEV2_IPV6_UDP_CS_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev2Ipv6UdpCsIlglCnt { + struct tagStIpsurxRocev2Ipv6UdpCsIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev2Ipv6UdpCsIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev2Ipv6UdpCsIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV2_IPV6_UDP_CS_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV1_DGID_ILGL_CNT + * @brief ROCEV1_DGID_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev1DgidIlglCnt { + struct tagStIpsurxRocev1DgidIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev1DgidIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev1DgidIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV1_DGID_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV1_SGID_ILGL_CNT + * @brief ROCEV1_SGID_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev1SgidIlglCnt { + struct tagStIpsurxRocev1SgidIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev1SgidIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev1SgidIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV1_SGID_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV1_IPVER_ILGL_CNT + * @brief ROCEV1_IPVER_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev1IpverIlglCnt { + struct tagStIpsurxRocev1IpverIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev1IpverIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev1IpverIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV1_IPVER_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV1_NXHDR_ILGL_CNT + * @brief ROCEV1_NXHDR_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev1NxhdrIlglCnt { + struct tagStIpsurxRocev1NxhdrIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev1NxhdrIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev1NxhdrIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV1_NXHDR_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCEV1_PLEN_ILGL_CNT + * @brief ROCEV1_PLEN_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRocev1PlenIlglCnt { + struct tagStIpsurxRocev1PlenIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRocev1PlenIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRocev1PlenIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCEV1_PLEN_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_ROCE_DQP_ILGL_CNT + * @brief ROCE_DQP_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxRoceDqpIlglCnt { + struct tagStIpsurxRoceDqpIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRoceDqpIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRoceDqpIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_ROCE_DQP_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_IB_ICRC_ILGL_CNT + * @brief IB_ICRC_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxIbIcrcIlglCnt { + struct tagStIpsurxIbIcrcIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxIbIcrcIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxIbIcrcIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_IB_ICRC_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_FC_CRC_ILGL_CNT + * @brief FC_CRC_ILGL计数器 + * Description: + */ +typedef union tagUnIpsurxFcCrcIlglCnt { + struct tagStIpsurxFcCrcIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxFcCrcIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxFcCrcIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FC_CRC_ILGL_CNT_U; + +/* ** + * Union name : IPSURX_TO_UP_PKT_ILGL_CNT + * @brief TO UP报文校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxToUpPktIlglCnt { + struct tagStIpsurxToUpPktIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxToUpPktIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxToUpPktIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TO_UP_PKT_ILGL_CNT_U; + + +/* ** + * Union name : IPSURX_NCSI_CTRL + * @brief NCSI控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiCtrl { + struct tagStIpsurxNcsiCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 25; /* * [31:7] */ + unsigned int ipsurxFicNcsiEn : 1; /* * + [6:6]预留通道属性为FIC，NCSI报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxHg2NcsiEn : 1; /* * + [5:5]预留通道属性为HG2，NCSI报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxMacNcsiEn : 1; /* * [4:4]通道属性为MAC，NCSI报文检测使能。1'b0：不使能；1'b1：使能。 */ + unsigned int reserved1 : 1; /* * [3:3] */ + unsigned int ipsurxNcsiPktPri : 3; /* * [2:0]NCSI报文优先级。3'b000，最高优先级；...3'b111，最低优先级。 */ +#else + unsigned int ipsurxNcsiPktPri : 3; /* * [2:0]NCSI报文优先级。3'b000，最高优先级；...3'b111，最低优先级。 */ + unsigned int reserved1 : 1; /* * [3:3] */ + unsigned int ipsurxMacNcsiEn : 1; /* * [4:4]通道属性为MAC，NCSI报文检测使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxHg2NcsiEn : 1; /* * + [5:5]预留通道属性为HG2，NCSI报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxFicNcsiEn : 1; /* * + [6:6]预留通道属性为FIC，NCSI报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int reserved0 : 25; /* * [31:7] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_FILTER_MNG + * @brief NCSI FILTER管理寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiFilterMng { + struct tagStIpsurxNcsiFilterMng { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3MacPort : 4; /* * [31:28]0x0~0xF：rule 3对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int reserved0 : 2; /* * [27:26] */ + unsigned int ipsurxNcsiFltRule3FwdAct : 1; /* * [25:25]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int + ipsurxNcsiFltRule3En : 1; /* * [24:24]rule3 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule2MacPort : 4; /* * [23:20]0x0~0xF：rule 2 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int reserved1 : 2; /* * [19:18] */ + unsigned int ipsurxNcsiFltRule2FwdAct : 1; /* * [17:17]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int + ipsurxNcsiFltRule2En : 1; /* * [16:16]rule2 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule1MacPort : 4; /* * [15:12]0x0~0xF：rule 1 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int reserved2 : 2; /* * [11:10] */ + unsigned int ipsurxNcsiFltRule1FwdAct : 1; /* * [9:9]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int + ipsurxNcsiFltRule1En : 1; /* * [8:8]rule1 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule0MacPort : 4; /* * [7:4]0x0~0xF：rule 0 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int reserved3 : 2; /* * [3:2] */ + unsigned int ipsurxNcsiFltRule0FwdAct : 1; /* * [1:1]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int + ipsurxNcsiFltRule0En : 1; /* * [0:0]rule0 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ +#else + unsigned int + ipsurxNcsiFltRule0En : 1; /* * [0:0]rule0 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule0FwdAct : 1; /* * [1:1]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int reserved3 : 2; /* * [3:2] */ + unsigned int ipsurxNcsiFltRule0MacPort : 4; /* * [7:4]0x0~0xF：rule 0 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int + ipsurxNcsiFltRule1En : 1; /* * [8:8]rule1 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule1FwdAct : 1; /* * [9:9]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int reserved2 : 2; /* * [11:10] */ + unsigned int ipsurxNcsiFltRule1MacPort : 4; /* * [15:12]0x0~0xF：rule 1 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int + ipsurxNcsiFltRule2En : 1; /* * [16:16]rule2 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule2FwdAct : 1; /* * [17:17]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int reserved1 : 2; /* * [19:18] */ + unsigned int ipsurxNcsiFltRule2MacPort : 4; /* * [23:20]0x0~0xF：rule 2 对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ + unsigned int + ipsurxNcsiFltRule3En : 1; /* * [24:24]rule3 控制寄存器。1'b0: disable;1'b1: + enable.【注意】当配置为disable，没有报文能通过该规则匹配而送到BMC/HOST。 + */ + unsigned int ipsurxNcsiFltRule3FwdAct : 1; /* * [25:25]匹配该规则检查的报文的转发动作。1'b0： to TILE & + BMC；1'b1： only to BMC。 */ + unsigned int reserved0 : 2; /* * [27:26] */ + unsigned int ipsurxNcsiFltRule3MacPort : 4; /* * [31:28]0x0~0xF：rule 3对应的报文输入MAC端口编号/FIC + TP编号。4条规则不能配置成相同的PORT。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_FILTER_MNG_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC3_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac3HCtrl { + struct tagStIpsurxNcsiRule3Mac3HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule3Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule3Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC3_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC3_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac3LCtrl { + struct tagStIpsurxNcsiRule3Mac3LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC3_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC2_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac2HCtrl { + struct tagStIpsurxNcsiRule3Mac2HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule3Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule3Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC2_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC2_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac2LCtrl { + struct tagStIpsurxNcsiRule3Mac2LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC2_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC1_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac1HCtrl { + struct tagStIpsurxNcsiRule3Mac1HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule3Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule3Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC1_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC1_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac1LCtrl { + struct tagStIpsurxNcsiRule3Mac1LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC1_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC0_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac0HCtrl { + struct tagStIpsurxNcsiRule3Mac0HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule3Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule3Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC0_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MAC0_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Mac0LCtrl { + struct tagStIpsurxNcsiRule3Mac0LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule3Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MAC0_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC3_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac3HCtrl { + struct tagStIpsurxNcsiRule2Mac3HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule2Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule2Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC3_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC3_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac3LCtrl { + struct tagStIpsurxNcsiRule2Mac3LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC3_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC2_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac2HCtrl { + struct tagStIpsurxNcsiRule2Mac2HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule2Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule2Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC2_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC2_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac2LCtrl { + struct tagStIpsurxNcsiRule2Mac2LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC2_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC1_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac1HCtrl { + struct tagStIpsurxNcsiRule2Mac1HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule2Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule2Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC1_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC1_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac1LCtrl { + struct tagStIpsurxNcsiRule2Mac1LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC1_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC0_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac0HCtrl { + struct tagStIpsurxNcsiRule2Mac0HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule2Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule2Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC0_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MAC0_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Mac0LCtrl { + struct tagStIpsurxNcsiRule2Mac0LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule2Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MAC0_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC3_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac3HCtrl { + struct tagStIpsurxNcsiRule1Mac3HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule1Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule1Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC3_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC3_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac3LCtrl { + struct tagStIpsurxNcsiRule1Mac3LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC3_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC2_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac2HCtrl { + struct tagStIpsurxNcsiRule1Mac2HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule1Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule1Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC2_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC2_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac2LCtrl { + struct tagStIpsurxNcsiRule1Mac2LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC2_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC1_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac1HCtrl { + struct tagStIpsurxNcsiRule1Mac1HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule1Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule1Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC1_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC1_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac1LCtrl { + struct tagStIpsurxNcsiRule1Mac1LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC1_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC0_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac0HCtrl { + struct tagStIpsurxNcsiRule1Mac0HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule1Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule1Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC0_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MAC0_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Mac0LCtrl { + struct tagStIpsurxNcsiRule1Mac0LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule1Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MAC0_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC3_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac3HCtrl { + struct tagStIpsurxNcsiRule0Mac3HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule0Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac3H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule0Dmac3Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC3_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC3_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac3LCtrl { + struct tagStIpsurxNcsiRule0Mac3LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac3L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC3_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC2_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac2HCtrl { + struct tagStIpsurxNcsiRule0Mac2HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule0Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac2H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule0Dmac2Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC2_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC2_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac2LCtrl { + struct tagStIpsurxNcsiRule0Mac2LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac2L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC2_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC1_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac1HCtrl { + struct tagStIpsurxNcsiRule0Mac1HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule0Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac1H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule0Dmac1Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC1_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC1_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac1LCtrl { + struct tagStIpsurxNcsiRule0Mac1LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac1L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC1_L_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC0_H_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac0HCtrl { + struct tagStIpsurxNcsiRule0Mac0HCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int ipsurxNcsiFltRule0Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac0H : 16; /* * [15:0]目的MAC地址高16比特。 */ + unsigned int + ipsurxNcsiFltRule0Dmac0Vld : 1; /* * + * [16:16]MAC地址有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该MAC地址的匹配检测。但是，如果一条规则的四个MAC地址都无效时，默认认为，所有报文都通过该规则的MAC地址检测。 + */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC0_H_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MAC0_L_CTRL + * @brief NCSI FILTER 的MAC地址控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Mac0LCtrl { + struct tagStIpsurxNcsiRule0Mac0LCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#else + unsigned int ipsurxNcsiFltRule0Dmac0L : 32; /* * [31:0]目的MAC地址低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MAC0_L_CTRL_U; + + +/* ** + * Union name : IPSURX_NCSI_RULE_VLAN_EN + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRuleVlanEn { + struct tagStIpsurxNcsiRuleVlanEn { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int + ipsurxNcsiRuleVlanEn : 4; /* * [3:0]NCSI FILTER VLAN使能寄存器。1'b0：所有携带VLAN + TAG的报文不能通过该规则检测，不含VLAN + TAG的报文通过该规则检测；1'b1：根据该条规则的8个VLAN控制寄存器的配置进行NCSI报文VLAN的检测。BIT[3]：NCSI + RULE3 VLAN EN；BIT[2]：NCSI RULE2 V LAN EN；BIT[1]：NCSI RULE1 VLAN + EN；BIT[0]：NCSI RULE0 VLAN EN。 */ +#else + unsigned int + ipsurxNcsiRuleVlanEn : 4; /* * [3:0]NCSI FILTER VLAN使能寄存器。1'b0：所有携带VLAN + TAG的报文不能通过该规则检测，不含VLAN + TAG的报文通过该规则检测；1'b1：根据该条规则的8个VLAN控制寄存器的配置进行NCSI报文VLAN的检测。BIT[3]：NCSI + RULE3 VLAN EN；BIT[2]：NCSI RULE2 V LAN EN；BIT[1]：NCSI RULE1 VLAN + EN；BIT[0]：NCSI RULE0 VLAN EN。 */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE_VLAN_EN_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN7_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan7Ctrl { + struct tagStIpsurxNcsiRule3Vlan7Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan7Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan7Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN7_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN6_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan6Ctrl { + struct tagStIpsurxNcsiRule3Vlan6Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan6Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan6Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN6_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN5_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan5Ctrl { + struct tagStIpsurxNcsiRule3Vlan5Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan5Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan5Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN5_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN4_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan4Ctrl { + struct tagStIpsurxNcsiRule3Vlan4Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan4Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan4Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN4_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN3_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan3Ctrl { + struct tagStIpsurxNcsiRule3Vlan3Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan3Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan3Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN3_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN2_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan2Ctrl { + struct tagStIpsurxNcsiRule3Vlan2Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan2Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan2Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN2_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN1_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan1Ctrl { + struct tagStIpsurxNcsiRule3Vlan1Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan1Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan1Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN1_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_VLAN0_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3Vlan0Ctrl { + struct tagStIpsurxNcsiRule3Vlan0Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule3Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule3Vlan0Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule3Vlan0Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule3Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_VLAN0_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN7_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan7Ctrl { + struct tagStIpsurxNcsiRule2Vlan7Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan7Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan7Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN7_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN6_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan6Ctrl { + struct tagStIpsurxNcsiRule2Vlan6Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan6Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan6Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN6_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN5_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan5Ctrl { + struct tagStIpsurxNcsiRule2Vlan5Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan5Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan5Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN5_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN4_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan4Ctrl { + struct tagStIpsurxNcsiRule2Vlan4Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan4Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan4Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN4_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN3_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan3Ctrl { + struct tagStIpsurxNcsiRule2Vlan3Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan3Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan3Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN3_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN2_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan2Ctrl { + struct tagStIpsurxNcsiRule2Vlan2Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan2Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan2Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN2_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN1_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan1Ctrl { + struct tagStIpsurxNcsiRule2Vlan1Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan1Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan1Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN1_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_VLAN0_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2Vlan0Ctrl { + struct tagStIpsurxNcsiRule2Vlan0Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule2Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule2Vlan0Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule2Vlan0Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule2Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_VLAN0_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN7_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan7Ctrl { + struct tagStIpsurxNcsiRule1Vlan7Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan7Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan7Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN7_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN6_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan6Ctrl { + struct tagStIpsurxNcsiRule1Vlan6Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan6Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan6Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN6_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN5_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan5Ctrl { + struct tagStIpsurxNcsiRule1Vlan5Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan5Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan5Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN5_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN4_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan4Ctrl { + struct tagStIpsurxNcsiRule1Vlan4Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan4Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan4Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN4_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN3_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan3Ctrl { + struct tagStIpsurxNcsiRule1Vlan3Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan3Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan3Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN3_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN2_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan2Ctrl { + struct tagStIpsurxNcsiRule1Vlan2Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan2Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan2Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN2_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN1_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan1Ctrl { + struct tagStIpsurxNcsiRule1Vlan1Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan1Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan1Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN1_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_VLAN0_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1Vlan0Ctrl { + struct tagStIpsurxNcsiRule1Vlan0Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule1Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule1Vlan0Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule1Vlan0Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule1Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_VLAN0_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN7_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan7Ctrl { + struct tagStIpsurxNcsiRule0Vlan7Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan7Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan7Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan7IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN7_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN6_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan6Ctrl { + struct tagStIpsurxNcsiRule0Vlan6Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan6Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan6Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan6IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN6_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN5_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan5Ctrl { + struct tagStIpsurxNcsiRule0Vlan5Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan5Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan5Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan5IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN5_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN4_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan4Ctrl { + struct tagStIpsurxNcsiRule0Vlan4Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan4Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan4Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan4IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN4_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN3_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan3Ctrl { + struct tagStIpsurxNcsiRule0Vlan3Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan3Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan3Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan3IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN3_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN2_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan2Ctrl { + struct tagStIpsurxNcsiRule0Vlan2Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan2Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan2Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan2IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid.【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN2_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN1_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan1Ctrl { + struct tagStIpsurxNcsiRule0Vlan1Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan1Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan1Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan1IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN1_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_VLAN0_CTRL + * @brief NCSI FILTER 的VLAN控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0Vlan0Ctrl { + struct tagStIpsurxNcsiRule0Vlan0Ctrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17] */ + unsigned int + ipsurxNcsiFltRule0Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxNcsiFltRule0Vlan0Id : 12; /* * [11:0]VLAN ID */ +#else + unsigned int ipsurxNcsiFltRule0Vlan0Id : 12; /* * [11:0]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int + ipsurxNcsiFltRule0Vlan0IdVld : 1; /* * [16:16]VLAN + * ID有效标志。1'b0：invalid；1'b1：valid。【注意】如果该比特为0，则没有报文能通过该VLAN + * ID的匹配检测。但是，如果一条规则的8个VLAN + * 都无效时，默认认为，所有报文都通过该规则的VLAN ID检测。 + */ + unsigned int reserved0 : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_VLAN0_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_BC_CTRL + * @brief NCSI FILTER 的广播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3BcCtrl { + struct tagStIpsurxNcsiRule3BcCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10] */ + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule3BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 22; /* * [31:10] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_BC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_BC_CTRL + * @brief NCSI FILTER 的广播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2BcCtrl { + struct tagStIpsurxNcsiRule2BcCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10] */ + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule2BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 22; /* * [31:10] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_BC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_BC_CTRL + * @brief NCSI FILTER 的广播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1BcCtrl { + struct tagStIpsurxNcsiRule1BcCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10] */ + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule1BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 22; /* * [31:10] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_BC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_BC_CTRL + * @brief NCSI FILTER 的广播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0BcCtrl { + struct tagStIpsurxNcsiRule0BcCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10] */ + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule0BcDmacEn : 1; /* * [0:0]Destination MAC address FF:FF:FF: FF:FF:FF enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcArpEn : 1; /* * [1:1]Ethernet type 0x0806 (ARP) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0BcIpv4En : 1; /* * [2:2]Ethernet type 0x800(IPv4) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0BcIpUdpEn : 1; /* * [3:3]IP header’s protocol domain value is 0x11 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt68En : 1; /* * [4:4]UDP destination port is 68 filter enable. (DHCP)1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt67En : 1; /* * [5:5]UDP destination port is 67 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt137En : 1; /* * [6:6]UDP destination port is 137 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcUdpPrt138En : 1; /* * [7:7]UDP destination port is 138 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcArpTipv4AddrEn : 1; /* * [8:8]ARP/IPv4 target IPv4 address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacEn : 1; /* * [9:9]DHCPv4 Client MAC address filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 22; /* * [31:10] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_BC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_BC_ARP_TIPV4_ADDR + * @brief NCSI FILTER的ARP/IPv4报文的目标IPv4地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3BcArpTipv4Addr { + struct tagStIpsurxNcsiRule3BcArpTipv4Addr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#else + unsigned int ipsurxNcsiFltRule3BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_BC_ARP_TIPV4_ADDR_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_BC_ARP_TIPV4_ADDR + * @brief NCSI FILTER的ARP/IPv4报文的目标IPv4地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2BcArpTipv4Addr { + struct tagStIpsurxNcsiRule2BcArpTipv4Addr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#else + unsigned int ipsurxNcsiFltRule2BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_BC_ARP_TIPV4_ADDR_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_BC_ARP_TIPV4_ADDR + * @brief NCSI FILTER的ARP/IPv4报文的目标IPv4地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1BcArpTipv4Addr { + struct tagStIpsurxNcsiRule1BcArpTipv4Addr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#else + unsigned int ipsurxNcsiFltRule1BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_BC_ARP_TIPV4_ADDR_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_BC_ARP_TIPV4_ADDR + * @brief NCSI FILTER的ARP/IPv4报文的目标IPv4地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0BcArpTipv4Addr { + struct tagStIpsurxNcsiRule0BcArpTipv4Addr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#else + unsigned int ipsurxNcsiFltRule0BcArpTipv4Addr : 32; /* * [31:0]ARP/IPv4报文的TAGRET IPv4 ADDRESS。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_BC_ARP_TIPV4_ADDR_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_BC_DHCPV4_CMAC_H + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3BcDhcpv4CmacH { + struct tagStIpsurxNcsiRule3BcDhcpv4CmacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_BC_DHCPV4_CMAC_H_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_BC_DHCPV4_CMAC_L + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3BcDhcpv4CmacL { + struct tagStIpsurxNcsiRule3BcDhcpv4CmacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#else + unsigned int ipsurxNcsiFltRule3BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_BC_DHCPV4_CMAC_L_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_BC_DHCPV4_CMAC_H + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2BcDhcpv4CmacH { + struct tagStIpsurxNcsiRule2BcDhcpv4CmacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_BC_DHCPV4_CMAC_H_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_BC_DHCPV4_CMAC_L + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2BcDhcpv4CmacL { + struct tagStIpsurxNcsiRule2BcDhcpv4CmacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#else + unsigned int ipsurxNcsiFltRule2BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_BC_DHCPV4_CMAC_L_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_BC_DHCPV4_CMAC_H + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1BcDhcpv4CmacH { + struct tagStIpsurxNcsiRule1BcDhcpv4CmacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_BC_DHCPV4_CMAC_H_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_BC_DHCPV4_CMAC_L + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1BcDhcpv4CmacL { + struct tagStIpsurxNcsiRule1BcDhcpv4CmacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#else + unsigned int ipsurxNcsiFltRule1BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_BC_DHCPV4_CMAC_L_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_BC_DHCPV4_CMAC_H + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0BcDhcpv4CmacH { + struct tagStIpsurxNcsiRule0BcDhcpv4CmacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ +#else + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacH : 16; /* * [15:0]DHCPv4报文CHADDR字段的高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_BC_DHCPV4_CMAC_H_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_BC_DHCPV4_CMAC_L + * @brief NCSI FILTER的DHCPV4报文的CHADDR地址 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0BcDhcpv4CmacL { + struct tagStIpsurxNcsiRule0BcDhcpv4CmacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#else + unsigned int ipsurxNcsiFltRule0BcDhcpv4CmacL : 32; /* * [31:0]DHCPv4报文CHADDR字段的[111:80]比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_BC_DHCPV4_CMAC_L_U; + +/* ** + * Union name : IPSURX_NCSI_RULE3_MC_CTRL + * @brief NCSI FILTER 的多播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule3McCtrl { + struct tagStIpsurxNcsiRule3McCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9] */ + unsigned int ipsurxNcsiFltRule3McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule3McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule3McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule3McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule3McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule3McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule3McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 23; /* * [31:9] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE3_MC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE2_MC_CTRL + * @brief NCSI FILTER 的多播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule2McCtrl { + struct tagStIpsurxNcsiRule2McCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9] */ + unsigned int ipsurxNcsiFltRule2McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule2McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule2McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule2McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule2McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule2McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule2McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 23; /* * [31:9] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE2_MC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE1_MC_CTRL + * @brief NCSI FILTER 的多播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule1McCtrl { + struct tagStIpsurxNcsiRule1McCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9] */ + unsigned int ipsurxNcsiFltRule1McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule1McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule1McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule1McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule1McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule1McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule1McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 23; /* * [31:9] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE1_MC_CTRL_U; + +/* ** + * Union name : IPSURX_NCSI_RULE0_MC_CTRL + * @brief NCSI FILTER 的多播报文控制寄存器 + * Description: + */ +typedef union tagUnIpsurxNcsiRule0McCtrl { + struct tagStIpsurxNcsiRule0McCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 23; /* * [31:9] */ + unsigned int ipsurxNcsiFltRule0McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule0McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ +#else + unsigned int ipsurxNcsiFltRule0McDmac0En : 1; /* * [0:0]Destination MAC address 33:33:00:00:00:01 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McDmac1En : 1; /* * [1:1]Destination MAC address 33:33:00:01:00:02 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McDmac2En : 1; /* * [2:2]Destination MAC address 33:33:00:01:00:03 enable.1'b0: + disable;1'b1: enable. */ + unsigned int ipsurxNcsiFltRule0McIpv6En : 1; /* * [3:3]Ethernet type 0x86DD (IPv6) enable.1'b0: disable;1'b1: + enable */ + unsigned int ipsurxNcsiFltRule0McIcmpv6En : 1; /* * [4:4]IP header’s next header domain value is 58 (ICMPv6) + * filter enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McUdpEn : 1; /* * [5:5]IP header’s next header domain value is 17 (UDP) filter + * enable.1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McIcmpv6Mt136En : 1; /* * [6:6]ICMPv6 header’s message type filed is 136 filter + * enable. (Neighbor Advertisement)1'b0: disable;1'b1: + * enable. + */ + unsigned int ipsurxNcsiFltRule0McIcmpv6Mt134En : 1; /* * [7:7]ICMPv6 header’s message type filed is 134 filter + * enable. (Router Advertisement)1'b0: disable;1'b1: enable. + */ + unsigned int ipsurxNcsiFltRule0McUdpPrt547En : 1; /* * [8:8]UDP destination port is 547 filter enable.1'b0: + disable;1'b1: enable. */ + unsigned int reserved : 23; /* * [31:9] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_NCSI_RULE0_MC_CTRL_U; + +/* ** + * Union name : IPSURX_TO_BMC_ONLY_PKT_ILGL_CNT + * @brief TO BMC ONLY报文校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxToBmcOnlyPktIlglCnt { + struct tagStIpsurxToBmcOnlyPktIlglCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxToBmcOnlyPktIlglCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxToBmcOnlyPktIlglCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TO_BMC_ONLY_PKT_ILGL_CNT_U; + + +/* ** + * Union name : IPSURX_WOL_CTRL + * @brief WOL控制寄存器 + * Description: + */ +typedef union tagUnIpsurxWolCtrl { + struct tagStIpsurxWolCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 24; /* * [31:8]reserved. */ + unsigned int ipsurxWolModEn : 1; /* * + [7:7]WOL工作模式使能。1'b0：不使能WOL工作模式；1'b1：使能WOL工作模式。该寄存器只控制报文的转发，不影响WOL报文的检测。 + */ + unsigned int ipsurxFicWolEn : 1; /* * + [6:6]预留通道属性为FIC，WOL报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxHg2WolEn : 1; /* * + [5:5]预留通道属性为HG2，WOL报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxMacWolEn : 1; /* * [4:4]通道属性为MAC，WOL报文检测使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxWolWkupCtrl : 4; /* * + [3:0]Bit[i]（i=0~3)控制IPSURX模块产生的唤醒host[i](i=0~3)的请求。1'b0：清除唤醒请求；1'b1：不清除唤醒请求。 + */ +#else + unsigned int ipsurxWolWkupCtrl : 4; /* * + [3:0]Bit[i]（i=0~3)控制IPSURX模块产生的唤醒host[i](i=0~3)的请求。1'b0：清除唤醒请求；1'b1：不清除唤醒请求。 + */ + unsigned int ipsurxMacWolEn : 1; /* * [4:4]通道属性为MAC，WOL报文检测使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxHg2WolEn : 1; /* * + [5:5]预留通道属性为HG2，WOL报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxFicWolEn : 1; /* * + [6:6]预留通道属性为FIC，WOL报文检测使能。1'b0：不使能；1'b1：使能。Hi1822V100只支持该值配置为0. + */ + unsigned int ipsurxWolModEn : 1; /* * + [7:7]WOL工作模式使能。1'b0：不使能WOL工作模式；1'b1：使能WOL工作模式。该寄存器只控制报文的转发，不影响WOL报文的检测。 + */ + unsigned int reserved : 24; /* * [31:8]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL_CTRL_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_CTRL1 + * @brief WOL TYPE1报文检测RULE控制寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkCtrl1 { + struct tagStIpsurxWol1ChkCtrl1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxWol1ChkRule7Opcode : 3; /* * [30:28]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved1 : 2; /* * [27:26] */ + unsigned int ipsurxWol1Rule7WkHost : 2; /* * [25:24]唤醒主机编号。 */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxWol1ChkRule6Opcode : 3; /* * [22:20]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved3 : 2; /* * [19:18] */ + unsigned int ipsurxWol1Rule6WkHost : 2; /* * [17:16]唤醒主机编号。 */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxWol1ChkRule5Opcode : 3; /* * [14:12]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved5 : 2; /* * [11:10] */ + unsigned int ipsurxWol1Rule5WkHost : 2; /* * [9:8]唤醒主机编号。 */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxWol1ChkRule4Opcode : 3; /* * [6:4]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved7 : 2; /* * [3:2] */ + unsigned int ipsurxWol1Rule4WkHost : 2; /* * [1:0]唤醒主机编号。 */ +#else + unsigned int ipsurxWol1Rule4WkHost : 2; /* * [1:0]唤醒主机编号。 */ + unsigned int reserved7 : 2; /* * [3:2] */ + unsigned int + ipsurxWol1ChkRule4Opcode : 3; /* * [6:4]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxWol1Rule5WkHost : 2; /* * [9:8]唤醒主机编号。 */ + unsigned int reserved5 : 2; /* * [11:10] */ + unsigned int + ipsurxWol1ChkRule5Opcode : 3; /* * [14:12]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxWol1Rule6WkHost : 2; /* * [17:16]唤醒主机编号。 */ + unsigned int reserved3 : 2; /* * [19:18] */ + unsigned int + ipsurxWol1ChkRule6Opcode : 3; /* * [22:20]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxWol1Rule7WkHost : 2; /* * [25:24]唤醒主机编号。 */ + unsigned int reserved1 : 2; /* * [27:26] */ + unsigned int + ipsurxWol1ChkRule7Opcode : 3; /* * [30:28]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_CTRL1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_CTRL0 + * @brief WOL TYPE1报文检测RULE控制寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkCtrl0 { + struct tagStIpsurxWol1ChkCtrl0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 1; /* * [31:31] */ + unsigned int + ipsurxWol1ChkRule3Opcode : 3; /* * [30:28]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved1 : 2; /* * [27:26] */ + unsigned int ipsurxWol1Rule3WkHost : 2; /* * [25:24]唤醒主机编号。 */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int + ipsurxWol1ChkRule2Opcode : 3; /* * [22:20]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved3 : 2; /* * [19:18] */ + unsigned int ipsurxWol1Rule2WkHost : 2; /* * [17:16]唤醒主机编号。 */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int + ipsurxWol1ChkRule1Opcode : 3; /* * [14:12]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved5 : 2; /* * [11:10] */ + unsigned int ipsurxWol1Rule1WkHost : 2; /* * [9:8]唤醒主机编号。 */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int + ipsurxWol1ChkRule0Opcode : 3; /* * [6:4]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved7 : 2; /* * [3:2] */ + unsigned int ipsurxWol1Rule0WkHost : 2; /* * [1:0]唤醒主机编号。 */ +#else + unsigned int ipsurxWol1Rule0WkHost : 2; /* * [1:0]唤醒主机编号。 */ + unsigned int reserved7 : 2; /* * [3:2] */ + unsigned int + ipsurxWol1ChkRule0Opcode : 3; /* * [6:4]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved6 : 1; /* * [7:7] */ + unsigned int ipsurxWol1Rule1WkHost : 2; /* * [9:8]唤醒主机编号。 */ + unsigned int reserved5 : 2; /* * [11:10] */ + unsigned int + ipsurxWol1ChkRule1Opcode : 3; /* * [14:12]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved4 : 1; /* * [15:15] */ + unsigned int ipsurxWol1Rule2WkHost : 2; /* * [17:16]唤醒主机编号。 */ + unsigned int reserved3 : 2; /* * [19:18] */ + unsigned int + ipsurxWol1ChkRule2Opcode : 3; /* * [22:20]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved2 : 1; /* * [23:23] */ + unsigned int ipsurxWol1Rule3WkHost : 2; /* * [25:24]唤醒主机编号。 */ + unsigned int reserved1 : 2; /* * [27:26] */ + unsigned int + ipsurxWol1ChkRule3Opcode : 3; /* * [30:28]WOL + * TYPE1报文的检测方式。3'b000：不根据该条规则检测；3'b001：检测DMAC；3'b010：检测magic报文；3'b011：检测IPv4 + * ARP报文；3'b100：检测IPv4 + * 报文；3'b101：检测IPv6报文；others：保留。 + */ + unsigned int reserved0 : 1; /* * [31:31] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_CTRL0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7MacH { + struct tagStIpsurxWol1ChkRule7MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule7MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule7MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7MacL { + struct tagStIpsurxWol1ChkRule7MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule7MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6MacH { + struct tagStIpsurxWol1ChkRule6MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule6MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule6MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6MacL { + struct tagStIpsurxWol1ChkRule6MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule6MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5MacH { + struct tagStIpsurxWol1ChkRule5MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule5MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule5MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5MacL { + struct tagStIpsurxWol1ChkRule5MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule5MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4MacH { + struct tagStIpsurxWol1ChkRule4MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule4MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule4MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4MacL { + struct tagStIpsurxWol1ChkRule4MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule4MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3MacH { + struct tagStIpsurxWol1ChkRule3MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule3MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule3MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3MacL { + struct tagStIpsurxWol1ChkRule3MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule3MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2MacH { + struct tagStIpsurxWol1ChkRule2MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule2MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule2MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2MacL { + struct tagStIpsurxWol1ChkRule2MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule2MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1MacH { + struct tagStIpsurxWol1ChkRule1MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule1MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule1MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1MacL { + struct tagStIpsurxWol1ChkRule1MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule1MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_MAC_H + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0MacH { + struct tagStIpsurxWol1ChkRule0MacH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule0MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ +#else + unsigned int ipsurxWol1ChkRule0MacaddrH : 16; /* * [15:0]WOL TYPE1报文检测的MAC ADDR高16比特。 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_MAC_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_MAC_L + * @brief WOL TYPE1报文检测RULE MAC ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0MacL { + struct tagStIpsurxWol1ChkRule0MacL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#else + unsigned int ipsurxWol1ChkRule0MacaddrL : 32; /* * [31:0]WOL TYPE1报文检测的MAC ADDR低32比特。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_MAC_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7Vlanid { + struct tagStIpsurxWol1ChkRule7Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule7Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule7Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule7Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule7Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6Vlanid { + struct tagStIpsurxWol1ChkRule6Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule6Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule6Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule6Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule6Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5Vlanid { + struct tagStIpsurxWol1ChkRule5Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule5Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule5Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule5Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule5Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4Vlanid { + struct tagStIpsurxWol1ChkRule4Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule4Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule4Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule4Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule4Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3Vlanid { + struct tagStIpsurxWol1ChkRule3Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule3Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule3Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule3Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule3Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2Vlanid { + struct tagStIpsurxWol1ChkRule2Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule2Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule2Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule2Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule2Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1Vlanid { + struct tagStIpsurxWol1ChkRule1Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule1Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule1Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule1Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule1Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_VLANID + * @brief WOL TYPE1报文检测RULE VLAN ID寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0Vlanid { + struct tagStIpsurxWol1ChkRule0Vlanid { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 19; /* * [31:13]reserved. */ + unsigned int ipsurxWol1ChkRule0Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int ipsurxWol1ChkRule0Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ +#else + unsigned int ipsurxWol1ChkRule0Vlanid : 12; /* * [11:0]WOL TYPE1报文检测的VLAN ID。 */ + unsigned int ipsurxWol1ChkRule0Vlanen : 1; /* * [12:12]1'b1：如果规则需要，比较VLAN ID；1'b0：始终不比较VLAN + * ID。 + */ + unsigned int reserved : 19; /* * [31:13]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_VLANID_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7IpDw0 { + struct tagStIpsurxWol1ChkRule7IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule7IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7IpDw1 { + struct tagStIpsurxWol1ChkRule7IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule7IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7IpDw2 { + struct tagStIpsurxWol1ChkRule7IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule7IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7IpDw3 { + struct tagStIpsurxWol1ChkRule7IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule7IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6IpDw0 { + struct tagStIpsurxWol1ChkRule6IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule6IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6IpDw1 { + struct tagStIpsurxWol1ChkRule6IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule6IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6IpDw2 { + struct tagStIpsurxWol1ChkRule6IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule6IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6IpDw3 { + struct tagStIpsurxWol1ChkRule6IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule6IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5IpDw0 { + struct tagStIpsurxWol1ChkRule5IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule5IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5IpDw1 { + struct tagStIpsurxWol1ChkRule5IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule5IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5IpDw2 { + struct tagStIpsurxWol1ChkRule5IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule5IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5IpDw3 { + struct tagStIpsurxWol1ChkRule5IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule5IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4IpDw0 { + struct tagStIpsurxWol1ChkRule4IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule4IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4IpDw1 { + struct tagStIpsurxWol1ChkRule4IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule4IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4IpDw2 { + struct tagStIpsurxWol1ChkRule4IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule4IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4IpDw3 { + struct tagStIpsurxWol1ChkRule4IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule4IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3IpDw0 { + struct tagStIpsurxWol1ChkRule3IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule3IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3IpDw1 { + struct tagStIpsurxWol1ChkRule3IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule3IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3IpDw2 { + struct tagStIpsurxWol1ChkRule3IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule3IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3IpDw3 { + struct tagStIpsurxWol1ChkRule3IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule3IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2IpDw0 { + struct tagStIpsurxWol1ChkRule2IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule2IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2IpDw1 { + struct tagStIpsurxWol1ChkRule2IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule2IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2IpDw2 { + struct tagStIpsurxWol1ChkRule2IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule2IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2IpDw3 { + struct tagStIpsurxWol1ChkRule2IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule2IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1IpDw0 { + struct tagStIpsurxWol1ChkRule1IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule1IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1IpDw1 { + struct tagStIpsurxWol1ChkRule1IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule1IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1IpDw2 { + struct tagStIpsurxWol1ChkRule1IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule1IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1IpDw3 { + struct tagStIpsurxWol1ChkRule1IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule1IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_IP_DW3_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_IP_DW0 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0IpDw0 { + struct tagStIpsurxWol1ChkRule0IpDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#else + unsigned int ipsurxWol1ChkRule0IpDw0 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[127:96]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_IP_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_IP_DW1 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0IpDw1 { + struct tagStIpsurxWol1ChkRule0IpDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#else + unsigned int ipsurxWol1ChkRule0IpDw1 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[95:64]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_IP_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_IP_DW2 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0IpDw2 { + struct tagStIpsurxWol1ChkRule0IpDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#else + unsigned int ipsurxWol1ChkRule0IpDw2 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[63:32]。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_IP_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_IP_DW3 + * @brief WOL TYPE1报文检测RULE IP地址寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0IpDw3 { + struct tagStIpsurxWol1ChkRule0IpDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#else + unsigned int ipsurxWol1ChkRule0IpDw3 : 32; /* * [31:0]WOL TYPE1报文检测的IPv6 地址[31:0]或者IPv4地址。 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_IP_DW3_U; + + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7NodeAddrH { + struct tagStIpsurxWol1ChkRule7NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule7NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule7NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE7_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule7NodeAddrL { + struct tagStIpsurxWol1ChkRule7NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule7NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule7NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE7_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6NodeAddrH { + struct tagStIpsurxWol1ChkRule6NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule6NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule6NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE6_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule6NodeAddrL { + struct tagStIpsurxWol1ChkRule6NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule6NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule6NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE6_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5NodeAddrH { + struct tagStIpsurxWol1ChkRule5NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule5NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule5NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE5_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule5NodeAddrL { + struct tagStIpsurxWol1ChkRule5NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule5NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule5NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE5_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4NodeAddrH { + struct tagStIpsurxWol1ChkRule4NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule4NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule4NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE4_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule4NodeAddrL { + struct tagStIpsurxWol1ChkRule4NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule4NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule4NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE4_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3NodeAddrH { + struct tagStIpsurxWol1ChkRule3NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule3NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule3NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE3_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule3NodeAddrL { + struct tagStIpsurxWol1ChkRule3NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule3NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule3NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE3_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2NodeAddrH { + struct tagStIpsurxWol1ChkRule2NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule2NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule2NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE2_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule2NodeAddrL { + struct tagStIpsurxWol1ChkRule2NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule2NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule2NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE2_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1NodeAddrH { + struct tagStIpsurxWol1ChkRule1NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule1NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule1NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE1_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule1NodeAddrL { + struct tagStIpsurxWol1ChkRule1NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule1NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule1NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE1_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_NODE_ADDR_H + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0NodeAddrH { + struct tagStIpsurxWol1ChkRule0NodeAddrH { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 16; /* * [31:16] */ + unsigned int ipsurxWol1ChkRule0NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ +#else + unsigned int ipsurxWol1ChkRule0NodeAddrH : 16; /* * [15:0]MAGIC报文检测的NODE ADDR高16比特 */ + unsigned int reserved : 16; /* * [31:16] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_NODE_ADDR_H_U; + +/* ** + * Union name : IPSURX_WOL1_CHK_RULE0_NODE_ADDR_L + * @brief MAGIC报文检测RULE NODE ADDR寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1ChkRule0NodeAddrL { + struct tagStIpsurxWol1ChkRule0NodeAddrL { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol1ChkRule0NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#else + unsigned int ipsurxWol1ChkRule0NodeAddrL : 32; /* * [31:0]MAGIC报文检测的NODE ADDR低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_CHK_RULE0_NODE_ADDR_L_U; + +/* ** + * Union name : IPSURX_WOL1_MAGIC_CHK_STATUS_DW0 + * @brief WOL magic报文检测状态寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1MagicChkStatusDw0 { + struct tagStIpsurxWol1MagicChkStatusDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol1P7rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#else + unsigned int + ipsurxWol1P6rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P6rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P7rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_MAGIC_CHK_STATUS_DW0_U; + +/* ** + * Union name : IPSURX_WOL1_MAGIC_CHK_STATUS_DW1 + * @brief WOL magic报文检测状态寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1MagicChkStatusDw1 { + struct tagStIpsurxWol1MagicChkStatusDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol1P5rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#else + unsigned int + ipsurxWol1P4rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P4rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P5rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_MAGIC_CHK_STATUS_DW1_U; + +/* ** + * Union name : IPSURX_WOL1_MAGIC_CHK_STATUS_DW2 + * @brief WOL magic报文检测状态寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1MagicChkStatusDw2 { + struct tagStIpsurxWol1MagicChkStatusDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol1P3rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#else + unsigned int + ipsurxWol1P2rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P2rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P3rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_MAGIC_CHK_STATUS_DW2_U; + +/* ** + * Union name : IPSURX_WOL1_MAGIC_CHK_STATUS_DW3 + * @brief WOL magic报文检测状态寄存器 + * Description: + */ +typedef union tagUnIpsurxWol1MagicChkStatusDw3 { + struct tagStIpsurxWol1MagicChkStatusDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol1P1rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#else + unsigned int + ipsurxWol1P0rl0MagicChkStatus : 2; /* * [1:0]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl1MagicChkStatus : 2; /* * [3:2]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl2MagicChkStatus : 2; /* * [5:4]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl3MagicChkStatus : 2; /* * [7:6]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl4MagicChkStatus : 2; /* * [9:8]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl5MagicChkStatus : 2; /* * [11:10]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl6MagicChkStatus : 2; /* * [13:12]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P0rl7MagicChkStatus : 2; /* * [15:14]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl0MagicChkStatus : 2; /* * [17:16]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl1MagicChkStatus : 2; /* * [19:18]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl2MagicChkStatus : 2; /* * [21:20]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl3MagicChkStatus : 2; /* * [23:22]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl4MagicChkStatus : 2; /* * [25:24]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl5MagicChkStatus : 2; /* * [27:26]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl6MagicChkStatus : 2; /* * [29:28]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ + unsigned int + ipsurxWol1P1rl7MagicChkStatus : 2; /* * [31:30]WOL + * MAGIC报文检测状态寄存器。2'b00：MAGIC_INI_ST；2'b01：MAGIC_SYN_FF_ST；2'b10：MAGIC_CMP_DMAC_ST1；2'b11：MAGIC_CMP_DMAC_ST2。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL1_MAGIC_CHK_STATUS_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_CTRL + * @brief WOL TYPE2报文检测控制寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkCtrl { + struct tagStIpsurxWol2ChkCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 9; /* * [31:23] */ + unsigned int ipsurxWol2ChkRule5Valid : 1; /* * + [22:22]rule5用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule5WkHost : 2; /* * [21:20]rule5唤醒主机编号。 */ + unsigned int reserved1 : 1; /* * [19:19] */ + unsigned int ipsurxWol2ChkRule4Valid : 1; /* * + [18:18]rule4用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule4WkHost : 2; /* * [17:16]rule4唤醒主机编号。 */ + unsigned int reserved2 : 1; /* * [15:15] */ + unsigned int ipsurxWol2ChkRule3Valid : 1; /* * + [14:14]rule3用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule3WkHost : 2; /* * [13:12]rule3唤醒主机编号。 */ + unsigned int reserved3 : 1; /* * [11:11] */ + unsigned int ipsurxWol2ChkRule2Valid : 1; /* * + [10:10]rule2用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule2WkHost : 2; /* * [9:8]rule2唤醒主机编号。 */ + unsigned int reserved4 : 1; /* * [7:7] */ + unsigned int ipsurxWol2ChkRule1Valid : 1; /* * + [6:6]rule1用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule1WkHost : 2; /* * [5:4]rule1唤醒主机编号。 */ + unsigned int reserved5 : 1; /* * [3:3] */ + unsigned int ipsurxWol2ChkRule0Valid : 1; /* * + [2:2]rule0用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int ipsurxWol2ChkRule0WkHost : 2; /* * [1:0]rule0唤醒主机编号。 */ +#else + unsigned int ipsurxWol2ChkRule0WkHost : 2; /* * [1:0]rule0唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule0Valid : 1; /* * + [2:2]rule0用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved5 : 1; /* * [3:3] */ + unsigned int ipsurxWol2ChkRule1WkHost : 2; /* * [5:4]rule1唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule1Valid : 1; /* * + [6:6]rule1用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved4 : 1; /* * [7:7] */ + unsigned int ipsurxWol2ChkRule2WkHost : 2; /* * [9:8]rule2唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule2Valid : 1; /* * + [10:10]rule2用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved3 : 1; /* * [11:11] */ + unsigned int ipsurxWol2ChkRule3WkHost : 2; /* * [13:12]rule3唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule3Valid : 1; /* * + [14:14]rule3用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved2 : 1; /* * [15:15] */ + unsigned int ipsurxWol2ChkRule4WkHost : 2; /* * [17:16]rule4唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule4Valid : 1; /* * + [18:18]rule4用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved1 : 1; /* * [19:19] */ + unsigned int ipsurxWol2ChkRule5WkHost : 2; /* * [21:20]rule5唤醒主机编号。 */ + unsigned int ipsurxWol2ChkRule5Valid : 1; /* * + [22:22]rule5用户自定义报文有效标志。1'b0：无效，不对该对规则进行匹配检查；1'b1：有效。 + */ + unsigned int reserved0 : 9; /* * [31:23] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_CTRL_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE5_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule5MaskDw0 { + struct tagStIpsurxWol2ChkRule5MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule5MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule5MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE5_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE5_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule5MaskDw1 { + struct tagStIpsurxWol2ChkRule5MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule5MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule5MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE5_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE5_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule5MaskDw2 { + struct tagStIpsurxWol2ChkRule5MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule5MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule5MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE5_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE5_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule5MaskDw3 { + struct tagStIpsurxWol2ChkRule5MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule5MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule5MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE5_MASK_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE4_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule4MaskDw0 { + struct tagStIpsurxWol2ChkRule4MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule4MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule4MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE4_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE4_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule4MaskDw1 { + struct tagStIpsurxWol2ChkRule4MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule4MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule4MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE4_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE4_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule4MaskDw2 { + struct tagStIpsurxWol2ChkRule4MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule4MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule4MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE4_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE4_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule4MaskDw3 { + struct tagStIpsurxWol2ChkRule4MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule4MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule4MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE4_MASK_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE3_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule3MaskDw0 { + struct tagStIpsurxWol2ChkRule3MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule3MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule3MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE3_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE3_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule3MaskDw1 { + struct tagStIpsurxWol2ChkRule3MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule3MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule3MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE3_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE3_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule3MaskDw2 { + struct tagStIpsurxWol2ChkRule3MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule3MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule3MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE3_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE3_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule3MaskDw3 { + struct tagStIpsurxWol2ChkRule3MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule3MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule3MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE3_MASK_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE2_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule2MaskDw0 { + struct tagStIpsurxWol2ChkRule2MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule2MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule2MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE2_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE2_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule2MaskDw1 { + struct tagStIpsurxWol2ChkRule2MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule2MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule2MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE2_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE2_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule2MaskDw2 { + struct tagStIpsurxWol2ChkRule2MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule2MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule2MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE2_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE2_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule2MaskDw3 { + struct tagStIpsurxWol2ChkRule2MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule2MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule2MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE2_MASK_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE1_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule1MaskDw0 { + struct tagStIpsurxWol2ChkRule1MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule1MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule1MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE1_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE1_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule1MaskDw1 { + struct tagStIpsurxWol2ChkRule1MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule1MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule1MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE1_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE1_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule1MaskDw2 { + struct tagStIpsurxWol2ChkRule1MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule1MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule1MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE1_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE1_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule1MaskDw3 { + struct tagStIpsurxWol2ChkRule1MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule1MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule1MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE1_MASK_DW3_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE0_MASK_DW0 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule0MaskDw0 { + struct tagStIpsurxWol2ChkRule0MaskDw0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule0MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule0MaskDw0 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器高32比特[127：96]。Bit[i](i=127~96)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE0_MASK_DW0_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE0_MASK_DW1 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule0MaskDw1 { + struct tagStIpsurxWol2ChkRule0MaskDw1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule0MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule0MaskDw1 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[95：64]。Bit[i](i=95~64)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE0_MASK_DW1_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE0_MASK_DW2 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule0MaskDw2 { + struct tagStIpsurxWol2ChkRule0MaskDw2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule0MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule0MaskDw2 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器比特[63：32]。Bit[i](i=63~32)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE0_MASK_DW2_U; + +/* ** + * Union name : IPSURX_WOL2_CHK_RULE0_MASK_DW3 + * @brief WOL TYPE2报文检测RULE屏蔽寄存器 + * Description: + */ +typedef union tagUnIpsurxWol2ChkRule0MaskDw3 { + struct tagStIpsurxWol2ChkRule0MaskDw3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxWol2ChkRule0MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#else + unsigned int + ipsurxWol2ChkRule0MaskDw3 : 32; /* * [31:0]WOL + * TYPE2报文检测屏蔽寄存器低32比特[31：0]。Bit[i](i=31~0)指示屏蔽packet + * data的字节i。1'b1: 比较packet data的byte[i]；1'b0: 不比较packet + * data的byte[i]。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_CHK_RULE0_MASK_DW3_U; + + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw00 { + struct tagStIpsurxWol2Rule5PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule5PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw01 { + struct tagStIpsurxWol2Rule5PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule5PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw02 { + struct tagStIpsurxWol2Rule5PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule5PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw03 { + struct tagStIpsurxWol2Rule5PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule5PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw04 { + struct tagStIpsurxWol2Rule5PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule5PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw05 { + struct tagStIpsurxWol2Rule5PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule5PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw06 { + struct tagStIpsurxWol2Rule5PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule5PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw07 { + struct tagStIpsurxWol2Rule5PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule5PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw08 { + struct tagStIpsurxWol2Rule5PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule5PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw09 { + struct tagStIpsurxWol2Rule5PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule5PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw10 { + struct tagStIpsurxWol2Rule5PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule5PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw11 { + struct tagStIpsurxWol2Rule5PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule5PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw12 { + struct tagStIpsurxWol2Rule5PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule5PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw13 { + struct tagStIpsurxWol2Rule5PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule5PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw14 { + struct tagStIpsurxWol2Rule5PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule5PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw15 { + struct tagStIpsurxWol2Rule5PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule5PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw16 { + struct tagStIpsurxWol2Rule5PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule5PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw17 { + struct tagStIpsurxWol2Rule5PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule5PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw18 { + struct tagStIpsurxWol2Rule5PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule5PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw19 { + struct tagStIpsurxWol2Rule5PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule5PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw20 { + struct tagStIpsurxWol2Rule5PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule5PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw21 { + struct tagStIpsurxWol2Rule5PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule5PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw22 { + struct tagStIpsurxWol2Rule5PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule5PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw23 { + struct tagStIpsurxWol2Rule5PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule5PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw24 { + struct tagStIpsurxWol2Rule5PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule5PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw25 { + struct tagStIpsurxWol2Rule5PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule5PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw26 { + struct tagStIpsurxWol2Rule5PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule5PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw27 { + struct tagStIpsurxWol2Rule5PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule5PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw28 { + struct tagStIpsurxWol2Rule5PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule5PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw29 { + struct tagStIpsurxWol2Rule5PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule5PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw30 { + struct tagStIpsurxWol2Rule5PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule5PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE5_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule5PktDw31 { + struct tagStIpsurxWol2Rule5PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule5PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule5PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE5_PKT_DW31_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw00 { + struct tagStIpsurxWol2Rule4PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule4PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw01 { + struct tagStIpsurxWol2Rule4PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule4PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw02 { + struct tagStIpsurxWol2Rule4PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule4PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw03 { + struct tagStIpsurxWol2Rule4PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule4PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw04 { + struct tagStIpsurxWol2Rule4PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule4PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw05 { + struct tagStIpsurxWol2Rule4PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule4PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw06 { + struct tagStIpsurxWol2Rule4PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule4PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw07 { + struct tagStIpsurxWol2Rule4PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule4PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw08 { + struct tagStIpsurxWol2Rule4PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule4PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw09 { + struct tagStIpsurxWol2Rule4PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule4PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw10 { + struct tagStIpsurxWol2Rule4PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule4PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw11 { + struct tagStIpsurxWol2Rule4PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule4PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw12 { + struct tagStIpsurxWol2Rule4PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule4PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw13 { + struct tagStIpsurxWol2Rule4PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule4PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw14 { + struct tagStIpsurxWol2Rule4PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule4PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw15 { + struct tagStIpsurxWol2Rule4PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule4PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw16 { + struct tagStIpsurxWol2Rule4PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule4PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw17 { + struct tagStIpsurxWol2Rule4PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule4PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw18 { + struct tagStIpsurxWol2Rule4PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule4PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw19 { + struct tagStIpsurxWol2Rule4PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule4PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw20 { + struct tagStIpsurxWol2Rule4PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule4PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw21 { + struct tagStIpsurxWol2Rule4PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule4PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw22 { + struct tagStIpsurxWol2Rule4PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule4PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw23 { + struct tagStIpsurxWol2Rule4PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule4PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw24 { + struct tagStIpsurxWol2Rule4PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule4PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw25 { + struct tagStIpsurxWol2Rule4PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule4PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw26 { + struct tagStIpsurxWol2Rule4PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule4PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw27 { + struct tagStIpsurxWol2Rule4PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule4PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw28 { + struct tagStIpsurxWol2Rule4PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule4PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw29 { + struct tagStIpsurxWol2Rule4PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule4PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw30 { + struct tagStIpsurxWol2Rule4PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule4PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE4_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule4PktDw31 { + struct tagStIpsurxWol2Rule4PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule4PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule4PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE4_PKT_DW31_U; + + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw00 { + struct tagStIpsurxWol2Rule3PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule3PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw01 { + struct tagStIpsurxWol2Rule3PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule3PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw02 { + struct tagStIpsurxWol2Rule3PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule3PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw03 { + struct tagStIpsurxWol2Rule3PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule3PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw04 { + struct tagStIpsurxWol2Rule3PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule3PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw05 { + struct tagStIpsurxWol2Rule3PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule3PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw06 { + struct tagStIpsurxWol2Rule3PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule3PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw07 { + struct tagStIpsurxWol2Rule3PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule3PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw08 { + struct tagStIpsurxWol2Rule3PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule3PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw09 { + struct tagStIpsurxWol2Rule3PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule3PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw10 { + struct tagStIpsurxWol2Rule3PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule3PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw11 { + struct tagStIpsurxWol2Rule3PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule3PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw12 { + struct tagStIpsurxWol2Rule3PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule3PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw13 { + struct tagStIpsurxWol2Rule3PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule3PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw14 { + struct tagStIpsurxWol2Rule3PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule3PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw15 { + struct tagStIpsurxWol2Rule3PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule3PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw16 { + struct tagStIpsurxWol2Rule3PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule3PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw17 { + struct tagStIpsurxWol2Rule3PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule3PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw18 { + struct tagStIpsurxWol2Rule3PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule3PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw19 { + struct tagStIpsurxWol2Rule3PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule3PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw20 { + struct tagStIpsurxWol2Rule3PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule3PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw21 { + struct tagStIpsurxWol2Rule3PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule3PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw22 { + struct tagStIpsurxWol2Rule3PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule3PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw23 { + struct tagStIpsurxWol2Rule3PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule3PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw24 { + struct tagStIpsurxWol2Rule3PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule3PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw25 { + struct tagStIpsurxWol2Rule3PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule3PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw26 { + struct tagStIpsurxWol2Rule3PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule3PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw27 { + struct tagStIpsurxWol2Rule3PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule3PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw28 { + struct tagStIpsurxWol2Rule3PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule3PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw29 { + struct tagStIpsurxWol2Rule3PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule3PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw30 { + struct tagStIpsurxWol2Rule3PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule3PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE3_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule3PktDw31 { + struct tagStIpsurxWol2Rule3PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule3PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule3PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE3_PKT_DW31_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw00 { + struct tagStIpsurxWol2Rule2PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule2PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw01 { + struct tagStIpsurxWol2Rule2PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule2PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw02 { + struct tagStIpsurxWol2Rule2PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule2PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw03 { + struct tagStIpsurxWol2Rule2PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule2PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw04 { + struct tagStIpsurxWol2Rule2PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule2PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw05 { + struct tagStIpsurxWol2Rule2PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule2PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw06 { + struct tagStIpsurxWol2Rule2PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule2PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw07 { + struct tagStIpsurxWol2Rule2PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule2PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw08 { + struct tagStIpsurxWol2Rule2PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule2PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw09 { + struct tagStIpsurxWol2Rule2PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule2PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw10 { + struct tagStIpsurxWol2Rule2PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule2PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw11 { + struct tagStIpsurxWol2Rule2PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule2PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw12 { + struct tagStIpsurxWol2Rule2PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule2PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw13 { + struct tagStIpsurxWol2Rule2PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule2PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw14 { + struct tagStIpsurxWol2Rule2PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule2PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw15 { + struct tagStIpsurxWol2Rule2PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule2PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw16 { + struct tagStIpsurxWol2Rule2PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule2PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw17 { + struct tagStIpsurxWol2Rule2PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule2PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw18 { + struct tagStIpsurxWol2Rule2PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule2PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw19 { + struct tagStIpsurxWol2Rule2PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule2PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw20 { + struct tagStIpsurxWol2Rule2PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule2PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw21 { + struct tagStIpsurxWol2Rule2PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule2PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw22 { + struct tagStIpsurxWol2Rule2PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule2PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw23 { + struct tagStIpsurxWol2Rule2PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule2PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw24 { + struct tagStIpsurxWol2Rule2PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule2PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw25 { + struct tagStIpsurxWol2Rule2PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule2PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw26 { + struct tagStIpsurxWol2Rule2PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule2PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw27 { + struct tagStIpsurxWol2Rule2PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule2PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw28 { + struct tagStIpsurxWol2Rule2PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule2PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw29 { + struct tagStIpsurxWol2Rule2PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule2PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw30 { + struct tagStIpsurxWol2Rule2PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule2PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE2_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule2PktDw31 { + struct tagStIpsurxWol2Rule2PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule2PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule2PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE2_PKT_DW31_U; + + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw00 { + struct tagStIpsurxWol2Rule1PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule1PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw01 { + struct tagStIpsurxWol2Rule1PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule1PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw02 { + struct tagStIpsurxWol2Rule1PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule1PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw03 { + struct tagStIpsurxWol2Rule1PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule1PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw04 { + struct tagStIpsurxWol2Rule1PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule1PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw05 { + struct tagStIpsurxWol2Rule1PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule1PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw06 { + struct tagStIpsurxWol2Rule1PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule1PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw07 { + struct tagStIpsurxWol2Rule1PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule1PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw08 { + struct tagStIpsurxWol2Rule1PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule1PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw09 { + struct tagStIpsurxWol2Rule1PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule1PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw10 { + struct tagStIpsurxWol2Rule1PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule1PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw11 { + struct tagStIpsurxWol2Rule1PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule1PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw12 { + struct tagStIpsurxWol2Rule1PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule1PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw13 { + struct tagStIpsurxWol2Rule1PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule1PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw14 { + struct tagStIpsurxWol2Rule1PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule1PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw15 { + struct tagStIpsurxWol2Rule1PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule1PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw16 { + struct tagStIpsurxWol2Rule1PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule1PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw17 { + struct tagStIpsurxWol2Rule1PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule1PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw18 { + struct tagStIpsurxWol2Rule1PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule1PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw19 { + struct tagStIpsurxWol2Rule1PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule1PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw20 { + struct tagStIpsurxWol2Rule1PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule1PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw21 { + struct tagStIpsurxWol2Rule1PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule1PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw22 { + struct tagStIpsurxWol2Rule1PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule1PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw23 { + struct tagStIpsurxWol2Rule1PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule1PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw24 { + struct tagStIpsurxWol2Rule1PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule1PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw25 { + struct tagStIpsurxWol2Rule1PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule1PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw26 { + struct tagStIpsurxWol2Rule1PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule1PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw27 { + struct tagStIpsurxWol2Rule1PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule1PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw28 { + struct tagStIpsurxWol2Rule1PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule1PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw29 { + struct tagStIpsurxWol2Rule1PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule1PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw30 { + struct tagStIpsurxWol2Rule1PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule1PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE1_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule1PktDw31 { + struct tagStIpsurxWol2Rule1PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule1PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule1PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE1_PKT_DW31_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW00 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw00 { + struct tagStIpsurxWol2Rule0PktDw00 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#else + unsigned int ipsurxWol2Rule0PktDw00 : 32; /* * [31:0]128字节用户自定义报文后DWORD00，对应128字节报文的高32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW00_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW01 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw01 { + struct tagStIpsurxWol2Rule0PktDw01 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#else + unsigned int ipsurxWol2Rule0PktDw01 : 32; /* * [31:0]128字节用户自定义报文后DWORD01 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW01_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW02 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw02 { + struct tagStIpsurxWol2Rule0PktDw02 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#else + unsigned int ipsurxWol2Rule0PktDw02 : 32; /* * [31:0]128字节用户自定义报文后DWORD02 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW02_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW03 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw03 { + struct tagStIpsurxWol2Rule0PktDw03 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#else + unsigned int ipsurxWol2Rule0PktDw03 : 32; /* * [31:0]128字节用户自定义报文后DWORD03 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW03_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW04 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw04 { + struct tagStIpsurxWol2Rule0PktDw04 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#else + unsigned int ipsurxWol2Rule0PktDw04 : 32; /* * [31:0]128字节用户自定义报文后DWORD04 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW04_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW05 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw05 { + struct tagStIpsurxWol2Rule0PktDw05 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#else + unsigned int ipsurxWol2Rule0PktDw05 : 32; /* * [31:0]128字节用户自定义报文后DWORD05 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW05_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW06 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw06 { + struct tagStIpsurxWol2Rule0PktDw06 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#else + unsigned int ipsurxWol2Rule0PktDw06 : 32; /* * [31:0]128字节用户自定义报文后DWORD06 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW06_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW07 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw07 { + struct tagStIpsurxWol2Rule0PktDw07 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#else + unsigned int ipsurxWol2Rule0PktDw07 : 32; /* * [31:0]128字节用户自定义报文后DWORD07 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW07_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW08 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw08 { + struct tagStIpsurxWol2Rule0PktDw08 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#else + unsigned int ipsurxWol2Rule0PktDw08 : 32; /* * [31:0]128字节用户自定义报文后DWORD08 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW08_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW09 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw09 { + struct tagStIpsurxWol2Rule0PktDw09 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#else + unsigned int ipsurxWol2Rule0PktDw09 : 32; /* * [31:0]128字节用户自定义报文后DWORD09 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW09_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW10 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw10 { + struct tagStIpsurxWol2Rule0PktDw10 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#else + unsigned int ipsurxWol2Rule0PktDw10 : 32; /* * [31:0]128字节用户自定义报文后DWORD10 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW10_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW11 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw11 { + struct tagStIpsurxWol2Rule0PktDw11 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#else + unsigned int ipsurxWol2Rule0PktDw11 : 32; /* * [31:0]128字节用户自定义报文后DWORD11 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW11_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW12 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw12 { + struct tagStIpsurxWol2Rule0PktDw12 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#else + unsigned int ipsurxWol2Rule0PktDw12 : 32; /* * [31:0]128字节用户自定义报文后DWORD12 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW12_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW13 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw13 { + struct tagStIpsurxWol2Rule0PktDw13 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#else + unsigned int ipsurxWol2Rule0PktDw13 : 32; /* * [31:0]128字节用户自定义报文后DWORD13 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW13_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW14 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw14 { + struct tagStIpsurxWol2Rule0PktDw14 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#else + unsigned int ipsurxWol2Rule0PktDw14 : 32; /* * [31:0]128字节用户自定义报文后DWORD14 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW14_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW15 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw15 { + struct tagStIpsurxWol2Rule0PktDw15 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#else + unsigned int ipsurxWol2Rule0PktDw15 : 32; /* * [31:0]128字节用户自定义报文后DWORD15 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW15_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW16 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw16 { + struct tagStIpsurxWol2Rule0PktDw16 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#else + unsigned int ipsurxWol2Rule0PktDw16 : 32; /* * [31:0]128字节用户自定义报文后DWORD16 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW16_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW17 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw17 { + struct tagStIpsurxWol2Rule0PktDw17 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#else + unsigned int ipsurxWol2Rule0PktDw17 : 32; /* * [31:0]128字节用户自定义报文后DWORD17 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW17_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW18 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw18 { + struct tagStIpsurxWol2Rule0PktDw18 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#else + unsigned int ipsurxWol2Rule0PktDw18 : 32; /* * [31:0]128字节用户自定义报文后DWORD18 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW18_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW19 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw19 { + struct tagStIpsurxWol2Rule0PktDw19 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#else + unsigned int ipsurxWol2Rule0PktDw19 : 32; /* * [31:0]128字节用户自定义报文后DWORD19 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW19_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW20 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw20 { + struct tagStIpsurxWol2Rule0PktDw20 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#else + unsigned int ipsurxWol2Rule0PktDw20 : 32; /* * [31:0]128字节用户自定义报文后DWORD20 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW20_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW21 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw21 { + struct tagStIpsurxWol2Rule0PktDw21 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#else + unsigned int ipsurxWol2Rule0PktDw21 : 32; /* * [31:0]128字节用户自定义报文后DWORD21 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW21_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW22 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw22 { + struct tagStIpsurxWol2Rule0PktDw22 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#else + unsigned int ipsurxWol2Rule0PktDw22 : 32; /* * [31:0]128字节用户自定义报文后DWORD22 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW22_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW23 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw23 { + struct tagStIpsurxWol2Rule0PktDw23 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#else + unsigned int ipsurxWol2Rule0PktDw23 : 32; /* * [31:0]128字节用户自定义报文后DWORD23 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW23_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW24 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw24 { + struct tagStIpsurxWol2Rule0PktDw24 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#else + unsigned int ipsurxWol2Rule0PktDw24 : 32; /* * [31:0]128字节用户自定义报文后DWORD24 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW24_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW25 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw25 { + struct tagStIpsurxWol2Rule0PktDw25 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#else + unsigned int ipsurxWol2Rule0PktDw25 : 32; /* * [31:0]128字节用户自定义报文后DWORD25 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW25_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW26 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw26 { + struct tagStIpsurxWol2Rule0PktDw26 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#else + unsigned int ipsurxWol2Rule0PktDw26 : 32; /* * [31:0]128字节用户自定义报文后DWORD26 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW26_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW27 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw27 { + struct tagStIpsurxWol2Rule0PktDw27 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#else + unsigned int ipsurxWol2Rule0PktDw27 : 32; /* * [31:0]128字节用户自定义报文后DWORD27 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW27_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW28 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw28 { + struct tagStIpsurxWol2Rule0PktDw28 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#else + unsigned int ipsurxWol2Rule0PktDw28 : 32; /* * [31:0]128字节用户自定义报文后DWORD28 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW28_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW29 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw29 { + struct tagStIpsurxWol2Rule0PktDw29 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#else + unsigned int ipsurxWol2Rule0PktDw29 : 32; /* * [31:0]128字节用户自定义报文后DWORD29 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW29_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW30 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw30 { + struct tagStIpsurxWol2Rule0PktDw30 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#else + unsigned int ipsurxWol2Rule0PktDw30 : 32; /* * [31:0]128字节用户自定义报文后DWORD30 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW30_U; + +/* ** + * Union name : IPSURX_WOL2_RULE0_PKT_DW31 + * @brief WOL TYPE2 RULE用户自定义报文 + * Description: + */ +typedef union tagUnIpsurxWol2Rule0PktDw31 { + struct tagStIpsurxWol2Rule0PktDw31 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxWol2Rule0PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#else + unsigned int ipsurxWol2Rule0PktDw31 : 32; /* * [31:0]128字节用户自定义报文后DWORD31，对应128字节报文的低32比特 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_WOL2_RULE0_PKT_DW31_U; + + +/* ** + * Union name : IPSURX_LLI_TYPE7 + * @brief LLI报文TYPE7寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType7 { + struct tagStIpsurxLliType7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType7Vld : 1; /* * [16:16]LLI报文TYPE7 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType7 : 16; /* * [15:0]LLI报文Ethernet TYPE7。 */ +#else + unsigned int ipsurxLliType7 : 16; /* * [15:0]LLI报文Ethernet TYPE7。 */ + unsigned int ipsurxLliType7Vld : 1; /* * [16:16]LLI报文TYPE7 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE7_U; + +/* ** + * Union name : IPSURX_LLI_TYPE6 + * @brief LLI报文TYPE6寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType6 { + struct tagStIpsurxLliType6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType6Vld : 1; /* * [16:16]LLI报文TYPE6 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType6 : 16; /* * [15:0]LLI报文Ethernet TYPE6。 */ +#else + unsigned int ipsurxLliType6 : 16; /* * [15:0]LLI报文Ethernet TYPE6。 */ + unsigned int ipsurxLliType6Vld : 1; /* * [16:16]LLI报文TYPE6 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE6_U; + +/* ** + * Union name : IPSURX_LLI_TYPE5 + * @brief LLI报文TYPE5寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType5 { + struct tagStIpsurxLliType5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType5Vld : 1; /* * [16:16]LLI报文TYPE5 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType5 : 16; /* * [15:0]LLI报文Ethernet TYPE5。 */ +#else + unsigned int ipsurxLliType5 : 16; /* * [15:0]LLI报文Ethernet TYPE5。 */ + unsigned int ipsurxLliType5Vld : 1; /* * [16:16]LLI报文TYPE5 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE5_U; + +/* ** + * Union name : IPSURX_LLI_TYPE4 + * @brief LLI报文TYPE4寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType4 { + struct tagStIpsurxLliType4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType4Vld : 1; /* * [16:16]LLI报文TYPE4 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType4 : 16; /* * [15:0]LLI报文Ethernet TYPE4。 */ +#else + unsigned int ipsurxLliType4 : 16; /* * [15:0]LLI报文Ethernet TYPE4。 */ + unsigned int ipsurxLliType4Vld : 1; /* * [16:16]LLI报文TYPE4 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE4_U; + +/* ** + * Union name : IPSURX_LLI_TYPE3 + * @brief LLI报文TYPE3寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType3 { + struct tagStIpsurxLliType3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType3Vld : 1; /* * [16:16]LLI报文TYPE3 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType3 : 16; /* * [15:0]LLI报文Ethernet TYPE3。 */ +#else + unsigned int ipsurxLliType3 : 16; /* * [15:0]LLI报文Ethernet TYPE3。 */ + unsigned int ipsurxLliType3Vld : 1; /* * [16:16]LLI报文TYPE3 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE3_U; + +/* ** + * Union name : IPSURX_LLI_TYPE2 + * @brief LLI报文TYPE2寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType2 { + struct tagStIpsurxLliType2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType2Vld : 1; /* * [16:16]LLI报文TYPE2 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType2 : 16; /* * [15:0]LLI报文Ethernet TYPE2。 */ +#else + unsigned int ipsurxLliType2 : 16; /* * [15:0]LLI报文Ethernet TYPE2。 */ + unsigned int ipsurxLliType2Vld : 1; /* * [16:16]LLI报文TYPE2 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE2_U; + +/* ** + * Union name : IPSURX_LLI_TYPE1 + * @brief LLI报文TYPE1寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType1 { + struct tagStIpsurxLliType1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType1Vld : 1; /* * [16:16]LLI报文TYPE1 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int ipsurxLliType1 : 16; /* * [15:0]LLI报文Ethernet TYPE1。 */ +#else + unsigned int ipsurxLliType1 : 16; /* * [15:0]LLI报文Ethernet TYPE1。 */ + unsigned int ipsurxLliType1Vld : 1; /* * [16:16]LLI报文TYPE1 VALID信号。1'b1：VALID；1'b0：INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE1_U; + +/* ** + * Union name : IPSURX_LLI_TYPE0 + * @brief LLI报文TYPE0寄存器 + * Description: + */ +typedef union tagUnIpsurxLliType0 { + struct tagStIpsurxLliType0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 15; /* * [31:17] */ + unsigned int ipsurxLliType0Vld : 1; /* * [16:16]LLI报文TYPE0 VALID信号。1'b1：VALID；1'b0: INVALID。 */ + unsigned int ipsurxLliType0 : 16; /* * [15:0]LLI报文Ethernet TYPE0。 */ +#else + unsigned int ipsurxLliType0 : 16; /* * [15:0]LLI报文Ethernet TYPE0。 */ + unsigned int ipsurxLliType0Vld : 1; /* * [16:16]LLI报文TYPE0 VALID信号。1'b1：VALID；1'b0: INVALID。 */ + unsigned int reserved : 15; /* * [31:17] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LLI_TYPE0_U; + +/* ** + * Union name : IPSURX_MAC_TB_CTRL + * @brief MAC Table控制寄存器 + * Description: + */ +typedef union tagUnIpsurxMacTbCtrl { + struct tagStIpsurxMacTbCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 24; /* * [31:8]reserved. */ + unsigned int reserved1 : 5; /* * [7:3] */ + unsigned int ipsurxFicMacTbEn : 1; /* * [2:2]通道属性为FIC，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxHg2MacTbEn : 1; /* * [1:1]通道属性为HG2，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxMacMacTbEn : 1; /* * [0:0]通道属性为MAC，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ +#else + unsigned int ipsurxMacMacTbEn : 1; /* * [0:0]通道属性为MAC，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxHg2MacTbEn : 1; /* * [1:1]通道属性为HG2，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxFicMacTbEn : 1; /* * [2:2]通道属性为FIC，MAC table查表使能。1'b0：不使能；1'b1：使能。 */ + unsigned int reserved1 : 5; /* * [7:3] */ + unsigned int reserved0 : 24; /* * [31:8]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_CTRL_U; + +/* ** + * Union name : IPSURX_PORT_ERID7 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid7 { + struct tagStIpsurxPortErid7 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry15Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry15Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry14Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry14Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry14Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry14Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry15Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry15Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID7_U; + +/* ** + * Union name : IPSURX_PORT_ERID6 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid6 { + struct tagStIpsurxPortErid6 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry13Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry13Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry12Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry12Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry12Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry12Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry13Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry13Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID6_U; + +/* ** + * Union name : IPSURX_PORT_ERID5 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid5 { + struct tagStIpsurxPortErid5 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry11Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry11Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry10Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry10Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry10Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry10Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry11Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry11Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID5_U; + +/* ** + * Union name : IPSURX_PORT_ERID4 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid4 { + struct tagStIpsurxPortErid4 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry9Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry9Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry8Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry8Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry8Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry8Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry9Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry9Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID4_U; + +/* ** + * Union name : IPSURX_PORT_ERID3 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid3 { + struct tagStIpsurxPortErid3 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry7Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry7Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry6Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry6Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry6Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry6Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry7Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry7Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID3_U; + +/* ** + * Union name : IPSURX_PORT_ERID2 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid2 { + struct tagStIpsurxPortErid2 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry5Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry5Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry4Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry4Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry4Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry4Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry5Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry5Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID2_U; + +/* ** + * Union name : IPSURX_PORT_ERID1 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid1 { + struct tagStIpsurxPortErid1 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry3Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry3Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry2Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry2Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry2Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry2Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry3Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry3Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID1_U; + +/* ** + * Union name : IPSURX_PORT_ERID0 + * @brief PORT->ERID表项寄存器 + * Description: + */ +typedef union tagUnIpsurxPortErid0 { + struct tagStIpsurxPortErid0 { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28] */ + unsigned int ipsurxPortEridEntry1Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int + ipsurxPortEridEntry1Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int ipsurxPortEridEntry0Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int + ipsurxPortEridEntry0Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ +#else + unsigned int + ipsurxPortEridEntry0Erid : 5; /* * [4:0]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved3 : 3; /* * [7:5] */ + unsigned int ipsurxPortEridEntry0Port : 4; /* * [11:8]报文入端口。建议使用默认值。 */ + unsigned int reserved2 : 4; /* * [15:12] */ + unsigned int + ipsurxPortEridEntry1Erid : 5; /* * [20:16]Edge relay + * identifier。5'h1F，指示IPSURX无法查找该端口对应的ERID，不用继续查找MAC表。其余值，IPSURX根据该ERID继续查找MAC表。 + */ + unsigned int reserved1 : 3; /* * [23:21] */ + unsigned int ipsurxPortEridEntry1Port : 4; /* * [27:24]报文入端口。建议使用默认值。 */ + unsigned int reserved0 : 4; /* * [31:28] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PORT_ERID0_U; + + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY63_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry63H { + struct tagStIpsurxMacTbEntry63H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry63Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry63MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry63MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry63Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY63_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY63_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry63M { + struct tagStIpsurxMacTbEntry63M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry63MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry63MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY63_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY63_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry63L { + struct tagStIpsurxMacTbEntry63L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry63VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry63Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry63Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry63Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry63Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry63VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY63_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY62_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry62H { + struct tagStIpsurxMacTbEntry62H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry62Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry62MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry62MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry62Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY62_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY62_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry62M { + struct tagStIpsurxMacTbEntry62M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry62MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry62MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY62_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY62_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry62L { + struct tagStIpsurxMacTbEntry62L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry62VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry62Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry62Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry62Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry62Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry62VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY62_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY61_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry61H { + struct tagStIpsurxMacTbEntry61H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry61Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry61MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry61MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry61Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY61_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY61_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry61M { + struct tagStIpsurxMacTbEntry61M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry61MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry61MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY61_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY61_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry61L { + struct tagStIpsurxMacTbEntry61L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry61VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry61Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry61Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry61Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry61Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry61VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY61_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY60_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry60H { + struct tagStIpsurxMacTbEntry60H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry60Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry60MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry60MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry60Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY60_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY60_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry60M { + struct tagStIpsurxMacTbEntry60M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry60MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry60MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY60_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY60_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry60L { + struct tagStIpsurxMacTbEntry60L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry60VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry60Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry60Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry60Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry60Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry60VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY60_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY59_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry59H { + struct tagStIpsurxMacTbEntry59H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry59Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry59MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry59MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry59Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY59_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY59_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry59M { + struct tagStIpsurxMacTbEntry59M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry59MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry59MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY59_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY59_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry59L { + struct tagStIpsurxMacTbEntry59L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry59VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry59Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry59Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry59Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry59Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry59VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY59_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY58_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry58H { + struct tagStIpsurxMacTbEntry58H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry58Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry58MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry58MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry58Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY58_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY58_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry58M { + struct tagStIpsurxMacTbEntry58M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry58MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry58MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY58_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY58_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry58L { + struct tagStIpsurxMacTbEntry58L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry58VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry58Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry58Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry58Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry58Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry58VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY58_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY57_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry57H { + struct tagStIpsurxMacTbEntry57H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry57Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry57MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry57MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry57Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY57_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY57_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry57M { + struct tagStIpsurxMacTbEntry57M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry57MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry57MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY57_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY57_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry57L { + struct tagStIpsurxMacTbEntry57L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry57VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry57Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry57Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry57Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry57Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry57VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY57_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY56_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry56H { + struct tagStIpsurxMacTbEntry56H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry56Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry56MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry56MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry56Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY56_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY56_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry56M { + struct tagStIpsurxMacTbEntry56M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry56MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry56MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY56_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY56_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry56L { + struct tagStIpsurxMacTbEntry56L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry56VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry56Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry56Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry56Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry56Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry56VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY56_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY55_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry55H { + struct tagStIpsurxMacTbEntry55H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry55Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry55MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry55MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry55Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY55_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY55_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry55M { + struct tagStIpsurxMacTbEntry55M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry55MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry55MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY55_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY55_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry55L { + struct tagStIpsurxMacTbEntry55L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry55VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry55Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry55Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry55Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry55Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry55VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY55_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY54_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry54H { + struct tagStIpsurxMacTbEntry54H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry54Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry54MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry54MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry54Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY54_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY54_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry54M { + struct tagStIpsurxMacTbEntry54M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry54MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry54MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY54_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY54_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry54L { + struct tagStIpsurxMacTbEntry54L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry54VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry54Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry54Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry54Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry54Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry54VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY54_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY53_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry53H { + struct tagStIpsurxMacTbEntry53H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry53Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry53MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry53MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry53Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY53_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY53_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry53M { + struct tagStIpsurxMacTbEntry53M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry53MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry53MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY53_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY53_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry53L { + struct tagStIpsurxMacTbEntry53L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry53VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry53Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry53Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry53Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry53Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry53VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY53_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY52_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry52H { + struct tagStIpsurxMacTbEntry52H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry52Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry52MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry52MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry52Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY52_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY52_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry52M { + struct tagStIpsurxMacTbEntry52M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry52MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry52MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY52_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY52_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry52L { + struct tagStIpsurxMacTbEntry52L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry52VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry52Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry52Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry52Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry52Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry52VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY52_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY51_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry51H { + struct tagStIpsurxMacTbEntry51H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry51Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry51MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry51MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry51Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY51_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY51_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry51M { + struct tagStIpsurxMacTbEntry51M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry51MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry51MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY51_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY51_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry51L { + struct tagStIpsurxMacTbEntry51L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry51VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry51Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry51Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry51Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry51Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry51VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY51_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY50_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry50H { + struct tagStIpsurxMacTbEntry50H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry50Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry50MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry50MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry50Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY50_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY50_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry50M { + struct tagStIpsurxMacTbEntry50M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry50MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry50MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY50_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY50_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry50L { + struct tagStIpsurxMacTbEntry50L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry50VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry50Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry50Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry50Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry50Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry50VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY50_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY49_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry49H { + struct tagStIpsurxMacTbEntry49H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry49Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry49MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry49MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry49Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY49_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY49_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry49M { + struct tagStIpsurxMacTbEntry49M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry49MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry49MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY49_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY49_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry49L { + struct tagStIpsurxMacTbEntry49L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry49VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry49Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry49Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry49Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry49Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry49VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY49_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY48_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry48H { + struct tagStIpsurxMacTbEntry48H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry48Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry48MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry48MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry48Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY48_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY48_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry48M { + struct tagStIpsurxMacTbEntry48M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry48MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry48MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY48_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY48_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry48L { + struct tagStIpsurxMacTbEntry48L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry48VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry48Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry48Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry48Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry48Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry48VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY48_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY47_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry47H { + struct tagStIpsurxMacTbEntry47H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry47Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry47MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry47MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry47Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY47_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY47_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry47M { + struct tagStIpsurxMacTbEntry47M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry47MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry47MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY47_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY47_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry47L { + struct tagStIpsurxMacTbEntry47L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry47VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry47Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry47Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry47Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry47Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry47VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY47_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY46_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry46H { + struct tagStIpsurxMacTbEntry46H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry46Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry46MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry46MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry46Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY46_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY46_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry46M { + struct tagStIpsurxMacTbEntry46M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry46MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry46MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY46_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY46_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry46L { + struct tagStIpsurxMacTbEntry46L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry46VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry46Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry46Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry46Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry46Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry46VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY46_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY45_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry45H { + struct tagStIpsurxMacTbEntry45H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry45Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry45MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry45MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry45Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY45_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY45_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry45M { + struct tagStIpsurxMacTbEntry45M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry45MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry45MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY45_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY45_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry45L { + struct tagStIpsurxMacTbEntry45L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry45VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry45Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry45Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry45Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry45Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry45VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY45_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY44_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry44H { + struct tagStIpsurxMacTbEntry44H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry44Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry44MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry44MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry44Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY44_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY44_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry44M { + struct tagStIpsurxMacTbEntry44M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry44MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry44MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY44_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY44_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry44L { + struct tagStIpsurxMacTbEntry44L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry44VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry44Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry44Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry44Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry44Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry44VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY44_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY43_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry43H { + struct tagStIpsurxMacTbEntry43H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry43Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry43MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry43MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry43Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY43_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY43_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry43M { + struct tagStIpsurxMacTbEntry43M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry43MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry43MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY43_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY43_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry43L { + struct tagStIpsurxMacTbEntry43L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry43VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry43Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry43Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry43Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry43Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry43VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY43_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY42_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry42H { + struct tagStIpsurxMacTbEntry42H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry42Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry42MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry42MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry42Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY42_H_U; + + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY42_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry42M { + struct tagStIpsurxMacTbEntry42M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry42MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry42MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY42_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY42_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry42L { + struct tagStIpsurxMacTbEntry42L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry42VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry42Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry42Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry42Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry42Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry42VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY42_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY41_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry41H { + struct tagStIpsurxMacTbEntry41H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry41Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry41MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry41MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry41Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY41_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY41_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry41M { + struct tagStIpsurxMacTbEntry41M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry41MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry41MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY41_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY41_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry41L { + struct tagStIpsurxMacTbEntry41L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry41VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry41Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry41Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry41Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry41Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry41VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY41_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY40_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry40H { + struct tagStIpsurxMacTbEntry40H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry40Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry40MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry40MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry40Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY40_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY40_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry40M { + struct tagStIpsurxMacTbEntry40M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry40MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry40MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY40_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY40_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry40L { + struct tagStIpsurxMacTbEntry40L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry40VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry40Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry40Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry40Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry40Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry40VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY40_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY39_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry39H { + struct tagStIpsurxMacTbEntry39H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry39Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry39MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry39MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry39Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY39_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY39_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry39M { + struct tagStIpsurxMacTbEntry39M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry39MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry39MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY39_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY39_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry39L { + struct tagStIpsurxMacTbEntry39L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry39VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry39Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry39Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry39Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry39Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry39VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY39_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY38_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry38H { + struct tagStIpsurxMacTbEntry38H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry38Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry38MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry38MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry38Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY38_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY38_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry38M { + struct tagStIpsurxMacTbEntry38M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry38MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry38MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY38_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY38_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry38L { + struct tagStIpsurxMacTbEntry38L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry38VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry38Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry38Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry38Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry38Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry38VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY38_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY37_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry37H { + struct tagStIpsurxMacTbEntry37H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry37Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry37MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry37MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry37Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY37_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY37_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry37M { + struct tagStIpsurxMacTbEntry37M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry37MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry37MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY37_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY37_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry37L { + struct tagStIpsurxMacTbEntry37L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry37VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry37Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry37Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry37Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry37Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry37VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY37_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY36_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry36H { + struct tagStIpsurxMacTbEntry36H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry36Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry36MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry36MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry36Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY36_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY36_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry36M { + struct tagStIpsurxMacTbEntry36M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry36MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry36MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY36_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY36_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry36L { + struct tagStIpsurxMacTbEntry36L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry36VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry36Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry36Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry36Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry36Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry36VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY36_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY35_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry35H { + struct tagStIpsurxMacTbEntry35H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry35Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry35MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry35MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry35Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY35_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY35_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry35M { + struct tagStIpsurxMacTbEntry35M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry35MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry35MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY35_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY35_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry35L { + struct tagStIpsurxMacTbEntry35L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry35VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry35Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry35Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry35Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry35Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry35VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY35_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY34_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry34H { + struct tagStIpsurxMacTbEntry34H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry34Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry34MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry34MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry34Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY34_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY34_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry34M { + struct tagStIpsurxMacTbEntry34M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry34MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry34MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY34_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY34_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry34L { + struct tagStIpsurxMacTbEntry34L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry34VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry34Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry34Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry34Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry34Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry34VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY34_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY33_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry33H { + struct tagStIpsurxMacTbEntry33H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry33Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry33MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry33MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry33Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY33_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY33_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry33M { + struct tagStIpsurxMacTbEntry33M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry33MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry33MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY33_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY33_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry33L { + struct tagStIpsurxMacTbEntry33L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry33VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry33Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry33Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry33Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry33Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry33VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY33_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY32_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry32H { + struct tagStIpsurxMacTbEntry32H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry32Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry32MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry32MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry32Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY32_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY32_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry32M { + struct tagStIpsurxMacTbEntry32M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry32MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry32MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY32_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY32_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry32L { + struct tagStIpsurxMacTbEntry32L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry32VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry32Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry32Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry32Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry32Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry32VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY32_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY31_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry31H { + struct tagStIpsurxMacTbEntry31H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry31Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry31MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry31MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry31Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY31_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY31_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry31M { + struct tagStIpsurxMacTbEntry31M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry31MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry31MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY31_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY31_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry31L { + struct tagStIpsurxMacTbEntry31L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry31VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry31Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry31Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry31Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry31Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry31VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY31_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY30_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry30H { + struct tagStIpsurxMacTbEntry30H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry30Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry30MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry30MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry30Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY30_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY30_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry30M { + struct tagStIpsurxMacTbEntry30M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry30MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry30MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY30_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY30_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry30L { + struct tagStIpsurxMacTbEntry30L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry30VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry30Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry30Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry30Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry30Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry30VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY30_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY29_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry29H { + struct tagStIpsurxMacTbEntry29H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry29Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry29MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry29MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry29Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY29_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY29_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry29M { + struct tagStIpsurxMacTbEntry29M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry29MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry29MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY29_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY29_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry29L { + struct tagStIpsurxMacTbEntry29L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry29VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry29Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry29Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry29Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry29Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry29VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY29_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY28_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry28H { + struct tagStIpsurxMacTbEntry28H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry28Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry28MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry28MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry28Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY28_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY28_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry28M { + struct tagStIpsurxMacTbEntry28M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry28MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry28MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY28_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY28_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry28L { + struct tagStIpsurxMacTbEntry28L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry28VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry28Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry28Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry28Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry28Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry28VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY28_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY27_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry27H { + struct tagStIpsurxMacTbEntry27H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry27Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry27MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry27MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry27Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY27_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY27_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry27M { + struct tagStIpsurxMacTbEntry27M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry27MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry27MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY27_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY27_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry27L { + struct tagStIpsurxMacTbEntry27L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry27VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry27Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry27Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry27Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry27Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry27VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY27_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY26_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry26H { + struct tagStIpsurxMacTbEntry26H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry26Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry26MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry26MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry26Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY26_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY26_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry26M { + struct tagStIpsurxMacTbEntry26M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry26MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry26MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY26_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY26_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry26L { + struct tagStIpsurxMacTbEntry26L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry26VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry26Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry26Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry26Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry26Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry26VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY26_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY25_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry25H { + struct tagStIpsurxMacTbEntry25H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry25Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry25MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry25MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry25Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY25_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY25_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry25M { + struct tagStIpsurxMacTbEntry25M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry25MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry25MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY25_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY25_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry25L { + struct tagStIpsurxMacTbEntry25L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry25VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry25Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry25Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry25Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry25Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry25VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY25_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY24_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry24H { + struct tagStIpsurxMacTbEntry24H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry24Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry24MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry24MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry24Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY24_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY24_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry24M { + struct tagStIpsurxMacTbEntry24M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry24MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry24MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY24_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY24_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry24L { + struct tagStIpsurxMacTbEntry24L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry24VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry24Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry24Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry24Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry24Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry24VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY24_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY23_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry23H { + struct tagStIpsurxMacTbEntry23H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry23Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry23MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry23MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry23Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY23_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY23_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry23M { + struct tagStIpsurxMacTbEntry23M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry23MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry23MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY23_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY23_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry23L { + struct tagStIpsurxMacTbEntry23L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry23VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry23Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry23Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry23Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry23Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry23VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY23_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY22_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry22H { + struct tagStIpsurxMacTbEntry22H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry22Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry22MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry22MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry22Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY22_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY22_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry22M { + struct tagStIpsurxMacTbEntry22M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry22MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry22MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY22_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY22_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry22L { + struct tagStIpsurxMacTbEntry22L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry22VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry22Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry22Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry22Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry22Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry22VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY22_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY21_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry21H { + struct tagStIpsurxMacTbEntry21H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry21Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry21MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry21MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry21Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY21_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY21_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry21M { + struct tagStIpsurxMacTbEntry21M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry21MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry21MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY21_M_U; + + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY21_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry21L { + struct tagStIpsurxMacTbEntry21L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry21VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry21Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry21Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry21Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry21Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry21VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY21_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY20_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry20H { + struct tagStIpsurxMacTbEntry20H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry20Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry20MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry20MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry20Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY20_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY20_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry20M { + struct tagStIpsurxMacTbEntry20M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry20MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry20MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY20_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY20_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry20L { + struct tagStIpsurxMacTbEntry20L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry20VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry20Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry20Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry20Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry20Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry20VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY20_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY19_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry19H { + struct tagStIpsurxMacTbEntry19H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry19Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry19MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry19MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry19Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY19_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY19_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry19M { + struct tagStIpsurxMacTbEntry19M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry19MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry19MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY19_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY19_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry19L { + struct tagStIpsurxMacTbEntry19L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry19VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry19Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry19Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry19Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry19Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry19VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY19_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY18_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry18H { + struct tagStIpsurxMacTbEntry18H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry18Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry18MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry18MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry18Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY18_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY18_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry18M { + struct tagStIpsurxMacTbEntry18M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry18MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry18MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY18_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY18_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry18L { + struct tagStIpsurxMacTbEntry18L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry18VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry18Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry18Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry18Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry18Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry18VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY18_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY17_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry17H { + struct tagStIpsurxMacTbEntry17H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry17Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry17MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry17MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry17Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY17_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY17_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry17M { + struct tagStIpsurxMacTbEntry17M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry17MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry17MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY17_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY17_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry17L { + struct tagStIpsurxMacTbEntry17L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry17VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry17Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry17Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry17Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry17Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry17VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY17_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY16_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry16H { + struct tagStIpsurxMacTbEntry16H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry16Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry16MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry16MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry16Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY16_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY16_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry16M { + struct tagStIpsurxMacTbEntry16M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry16MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry16MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY16_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY16_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry16L { + struct tagStIpsurxMacTbEntry16L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry16VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry16Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry16Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry16Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry16Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry16VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY16_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY15_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry15H { + struct tagStIpsurxMacTbEntry15H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry15Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry15MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry15MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry15Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY15_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY15_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry15M { + struct tagStIpsurxMacTbEntry15M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry15MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry15MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY15_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY15_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry15L { + struct tagStIpsurxMacTbEntry15L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry15VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry15Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry15Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry15Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry15Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry15VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY15_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY14_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry14H { + struct tagStIpsurxMacTbEntry14H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry14Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry14MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry14MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry14Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY14_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY14_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry14M { + struct tagStIpsurxMacTbEntry14M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry14MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry14MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY14_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY14_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry14L { + struct tagStIpsurxMacTbEntry14L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry14VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry14Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry14Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry14Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry14Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry14VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY14_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY13_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry13H { + struct tagStIpsurxMacTbEntry13H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry13Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry13MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry13MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry13Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY13_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY13_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry13M { + struct tagStIpsurxMacTbEntry13M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry13MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry13MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY13_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY13_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry13L { + struct tagStIpsurxMacTbEntry13L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry13VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry13Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry13Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry13Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry13Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry13VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY13_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY12_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry12H { + struct tagStIpsurxMacTbEntry12H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry12Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry12MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry12MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry12Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY12_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY12_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry12M { + struct tagStIpsurxMacTbEntry12M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry12MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry12MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY12_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY12_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry12L { + struct tagStIpsurxMacTbEntry12L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry12VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry12Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry12Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry12Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry12Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry12VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY12_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY11_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry11H { + struct tagStIpsurxMacTbEntry11H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry11Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry11MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry11MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry11Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY11_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY11_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry11M { + struct tagStIpsurxMacTbEntry11M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry11MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry11MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY11_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY11_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry11L { + struct tagStIpsurxMacTbEntry11L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry11VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry11Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry11Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry11Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry11Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry11VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY11_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY10_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry10H { + struct tagStIpsurxMacTbEntry10H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry10Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry10MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry10MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry10Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY10_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY10_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry10M { + struct tagStIpsurxMacTbEntry10M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry10MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry10MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY10_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY10_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry10L { + struct tagStIpsurxMacTbEntry10L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry10VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry10Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry10Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry10Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry10Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry10VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY10_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY9_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry9H { + struct tagStIpsurxMacTbEntry9H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry9Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry9MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry9MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry9Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY9_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY9_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry9M { + struct tagStIpsurxMacTbEntry9M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry9MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry9MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY9_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY9_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry9L { + struct tagStIpsurxMacTbEntry9L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry9VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry9Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry9Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry9Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry9Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry9VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY9_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY8_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry8H { + struct tagStIpsurxMacTbEntry8H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry8Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry8MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry8MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry8Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY8_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY8_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry8M { + struct tagStIpsurxMacTbEntry8M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry8MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry8MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY8_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY8_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry8L { + struct tagStIpsurxMacTbEntry8L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry8VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry8Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry8Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry8Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry8Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry8VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY8_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY7_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry7H { + struct tagStIpsurxMacTbEntry7H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry7Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry7MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry7MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry7Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY7_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY7_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry7M { + struct tagStIpsurxMacTbEntry7M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry7MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry7MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY7_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY7_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry7L { + struct tagStIpsurxMacTbEntry7L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry7VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry7Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry7Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry7Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry7Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry7VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY7_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY6_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry6H { + struct tagStIpsurxMacTbEntry6H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry6Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry6MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry6MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry6Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY6_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY6_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry6M { + struct tagStIpsurxMacTbEntry6M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry6MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry6MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY6_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY6_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry6L { + struct tagStIpsurxMacTbEntry6L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry6VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry6Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry6Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry6Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry6Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry6VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY6_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY5_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry5H { + struct tagStIpsurxMacTbEntry5H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry5Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry5MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry5MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry5Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY5_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY5_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry5M { + struct tagStIpsurxMacTbEntry5M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry5MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry5MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY5_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY5_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry5L { + struct tagStIpsurxMacTbEntry5L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry5VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry5Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry5Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry5Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry5Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry5VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY5_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY4_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry4H { + struct tagStIpsurxMacTbEntry4H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry4Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry4MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry4MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry4Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY4_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY4_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry4M { + struct tagStIpsurxMacTbEntry4M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry4MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry4MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY4_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY4_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry4L { + struct tagStIpsurxMacTbEntry4L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry4VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry4Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry4Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry4Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry4Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry4VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY4_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY3_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry3H { + struct tagStIpsurxMacTbEntry3H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry3Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry3MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry3MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry3Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY3_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY3_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry3M { + struct tagStIpsurxMacTbEntry3M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry3MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry3MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY3_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY3_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry3L { + struct tagStIpsurxMacTbEntry3L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry3VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry3Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry3Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry3Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry3Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry3VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY3_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY2_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry2H { + struct tagStIpsurxMacTbEntry2H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry2Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry2MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry2MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry2Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY2_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY2_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry2M { + struct tagStIpsurxMacTbEntry2M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry2MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry2MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY2_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY2_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry2L { + struct tagStIpsurxMacTbEntry2L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry2VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry2Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry2Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry2Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry2Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry2VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY2_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY1_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry1H { + struct tagStIpsurxMacTbEntry1H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry1Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry1MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry1MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry1Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY1_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY1_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry1M { + struct tagStIpsurxMacTbEntry1M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry1MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry1MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY1_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY1_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry1L { + struct tagStIpsurxMacTbEntry1L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry1VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry1Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry1Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry1Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry1Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry1VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY1_L_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY0_H + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry0H { + struct tagStIpsurxMacTbEntry0H { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21]reserved. */ + unsigned int ipsurxMacTbEntry0Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int ipsurxMacTbEntry0MacH : 16; /* * [15:0]目的MAC地址高16比特 */ +#else + unsigned int ipsurxMacTbEntry0MacH : 16; /* * [15:0]目的MAC地址高16比特 */ + unsigned int ipsurxMacTbEntry0Erid : 5; /* * [20:16]Edge relay identifier。当配置为5'h1F时，该条不会查找成功。 + */ + unsigned int reserved : 11; /* * [31:21]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY0_H_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY0_M + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry0M { + struct tagStIpsurxMacTbEntry0M { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxMacTbEntry0MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#else + unsigned int ipsurxMacTbEntry0MacL : 32; /* * [31:0]目的MAC地址低32比特 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY0_M_U; + +/* ** + * Union name : IPSURX_MAC_TB_ENTRY0_L + * @brief 目的MAC到VF/PF功能号映射表 + * Description: + */ +typedef union tagUnIpsurxMacTbEntry0L { + struct tagStIpsurxMacTbEntry0L { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]reserved. */ + unsigned int ipsurxMacTbEntry0VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry0Hostid : 2; /* * [11:10]HOST ID */ + unsigned int ipsurxMacTbEntry0Vfn : 10; /* * [9:0]VF/PF功能号 */ +#else + unsigned int ipsurxMacTbEntry0Vfn : 10; /* * [9:0]VF/PF功能号 */ + unsigned int ipsurxMacTbEntry0Hostid : 2; /* * [11:10]HOST ID */ + unsigned int reserved1 : 4; /* * [15:12] */ + unsigned int ipsurxMacTbEntry0VlanId : 12; /* * [27:16]VLAN ID */ + unsigned int reserved0 : 4; /* * [31:28]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_MAC_TB_ENTRY0_L_U; + + +/* ** + * Union name : IPSURX_UNCRT_ERR_CTRL + * @brief IPSURX致命错误控制寄存器 + * Description: + */ +typedef union tagUnIpsurxUncrtErrCtrl { + struct tagStIpsurxUncrtErrCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 15; /* * [31:17]reserved. */ + unsigned int ipsurxUncrtErrCtrl : 1; /* * + [16:16]1'b1：允许IPSURX模块产生致命错误；1'b0：不允许IPSURX模块产生致命错误。 + */ + unsigned int ipsurxTcamUncrtErrCtrl : 1; /* * [15:15]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxTcamArtUncrtErrCtrl : 1; /* * [14:14]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxTptUncrtErrCtrl : 1; /* * [13:13]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqContext0UncrtErrCtrl : 1; /* * [12:12]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 + */ + unsigned int ipsurxRenqContext1UncrtErrCtrl : 1; /* * [11:11]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 + */ + unsigned int reserved1 : 1; /* * [10:10] */ + unsigned int ipsurxRenqOfUncrtErrCtrl : 1; /* * [9:9]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqIfUncrtErrCtrl : 1; /* * [8:8]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int reserved3 : 1; /* * [6:6] */ + unsigned int ipsurxLcvFifoUncrtErrCtrl : 1; /* * [5:5]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxLcvppContextUncrtErrCtrl : 1; /* * [4:4]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxPpcRamUncrtCtrl : 1; /* * [3:3]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqOfifoOvflCtrl : 1; /* * [2:2]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqIfifoOvflCtrl : 1; /* * [1:1]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxLcvFifoOvflCtrl : 1; /* * [0:0]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ +#else + unsigned int ipsurxLcvFifoOvflCtrl : 1; /* * [0:0]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqIfifoOvflCtrl : 1; /* * [1:1]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqOfifoOvflCtrl : 1; /* * [2:2]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxPpcRamUncrtCtrl : 1; /* * [3:3]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxLcvppContextUncrtErrCtrl : 1; /* * [4:4]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxLcvFifoUncrtErrCtrl : 1; /* * [5:5]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int reserved3 : 1; /* * [6:6] */ + unsigned int reserved2 : 1; /* * [7:7] */ + unsigned int ipsurxRenqIfUncrtErrCtrl : 1; /* * [8:8]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxRenqOfUncrtErrCtrl : 1; /* * [9:9]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int reserved1 : 1; /* * [10:10] */ + unsigned int ipsurxRenqContext1UncrtErrCtrl : 1; /* * [11:11]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 + */ + unsigned int ipsurxRenqContext0UncrtErrCtrl : 1; /* * [12:12]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 + */ + unsigned int ipsurxTptUncrtErrCtrl : 1; /* * [13:13]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxTcamArtUncrtErrCtrl : 1; /* * [14:14]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxTcamUncrtErrCtrl : 1; /* * [15:15]1'b1：允许产生致命错误；1'b0：不允许产生致命错误。 */ + unsigned int ipsurxUncrtErrCtrl : 1; /* * + [16:16]1'b1：允许IPSURX模块产生致命错误；1'b0：不允许IPSURX模块产生致命错误。 + */ + unsigned int reserved0 : 15; /* * [31:17]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_UNCRT_ERR_CTRL_U; + +/* ** + * Union name : IPSURX_FIFO_TH + * @brief IPSURX FIFO门限寄存器 + * Description: + */ +typedef union tagUnIpsurxFifoTh { + struct tagStIpsurxFifoTh { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29] */ + unsigned int ipsurxRenqOfBpTh : 5; /* * [28:24]RENQ模块输出FIFO的反压门限。建议不要修改。可配置范围：5'd18 -- + 5'd24. */ + unsigned int reserved1 : 2; /* * [23:22] */ + unsigned int ipsurxRenqIfBpTh : 6; /* * [21:16]RENQ模块输入FIFO反压门限。建议不要修改。可配置范围:6'd18 -- + * 6'd22. + */ + unsigned int reserved2 : 1; /* * [15:15] */ + unsigned int ipsurxLcvFifoBpTh : 7; /* * [14:8]LCV模块输入FIFO反压门限。建议不要修改。可配置范围: 7'd30 -- + * 7'd44. + */ + unsigned int reserved3 : 2; /* * [7:6] */ + unsigned int ipsurxRenqOfAemptyTh : 2; /* * [5:4]RENQ模块输出FIFO几乎空门限。建议不要修改。 */ + unsigned int ipsurxRenqIfAemptyTh : 2; /* * [3:2]RENQ模块输入FIFO几乎空门限。建议不要修改。 */ + unsigned int ipsurxLcvFifoAemptyTh : 2; /* * [1:0]LCV模块输入FIFO几乎空门限。建议不要修改。 */ +#else + unsigned int ipsurxLcvFifoAemptyTh : 2; /* * [1:0]LCV模块输入FIFO几乎空门限。建议不要修改。 */ + unsigned int ipsurxRenqIfAemptyTh : 2; /* * [3:2]RENQ模块输入FIFO几乎空门限。建议不要修改。 */ + unsigned int ipsurxRenqOfAemptyTh : 2; /* * [5:4]RENQ模块输出FIFO几乎空门限。建议不要修改。 */ + unsigned int reserved3 : 2; /* * [7:6] */ + unsigned int ipsurxLcvFifoBpTh : 7; /* * [14:8]LCV模块输入FIFO反压门限。建议不要修改。可配置范围: 7'd30 -- + * 7'd44. + */ + unsigned int reserved2 : 1; /* * [15:15] */ + unsigned int ipsurxRenqIfBpTh : 6; /* * [21:16]RENQ模块输入FIFO反压门限。建议不要修改。可配置范围:6'd18 -- + * 6'd22. + */ + unsigned int reserved1 : 2; /* * [23:22] */ + unsigned int ipsurxRenqOfBpTh : 5; /* * [28:24]RENQ模块输出FIFO的反压门限。建议不要修改。可配置范围：5'd18 -- + 5'd24. */ + unsigned int reserved0 : 3; /* * [31:29] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIFO_TH_U; + +/* ** + * Union name : IPSURX_RAMMOD_CTRL + * @brief IPSURX模块RAM MOD控制寄存器 + * Description: + */ +typedef union tagUnIpsurxRammodCtrl { + struct tagStIpsurxRammodCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 11; /* * [31:21] */ + unsigned int ipsurxMemPowerModeCtrl : 6; /* * [20:15]建议不要修改。 */ + unsigned int ipsurxSpRamTmodCtrl : 7; /* * [14:8]建议不要修改。 */ + unsigned int ipsurxTpRamTmodCtrl : 8; /* * [7:0]建议不要修改。 */ +#else + unsigned int ipsurxTpRamTmodCtrl : 8; /* * [7:0]建议不要修改。 */ + unsigned int ipsurxSpRamTmodCtrl : 7; /* * [14:8]建议不要修改。 */ + unsigned int ipsurxMemPowerModeCtrl : 6; /* * [20:15]建议不要修改。 */ + unsigned int reserved : 11; /* * [31:21] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RAMMOD_CTRL_U; + +/* ** + * Union name : IPSURX_RAM_ERR_CHK_BYPASS + * @brief IPSURX模块RAM错误检查BYPASS寄存器 + * Description: + */ +typedef union tagUnIpsurxRamErrChkBypass { + struct tagStIpsurxRamErrChkBypass { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved. */ + unsigned int ipsurxRamErrChkBypass : 1; /* * [0:0]1'b0：使能RAM ECC校验；1'b1：不使能RAM ECC校验。 */ +#else + unsigned int ipsurxRamErrChkBypass : 1; /* * [0:0]1'b0：使能RAM ECC校验；1'b1：不使能RAM ECC校验。 */ + unsigned int reserved : 31; /* * [31:1]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RAM_ERR_CHK_BYPASS_U; + +/* ** + * Union name : IPSURX_RAM_ERR_INJ + * @brief IPSURX模块RAM错误注入寄存器 + * Description: + */ +typedef union tagUnIpsurxRamErrInj { + struct tagStIpsurxRamErrInj { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 4; /* * [31:28]保留 */ + unsigned int ipsurxRenqOfRamUncrtErrInj : 1; /* * [27:27]RENQ Output FIFO + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqOfRamCrtErrInj : 1; /* * [26:26]RENQ Output FIFO + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext1RamUncrtErrInj : 1; /* * [25:25]RENQ CONTEXT1 + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext1RamCrtErrInj : 1; /* * [24:24]RENQ CONTEXT1 + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext0RamUncrtErrInj : 1; /* * [23:23]RENQ CONTEXT0 + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext0RamCrtErrInj : 1; /* * [22:22]RENQ CONTEXT0 + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqIfRamUncrtErrInj : 1; /* * [21:21]RENQ Input FIFO + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqIfRamCrtErrInj : 1; /* * [20:20]RENQ Input FIFO + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int reserved1 : 8; /* * [19:12] */ + unsigned int ipsurxLcvContextRamUncrtErrInj : 1; /* * [11:11]LCV CONTEXT + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxLcvContextRamCrtErrInj : 1; /* * [10:10]LCV CONTEXT + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxLcvFifoRamUncrtErrInj : 1; /* * [9:9]LCV FIFO RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 + */ + unsigned int ipsurxLcvFifoRamCrtErrInj : 1; /* * [8:8]LCV FIFO RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxPpcDramUncrtErrInj : 1; /* * [7:7]PPC DATA RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxPpcDramCrtErrInj : 1; /* * [6:6]PPC DATA RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTptUncrtErrInj : 1; /* * [5:5]TCP Port Table RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTptCrtErrInj : 1; /* * [4:4]TCP Port Table RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamArtUncrtErrInj : 1; /* * [3:3]TCAM ART不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamArtCrtErrInj : 1; /* * [2:2]TCAM ART可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamUncrtErrInj : 1; /* * [1:1]TCAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamCrtErrInj : 1; /* * [0:0]TCAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ +#else + unsigned int ipsurxTcamCrtErrInj : 1; /* * [0:0]TCAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamUncrtErrInj : 1; /* * [1:1]TCAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamArtCrtErrInj : 1; /* * [2:2]TCAM ART可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTcamArtUncrtErrInj : 1; /* * [3:3]TCAM ART不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTptCrtErrInj : 1; /* * [4:4]TCP Port Table RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxTptUncrtErrInj : 1; /* * [5:5]TCP Port Table RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxPpcDramCrtErrInj : 1; /* * [6:6]PPC DATA RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxPpcDramUncrtErrInj : 1; /* * [7:7]PPC DATA RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxLcvFifoRamCrtErrInj : 1; /* * [8:8]LCV FIFO RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxLcvFifoRamUncrtErrInj : 1; /* * [9:9]LCV FIFO RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 + */ + unsigned int ipsurxLcvContextRamCrtErrInj : 1; /* * [10:10]LCV CONTEXT + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxLcvContextRamUncrtErrInj : 1; /* * [11:11]LCV CONTEXT + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int reserved1 : 8; /* * [19:12] */ + unsigned int ipsurxRenqIfRamCrtErrInj : 1; /* * [20:20]RENQ Input FIFO + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqIfRamUncrtErrInj : 1; /* * [21:21]RENQ Input FIFO + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext0RamCrtErrInj : 1; /* * [22:22]RENQ CONTEXT0 + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext0RamUncrtErrInj : 1; /* * [23:23]RENQ CONTEXT0 + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext1RamCrtErrInj : 1; /* * [24:24]RENQ CONTEXT1 + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqContext1RamUncrtErrInj : 1; /* * [25:25]RENQ CONTEXT1 + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqOfRamCrtErrInj : 1; /* * [26:26]RENQ Output FIFO + RAM可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int ipsurxRenqOfRamUncrtErrInj : 1; /* * [27:27]RENQ Output FIFO + RAM不可纠错误注入。1'b0：不插入；1'b1：插入。 */ + unsigned int reserved0 : 4; /* * [31:28]保留 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RAM_ERR_INJ_U; + +/* ** + * Union name : IPSURX_TCAM_CTRL + * @brief TCAM控制寄存器 + * Description: + */ +typedef union tagUnIpsurxTcamCtrl { + struct tagStIpsurxTcamCtrl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int + ipsurxTcamMbistTSel : 2; /* * [31:30]用于调节TCAM IP里面的read电路的时序， + * 默认值是2'b10。ATE筛片的时候，测试有read问题或者良率不行的时候，可以调大T_SEL改善；或者良率可以，并提高TCAM读速度的时候，可以调小T_SEL。 + */ + unsigned int ipsurxTcamMbistTest : 2; /* * + [29:28]2'b00：不进行筛片；2'b01：筛除弱pmos；2'b10：筛除弱nmos；2'b11：筛除弱pmos/nmos。 + */ + unsigned int ipsurxTcamMbistEn : 1; /* * [27:27]Function MBIST测试使能1'b0：不使能；1'b1：使能。 */ + unsigned int reserved : 9; /* * [26:18] */ + unsigned int + ipsurxTcamCfgSearchCtrl : 1; /* * [17:17]1'b0：返回命中TCAM KEY + 的地址；1'b1：返回TCAM查找的ART表项结果。在一次查找返回结果之前不能修改该值。 + */ + unsigned int ipsurxTcamLkupEn : 1; /* * [16:16]TCAM逻辑查找使能。1'b0：禁止；1'b1：使能。 */ + unsigned int ipsurxTcamBkScanIntervalUnit : 8; /* * + [15:8]TCAM背景扫描间隔计数单位，最小值为16。当配置值小于16时，硬件会自动将配置值修改为16。 + */ + unsigned int + ipsurxTcamBkScanPeriod : 8; /* * + * [7:0]TCAM背景扫描间隔周期。实际的TCAM扫描启动间隔：当前背景扫描完成后ipsurx_tcam_bk_scan_interval_unit + * * ipsurx_tcam_bk_scan_period个CYCLE。注意：当两个参数的乘积为0时，表示不使能TCAM背景扫描。 + */ +#else + unsigned int + ipsurxTcamBkScanPeriod : 8; /* * + * [7:0]TCAM背景扫描间隔周期。实际的TCAM扫描启动间隔：当前背景扫描完成后ipsurx_tcam_bk_scan_interval_unit + * * ipsurx_tcam_bk_scan_period个CYCLE。注意：当两个参数的乘积为0时，表示不使能TCAM背景扫描。 + */ + unsigned int ipsurxTcamBkScanIntervalUnit : 8; /* * + [15:8]TCAM背景扫描间隔计数单位，最小值为16。当配置值小于16时，硬件会自动将配置值修改为16。 + */ + unsigned int ipsurxTcamLkupEn : 1; /* * [16:16]TCAM逻辑查找使能。1'b0：禁止；1'b1：使能。 */ + unsigned int + ipsurxTcamCfgSearchCtrl : 1; /* * [17:17]1'b0：返回命中TCAM KEY + 的地址；1'b1：返回TCAM查找的ART表项结果。在一次查找返回结果之前不能修改该值。 + */ + unsigned int reserved : 9; /* * [26:18] */ + unsigned int ipsurxTcamMbistEn : 1; /* * [27:27]Function MBIST测试使能1'b0：不使能；1'b1：使能。 */ + unsigned int ipsurxTcamMbistTest : 2; /* * + [29:28]2'b00：不进行筛片；2'b01：筛除弱pmos；2'b10：筛除弱nmos；2'b11：筛除弱pmos/nmos。 + */ + unsigned int + ipsurxTcamMbistTSel : 2; /* * [31:30]用于调节TCAM IP里面的read电路的时序， + * 默认值是2'b10。ATE筛片的时候，测试有read问题或者良率不行的时候，可以调大T_SEL改善；或者良率可以，并提高TCAM读速度的时候，可以调小T_SEL。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_CTRL_U; + +/* ** + * Union name : IPSURX_TCAM_MBIST_DONE + * @brief TCAM MBIST完成状态信号 + * Description: + */ +typedef union tagUnIpsurxTcamMbistDone { + struct tagStIpsurxTcamMbistDone { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 31; /* * [31:1]reserved. */ + unsigned int ipsurxTcamMbistDone : 1; /* * [0:0]1'b0：未完成。1'b1：MBIST完成。 */ +#else + unsigned int ipsurxTcamMbistDone : 1; /* * [0:0]1'b0：未完成。1'b1：MBIST完成。 */ + unsigned int reserved : 31; /* * [31:1]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_MBIST_DONE_U; + +/* ** + * Union name : IPSURX_FIFO_CNT + * @brief IPSURX FIFO当前深度计数寄存器 + * Description: + */ +typedef union tagUnIpsurxFifoCnt { + struct tagStIpsurxFifoCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 10; /* * [31:22]reserved. */ + unsigned int ipsurxRenqOfCnt : 6; /* * [21:16]RENQ 输出FIFO当前深度。 */ + unsigned int reserved1 : 2; /* * [15:14] */ + unsigned int ipsurxRenqIfCnt : 6; /* * [13:8]RENQ 输入FIFO当前深度。 */ + unsigned int ipsurxLcvFifoCnt : 8; /* * [7:0]LCV模块输入FIFO当前深度。 */ +#else + unsigned int ipsurxLcvFifoCnt : 8; /* * [7:0]LCV模块输入FIFO当前深度。 */ + unsigned int ipsurxRenqIfCnt : 6; /* * [13:8]RENQ 输入FIFO当前深度。 */ + unsigned int reserved1 : 2; /* * [15:14] */ + unsigned int ipsurxRenqOfCnt : 6; /* * [21:16]RENQ 输出FIFO当前深度。 */ + unsigned int reserved0 : 10; /* * [31:22]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIFO_CNT_U; + +/* ** + * Union name : IPSURX_FIFO_CURR_ST + * @brief IPSURX FIFO当前状态寄存器 + * Description: + */ +typedef union tagUnIpsurxFifoCurrSt { + struct tagStIpsurxFifoCurrSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 17; /* * [31:15]reserved. */ + unsigned int ipsurxRenqOfOverflowCurr : 1; /* * [14:14]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqOfFullCurr : 1; /* * [13:13]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqOfAfullCurr : 1; /* * [12:12]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqOfEmptyCurr : 1; /* * [11:11]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqOfAemptyCurr : 1; /* * [10:10]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqIfOverflowCurr : 1; /* * [9:9]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqIfFullCurr : 1; /* * [8:8]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqIfAfullCurr : 1; /* * [7:7]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqIfEmptyCurr : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqIfAemptyCurr : 1; /* * [5:5]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxLcvFifoOverflowCurr : 1; /* * [4:4]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxLcvFifoFullCurr : 1; /* * [3:3]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxLcvFifoAfullCurr : 1; /* * [2:2]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxLcvFifoEmptyCurr : 1; /* * [1:1]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxLcvFifoAemptyCurr : 1; /* * [0:0]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ +#else + unsigned int ipsurxLcvFifoAemptyCurr : 1; /* * [0:0]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxLcvFifoEmptyCurr : 1; /* * [1:1]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxLcvFifoAfullCurr : 1; /* * [2:2]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxLcvFifoFullCurr : 1; /* * [3:3]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxLcvFifoOverflowCurr : 1; /* * [4:4]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqIfAemptyCurr : 1; /* * [5:5]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqIfEmptyCurr : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqIfAfullCurr : 1; /* * [7:7]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqIfFullCurr : 1; /* * [8:8]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqIfOverflowCurr : 1; /* * [9:9]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqOfAemptyCurr : 1; /* * [10:10]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqOfEmptyCurr : 1; /* * [11:11]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqOfAfullCurr : 1; /* * [12:12]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqOfFullCurr : 1; /* * [13:13]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqOfOverflowCurr : 1; /* * [14:14]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 17; /* * [31:15]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIFO_CURR_ST_U; + +/* ** + * Union name : IPSUTX_IPSURX_CSR_AFIFO_CURR_ST + * @brief IPSURX CSR异步FIFO当前状态寄存器 + * Description: + */ +typedef union tagUnIpsutxIpsurxCsrAfifoCurrSt { + struct tagStIpsutxIpsurxCsrAfifoCurrSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6] */ + unsigned int ipsutxIpsurxCsrIntAfifoOverflowCurr : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrIntAfifoFullCurr : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrIntAfifoEmptyCurr : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrAfifoOverflowCurr : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrAfifoFullCurr : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrAfifoEmptyCurr : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ +#else + unsigned int ipsutxIpsurxCsrAfifoEmptyCurr : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrAfifoFullCurr : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrAfifoOverflowCurr : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrIntAfifoEmptyCurr : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrIntAfifoFullCurr : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrIntAfifoOverflowCurr : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 26; /* * [31:6] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSUTX_IPSURX_CSR_AFIFO_CURR_ST_U; + +/* ** + * Union name : IPSURX_FIFO_HIS_ST + * @brief IPSURX FIFO历史状态寄存器 + * Description: + */ +typedef union tagUnIpsurxFifoHisSt { + struct tagStIpsurxFifoHisSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 17; /* * [31:15]reserved. */ + unsigned int ipsurxRenqOfOverflowHst : 1; /* * [14:14]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqOfFullHst : 1; /* * [13:13]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqOfAfullHst : 1; /* * [12:12]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqOfEmptyHst : 1; /* * [11:11]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqOfAemptyHst : 1; /* * [10:10]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqIfOverflowHst : 1; /* * [9:9]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqIfFullHst : 1; /* * [8:8]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqIfAfullHst : 1; /* * [7:7]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqIfEmptyHst : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqIfAemptyHst : 1; /* * [5:5]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxLcvFifoOverflowHst : 1; /* * [4:4]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxLcvFifoFullHst : 1; /* * [3:3]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxLcvFifoAfullHst : 1; /* * [2:2]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxLcvFifoEmptyHst : 1; /* * [1:1]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxLcvFifoAemptyHst : 1; /* * [0:0]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ +#else + unsigned int ipsurxLcvFifoAemptyHst : 1; /* * [0:0]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxLcvFifoEmptyHst : 1; /* * [1:1]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxLcvFifoAfullHst : 1; /* * [2:2]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxLcvFifoFullHst : 1; /* * [3:3]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxLcvFifoOverflowHst : 1; /* * [4:4]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqIfAemptyHst : 1; /* * [5:5]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqIfEmptyHst : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqIfAfullHst : 1; /* * [7:7]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqIfFullHst : 1; /* * [8:8]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqIfOverflowHst : 1; /* * [9:9]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxRenqOfAemptyHst : 1; /* * [10:10]FIFO几乎空标志。1'b1：几乎空；1'b0：非几乎空。 */ + unsigned int ipsurxRenqOfEmptyHst : 1; /* * [11:11]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxRenqOfAfullHst : 1; /* * [12:12]几乎满标志。1'b1：几乎满；1'b0：非几乎满。 */ + unsigned int ipsurxRenqOfFullHst : 1; /* * [13:13]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxRenqOfOverflowHst : 1; /* * [14:14]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 17; /* * [31:15]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_FIFO_HIS_ST_U; + +/* ** + * Union name : IPSUTX_IPSURX_CSR_AFIFO_HIS_ST + * @brief IPSURX CSR异步FIFO历史状态寄存器 + * Description: + */ +typedef union tagUnIpsutxIpsurxCsrAfifoHisSt { + struct tagStIpsutxIpsurxCsrAfifoHisSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 26; /* * [31:6]reserved. */ + unsigned int ipsutxIpsurxCsrIntAfifoOverflowHst : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrIntAfifoFullHst : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrIntAfifoEmptyHst : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrAfifoOverflowHst : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrAfifoFullHst : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrAfifoEmptyHst : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ +#else + unsigned int ipsutxIpsurxCsrAfifoEmptyHst : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrAfifoFullHst : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrAfifoOverflowHst : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsutxIpsurxCsrIntAfifoEmptyHst : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsutxIpsurxCsrIntAfifoFullHst : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsutxIpsurxCsrIntAfifoOverflowHst : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 26; /* * [31:6]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSUTX_IPSURX_CSR_AFIFO_HIS_ST_U; + +/* ** + * Union name : IPSURX_REC_BP_CNT + * @brief IPSURX接收反压次数计数器 + * Description: + */ +typedef union tagUnIpsurxRecBpCnt { + struct tagStIpsurxRecBpCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRecBpCnt : 32; /* * [31:0]IPSURX收到反压次数计数器 */ +#else + unsigned int ipsurxRecBpCnt : 32; /* * [31:0]IPSURX收到反压次数计数器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_REC_BP_CNT_U; + +/* ** + * Union name : IPSURX_GEN_BP_CNT + * @brief IPSURX产生反压次数计数器 + * Description: + */ +typedef union tagUnIpsurxGenBpCnt { + struct tagStIpsurxGenBpCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxGenBpCnt : 32; /* * [31:0]IPSURX产生反压次数计数器 */ +#else + unsigned int ipsurxGenBpCnt : 32; /* * [31:0]IPSURX产生反压次数计数器 */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_GEN_BP_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_MBIST_MEM_ERR_CNT + * @brief TCAM MBIST MEM错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamMbistMemErrCnt { + struct tagStIpsurxTcamMbistMemErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamMbistMemErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamMbistMemErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_MBIST_MEM_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_MBIST_CMP_ERR_CNT + * @brief TCAM MBIST 匹配错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamMbistCmpErrCnt { + struct tagStIpsurxTcamMbistCmpErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamMbistCmpErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamMbistCmpErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_MBIST_CMP_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_CRT_ERR_CNT + * @brief TCAM可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamCrtErrCnt { + struct tagStIpsurxTcamCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_UNCRT_ERR_CNT + * @brief TCAM不可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamUncrtErrCnt { + struct tagStIpsurxTcamUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_ART_CRT_ERR_CNT + * @brief TCAM/ART 可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamArtCrtErrCnt { + struct tagStIpsurxTcamArtCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamArtCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamArtCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_ART_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TCAM_ART_UNCRT_ERR_CNT + * @brief TCAM/ART 不可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxTcamArtUncrtErrCnt { + struct tagStIpsurxTcamArtUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTcamArtUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTcamArtUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TCAM_ART_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_PKT_DROP_BY_TCAM_CNT + * @brief TCAM指定丢弃报文计数器 + * Description: + */ +typedef union tagUnIpsurxPktDropByTcamCnt { + struct tagStIpsurxPktDropByTcamCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxPktDropByTcamCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxPktDropByTcamCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PKT_DROP_BY_TCAM_CNT_U; + +/* ** + * Union name : IPSURX_TPT_CRT_ERR_CNT + * @brief TPT 可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxTptCrtErrCnt { + struct tagStIpsurxTptCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTptCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTptCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TPT_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_TPT_UNCRT_ERR_CNT + * @brief TPT 不可纠ECC校验错计数器 + * Description: + */ +typedef union tagUnIpsurxTptUncrtErrCnt { + struct tagStIpsurxTptUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxTptUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxTptUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_TPT_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_PPC_DRAM_CRT_ERR_CNT + * @brief PPC模块数据RAM可纠ECC校验校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxPpcDramCrtErrCnt { + struct tagStIpsurxPpcDramCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxPpcDramCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxPpcDramCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PPC_DRAM_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_PPC_DRAM_UNCRT_ERR_CNT + * @brief PPC模块数据RAM不可纠校验校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxPpcDramUncrtErrCnt { + struct tagStIpsurxPpcDramUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxPpcDramUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxPpcDramUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_PPC_DRAM_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_LCV_FIFO_RAM_CRT_ERR_CNT + * @brief LCV 输入FIFO RAM可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxLcvFifoRamCrtErrCnt { + struct tagStIpsurxLcvFifoRamCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxLcvFifoRamCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxLcvFifoRamCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCV_FIFO_RAM_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_LCV_FIFO_RAM_UNCRT_ERR_CNT + * @brief LCV 输入FIFO RAM不可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxLcvFifoRamUncrtErrCnt { + struct tagStIpsurxLcvFifoRamUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxLcvFifoRamUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxLcvFifoRamUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCV_FIFO_RAM_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_LCV_CONTEXT_CRT_ERR_CNT + * @brief LCV模块Context可纠ECC校验校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxLcvContextCrtErrCnt { + struct tagStIpsurxLcvContextCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxLcvContextCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxLcvContextCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCV_CONTEXT_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_LCV_CONTEXT_UNCRT_ERR_CNT + * @brief LCV模块Context不可纠校验校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxLcvContextUncrtErrCnt { + struct tagStIpsurxLcvContextUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxLcvContextUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxLcvContextUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_LCV_CONTEXT_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_IF_RAM_CRT_ERR_CNT + * @brief RENQ 输入FIFO RAM可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqIfRamCrtErrCnt { + struct tagStIpsurxRenqIfRamCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqIfRamCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqIfRamCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_IF_RAM_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_IF_RAM_UNCRT_ERR_CNT + * @brief RENQ 输入FIFO RAM不可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqIfRamUncrtErrCnt { + struct tagStIpsurxRenqIfRamUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqIfRamUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqIfRamUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_IF_RAM_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT0_CRT_ERR_CNT + * @brief RENQ CONTEXT RAM可纠校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqContext0CrtErrCnt { + struct tagStIpsurxRenqContext0CrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqContext0CrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqContext0CrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT0_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT0_UNCRT_ERR_CNT + * @brief RENQ CONTEXT RAM不可纠校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqContext0UncrtErrCnt { + struct tagStIpsurxRenqContext0UncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqContext0UncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqContext0UncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT0_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT1_CRT_ERR_CNT + * @brief RENQ CONTEXT RAM可纠校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqContext1CrtErrCnt { + struct tagStIpsurxRenqContext1CrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqContext1CrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqContext1CrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT1_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_CONTEXT1_UNCRT_ERR_CNT + * @brief RENQ CONTEXT RAM不可纠校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqContext1UncrtErrCnt { + struct tagStIpsurxRenqContext1UncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqContext1UncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqContext1UncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_CONTEXT1_UNCRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_OF_RAM_CRT_ERR_CNT + * @brief RENQ 输出FIFO RAM可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqOfRamCrtErrCnt { + struct tagStIpsurxRenqOfRamCrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqOfRamCrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqOfRamCrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_OF_RAM_CRT_ERR_CNT_U; + +/* ** + * Union name : IPSURX_RENQ_OF_RAM_UNCRT_ERR_CNT + * @brief RENQ 输出FIFO RAM不可纠ECC校验错误计数器 + * Description: + */ +typedef union tagUnIpsurxRenqOfRamUncrtErrCnt { + struct tagStIpsurxRenqOfRamUncrtErrCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxRenqOfRamUncrtErrCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxRenqOfRamUncrtErrCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RENQ_OF_RAM_UNCRT_ERR_CNT_U; + + +/* ** + * Union name : IPSURX_CH16_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh16RxPktCnt { + struct tagStIpsurxCh16RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh16RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh16RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH16_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH16_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh16TxPktCnt { + struct tagStIpsurxCh16TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh16TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh16TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH16_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH15_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh15RxPktCnt { + struct tagStIpsurxCh15RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh15RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh15RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH15_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH15_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh15TxPktCnt { + struct tagStIpsurxCh15TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh15TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh15TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH15_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH14_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh14RxPktCnt { + struct tagStIpsurxCh14RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh14RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh14RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH14_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH14_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh14TxPktCnt { + struct tagStIpsurxCh14TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh14TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh14TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH14_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH13_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh13RxPktCnt { + struct tagStIpsurxCh13RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh13RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh13RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH13_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH13_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh13TxPktCnt { + struct tagStIpsurxCh13TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh13TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh13TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH13_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH12_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh12RxPktCnt { + struct tagStIpsurxCh12RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh12RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh12RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH12_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH12_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh12TxPktCnt { + struct tagStIpsurxCh12TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh12TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh12TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH12_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH11_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh11RxPktCnt { + struct tagStIpsurxCh11RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh11RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh11RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH11_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH11_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh11TxPktCnt { + struct tagStIpsurxCh11TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh11TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh11TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH11_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH10_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh10RxPktCnt { + struct tagStIpsurxCh10RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh10RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh10RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH10_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH10_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh10TxPktCnt { + struct tagStIpsurxCh10TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh10TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh10TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH10_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH09_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh09RxPktCnt { + struct tagStIpsurxCh09RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh09RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh09RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH09_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH09_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh09TxPktCnt { + struct tagStIpsurxCh09TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh09TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh09TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH09_TX_PKT_CNT_U; + + +/* ** + * Union name : IPSURX_CH08_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh08RxPktCnt { + struct tagStIpsurxCh08RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh08RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh08RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH08_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH08_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh08TxPktCnt { + struct tagStIpsurxCh08TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh08TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh08TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH08_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH07_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh07RxPktCnt { + struct tagStIpsurxCh07RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh07RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh07RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH07_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH07_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh07TxPktCnt { + struct tagStIpsurxCh07TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh07TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh07TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH07_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH06_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh06RxPktCnt { + struct tagStIpsurxCh06RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh06RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh06RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH06_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH06_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh06TxPktCnt { + struct tagStIpsurxCh06TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh06TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh06TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH06_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH05_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh05RxPktCnt { + struct tagStIpsurxCh05RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh05RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh05RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH05_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH05_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh05TxPktCnt { + struct tagStIpsurxCh05TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh05TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh05TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH05_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH04_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh04RxPktCnt { + struct tagStIpsurxCh04RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh04RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh04RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH04_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH04_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh04TxPktCnt { + struct tagStIpsurxCh04TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh04TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh04TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH04_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH03_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh03RxPktCnt { + struct tagStIpsurxCh03RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh03RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh03RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH03_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH03_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh03TxPktCnt { + struct tagStIpsurxCh03TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh03TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh03TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH03_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH02_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh02RxPktCnt { + struct tagStIpsurxCh02RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh02RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh02RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH02_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH02_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh02TxPktCnt { + struct tagStIpsurxCh02TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh02TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh02TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH02_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH01_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh01RxPktCnt { + struct tagStIpsurxCh01RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh01RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh01RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH01_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH01_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh01TxPktCnt { + struct tagStIpsurxCh01TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh01TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh01TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH01_TX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH00_RX_PKT_CNT + * @brief 通道接收报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh00RxPktCnt { + struct tagStIpsurxCh00RxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh00RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ +#else + unsigned long long ipsurxCh00RxPktCnt : 48; /* * [47:0]基于通道，统计接收到的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH00_RX_PKT_CNT_U; + +/* ** + * Union name : IPSURX_CH00_TX_PKT_CNT + * @brief 通道发送到CPB的报文数量计数器 + * Description: + */ +typedef union tagUnIpsurxCh00TxPktCnt { + struct tagStIpsurxCh00TxPktCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned long long reserved : 16; /* * [63:48]reserved. */ + unsigned long long ipsurxCh00TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ +#else + unsigned long long ipsurxCh00TxPktCnt : 48; /* * [47:0]基于通道，统计发送的报文数量。 */ + unsigned long long reserved : 16; /* * [63:48]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned long long ullValue; +} CSR_IPSURX_CH00_TX_PKT_CNT_U; + + +/* ** + * Union name : IPSURX_API_CSR_FIFO_CURR_ST + * @brief IPSURX CSR FIFO当前状态寄存器 + * Description: + */ +typedef union tagUnIpsurxApiCsrFifoCurrSt { + struct tagStIpsurxApiCsrFifoCurrSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12] */ + unsigned int ipsurxApiSfifoOverflowCurr : 1; /* * [11:11]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiSfifoFullCurr : 1; /* * [10:10]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiSfifoEmptyCurr : 1; /* * [9:9]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiAfifoOverflowCurr : 1; /* * [8:8]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiAfifoFullCurr : 1; /* * [7:7]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiAfifoEmptyCurr : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrIntAfifoOverflowCurr : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrIntAfifoFullCurr : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrIntAfifoEmptyCurr : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrAfifoOverflowCurr : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrAfifoFullCurr : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrAfifoEmptyCurr : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ +#else + unsigned int ipsurxCnbCsrAfifoEmptyCurr : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrAfifoFullCurr : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrAfifoOverflowCurr : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrIntAfifoEmptyCurr : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrIntAfifoFullCurr : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrIntAfifoOverflowCurr : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiAfifoEmptyCurr : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiAfifoFullCurr : 1; /* * [7:7]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiAfifoOverflowCurr : 1; /* * [8:8]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiSfifoEmptyCurr : 1; /* * [9:9]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiSfifoFullCurr : 1; /* * [10:10]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiSfifoOverflowCurr : 1; /* * [11:11]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 20; /* * [31:12] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_CSR_FIFO_CURR_ST_U; + +/* ** + * Union name : IPSURX_API_CSR_FIFO_HIS_ST + * @brief IPSURX CSR FIFO历史状态寄存器 + * Description: + */ +typedef union tagUnIpsurxApiCsrFifoHisSt { + struct tagStIpsurxApiCsrFifoHisSt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 20; /* * [31:12]reserved. */ + unsigned int ipsurxApiSfifoOverflowHst : 1; /* * [11:11]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiSfifoFullHst : 1; /* * [10:10]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiSfifoEmptyHst : 1; /* * [9:9]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiAfifoOverflowHst : 1; /* * [8:8]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiAfifoFullHst : 1; /* * [7:7]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiAfifoEmptyHst : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrIntAfifoOverflowHst : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrIntAfifoFullHst : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrIntAfifoEmptyHst : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrAfifoOverflowHst : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrAfifoFullHst : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrAfifoEmptyHst : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ +#else + unsigned int ipsurxCnbCsrAfifoEmptyHst : 1; /* * [0:0]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrAfifoFullHst : 1; /* * [1:1]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrAfifoOverflowHst : 1; /* * [2:2]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxCnbCsrIntAfifoEmptyHst : 1; /* * [3:3]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxCnbCsrIntAfifoFullHst : 1; /* * [4:4]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxCnbCsrIntAfifoOverflowHst : 1; /* * [5:5]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiAfifoEmptyHst : 1; /* * [6:6]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiAfifoFullHst : 1; /* * [7:7]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiAfifoOverflowHst : 1; /* * [8:8]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int ipsurxApiSfifoEmptyHst : 1; /* * [9:9]FIFO空标志。1'b1：空；1'b0：非空。 */ + unsigned int ipsurxApiSfifoFullHst : 1; /* * [10:10]FIFO满标志。1'b1：满；1'b0：非满。 */ + unsigned int ipsurxApiSfifoOverflowHst : 1; /* * [11:11]FIFO溢出标志。1'b1：FIFO溢出；1'b0：无溢出。 */ + unsigned int reserved : 20; /* * [31:12]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_CSR_FIFO_HIS_ST_U; + +/* ** + * Union name : IPSURX_API_ERR_FLIT_CNT + * @brief IPSURX错误API FLIT计数器 + * Description: + */ +typedef union tagUnIpsurxApiErrFlitCnt { + struct tagStIpsurxApiErrFlitCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxApiErrFlitCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxApiErrFlitCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_ERR_FLIT_CNT_U; + +/* ** + * Union name : IPSURX_API_CRT_FLIT_CNT + * @brief IPSURX正确API FLIT计数器 + * Description: + */ +typedef union tagUnIpsurxApiCrtFlitCnt { + struct tagStIpsurxApiCrtFlitCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxApiCrtFlitCnt : 32; /* * [31:0] */ +#else + unsigned int ipsurxApiCrtFlitCnt : 32; /* * [31:0] */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_CRT_FLIT_CNT_U; + +/* ** + * Union name : IPSURX_API_DROP_FOR_FULL_CNT + * @brief IPSURX丢弃正确API计数器 + * Description: + */ +typedef union tagUnIpsurxApiDropForFullCnt { + struct tagStIpsurxApiDropForFullCnt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int ipsurxApiDropForFullCnt : 32; /* * + [31:0]由于API在RING时钟域，可能大量突发给IPSURX，IPSURX可能来不及处理。这种情况下，会直接丢弃已经通过合法性检查的API，并进行计数。 + */ +#else + unsigned int ipsurxApiDropForFullCnt : 32; /* * + [31:0]由于API在RING时钟域，可能大量突发给IPSURX，IPSURX可能来不及处理。这种情况下，会直接丢弃已经通过合法性检查的API，并进行计数。 + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_DROP_FOR_FULL_CNT_U; + +/* ** + * Union name : IPSURX_API_ERR_INT_VECTOR + * @brief IPSURX API错误中断向量寄存器 + * Description: + */ +typedef union tagUnIpsurxApiErrIntVector { + struct tagStIpsurxApiErrIntVector { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved0 : 3; /* * [31:29]Reserved */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported thru this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + * and MSI-X table index. The detail of the 24-bit register is defined by CPI in + * Hi1822V100 FS + */ +#else + unsigned int cpiIntIndex : 24; /* * [23:0]Software must program the 24-bit CSR to specify the destination PFs + * and MSI-X table index. The detail of the 24-bit register is defined by CPI in + * Hi1822V100 FS + */ + unsigned int reserved1 : 3; /* * [26:24]Reserved */ + unsigned int enable : 1; /* * [27:27]Interrupt enable flag, enables all interrupts reported thru this + * register1'b0: interrupt disable;1'b1: interrupt enable. + */ + unsigned int intIssue : 1; /* * [28:28]Interrupt issued flag.1'b0: no interrupt issued;1'b1: interrupt issued, + * CP need to write 0 to clear. + */ + unsigned int reserved0 : 3; /* * [31:29]Reserved */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_ERR_INT_VECTOR_U; + +/* ** + * Union name : IPSURX_API_ERR_INT + * @brief IPSURX API错误中断寄存器 + * Description: + */ +typedef union tagUnIpsurxApiErrInt { + struct tagStIpsurxApiErrInt { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_API_ERR_INT_MASK register. + */ + unsigned int reserved : 9; /* * [15:7]Reserved */ + unsigned int intData : 7; /* * [6:0]These 7 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ +#else + unsigned int intData : 7; /* * [6:0]These 7 bits are not implemented as real registers. Each bit is a shadow + * copy of the error bits from the corresponding error registers on the sheet. + */ + unsigned int reserved : 9; /* * [15:7]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]These 16 bits are not real registers. They are shadow copies of the + * program_csr_id bits in the IPSURX_API_ERR_INT_MASK register. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_ERR_INT_U; + +/* ** + * Union name : IPSURX_API_ERR_INT_MASK + * @brief IPSURX API错误中断MASK寄存器 + * Description: + */ +typedef union tagUnIpsurxApiErrIntMask { + struct tagStIpsurxApiErrIntMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ + unsigned int reserved : 9; /* * [15:7]Reserved */ + unsigned int + errMask : 7; /* * + [6:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[6]对应TILE写给IPSURX的反标API路径上的FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。bit[5]对应CSR路径上，IPSURX时钟域到RING时钟域的 + 异步FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。Bit[4:0]对应非致命中断，用户可以根据自己需要处理。 + */ +#else + unsigned int + errMask : 7; /* * + [6:0]每一个比特对应一个中断事件。Bit[i]=1'b1，允许对应中断事件上报中断；Bit[i]=1'b0，不允许对应中断事件上报中断。bit[6]对应TILE写给IPSURX的反标API路径上的FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。bit[5]对应CSR路径上，IPSURX时钟域到RING时钟域的 + 异步FIFO溢出事件。作为致命中断，建议芯片初始化完成后打开该比特。Bit[4:0]对应非致命中断，用户可以根据自己需要处理。 + */ + unsigned int reserved : 9; /* * [15:7]Reserved */ + unsigned int programCsrId : 16; /* * [31:16]Programmable CSR ID, indicates to the CP which CSR module (or group + * of CSR modules) asked for the interrupt. + */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_ERR_INT_MASK_U; + +/* ** + * Union name : IPSURX_API_FLIT_TYPE_ERR + * @brief FLIT TYPE错误中断 + * Description: + */ +typedef union tagUnIpsurxApiFlitTypeErr { + struct tagStIpsurxApiFlitTypeErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int sticky : 2; /* * [3:2]sticky[1:0]: received flit type. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 2; /* * [3:2]sticky[1:0]: received flit type. */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_FLIT_TYPE_ERR_U; + +/* ** + * Union name : IPSURX_API_CODE_ERR + * @brief API CODE错误中断 + * Description: + */ +typedef union tagUnIpsurxApiCodeErr { + struct tagStIpsurxApiCodeErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 28; /* * [31:4]reserved. */ + unsigned int sticky : 2; /* * [3:2]sticky[1:0]: received API code field. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 2; /* * [3:2]sticky[1:0]: received API code field. */ + unsigned int reserved : 28; /* * [31:4]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_CODE_ERR_U; + +/* ** + * Union name : IPSURX_API_SRC_ERR + * @brief API SRC 错误中断 + * Description: + */ +typedef union tagUnIpsurxApiSrcErr { + struct tagStIpsurxApiSrcErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved. */ + unsigned int sticky : 5; /* * [6:2]sticky[4:0]: received API SRC field. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 5; /* * [6:2]sticky[4:0]: received API SRC field. */ + unsigned int reserved : 25; /* * [31:7]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_SRC_ERR_U; + +/* ** + * Union name : IPSURX_API_OPCODE_ERR + * @brief API OPCODE 错误中断 + * Description: + */ +typedef union tagUnIpsurxApiOpcodeErr { + struct tagStIpsurxApiOpcodeErr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 25; /* * [31:7]reserved. */ + unsigned int sticky : 5; /* * [6:2]sticky[4:0]: received API OPCODE field. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 5; /* * [6:2]sticky[4:0]: received API OPCODE field. */ + unsigned int reserved : 25; /* * [31:7]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_OPCODE_ERR_U; + +/* ** + * Union name : IPSURX_API_MERR + * @brief API错误中断寄存器 + * Description: + */ +typedef union tagUnIpsurxApiMerr { + struct tagStIpsurxApiMerr { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 22; /* * [31:10]reserved. */ + unsigned int apiAMerr : 1; /* * [9:9]API A-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiAErr : 1; /* * [8:8]API A-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiMMerr : 1; /* * [7:7]API M-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiMErr : 1; /* * [6:6]API M-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiE0Merr : 1; /* * [5:5]API E0-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiE0Err : 1; /* * [4:4]API E0-bit error1'b0: no error found;1'b1: error found. */ + unsigned int apiE1Merr : 1; /* * [3:3]API E1-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiE1Err : 1; /* * [2:2]API E1-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiSMerr : 1; /* * [1:1]API S-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiSErr : 1; /* * [0:0]API S-bit error.1'b0: no error found;1'b1: error found. */ +#else + unsigned int apiSErr : 1; /* * [0:0]API S-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiSMerr : 1; /* * [1:1]API S-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiE1Err : 1; /* * [2:2]API E1-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiE1Merr : 1; /* * [3:3]API E1-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiE0Err : 1; /* * [4:4]API E0-bit error1'b0: no error found;1'b1: error found. */ + unsigned int apiE0Merr : 1; /* * [5:5]API E0-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiMErr : 1; /* * [6:6]API M-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiMMerr : 1; /* * [7:7]API M-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int apiAErr : 1; /* * [8:8]API A-bit error.1'b0: no error found;1'b1: error found. */ + unsigned int apiAMerr : 1; /* * [9:9]API A-bit multi-error.1'b0: not more than 1 error found;1'b1: more than 1 + * errors found. + */ + unsigned int reserved : 22; /* * [31:10]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_MERR_U; + +/* ** + * Union name : IPSURX_API_MERR_MASK + * @brief API错误中断MASK寄存器 + * Description: + */ +typedef union tagUnIpsurxApiMerrMask { + struct tagStIpsurxApiMerrMask { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 27; /* * [31:5]reserved. */ + unsigned int apiAErrMask : 1; /* * [4:4]1'b1：允许上报API A比特错误中断；1'b0：不允许上报API A比特错误中断。 */ + unsigned int apiMErrMask : 1; /* * [3:3]1'b1：允许上报API M比特错误中断；1'b0：不允许上报API M比特错误中断。 */ + unsigned int apiE0ErrMask : 1; /* * [2:2]1'b1：允许上报API E0比特错误中断；1'b0：不允许上报API E0比特错误中断。 + */ + unsigned int apiE1ErrMask : 1; /* * [1:1]1'b1：允许上报API E1比特错误中断；1'b0：不允许上报API E1比特错误中断。 + */ + unsigned int apiSErrMask : 1; /* * [0:0]1'b1：允许上报API S比特错误中断；1'b0：不允许上报API S比特错误中断。 */ +#else + unsigned int apiSErrMask : 1; /* * [0:0]1'b1：允许上报API S比特错误中断；1'b0：不允许上报API S比特错误中断。 */ + unsigned int apiE1ErrMask : 1; /* * [1:1]1'b1：允许上报API E1比特错误中断；1'b0：不允许上报API E1比特错误中断。 + */ + unsigned int apiE0ErrMask : 1; /* * [2:2]1'b1：允许上报API E0比特错误中断；1'b0：不允许上报API E0比特错误中断。 + */ + unsigned int apiMErrMask : 1; /* * [3:3]1'b1：允许上报API M比特错误中断；1'b0：不允许上报API M比特错误中断。 */ + unsigned int apiAErrMask : 1; /* * [4:4]1'b1：允许上报API A比特错误中断；1'b0：不允许上报API A比特错误中断。 */ + unsigned int reserved : 27; /* * [31:5]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_MERR_MASK_U; + +/* ** + * Union name : IPSURX_RING_AFIFO_OVFL + * @brief + * Description: + */ +typedef union tagUnIpsurxRingAfifoOvfl { + struct tagStIpsurxRingAfifoOvfl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int sticky : 1; /* * [2:2]IPSURX时钟域到RING时钟域溢出异步FIFO编号。1'b0: IPSURX到RING + * CSR异步FIFO溢出；1'b1: IPSURX到RING 中断CSR异步FIFO溢出。 + */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 1; /* * [2:2]IPSURX时钟域到RING时钟域溢出异步FIFO编号。1'b0: IPSURX到RING + * CSR异步FIFO溢出；1'b1: IPSURX到RING 中断CSR异步FIFO溢出。 + */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_RING_AFIFO_OVFL_U; + +/* ** + * Union name : IPSURX_API_FIFO_OVFL + * @brief + * Description: + */ +typedef union tagUnIpsurxApiFifoOvfl { + struct tagStIpsurxApiFifoOvfl { + /* * Define the struct bits */ +#if (BYTE_ORDER == BIG_ENDIAN) + unsigned int reserved : 29; /* * [31:3]reserved. */ + unsigned int sticky : 1; /* * [2:2]TILE写给IPSURX的反标API路径上的溢出FIFO编号。1'b0: 同步FIFO溢出；1'b1: + 异步FIFO溢出。 */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ +#else + unsigned int errorBit : 1; /* * [0:0]1'b0: no error found;1'b1: error found. */ + unsigned int multiErrorBit : 1; /* * [1:1]1'b0: not more than 1 error found;1'b1: more than 1 errors found. */ + unsigned int sticky : 1; /* * [2:2]TILE写给IPSURX的反标API路径上的溢出FIFO编号。1'b0: 同步FIFO溢出；1'b1: + 异步FIFO溢出。 */ + unsigned int reserved : 29; /* * [31:3]reserved. */ +#endif + } bs; + /* * Define an unsigned member */ + unsigned int ulValue; +} CSR_IPSURX_API_FIFO_OVFL_U; + + +#ifdef __cplusplus +#if __cplusplus +} +#endif +#endif /* * __cplusplus */ + +#endif /* * HI1822_CSR_IPSURX_TYPEDEF_H */ diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_c_union_define.h new file mode 100644 index 000000000..7b545a081 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_c_union_define.h @@ -0,0 +1,2872 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : Hi1823_hi1823_typedef.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2019/09/06 10:44:42 Create file +// ****************************************************************************** + +#ifndef IPSUTX_C_UNION_DEFINE_H +#define IPSUTX_C_UNION_DEFINE_H + +/* Define the union csr_ipsutx_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fpga_ver_u; + +/* Define the union csr_ipsutx_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_emu_ver_u; + +/* Define the union csr_ipsutx_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_crc_cs_init_start : 1; /* [0] */ + u32 ipsutx_tcam_init_start : 1; /* [1] */ + u32 ipsutx_difx_rslt_init_start : 1; /* [2] */ + u32 rsv_0 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_initctab_start_u; + +/* Define the union csr_ipsutx_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_crc_cs_init_done : 1; /* [0] */ + u32 ipsutx_tcam_init_done : 1; /* [1] */ + u32 ipsutx_difx_rslt_init_done : 1; /* [2] */ + u32 rsv_1 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_initctab_done_u; + +/* Define the union csr_ipsutx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 ipsutx_int_enable : 1; /* [27] */ + u32 ipsutx_int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_int_vector_u; + +/* Define the union csr_ipsutx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_int_data : 7; /* [6:0] */ + u32 rsv_4 : 9; /* [15:7] */ + u32 ipsutx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_int_u; + +/* Define the union csr_ipsutx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_int_en : 7; /* [6:0] */ + u32 rsv_5 : 9; /* [15:7] */ + u32 ipsutx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_int_en_u; + +/* Define the union csr_ipsutx_ram_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ucerr : 1; /* [0] */ + u32 ipsutx_ram_ucerr_insrt : 1; /* [1] */ + u32 ipsutx_ram_ucerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ucerr_u; + +/* Define the union csr_ipsutx_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_cerr : 1; /* [0] */ + u32 ipsutx_ram_cerr_insrt : 1; /* [1] */ + u32 ipsutx_ram_cerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_cerr_u; + +/* Define the union csr_ipsutx_fifo_of_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_fifo_of_err : 1; /* [0] */ + u32 ipsutx_fifo_of_err_insrt : 1; /* [1] */ + u32 ipsutx_fifo_of_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_of_err_u; + +/* Define the union csr_ipsutx_sop_eop_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_sop_eop_err : 1; /* [0] */ + u32 ipsutx_sop_eop_err_insrt : 1; /* [1] */ + u32 ipsutx_sop_eop_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_sop_eop_err_u; + +/* Define the union csr_ipsutx_difx_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_err : 1; /* [0] */ + u32 ipsutx_difx_err_insrt : 1; /* [1] */ + u32 ipsutx_difx_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_u; + +/* Define the union csr_ipsutx_parse_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_parse_err : 1; /* [0] */ + u32 ipsutx_parse_err_insrt : 1; /* [1] */ + u32 ipsutx_parse_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_parse_err_u; + +/* Define the union csr_ipsutx_schnl_cfg_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_schnl_cfg_err : 1; /* [0] */ + u32 ipsutx_schnl_cfg_err_insrt : 1; /* [1] */ + u32 ipsutx_schnl_cfg_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_schnl_cfg_err_u; + +/* Define the union csr_ipsutx_err_type_int_mask_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_err_type_int_mask_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_err_type_int_mask_dw3_u; + +/* Define the union csr_ipsutx_err_type_int_mask_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_err_type_int_mask_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_err_type_int_mask_dw2_u; + +/* Define the union csr_ipsutx_err_type_int_mask_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_err_type_int_mask_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_err_type_int_mask_dw1_u; + +/* Define the union csr_ipsutx_err_type_int_mask_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_err_type_int_mask_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_err_type_int_mask_dw0_u; + +/* Define the union csr_ipsutx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_indrect_addr : 24; /* [23:0] */ + u32 ipsutx_indrect_tab : 4; /* [27:24] */ + u32 ipsutx_indrect_stat : 2; /* [29:28] */ + u32 ipsutx_indrect_mode : 1; /* [30] */ + u32 ipsutx_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_indrect_ctrl_u; + +/* Define the union csr_ipsutx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_indrect_timeout_u; + +/* Define the union csr_ipsutx_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_indrect_data_u; + +/* Define the union csr_ipsutx_cat_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 2; /* [1:0] */ + u32 ipsutx_ch_cvlan_tpid_sel : 5; /* [6:2] */ + u32 ipsutx_ch_cvlan : 1; /* [7] */ + u32 rsv_7 : 2; /* [9:8] */ + u32 ipsutx_ch_svlan_tpid_sel : 5; /* [14:10] */ + u32 ipsutx_ch_svlan : 1; /* [15] */ + u32 rsv_8 : 2; /* [17:16] */ + u32 ipsutx_ch_dsatag : 1; /* [18] */ + u32 rsv_9 : 1; /* [19] */ + u32 ipsutx_ch_evtag_tpid_sel : 4; /* [23:20] */ + u32 ipsutx_ch_evtag : 2; /* [25:24] */ + u32 rsv_10 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cat_dw0_u; + +/* Define the union csr_ipsutx_cat_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 4; /* [3:0] */ + u32 ipsutx_ch_ipv4_tcp_syn_chk_en : 1; /* [4] */ + u32 rsv_12 : 7; /* [11:5] */ + u32 ipsutx_ch_ipv4_udp_len_chk_en : 1; /* [12] */ + u32 ipsutx_ch_ipv4_dip_rsv_addr_chk_en : 1; /* [13] */ + u32 ipsutx_ch_ipv4_dip_zero_chk_en : 1; /* [14] */ + u32 ipsutx_ch_ipv4_dip_lb_chk_en : 1; /* [15] */ + u32 ipsutx_ch_ipv4_sip_lb_chk_en : 1; /* [16] */ + u32 ipsutx_ch_ipv4_sip_mc_chk_en : 1; /* [17] */ + u32 ipsutx_ch_ipv4_sip_dip_chk_en : 1; /* [18] */ + u32 ipsutx_ch_ipv4_ihl_chk_en : 1; /* [19] */ + u32 ipsutx_ch_ipv4_ver_chk_en : 1; /* [20] */ + u32 ipsutx_ch_ipv4_len_chk_en : 1; /* [21] */ + u32 rsv_13 : 6; /* [27:22] */ + u32 ipsutx_ch_8023_len_chk_en : 1; /* [28] */ + u32 ipsutx_ch_da_sa_equal_chk_en : 1; /* [29] */ + u32 ipsutx_ch_smac_chk_en : 1; /* [30] */ + u32 ipsutx_ch_dmac_zero_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cat_dw1_u; + +/* Define the union csr_ipsutx_cat_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ch_tunnel_da_sa_equal_chk_en : 1; /* [0] */ + u32 ipsutx_ch_tunnel_smac_chk_en : 1; /* [1] */ + u32 ipsutx_ch_tunnel_dmac_zero_chk_en : 1; /* [2] */ + u32 ipsutx_ch_tunnel_nvgre_cvlan_chk_en : 1; /* [3] */ + u32 rsv_14 : 4; /* [7:4] */ + u32 ipsutx_ch_tunnel_cvlan_tpid_sel : 5; /* [12:8] */ + u32 ipsutx_ch_tunnel_cvlan : 1; /* [13] */ + u32 ipsutx_ch_tunnel_svlan_tpid_sel : 5; /* [18:14] */ + u32 ipsutx_ch_tunnel_svlan : 1; /* [19] */ + u32 ipsutx_ch_tunnel_vni_chk_en : 1; /* [20] */ + u32 ipsutx_ch_nvgre_crks_chk_en : 1; /* [21] */ + u32 ipsutx_ch_ipv6_tcp_syn_chk_en : 1; /* [22] */ + u32 rsv_15 : 5; /* [27:23] */ + u32 ipsutx_ch_ipv6_dip_chk_en : 1; /* [28] */ + u32 ipsutx_ch_ipv6_sip_chk_en : 1; /* [29] */ + u32 ipsutx_ch_ipv6_ver_chk_en : 1; /* [30] */ + u32 ipsutx_ch_ipv6_len_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cat_dw2_u; + +/* Define the union csr_ipsutx_cat_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_16 : 1; /* [0] */ + u32 ipsutx_ch_tcam_key_sel : 1; /* [1] */ + u32 rsv_17 : 11; /* [12:2] */ + u32 ipsutx_ch_tunnel_ipv6_dip_chk_en : 1; /* [13] */ + u32 ipsutx_ch_tunnel_ipv6_sip_chk_en : 1; /* [14] */ + u32 ipsutx_ch_tunnel_ipv6_ver_chk_en : 1; /* [15] */ + u32 ipsutx_ch_tunnel_ipv6_len_chk_en : 1; /* [16] */ + u32 rsv_18 : 4; /* [20:17] */ + u32 ipsutx_ch_tunnel_ipv4_udp_len_chk_en : 1; /* [21] */ + u32 ipsutx_ch_tunnel_ipv4_dip_rsv_addr_chk_en : 1; /* [22] */ + u32 ipsutx_ch_tunnel_ipv4_dip_zero_chk_en : 1; /* [23] */ + u32 ipsutx_ch_tunnel_ipv4_dip_lb_chk_en : 1; /* [24] */ + u32 ipsutx_ch_tunnel_ipv4_sip_lb_chk_en : 1; /* [25] */ + u32 ipsutx_ch_tunnel_ipv4_sip_mc_chk_en : 1; /* [26] */ + u32 ipsutx_ch_tunnel_ipv4_sip_dip_chk_en : 1; /* [27] */ + u32 ipsutx_ch_tunnel_ipv4_ihl_chk_en : 1; /* [28] */ + u32 ipsutx_ch_tunnel_ipv4_ver_chk_en : 1; /* [29] */ + u32 ipsutx_ch_tunnel_ipv4_len_chk_en : 1; /* [30] */ + u32 ipsutx_ch_tunnel_8023_len_chk_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cat_dw3_u; + +/* Define the union csr_ipsutx_cpi_ec_ch_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_ec_ch0 : 5; /* [4:0] */ + u32 rsv_19 : 2; /* [6:5] */ + u32 ipsutx_cpi_ec_ch0_vld : 1; /* [7] */ + u32 ipsutx_cpi_ec_ch1 : 5; /* [12:8] */ + u32 rsv_20 : 2; /* [14:13] */ + u32 ipsutx_cpi_ec_ch1_vld : 1; /* [15] */ + u32 rsv_21 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_ec_ch_u; + +/* Define the union csr_ipsutx_cpi_virtio_ch_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_virtio_ch0 : 5; /* [4:0] */ + u32 rsv_22 : 2; /* [6:5] */ + u32 ipsutx_cpi_virtio_ch0_vld : 1; /* [7] */ + u32 ipsutx_cpi_virtio_ch1 : 5; /* [12:8] */ + u32 rsv_23 : 2; /* [14:13] */ + u32 ipsutx_cpi_virtio_ch1_vld : 1; /* [15] */ + u32 ipsutx_cpi_virtio_ch2 : 5; /* [20:16] */ + u32 rsv_24 : 2; /* [22:21] */ + u32 ipsutx_cpi_virtio_ch2_vld : 1; /* [23] */ + u32 ipsutx_cpi_virtio_ch3 : 5; /* [28:24] */ + u32 rsv_25 : 2; /* [30:29] */ + u32 ipsutx_cpi_virtio_ch3_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_virtio_ch_u; + +/* Define the union csr_ipsutx_bandwidth_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_bw : 7; /* [6:0] */ + u32 rsv_26 : 1; /* [7] */ + u32 ipsutx_petx_bw : 7; /* [14:8] */ + u32 rsv_27 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_bandwidth_cfg_u; + +/* Define the union csr_ipsutx_ppop_mpu_timer_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_mpu_timer : 20; /* [19:0] */ + u32 rsv_28 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_mpu_timer_u; + +/* Define the union csr_ipsutx_cpi_difx_ch_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_29 : 5; /* [4:0] */ + u32 ipsutx_cpi_difx_ch_en : 15; /* [19:5] */ + u32 rsv_30 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_difx_ch_en_u; + +/* Define the union csr_ipsutx_sop_eop_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sop_eop_st : 20; /* [19:0] */ + u32 ipsutx_petx_sop_eop_st : 3; /* [22:20] */ + u32 ipsutx_mpu_sop_eop_st : 1; /* [23] */ + u32 ipsutx_ppop_sop_eop_st : 1; /* [24] */ + u32 ipsutx_petx_pdu_st : 3; /* [27:25] */ + u32 rsv_31 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_sop_eop_st_u; + +/* Define the union csr_ipsutx_cpi_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_sop_with_err_cnt_u; + +/* Define the union csr_ipsutx_cpi_abort_bf_ipsutx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_abort_bf_ipsutx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_abort_bf_ipsutx_cnt_u; + +/* Define the union csr_ipsutx_cpi_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_sop_sop_err_cnt_u; + +/* Define the union csr_ipsutx_mag_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_petx_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mag_sop_with_err_cnt_u; + +/* Define the union csr_ipsutx_mag_abort_bf_ipsutx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_petx_abort_bf_ipsutx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mag_abort_bf_ipsutx_cnt_u; + +/* Define the union csr_ipsutx_mag_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_petx_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mag_sop_sop_err_cnt_u; + +/* Define the union csr_ipsutx_mag_1stpdu_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_petx_1stpdu_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mag_1stpdu_with_err_cnt_u; + +/* Define the union csr_ipsutx_mag_1stpdu_1stpdu_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_petx_1stpdu_1stpdu_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mag_1stpdu_1stpdu_err_cnt_u; + +/* Define the union csr_ipsutx_mpu_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_sop_with_err_cnt_u; + +/* Define the union csr_ipsutx_mpu_abort_bf_ipsutx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_abort_bf_ipsutx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_abort_bf_ipsutx_cnt_u; + +/* Define the union csr_ipsutx_mpu_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_sop_sop_err_cnt_u; + +/* Define the union csr_ipsutx_ppop_sop_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_sop_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_sop_with_err_cnt_u; + +/* Define the union csr_ipsutx_ppop_abort_bf_ipsutx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_abort_bf_ipsutx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_abort_bf_ipsutx_cnt_u; + +/* Define the union csr_ipsutx_ppop_sop_sop_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_sop_sop_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_sop_sop_err_cnt_u; + +/* Define the union csr_ipsutx_pkt_min_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_pkt_min_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_pkt_min_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_pkt_max_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_pkt_max_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_pkt_max_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_mpu_pkt_min_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_pkt_min_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_pkt_min_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_mpu_pkt_max_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_pkt_max_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_pkt_max_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ppop_pkt_min_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_pkt_min_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_pkt_min_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ppop_pkt_max_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_pkt_max_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_pkt_max_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ppop_mpu_timeout_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_mpu_timeout_cnt : 16; /* [15:0] */ + u32 ipsutx_ppop_timeout_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_mpu_timeout_cnt_u; + +/* Define the union csr_ipsutx_sor_eor_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sor_eor_st : 2; /* [1:0] */ + u32 rsv_32 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_sor_eor_st_u; + +/* Define the union csr_ipsutx_cpi_sor_with_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sor_with_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_sor_with_err_cnt_u; + +/* Define the union csr_ipsutx_cpi_sor_sor_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cpi_sor_sor_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cpi_sor_sor_err_cnt_u; + +/* Define the union csr_ipsutx_evtag_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_evtag_tpid2 : 16; /* [15:0] */ + u32 ipsutx_evtag_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_evtag_tpid1_u; + +/* Define the union csr_ipsutx_evtag_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_evtag_tpid0 : 16; /* [15:0] */ + u32 ipsutx_evtag_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_evtag_tpid0_u; + +/* Define the union csr_ipsutx_svlan_tpid2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_svlan_tpid4 : 16; /* [15:0] */ + u32 rsv_33 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_svlan_tpid2_u; + +/* Define the union csr_ipsutx_svlan_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_svlan_tpid2 : 16; /* [15:0] */ + u32 ipsutx_svlan_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_svlan_tpid1_u; + +/* Define the union csr_ipsutx_svlan_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_svlan_tpid0 : 16; /* [15:0] */ + u32 ipsutx_svlan_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_svlan_tpid0_u; + +/* Define the union csr_ipsutx_cvlan_tpid2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cvlan_tpid4 : 16; /* [15:0] */ + u32 rsv_34 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cvlan_tpid2_u; + +/* Define the union csr_ipsutx_cvlan_tpid1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cvlan_tpid2 : 16; /* [15:0] */ + u32 ipsutx_cvlan_tpid3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cvlan_tpid1_u; + +/* Define the union csr_ipsutx_cvlan_tpid0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cvlan_tpid0 : 16; /* [15:0] */ + u32 ipsutx_cvlan_tpid1 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cvlan_tpid0_u; + +/* Define the union csr_ipsutx_8023_max_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_8023_max_len : 11; /* [10:0] */ + u32 rsv_35 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_8023_max_len_u; + +/* Define the union csr_ipsutx_8023_jumbo_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_8023_jumbo_tpid : 16; /* [15:0] */ + u32 ipsutx_8023_jumbo_chk_en : 1; /* [16] */ + u32 rsv_36 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_8023_jumbo_cfg_u; + +/* Define the union csr_ipsutx_l2_dmac_eth_chk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_lldp_dmac_chk_en : 1; /* [0] */ + u32 ipsutx_lacp_dmac_chk_en : 1; /* [1] */ + u32 ipsutx_pfc_dmac_chk_en : 1; /* [2] */ + u32 ipsutx_pause_dmac_chk_en : 1; /* [3] */ + u32 ipsutx_tunnel_lldp_dmac_chk_en : 1; /* [4] */ + u32 ipsutx_tunnel_lacp_dmac_chk_en : 1; /* [5] */ + u32 ipsutx_tunnel_pfc_dmac_chk_en : 1; /* [6] */ + u32 ipsutx_tunnel_pause_dmac_chk_en : 1; /* [7] */ + u32 rsv_37 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2_dmac_eth_chk_en_u; + +/* Define the union csr_ipsutx_igmpv4_dip_chk_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_igmpv4_dip_chk_en : 1; /* [0] */ + u32 rsv_38 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_igmpv4_dip_chk_en_u; + +/* Define the union csr_ipsutx_ipv6_spec_mc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_spec_mcast : 16; /* [15:0] */ + u32 ipsutx_ipv6_spec_mcast_mask : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_spec_mc_u; + +/* Define the union csr_ipsutx_rocev2_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_rocev2_dport : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_rocev2_dport_u; + +/* Define the union csr_ipsutx_natt_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_natt_dport : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_natt_dport_u; + +/* Define the union csr_ipsutx_vxlan_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_vxlan_dport : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_vxlan_dport_u; + +/* Define the union csr_ipsutx_vxlan_gpe_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_vxlan_gpe_dport : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_vxlan_gpe_dport_u; + +/* Define the union csr_ipsutx_geneve_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_geneve_dport : 16; /* [15:0] */ + u32 rsv_43 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_geneve_dport_u; + +/* Define the union csr_ipsutx_ipv4_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_np : 8; /* [7:0] */ + u32 rsv_44 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_np_u; + +/* Define the union csr_ipsutx_ipv6_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_np : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_np_u; + +/* Define the union csr_ipsutx_ethernet_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ethernet_np : 8; /* [7:0] */ + u32 rsv_46 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ethernet_np_u; + +/* Define the union csr_ipsutx_ioam_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ioam_np : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ioam_np_u; + +/* Define the union csr_ipsutx_int_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_int_np : 8; /* [7:0] */ + u32 rsv_48 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_int_np_u; + +/* Define the union csr_ipsutx_nsh_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_nsh_np : 8; /* [7:0] */ + u32 rsv_49 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_nsh_np_u; + +/* Define the union csr_ipsutx_ah_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ah_np : 8; /* [7:0] */ + u32 rsv_50 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ah_np_u; + +/* Define the union csr_ipsutx_esp_np_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_esp_np : 8; /* [7:0] */ + u32 rsv_51 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_esp_np_u; + +/* Define the union csr_ipsutx_tcp_coco_with_ts_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcp_coco_with_ts_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcp_coco_with_ts_dw0_u; + +/* Define the union csr_ipsutx_tcp_coco_without_ts_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcp_coco_without_ts_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcp_coco_without_ts_dw0_u; + +/* Define the union csr_ipsutx_tcp_coco_dw0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcp_coco_dw0_mask : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcp_coco_dw0_mask_u; + +/* Define the union csr_ipsutx_ipv6_ext_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_ext_nh : 8; /* [7:0] */ + u32 ipsutx_ipv6_ext_vld : 1; /* [8] */ + u32 rsv_52 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_ext_ctrl_u; + +/* Define the union csr_ipsutx_bgp_dport_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_bgp_dport : 16; /* [15:0] */ + u32 rsv_53 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_bgp_dport_u; + +/* Define the union csr_ipsutx_esp_prtl_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_esp_prtl_type : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_esp_prtl_type_u; + +/* Define the union csr_ipsutx_crc_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_crc_dat_bit_rev : 1; /* [0] */ + u32 ipsutx_difx_crc_rslt_bit_rev : 1; /* [1] */ + u32 ipsutx_difx_crc_rslt_inv : 1; /* [2] */ + u32 rsv_55 : 1; /* [3] */ + u32 ipsutx_difx_crc2_dat_bit_rev : 1; /* [4] */ + u32 ipsutx_difx_crc2_rslt_bit_rev : 1; /* [5] */ + u32 ipsutx_difx_crc2_rslt_inv : 1; /* [6] */ + u32 rsv_56 : 1; /* [7] */ + u32 ipsutx_iscsi_crc_dat_bit_rev : 1; /* [8] */ + u32 ipsutx_iscsi_crc_rslt_bit_rev : 1; /* [9] */ + u32 ipsutx_iscsi_crc_rslt_inv : 1; /* [10] */ + u32 rsv_57 : 1; /* [11] */ + u32 ipsutx_sctp_crc_dat_bit_rev : 1; /* [12] */ + u32 ipsutx_sctp_crc_rslt_bit_rev : 1; /* [13] */ + u32 ipsutx_sctp_crc_rslt_inv : 1; /* [14] */ + u32 rsv_58 : 4; /* [18:15] */ + u32 ipsutx_difx_cs_rslt_bit_inv : 1; /* [19] */ + u32 ipsutx_difx_cs_rslt_1s_inv : 1; /* [20] */ + u32 ipsutx_difx_cs_rslt_0s_inv : 1; /* [21] */ + u32 rsv_59 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_crc_ctrl_u; + +/* Define the union csr_ipsutx_sctp_crc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_sctp_crc_ini : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_sctp_crc_ini_u; + +/* Define the union csr_ipsutx_iscsi_crc_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_iscsi_crc_ini : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_iscsi_crc_ini_u; + +/* Define the union csr_ipsutx_difx_agm_ini_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_cs_ini : 16; /* [15:0] */ + u32 ipsutx_difx_crc_ini : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_agm_ini_u; + +/* Define the union csr_ipsutx_difx_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_verify_special_case_en : 1; /* [0] */ + u32 rsv_60 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_ctrl_u; + +/* Define the union csr_ipsutx_l2nic_fwd_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_fwd_pkt_len_max : 19; /* [18:0] */ + u32 rsv_61 : 5; /* [23:19] */ + u32 ipsutx_l2nic_fwd_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_fwd_pkt_len_u; + +/* Define the union csr_ipsutx_l2nic_parse_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_parse_pkt_len_max : 19; /* [18:0] */ + u32 rsv_62 : 5; /* [23:19] */ + u32 ipsutx_l2nic_parse_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_parse_pkt_len_u; + +/* Define the union csr_ipsutx_l2nic_gso_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_gso_pkt_len_max : 19; /* [18:0] */ + u32 rsv_63 : 5; /* [23:19] */ + u32 ipsutx_l2nic_gso_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_gso_pkt_len_u; + +/* Define the union csr_ipsutx_ec_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_pkt_len_max : 19; /* [18:0] */ + u32 rsv_64 : 5; /* [23:19] */ + u32 ipsutx_ec_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_pkt_len_u; + +/* Define the union csr_ipsutx_non_l2nic_fwd_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_non_l2nic_fwd_pkt_len_max : 19; /* [18:0] */ + u32 rsv_65 : 5; /* [23:19] */ + u32 ipsutx_non_l2nic_fwd_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_non_l2nic_fwd_pkt_len_u; + +/* Define the union csr_ipsutx_toe_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_toe_pkt_len_max : 19; /* [18:0] */ + u32 rsv_66 : 5; /* [23:19] */ + u32 ipsutx_toe_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_toe_pkt_len_u; + +/* Define the union csr_ipsutx_non_tcp_difx_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_non_tcp_difx_pkt_len_max : 19; /* [18:0] */ + u32 rsv_67 : 5; /* [23:19] */ + u32 ipsutx_non_tcp_difx_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_non_tcp_difx_pkt_len_u; + +/* Define the union csr_ipsutx_ioe_difx_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ioe_difx_pkt_len_max : 19; /* [18:0] */ + u32 rsv_68 : 5; /* [23:19] */ + u32 ipsutx_ioe_difx_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ioe_difx_pkt_len_u; + +/* Define the union csr_ipsutx_ipsec_lb_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipsec_lb_pkt_len_max : 19; /* [18:0] */ + u32 rsv_69 : 5; /* [23:19] */ + u32 ipsutx_ipsec_lb_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipsec_lb_pkt_len_u; + +/* Define the union csr_ipsutx_pkt_lb_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_pkt_lb_pkt_len_max : 19; /* [18:0] */ + u32 rsv_70 : 5; /* [23:19] */ + u32 ipsutx_pkt_lb_pkt_len_min : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_pkt_lb_pkt_len_u; + +/* Define the union csr_ipsutx_mpu_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_pkt_len_max : 16; /* [15:0] */ + u32 ipsutx_up_pkt_len_min : 8; /* [23:16] */ + u32 rsv_71 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_pkt_len_u; + +/* Define the union csr_ipsutx_ppop_pkt_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_pkt_len_max : 16; /* [15:0] */ + u32 ipsutx_ppop_pkt_len_min : 8; /* [23:16] */ + u32 rsv_72 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_pkt_len_u; + +/* Define the union csr_ipsutx_mpu_push_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_push_len : 4; /* [3:0] */ + u32 rsv_73 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_push_len_u; + +/* Define the union csr_ipsutx_ppop_push_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_push_len : 4; /* [3:0] */ + u32 rsv_74 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_push_len_u; + +/* Define the union csr_ipsutx_push_len_l2f_oth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_push_len_l2f_none : 4; /* [3:0] */ + u32 rsv_75 : 4; /* [7:4] */ + u32 ipsutx_push_len_err : 4; /* [11:8] */ + u32 rsv_76 : 4; /* [15:12] */ + u32 ipsutx_push_len_max : 4; /* [19:16] */ + u32 ipsutx_push_len_gso_no_hdr : 4; /* [23:20] */ + u32 ipsutx_push_len_pldofs_non_zero : 4; /* [27:24] */ + u32 rsv_77 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_push_len_l2f_oth_u; + +/* Define the union csr_ipsutx_push_len_l3f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_push_len_l3f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_push_len_l3f_u; + +/* Define the union csr_ipsutx_push_len_l45f_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_push_len_l45f : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_push_len_l45f_u; + +/* Define the union csr_ipsutx_l2nic_fwd_dir_push_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_fwd_dir_push_len : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_fwd_dir_push_len_u; + +/* Define the union csr_ipsutx_l2nic_fwd_dir_sumop1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_fwd_dir_sumop1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_fwd_dir_sumop1_u; + +/* Define the union csr_ipsutx_l2nic_fwd_dir_sumop0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_fwd_dir_sumop0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_fwd_dir_sumop0_u; + +/* Define the union csr_ipsutx_mpu_sum_op_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_up_totile_sumop : 8; /* [7:0] */ + u32 ipsutx_up_tooq_sumop : 8; /* [15:8] */ + u32 rsv_78 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_sum_op_u; + +/* Define the union csr_ipsutx_ppop_sum_op_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_totile_sumop : 8; /* [7:0] */ + u32 rsv_79 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_sum_op_u; + +/* Define the union csr_ipsutx_dmac_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_dmac_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_dmac_zero_cnt_u; + +/* Define the union csr_ipsutx_smac_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_smac_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_smac_ilgl_cnt_u; + +/* Define the union csr_ipsutx_da_sa_equal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_da_sa_equal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_da_sa_equal_cnt_u; + +/* Define the union csr_ipsutx_eth_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_eth_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_eth_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_dmac_zero_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_dmac_zero_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_dmac_zero_cnt_u; + +/* Define the union csr_ipsutx_tunnel_smac_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_smac_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_smac_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_da_sa_equal_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_da_sa_equal_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_da_sa_equal_cnt_u; + +/* Define the union csr_ipsutx_tunnel_eth_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_eth_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_eth_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_ver_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_ihl_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_ihl_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_ihl_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_sip_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_sip_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_sip_dip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_sip_mc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_sip_mc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_sip_mc_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_sip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_sip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_sip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_dip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_dip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_dip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_dip_zero_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_dip_zero_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_dip_zero_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_dip_rsv_addr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_dip_rsv_addr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_dip_rsv_addr_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_udp_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_udp_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_udp_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv4_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv4_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv4_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv6_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_ver_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv6_sip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_sip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_sip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv6_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_dip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ipv6_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ipv6_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ipv6_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_ver_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_ihl_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_ihl_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_ihl_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_sip_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_sip_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_sip_dip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_sip_mc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_sip_mc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_sip_mc_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_sip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_sip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_sip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_dip_lb_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_dip_lb_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_dip_lb_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_dip_zero_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_dip_zero_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_dip_zero_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_dip_rsv_addr_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_udp_len_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_udp_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_udp_len_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv4_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv4_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv4_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv6_ver_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv6_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv6_ver_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv6_sip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv6_sip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv6_sip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv6_dip_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv6_dip_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv6_dip_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tunnel_ipv6_tlen_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_ipv6_tlen_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_ipv6_tlen_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tcp_land_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcp_land_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcp_land_ilgl_cnt_u; + +/* Define the union csr_ipsutx_llc_snap_enc_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_llc_snap_enc_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_llc_snap_enc_ilgl_cnt_u; + +/* Define the union csr_ipsutx_eth_type_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_eth_type_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_eth_type_ilgl_cnt_u; + +/* Define the union csr_ipsutx_vxlan_gpe_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_vxlan_gpe_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_vxlan_gpe_other_ver_cnt_u; + +/* Define the union csr_ipsutx_geneve_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_geneve_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_geneve_other_ver_cnt_u; + +/* Define the union csr_ipsutx_nsh_other_ver_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_nsh_other_ver_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_nsh_other_ver_cnt_u; + +/* Define the union csr_ipsutx_nsh_len_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_nsh_len_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_nsh_len_cnt_u; + +/* Define the union csr_ipsutx_tunnel_nvgre_cvlan_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tunnel_nvgre_cvlan_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tunnel_nvgre_cvlan_ilgl_cnt_u; + +/* Define the union csr_ipsutx_nvgre_crks_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_nvgre_crks_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_nvgre_crks_ilgl_cnt_u; + +/* Define the union csr_ipsutx_hdr_len_min_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdr_len_min_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_hdr_len_min_ilgl_cnt_u; + +/* Define the union csr_ipsutx_sctp_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_sctp_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_sctp_ilgl_cnt_u; + +/* Define the union csr_ipsutx_gso_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_gso_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_gso_ilgl_cnt_u; + +/* Define the union csr_ipsutx_lli_type_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_lli_type : 16; /* [15:0] */ + u32 ipsutx_lli_type_vld : 1; /* [16] */ + u32 rsv_80 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_lli_type_u; + +/* Define the union csr_ipsutx_tcam_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcam_bk_scan_period : 8; /* [7:0] */ + u32 ipsutx_tcam_bk_scan_interval_unit : 8; /* [15:8] */ + u32 ipsutx_tcam_lkup_en : 1; /* [16] */ + u32 rsv_81 : 10; /* [26:17] */ + u32 ipsutx_tcam_mbist_en : 1; /* [27] */ + u32 ipsutx_tcam_mbist_test : 2; /* [29:28] */ + u32 ipsutx_tcam_mbist_t_sel : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcam_ctrl_u; + +/* Define the union csr_ipsutx_tcam_mbist_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcam_mbist_done : 1; /* [0] */ + u32 rsv_82 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcam_mbist_done_u; + +/* Define the union csr_ipsutx_ec_rf_mask0_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask0_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask0_dw0_u; + +/* Define the union csr_ipsutx_ec_rf_mask0_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask0_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask0_dw1_u; + +/* Define the union csr_ipsutx_ec_rf_mask0_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask0_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask0_dw2_u; + +/* Define the union csr_ipsutx_ec_rf_mask0_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask0_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask0_dw3_u; + +/* Define the union csr_ipsutx_ec_rf_mask1_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask1_dw0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask1_dw0_u; + +/* Define the union csr_ipsutx_ec_rf_mask1_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask1_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask1_dw1_u; + +/* Define the union csr_ipsutx_ec_rf_mask1_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask1_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask1_dw2_u; + +/* Define the union csr_ipsutx_ec_rf_mask1_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ec_rf_mask1_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ec_rf_mask1_dw3_u; + +/* Define the union csr_ipsutx_tcam_mbist_mem_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcam_mbist_mem_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcam_mbist_mem_err_cnt_u; + +/* Define the union csr_ipsutx_tcam_mbist_cmp_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcam_mbist_cmp_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcam_mbist_cmp_err_cnt_u; + +/* Define the union csr_ipsutx_uncrt_err_ctrl_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_ovfl_ctrl : 1; /* [0] */ + u32 ipsutx_datf_ovfl_ctrl : 1; /* [1] */ + u32 ipsutx_cincf_ovfl_ctrl : 1; /* [2] */ + u32 ipsutx_ciec0f_ovfl_ctrl : 1; /* [3] */ + u32 ipsutx_ciec1f_ovfl_ctrl : 1; /* [4] */ + u32 rsv_83 : 4; /* [8:5] */ + u32 ipsutx_pktlbf_ovfl_ctrl : 1; /* [9] */ + u32 ipsutx_difxf_ovfl_ctrl : 1; /* [10] */ + u32 ipsutx_haf_ovfl_ctrl : 1; /* [11] */ + u32 ipsutx_ecf_ovfl_ctrl : 1; /* [12] */ + u32 ipsutx_ulef_ovfl_ctrl : 1; /* [13] */ + u32 rsv_84 : 1; /* [14] */ + u32 ipsutx_tenqf_ovfl_ctrl : 1; /* [15] */ + u32 rsv_85 : 4; /* [19:16] */ + u32 ipsutx_fatal_err_ctrl : 1; /* [20] */ + u32 rsv_86 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_uncrt_err_ctrl_dw0_u; + +/* Define the union csr_ipsutx_uncrt_err_ctrl_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_ram_uncrt_ctrl : 1; /* [0] */ + u32 ipsutx_datf_ram_uncrt_ctrl : 1; /* [1] */ + u32 ipsutx_tcam_uncrt_ctrl : 1; /* [2] */ + u32 ipsutx_tcam_art_uncrt_ctrl : 1; /* [3] */ + u32 ipsutx_cif_ram_uncrt_ctrl : 1; /* [4] */ + u32 ipsutx_difxcalc_ctx6_uncrt_ctrl : 1; /* [5] */ + u32 ipsutx_difxf_ram_uncrt_ctrl : 1; /* [6] */ + u32 ipsutx_haf_ram_uncrt_ctrl : 1; /* [7] */ + u32 ipsutx_ulef_ram_uncrt_ctrl : 1; /* [8] */ + u32 rsv_87 : 1; /* [9] */ + u32 ipsutx_tenqf_ram_uncrt_ctrl : 1; /* [10] */ + u32 ipsutx_difxram_uncrt_ctrl : 1; /* [11] */ + u32 ipsutx_difx_rslt_ctx_uncrt_ctrl : 1; /* [12] */ + u32 ipsutx_segspl_ctx1_uncrt_ctrl : 1; /* [13] */ + u32 ipsutx_tenq_ctx3_uncrt_ctrl : 1; /* [14] */ + u32 rsv_88 : 1; /* [15] */ + u32 ipsutx_cpi_sop_sop_err_ctrl : 1; /* [16] */ + u32 ipsutx_cpi_sop_with_err_ctrl : 1; /* [17] */ + u32 ipsutx_petx_sop_sop_err_ctrl : 1; /* [18] */ + u32 ipsutx_petx_sop_with_err_ctrl : 1; /* [19] */ + u32 ipsutx_petx_1stpdu_1stpdu_err_ctrl : 1; /* [20] */ + u32 ipsutx_petx_1stpdu_with_err_ctrl : 1; /* [21] */ + u32 ipsutx_mpu_sop_sop_err_ctrl : 1; /* [22] */ + u32 ipsutx_mpu_sop_with_err_ctrl : 1; /* [23] */ + u32 ipsutx_mpu_timeout_ctrl : 1; /* [24] */ + u32 ipsutx_ppop_sop_sop_err_ctrl : 1; /* [25] */ + u32 ipsutx_ppop_sop_with_err_ctrl : 1; /* [26] */ + u32 ipsutx_ppop_timeout_ctrl : 1; /* [27] */ + u32 ipsutx_cpi_sor_sor_err_crtl : 1; /* [28] */ + u32 ipsutx_cpi_sor_with_err_ctrl : 1; /* [29] */ + u32 rsv_89 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_uncrt_err_ctrl_dw1_u; + +/* Define the union csr_ipsutx_rammod_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tp_ram_tmod_ctrl : 8; /* [7:0] */ + u32 ipsutx_sp_ram_tmod_ctrl : 7; /* [14:8] */ + u32 ipsutx_mem_power_mode_ctrl : 6; /* [20:15] */ + u32 rsv_90 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_rammod_ctrl_u; + +/* Define the union csr_ipsutx_ram_err_chk_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_err_chk_bypass : 1; /* [0] */ + u32 rsv_91 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_err_chk_bypass_u; + +/* Define the union csr_ipsutx_ram_err_inj_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_ram_uncrt_err_inj : 1; /* [0] */ + u32 ipsutx_datf_ram_uncrt_err_inj : 1; /* [1] */ + u32 ipsutx_tcam_uncrt_err_inj : 1; /* [2] */ + u32 ipsutx_tcam_art_uncrt_err_inj : 1; /* [3] */ + u32 ipsutx_cif_ram_uncrt_err_inj : 1; /* [4] */ + u32 ipsutx_difxcalc_ctx6_uncrt_err_inj : 1; /* [5] */ + u32 ipsutx_difxf_ram_uncrt_err_inj : 1; /* [6] */ + u32 ipsutx_haf_ram_uncrt_err_inj : 1; /* [7] */ + u32 ipsutx_ulef_ram_uncrt_err_inj : 1; /* [8] */ + u32 rsv_92 : 1; /* [9] */ + u32 ipsutx_tenqf_ram_uncrt_err_inj : 1; /* [10] */ + u32 ipsutx_difxram_uncrt_err_inj : 1; /* [11] */ + u32 ipsutx_difx_rslt_ctx_uncrt_err_inj : 1; /* [12] */ + u32 ipsutx_segspl_ctx1_uncrt_err_inj : 1; /* [13] */ + u32 ipsutx_tenq_ctx3_uncrt_err_inj : 1; /* [14] */ + u32 rsv_93 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_err_inj_dw0_u; + +/* Define the union csr_ipsutx_ram_err_inj_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_ram_crt_err_inj : 1; /* [0] */ + u32 ipsutx_datf_ram_crt_err_inj : 1; /* [1] */ + u32 ipsutx_tcam_crt_err_inj : 1; /* [2] */ + u32 ipsutx_tcam_art_crt_err_inj : 1; /* [3] */ + u32 ipsutx_cif_ram_crt_err_inj : 1; /* [4] */ + u32 ipsutx_difxcalc_ctx6_crt_err_inj : 1; /* [5] */ + u32 ipsutx_difxf_ram_crt_err_inj : 1; /* [6] */ + u32 ipsutx_haf_ram_crt_err_inj : 1; /* [7] */ + u32 ipsutx_ulef_ram_crt_err_inj : 1; /* [8] */ + u32 rsv_94 : 1; /* [9] */ + u32 ipsutx_tenqf_ram_crt_err_inj : 1; /* [10] */ + u32 ipsutx_difxram_crt_err_inj : 1; /* [11] */ + u32 ipsutx_difx_rslt_ctx_crt_err_inj : 1; /* [12] */ + u32 ipsutx_segspl_ctx1_crt_err_inj : 1; /* [13] */ + u32 ipsutx_tenq_ctx3_crt_err_inj : 1; /* [14] */ + u32 rsv_95 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_err_inj_dw1_u; + +/* Define the union csr_ipsutx_fifo_th1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_af_th : 7; /* [6:0] */ + u32 rsv_96 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_th1_u; + +/* Define the union csr_ipsutx_fifo_th0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tenqof_af_th : 7; /* [6:0] */ + u32 rsv_97 : 9; /* [15:7] */ + u32 ipsutx_ulef_af_th : 7; /* [22:16] */ + u32 rsv_98 : 1; /* [23] */ + u32 ipsutx_difxf_af_th : 6; /* [29:24] */ + u32 rsv_99 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_th0_u; + +/* Define the union csr_ipsutx_fifo_sts5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_100 : 12; /* [11:0] */ + u32 ipsutx_tenqof_cnt : 7; /* [18:12] */ + u32 ipsutx_tenqof_empty : 1; /* [19] */ + u32 ipsutx_tenqof_full : 1; /* [20] */ + u32 ipsutx_tenqof_of : 1; /* [21] */ + u32 ipsutx_tenqof_af : 1; /* [22] */ + u32 rsv_101 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_sts5_u; + +/* Define the union csr_ipsutx_fifo_sts4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ecf_cnt : 5; /* [4:0] */ + u32 ipsutx_ecf_empty : 1; /* [5] */ + u32 ipsutx_ecf_full : 1; /* [6] */ + u32 ipsutx_ecf_of : 1; /* [7] */ + u32 rsv_102 : 8; /* [15:8] */ + u32 ipsutx_ulef_cnt : 7; /* [22:16] */ + u32 ipsutx_ulef_empty : 1; /* [23] */ + u32 ipsutx_ulef_full : 1; /* [24] */ + u32 ipsutx_ulef_of : 1; /* [25] */ + u32 ipsutx_ulef_af : 1; /* [26] */ + u32 rsv_103 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_sts4_u; + +/* Define the union csr_ipsutx_fifo_sts3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difxf_cnt : 6; /* [5:0] */ + u32 ipsutx_difxf_empty : 1; /* [6] */ + u32 ipsutx_difxf_full : 1; /* [7] */ + u32 ipsutx_difxf_of : 1; /* [8] */ + u32 ipsutx_difxf_af : 1; /* [9] */ + u32 rsv_104 : 2; /* [11:10] */ + u32 ipsutx_haf_cnt : 7; /* [18:12] */ + u32 ipsutx_haf_empty : 1; /* [19] */ + u32 ipsutx_haf_full : 1; /* [20] */ + u32 ipsutx_haf_of : 1; /* [21] */ + u32 ipsutx_datf_cnt : 6; /* [27:22] */ + u32 ipsutx_datf_empty : 1; /* [28] */ + u32 ipsutx_datf_full : 1; /* [29] */ + u32 ipsutx_datf_of : 1; /* [30] */ + u32 rsv_105 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_sts3_u; + +/* Define the union csr_ipsutx_fifo_sts2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_hdrf_cnt : 7; /* [6:0] */ + u32 ipsutx_hdrf_empty : 1; /* [7] */ + u32 ipsutx_hdrf_full : 1; /* [8] */ + u32 ipsutx_hdrf_of : 1; /* [9] */ + u32 ipsutx_hdrf_af : 1; /* [10] */ + u32 rsv_106 : 9; /* [19:11] */ + u32 ipsutx_pktlbf_cnt : 5; /* [24:20] */ + u32 ipsutx_pktlbf_empty : 1; /* [25] */ + u32 ipsutx_pktlbf_full : 1; /* [26] */ + u32 ipsutx_pktlbf_of : 1; /* [27] */ + u32 rsv_107 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_sts2_u; + +/* Define the union csr_ipsutx_fifo_sts1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cincf_cnt : 6; /* [5:0] */ + u32 ipsutx_cincf_empty : 1; /* [6] */ + u32 ipsutx_cincf_full : 1; /* [7] */ + u32 ipsutx_cincf_of : 1; /* [8] */ + u32 ipsutx_ciec0f_cnt : 6; /* [14:9] */ + u32 ipsutx_ciec0f_empty : 1; /* [15] */ + u32 ipsutx_ciec0f_full : 1; /* [16] */ + u32 ipsutx_ciec0f_of : 1; /* [17] */ + u32 rsv_108 : 2; /* [19:18] */ + u32 ipsutx_ciec1f_cnt : 6; /* [25:20] */ + u32 ipsutx_ciec1f_empty : 1; /* [26] */ + u32 ipsutx_ciec1f_full : 1; /* [27] */ + u32 ipsutx_ciec1f_of : 1; /* [28] */ + u32 rsv_109 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_fifo_sts1_u; + +/* Define the union csr_ipsutx_ram_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ucerr_cnt_u; + +/* Define the union csr_ipsutx_ram_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_cerr_cnt_u; + +/* Define the union csr_ipsutx_ram_ctrl_bus_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ctrl_bus_dw0 : 6; /* [5:0] */ + u32 rsv_110 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ctrl_bus_dw0_u; + +/* Define the union csr_ipsutx_ram_ctrl_bus_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ctrl_bus_dw1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ctrl_bus_dw1_u; + +/* Define the union csr_ipsutx_ram_ctrl_bus_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ctrl_bus_dw2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ctrl_bus_dw2_u; + +/* Define the union csr_ipsutx_ram_ctrl_bus_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ctrl_bus_dw3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ctrl_bus_dw3_u; + +/* Define the union csr_ipsutx_ram_ctrl_bus_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ram_ctrl_bus_dw4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ram_ctrl_bus_dw4_u; + +/* Define the union csr_ipsutx_tcam_ctrl_bus_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcam_ctrl_bus : 10; /* [9:0] */ + u32 rsv_111 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcam_ctrl_bus_u; + +/* Define the union csr_ipsutx_rcv_cpb_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_rcv_cpb_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_rcv_cpb_bp_cnt_u; + +/* Define the union csr_ipsutx_mpu_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_mpu_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_mpu_bp_cnt_u; + +/* Define the union csr_ipsutx_ppop_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ppop_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ppop_bp_cnt_u; + +/* Define the union csr_ipsutx_difx_grd_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_grd_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_grd_ilgl_cnt_u; + +/* Define the union csr_ipsutx_difx_ref_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_ref_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_ref_ilgl_cnt_u; + +/* Define the union csr_ipsutx_difx_app_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_app_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_app_ilgl_cnt_u; + +/* Define the union csr_ipsutx_gso_sctp_plofs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_gso_sctp_plofs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_gso_sctp_plofs_ilgl_cnt_u; + +/* Define the union csr_ipsutx_tcp_sd_ofs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tcp_sd_ofs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tcp_sd_ofs_ilgl_cnt_u; + +/* Define the union csr_ipsutx_l2nic_plofs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_l2nic_plofs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_l2nic_plofs_ilgl_cnt_u; + +/* Define the union csr_ipsutx_ioe_rsp_hdr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_ioe_rsp_hdr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_ioe_rsp_hdr_ilgl_cnt_u; + +/* Define the union csr_ipsutx_pkt_lb_md_hdr_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_pkt_lb_md_hdr_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_pkt_lb_md_hdr_ilgl_cnt_u; + +/* Define the union csr_ipsutx_pdu_sd_ofs_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_pdu_sd_ofs_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_pdu_sd_ofs_ilgl_cnt_u; + +/* Define the union csr_ipsutx_cry_err1_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cry_err1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cry_err1_ilgl_cnt_u; + +/* Define the union csr_ipsutx_cry_err2_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cry_err2_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cry_err2_ilgl_cnt_u; + +/* Define the union csr_ipsutx_cry_bd_ilgl_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_cry_bd_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_cry_bd_ilgl_ilgl_cnt_u; + +/* Define the union csr_ipsutx_rx_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_rx_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_rx_pkt_cnt_u; + +/* Define the union csr_ipsutx_tx_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_tx_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_tx_pkt_cnt_u; + +/* Define the union csr_ipsutx_edit_type_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_edit_type_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_edit_type_pkt_cnt_u; + +/* Define the union csr_ipsutx_edit_type_cry_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_edit_type_cry_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_edit_type_cry_pkt_cnt_u; + +/* Define the union csr_ipsutx_patn_id_ext_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_patn_id_ext : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_patn_id_ext_u; + +/* Define the union csr_ipsutx_patn_id_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_patn_id_int : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_patn_id_int_u; + +/* Define the union csr_ipsutx_err_patn_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_err_patn_id : 4; /* [3:0] */ + u32 rsv_112 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_err_patn_id_u; + +/* Define the union csr_ipsutx_virtio_patn_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_virtio_patn_id : 4; /* [3:0] */ + u32 rsv_113 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_virtio_patn_id_u; + +/* Define the union csr_ipsutx_difx_err_dfx_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_err_dfx_clr : 1; /* [0] */ + u32 rsv_114 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_dfx_clr_u; + +/* Define the union csr_ipsutx_difx_err_info_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_guard_err : 1; /* [0] */ + u32 ipsutx_difx_app_err : 1; /* [1] */ + u32 ipsutx_difx_ref_err : 1; /* [2] */ + u32 rsv_115 : 1; /* [3] */ + u32 ipsutx_difx_vrf_type : 2; /* [5:4] */ + u32 rsv_116 : 2; /* [7:6] */ + u32 ipsutx_difx_err_schnl : 5; /* [12:8] */ + u32 rsv_117 : 3; /* [15:13] */ + u32 ipsutx_difx_task_tag : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_info_dw0_u; + +/* Define the union csr_ipsutx_difx_err_info_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_rcv_guard : 16; /* [15:0] */ + u32 ipsutx_difx_rcv_app : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_info_dw1_u; + +/* Define the union csr_ipsutx_difx_err_info_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_rcv_ref : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_info_dw2_u; + +/* Define the union csr_ipsutx_difx_err_info_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_exp_guard : 16; /* [15:0] */ + u32 ipsutx_difx_exp_app : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_info_dw3_u; + +/* Define the union csr_ipsutx_difx_err_info_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsutx_difx_exp_ref : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ipsutx_difx_err_info_dw4_u; + +#endif // IPSUTX_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_reg_offset.h new file mode 100644 index 000000000..6e99fe2bf --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ipsutx_reg_offset.h @@ -0,0 +1,429 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : Hi1823_hi1823_addr_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : 2019/09/06 10:44:42 Create file +// ****************************************************************************** + +#ifndef IPSUTX_REG_OFFSET_H +#define IPSUTX_REG_OFFSET_H + +/* IPSUTX_CSR Base address of Module's Register */ +#define CSR_IPSUTX_CSR_BASE (0x2000) + +/* **************************************************************************** */ +/* IPSUTX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_IPSUTX_CSR_IPSUTX_FPGA_VER_REG (CSR_IPSUTX_CSR_BASE + 0x0) /* 版本寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EMU_VER_REG (CSR_IPSUTX_CSR_BASE + 0x4) /* 版本寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INITCTAB_START_REG (CSR_IPSUTX_CSR_BASE + 0x8) /* 配置表初始化使能寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INITCTAB_DONE_REG (CSR_IPSUTX_CSR_BASE + 0xC) /* 配置表初始化状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INT_VECTOR_REG (CSR_IPSUTX_CSR_BASE + 0x10) /* Interrupt Vector Register */ +#define CSR_IPSUTX_CSR_IPSUTX_INT_REG (CSR_IPSUTX_CSR_BASE + 0x14) /* Interrupt Data Register */ +#define CSR_IPSUTX_CSR_IPSUTX_INT_EN_REG (CSR_IPSUTX_CSR_BASE + 0x18) /* Interrupt Mask Register */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_UCERR_REG (CSR_IPSUTX_CSR_BASE + 0x1C) /* RAM不可纠错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CERR_REG (CSR_IPSUTX_CSR_BASE + 0x20) /* RAM可纠错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_OF_ERR_REG (CSR_IPSUTX_CSR_BASE + 0x24) /* FIFO溢出错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SOP_EOP_ERR_REG (CSR_IPSUTX_CSR_BASE + 0x28) /* SOP/EOP检查错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_REG (CSR_IPSUTX_CSR_BASE + 0x2C) /* DIF/DIX校验错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PARSE_ERR_REG (CSR_IPSUTX_CSR_BASE + 0x30) /* 报文解析检查错误中断错误寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SCHNL_CFG_ERR_REG (CSR_IPSUTX_CSR_BASE + 0x34) /* 报文通道配置错误中断寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ERR_TYPE_INT_MASK_DW3_REG (CSR_IPSUTX_CSR_BASE + 0x50) /* Error_type中断使能寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ERR_TYPE_INT_MASK_DW2_REG (CSR_IPSUTX_CSR_BASE + 0x54) /* Error_type中断使能寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ERR_TYPE_INT_MASK_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x58) /* Error_type中断使能寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ERR_TYPE_INT_MASK_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x5C) /* Error_type中断使能寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x80) /* 间接寻址控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_TIMEOUT_REG (CSR_IPSUTX_CSR_BASE + 0x84) /* 间接寻址TIMEOUT配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_0_REG (CSR_IPSUTX_CSR_BASE + 0x88) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_1_REG (CSR_IPSUTX_CSR_BASE + 0x8C) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_2_REG (CSR_IPSUTX_CSR_BASE + 0x90) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_3_REG (CSR_IPSUTX_CSR_BASE + 0x94) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_4_REG (CSR_IPSUTX_CSR_BASE + 0x98) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_5_REG (CSR_IPSUTX_CSR_BASE + 0x9C) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_6_REG (CSR_IPSUTX_CSR_BASE + 0xA0) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_7_REG (CSR_IPSUTX_CSR_BASE + 0xA4) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_8_REG (CSR_IPSUTX_CSR_BASE + 0xA8) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_9_REG (CSR_IPSUTX_CSR_BASE + 0xAC) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_10_REG (CSR_IPSUTX_CSR_BASE + 0xB0) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_11_REG (CSR_IPSUTX_CSR_BASE + 0xB4) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_12_REG (CSR_IPSUTX_CSR_BASE + 0xB8) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_13_REG (CSR_IPSUTX_CSR_BASE + 0xBC) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_14_REG (CSR_IPSUTX_CSR_BASE + 0xC0) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_INDRECT_DATA_15_REG (CSR_IPSUTX_CSR_BASE + 0xC4) /* 间接寻址数据寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CAT_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x100) /* IPSUTX通道属性配置表 */ +#define CSR_IPSUTX_CSR_IPSUTX_CAT_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x104) /* IPSUTX通道属性配置表 */ +#define CSR_IPSUTX_CSR_IPSUTX_CAT_DW2_REG (CSR_IPSUTX_CSR_BASE + 0x108) /* IPSUTX通道属性配置表 */ +#define CSR_IPSUTX_CSR_IPSUTX_CAT_DW3_REG (CSR_IPSUTX_CSR_BASE + 0x10C) /* IPSUTX通道属性配置表 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_EC_CH_REG (CSR_IPSUTX_CSR_BASE + 0x110) /* EC通道配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_VIRTIO_CH_REG (CSR_IPSUTX_CSR_BASE + 0x114) /* VirtIO-net通道配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_BANDWIDTH_CFG_REG (CSR_IPSUTX_CSR_BASE + 0x118) /* 带宽配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_MPU_TIMER_REG (CSR_IPSUTX_CSR_BASE + 0x11C) /* PPOP/MPU接口计时器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_DIFX_CH_EN_REG (CSR_IPSUTX_CSR_BASE + 0x120) /* DIFX通道配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_SOP_EOP_ST_REG (CSR_IPSUTX_CSR_BASE + 0x200) /* SOP/EOP检测状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_SOP_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x204) /* SOP_WITH_ERR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_ABORT_BF_IPSUTX_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x208) /* ABORT_BF_IPSUTX错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_SOP_SOP_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x20C) /* SOP_SOP错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MAG_SOP_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x210) /* SOP_WITH_ERR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MAG_ABORT_BF_IPSUTX_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x214) /* ABORT_BF_IPSUTX错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_MAG_SOP_SOP_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x218) /* SOP_SOP错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MAG_1STPDU_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x21C) /* 1STPDU_WITH_ERR错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_MAG_1STPDU_1STPDU_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x220) /* 1STPDU_1STPDU错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_SOP_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x224) /* SOP_WITH_ERR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_ABORT_BF_IPSUTX_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x228) /* ABORT_BF_IPSUTX错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_SOP_SOP_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x22C) /* SOP_SOP错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_SOP_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x230) /* SOP_WITH_ERR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_ABORT_BF_IPSUTX_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x234) /* ABORT_BF_IPSUTX错误计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_SOP_SOP_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x238) /* SOP_SOP错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PKT_MIN_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x23C) /* 接收超短报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PKT_MAX_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x240) /* 接收超长报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_PKT_MIN_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x244) /* 接收超短报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_PKT_MAX_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x248) /* 接收超长报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_PKT_MIN_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x24C) /* 接收超短报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_PKT_MAX_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x250) /* 接收超长报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_MPU_TIMEOUT_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x254) /* PPOP/MPU报文超时错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SOR_EOR_ST_REG (CSR_IPSUTX_CSR_BASE + 0x258) /* SOR/EOR检测状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_SOR_WITH_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x25C) /* SOR_WITH_ERR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CPI_SOR_SOR_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x260) /* SOR_SOR错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EVTAG_TPID1_REG (CSR_IPSUTX_CSR_BASE + 0x300) /* ETAG/VNTAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EVTAG_TPID0_REG (CSR_IPSUTX_CSR_BASE + 0x304) /* ETAG/VNTAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SVLAN_TPID2_REG (CSR_IPSUTX_CSR_BASE + 0x308) /* SVLAN TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SVLAN_TPID1_REG (CSR_IPSUTX_CSR_BASE + 0x30C) /* SVLAN TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SVLAN_TPID0_REG (CSR_IPSUTX_CSR_BASE + 0x310) /* SVLAN TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CVLAN_TPID2_REG (CSR_IPSUTX_CSR_BASE + 0x314) /* CVLAN-TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CVLAN_TPID1_REG (CSR_IPSUTX_CSR_BASE + 0x318) /* CVLAN-TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CVLAN_TPID0_REG (CSR_IPSUTX_CSR_BASE + 0x31C) /* CVLAN-TAG TPID配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_8023_MAX_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x320) /* 802.3最大长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_8023_JUMBO_CFG_REG (CSR_IPSUTX_CSR_BASE + 0x324) /* 802.3Jumbo帧配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2_DMAC_ETH_CHK_EN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x328) /* L2报文DMAC/ETH检测使能配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IGMPV4_DIP_CHK_EN_REG (CSR_IPSUTX_CSR_BASE + 0x32C) /* IGMPv4 DIP检测控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_SPEC_MC_REG (CSR_IPSUTX_CSR_BASE + 0x330) /* IPv6指定多播寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ROCEV2_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x334) /* RoCEV2目的UDP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_NATT_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x338) /* NATT目的UDP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_VXLAN_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x33C) /* VXLAN目的UDP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_VXLAN_GPE_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x340) /* VXLAN GPE目的UDP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_GENEVE_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x344) /* GENEVE目的UDP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_NP_REG (CSR_IPSUTX_CSR_BASE + 0x348) /* IPv4 Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_NP_REG (CSR_IPSUTX_CSR_BASE + 0x34C) /* IPv6 Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_ETHERNET_NP_REG (CSR_IPSUTX_CSR_BASE + 0x350) /* Ethernet Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_IOAM_NP_REG (CSR_IPSUTX_CSR_BASE + 0x354) /* IOAM Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_INT_NP_REG (CSR_IPSUTX_CSR_BASE + 0x358) /* INT Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_NSH_NP_REG (CSR_IPSUTX_CSR_BASE + 0x35C) /* NSH Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_AH_NP_REG (CSR_IPSUTX_CSR_BASE + 0x360) /* AH Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_ESP_NP_REG (CSR_IPSUTX_CSR_BASE + 0x364) /* ESP Next Protocol号 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCP_COCO_WITH_TS_DW0_REG \ + (CSR_IPSUTX_CSR_BASE + 0x368) /* 带时戳的TCP COCO DW0配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCP_COCO_WITHOUT_TS_DW0_REG \ + (CSR_IPSUTX_CSR_BASE + 0x36C) /* 不带时戳的TCP COCO DW0配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCP_COCO_DW0_MASK_REG (CSR_IPSUTX_CSR_BASE + 0x370) /* TCP COCO DW0掩码配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_EXT_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x374) /* IPv6扩展头配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_BGP_DPORT_REG (CSR_IPSUTX_CSR_BASE + 0x378) /* BGP目的TCP PORT号 */ +#define CSR_IPSUTX_CSR_IPSUTX_ESP_PRTL_TYPE_REG (CSR_IPSUTX_CSR_BASE + 0x37C) /* ESP Protocol Type号 */ +#define CSR_IPSUTX_CSR_IPSUTX_CRC_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x400) /* IPSUTX CRC控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SCTP_CRC_INI_REG (CSR_IPSUTX_CSR_BASE + 0x404) /* SCTP报文CRC 初始值寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ISCSI_CRC_INI_REG (CSR_IPSUTX_CSR_BASE + 0x408) /* iscsi报文头CRC 初始值寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_AGM_INI_REG (CSR_IPSUTX_CSR_BASE + 0x454) /* DIX/DIF算法初始值配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x458) /* DIF/DIX控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_FWD_PKT_LEN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x45C) /* L2NIC_FWD_DIRECT报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_PARSE_PKT_LEN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x460) /* L2NIC_PARSE_ONLY报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_GSO_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x464) /* L2NIC_GSO报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x468) /* EC报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_NON_L2NIC_FWD_PKT_LEN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x46C) /* NON-L2NIC_FWD_DIRECT报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TOE_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x470) /* TOE报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_NON_TCP_DIFX_PKT_LEN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x474) /* NON-TCP_PKT_DIFX报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IOE_DIFX_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x478) /* IOE_DIFX报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPSEC_LB_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x47C) /* IPSEC_LB报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PKT_LB_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x480) /* PKT_LB报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x484) /* UP报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_PKT_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x488) /* PPOP报文长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_PUSH_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x48C) /* UP报文的推送长度 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_PUSH_LEN_REG (CSR_IPSUTX_CSR_BASE + 0x490) /* PPOP报文的推送长度 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L2F_OTH_REG \ + (CSR_IPSUTX_CSR_BASE + 0x494) /* L2 Final和其他报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L3F_0_REG (CSR_IPSUTX_CSR_BASE + 0x498) /* L3 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L3F_1_REG (CSR_IPSUTX_CSR_BASE + 0x49C) /* L3 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L3F_2_REG (CSR_IPSUTX_CSR_BASE + 0x4A0) /* L3 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L3F_3_REG (CSR_IPSUTX_CSR_BASE + 0x4A4) /* L3 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L45F_0_REG (CSR_IPSUTX_CSR_BASE + 0x4A8) /* L4-5 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L45F_1_REG (CSR_IPSUTX_CSR_BASE + 0x4AC) /* L4-5 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L45F_2_REG (CSR_IPSUTX_CSR_BASE + 0x4B0) /* L4-5 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PUSH_LEN_L45F_3_REG (CSR_IPSUTX_CSR_BASE + 0x4B4) /* L4-5 Final报文推送长度配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_FWD_DIR_PUSH_LEN_REG \ + (CSR_IPSUTX_CSR_BASE + 0x4B8) /* L2NIC_FWD_DIRECT报文的推送长度 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_FWD_DIR_SUMOP1_REG (CSR_IPSUTX_CSR_BASE + 0x4BC) /* L2NIC_FWD_DIRECT报文的SUMOP */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_FWD_DIR_SUMOP0_REG (CSR_IPSUTX_CSR_BASE + 0x4C0) /* L2NIC_FWD_DIRECT报文的SUMOP */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_SUM_OP_REG (CSR_IPSUTX_CSR_BASE + 0x4D0) /* MPU报文SUM_OP配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_SUM_OP_REG (CSR_IPSUTX_CSR_BASE + 0x4D4) /* PPOP报文SUM_OP配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DMAC_ZERO_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x500) /* 目的MAC为0错误报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SMAC_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x504) /* 源MAC错误报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DA_SA_EQUAL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x508) /* 源目的MAC相等报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ETH_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x50C) /* ETH_LEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_DMAC_ZERO_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x510) /* 目的MAC为0错误报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_SMAC_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x514) /* 源MAC错误报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_DA_SA_EQUAL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x518) /* 源目的MAC相等报文计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_ETH_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x51C) /* ETH_LEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_VER_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x520) /* IPV4_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_IHL_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x524) /* IPV4_IHL_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_SIP_DIP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x528) /* IPV4_SIP_DIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_SIP_MC_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x52C) /* IPV4_SIP_MC_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_SIP_LB_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x530) /* IPV4_SIP_LB_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_DIP_LB_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x534) /* IPV4_DIP_LB_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_DIP_ZERO_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x538) /* IPV4_DIP_ZERO_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_DIP_RSV_ADDR_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x53C) /* IPV4_DIP_RSV_ADDR_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_UDP_LEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x540) /* IPV4_UDP_LEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV4_TLEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x544) /* IPV4_TLEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_VER_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x548) /* IPV6_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_SIP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x54C) /* IPV6_SIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_DIP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x550) /* IPV6_DIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IPV6_TLEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x554) /* IPV6_TLEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_VER_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x558) /* IPV4_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_IHL_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x55C) /* IPV4_IHL_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_SIP_DIP_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x560) /* IPV4_SIP_DIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_SIP_MC_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x564) /* IPV4_SIP_MC_ILGL计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_SIP_LB_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x568) /* IPV4_SIP_LB_ILGL计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_DIP_LB_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x56C) /* IPV4_DIP_LB_ILGL计数器 \ + */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_DIP_ZERO_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x570) /* IPV4_DIP_ZERO_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_DIP_RSV_ADDR_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x574) /* IPV4_DIP_RSV_ADDR_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_UDP_LEN_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x578) /* IPV4_UDP_LEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV4_TLEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x57C) /* IPV4_TLEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV6_VER_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x580) /* IPV6_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV6_SIP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x584) /* IPV6_SIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV6_DIP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x588) /* IPV6_DIP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_IPV6_TLEN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x58C) /* IPV6_TLEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCP_LAND_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x590) /* TCP_LAND_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLC_SNAP_ENC_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x594) /* LLC_SNAP_ENC_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_ETH_TYPE_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x598) /* ETH_TYPE_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_VXLAN_GPE_OTHER_VER_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x59C) /* VXLAN_GPE_OTHER_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_GENEVE_OTHER_VER_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5A0) /* GENEVE_OTHER_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_NSH_OTHER_VER_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5A4) /* NSH_OTHER_VER_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_NSH_LEN_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5A8) /* NSH_LEN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TUNNEL_NVGRE_CVLAN_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x5AC) /* nvGRE报文内层CVLAN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_NVGRE_CRKS_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5B0) /* NVGRE_CRKS_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_HDR_LEN_MIN_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5B4) /* PKT_HDR_LEN_MIN_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_SCTP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5B8) /* SCTP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_GSO_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x5BC) /* GSO_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_0_REG (CSR_IPSUTX_CSR_BASE + 0x600) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_1_REG (CSR_IPSUTX_CSR_BASE + 0x604) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_2_REG (CSR_IPSUTX_CSR_BASE + 0x608) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_3_REG (CSR_IPSUTX_CSR_BASE + 0x60C) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_4_REG (CSR_IPSUTX_CSR_BASE + 0x610) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_5_REG (CSR_IPSUTX_CSR_BASE + 0x614) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_6_REG (CSR_IPSUTX_CSR_BASE + 0x618) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_LLI_TYPE_7_REG (CSR_IPSUTX_CSR_BASE + 0x61C) /* LLI报文TYPE寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCAM_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x620) /* TCAM控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCAM_MBIST_DONE_REG (CSR_IPSUTX_CSR_BASE + 0x624) /* TCAM MBIST完成状态信号 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK0_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x628) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK0_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x62C) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK0_DW2_REG (CSR_IPSUTX_CSR_BASE + 0x630) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK0_DW3_REG (CSR_IPSUTX_CSR_BASE + 0x634) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK1_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x638) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK1_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x63C) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK1_DW2_REG (CSR_IPSUTX_CSR_BASE + 0x640) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_EC_RF_MASK1_DW3_REG (CSR_IPSUTX_CSR_BASE + 0x644) /* EC RF替换mask配置 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCAM_MBIST_MEM_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x648) /* TCAM MBIST MEM错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCAM_MBIST_CMP_ERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x64C) /* TCAM MBIST匹配错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_UNCRT_ERR_CTRL_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x700) /* IPSUTX致命错误控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_UNCRT_ERR_CTRL_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x704) /* IPSUTX致命错误控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAMMOD_CTRL_REG (CSR_IPSUTX_CSR_BASE + 0x708) /* IPSUTX模块RAM MOD控制寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_ERR_CHK_BYPASS_REG \ + (CSR_IPSUTX_CSR_BASE + 0x70C) /* IPSUTX模块RAM错误检查BYPASS寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_ERR_INJ_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x710) /* IPSUTX模块RAM错误注入寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_ERR_INJ_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x714) /* IPSUTX模块RAM错误注入寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_TH1_REG (CSR_IPSUTX_CSR_BASE + 0x718) /* IPSUTX FIFO门限寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_TH0_REG (CSR_IPSUTX_CSR_BASE + 0x71C) /* IPSUTX FIFO门限寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_STS5_REG (CSR_IPSUTX_CSR_BASE + 0x720) /* IPSUTX FIFO当前状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_STS4_REG (CSR_IPSUTX_CSR_BASE + 0x724) /* IPSUTX FIFO当前状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_STS3_REG (CSR_IPSUTX_CSR_BASE + 0x728) /* IPSUTX FIFO当前状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_STS2_REG (CSR_IPSUTX_CSR_BASE + 0x72C) /* IPSUTX FIFO当前状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_FIFO_STS1_REG (CSR_IPSUTX_CSR_BASE + 0x730) /* IPSUTX FIFO当前状态寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_UCERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x738) /* IPSUTX RAM不可纠错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CERR_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x73C) /* IPSUTX RAM可纠错误计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CTRL_BUS_DW0_REG (CSR_IPSUTX_CSR_BASE + 0x740) /* IPSUTX RAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CTRL_BUS_DW1_REG (CSR_IPSUTX_CSR_BASE + 0x744) /* IPSUTX RAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CTRL_BUS_DW2_REG (CSR_IPSUTX_CSR_BASE + 0x748) /* IPSUTX RAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CTRL_BUS_DW3_REG (CSR_IPSUTX_CSR_BASE + 0x74C) /* IPSUTX RAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RAM_CTRL_BUS_DW4_REG (CSR_IPSUTX_CSR_BASE + 0x750) /* IPSUTX RAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCAM_CTRL_BUS_REG (CSR_IPSUTX_CSR_BASE + 0x754) /* IPSUTX TCAM CTRL_BUS配置寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RCV_CPB_BP_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x800) /* IPSUTX接收CPB反压次数计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_MPU_BP_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x804) /* 发送至MPU的反压计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PPOP_BP_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x808) /* 发送至PPOP的反压计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_GRD_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x80C) /* DIFX_GRD_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_REF_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x810) /* DIFX_REF_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_APP_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x814) /* DIFX_APP_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_GSO_SCTP_PLOFS_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x818) /* GSO/SCTP报文PLOFS_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TCP_SD_OFS_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x81C) /* IOE/PKT_LB报文TCP_SD_OFS_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_L2NIC_PLOFS_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x820) /* L2NIC报文PLOFS_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_IOE_RSP_HDR_ILGL_CNT_REG (CSR_IPSUTX_CSR_BASE + 0x824) /* IOE报文的RSP_HDR_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PKT_LB_MD_HDR_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x828) /* PKT_LB报文和IPSEC报文的MD_HDR_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PDU_SD_OFS_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x82C) /* IOE/NTCP报文PDU_SD_OFS_ILGL计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_CRY_ERR1_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x830) /* IPSUTX入口的加密模块的错误CRYPTOTX_ERR1个数计数器，基于包统计。 */ +#define CSR_IPSUTX_CSR_IPSUTX_CRY_ERR2_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x834) /* IPSUTX入口的加密模块的错误CRYPTOTX_ERR2个数计数器，基于包统计。 */ +#define CSR_IPSUTX_CSR_IPSUTX_CRY_BD_ILGL_ILGL_CNT_REG \ + (CSR_IPSUTX_CSR_BASE + 0x838) /* IPSUTX入口的加密模块的错误CRYPTOTX_BD_ILGL个数计数器，基于包统计。 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_0_REG (CSR_IPSUTX_CSR_BASE + 0x900) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_1_REG (CSR_IPSUTX_CSR_BASE + 0x904) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_2_REG (CSR_IPSUTX_CSR_BASE + 0x908) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_3_REG (CSR_IPSUTX_CSR_BASE + 0x90C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_4_REG (CSR_IPSUTX_CSR_BASE + 0x910) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_5_REG (CSR_IPSUTX_CSR_BASE + 0x914) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_6_REG (CSR_IPSUTX_CSR_BASE + 0x918) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_7_REG (CSR_IPSUTX_CSR_BASE + 0x91C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_8_REG (CSR_IPSUTX_CSR_BASE + 0x920) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_9_REG (CSR_IPSUTX_CSR_BASE + 0x924) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_10_REG (CSR_IPSUTX_CSR_BASE + 0x928) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_11_REG (CSR_IPSUTX_CSR_BASE + 0x92C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_12_REG (CSR_IPSUTX_CSR_BASE + 0x930) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_13_REG (CSR_IPSUTX_CSR_BASE + 0x934) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_14_REG (CSR_IPSUTX_CSR_BASE + 0x938) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_15_REG (CSR_IPSUTX_CSR_BASE + 0x93C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_16_REG (CSR_IPSUTX_CSR_BASE + 0x940) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_17_REG (CSR_IPSUTX_CSR_BASE + 0x944) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_18_REG (CSR_IPSUTX_CSR_BASE + 0x948) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_19_REG (CSR_IPSUTX_CSR_BASE + 0x94C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_20_REG (CSR_IPSUTX_CSR_BASE + 0x950) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_21_REG (CSR_IPSUTX_CSR_BASE + 0x954) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_22_REG (CSR_IPSUTX_CSR_BASE + 0x958) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_RX_PKT_CNT_23_REG (CSR_IPSUTX_CSR_BASE + 0x95C) /* 通道接收报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_0_REG (CSR_IPSUTX_CSR_BASE + 0x964) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_1_REG (CSR_IPSUTX_CSR_BASE + 0x968) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_2_REG (CSR_IPSUTX_CSR_BASE + 0x96C) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_3_REG (CSR_IPSUTX_CSR_BASE + 0x970) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_4_REG (CSR_IPSUTX_CSR_BASE + 0x974) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_5_REG (CSR_IPSUTX_CSR_BASE + 0x978) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_6_REG (CSR_IPSUTX_CSR_BASE + 0x97C) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_7_REG (CSR_IPSUTX_CSR_BASE + 0x980) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_8_REG (CSR_IPSUTX_CSR_BASE + 0x984) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_9_REG (CSR_IPSUTX_CSR_BASE + 0x988) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_10_REG (CSR_IPSUTX_CSR_BASE + 0x98C) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_11_REG (CSR_IPSUTX_CSR_BASE + 0x990) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_12_REG (CSR_IPSUTX_CSR_BASE + 0x994) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_13_REG (CSR_IPSUTX_CSR_BASE + 0x998) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_14_REG (CSR_IPSUTX_CSR_BASE + 0x99C) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_15_REG (CSR_IPSUTX_CSR_BASE + 0x9A0) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_16_REG (CSR_IPSUTX_CSR_BASE + 0x9A4) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_17_REG (CSR_IPSUTX_CSR_BASE + 0x9A8) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_18_REG (CSR_IPSUTX_CSR_BASE + 0x9AC) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_19_REG (CSR_IPSUTX_CSR_BASE + 0x9B0) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_20_REG (CSR_IPSUTX_CSR_BASE + 0x9B4) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_21_REG (CSR_IPSUTX_CSR_BASE + 0x9B8) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_22_REG (CSR_IPSUTX_CSR_BASE + 0x9BC) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_TX_PKT_CNT_23_REG (CSR_IPSUTX_CSR_BASE + 0x9C0) /* 通道发送到CPB的报文数量计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_0_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9C8) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_1_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9CC) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_2_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9D0) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_3_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9D4) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_4_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9D8) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_5_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9DC) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_6_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9E0) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_7_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9E4) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_8_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9E8) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_9_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9EC) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_10_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9F0) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_11_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9F4) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_12_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9F8) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_13_REG \ + (CSR_IPSUTX_CSR_BASE + 0x9FC) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_14_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA00) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_PKT_CNT_15_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA04) /* 通道发送到CPB的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_0_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA08) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_1_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA0C) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_2_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA10) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_3_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA14) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_4_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA18) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_5_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA1C) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_6_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA20) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_7_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA24) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_8_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA28) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_9_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA2C) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_10_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA30) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_11_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA34) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_12_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA38) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_13_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA3C) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_14_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA40) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_EDIT_TYPE_CRY_PKT_CNT_15_REG \ + (CSR_IPSUTX_CSR_BASE + 0xA44) /* IPSUTX接收到的从CRYPTOTX来的报文EDIT_TYPE计数器 */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_0_REG (CSR_IPSUTX_CSR_BASE + 0xB00) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_1_REG (CSR_IPSUTX_CSR_BASE + 0xB04) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_2_REG (CSR_IPSUTX_CSR_BASE + 0xB08) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_3_REG (CSR_IPSUTX_CSR_BASE + 0xB0C) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_4_REG (CSR_IPSUTX_CSR_BASE + 0xB10) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_5_REG (CSR_IPSUTX_CSR_BASE + 0xB14) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_6_REG (CSR_IPSUTX_CSR_BASE + 0xB18) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_EXT_7_REG (CSR_IPSUTX_CSR_BASE + 0xB1C) /* 隧道外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_INT_0_REG (CSR_IPSUTX_CSR_BASE + 0xB20) /* 隧道内层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_INT_1_REG (CSR_IPSUTX_CSR_BASE + 0xB24) /* 隧道内层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_INT_2_REG (CSR_IPSUTX_CSR_BASE + 0xB28) /* 隧道内层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_PATN_ID_INT_3_REG (CSR_IPSUTX_CSR_BASE + 0xB2C) /* 隧道内层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_ERR_PATN_ID_REG (CSR_IPSUTX_CSR_BASE + 0xB30) /* 报文解析出错时的外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_VIRTIO_PATN_ID_REG \ + (CSR_IPSUTX_CSR_BASE + 0xB34) /* 报文存在VirtIO-net时的外层PATTERN ID */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_DFX_CLR_REG (CSR_IPSUTX_CSR_BASE + 0xC00) /* IPSUTX DIF/DIX错误DFX清除寄存器 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_INFO_DW0_REG (CSR_IPSUTX_CSR_BASE + 0xC04) /* IPSUTX DIF/DIX错误信息 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_INFO_DW1_REG (CSR_IPSUTX_CSR_BASE + 0xC08) /* IPSUTX DIF/DIX错误信息 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_INFO_DW2_REG (CSR_IPSUTX_CSR_BASE + 0xC0C) /* IPSUTX DIF/DIX错误信息 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_INFO_DW3_REG (CSR_IPSUTX_CSR_BASE + 0xC10) /* IPSUTX DIF/DIX错误信息 */ +#define CSR_IPSUTX_CSR_IPSUTX_DIFX_ERR_INFO_DW4_REG (CSR_IPSUTX_CSR_BASE + 0xC14) /* IPSUTX DIF/DIX错误信息 */ + +#endif // IPSUTX_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_c_union_define.h new file mode 100644 index 000000000..1a9b59da5 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_c_union_define.h @@ -0,0 +1,741 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : lcam_c_union_define.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : xxx +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/05/14 16:55:24 Create file +// ****************************************************************************** + +#ifndef LCAM_C_UNION_DEFINE_H +#define LCAM_C_UNION_DEFINE_H + +/* Define the union csr_lcam_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_version_u; + +/* Define the union csr_lcam_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_indrect_addr : 5; /* [4:0] */ + u32 rsv_0 : 19; /* [23:5] */ + u32 lcam_indrect_tab : 1; /* [24] */ + u32 rsv_1 : 3; /* [27:25] */ + u32 lcam_indrect_status : 2; /* [29:28] */ + u32 lcam_indrect_mode : 1; /* [30] */ + u32 lcam_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_indrect_ctrl_u; + +/* Define the union csr_lcam_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_indrect_timeout_u; + +/* Define the union csr_lcam_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_indrect_data_0_u; + +/* Define the union csr_lcam_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_indrect_data_1_u; + +/* Define the union csr_lcam_indrect_data_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_indrect_data_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_indrect_data_2_u; + +/* Define the union csr_lcam_scan_period_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_scan_period : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_scan_period_u; + +/* Define the union csr_lcam_scan_period_gra_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_scan_period_gra : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_scan_period_gra_u; + +/* Define the union csr_lcam_scan_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_scan_en : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_scan_en_u; + +/* Define the union csr_lcam_common_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_block_gating : 5; /* [4:0] */ + u32 rp_lcam_tcam_init_en : 1; /* [5] */ + u32 rp_lcam_ag_init_en : 1; /* [6] */ + u32 rp_check_en : 1; /* [7] */ + u32 sp_ram_tmod : 7; /* [14:8] */ + u32 sp_ret1n : 1; /* [15] */ + u32 rp_lcam_cnt_src_sel : 1; /* [16] */ + u32 rp_lcam_cnt_en : 1; /* [17] */ + u32 rp_lcam_resp_e0_en : 1; /* [18] */ + u32 rp_tcam_search_low_power_en : 1; /* [19] */ + u32 rp_rx_async_fifo_wr_bp_thrd : 4; /* [23:20] */ + u32 rp_tx_async_fifo_wr_bp_thrd : 4; /* [27:24] */ + u32 rsv_2 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_common_cfg_u; + +/* Define the union csr_lcam_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_uncrt_err_clr : 1; /* [0] */ + u32 rp_lcam_api_drop_err_mask : 1; /* [1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_uncrt_err_u; + +/* Define the union csr_lcam_wrr_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_tcam_wrr_weight : 16; /* [15:0] */ + u32 rsv_3 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_wrr_weight_u; + +/* Define the union csr_lcam_ring_rx_rqst_correct_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_ring_rx_rqst_correct_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_rx_rqst_correct_cnt_u; + +/* Define the union csr_lcam_ring_rx_rqst_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_ring_rx_rqst_err_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_rx_rqst_err_cnt_u; + +/* Define the union csr_lcam_ring_rx_rqst_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_ring_rx_rqst_drop_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_rx_rqst_drop_cnt_u; + +/* Define the union csr_lcam_ring_tx_rqst_correct_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_ring_tx_rqst_correct_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_tx_rqst_correct_cnt_u; + +/* Define the union csr_lcam_ring_tx_rqst_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_ring_tx_rqst_err_cnt : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_tx_rqst_err_cnt_u; + +/* Define the union csr_lcam_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_4 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_5 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_int_vector_u; + +/* Define the union csr_lcam_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 7; /* [6:0] */ + u32 rsv_6 : 9; /* [15:7] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_int_u; + +/* Define the union csr_lcam_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 7; /* [6:0] */ + u32 rsv_7 : 9; /* [15:7] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_int_mask_u; + +/* Define the union csr_lcam_ring_itf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_drop_err : 1; /* [0] */ + u32 api_drop_merr : 1; /* [1] */ + u32 miss_sop_err : 1; /* [2] */ + u32 miss_sop_merr : 1; /* [3] */ + u32 miss_eop_err : 1; /* [4] */ + u32 miss_eop_merr : 1; /* [5] */ + u32 illegal_op_id_err : 1; /* [6] */ + u32 illegal_op_id_merr : 1; /* [7] */ + u32 api_overlong_err : 1; /* [8] */ + u32 api_overlong_merr : 1; /* [9] */ + u32 api_tooshort_err : 1; /* [10] */ + u32 api_tooshort_merr : 1; /* [11] */ + u32 req_asyn_overflow_err : 1; /* [12] */ + u32 req_asyn_overflow_merr : 1; /* [13] */ + u32 rsp_asyn_overflow_err : 1; /* [14] */ + u32 rsp_asyn_overflow_merr : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_itf_err_u; + +/* Define the union csr_lcam_ring_itf_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_drop_err_mask : 1; /* [0] */ + u32 miss_sop_err_mask : 1; /* [1] */ + u32 miss_eop_err_mask : 1; /* [2] */ + u32 illegal_op_id_err_mask : 1; /* [3] */ + u32 api_overlong_err_mask : 1; /* [4] */ + u32 api_tooshort_err_mask : 1; /* [5] */ + u32 req_asyn_overflow_err_mask : 1; /* [6] */ + u32 rsp_asyn_overflow_err_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ring_itf_err_mask_u; + +/* Define the union csr_lcam_ad_ecc_one_bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 17; /* [18:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ad_ecc_one_bit_err_u; + +/* Define the union csr_lcam_ad_ecc_two_bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 17; /* [18:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ad_ecc_two_bit_err_u; + +/* Define the union csr_lcam_tcam_ecc_one_bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 22; /* [23:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_tcam_ecc_one_bit_err_u; + +/* Define the union csr_lcam_tcam_ecc_two_bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 22; /* [23:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_tcam_ecc_two_bit_err_u; + +/* Define the union csr_lcam_cmd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ag_addr_outof_range_err : 1; /* [0] */ + u32 ag_addr_outof_range_merr : 1; /* [1] */ + u32 tcam_op_addr_cmd_err : 1; /* [2] */ + u32 tcam_op_addr_cmd_merr : 1; /* [3] */ + u32 move_new_eq_old_err : 1; /* [4] */ + u32 move_new_eq_old_merr : 1; /* [5] */ + u32 move_len_outof_err : 1; /* [6] */ + u32 move_len_outof_merr : 1; /* [7] */ + u32 move_old_outof_err : 1; /* [8] */ + u32 move_old_outof_merr : 1; /* [9] */ + u32 move_new_outof_err : 1; /* [10] */ + u32 move_new_outof_merr : 1; /* [11] */ + u32 move_len_zero_err : 1; /* [12] */ + u32 move_len_zero_merr : 1; /* [13] */ + u32 target_blk_gating_err : 1; /* [14] */ + u32 target_blk_gating_merr : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_cmd_err_u; + +/* Define the union csr_lcam_cmd_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ag_addr_outof_range_err_mask : 1; /* [0] */ + u32 tcam_op_addr_cmd_err_mask : 1; /* [1] */ + u32 move_new_eq_old_err_mask : 1; /* [2] */ + u32 move_len_outof_err_mask : 1; /* [3] */ + u32 move_old_outof_err_mask : 1; /* [4] */ + u32 move_new_outof_err_mask : 1; /* [5] */ + u32 move_len_zero_err_mask : 1; /* [6] */ + u32 target_blk_gating_err_mask : 1; /* [7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_cmd_err_mask_u; + +/* Define the union csr_lcam_init_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_tcam_init_done : 1; /* [0] */ + u32 lcam_ag_init_done : 1; /* [1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_init_status_u; + +/* Define the union csr_lcam_ecc_err_inj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_lcam_ad_one_bit_err_inj_req : 1; /* [0] */ + u32 rp_lcam_ad_two_bit_err_inj_req : 1; /* [1] */ + u32 rp_lcam_tcam_one_bit_err_inj_req : 1; /* [2] */ + u32 rp_lcam_tcam_two_bit_err_inj_req : 1; /* [3] */ + u32 rsv_8 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_ecc_err_inj_u; + +/* Define the union csr_lcam_src_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_chk_err : 1; /* [0] */ + u32 src_chk_merr : 1; /* [1] */ + u32 sticky : 5; /* [6:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_src_err_u; + +/* Define the union csr_lcam_src_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_err_mask : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_src_err_mask_u; + +/* Define the union csr_lcam_src_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_cfg : 9; /* [8:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_src_cfg_u; + +/* Define the union csr_lcam_src_cfg_node_id0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 node_id_tile0 : 5; /* [4:0] */ + u32 node_id_tile1 : 5; /* [9:5] */ + u32 node_id_tile2 : 5; /* [14:10] */ + u32 node_id_tile3 : 5; /* [19:15] */ + u32 node_id_tile4 : 5; /* [24:20] */ + u32 node_id_tile5 : 5; /* [29:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_src_cfg_node_id0_u; + +/* Define the union csr_lcam_src_cfg_node_id1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 node_id_tile6 : 5; /* [4:0] */ + u32 node_id_tile7 : 5; /* [9:5] */ + u32 node_id_mpu : 5; /* [14:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_src_cfg_node_id1_u; + +/* Define the union csr_lcam_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_mem_ctrl_bus_cfg0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_lcam_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_mem_ctrl_bus_cfg1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_lcam_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_mem_ctrl_bus_cfg2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_lcam_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_mem_ctrl_bus_cfg3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_lcam_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_mem_ctrl_bus_cfg4 : 6; /* [5:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_lcam_tcam_ctrl_bus_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lcam_tcam_ctrl_bus_cfg : 10; /* [9:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_lcam_tcam_ctrl_bus_cfg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_lcam_version_u lcam_version; /* 0 */ + volatile csr_lcam_indrect_ctrl_u lcam_indrect_ctrl; /* 4 */ + volatile csr_lcam_indrect_timeout_u lcam_indrect_timeout; /* 8 */ + volatile csr_lcam_indrect_data_0_u lcam_indrect_data_0; /* C */ + volatile csr_lcam_indrect_data_1_u lcam_indrect_data_1; /* 10 */ + volatile csr_lcam_indrect_data_2_u lcam_indrect_data_2; /* 14 */ + volatile csr_lcam_scan_period_u lcam_scan_period; /* 18 */ + volatile csr_lcam_scan_period_gra_u lcam_scan_period_gra; /* 1C */ + volatile csr_lcam_scan_en_u lcam_scan_en; /* 20 */ + volatile csr_lcam_common_cfg_u lcam_common_cfg; /* 24 */ + volatile csr_lcam_uncrt_err_u lcam_uncrt_err; /* 28 */ + volatile csr_lcam_wrr_weight_u lcam_wrr_weight; /* 2C */ + volatile csr_lcam_ring_rx_rqst_correct_cnt_u lcam_ring_rx_rqst_correct_cnt; /* 30 */ + volatile csr_lcam_ring_rx_rqst_err_cnt_u lcam_ring_rx_rqst_err_cnt; /* 34 */ + volatile csr_lcam_ring_rx_rqst_drop_cnt_u lcam_ring_rx_rqst_drop_cnt; /* 38 */ + volatile csr_lcam_ring_tx_rqst_correct_cnt_u lcam_ring_tx_rqst_correct_cnt; /* 3C */ + volatile csr_lcam_ring_tx_rqst_err_cnt_u lcam_ring_tx_rqst_err_cnt; /* 40 */ + volatile csr_lcam_int_vector_u lcam_int_vector; /* 44 */ + volatile csr_lcam_int_u lcam_int; /* 48 */ + volatile csr_lcam_int_mask_u lcam_int_mask; /* 4C */ + volatile csr_lcam_ring_itf_err_u lcam_ring_itf_err; /* 50 */ + volatile csr_lcam_ring_itf_err_mask_u lcam_ring_itf_err_mask; /* 54 */ + volatile csr_lcam_ad_ecc_one_bit_err_u lcam_ad_ecc_one_bit_err; /* 58 */ + volatile csr_lcam_ad_ecc_two_bit_err_u lcam_ad_ecc_two_bit_err; /* 5C */ + volatile csr_lcam_tcam_ecc_one_bit_err_u lcam_tcam_ecc_one_bit_err; /* 60 */ + volatile csr_lcam_tcam_ecc_two_bit_err_u lcam_tcam_ecc_two_bit_err; /* 64 */ + volatile csr_lcam_cmd_err_u lcam_cmd_err; /* 68 */ + volatile csr_lcam_cmd_err_mask_u lcam_cmd_err_mask; /* 6C */ + volatile csr_lcam_init_status_u lcam_init_status; /* 70 */ + volatile csr_lcam_ecc_err_inj_u lcam_ecc_err_inj; /* 74 */ + volatile csr_lcam_src_err_u lcam_src_err; /* 80 */ + volatile csr_lcam_src_err_mask_u lcam_src_err_mask; /* 84 */ + volatile csr_lcam_src_cfg_u lcam_src_cfg; /* 88 */ + volatile csr_lcam_src_cfg_node_id0_u lcam_src_cfg_node_id0; /* 8C */ + volatile csr_lcam_src_cfg_node_id1_u lcam_src_cfg_node_id1; /* 90 */ + volatile csr_lcam_mem_ctrl_bus_cfg0_u lcam_mem_ctrl_bus_cfg0; /* 94 */ + volatile csr_lcam_mem_ctrl_bus_cfg1_u lcam_mem_ctrl_bus_cfg1; /* 98 */ + volatile csr_lcam_mem_ctrl_bus_cfg2_u lcam_mem_ctrl_bus_cfg2; /* 9C */ + volatile csr_lcam_mem_ctrl_bus_cfg3_u lcam_mem_ctrl_bus_cfg3; /* A0 */ + volatile csr_lcam_mem_ctrl_bus_cfg4_u lcam_mem_ctrl_bus_cfg4; /* A4 */ + volatile csr_lcam_tcam_ctrl_bus_cfg_u lcam_tcam_ctrl_bus_cfg; /* A8 */ +} S_lcam_csr_REGS_TYPE; + +/* Declare the struct pointor of the module lcam_csr */ +extern volatile S_lcam_csr_REGS_TYPE *goplcam_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetLCAM_VERSION_lcam_version(unsigned int ulcam_version); +int iSetLCAM_INDRECT_CTRL_lcam_indrect_addr(unsigned int ulcam_indrect_addr); +int iSetLCAM_INDRECT_CTRL_lcam_indrect_tab(unsigned int ulcam_indrect_tab); +int iSetLCAM_INDRECT_CTRL_lcam_indrect_status(unsigned int ulcam_indrect_status); +int iSetLCAM_INDRECT_CTRL_lcam_indrect_mode(unsigned int ulcam_indrect_mode); +int iSetLCAM_INDRECT_CTRL_lcam_indrect_vld(unsigned int ulcam_indrect_vld); +int iSetLCAM_INDRECT_TIMEOUT_lcam_indrect_timeout(unsigned int ulcam_indrect_timeout); +int iSetLCAM_INDRECT_DATA_0_lcam_indrect_data_0(unsigned int ulcam_indrect_data_0); +int iSetLCAM_INDRECT_DATA_1_lcam_indrect_data_1(unsigned int ulcam_indrect_data_1); +int iSetLCAM_INDRECT_DATA_2_lcam_indrect_data_2(unsigned int ulcam_indrect_data_2); +int iSetLCAM_SCAN_PERIOD_rp_lcam_scan_period(unsigned int urp_lcam_scan_period); +int iSetLCAM_SCAN_PERIOD_GRA_rp_lcam_scan_period_gra(unsigned int urp_lcam_scan_period_gra); +int iSetLCAM_SCAN_EN_rp_lcam_scan_en(unsigned int urp_lcam_scan_en); +int iSetLCAM_COMMON_CFG_rp_block_gating(unsigned int urp_block_gating); +int iSetLCAM_COMMON_CFG_rp_lcam_tcam_init_en(unsigned int urp_lcam_tcam_init_en); +int iSetLCAM_COMMON_CFG_rp_lcam_ag_init_en(unsigned int urp_lcam_ag_init_en); +int iSetLCAM_COMMON_CFG_rp_check_en(unsigned int urp_check_en); +int iSetLCAM_COMMON_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetLCAM_COMMON_CFG_sp_ret1n(unsigned int usp_ret1n); +int iSetLCAM_COMMON_CFG_rp_lcam_cnt_src_sel(unsigned int urp_lcam_cnt_src_sel); +int iSetLCAM_COMMON_CFG_rp_lcam_cnt_en(unsigned int urp_lcam_cnt_en); +int iSetLCAM_COMMON_CFG_rp_lcam_resp_e0_en(unsigned int urp_lcam_resp_e0_en); +int iSetLCAM_COMMON_CFG_rp_tcam_search_low_power_en(unsigned int urp_tcam_search_low_power_en); +int iSetLCAM_COMMON_CFG_rp_rx_async_fifo_wr_bp_thrd(unsigned int urp_rx_async_fifo_wr_bp_thrd); +int iSetLCAM_COMMON_CFG_rp_tx_async_fifo_wr_bp_thrd(unsigned int urp_tx_async_fifo_wr_bp_thrd); +int iSetLCAM_UNCRT_ERR_rp_lcam_uncrt_err_clr(unsigned int urp_lcam_uncrt_err_clr); +int iSetLCAM_UNCRT_ERR_rp_lcam_api_drop_err_mask(unsigned int urp_lcam_api_drop_err_mask); +int iSetLCAM_WRR_WEIGHT_rp_lcam_tcam_wrr_weight(unsigned int urp_lcam_tcam_wrr_weight); +int iSetLCAM_RING_RX_RQST_CORRECT_CNT_lcam_ring_rx_rqst_correct_cnt(unsigned int ulcam_ring_rx_rqst_correct_cnt); +int iSetLCAM_RING_RX_RQST_ERR_CNT_lcam_ring_rx_rqst_err_cnt(unsigned int ulcam_ring_rx_rqst_err_cnt); +int iSetLCAM_RING_RX_RQST_DROP_CNT_lcam_ring_rx_rqst_drop_cnt(unsigned int ulcam_ring_rx_rqst_drop_cnt); +int iSetLCAM_RING_TX_RQST_CORRECT_CNT_lcam_ring_tx_rqst_correct_cnt(unsigned int ulcam_ring_tx_rqst_correct_cnt); +int iSetLCAM_RING_TX_RQST_ERR_CNT_lcam_ring_tx_rqst_err_cnt(unsigned int ulcam_ring_tx_rqst_err_cnt); +int iSetLCAM_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetLCAM_INT_VECTOR_enable(unsigned int uenable); +int iSetLCAM_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetLCAM_INT_int_data(unsigned int uint_data); +int iSetLCAM_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetLCAM_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetLCAM_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetLCAM_RING_ITF_ERR_api_drop_err(unsigned int uapi_drop_err); +int iSetLCAM_RING_ITF_ERR_api_drop_merr(unsigned int uapi_drop_merr); +int iSetLCAM_RING_ITF_ERR_miss_sop_err(unsigned int umiss_sop_err); +int iSetLCAM_RING_ITF_ERR_miss_sop_merr(unsigned int umiss_sop_merr); +int iSetLCAM_RING_ITF_ERR_miss_eop_err(unsigned int umiss_eop_err); +int iSetLCAM_RING_ITF_ERR_miss_eop_merr(unsigned int umiss_eop_merr); +int iSetLCAM_RING_ITF_ERR_illegal_op_id_err(unsigned int uillegal_op_id_err); +int iSetLCAM_RING_ITF_ERR_illegal_op_id_merr(unsigned int uillegal_op_id_merr); +int iSetLCAM_RING_ITF_ERR_api_overlong_err(unsigned int uapi_overlong_err); +int iSetLCAM_RING_ITF_ERR_api_overlong_merr(unsigned int uapi_overlong_merr); +int iSetLCAM_RING_ITF_ERR_api_tooshort_err(unsigned int uapi_tooshort_err); +int iSetLCAM_RING_ITF_ERR_api_tooshort_merr(unsigned int uapi_tooshort_merr); +int iSetLCAM_RING_ITF_ERR_req_asyn_overflow_err(unsigned int ureq_asyn_overflow_err); +int iSetLCAM_RING_ITF_ERR_req_asyn_overflow_merr(unsigned int ureq_asyn_overflow_merr); +int iSetLCAM_RING_ITF_ERR_rsp_asyn_overflow_err(unsigned int ursp_asyn_overflow_err); +int iSetLCAM_RING_ITF_ERR_rsp_asyn_overflow_merr(unsigned int ursp_asyn_overflow_merr); +int iSetLCAM_RING_ITF_ERR_MASK_api_drop_err_mask(unsigned int uapi_drop_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_miss_sop_err_mask(unsigned int umiss_sop_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_miss_eop_err_mask(unsigned int umiss_eop_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_illegal_op_id_err_mask(unsigned int uillegal_op_id_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_api_overlong_err_mask(unsigned int uapi_overlong_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_api_tooshort_err_mask(unsigned int uapi_tooshort_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_req_asyn_overflow_err_mask(unsigned int ureq_asyn_overflow_err_mask); +int iSetLCAM_RING_ITF_ERR_MASK_rsp_asyn_overflow_err_mask(unsigned int ursp_asyn_overflow_err_mask); +int iSetLCAM_AD_ECC_ONE_BIT_ERR_error_bit(unsigned int uerror_bit); +int iSetLCAM_AD_ECC_ONE_BIT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetLCAM_AD_ECC_ONE_BIT_ERR_sticky(unsigned int usticky); +int iSetLCAM_AD_ECC_TWO_BIT_ERR_error_bit(unsigned int uerror_bit); +int iSetLCAM_AD_ECC_TWO_BIT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetLCAM_AD_ECC_TWO_BIT_ERR_sticky(unsigned int usticky); +int iSetLCAM_TCAM_ECC_ONE_BIT_ERR_error_bit(unsigned int uerror_bit); +int iSetLCAM_TCAM_ECC_ONE_BIT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetLCAM_TCAM_ECC_ONE_BIT_ERR_sticky(unsigned int usticky); +int iSetLCAM_TCAM_ECC_TWO_BIT_ERR_error_bit(unsigned int uerror_bit); +int iSetLCAM_TCAM_ECC_TWO_BIT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetLCAM_TCAM_ECC_TWO_BIT_ERR_sticky(unsigned int usticky); +int iSetLCAM_CMD_ERR_ag_addr_outof_range_err(unsigned int uag_addr_outof_range_err); +int iSetLCAM_CMD_ERR_ag_addr_outof_range_merr(unsigned int uag_addr_outof_range_merr); +int iSetLCAM_CMD_ERR_tcam_op_addr_cmd_err(unsigned int utcam_op_addr_cmd_err); +int iSetLCAM_CMD_ERR_tcam_op_addr_cmd_merr(unsigned int utcam_op_addr_cmd_merr); +int iSetLCAM_CMD_ERR_move_new_eq_old_err(unsigned int umove_new_eq_old_err); +int iSetLCAM_CMD_ERR_move_new_eq_old_merr(unsigned int umove_new_eq_old_merr); +int iSetLCAM_CMD_ERR_move_len_outof_err(unsigned int umove_len_outof_err); +int iSetLCAM_CMD_ERR_move_len_outof_merr(unsigned int umove_len_outof_merr); +int iSetLCAM_CMD_ERR_move_old_outof_err(unsigned int umove_old_outof_err); +int iSetLCAM_CMD_ERR_move_old_outof_merr(unsigned int umove_old_outof_merr); +int iSetLCAM_CMD_ERR_move_new_outof_err(unsigned int umove_new_outof_err); +int iSetLCAM_CMD_ERR_move_new_outof_merr(unsigned int umove_new_outof_merr); +int iSetLCAM_CMD_ERR_move_len_zero_err(unsigned int umove_len_zero_err); +int iSetLCAM_CMD_ERR_move_len_zero_merr(unsigned int umove_len_zero_merr); +int iSetLCAM_CMD_ERR_target_blk_gating_err(unsigned int utarget_blk_gating_err); +int iSetLCAM_CMD_ERR_target_blk_gating_merr(unsigned int utarget_blk_gating_merr); +int iSetLCAM_CMD_ERR_MASK_ag_addr_outof_range_err_mask(unsigned int uag_addr_outof_range_err_mask); +int iSetLCAM_CMD_ERR_MASK_tcam_op_addr_cmd_err_mask(unsigned int utcam_op_addr_cmd_err_mask); +int iSetLCAM_CMD_ERR_MASK_move_new_eq_old_err_mask(unsigned int umove_new_eq_old_err_mask); +int iSetLCAM_CMD_ERR_MASK_move_len_outof_err_mask(unsigned int umove_len_outof_err_mask); +int iSetLCAM_CMD_ERR_MASK_move_old_outof_err_mask(unsigned int umove_old_outof_err_mask); +int iSetLCAM_CMD_ERR_MASK_move_new_outof_err_mask(unsigned int umove_new_outof_err_mask); +int iSetLCAM_CMD_ERR_MASK_move_len_zero_err_mask(unsigned int umove_len_zero_err_mask); +int iSetLCAM_CMD_ERR_MASK_target_blk_gating_err_mask(unsigned int utarget_blk_gating_err_mask); +int iSetLCAM_INIT_STATUS_lcam_tcam_init_done(unsigned int ulcam_tcam_init_done); +int iSetLCAM_INIT_STATUS_lcam_ag_init_done(unsigned int ulcam_ag_init_done); +int iSetLCAM_ECC_ERR_INJ_rp_lcam_ad_one_bit_err_inj_req(unsigned int urp_lcam_ad_one_bit_err_inj_req); +int iSetLCAM_ECC_ERR_INJ_rp_lcam_ad_two_bit_err_inj_req(unsigned int urp_lcam_ad_two_bit_err_inj_req); +int iSetLCAM_ECC_ERR_INJ_rp_lcam_tcam_one_bit_err_inj_req(unsigned int urp_lcam_tcam_one_bit_err_inj_req); +int iSetLCAM_ECC_ERR_INJ_rp_lcam_tcam_two_bit_err_inj_req(unsigned int urp_lcam_tcam_two_bit_err_inj_req); +int iSetLCAM_SRC_ERR_src_chk_err(unsigned int usrc_chk_err); +int iSetLCAM_SRC_ERR_src_chk_merr(unsigned int usrc_chk_merr); +int iSetLCAM_SRC_ERR_sticky(unsigned int usticky); +int iSetLCAM_SRC_ERR_MASK_src_err_mask(unsigned int usrc_err_mask); +int iSetLCAM_SRC_CFG_src_cfg(unsigned int usrc_cfg); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile0(unsigned int unode_id_tile0); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile1(unsigned int unode_id_tile1); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile2(unsigned int unode_id_tile2); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile3(unsigned int unode_id_tile3); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile4(unsigned int unode_id_tile4); +int iSetLCAM_SRC_CFG_NODE_ID0_node_id_tile5(unsigned int unode_id_tile5); +int iSetLCAM_SRC_CFG_NODE_ID1_node_id_tile6(unsigned int unode_id_tile6); +int iSetLCAM_SRC_CFG_NODE_ID1_node_id_tile7(unsigned int unode_id_tile7); +int iSetLCAM_SRC_CFG_NODE_ID1_node_id_mpu(unsigned int unode_id_mpu); +int iSetLCAM_MEM_CTRL_BUS_CFG0_lcam_mem_ctrl_bus_cfg0(unsigned int ulcam_mem_ctrl_bus_cfg0); +int iSetLCAM_MEM_CTRL_BUS_CFG1_lcam_mem_ctrl_bus_cfg1(unsigned int ulcam_mem_ctrl_bus_cfg1); +int iSetLCAM_MEM_CTRL_BUS_CFG2_lcam_mem_ctrl_bus_cfg2(unsigned int ulcam_mem_ctrl_bus_cfg2); +int iSetLCAM_MEM_CTRL_BUS_CFG3_lcam_mem_ctrl_bus_cfg3(unsigned int ulcam_mem_ctrl_bus_cfg3); +int iSetLCAM_MEM_CTRL_BUS_CFG4_lcam_mem_ctrl_bus_cfg4(unsigned int ulcam_mem_ctrl_bus_cfg4); +int iSetLCAM_TCAM_CTRL_BUS_CFG_lcam_tcam_ctrl_bus_cfg(unsigned int ulcam_tcam_ctrl_bus_cfg); + + +#endif // LCAM_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_reg_offset.h new file mode 100644 index 000000000..d886511cd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/lcam_reg_offset.h @@ -0,0 +1,72 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : lcam_reg_offset.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : xxx +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/05/14 16:55:24 Create file +// ****************************************************************************** + +#ifndef LCAM_REG_OFFSET_H +#define LCAM_REG_OFFSET_H + +/* lcam_csr Base address of Module's Register */ +#define CSR_LCAM_CSR_BASE (0x0) + +/* **************************************************************************** */ +/* lcam_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_LCAM_CSR_LCAM_VERSION_REG (CSR_LCAM_CSR_BASE + 0x0) /* Version Log register */ +#define CSR_LCAM_CSR_LCAM_INDRECT_CTRL_REG (CSR_LCAM_CSR_BASE + 0x4) /* LCAM间接寻址控制寄存器 */ +#define CSR_LCAM_CSR_LCAM_INDRECT_TIMEOUT_REG (CSR_LCAM_CSR_BASE + 0x8) /* LCAM间接寻址TIMEOUT配置寄存器 */ +#define CSR_LCAM_CSR_LCAM_INDRECT_DATA_0_REG (CSR_LCAM_CSR_BASE + 0xC) /* LCAM间接寻址数据寄存器 */ +#define CSR_LCAM_CSR_LCAM_INDRECT_DATA_1_REG (CSR_LCAM_CSR_BASE + 0x10) /* LCAM间接寻址数据寄存器 */ +#define CSR_LCAM_CSR_LCAM_INDRECT_DATA_2_REG (CSR_LCAM_CSR_BASE + 0x14) /* LCAM间接寻址数据寄存器 */ +#define CSR_LCAM_CSR_LCAM_SCAN_PERIOD_REG (CSR_LCAM_CSR_BASE + 0x18) /* LCAM背景周期 */ +#define CSR_LCAM_CSR_LCAM_SCAN_PERIOD_GRA_REG (CSR_LCAM_CSR_BASE + 0x1C) /* LCAM背景周期计数粒度 */ +#define CSR_LCAM_CSR_LCAM_SCAN_EN_REG (CSR_LCAM_CSR_BASE + 0x20) /* LCAM背景周期使能 */ +#define CSR_LCAM_CSR_LCAM_COMMON_CFG_REG (CSR_LCAM_CSR_BASE + 0x24) /* LCAM 其它的配置 */ +#define CSR_LCAM_CSR_LCAM_UNCRT_ERR_REG \ + (CSR_LCAM_CSR_BASE + 0x28) /* LCAM 致命中断标记配置入口发生丢弃API错误时，中断信号都会输出到顶层 */ +#define CSR_LCAM_CSR_LCAM_WRR_WEIGHT_REG (CSR_LCAM_CSR_BASE + 0x2C) /* LCAM TCAM 仲裁器权重 */ +#define CSR_LCAM_CSR_LCAM_RING_RX_RQST_CORRECT_CNT_REG \ + (CSR_LCAM_CSR_BASE + 0x30) /* The number of correct api /flit received in RING interfaces */ +#define CSR_LCAM_CSR_LCAM_RING_RX_RQST_ERR_CNT_REG \ + (CSR_LCAM_CSR_BASE + 0x34) /* The number of error api /flit received in RING interfaces */ +#define CSR_LCAM_CSR_LCAM_RING_RX_RQST_DROP_CNT_REG \ + (CSR_LCAM_CSR_BASE + 0x38) /* The number of dropped api/flit received in RING interfaces */ +#define CSR_LCAM_CSR_LCAM_RING_TX_RQST_CORRECT_CNT_REG \ + (CSR_LCAM_CSR_BASE + 0x3C) /* The number of correct api/flit send to RING interfaces */ +#define CSR_LCAM_CSR_LCAM_RING_TX_RQST_ERR_CNT_REG \ + (CSR_LCAM_CSR_BASE + 0x40) /* The number of error api/flit send to RING interfaces */ +#define CSR_LCAM_CSR_LCAM_INT_VECTOR_REG (CSR_LCAM_CSR_BASE + 0x44) +#define CSR_LCAM_CSR_LCAM_INT_REG (CSR_LCAM_CSR_BASE + 0x48) /* SMIR interrupt data */ +#define CSR_LCAM_CSR_LCAM_INT_MASK_REG (CSR_LCAM_CSR_BASE + 0x4C) /* SMIR interrupt mask configuration */ +#define CSR_LCAM_CSR_LCAM_RING_ITF_ERR_REG (CSR_LCAM_CSR_BASE + 0x50) /* RING request channel 入口和出口发生的错误 */ +#define CSR_LCAM_CSR_LCAM_RING_ITF_ERR_MASK_REG (CSR_LCAM_CSR_BASE + 0x54) +#define CSR_LCAM_CSR_LCAM_AD_ECC_ONE_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x58) /* LCAM AD memory发生ECC校验1比特错误 */ +#define CSR_LCAM_CSR_LCAM_AD_ECC_TWO_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x5C) /* LCAM AD memory发生ECC校验2比特错误 */ +#define CSR_LCAM_CSR_LCAM_TCAM_ECC_ONE_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x60) /* LCAM TCAM IP发生ECC校验1比特错误 */ +#define CSR_LCAM_CSR_LCAM_TCAM_ECC_TWO_BIT_ERR_REG (CSR_LCAM_CSR_BASE + 0x64) /* LCAM TCAM IP发生ECC校验2比特错误 */ +#define CSR_LCAM_CSR_LCAM_CMD_ERR_REG (CSR_LCAM_CSR_BASE + 0x68) /* 软件配置错误 */ +#define CSR_LCAM_CSR_LCAM_CMD_ERR_MASK_REG (CSR_LCAM_CSR_BASE + 0x6C) +#define CSR_LCAM_CSR_LCAM_INIT_STATUS_REG (CSR_LCAM_CSR_BASE + 0x70) +#define CSR_LCAM_CSR_LCAM_ECC_ERR_INJ_REG (CSR_LCAM_CSR_BASE + 0x74) /* LCAM ECC memory error injection */ +#define CSR_LCAM_CSR_LCAM_SRC_ERR_REG (CSR_LCAM_CSR_BASE + 0x80) +#define CSR_LCAM_CSR_LCAM_SRC_ERR_MASK_REG (CSR_LCAM_CSR_BASE + 0x84) +#define CSR_LCAM_CSR_LCAM_SRC_CFG_REG (CSR_LCAM_CSR_BASE + 0x88) +#define CSR_LCAM_CSR_LCAM_SRC_CFG_NODE_ID0_REG (CSR_LCAM_CSR_BASE + 0x8C) +#define CSR_LCAM_CSR_LCAM_SRC_CFG_NODE_ID1_REG (CSR_LCAM_CSR_BASE + 0x90) +#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG0_REG (CSR_LCAM_CSR_BASE + 0x94) +#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG1_REG (CSR_LCAM_CSR_BASE + 0x98) +#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG2_REG (CSR_LCAM_CSR_BASE + 0x9C) +#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG3_REG (CSR_LCAM_CSR_BASE + 0xA0) +#define CSR_LCAM_CSR_LCAM_MEM_CTRL_BUS_CFG4_REG (CSR_LCAM_CSR_BASE + 0xA4) +#define CSR_LCAM_CSR_LCAM_TCAM_CTRL_BUS_CFG_REG (CSR_LCAM_CSR_BASE + 0xA8) + +#endif // LCAM_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_c_union_define.h new file mode 100644 index 000000000..7d81af8b6 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_c_union_define.h @@ -0,0 +1,11885 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : mqm_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:55:24 Create file +// ****************************************************************************** + +#ifndef MQM_C_UNION_DEFINE_H +#define MQM_C_UNION_DEFINE_H + +/* Define the union csr_mqm_edition_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_edition_u; + +/* Define the union csr_mqm_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_initctab_start : 1; /* [0] */ + u32 brm_initctab_start : 1; /* [1] */ + u32 iqm_initctab_start : 1; /* [2] */ + u32 msc_initctab_start : 1; /* [3] */ + u32 eqm_initctab_start : 1; /* [4] */ + u32 deqc_initctab_start : 1; /* [5] */ + u32 rsv_0 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_initctab_start_u; + +/* Define the union csr_mqm_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_initctab_done : 1; /* [0] */ + u32 rsv_1 : 15; /* [15:1] */ + u32 enqc_mqm_init_done : 1; /* [16] */ + u32 brm_mqm_init_done : 1; /* [17] */ + u32 iqm_mqm_init_done : 1; /* [18] */ + u32 msc_mqm_init_done : 1; /* [19] */ + u32 eqm_mqm_init_done : 1; /* [20] */ + u32 deqc_mqm_init_done : 1; /* [21] */ + u32 rsv_2 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_initctab_done_u; + +/* Define the union csr_mqm_cfg_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cfg_ok : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_cfg_ok_u; + +/* Define the union csr_mqm_initlogic_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_initlogic_done : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_initlogic_done_u; + +/* Define the union csr_mqm_top_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_cpi_int_index : 24; /* [23:0] */ + u32 rsv_5 : 3; /* [26:24] */ + u32 mqm_top_enable : 1; /* [27] */ + u32 mqm_top_int_issue : 1; /* [28] */ + u32 rsv_6 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_int_vector_u; + +/* Define the union csr_mqm_top_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_int_data : 4; /* [3:0] */ + u32 rsv_7 : 12; /* [15:4] */ + u32 mqm_top_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_int_u; + +/* Define the union csr_mqm_top_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_int_en : 4; /* [3:0] */ + u32 rsv_8 : 12; /* [15:4] */ + u32 mqm_top_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_int_en_u; + +/* Define the union csr_vf_flush_done_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_done_err : 1; /* [0] */ + u32 vf_flush_done_err_insrt : 1; /* [1] */ + u32 vf_flush_done_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_done_int_u; + +/* Define the union csr_mqm_rx_cnp_e0_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cnp_api_e0_err : 1; /* [0] */ + u32 mqm_cnp_api_e0_err_insert : 1; /* [1] */ + u32 mqm_cnp_api_e0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rx_cnp_e0_err_int_u; + +/* Define the union csr_mqm_rx_cnp_e1_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cnp_api_e1_err : 1; /* [0] */ + u32 mqm_cnp_api_e1_err_insert : 1; /* [1] */ + u32 mqm_cnp_api_e1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rx_cnp_e1_err_int_u; + +/* Define the union csr_mqm_top_fifo_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_fifo_int_err0 : 1; /* [0] */ + u32 mqm_top_fifo_int_err0_insrt : 1; /* [1] */ + u32 mqm_top_fifo_int_err1 : 1; /* [2] */ + u32 mqm_top_fifo_int_err1_insrt : 1; /* [3] */ + u32 mqm_top_fifo_int_err2 : 1; /* [4] */ + u32 mqm_top_fifo_int_err2_insrt : 1; /* [5] */ + u32 mqm_top_fifo_int_err3 : 1; /* [6] */ + u32 mqm_top_fifo_int_err3_insrt : 1; /* [7] */ + u32 rsv_9 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_fifo_int_u; + +/* Define the union csr_mqm_top_fifo_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_fifo_int_err0_en : 1; /* [0] */ + u32 mqm_top_fifo_int_err1_en : 1; /* [1] */ + u32 mqm_top_fifo_int_err2_en : 1; /* [2] */ + u32 mqm_top_fifo_int_err3_en : 1; /* [3] */ + u32 rsv_10 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_fifo_int_mask_u; + +/* Define the union csr_use_host_bitmap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 use_host_bmp : 4; /* [3:0] */ + u32 rsv_11 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_use_host_bitmap_u; + +/* Define the union csr_db_type_maping_tab0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 type0_map_id : 3; /* [2:0] */ + u32 type0_map_en : 1; /* [3] */ + u32 type1_map_id : 3; /* [6:4] */ + u32 type1_map_en : 1; /* [7] */ + u32 type2_map_id : 3; /* [10:8] */ + u32 type2_map_en : 1; /* [11] */ + u32 rsv_12 : 4; /* [15:12] */ + u32 type4_map_id : 3; /* [18:16] */ + u32 type4_map_en : 1; /* [19] */ + u32 rsv_13 : 4; /* [23:20] */ + u32 type6_map_id : 3; /* [26:24] */ + u32 type6_map_en : 1; /* [27] */ + u32 type7_map_id : 3; /* [30:28] */ + u32 type7_map_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_type_maping_tab0_u; + +/* Define the union csr_db_type_maping_tab1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 type8_map_id : 3; /* [2:0] */ + u32 type8_map_en : 1; /* [3] */ + u32 type9_map_id : 3; /* [6:4] */ + u32 type9_map_en : 1; /* [7] */ + u32 type10_map_id : 3; /* [10:8] */ + u32 type10_map_en : 1; /* [11] */ + u32 type11_map_id : 3; /* [14:12] */ + u32 type11_map_en : 1; /* [15] */ + u32 type12_map_id : 3; /* [18:16] */ + u32 type12_map_en : 1; /* [19] */ + u32 type13_map_id : 3; /* [22:20] */ + u32 type13_map_en : 1; /* [23] */ + u32 type14_map_id : 3; /* [26:24] */ + u32 type14_map_en : 1; /* [27] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_type_maping_tab1_u; + +/* Define the union csr_db_type_maping_tab2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_15 : 4; /* [3:0] */ + u32 type17_map_id : 3; /* [6:4] */ + u32 type17_map_en : 1; /* [7] */ + u32 rsv_16 : 8; /* [15:8] */ + u32 type20_map_id : 3; /* [18:16] */ + u32 type20_map_en : 1; /* [19] */ + u32 type21_map_id : 3; /* [22:20] */ + u32 type21_map_en : 1; /* [23] */ + u32 type22_map_id : 3; /* [26:24] */ + u32 type22_map_en : 1; /* [27] */ + u32 type23_map_id : 3; /* [30:28] */ + u32 type23_map_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_type_maping_tab2_u; + +/* Define the union csr_db_type_maping_tab3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 type24_map_id : 3; /* [2:0] */ + u32 type24_map_en : 1; /* [3] */ + u32 rsv_17 : 24; /* [27:4] */ + u32 type31_map_id : 3; /* [30:28] */ + u32 type31_map_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_type_maping_tab3_u; + +/* Define the union csr_mqm_cmq_enq_mode_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cmq_enq_mode_cfg : 2; /* [1:0] */ + u32 rsv_18 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_cmq_enq_mode_cfg_u; + +/* Define the union csr_mqm_max_dma_crdt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_max_dma_credit_sge_cfg : 8; /* [7:0] */ + u32 mqm_max_dma_credit_data_cfg : 8; /* [15:8] */ + u32 rsv_19 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_max_dma_crdt_cfg_u; + +/* Define the union csr_mqm_soc_use_pf_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_soc_use_pf_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_soc_use_pf_cfg_u; + +/* Define the union csr_mqm_pf_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_pf_offset_cfg : 4; /* [3:0] */ + u32 mqm_pf_use_mode_cfg : 3; /* [6:4] */ + u32 rsv_20 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_pf_cfg_u; + +/* Define the union csr_mqm_vf_flush_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_id : 13; /* [12:0] */ + u32 rsv_21 : 3; /* [15:13] */ + u32 vf_flush_host_id : 3; /* [18:16] */ + u32 rsv_22 : 1; /* [19] */ + u32 vf_flush_ep_id : 3; /* [22:20] */ + u32 rsv_23 : 1; /* [23] */ + u32 vf_flush_vld : 1; /* [24] */ + u32 rsv_24 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_vf_flush_cfg_u; + +/* Define the union csr_mqm_vf_flush_nmq_id_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_nmqid : 13; /* [12:0] */ + u32 rsv_25 : 3; /* [15:13] */ + u32 vf_flush_nmq_cos_id : 3; /* [18:16] */ + u32 rsv_26 : 5; /* [23:19] */ + u32 vf_flush_nmq_vld : 1; /* [24] */ + u32 rsv_27 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_vf_flush_nmq_id_cfg_u; + +/* Define the union csr_mqm_vf_flush_nfmq_id_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_nfmqid : 12; /* [11:0] */ + u32 rsv_28 : 4; /* [15:12] */ + u32 vf_flush_nfmq_cos_id : 3; /* [18:16] */ + u32 rsv_29 : 5; /* [23:19] */ + u32 vf_flush_nfmq_vld : 1; /* [24] */ + u32 rsv_30 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_vf_flush_nfmq_id_cfg_u; + +/* Define the union csr_vf_flush_r_txq_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_r_txq_num : 21; /* [20:0] */ + u32 rsv_31 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_r_txq_num_u; + +/* Define the union csr_vf_flush_r_txq_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_r_txq_baddr : 20; /* [19:0] */ + u32 rsv_32 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_r_txq_baddr_u; + +/* Define the union csr_vf_flush_s_txq_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_s_txq_num : 21; /* [20:0] */ + u32 rsv_33 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_s_txq_num_u; + +/* Define the union csr_vf_flush_s_txq_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_s_txq_baddr : 20; /* [19:0] */ + u32 rsv_34 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_s_txq_baddr_u; + +/* Define the union csr_vf_flush_f_txq_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_f_txq_num : 21; /* [20:0] */ + u32 rsv_35 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_f_txq_num_u; + +/* Define the union csr_vf_flush_f_txq_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_f_txq_baddr : 20; /* [19:0] */ + u32 rsv_36 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_f_txq_baddr_u; + +/* Define the union csr_vf_flush_u_txq_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_u_txq_num : 21; /* [20:0] */ + u32 rsv_37 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_u_txq_num_u; + +/* Define the union csr_vf_flush_u_txq_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_u_txq_baddr : 20; /* [19:0] */ + u32 rsv_38 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_u_txq_baddr_u; + +/* Define the union csr_vf_flush_lnic_sq_txq_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_ls_txq_num : 14; /* [13:0] */ + u32 rsv_39 : 2; /* [15:14] */ + u32 vf_flush_ls_txq_baddr : 13; /* [28:16] */ + u32 rsv_40 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_lnic_sq_txq_info_u; + +/* Define the union csr_vf_flush_lnic_rq_txq_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_flush_lr_txq_num : 14; /* [13:0] */ + u32 rsv_41 : 2; /* [15:14] */ + u32 vf_flush_lr_txq_baddr : 13; /* [28:16] */ + u32 rsv_42 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vf_flush_lnic_rq_txq_info_u; + +/* Define the union csr_mqm_vf_flush_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_vf_flush_done : 1; /* [0] */ + u32 rsv_43 : 3; /* [3:1] */ + u32 deqc_vf_flush_done : 1; /* [4] */ + u32 eqm_vf_flush_done : 1; /* [5] */ + u32 msc_vf_flush_done : 1; /* [6] */ + u32 iqm_vf_flush_done : 1; /* [7] */ + u32 enqc_vf_flush_done : 1; /* [8] */ + u32 rsv_44 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_vf_flush_done_u; + +/* Define the union csr_mqm_uncrt_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_uncrt_err_mask : 1; /* [0] */ + u32 other_uncrt_err_mask : 1; /* [1] */ + u32 rsv_45 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_uncrt_err_mask_u; + +/* Define the union csr_mqm_uncrt_err_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_uncrt_err_clr : 1; /* [0] */ + u32 other_uncrt_err_clr : 1; /* [1] */ + u32 rsv_46 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_uncrt_err_clr_u; + +/* Define the union csr_mqm_vf_count_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_count_designate_vfid : 13; /* [12:0] */ + u32 rsv_47 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_vf_count_cfg_u; + +/* Define the union csr_mqm_rx_designate_vfid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_rx_designate_vfid_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rx_designate_vfid_cnt_u; + +/* Define the union csr_mqm_filt_designate_vfid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_filt_designate_vfid_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_filt_designate_vfid_cnt_u; + +/* Define the union csr_mqm_tx_sm_designate_vfid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_tx_sm_designate_vfid_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_tx_sm_designate_vfid_cnt_u; + +/* Define the union csr_mqm_tx_qu_designate_vfid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_tx_qu_designate_vfid_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_tx_qu_designate_vfid_cnt_u; + +/* Define the union csr_mqm_rcv_tile_api_op_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_rcv_tile_opid_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rcv_tile_api_op_err_cnt_u; + +/* Define the union csr_mqm_rcv_tile_fast_cnp_api_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_rcv_tile_fast_cnp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rcv_tile_fast_cnp_api_cnt_u; + +/* Define the union csr_mqm_rcv_tile_cnp_api_e0e1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_rcv_tile_fast_cnp_e0e1_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_rcv_tile_cnp_api_e0e1_cnt_u; + +/* Define the union csr_mqm_nd_rs_rqst_credit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_nd_rs_rqst_credit : 3; /* [2:0] */ + u32 rsv_48 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_nd_rs_rqst_credit_u; + +/* Define the union csr_mqm_top_fifo_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_top_fifo0_st : 2; /* [1:0] */ + u32 mqm_top_fifo1_st : 2; /* [3:2] */ + u32 rsv_49 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_top_fifo_st_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_mqm_edition_u mqm_edition; /* 0 */ + volatile csr_mqm_initctab_start_u mqm_initctab_start; /* 4 */ + volatile csr_mqm_initctab_done_u mqm_initctab_done; /* 8 */ + volatile csr_mqm_cfg_ok_u mqm_cfg_ok; /* C */ + volatile csr_mqm_initlogic_done_u mqm_initlogic_done; /* 10 */ + volatile csr_mqm_top_int_vector_u mqm_top_int_vector; /* 30 */ + volatile csr_mqm_top_int_u mqm_top_int; /* 34 */ + volatile csr_mqm_top_int_en_u mqm_top_int_en; /* 38 */ + volatile csr_vf_flush_done_int_u vf_flush_done_int; /* 3C */ + volatile csr_mqm_rx_cnp_e0_err_int_u mqm_rx_cnp_e0_err_int; /* 40 */ + volatile csr_mqm_rx_cnp_e1_err_int_u mqm_rx_cnp_e1_err_int; /* 44 */ + volatile csr_mqm_top_fifo_int_u mqm_top_fifo_int; /* 48 */ + volatile csr_mqm_top_fifo_int_mask_u mqm_top_fifo_int_mask; /* 4C */ + volatile csr_use_host_bitmap_u use_host_bitmap; /* 80 */ + volatile csr_db_type_maping_tab0_u db_type_maping_tab0; /* 84 */ + volatile csr_db_type_maping_tab1_u db_type_maping_tab1; /* 88 */ + volatile csr_db_type_maping_tab2_u db_type_maping_tab2; /* 8C */ + volatile csr_db_type_maping_tab3_u db_type_maping_tab3; /* 90 */ + volatile csr_mqm_cmq_enq_mode_cfg_u mqm_cmq_enq_mode_cfg; /* 94 */ + volatile csr_mqm_max_dma_crdt_cfg_u mqm_max_dma_crdt_cfg; /* 98 */ + volatile csr_mqm_soc_use_pf_cfg_u mqm_soc_use_pf_cfg[4]; /* 9C */ + volatile csr_mqm_pf_cfg_u mqm_pf_cfg; /* AC */ + volatile csr_mqm_vf_flush_cfg_u mqm_vf_flush_cfg; /* 100 */ + volatile csr_mqm_vf_flush_nmq_id_cfg_u mqm_vf_flush_nmq_id_cfg[8]; /* 104 */ + volatile csr_mqm_vf_flush_nfmq_id_cfg_u mqm_vf_flush_nfmq_id_cfg[8]; /* 124 */ + volatile csr_vf_flush_r_txq_num_u vf_flush_r_txq_num; /* 144 */ + volatile csr_vf_flush_r_txq_baddr_u vf_flush_r_txq_baddr; /* 148 */ + volatile csr_vf_flush_s_txq_num_u vf_flush_s_txq_num; /* 14C */ + volatile csr_vf_flush_s_txq_baddr_u vf_flush_s_txq_baddr; /* 150 */ + volatile csr_vf_flush_f_txq_num_u vf_flush_f_txq_num; /* 154 */ + volatile csr_vf_flush_f_txq_baddr_u vf_flush_f_txq_baddr; /* 158 */ + volatile csr_vf_flush_u_txq_num_u vf_flush_u_txq_num; /* 15C */ + volatile csr_vf_flush_u_txq_baddr_u vf_flush_u_txq_baddr; /* 160 */ + volatile csr_vf_flush_lnic_sq_txq_info_u vf_flush_lnic_sq_txq_info; /* 164 */ + volatile csr_vf_flush_lnic_rq_txq_info_u vf_flush_lnic_rq_txq_info; /* 168 */ + volatile csr_mqm_vf_flush_done_u mqm_vf_flush_done; /* 174 */ + volatile csr_mqm_uncrt_err_mask_u mqm_uncrt_err_mask; /* 200 */ + volatile csr_mqm_uncrt_err_clr_u mqm_uncrt_err_clr; /* 204 */ + volatile csr_mqm_vf_count_cfg_u mqm_vf_count_cfg; /* 304 */ + volatile csr_mqm_rx_designate_vfid_cnt_u mqm_rx_designate_vfid_cnt; /* 308 */ + volatile csr_mqm_filt_designate_vfid_cnt_u mqm_filt_designate_vfid_cnt; /* 30C */ + volatile csr_mqm_tx_sm_designate_vfid_cnt_u mqm_tx_sm_designate_vfid_cnt; /* 310 */ + volatile csr_mqm_tx_qu_designate_vfid_cnt_u mqm_tx_qu_designate_vfid_cnt; /* 314 */ + volatile csr_mqm_rcv_tile_api_op_err_cnt_u mqm_rcv_tile_api_op_err_cnt; /* 318 */ + volatile csr_mqm_rcv_tile_fast_cnp_api_cnt_u mqm_rcv_tile_fast_cnp_api_cnt; /* 31C */ + volatile csr_mqm_rcv_tile_cnp_api_e0e1_cnt_u mqm_rcv_tile_cnp_api_e0e1_cnt; /* 320 */ + volatile csr_mqm_nd_rs_rqst_credit_u mqm_nd_rs_rqst_credit; /* 324 */ + volatile csr_mqm_top_fifo_st_u mqm_top_fifo_st; /* 328 */ +} S_mqm_top_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_top */ +extern volatile S_mqm_top_REGS_TYPE *gopmqm_topAllReg; + +/* Declare the functions that set the member value */ +int iSetMQM_EDITION_mqm_version(unsigned int umqm_version); +int iSetMQM_INITCTAB_START_enqc_initctab_start(unsigned int uenqc_initctab_start); +int iSetMQM_INITCTAB_START_brm_initctab_start(unsigned int ubrm_initctab_start); +int iSetMQM_INITCTAB_START_iqm_initctab_start(unsigned int uiqm_initctab_start); +int iSetMQM_INITCTAB_START_msc_initctab_start(unsigned int umsc_initctab_start); +int iSetMQM_INITCTAB_START_eqm_initctab_start(unsigned int ueqm_initctab_start); +int iSetMQM_INITCTAB_START_deqc_initctab_start(unsigned int udeqc_initctab_start); +int iSetMQM_INITCTAB_DONE_mqm_initctab_done(unsigned int umqm_initctab_done); +int iSetMQM_INITCTAB_DONE_enqc_mqm_init_done(unsigned int uenqc_mqm_init_done); +int iSetMQM_INITCTAB_DONE_brm_mqm_init_done(unsigned int ubrm_mqm_init_done); +int iSetMQM_INITCTAB_DONE_iqm_mqm_init_done(unsigned int uiqm_mqm_init_done); +int iSetMQM_INITCTAB_DONE_msc_mqm_init_done(unsigned int umsc_mqm_init_done); +int iSetMQM_INITCTAB_DONE_eqm_mqm_init_done(unsigned int ueqm_mqm_init_done); +int iSetMQM_INITCTAB_DONE_deqc_mqm_init_done(unsigned int udeqc_mqm_init_done); +int iSetMQM_CFG_OK_mqm_cfg_ok(unsigned int umqm_cfg_ok); +int iSetMQM_INITLOGIC_DONE_mqm_initlogic_done(unsigned int umqm_initlogic_done); +int iSetMQM_TOP_INT_VECTOR_mqm_top_cpi_int_index(unsigned int umqm_top_cpi_int_index); +int iSetMQM_TOP_INT_VECTOR_mqm_top_enable(unsigned int umqm_top_enable); +int iSetMQM_TOP_INT_VECTOR_mqm_top_int_issue(unsigned int umqm_top_int_issue); +int iSetMQM_TOP_INT_mqm_top_int_data(unsigned int umqm_top_int_data); +int iSetMQM_TOP_INT_mqm_top_program_csr_id_ro(unsigned int umqm_top_program_csr_id_ro); +int iSetMQM_TOP_INT_EN_mqm_top_int_en(unsigned int umqm_top_int_en); +int iSetMQM_TOP_INT_EN_mqm_top_program_csr_id(unsigned int umqm_top_program_csr_id); +int iSetVF_FLUSH_DONE_INT_vf_flush_done_err(unsigned int uvf_flush_done_err); +int iSetVF_FLUSH_DONE_INT_vf_flush_done_err_insrt(unsigned int uvf_flush_done_err_insrt); +int iSetVF_FLUSH_DONE_INT_vf_flush_done_err_info(unsigned int uvf_flush_done_err_info); +int iSetMQM_RX_CNP_E0_ERR_INT_mqm_cnp_api_e0_err(unsigned int umqm_cnp_api_e0_err); +int iSetMQM_RX_CNP_E0_ERR_INT_mqm_cnp_api_e0_err_insert(unsigned int umqm_cnp_api_e0_err_insert); +int iSetMQM_RX_CNP_E0_ERR_INT_mqm_cnp_api_e0_err_info(unsigned int umqm_cnp_api_e0_err_info); +int iSetMQM_RX_CNP_E1_ERR_INT_mqm_cnp_api_e1_err(unsigned int umqm_cnp_api_e1_err); +int iSetMQM_RX_CNP_E1_ERR_INT_mqm_cnp_api_e1_err_insert(unsigned int umqm_cnp_api_e1_err_insert); +int iSetMQM_RX_CNP_E1_ERR_INT_mqm_cnp_api_e1_err_info(unsigned int umqm_cnp_api_e1_err_info); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err0(unsigned int umqm_top_fifo_int_err0); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err0_insrt(unsigned int umqm_top_fifo_int_err0_insrt); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err1(unsigned int umqm_top_fifo_int_err1); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err1_insrt(unsigned int umqm_top_fifo_int_err1_insrt); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err2(unsigned int umqm_top_fifo_int_err2); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err2_insrt(unsigned int umqm_top_fifo_int_err2_insrt); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err3(unsigned int umqm_top_fifo_int_err3); +int iSetMQM_TOP_FIFO_INT_mqm_top_fifo_int_err3_insrt(unsigned int umqm_top_fifo_int_err3_insrt); +int iSetMQM_TOP_FIFO_INT_MASK_mqm_top_fifo_int_err0_en(unsigned int umqm_top_fifo_int_err0_en); +int iSetMQM_TOP_FIFO_INT_MASK_mqm_top_fifo_int_err1_en(unsigned int umqm_top_fifo_int_err1_en); +int iSetMQM_TOP_FIFO_INT_MASK_mqm_top_fifo_int_err2_en(unsigned int umqm_top_fifo_int_err2_en); +int iSetMQM_TOP_FIFO_INT_MASK_mqm_top_fifo_int_err3_en(unsigned int umqm_top_fifo_int_err3_en); +int iSetUSE_HOST_BITMAP_use_host_bmp(unsigned int uuse_host_bmp); +int iSetDB_TYPE_MAPING_TAB0_type0_map_id(unsigned int utype0_map_id); +int iSetDB_TYPE_MAPING_TAB0_type0_map_en(unsigned int utype0_map_en); +int iSetDB_TYPE_MAPING_TAB0_type1_map_id(unsigned int utype1_map_id); +int iSetDB_TYPE_MAPING_TAB0_type1_map_en(unsigned int utype1_map_en); +int iSetDB_TYPE_MAPING_TAB0_type2_map_id(unsigned int utype2_map_id); +int iSetDB_TYPE_MAPING_TAB0_type2_map_en(unsigned int utype2_map_en); +int iSetDB_TYPE_MAPING_TAB0_type4_map_id(unsigned int utype4_map_id); +int iSetDB_TYPE_MAPING_TAB0_type4_map_en(unsigned int utype4_map_en); +int iSetDB_TYPE_MAPING_TAB0_type6_map_id(unsigned int utype6_map_id); +int iSetDB_TYPE_MAPING_TAB0_type6_map_en(unsigned int utype6_map_en); +int iSetDB_TYPE_MAPING_TAB0_type7_map_id(unsigned int utype7_map_id); +int iSetDB_TYPE_MAPING_TAB0_type7_map_en(unsigned int utype7_map_en); +int iSetDB_TYPE_MAPING_TAB1_type8_map_id(unsigned int utype8_map_id); +int iSetDB_TYPE_MAPING_TAB1_type8_map_en(unsigned int utype8_map_en); +int iSetDB_TYPE_MAPING_TAB1_type9_map_id(unsigned int utype9_map_id); +int iSetDB_TYPE_MAPING_TAB1_type9_map_en(unsigned int utype9_map_en); +int iSetDB_TYPE_MAPING_TAB1_type10_map_id(unsigned int utype10_map_id); +int iSetDB_TYPE_MAPING_TAB1_type10_map_en(unsigned int utype10_map_en); +int iSetDB_TYPE_MAPING_TAB1_type11_map_id(unsigned int utype11_map_id); +int iSetDB_TYPE_MAPING_TAB1_type11_map_en(unsigned int utype11_map_en); +int iSetDB_TYPE_MAPING_TAB1_type12_map_id(unsigned int utype12_map_id); +int iSetDB_TYPE_MAPING_TAB1_type12_map_en(unsigned int utype12_map_en); +int iSetDB_TYPE_MAPING_TAB1_type13_map_id(unsigned int utype13_map_id); +int iSetDB_TYPE_MAPING_TAB1_type13_map_en(unsigned int utype13_map_en); +int iSetDB_TYPE_MAPING_TAB1_type14_map_id(unsigned int utype14_map_id); +int iSetDB_TYPE_MAPING_TAB1_type14_map_en(unsigned int utype14_map_en); +int iSetDB_TYPE_MAPING_TAB2_type17_map_id(unsigned int utype17_map_id); +int iSetDB_TYPE_MAPING_TAB2_type17_map_en(unsigned int utype17_map_en); +int iSetDB_TYPE_MAPING_TAB2_type20_map_id(unsigned int utype20_map_id); +int iSetDB_TYPE_MAPING_TAB2_type20_map_en(unsigned int utype20_map_en); +int iSetDB_TYPE_MAPING_TAB2_type21_map_id(unsigned int utype21_map_id); +int iSetDB_TYPE_MAPING_TAB2_type21_map_en(unsigned int utype21_map_en); +int iSetDB_TYPE_MAPING_TAB2_type22_map_id(unsigned int utype22_map_id); +int iSetDB_TYPE_MAPING_TAB2_type22_map_en(unsigned int utype22_map_en); +int iSetDB_TYPE_MAPING_TAB2_type23_map_id(unsigned int utype23_map_id); +int iSetDB_TYPE_MAPING_TAB2_type23_map_en(unsigned int utype23_map_en); +int iSetDB_TYPE_MAPING_TAB3_type24_map_id(unsigned int utype24_map_id); +int iSetDB_TYPE_MAPING_TAB3_type24_map_en(unsigned int utype24_map_en); +int iSetDB_TYPE_MAPING_TAB3_type31_map_id(unsigned int utype31_map_id); +int iSetDB_TYPE_MAPING_TAB3_type31_map_en(unsigned int utype31_map_en); +int iSetMQM_CMQ_ENQ_MODE_CFG_mqm_cmq_enq_mode_cfg(unsigned int umqm_cmq_enq_mode_cfg); +int iSetMQM_MAX_DMA_CRDT_CFG_mqm_max_dma_credit_sge_cfg(unsigned int umqm_max_dma_credit_sge_cfg); +int iSetMQM_MAX_DMA_CRDT_CFG_mqm_max_dma_credit_data_cfg(unsigned int umqm_max_dma_credit_data_cfg); +int iSetMQM_SOC_USE_PF_CFG_mqm_soc_use_pf_cfg(unsigned int umqm_soc_use_pf_cfg); +int iSetMQM_PF_CFG_mqm_pf_offset_cfg(unsigned int umqm_pf_offset_cfg); +int iSetMQM_PF_CFG_mqm_pf_use_mode_cfg(unsigned int umqm_pf_use_mode_cfg); +int iSetMQM_VF_FLUSH_CFG_vf_flush_id(unsigned int uvf_flush_id); +int iSetMQM_VF_FLUSH_CFG_vf_flush_host_id(unsigned int uvf_flush_host_id); +int iSetMQM_VF_FLUSH_CFG_vf_flush_ep_id(unsigned int uvf_flush_ep_id); +int iSetMQM_VF_FLUSH_CFG_vf_flush_vld(unsigned int uvf_flush_vld); +int iSetMQM_VF_FLUSH_NMQ_ID_CFG_vf_flush_nmqid(unsigned int uvf_flush_nmqid); +int iSetMQM_VF_FLUSH_NMQ_ID_CFG_vf_flush_nmq_cos_id(unsigned int uvf_flush_nmq_cos_id); +int iSetMQM_VF_FLUSH_NMQ_ID_CFG_vf_flush_nmq_vld(unsigned int uvf_flush_nmq_vld); +int iSetMQM_VF_FLUSH_NFMQ_ID_CFG_vf_flush_nfmqid(unsigned int uvf_flush_nfmqid); +int iSetMQM_VF_FLUSH_NFMQ_ID_CFG_vf_flush_nfmq_cos_id(unsigned int uvf_flush_nfmq_cos_id); +int iSetMQM_VF_FLUSH_NFMQ_ID_CFG_vf_flush_nfmq_vld(unsigned int uvf_flush_nfmq_vld); +int iSetVF_FLUSH_R_TXQ_NUM_vf_flush_r_txq_num(unsigned int uvf_flush_r_txq_num); +int iSetVF_FLUSH_R_TXQ_BADDR_vf_flush_r_txq_baddr(unsigned int uvf_flush_r_txq_baddr); +int iSetVF_FLUSH_S_TXQ_NUM_vf_flush_s_txq_num(unsigned int uvf_flush_s_txq_num); +int iSetVF_FLUSH_S_TXQ_BADDR_vf_flush_s_txq_baddr(unsigned int uvf_flush_s_txq_baddr); +int iSetVF_FLUSH_F_TXQ_NUM_vf_flush_f_txq_num(unsigned int uvf_flush_f_txq_num); +int iSetVF_FLUSH_F_TXQ_BADDR_vf_flush_f_txq_baddr(unsigned int uvf_flush_f_txq_baddr); +int iSetVF_FLUSH_U_TXQ_NUM_vf_flush_u_txq_num(unsigned int uvf_flush_u_txq_num); +int iSetVF_FLUSH_U_TXQ_BADDR_vf_flush_u_txq_baddr(unsigned int uvf_flush_u_txq_baddr); +int iSetVF_FLUSH_LNIC_SQ_TXQ_INFO_vf_flush_ls_txq_num(unsigned int uvf_flush_ls_txq_num); +int iSetVF_FLUSH_LNIC_SQ_TXQ_INFO_vf_flush_ls_txq_baddr(unsigned int uvf_flush_ls_txq_baddr); +int iSetVF_FLUSH_LNIC_RQ_TXQ_INFO_vf_flush_lr_txq_num(unsigned int uvf_flush_lr_txq_num); +int iSetVF_FLUSH_LNIC_RQ_TXQ_INFO_vf_flush_lr_txq_baddr(unsigned int uvf_flush_lr_txq_baddr); +int iSetMQM_VF_FLUSH_DONE_mqm_vf_flush_done(unsigned int umqm_vf_flush_done); +int iSetMQM_VF_FLUSH_DONE_deqc_vf_flush_done(unsigned int udeqc_vf_flush_done); +int iSetMQM_VF_FLUSH_DONE_eqm_vf_flush_done(unsigned int ueqm_vf_flush_done); +int iSetMQM_VF_FLUSH_DONE_msc_vf_flush_done(unsigned int umsc_vf_flush_done); +int iSetMQM_VF_FLUSH_DONE_iqm_vf_flush_done(unsigned int uiqm_vf_flush_done); +int iSetMQM_VF_FLUSH_DONE_enqc_vf_flush_done(unsigned int uenqc_vf_flush_done); +int iSetMQM_UNCRT_ERR_MASK_ram_uncrt_err_mask(unsigned int uram_uncrt_err_mask); +int iSetMQM_UNCRT_ERR_MASK_other_uncrt_err_mask(unsigned int uother_uncrt_err_mask); +int iSetMQM_UNCRT_ERR_CLR_ram_uncrt_err_clr(unsigned int uram_uncrt_err_clr); +int iSetMQM_UNCRT_ERR_CLR_other_uncrt_err_clr(unsigned int uother_uncrt_err_clr); +int iSetMQM_VF_COUNT_CFG_mqm_count_designate_vfid(unsigned int umqm_count_designate_vfid); +int iSetMQM_RX_DESIGNATE_VFID_CNT_mqm_rx_designate_vfid_cnt(unsigned int umqm_rx_designate_vfid_cnt); +int iSetMQM_FILT_DESIGNATE_VFID_CNT_mqm_filt_designate_vfid_cnt(unsigned int umqm_filt_designate_vfid_cnt); +int iSetMQM_TX_SM_DESIGNATE_VFID_CNT_mqm_tx_sm_designate_vfid_cnt(unsigned int umqm_tx_sm_designate_vfid_cnt); +int iSetMQM_TX_QU_DESIGNATE_VFID_CNT_mqm_tx_qu_designate_vfid_cnt(unsigned int umqm_tx_qu_designate_vfid_cnt); +int iSetMQM_RCV_TILE_API_OP_ERR_CNT_mqm_rcv_tile_opid_err_cnt(unsigned int umqm_rcv_tile_opid_err_cnt); +int iSetMQM_RCV_TILE_FAST_CNP_API_CNT_mqm_rcv_tile_fast_cnp_cnt(unsigned int umqm_rcv_tile_fast_cnp_cnt); +int iSetMQM_RCV_TILE_CNP_API_E0E1_CNT_mqm_rcv_tile_fast_cnp_e0e1_cnt(unsigned int umqm_rcv_tile_fast_cnp_e0e1_cnt); +int iSetMQM_ND_RS_RQST_CREDIT_mqm_nd_rs_rqst_credit(unsigned int umqm_nd_rs_rqst_credit); +int iSetMQM_TOP_FIFO_ST_mqm_top_fifo0_st(unsigned int umqm_top_fifo0_st); +int iSetMQM_TOP_FIFO_ST_mqm_top_fifo1_st(unsigned int umqm_top_fifo1_st); + +/* Define the union csr_enqc_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rw_rsv0_u; + +/* Define the union csr_enqc_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rw_rsv1_u; + +/* Define the union csr_enqc_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rw_rsv2_u; + +/* Define the union csr_enqc_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rw_rsv3_u; + +/* Define the union csr_enqc_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_indrect_addr : 14; /* [13:0] */ + u32 rsv_0 : 10; /* [23:14] */ + u32 enqc_indrect_tab : 4; /* [27:24] */ + u32 enqc_indrect_status : 2; /* [29:28] */ + u32 enqc_indrect_mode : 1; /* [30] */ + u32 enqc_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_indrect_ctrl_u; + +/* Define the union csr_enqc_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_indrect_timeout_u; + +/* Define the union csr_enqc_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_indrect_data_0_u; + +/* Define the union csr_enqc_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_indrect_data_1_u; + +/* Define the union csr_enqc_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_cpi_int_index : 24; /* [23:0] */ + u32 rsv_1 : 3; /* [26:24] */ + u32 enqc_enable : 1; /* [27] */ + u32 enqc_int_issue : 1; /* [28] */ + u32 rsv_2 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_int_vector_u; + +/* Define the union csr_enqc_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_int_data : 13; /* [12:0] */ + u32 rsv_3 : 3; /* [15:13] */ + u32 enqc_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_int_u; + +/* Define the union csr_enqc_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_int_en : 13; /* [12:0] */ + u32 rsv_4 : 3; /* [15:13] */ + u32 enqc_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_int_en_u; + +/* Define the union csr_enqc_mem_ecc_err0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_ecc0_err : 1; /* [0] */ + u32 enqc_ecc0_err_insert : 1; /* [1] */ + u32 enqc_ecc0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ecc_err0_u; + +/* Define the union csr_enqc_mem_ecc_err1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_ecc1_err : 1; /* [0] */ + u32 enqc_ecc1_err_insert : 1; /* [1] */ + u32 enqc_ecc1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ecc_err1_u; + +/* Define the union csr_table_rd_invld_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 table_rd_err : 1; /* [0] */ + u32 table_rd_err_insert : 1; /* [1] */ + u32 table_rd_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_table_rd_invld_int_u; + +/* Define the union csr_vfpf_to_host_id_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfpf_hid_err : 1; /* [0] */ + u32 vfpf_hid_err_insert : 1; /* [1] */ + u32 vfpf_hid_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_vfpf_to_host_id_int_u; + +/* Define the union csr_qu_enqc_db_if_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_enqc_db_interface_err : 1; /* [0] */ + u32 qu_enqc_db_interface_err_insert : 1; /* [1] */ + u32 qu_enqc_db_interface_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qu_enqc_db_if_int_u; + +/* Define the union csr_cpi_discard_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_discard_int_err : 1; /* [0] */ + u32 cpi_discard_int_err_insert : 1; /* [1] */ + u32 cpi_discard_int_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_discard_int_u; + +/* Define the union csr_enqc_fifo_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_fifo_wr_ovfl_int_err : 1; /* [0] */ + u32 cpi_fifo_wr_ovfl_int_err_insert : 1; /* [1] */ + u32 tile_fifo_wr_ovfl_int_err : 1; /* [2] */ + u32 tile_fifo_wr_ovfl_int_err_insert : 1; /* [3] */ + u32 sm_fifo_wr_ovfl_int_err : 1; /* [4] */ + u32 sm_fifo_wr_ovfl_int_err_insert : 1; /* [5] */ + u32 mrf_fifo_wr_ovfl_int_err : 1; /* [6] */ + u32 mrf_fifo_wr_ovfl_int_err_insert : 1; /* [7] */ + u32 dul_fifo_wr_ovfl_int_err : 1; /* [8] */ + u32 dul_fifo_wr_ovfl_int_err_insert : 1; /* [9] */ + u32 emq_enq_fifo_wr_ovfl_int_err : 1; /* [10] */ + u32 emq_enq_fifo_wr_ovfl_int_err_insert : 1; /* [11] */ + u32 cpi_fifo_rd_udfl_int_err : 1; /* [12] */ + u32 cpi_fifo_rd_udfl_int_err_insert : 1; /* [13] */ + u32 emq_enq_fifo_rd_udfl_int_err : 1; /* [14] */ + u32 emq_enq_fifo_rd_udfl_int_err_insert : 1; /* [15] */ + u32 passthru_fifo_rd_udfl_int_err : 1; /* [16] */ + u32 passthru_fifo_rd_udfl_int_err_insert : 1; /* [17] */ + u32 passthru_fifo_wr_ovfl_int_err : 1; /* [18] */ + u32 passthru_fifo_wr_ovfl_int_err_insert : 1; /* [19] */ + u32 qu_fifo_wr_ovfl_int_err : 1; /* [20] */ + u32 qu_fifo_wr_ovfl_int_err_insert : 1; /* [21] */ + u32 qu_fifo_rd_udfl_int_err : 1; /* [22] */ + u32 qu_fifo_rd_udfl_int_err_insert : 1; /* [23] */ + u32 tile_fifo_rd_udfl_int_err : 1; /* [24] */ + u32 tile_fifo_rd_udfl_int_err_insert : 1; /* [25] */ + u32 sm_fifo_rd_udfl_int_err : 1; /* [26] */ + u32 sm_fifo_rd_udfl_int_err_insert : 1; /* [27] */ + u32 rsv_5 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_fifo_int_u; + +/* Define the union csr_enqc_fifo_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_fifo_wr_ovfl_int_err_en : 1; /* [0] */ + u32 tile_fifo_wr_ovfl_int_err_en : 1; /* [1] */ + u32 sm_fifo_wr_ovfl_int_err_en : 1; /* [2] */ + u32 mrf_fifo_wr_ovfl_int_err_en : 1; /* [3] */ + u32 dul_fifo_wr_ovfl_int_err_en : 1; /* [4] */ + u32 emq_enq_fifo_wr_ovfl_int_err_en : 1; /* [5] */ + u32 cpi_fifo_rd_udfl_int_err_en : 1; /* [6] */ + u32 emq_enq_fifo_rd_udfl_int_err_en : 1; /* [7] */ + u32 passthru_fifo_rd_udfl_int_err_en : 1; /* [8] */ + u32 passthru_fifo_wr_ovfl_int_err_en : 1; /* [9] */ + u32 qu_fifo_rd_udfl_int_err_en : 1; /* [10] */ + u32 qu_fifo_wr_ovfl_int_err_en : 1; /* [11] */ + u32 tile_fifo_rd_udfl_int_err_en : 1; /* [12] */ + u32 sm_fifo_rd_udfl_int_err_en : 1; /* [13] */ + u32 rsv_6 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_fifo_int_en_u; + +/* Define the union csr_enqc_qf_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_qf_int_err : 1; /* [0] */ + u32 enqc_qf_int_err_insert : 1; /* [1] */ + u32 enqc_qf_int_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_qf_int_u; + +/* Define the union csr_rx_ring_e0_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_e0_err : 1; /* [0] */ + u32 ring_e0_err_insert : 1; /* [1] */ + u32 ring_e0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_ring_e0_err_int_u; + +/* Define the union csr_rx_ring_e1_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_e1_err : 1; /* [0] */ + u32 ring_e1_err_insert : 1; /* [1] */ + u32 ring_e1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rx_ring_e1_err_int_u; + +/* Define the union csr_enqc_txqid_ovfl_vf_range_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 txqid_ovfl_vf_range_int_err : 1; /* [0] */ + u32 txqid_ovfl_vf_range_int_err_insert : 1; /* [1] */ + u32 txqid_ovfl_vf_range_int_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_txqid_ovfl_vf_range_int_u; + +/* Define the union csr_enqc_nonf_num_ovfl_thr_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nonf_num_ovfl_err : 1; /* [0] */ + u32 nonf_num_ovfl_err_insert : 1; /* [1] */ + u32 nonf_num_ovfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_nonf_num_ovfl_thr_int_u; + +/* Define the union csr_enqc_err_typ_db_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 db_type_err : 1; /* [0] */ + u32 db_type_err_insert : 1; /* [1] */ + u32 db_type_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_err_typ_db_int_u; + +/* Define the union csr_enqc_mem_ecc_req0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vfp1_mem_ecc_req : 2; /* [1:0] */ + u32 vfp2_mem_ecc_req : 2; /* [3:2] */ + u32 vfp3_mem_ecc_req : 2; /* [5:4] */ + u32 vfr_mem_ecc_req : 2; /* [7:6] */ + u32 vf2nmq_mem_ecc_req : 2; /* [9:8] */ + u32 vf2nfmq_mem_ecc_req : 2; /* [11:10] */ + u32 emq_cnt_mem_ecc_req : 2; /* [13:12] */ + u32 durf_fifo_a_mem_err_req : 2; /* [15:14] */ + u32 durf_fifo_b_mem_err_req : 2; /* [17:16] */ + u32 mrf_fifo_a_mem_err_req : 2; /* [19:18] */ + u32 mrf_fifo_b_mem_err_req : 2; /* [21:20] */ + u32 vf_pi_baddr_lim_mem_err_req : 2; /* [23:22] */ + u32 rsv_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ecc_req0_u; + +/* Define the union csr_enqc_mem_ecc_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf2ep_mem_err_req : 2; /* [1:0] */ + u32 vf_range1_mem_err_req : 2; /* [3:2] */ + u32 vf_range2_mem_err_req : 2; /* [5:4] */ + u32 vf_range3_mem_err_req : 2; /* [7:6] */ + u32 vf_nonflt_thr_mem_err_req : 2; /* [9:8] */ + u32 vf_nonflt_cnt_mem_err_req : 2; /* [11:10] */ + u32 rsv_8 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ecc_req1_u; + +/* Define the union csr_enqc_qu_db_if_uncrt_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_enqc_db_if_err_en : 1; /* [0] */ + u32 rsv_9 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_qu_db_if_uncrt_int_en_u; + +/* Define the union csr_enqc_uncrt_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qf_clr_err_uncrt_int_en : 1; /* [0] */ + u32 rx_ring_e1_uncrt_int_en : 1; /* [1] */ + u32 rx_ring_e0_uncrt_int_en : 1; /* [2] */ + u32 rsv_10 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_uncrt_int_en_u; + +/* Define the union csr_enqc_sendq_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_stxq_baddr : 21; /* [20:0] */ + u32 rsv_11 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_sendq_base_addr_u; + +/* Define the union csr_enqc_sendq_scope_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_stxq_lim : 21; /* [20:0] */ + u32 rsv_12 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_sendq_scope_u; + +/* Define the union csr_enqc_taskio_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_ttxq_baddr : 21; /* [20:0] */ + u32 rsv_13 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_taskio_base_addr_u; + +/* Define the union csr_enqc_taskio_scope_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_ttxq_lim : 21; /* [20:0] */ + u32 rsv_14 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_taskio_scope_u; + +/* Define the union csr_enqc_rdma_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_rtxq_baddr : 21; /* [20:0] */ + u32 rsv_15 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rdma_base_addr_u; + +/* Define the union csr_enqc_rdma_scope_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_rtxq_lim : 21; /* [20:0] */ + u32 rsv_16 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rdma_scope_u; + +/* Define the union csr_enqc_ftxqid_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_ftxq_baddr : 21; /* [20:0] */ + u32 rsv_17 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_ftxqid_base_addr_u; + +/* Define the union csr_enqc_ftxqid_scope_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_ftxq_lim : 21; /* [20:0] */ + u32 rsv_18 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_ftxqid_scope_u; + +/* Define the union csr_enqc_utxqid_base_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_utxq_baddr : 21; /* [20:0] */ + u32 rsv_19 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_utxqid_base_addr_u; + +/* Define the union csr_enqc_utxqid_scope_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flt_utxq_lim : 21; /* [20:0] */ + u32 rsv_20 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_utxqid_scope_u; + +/* Define the union csr_soc_pf_base_lnic_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_base_lnic_sq_soc : 9; /* [8:0] */ + u32 rsv_21 : 3; /* [11:9] */ + u32 pf_base_lnic_rq_soc : 12; /* [23:12] */ + u32 rsv_22 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_pf_base_lnic_u; + +/* Define the union csr_soc_pf_range_lnic_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pf_range_dat_lnic_sq_soc : 8; /* [7:0] */ + u32 rsv_23 : 4; /* [11:8] */ + u32 pf_range_dat_lnic_rq_soc : 11; /* [22:12] */ + u32 rsv_24 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_pf_range_lnic_u; + +/* Define the union csr_enqc_host_lnic_sq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_lnic_sq_baddr : 17; /* [16:0] */ + u32 rsv_25 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_lnic_sq_cnt_baddr_u; + +/* Define the union csr_enqc_host_lnic_sq_cnt_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_lnic_sq_lim : 17; /* [16:0] */ + u32 rsv_26 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_lnic_sq_cnt_limit_u; + +/* Define the union csr_enqc_host_lnic_rq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_lnic_rq_baddr : 17; /* [16:0] */ + u32 rsv_27 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_lnic_rq_cnt_baddr_u; + +/* Define the union csr_enqc_host_lnic_rq_cnt_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_lnic_rq_lim : 17; /* [16:0] */ + u32 rsv_28 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_lnic_rq_cnt_limit_u; + +/* Define the union csr_enqc_sq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_send_baddr : 17; /* [16:0] */ + u32 rsv_29 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_sq_cnt_baddr_u; + +/* Define the union csr_enqc_sq_cnt_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_send_lim : 17; /* [16:0] */ + u32 rsv_30 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_sq_cnt_limit_u; + +/* Define the union csr_enqc_host_cmq_cnt_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_cmq_lim : 17; /* [16:0] */ + u32 rsv_31 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_cmq_cnt_limit_u; + +/* Define the union csr_enqc_pf_range_portx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 portx_pf_func_idx_l : 5; /* [4:0] */ + u32 rsv_32 : 11; /* [15:5] */ + u32 portx_pf_func_idx_h : 5; /* [20:16] */ + u32 rsv_33 : 10; /* [30:21] */ + u32 portx_pf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_pf_range_portx_u; + +/* Define the union csr_enqc_vf_range_portx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 portx_vf_func_idx_l : 12; /* [11:0] */ + u32 rsv_34 : 4; /* [15:12] */ + u32 portx_vf_func_idx_h : 12; /* [27:16] */ + u32 rsv_35 : 3; /* [30:28] */ + u32 portx_vf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_vf_range_portx_u; + +/* Define the union csr_enqc_lvf_range_portx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 portx_lvf_func_idx_l : 12; /* [11:0] */ + u32 rsv_36 : 4; /* [15:12] */ + u32 portx_lvf_func_idx_h : 12; /* [27:16] */ + u32 rsv_37 : 3; /* [30:28] */ + u32 portx_lvf_func_idx_v : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_lvf_range_portx_u; + +/* Define the union csr_enqc_enqc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq2emq_cfg : 1; /* [0] */ + u32 rsv_38 : 3; /* [3:1] */ + u32 enqc_qf_rdma_half_cfg : 1; /* [4] */ + u32 rsv_39 : 7; /* [11:5] */ + u32 cpi_discard_en : 1; /* [12] */ + u32 rsv_40 : 3; /* [15:13] */ + u32 rx_du_length_unit : 5; /* [20:16] */ + u32 rsv_41 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_enqc_cfg_u; + +/* Define the union csr_soc_stateful_db_map_hid_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soc_stateful_db_map_hid : 2; /* [1:0] */ + u32 soc_stateful_db_map_vld : 1; /* [2] */ + u32 rsv_42 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_stateful_db_map_hid_u; + +/* Define the union csr_enqc_in_fifo_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_aful_gap : 4; /* [3:0] */ + u32 rsv_43 : 4; /* [7:4] */ + u32 tile_aful_gap : 3; /* [10:8] */ + u32 rsv_44 : 5; /* [15:11] */ + u32 qu_aful_gap : 4; /* [19:16] */ + u32 rsv_45 : 4; /* [23:20] */ + u32 sm_aful_gap : 3; /* [26:24] */ + u32 rsv_46 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_in_fifo_gap_u; + +/* Define the union csr_enqc_eqm_pt_fifo_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 passthru_fifo_aful_gap : 4; /* [3:0] */ + u32 rsv_47 : 4; /* [7:4] */ + u32 emq_enq_fifo_afull_gap : 4; /* [11:8] */ + u32 rsv_48 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_eqm_pt_fifo_gap_u; + +/* Define the union csr_enqc_mrf_fifo_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mrf_afull_th : 9; /* [8:0] */ + u32 rsv_49 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mrf_fifo_bp_th_u; + +/* Define the union csr_enqc_durf_fifo_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 durf_afull_th : 9; /* [8:0] */ + u32 rsv_50 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_durf_fifo_bp_th_u; + +/* Define the union csr_enqc_wrr_weight0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_weight : 8; /* [7:0] */ + u32 tile_weight : 8; /* [15:8] */ + u32 sm_weight : 8; /* [23:16] */ + u32 rsv_51 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_wrr_weight0_u; + +/* Define the union csr_enqc_wrr_weight1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_weight : 8; /* [7:0] */ + u32 rsv_52 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_wrr_weight1_u; + +/* Define the union csr_enqc_rx_du_len_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_du_len_clr : 1; /* [0] */ + u32 rsv_53 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_du_len_clr_u; + +/* Define the union csr_enqc_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_54 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ecc_bypass_en_u; + +/* Define the union csr_enqc_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_enqc_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_enqc_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_enqc_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_enqc_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_55 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_enqc_host_cmq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_host_cmq_baddr : 17; /* [16:0] */ + u32 rsv_56 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_host_cmq_cnt_baddr_u; + +/* Define the union csr_enqc_soc_lnic_sq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_soc_lnic_sq_baddr : 17; /* [16:0] */ + u32 rsv_57 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_soc_lnic_sq_cnt_baddr_u; + +/* Define the union csr_enqc_soc_lnic_rq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_soc_lnic_rq_baddr : 17; /* [16:0] */ + u32 rsv_58 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_soc_lnic_rq_cnt_baddr_u; + +/* Define the union csr_enqc_soc_cmq_cnt_baddr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_soc_cmq_baddr : 17; /* [16:0] */ + u32 rsv_59 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_soc_cmq_cnt_baddr_u; + +/* Define the union csr_enqc_soc_db_cnt_limit_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_soc_lnic_sq_lim : 9; /* [8:0] */ + u32 rsv_60 : 3; /* [11:9] */ + u32 cnt_soc_lnic_rq_lim : 11; /* [22:12] */ + u32 rsv_61 : 1; /* [23] */ + u32 cnt_soc_cmq_lim : 7; /* [30:24] */ + u32 rsv_62 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_soc_db_cnt_limit_u; + +/* Define the union csr_pass_through_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 passthru_enable : 1; /* [0] */ + u32 rsv_63 : 7; /* [7:1] */ + u32 passthrou_timeout_value : 4; /* [11:8] */ + u32 rsv_64 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pass_through_cfg_u; + +/* Define the union csr_enqc_root_host_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_xon_inmq : 4; /* [3:0] */ + u32 host_xon_infmq : 4; /* [7:4] */ + u32 root_xon_inmq : 1; /* [8] */ + u32 rsv_65 : 3; /* [11:9] */ + u32 root_xon_infmq : 1; /* [12] */ + u32 rsv_66 : 3; /* [15:13] */ + u32 root_xon_total : 1; /* [16] */ + u32 rsv_67 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_root_host_xon_sta_u; + +/* Define the union csr_enqc_hostep_inmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_xon_inmq_h0 : 8; /* [7:0] */ + u32 ep_xon_inmq_h1 : 8; /* [15:8] */ + u32 ep_xon_inmq_h2 : 8; /* [23:16] */ + u32 ep_xon_inmq_h3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_hostep_inmq_xon_sta_u; + +/* Define the union csr_enqc_hostep_infmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_xon_infmq_h0 : 8; /* [7:0] */ + u32 ep_xon_infmq_h1 : 8; /* [15:8] */ + u32 ep_xon_infmq_h2 : 8; /* [23:16] */ + u32 ep_xon_infmq_h3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_hostep_infmq_xon_sta_u; + +/* Define the union csr_enqc_hec_inmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hec_xon_inmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_hec_inmq_xon_sta_u; + +/* Define the union csr_enqc_hec_infmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hec_xon_infmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_hec_infmq_xon_sta_u; + +/* Define the union csr_enqc_que_inmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 que_xon_inmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_que_inmq_xon_sta_u; + +/* Define the union csr_enqc_que_infmq_xon_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 que_xon_infmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_que_infmq_xon_sta_u; + +/* Define the union csr_enqc_flush_qf_emqcnt_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flush_soc_cmd_qf_done : 1; /* [0] */ + u32 flush_host_cmd_qf_done : 1; /* [1] */ + u32 flush_soc_ls_qf_done : 1; /* [2] */ + u32 flush_soc_lr_qf_done : 1; /* [3] */ + u32 flush_host_ls_qf_done : 1; /* [4] */ + u32 flush_host_lr_qf_done : 1; /* [5] */ + u32 flush_sq_qf_done : 1; /* [6] */ + u32 flush_rq_qf_done : 1; /* [7] */ + u32 flush_ucode_qf_done : 1; /* [8] */ + u32 flush_rdma_qf_done : 1; /* [9] */ + u32 flush_emqcnt_done : 1; /* [10] */ + u32 flush_pt_fifo_done : 1; /* [11] */ + u32 rsv_68 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_flush_qf_emqcnt_done_u; + +/* Define the union csr_enqc_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_ecc_1bit_err_cnt_u; + +/* Define the union csr_enqc_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_ecc_2bit_err_cnt_u; + +/* Define the union csr_enqc_rx_du_packet_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_du_pkt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_du_packet_u; + +/* Define the union csr_enqc_rx_du_length_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_du_length : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_du_length_u; + +/* Define the union csr_cpi_in_emqcnt_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_cnt : 5; /* [4:0] */ + u32 rsv_69 : 3; /* [7:5] */ + u32 cpi_full : 1; /* [8] */ + u32 rsv_70 : 3; /* [11:9] */ + u32 cpi_empt : 1; /* [12] */ + u32 rsv_71 : 3; /* [15:13] */ + u32 emqenq_fifo_cnt : 5; /* [20:16] */ + u32 rsv_72 : 3; /* [23:21] */ + u32 emqenq_fifo_full : 1; /* [24] */ + u32 rsv_73 : 3; /* [27:25] */ + u32 emqenq_fifo_empt : 1; /* [28] */ + u32 rsv_74 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpi_in_emqcnt_fifo_status_u; + +/* Define the union csr_sm_in_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_wfifo_cnt : 4; /* [3:0] */ + u32 rsv_75 : 4; /* [7:4] */ + u32 sm_full : 1; /* [8] */ + u32 rsv_76 : 3; /* [11:9] */ + u32 sm_aful : 1; /* [12] */ + u32 rsv_77 : 3; /* [15:13] */ + u32 sm_empt : 1; /* [16] */ + u32 rsv_78 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_in_fifo_status_u; + +/* Define the union csr_tile_qu_in_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tile_wfifo_cnt : 4; /* [3:0] */ + u32 rsv_79 : 4; /* [7:4] */ + u32 tile_full : 1; /* [8] */ + u32 rsv_80 : 3; /* [11:9] */ + u32 tile_empt : 1; /* [12] */ + u32 rsv_81 : 3; /* [15:13] */ + u32 qu_wfifo_cnt : 5; /* [20:16] */ + u32 rsv_82 : 3; /* [23:21] */ + u32 qu_full : 1; /* [24] */ + u32 rsv_83 : 3; /* [27:25] */ + u32 qu_empt : 1; /* [28] */ + u32 rsv_84 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tile_qu_in_fifo_status_u; + +/* Define the union csr_enqc_mrf_du_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mrf_fifo_cnt : 9; /* [8:0] */ + u32 rsv_85 : 3; /* [11:9] */ + u32 mrf_fifo_full : 1; /* [12] */ + u32 mrf_fifo_empt : 1; /* [13] */ + u32 mrf_fifo_aful : 1; /* [14] */ + u32 rsv_86 : 1; /* [15] */ + u32 durf_fifo_cnt : 9; /* [24:16] */ + u32 rsv_87 : 3; /* [27:25] */ + u32 durf_fifo_full : 1; /* [28] */ + u32 durf_fifo_empt : 1; /* [29] */ + u32 durf_fifo_aful : 1; /* [30] */ + u32 rsv_88 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_mrf_du_fifo_status_u; + +/* Define the union csr_enqc_passthru_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 passthru_fifo_cnt : 5; /* [4:0] */ + u32 rsv_89 : 3; /* [7:5] */ + u32 passthru_fifo_dfx : 2; /* [9:8] */ + u32 rsv_90 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_passthru_fifo_status_u; + +/* Define the union csr_enqc_input_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_cpi_db_bp : 1; /* [0] */ + u32 rsv_91 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_input_bp_u; + +/* Define the union csr_enqc_eqm_qd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_eqm_qd_cnt : 23; /* [22:0] */ + u32 rsv_92 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_eqm_qd_cnt_u; + +/* Define the union csr_enqc_rx_cpi_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_cpi_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_cpi_pkt_cnt_u; + +/* Define the union csr_enqc_rx_sm_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_sm_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_sm_pkt_cnt_u; + +/* Define the union csr_enqc_rx_tile_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_tile_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_tile_pkt_cnt_u; + +/* Define the union csr_enqc_rx_qu_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_qu_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_qu_pkt_cnt_u; + +/* Define the union csr_enqc_dis_cpi_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_dis_cpi_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_dis_cpi_cnt_u; + +/* Define the union csr_enqc_rx_ring_err_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_ring_err_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_ring_err_db_cnt_u; + +/* Define the union csr_enqc_enq_iqm_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq_iqm_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_enq_iqm_cnt_u; + +/* Define the union csr_enqc_enq_eqm_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq_eqm_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_enq_eqm_cnt_u; + +/* Define the union csr_enqc_filterd_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_filterd_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_filterd_db_cnt_u; + +/* Define the union csr_enqc_rx_sm_cp_sge_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_cp_sge_crdt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_sm_cp_sge_crdt_u; + +/* Define the union csr_enqc_rx_sm_dp_sge_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_dp_sge_crdt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_sm_dp_sge_crdt_u; + +/* Define the union csr_enqc_rx_sm_cp_data_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_cp_data_crdt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_sm_cp_data_crdt_u; + +/* Define the union csr_enqc_rx_sm_dp_data_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_dp_data_crdt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_sm_dp_data_crdt_u; + +/* Define the union csr_enqc_rx_dp_nofl_db_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_rx_dp_nofl_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_enqc_rx_dp_nofl_db_u; + +/* Define the union csr_db_ovfl_vf_range_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 db_ovfl_vf_range_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_db_ovfl_vf_range_cnt_u; + +/* Define the union csr_nonf_db_num_ovfl_thr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nonf_db_num_ovfl_thr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nonf_db_num_ovfl_thr_cnt_u; + +/* Define the union csr_mqm_err_typ_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_err_typ_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mqm_err_typ_db_cnt_u; + +/* Define the union csr_pass_through_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 passthru_fsm : 2; /* [1:0] */ + u32 rsv_93 : 2; /* [3:2] */ + u32 passthru_fifo_status : 2; /* [5:4] */ + u32 rsv_94 : 10; /* [15:6] */ + u32 iqm_enqc_inner_empt : 1; /* [16] */ + u32 eqm_enqc_outer_empt : 1; /* [17] */ + u32 enqc_passthru_pipe_empt : 1; /* [18] */ + u32 rsv_95 : 1; /* [19] */ + u32 iqm_enqc_inner_bp : 1; /* [20] */ + u32 qu_mqm_underload : 1; /* [21] */ + u32 rsv_96 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pass_through_sta_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_enqc_rw_rsv0_u enqc_rw_rsv0; /* 0 */ + volatile csr_enqc_rw_rsv1_u enqc_rw_rsv1; /* 4 */ + volatile csr_enqc_rw_rsv2_u enqc_rw_rsv2; /* 8 */ + volatile csr_enqc_rw_rsv3_u enqc_rw_rsv3; /* C */ + volatile csr_enqc_indrect_ctrl_u enqc_indrect_ctrl; /* 10 */ + volatile csr_enqc_indrect_timeout_u enqc_indrect_timeout; /* 14 */ + volatile csr_enqc_indrect_data_0_u enqc_indrect_data_0; /* 18 */ + volatile csr_enqc_indrect_data_1_u enqc_indrect_data_1; /* 1C */ + volatile csr_enqc_int_vector_u enqc_int_vector; /* 20 */ + volatile csr_enqc_int_u enqc_int; /* 24 */ + volatile csr_enqc_int_en_u enqc_int_en; /* 28 */ + volatile csr_enqc_mem_ecc_err0_u enqc_mem_ecc_err0; /* 2C */ + volatile csr_enqc_mem_ecc_err1_u enqc_mem_ecc_err1; /* 30 */ + volatile csr_table_rd_invld_int_u table_rd_invld_int; /* 34 */ + volatile csr_vfpf_to_host_id_int_u vfpf_to_host_id_int; /* 38 */ + volatile csr_qu_enqc_db_if_int_u qu_enqc_db_if_int; /* 3C */ + volatile csr_cpi_discard_int_u cpi_discard_int; /* 40 */ + volatile csr_enqc_fifo_int_u enqc_fifo_int; /* 44 */ + volatile csr_enqc_fifo_int_en_u enqc_fifo_int_en; /* 48 */ + volatile csr_enqc_qf_int_u enqc_qf_int; /* 4C */ + volatile csr_rx_ring_e0_err_int_u rx_ring_e0_err_int; /* 50 */ + volatile csr_rx_ring_e1_err_int_u rx_ring_e1_err_int; /* 54 */ + volatile csr_enqc_txqid_ovfl_vf_range_int_u enqc_txqid_ovfl_vf_range_int; /* 58 */ + volatile csr_enqc_nonf_num_ovfl_thr_int_u enqc_nonf_num_ovfl_thr_int; /* 5C */ + volatile csr_enqc_err_typ_db_int_u enqc_err_typ_db_int; /* 60 */ + volatile csr_enqc_mem_ecc_req0_u enqc_mem_ecc_req0; /* 80 */ + volatile csr_enqc_mem_ecc_req1_u enqc_mem_ecc_req1; /* 84 */ + volatile csr_enqc_qu_db_if_uncrt_int_en_u enqc_qu_db_if_uncrt_int_en; /* 88 */ + volatile csr_enqc_uncrt_int_en_u enqc_uncrt_int_en; /* 8C */ + volatile csr_enqc_sendq_base_addr_u enqc_sendq_base_addr; /* B0 */ + volatile csr_enqc_sendq_scope_u enqc_sendq_scope; /* B4 */ + volatile csr_enqc_taskio_base_addr_u enqc_taskio_base_addr; /* B8 */ + volatile csr_enqc_taskio_scope_u enqc_taskio_scope; /* BC */ + volatile csr_enqc_rdma_base_addr_u enqc_rdma_base_addr; /* C0 */ + volatile csr_enqc_rdma_scope_u enqc_rdma_scope; /* C4 */ + volatile csr_enqc_ftxqid_base_addr_u enqc_ftxqid_base_addr; /* C8 */ + volatile csr_enqc_ftxqid_scope_u enqc_ftxqid_scope; /* CC */ + volatile csr_enqc_utxqid_base_addr_u enqc_utxqid_base_addr; /* D0 */ + volatile csr_enqc_utxqid_scope_u enqc_utxqid_scope; /* D4 */ + volatile csr_soc_pf_base_lnic_u soc_pf_base_lnic[8]; /* D8 */ + volatile csr_soc_pf_range_lnic_u soc_pf_range_lnic[8]; /* F8 */ + volatile csr_enqc_host_lnic_sq_cnt_baddr_u enqc_host_lnic_sq_cnt_baddr; /* 118 */ + volatile csr_enqc_host_lnic_sq_cnt_limit_u enqc_host_lnic_sq_cnt_limit; /* 11C */ + volatile csr_enqc_host_lnic_rq_cnt_baddr_u enqc_host_lnic_rq_cnt_baddr; /* 120 */ + volatile csr_enqc_host_lnic_rq_cnt_limit_u enqc_host_lnic_rq_cnt_limit; /* 124 */ + volatile csr_enqc_sq_cnt_baddr_u enqc_sq_cnt_baddr; /* 128 */ + volatile csr_enqc_sq_cnt_limit_u enqc_sq_cnt_limit; /* 12C */ + volatile csr_enqc_host_cmq_cnt_limit_u enqc_host_cmq_cnt_limit; /* 130 */ + volatile csr_enqc_pf_range_portx_u enqc_pf_range_portx[5]; /* 134 */ + volatile csr_enqc_vf_range_portx_u enqc_vf_range_portx[4]; /* 148 */ + volatile csr_enqc_lvf_range_portx_u enqc_lvf_range_portx[4]; /* 158 */ + volatile csr_enqc_enqc_cfg_u enqc_enqc_cfg; /* 168 */ + volatile csr_soc_stateful_db_map_hid_u soc_stateful_db_map_hid; /* 16C */ + volatile csr_enqc_in_fifo_gap_u enqc_in_fifo_gap; /* 170 */ + volatile csr_enqc_eqm_pt_fifo_gap_u enqc_eqm_pt_fifo_gap; /* 174 */ + volatile csr_enqc_mrf_fifo_bp_th_u enqc_mrf_fifo_bp_th; /* 178 */ + volatile csr_enqc_durf_fifo_bp_th_u enqc_durf_fifo_bp_th; /* 17C */ + volatile csr_enqc_wrr_weight0_u enqc_wrr_weight0; /* 180 */ + volatile csr_enqc_wrr_weight1_u enqc_wrr_weight1; /* 184 */ + volatile csr_enqc_rx_du_len_clr_u enqc_rx_du_len_clr; /* 188 */ + volatile csr_enqc_mem_ecc_bypass_en_u enqc_mem_ecc_bypass_en; /* 18C */ + volatile csr_enqc_mem_ctrl_bus_cfg0_u enqc_mem_ctrl_bus_cfg0; /* 190 */ + volatile csr_enqc_mem_ctrl_bus_cfg1_u enqc_mem_ctrl_bus_cfg1; /* 194 */ + volatile csr_enqc_mem_ctrl_bus_cfg2_u enqc_mem_ctrl_bus_cfg2; /* 198 */ + volatile csr_enqc_mem_ctrl_bus_cfg3_u enqc_mem_ctrl_bus_cfg3; /* 19C */ + volatile csr_enqc_mem_ctrl_bus_cfg4_u enqc_mem_ctrl_bus_cfg4; /* 1A0 */ + volatile csr_enqc_host_cmq_cnt_baddr_u enqc_host_cmq_cnt_baddr; /* 1A4 */ + volatile csr_enqc_soc_lnic_sq_cnt_baddr_u enqc_soc_lnic_sq_cnt_baddr; /* 1A8 */ + volatile csr_enqc_soc_lnic_rq_cnt_baddr_u enqc_soc_lnic_rq_cnt_baddr; /* 1AC */ + volatile csr_enqc_soc_cmq_cnt_baddr_u enqc_soc_cmq_cnt_baddr; /* 1B0 */ + volatile csr_enqc_soc_db_cnt_limit_u enqc_soc_db_cnt_limit; /* 1B4 */ + volatile csr_pass_through_cfg_u pass_through_cfg; /* 1B8 */ + volatile csr_enqc_root_host_xon_sta_u enqc_root_host_xon_sta; /* 1C0 */ + volatile csr_enqc_hostep_inmq_xon_sta_u enqc_hostep_inmq_xon_sta; /* 1C4 */ + volatile csr_enqc_hostep_infmq_xon_sta_u enqc_hostep_infmq_xon_sta; /* 1C8 */ + volatile csr_enqc_hec_inmq_xon_sta_u enqc_hec_inmq_xon_sta[8]; /* 1CC */ + volatile csr_enqc_hec_infmq_xon_sta_u enqc_hec_infmq_xon_sta[8]; /* 1EC */ + volatile csr_enqc_que_inmq_xon_sta_u enqc_que_inmq_xon_sta[256]; /* 20C */ + volatile csr_enqc_que_infmq_xon_sta_u enqc_que_infmq_xon_sta[128]; /* 60C */ + volatile csr_enqc_flush_qf_emqcnt_done_u enqc_flush_qf_emqcnt_done; /* 80C */ + volatile csr_enqc_ecc_1bit_err_cnt_u enqc_ecc_1bit_err_cnt; /* 810 */ + volatile csr_enqc_ecc_2bit_err_cnt_u enqc_ecc_2bit_err_cnt; /* 814 */ + volatile csr_enqc_rx_du_packet_u enqc_rx_du_packet; /* 830 */ + volatile csr_enqc_rx_du_length_u enqc_rx_du_length; /* 834 */ + volatile csr_cpi_in_emqcnt_fifo_status_u cpi_in_emqcnt_fifo_status; /* 838 */ + volatile csr_sm_in_fifo_status_u sm_in_fifo_status; /* 83C */ + volatile csr_tile_qu_in_fifo_status_u tile_qu_in_fifo_status; /* 840 */ + volatile csr_enqc_mrf_du_fifo_status_u enqc_mrf_du_fifo_status; /* 844 */ + volatile csr_enqc_passthru_fifo_status_u enqc_passthru_fifo_status; /* 848 */ + volatile csr_enqc_input_bp_u enqc_input_bp; /* 84C */ + volatile csr_enqc_eqm_qd_cnt_u enqc_eqm_qd_cnt; /* 850 */ + volatile csr_enqc_rx_cpi_pkt_cnt_u enqc_rx_cpi_pkt_cnt; /* 854 */ + volatile csr_enqc_rx_sm_pkt_cnt_u enqc_rx_sm_pkt_cnt; /* 858 */ + volatile csr_enqc_rx_tile_pkt_cnt_u enqc_rx_tile_pkt_cnt; /* 85C */ + volatile csr_enqc_rx_qu_pkt_cnt_u enqc_rx_qu_pkt_cnt; /* 860 */ + volatile csr_enqc_dis_cpi_cnt_u enqc_dis_cpi_cnt; /* 864 */ + volatile csr_enqc_rx_ring_err_db_cnt_u enqc_rx_ring_err_db_cnt; /* 868 */ + volatile csr_enqc_enq_iqm_cnt_u enqc_enq_iqm_cnt; /* 86C */ + volatile csr_enqc_enq_eqm_cnt_u enqc_enq_eqm_cnt; /* 870 */ + volatile csr_enqc_filterd_db_cnt_u enqc_filterd_db_cnt; /* 874 */ + volatile csr_enqc_rx_sm_cp_sge_crdt_u enqc_rx_sm_cp_sge_crdt; /* 878 */ + volatile csr_enqc_rx_sm_dp_sge_crdt_u enqc_rx_sm_dp_sge_crdt; /* 87C */ + volatile csr_enqc_rx_sm_cp_data_crdt_u enqc_rx_sm_cp_data_crdt; /* 880 */ + volatile csr_enqc_rx_sm_dp_data_crdt_u enqc_rx_sm_dp_data_crdt; /* 884 */ + volatile csr_enqc_rx_dp_nofl_db_u enqc_rx_dp_nofl_db; /* 888 */ + volatile csr_db_ovfl_vf_range_cnt_u db_ovfl_vf_range_cnt; /* 88C */ + volatile csr_nonf_db_num_ovfl_thr_cnt_u nonf_db_num_ovfl_thr_cnt; /* 890 */ + volatile csr_mqm_err_typ_db_cnt_u mqm_err_typ_db_cnt; /* 894 */ + volatile csr_pass_through_sta_u pass_through_sta; /* 898 */ +} S_mqm_enqc_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_enqc */ +extern volatile S_mqm_enqc_REGS_TYPE *gopmqm_enqcAllReg; + +/* Declare the functions that set the member value */ +int iSetENQC_RW_RSV0_enqc_rw_rsv0(unsigned int uenqc_rw_rsv0); +int iSetENQC_RW_RSV1_enqc_rw_rsv1(unsigned int uenqc_rw_rsv1); +int iSetENQC_RW_RSV2_enqc_rw_rsv2(unsigned int uenqc_rw_rsv2); +int iSetENQC_RW_RSV3_enqc_rw_rsv3(unsigned int uenqc_rw_rsv3); +int iSetENQC_INDRECT_CTRL_enqc_indrect_addr(unsigned int uenqc_indrect_addr); +int iSetENQC_INDRECT_CTRL_enqc_indrect_tab(unsigned int uenqc_indrect_tab); +int iSetENQC_INDRECT_CTRL_enqc_indrect_status(unsigned int uenqc_indrect_status); +int iSetENQC_INDRECT_CTRL_enqc_indrect_mode(unsigned int uenqc_indrect_mode); +int iSetENQC_INDRECT_CTRL_enqc_indrect_vld(unsigned int uenqc_indrect_vld); +int iSetENQC_INDRECT_TIMEOUT_enqc_indrect_timeout(unsigned int uenqc_indrect_timeout); +int iSetENQC_INDRECT_DATA_0_enqc_indrect_data_0(unsigned int uenqc_indrect_data_0); +int iSetENQC_INDRECT_DATA_1_enqc_indrect_data_1(unsigned int uenqc_indrect_data_1); +int iSetENQC_INT_VECTOR_enqc_cpi_int_index(unsigned int uenqc_cpi_int_index); +int iSetENQC_INT_VECTOR_enqc_enable(unsigned int uenqc_enable); +int iSetENQC_INT_VECTOR_enqc_int_issue(unsigned int uenqc_int_issue); +int iSetENQC_INT_enqc_int_data(unsigned int uenqc_int_data); +int iSetENQC_INT_enqc_program_csr_id_ro(unsigned int uenqc_program_csr_id_ro); +int iSetENQC_INT_EN_enqc_int_en(unsigned int uenqc_int_en); +int iSetENQC_INT_EN_enqc_program_csr_id(unsigned int uenqc_program_csr_id); +int iSetENQC_MEM_ECC_ERR0_enqc_ecc0_err(unsigned int uenqc_ecc0_err); +int iSetENQC_MEM_ECC_ERR0_enqc_ecc0_err_insert(unsigned int uenqc_ecc0_err_insert); +int iSetENQC_MEM_ECC_ERR0_enqc_ecc0_err_info(unsigned int uenqc_ecc0_err_info); +int iSetENQC_MEM_ECC_ERR1_enqc_ecc1_err(unsigned int uenqc_ecc1_err); +int iSetENQC_MEM_ECC_ERR1_enqc_ecc1_err_insert(unsigned int uenqc_ecc1_err_insert); +int iSetENQC_MEM_ECC_ERR1_enqc_ecc1_err_info(unsigned int uenqc_ecc1_err_info); +int iSetTABLE_RD_INVLD_INT_table_rd_err(unsigned int utable_rd_err); +int iSetTABLE_RD_INVLD_INT_table_rd_err_insert(unsigned int utable_rd_err_insert); +int iSetTABLE_RD_INVLD_INT_table_rd_err_info(unsigned int utable_rd_err_info); +int iSetVFPF_TO_HOST_ID_INT_vfpf_hid_err(unsigned int uvfpf_hid_err); +int iSetVFPF_TO_HOST_ID_INT_vfpf_hid_err_insert(unsigned int uvfpf_hid_err_insert); +int iSetVFPF_TO_HOST_ID_INT_vfpf_hid_err_info(unsigned int uvfpf_hid_err_info); +int iSetQU_ENQC_DB_IF_INT_qu_enqc_db_interface_err(unsigned int uqu_enqc_db_interface_err); +int iSetQU_ENQC_DB_IF_INT_qu_enqc_db_interface_err_insert(unsigned int uqu_enqc_db_interface_err_insert); +int iSetQU_ENQC_DB_IF_INT_qu_enqc_db_interface_err_info(unsigned int uqu_enqc_db_interface_err_info); +int iSetCPI_DISCARD_INT_cpi_discard_int_err(unsigned int ucpi_discard_int_err); +int iSetCPI_DISCARD_INT_cpi_discard_int_err_insert(unsigned int ucpi_discard_int_err_insert); +int iSetCPI_DISCARD_INT_cpi_discard_int_err_info(unsigned int ucpi_discard_int_err_info); +int iSetENQC_FIFO_INT_cpi_fifo_wr_ovfl_int_err(unsigned int ucpi_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_cpi_fifo_wr_ovfl_int_err_insert(unsigned int ucpi_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_tile_fifo_wr_ovfl_int_err(unsigned int utile_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_tile_fifo_wr_ovfl_int_err_insert(unsigned int utile_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_sm_fifo_wr_ovfl_int_err(unsigned int usm_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_sm_fifo_wr_ovfl_int_err_insert(unsigned int usm_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_mrf_fifo_wr_ovfl_int_err(unsigned int umrf_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_mrf_fifo_wr_ovfl_int_err_insert(unsigned int umrf_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_dul_fifo_wr_ovfl_int_err(unsigned int udul_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_dul_fifo_wr_ovfl_int_err_insert(unsigned int udul_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_emq_enq_fifo_wr_ovfl_int_err(unsigned int uemq_enq_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_emq_enq_fifo_wr_ovfl_int_err_insert(unsigned int uemq_enq_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_cpi_fifo_rd_udfl_int_err(unsigned int ucpi_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_cpi_fifo_rd_udfl_int_err_insert(unsigned int ucpi_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_emq_enq_fifo_rd_udfl_int_err(unsigned int uemq_enq_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_emq_enq_fifo_rd_udfl_int_err_insert(unsigned int uemq_enq_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_passthru_fifo_rd_udfl_int_err(unsigned int upassthru_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_passthru_fifo_rd_udfl_int_err_insert(unsigned int upassthru_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_passthru_fifo_wr_ovfl_int_err(unsigned int upassthru_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_passthru_fifo_wr_ovfl_int_err_insert(unsigned int upassthru_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_qu_fifo_wr_ovfl_int_err(unsigned int uqu_fifo_wr_ovfl_int_err); +int iSetENQC_FIFO_INT_qu_fifo_wr_ovfl_int_err_insert(unsigned int uqu_fifo_wr_ovfl_int_err_insert); +int iSetENQC_FIFO_INT_qu_fifo_rd_udfl_int_err(unsigned int uqu_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_qu_fifo_rd_udfl_int_err_insert(unsigned int uqu_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_tile_fifo_rd_udfl_int_err(unsigned int utile_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_tile_fifo_rd_udfl_int_err_insert(unsigned int utile_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_sm_fifo_rd_udfl_int_err(unsigned int usm_fifo_rd_udfl_int_err); +int iSetENQC_FIFO_INT_sm_fifo_rd_udfl_int_err_insert(unsigned int usm_fifo_rd_udfl_int_err_insert); +int iSetENQC_FIFO_INT_EN_cpi_fifo_wr_ovfl_int_err_en(unsigned int ucpi_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_tile_fifo_wr_ovfl_int_err_en(unsigned int utile_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_sm_fifo_wr_ovfl_int_err_en(unsigned int usm_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_mrf_fifo_wr_ovfl_int_err_en(unsigned int umrf_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_dul_fifo_wr_ovfl_int_err_en(unsigned int udul_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_emq_enq_fifo_wr_ovfl_int_err_en(unsigned int uemq_enq_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_cpi_fifo_rd_udfl_int_err_en(unsigned int ucpi_fifo_rd_udfl_int_err_en); +int iSetENQC_FIFO_INT_EN_emq_enq_fifo_rd_udfl_int_err_en(unsigned int uemq_enq_fifo_rd_udfl_int_err_en); +int iSetENQC_FIFO_INT_EN_passthru_fifo_rd_udfl_int_err_en(unsigned int upassthru_fifo_rd_udfl_int_err_en); +int iSetENQC_FIFO_INT_EN_passthru_fifo_wr_ovfl_int_err_en(unsigned int upassthru_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_qu_fifo_rd_udfl_int_err_en(unsigned int uqu_fifo_rd_udfl_int_err_en); +int iSetENQC_FIFO_INT_EN_qu_fifo_wr_ovfl_int_err_en(unsigned int uqu_fifo_wr_ovfl_int_err_en); +int iSetENQC_FIFO_INT_EN_tile_fifo_rd_udfl_int_err_en(unsigned int utile_fifo_rd_udfl_int_err_en); +int iSetENQC_FIFO_INT_EN_sm_fifo_rd_udfl_int_err_en(unsigned int usm_fifo_rd_udfl_int_err_en); +int iSetENQC_QF_INT_enqc_qf_int_err(unsigned int uenqc_qf_int_err); +int iSetENQC_QF_INT_enqc_qf_int_err_insert(unsigned int uenqc_qf_int_err_insert); +int iSetENQC_QF_INT_enqc_qf_int_err_info(unsigned int uenqc_qf_int_err_info); +int iSetRX_RING_E0_ERR_INT_ring_e0_err(unsigned int uring_e0_err); +int iSetRX_RING_E0_ERR_INT_ring_e0_err_insert(unsigned int uring_e0_err_insert); +int iSetRX_RING_E0_ERR_INT_ring_e0_err_info(unsigned int uring_e0_err_info); +int iSetRX_RING_E1_ERR_INT_ring_e1_err(unsigned int uring_e1_err); +int iSetRX_RING_E1_ERR_INT_ring_e1_err_insert(unsigned int uring_e1_err_insert); +int iSetRX_RING_E1_ERR_INT_ring_e1_err_info(unsigned int uring_e1_err_info); +int iSetENQC_TXQID_OVFL_VF_RANGE_INT_txqid_ovfl_vf_range_int_err(unsigned int utxqid_ovfl_vf_range_int_err); +int iSetENQC_TXQID_OVFL_VF_RANGE_INT_txqid_ovfl_vf_range_int_err_insert( + unsigned int utxqid_ovfl_vf_range_int_err_insert); +int iSetENQC_TXQID_OVFL_VF_RANGE_INT_txqid_ovfl_vf_range_int_err_info(unsigned int utxqid_ovfl_vf_range_int_err_info); +int iSetENQC_NONF_NUM_OVFL_THR_INT_nonf_num_ovfl_err(unsigned int unonf_num_ovfl_err); +int iSetENQC_NONF_NUM_OVFL_THR_INT_nonf_num_ovfl_err_insert(unsigned int unonf_num_ovfl_err_insert); +int iSetENQC_NONF_NUM_OVFL_THR_INT_nonf_num_ovfl_err_info(unsigned int unonf_num_ovfl_err_info); +int iSetENQC_ERR_TYP_DB_INT_db_type_err(unsigned int udb_type_err); +int iSetENQC_ERR_TYP_DB_INT_db_type_err_insert(unsigned int udb_type_err_insert); +int iSetENQC_ERR_TYP_DB_INT_db_type_err_info(unsigned int udb_type_err_info); +int iSetENQC_MEM_ECC_REQ0_vfp1_mem_ecc_req(unsigned int uvfp1_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_vfp2_mem_ecc_req(unsigned int uvfp2_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_vfp3_mem_ecc_req(unsigned int uvfp3_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_vfr_mem_ecc_req(unsigned int uvfr_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_vf2nmq_mem_ecc_req(unsigned int uvf2nmq_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_vf2nfmq_mem_ecc_req(unsigned int uvf2nfmq_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_emq_cnt_mem_ecc_req(unsigned int uemq_cnt_mem_ecc_req); +int iSetENQC_MEM_ECC_REQ0_durf_fifo_a_mem_err_req(unsigned int udurf_fifo_a_mem_err_req); +int iSetENQC_MEM_ECC_REQ0_durf_fifo_b_mem_err_req(unsigned int udurf_fifo_b_mem_err_req); +int iSetENQC_MEM_ECC_REQ0_mrf_fifo_a_mem_err_req(unsigned int umrf_fifo_a_mem_err_req); +int iSetENQC_MEM_ECC_REQ0_mrf_fifo_b_mem_err_req(unsigned int umrf_fifo_b_mem_err_req); +int iSetENQC_MEM_ECC_REQ0_vf_pi_baddr_lim_mem_err_req(unsigned int uvf_pi_baddr_lim_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf2ep_mem_err_req(unsigned int uvf2ep_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf_range1_mem_err_req(unsigned int uvf_range1_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf_range2_mem_err_req(unsigned int uvf_range2_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf_range3_mem_err_req(unsigned int uvf_range3_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf_nonflt_thr_mem_err_req(unsigned int uvf_nonflt_thr_mem_err_req); +int iSetENQC_MEM_ECC_REQ1_vf_nonflt_cnt_mem_err_req(unsigned int uvf_nonflt_cnt_mem_err_req); +int iSetENQC_QU_DB_IF_UNCRT_INT_EN_qu_enqc_db_if_err_en(unsigned int uqu_enqc_db_if_err_en); +int iSetENQC_UNCRT_INT_EN_qf_clr_err_uncrt_int_en(unsigned int uqf_clr_err_uncrt_int_en); +int iSetENQC_UNCRT_INT_EN_rx_ring_e1_uncrt_int_en(unsigned int urx_ring_e1_uncrt_int_en); +int iSetENQC_UNCRT_INT_EN_rx_ring_e0_uncrt_int_en(unsigned int urx_ring_e0_uncrt_int_en); +int iSetENQC_SENDQ_BASE_ADDR_flt_stxq_baddr(unsigned int uflt_stxq_baddr); +int iSetENQC_SENDQ_SCOPE_flt_stxq_lim(unsigned int uflt_stxq_lim); +int iSetENQC_TASKIO_BASE_ADDR_flt_ttxq_baddr(unsigned int uflt_ttxq_baddr); +int iSetENQC_TASKIO_SCOPE_flt_ttxq_lim(unsigned int uflt_ttxq_lim); +int iSetENQC_RDMA_BASE_ADDR_flt_rtxq_baddr(unsigned int uflt_rtxq_baddr); +int iSetENQC_RDMA_SCOPE_flt_rtxq_lim(unsigned int uflt_rtxq_lim); +int iSetENQC_FTXQID_BASE_ADDR_flt_ftxq_baddr(unsigned int uflt_ftxq_baddr); +int iSetENQC_FTXQID_SCOPE_flt_ftxq_lim(unsigned int uflt_ftxq_lim); +int iSetENQC_UTXQID_BASE_ADDR_flt_utxq_baddr(unsigned int uflt_utxq_baddr); +int iSetENQC_UTXQID_SCOPE_flt_utxq_lim(unsigned int uflt_utxq_lim); +int iSetSOC_PF_BASE_LNIC_pf_base_lnic_sq_soc(unsigned int upf_base_lnic_sq_soc); +int iSetSOC_PF_BASE_LNIC_pf_base_lnic_rq_soc(unsigned int upf_base_lnic_rq_soc); +int iSetSOC_PF_RANGE_LNIC_pf_range_dat_lnic_sq_soc(unsigned int upf_range_dat_lnic_sq_soc); +int iSetSOC_PF_RANGE_LNIC_pf_range_dat_lnic_rq_soc(unsigned int upf_range_dat_lnic_rq_soc); +int iSetENQC_HOST_LNIC_SQ_CNT_BADDR_cnt_host_lnic_sq_baddr(unsigned int ucnt_host_lnic_sq_baddr); +int iSetENQC_HOST_LNIC_SQ_CNT_LIMIT_cnt_host_lnic_sq_lim(unsigned int ucnt_host_lnic_sq_lim); +int iSetENQC_HOST_LNIC_RQ_CNT_BADDR_cnt_host_lnic_rq_baddr(unsigned int ucnt_host_lnic_rq_baddr); +int iSetENQC_HOST_LNIC_RQ_CNT_LIMIT_cnt_host_lnic_rq_lim(unsigned int ucnt_host_lnic_rq_lim); +int iSetENQC_SQ_CNT_BADDR_cnt_send_baddr(unsigned int ucnt_send_baddr); +int iSetENQC_SQ_CNT_LIMIT_cnt_send_lim(unsigned int ucnt_send_lim); +int iSetENQC_HOST_CMQ_CNT_LIMIT_cnt_host_cmq_lim(unsigned int ucnt_host_cmq_lim); +int iSetENQC_PF_RANGE_PORTX_portx_pf_func_idx_l(unsigned int uportx_pf_func_idx_l); +int iSetENQC_PF_RANGE_PORTX_portx_pf_func_idx_h(unsigned int uportx_pf_func_idx_h); +int iSetENQC_PF_RANGE_PORTX_portx_pf_func_idx_v(unsigned int uportx_pf_func_idx_v); +int iSetENQC_VF_RANGE_PORTX_portx_vf_func_idx_l(unsigned int uportx_vf_func_idx_l); +int iSetENQC_VF_RANGE_PORTX_portx_vf_func_idx_h(unsigned int uportx_vf_func_idx_h); +int iSetENQC_VF_RANGE_PORTX_portx_vf_func_idx_v(unsigned int uportx_vf_func_idx_v); +int iSetENQC_LVF_RANGE_PORTX_portx_lvf_func_idx_l(unsigned int uportx_lvf_func_idx_l); +int iSetENQC_LVF_RANGE_PORTX_portx_lvf_func_idx_h(unsigned int uportx_lvf_func_idx_h); +int iSetENQC_LVF_RANGE_PORTX_portx_lvf_func_idx_v(unsigned int uportx_lvf_func_idx_v); +int iSetENQC_ENQC_CFG_enqc_enq2emq_cfg(unsigned int uenqc_enq2emq_cfg); +int iSetENQC_ENQC_CFG_enqc_qf_rdma_half_cfg(unsigned int uenqc_qf_rdma_half_cfg); +int iSetENQC_ENQC_CFG_cpi_discard_en(unsigned int ucpi_discard_en); +int iSetENQC_ENQC_CFG_rx_du_length_unit(unsigned int urx_du_length_unit); +int iSetSOC_STATEFUL_DB_MAP_HID_soc_stateful_db_map_hid(unsigned int usoc_stateful_db_map_hid); +int iSetSOC_STATEFUL_DB_MAP_HID_soc_stateful_db_map_vld(unsigned int usoc_stateful_db_map_vld); +int iSetENQC_IN_FIFO_GAP_cpi_aful_gap(unsigned int ucpi_aful_gap); +int iSetENQC_IN_FIFO_GAP_tile_aful_gap(unsigned int utile_aful_gap); +int iSetENQC_IN_FIFO_GAP_qu_aful_gap(unsigned int uqu_aful_gap); +int iSetENQC_IN_FIFO_GAP_sm_aful_gap(unsigned int usm_aful_gap); +int iSetENQC_EQM_PT_FIFO_GAP_passthru_fifo_aful_gap(unsigned int upassthru_fifo_aful_gap); +int iSetENQC_EQM_PT_FIFO_GAP_emq_enq_fifo_afull_gap(unsigned int uemq_enq_fifo_afull_gap); +int iSetENQC_MRF_FIFO_BP_TH_mrf_afull_th(unsigned int umrf_afull_th); +int iSetENQC_DURF_FIFO_BP_TH_durf_afull_th(unsigned int udurf_afull_th); +int iSetENQC_WRR_WEIGHT0_cpi_weight(unsigned int ucpi_weight); +int iSetENQC_WRR_WEIGHT0_tile_weight(unsigned int utile_weight); +int iSetENQC_WRR_WEIGHT0_sm_weight(unsigned int usm_weight); +int iSetENQC_WRR_WEIGHT1_qu_weight(unsigned int uqu_weight); +int iSetENQC_RX_DU_LEN_CLR_enqc_rx_du_len_clr(unsigned int uenqc_rx_du_len_clr); +int iSetENQC_MEM_ECC_BYPASS_EN_enqc_mem_ecc_bypass(unsigned int uenqc_mem_ecc_bypass); +int iSetENQC_MEM_CTRL_BUS_CFG0_enqc_mem_ctrl_bus_0(unsigned int uenqc_mem_ctrl_bus_0); +int iSetENQC_MEM_CTRL_BUS_CFG1_enqc_mem_ctrl_bus_1(unsigned int uenqc_mem_ctrl_bus_1); +int iSetENQC_MEM_CTRL_BUS_CFG2_enqc_mem_ctrl_bus_2(unsigned int uenqc_mem_ctrl_bus_2); +int iSetENQC_MEM_CTRL_BUS_CFG3_enqc_mem_ctrl_bus_3(unsigned int uenqc_mem_ctrl_bus_3); +int iSetENQC_MEM_CTRL_BUS_CFG4_enqc_mem_ctrl_bus_4(unsigned int uenqc_mem_ctrl_bus_4); +int iSetENQC_HOST_CMQ_CNT_BADDR_cnt_host_cmq_baddr(unsigned int ucnt_host_cmq_baddr); +int iSetENQC_SOC_LNIC_SQ_CNT_BADDR_cnt_soc_lnic_sq_baddr(unsigned int ucnt_soc_lnic_sq_baddr); +int iSetENQC_SOC_LNIC_RQ_CNT_BADDR_cnt_soc_lnic_rq_baddr(unsigned int ucnt_soc_lnic_rq_baddr); +int iSetENQC_SOC_CMQ_CNT_BADDR_cnt_soc_cmq_baddr(unsigned int ucnt_soc_cmq_baddr); +int iSetENQC_SOC_DB_CNT_LIMIT_cnt_soc_lnic_sq_lim(unsigned int ucnt_soc_lnic_sq_lim); +int iSetENQC_SOC_DB_CNT_LIMIT_cnt_soc_lnic_rq_lim(unsigned int ucnt_soc_lnic_rq_lim); +int iSetENQC_SOC_DB_CNT_LIMIT_cnt_soc_cmq_lim(unsigned int ucnt_soc_cmq_lim); +int iSetPASS_THROUGH_CFG_passthru_enable(unsigned int upassthru_enable); +int iSetPASS_THROUGH_CFG_passthrou_timeout_value(unsigned int upassthrou_timeout_value); +int iSetENQC_ROOT_HOST_XON_STA_host_xon_inmq(unsigned int uhost_xon_inmq); +int iSetENQC_ROOT_HOST_XON_STA_host_xon_infmq(unsigned int uhost_xon_infmq); +int iSetENQC_ROOT_HOST_XON_STA_root_xon_inmq(unsigned int uroot_xon_inmq); +int iSetENQC_ROOT_HOST_XON_STA_root_xon_infmq(unsigned int uroot_xon_infmq); +int iSetENQC_ROOT_HOST_XON_STA_root_xon_total(unsigned int uroot_xon_total); +int iSetENQC_HOSTEP_INMQ_XON_STA_ep_xon_inmq_h0(unsigned int uep_xon_inmq_h0); +int iSetENQC_HOSTEP_INMQ_XON_STA_ep_xon_inmq_h1(unsigned int uep_xon_inmq_h1); +int iSetENQC_HOSTEP_INMQ_XON_STA_ep_xon_inmq_h2(unsigned int uep_xon_inmq_h2); +int iSetENQC_HOSTEP_INMQ_XON_STA_ep_xon_inmq_h3(unsigned int uep_xon_inmq_h3); +int iSetENQC_HOSTEP_INFMQ_XON_STA_ep_xon_infmq_h0(unsigned int uep_xon_infmq_h0); +int iSetENQC_HOSTEP_INFMQ_XON_STA_ep_xon_infmq_h1(unsigned int uep_xon_infmq_h1); +int iSetENQC_HOSTEP_INFMQ_XON_STA_ep_xon_infmq_h2(unsigned int uep_xon_infmq_h2); +int iSetENQC_HOSTEP_INFMQ_XON_STA_ep_xon_infmq_h3(unsigned int uep_xon_infmq_h3); +int iSetENQC_HEC_INMQ_XON_STA_hec_xon_inmq(unsigned int uhec_xon_inmq); +int iSetENQC_HEC_INFMQ_XON_STA_hec_xon_infmq(unsigned int uhec_xon_infmq); +int iSetENQC_QUE_INMQ_XON_STA_que_xon_inmq(unsigned int uque_xon_inmq); +int iSetENQC_QUE_INFMQ_XON_STA_que_xon_infmq(unsigned int uque_xon_infmq); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_soc_cmd_qf_done(unsigned int uflush_soc_cmd_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_host_cmd_qf_done(unsigned int uflush_host_cmd_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_soc_ls_qf_done(unsigned int uflush_soc_ls_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_soc_lr_qf_done(unsigned int uflush_soc_lr_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_host_ls_qf_done(unsigned int uflush_host_ls_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_host_lr_qf_done(unsigned int uflush_host_lr_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_sq_qf_done(unsigned int uflush_sq_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_rq_qf_done(unsigned int uflush_rq_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_ucode_qf_done(unsigned int uflush_ucode_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_rdma_qf_done(unsigned int uflush_rdma_qf_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_emqcnt_done(unsigned int uflush_emqcnt_done); +int iSetENQC_FLUSH_QF_EMQCNT_DONE_flush_pt_fifo_done(unsigned int uflush_pt_fifo_done); +int iSetENQC_ECC_1BIT_ERR_CNT_enqc_ecc_1bit_err_cnt(unsigned int uenqc_ecc_1bit_err_cnt); +int iSetENQC_ECC_2BIT_ERR_CNT_enqc_ecc_2bit_err_cnt(unsigned int uenqc_ecc_2bit_err_cnt); +int iSetENQC_RX_DU_PACKET_enqc_rx_du_pkt(unsigned int uenqc_rx_du_pkt); +int iSetENQC_RX_DU_LENGTH_enqc_rx_du_length(unsigned int uenqc_rx_du_length); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_cpi_cnt(unsigned int ucpi_cnt); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_cpi_full(unsigned int ucpi_full); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_cpi_empt(unsigned int ucpi_empt); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_emqenq_fifo_cnt(unsigned int uemqenq_fifo_cnt); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_emqenq_fifo_full(unsigned int uemqenq_fifo_full); +int iSetCPI_IN_EMQCNT_FIFO_STATUS_emqenq_fifo_empt(unsigned int uemqenq_fifo_empt); +int iSetSM_IN_FIFO_STATUS_sm_wfifo_cnt(unsigned int usm_wfifo_cnt); +int iSetSM_IN_FIFO_STATUS_sm_full(unsigned int usm_full); +int iSetSM_IN_FIFO_STATUS_sm_aful(unsigned int usm_aful); +int iSetSM_IN_FIFO_STATUS_sm_empt(unsigned int usm_empt); +int iSetTILE_QU_IN_FIFO_STATUS_tile_wfifo_cnt(unsigned int utile_wfifo_cnt); +int iSetTILE_QU_IN_FIFO_STATUS_tile_full(unsigned int utile_full); +int iSetTILE_QU_IN_FIFO_STATUS_tile_empt(unsigned int utile_empt); +int iSetTILE_QU_IN_FIFO_STATUS_qu_wfifo_cnt(unsigned int uqu_wfifo_cnt); +int iSetTILE_QU_IN_FIFO_STATUS_qu_full(unsigned int uqu_full); +int iSetTILE_QU_IN_FIFO_STATUS_qu_empt(unsigned int uqu_empt); +int iSetENQC_MRF_DU_FIFO_STATUS_mrf_fifo_cnt(unsigned int umrf_fifo_cnt); +int iSetENQC_MRF_DU_FIFO_STATUS_mrf_fifo_full(unsigned int umrf_fifo_full); +int iSetENQC_MRF_DU_FIFO_STATUS_mrf_fifo_empt(unsigned int umrf_fifo_empt); +int iSetENQC_MRF_DU_FIFO_STATUS_mrf_fifo_aful(unsigned int umrf_fifo_aful); +int iSetENQC_MRF_DU_FIFO_STATUS_durf_fifo_cnt(unsigned int udurf_fifo_cnt); +int iSetENQC_MRF_DU_FIFO_STATUS_durf_fifo_full(unsigned int udurf_fifo_full); +int iSetENQC_MRF_DU_FIFO_STATUS_durf_fifo_empt(unsigned int udurf_fifo_empt); +int iSetENQC_MRF_DU_FIFO_STATUS_durf_fifo_aful(unsigned int udurf_fifo_aful); +int iSetENQC_PASSTHRU_FIFO_STATUS_passthru_fifo_cnt(unsigned int upassthru_fifo_cnt); +int iSetENQC_PASSTHRU_FIFO_STATUS_passthru_fifo_dfx(unsigned int upassthru_fifo_dfx); +int iSetENQC_INPUT_BP_mqm_cpi_db_bp(unsigned int umqm_cpi_db_bp); +int iSetENQC_EQM_QD_CNT_enqc_eqm_qd_cnt(unsigned int uenqc_eqm_qd_cnt); +int iSetENQC_RX_CPI_PKT_CNT_enqc_rx_cpi_pkt_cnt(unsigned int uenqc_rx_cpi_pkt_cnt); +int iSetENQC_RX_SM_PKT_CNT_enqc_rx_sm_pkt_cnt(unsigned int uenqc_rx_sm_pkt_cnt); +int iSetENQC_RX_TILE_PKT_CNT_enqc_rx_tile_pkt_cnt(unsigned int uenqc_rx_tile_pkt_cnt); +int iSetENQC_RX_QU_PKT_CNT_enqc_rx_qu_pkt_cnt(unsigned int uenqc_rx_qu_pkt_cnt); +int iSetENQC_DIS_CPI_CNT_enqc_dis_cpi_cnt(unsigned int uenqc_dis_cpi_cnt); +int iSetENQC_RX_RING_ERR_DB_CNT_enqc_rx_ring_err_db_cnt(unsigned int uenqc_rx_ring_err_db_cnt); +int iSetENQC_ENQ_IQM_CNT_enqc_enq_iqm_cnt(unsigned int uenqc_enq_iqm_cnt); +int iSetENQC_ENQ_EQM_CNT_enqc_enq_eqm_cnt(unsigned int uenqc_enq_eqm_cnt); +int iSetENQC_FILTERD_DB_CNT_enqc_filterd_db_cnt(unsigned int uenqc_filterd_db_cnt); +int iSetENQC_RX_SM_CP_SGE_CRDT_enqc_rx_cp_sge_crdt(unsigned int uenqc_rx_cp_sge_crdt); +int iSetENQC_RX_SM_DP_SGE_CRDT_enqc_rx_dp_sge_crdt(unsigned int uenqc_rx_dp_sge_crdt); +int iSetENQC_RX_SM_CP_DATA_CRDT_enqc_rx_cp_data_crdt(unsigned int uenqc_rx_cp_data_crdt); +int iSetENQC_RX_SM_DP_DATA_CRDT_enqc_rx_dp_data_crdt(unsigned int uenqc_rx_dp_data_crdt); +int iSetENQC_RX_DP_NOFL_DB_enqc_rx_dp_nofl_db_cnt(unsigned int uenqc_rx_dp_nofl_db_cnt); +int iSetDB_OVFL_VF_RANGE_CNT_db_ovfl_vf_range_cnt(unsigned int udb_ovfl_vf_range_cnt); +int iSetNONF_DB_NUM_OVFL_THR_CNT_nonf_db_num_ovfl_thr_cnt(unsigned int unonf_db_num_ovfl_thr_cnt); +int iSetMQM_ERR_TYP_DB_CNT_mqm_err_typ_db_cnt(unsigned int umqm_err_typ_db_cnt); +int iSetPASS_THROUGH_STA_passthru_fsm(unsigned int upassthru_fsm); +int iSetPASS_THROUGH_STA_passthru_fifo_status(unsigned int upassthru_fifo_status); +int iSetPASS_THROUGH_STA_iqm_enqc_inner_empt(unsigned int uiqm_enqc_inner_empt); +int iSetPASS_THROUGH_STA_eqm_enqc_outer_empt(unsigned int ueqm_enqc_outer_empt); +int iSetPASS_THROUGH_STA_enqc_passthru_pipe_empt(unsigned int uenqc_passthru_pipe_empt); +int iSetPASS_THROUGH_STA_iqm_enqc_inner_bp(unsigned int uiqm_enqc_inner_bp); +int iSetPASS_THROUGH_STA_qu_mqm_underload(unsigned int uqu_mqm_underload); + +/* Define the union csr_brm_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_rw_rsv0_u; + +/* Define the union csr_brm_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_rw_rsv1_u; + +/* Define the union csr_brm_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_rw_rsv2_u; + +/* Define the union csr_brm_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_rw_rsv3_u; + +/* Define the union csr_brm_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_indrect_addr : 13; /* [12:0] */ + u32 rsv_0 : 11; /* [23:13] */ + u32 brm_indrect_tab : 4; /* [27:24] */ + u32 brm_indrect_status : 2; /* [29:28] */ + u32 brm_indrect_mode : 1; /* [30] */ + u32 brm_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_indrect_ctrl_u; + +/* Define the union csr_brm_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_indrect_timeout_u; + +/* Define the union csr_brm_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_indrect_data_0_u; + +/* Define the union csr_brm_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_indrect_data_1_u; + +/* Define the union csr_brm_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_cpi_int_index : 24; /* [23:0] */ + u32 rsv_1 : 3; /* [26:24] */ + u32 brm_enable : 1; /* [27] */ + u32 brm_int_issue : 1; /* [28] */ + u32 rsv_2 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_int_vector_u; + +/* Define the union csr_brm_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_int_data : 4; /* [3:0] */ + u32 rsv_3 : 12; /* [15:4] */ + u32 brm_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_int_u; + +/* Define the union csr_brm_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_int_en : 4; /* [3:0] */ + u32 rsv_4 : 12; /* [15:4] */ + u32 brm_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_int_en_u; + +/* Define the union csr_brm_mem_ecc0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_ecc0_err : 1; /* [0] */ + u32 brm_ecc0_err_insert : 1; /* [1] */ + u32 brm_ecc0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ecc0_u; + +/* Define the union csr_brm_mem_ecc1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_ecc1_err : 1; /* [0] */ + u32 brm_ecc1_err_insert : 1; /* [1] */ + u32 brm_ecc1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ecc1_u; + +/* Define the union csr_brm_db_flt_addr_ovfl_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_qf_ovfl_err : 1; /* [0] */ + u32 brm_qf_ovfl_err_insert : 1; /* [1] */ + u32 brm_qf_ovfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_db_flt_addr_ovfl_int_u; + +/* Define the union csr_brm_cnt_addr_ovfl_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_cnt_ovfl_err : 1; /* [0] */ + u32 brm_cnt_ovfl_err_insert : 1; /* [1] */ + u32 brm_cnt_ovfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_cnt_addr_ovfl_int_u; + +/* Define the union csr_brm_att_cnt_mem_ecc_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slc7_err_req : 2; /* [1:0] */ + u32 slc8_err_req : 2; /* [3:2] */ + u32 slc9_err_req : 2; /* [5:4] */ + u32 slc10_err_req : 2; /* [7:6] */ + u32 slc11_err_req : 2; /* [9:8] */ + u32 slc12_err_req : 2; /* [11:10] */ + u32 slc13_err_req : 2; /* [13:12] */ + u32 slc14_err_req : 2; /* [15:14] */ + u32 slc15_err_req : 2; /* [17:16] */ + u32 slc16_err_req : 2; /* [19:18] */ + u32 slc17_err_req : 2; /* [21:20] */ + u32 dwq_err_req : 2; /* [23:22] */ + u32 rsv_5 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_att_cnt_mem_ecc_req_u; + +/* Define the union csr_brm_qf_qd_mem_ecc_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 slc0_lc_err_req : 2; /* [1:0] */ + u32 slc0_err_req : 2; /* [3:2] */ + u32 slc1_err_req : 2; /* [5:4] */ + u32 slc2_err_req : 2; /* [7:6] */ + u32 slc3_err_req : 2; /* [9:8] */ + u32 slc4_err_req : 2; /* [11:10] */ + u32 slc5_err_req : 2; /* [13:12] */ + u32 slc6_err_req : 2; /* [15:14] */ + u32 slc18_err_req : 2; /* [17:16] */ + u32 slc19_err_req : 2; /* [19:18] */ + u32 rsv_6 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_qf_qd_mem_ecc_req_u; + +/* Define the union csr_brm_que_filt_spa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 que_filt_spa : 3; /* [2:0] */ + u32 rsv_7 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_que_filt_spa_u; + +/* Define the union csr_brm_att_size_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_att_size : 4; /* [3:0] */ + u32 rsv_8 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_att_size_u; + +/* Define the union csr_brm_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_9 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ecc_bypass_en_u; + +/* Define the union csr_brm_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_brm_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_brm_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_brm_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_brm_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_10 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_brm_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_ecc_1bit_err_cnt_u; + +/* Define the union csr_brm_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brm_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_brm_ecc_2bit_err_cnt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_brm_rw_rsv0_u brm_rw_rsv0; /* 0 */ + volatile csr_brm_rw_rsv1_u brm_rw_rsv1; /* 4 */ + volatile csr_brm_rw_rsv2_u brm_rw_rsv2; /* 8 */ + volatile csr_brm_rw_rsv3_u brm_rw_rsv3; /* C */ + volatile csr_brm_indrect_ctrl_u brm_indrect_ctrl; /* 10 */ + volatile csr_brm_indrect_timeout_u brm_indrect_timeout; /* 14 */ + volatile csr_brm_indrect_data_0_u brm_indrect_data_0; /* 18 */ + volatile csr_brm_indrect_data_1_u brm_indrect_data_1; /* 1C */ + volatile csr_brm_int_vector_u brm_int_vector; /* 20 */ + volatile csr_brm_int_u brm_int; /* 24 */ + volatile csr_brm_int_en_u brm_int_en; /* 28 */ + volatile csr_brm_mem_ecc0_u brm_mem_ecc0; /* 2C */ + volatile csr_brm_mem_ecc1_u brm_mem_ecc1; /* 30 */ + volatile csr_brm_db_flt_addr_ovfl_int_u brm_db_flt_addr_ovfl_int; /* 34 */ + volatile csr_brm_cnt_addr_ovfl_int_u brm_cnt_addr_ovfl_int; /* 38 */ + volatile csr_brm_att_cnt_mem_ecc_req_u brm_att_cnt_mem_ecc_req; /* 50 */ + volatile csr_brm_qf_qd_mem_ecc_req_u brm_qf_qd_mem_ecc_req; /* 54 */ + volatile csr_brm_que_filt_spa_u brm_que_filt_spa; /* 80 */ + volatile csr_brm_att_size_u brm_att_size; /* 84 */ + volatile csr_brm_mem_ecc_bypass_en_u brm_mem_ecc_bypass_en; /* 88 */ + volatile csr_brm_mem_ctrl_bus_cfg0_u brm_mem_ctrl_bus_cfg0; /* 8C */ + volatile csr_brm_mem_ctrl_bus_cfg1_u brm_mem_ctrl_bus_cfg1; /* 90 */ + volatile csr_brm_mem_ctrl_bus_cfg2_u brm_mem_ctrl_bus_cfg2; /* 94 */ + volatile csr_brm_mem_ctrl_bus_cfg3_u brm_mem_ctrl_bus_cfg3; /* 98 */ + volatile csr_brm_mem_ctrl_bus_cfg4_u brm_mem_ctrl_bus_cfg4; /* 9C */ + volatile csr_brm_ecc_1bit_err_cnt_u brm_ecc_1bit_err_cnt; /* B0 */ + volatile csr_brm_ecc_2bit_err_cnt_u brm_ecc_2bit_err_cnt; /* B4 */ +} S_mqm_brm_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_brm */ +extern volatile S_mqm_brm_REGS_TYPE *gopmqm_brmAllReg; + +/* Declare the functions that set the member value */ +int iSetBRM_RW_RSV0_brm_rw_rsv0(unsigned int ubrm_rw_rsv0); +int iSetBRM_RW_RSV1_brm_rw_rsv1(unsigned int ubrm_rw_rsv1); +int iSetBRM_RW_RSV2_brm_rw_rsv2(unsigned int ubrm_rw_rsv2); +int iSetBRM_RW_RSV3_brm_rw_rsv3(unsigned int ubrm_rw_rsv3); +int iSetBRM_INDRECT_CTRL_brm_indrect_addr(unsigned int ubrm_indrect_addr); +int iSetBRM_INDRECT_CTRL_brm_indrect_tab(unsigned int ubrm_indrect_tab); +int iSetBRM_INDRECT_CTRL_brm_indrect_status(unsigned int ubrm_indrect_status); +int iSetBRM_INDRECT_CTRL_brm_indrect_mode(unsigned int ubrm_indrect_mode); +int iSetBRM_INDRECT_CTRL_brm_indrect_vld(unsigned int ubrm_indrect_vld); +int iSetBRM_INDRECT_TIMEOUT_brm_indrect_timeout(unsigned int ubrm_indrect_timeout); +int iSetBRM_INDRECT_DATA_0_brm_indrect_data_0(unsigned int ubrm_indrect_data_0); +int iSetBRM_INDRECT_DATA_1_brm_indrect_data_1(unsigned int ubrm_indrect_data_1); +int iSetBRM_INT_VECTOR_brm_cpi_int_index(unsigned int ubrm_cpi_int_index); +int iSetBRM_INT_VECTOR_brm_enable(unsigned int ubrm_enable); +int iSetBRM_INT_VECTOR_brm_int_issue(unsigned int ubrm_int_issue); +int iSetBRM_INT_brm_int_data(unsigned int ubrm_int_data); +int iSetBRM_INT_brm_program_csr_id_ro(unsigned int ubrm_program_csr_id_ro); +int iSetBRM_INT_EN_brm_int_en(unsigned int ubrm_int_en); +int iSetBRM_INT_EN_brm_program_csr_id(unsigned int ubrm_program_csr_id); +int iSetBRM_MEM_ECC0_brm_ecc0_err(unsigned int ubrm_ecc0_err); +int iSetBRM_MEM_ECC0_brm_ecc0_err_insert(unsigned int ubrm_ecc0_err_insert); +int iSetBRM_MEM_ECC0_brm_ecc0_err_info(unsigned int ubrm_ecc0_err_info); +int iSetBRM_MEM_ECC1_brm_ecc1_err(unsigned int ubrm_ecc1_err); +int iSetBRM_MEM_ECC1_brm_ecc1_err_insert(unsigned int ubrm_ecc1_err_insert); +int iSetBRM_MEM_ECC1_brm_ecc1_err_info(unsigned int ubrm_ecc1_err_info); +int iSetBRM_DB_FLT_ADDR_OVFL_INT_brm_qf_ovfl_err(unsigned int ubrm_qf_ovfl_err); +int iSetBRM_DB_FLT_ADDR_OVFL_INT_brm_qf_ovfl_err_insert(unsigned int ubrm_qf_ovfl_err_insert); +int iSetBRM_DB_FLT_ADDR_OVFL_INT_brm_qf_ovfl_err_info(unsigned int ubrm_qf_ovfl_err_info); +int iSetBRM_CNT_ADDR_OVFL_INT_brm_cnt_ovfl_err(unsigned int ubrm_cnt_ovfl_err); +int iSetBRM_CNT_ADDR_OVFL_INT_brm_cnt_ovfl_err_insert(unsigned int ubrm_cnt_ovfl_err_insert); +int iSetBRM_CNT_ADDR_OVFL_INT_brm_cnt_ovfl_err_info(unsigned int ubrm_cnt_ovfl_err_info); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc7_err_req(unsigned int uslc7_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc8_err_req(unsigned int uslc8_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc9_err_req(unsigned int uslc9_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc10_err_req(unsigned int uslc10_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc11_err_req(unsigned int uslc11_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc12_err_req(unsigned int uslc12_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc13_err_req(unsigned int uslc13_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc14_err_req(unsigned int uslc14_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc15_err_req(unsigned int uslc15_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc16_err_req(unsigned int uslc16_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_slc17_err_req(unsigned int uslc17_err_req); +int iSetBRM_ATT_CNT_MEM_ECC_REQ_dwq_err_req(unsigned int udwq_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc0_lc_err_req(unsigned int uslc0_lc_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc0_err_req(unsigned int uslc0_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc1_err_req(unsigned int uslc1_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc2_err_req(unsigned int uslc2_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc3_err_req(unsigned int uslc3_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc4_err_req(unsigned int uslc4_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc5_err_req(unsigned int uslc5_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc6_err_req(unsigned int uslc6_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc18_err_req(unsigned int uslc18_err_req); +int iSetBRM_QF_QD_MEM_ECC_REQ_slc19_err_req(unsigned int uslc19_err_req); +int iSetBRM_QUE_FILT_SPA_que_filt_spa(unsigned int uque_filt_spa); +int iSetBRM_ATT_SIZE_brm_att_size(unsigned int ubrm_att_size); +int iSetBRM_MEM_ECC_BYPASS_EN_brm_mem_ecc_bypass(unsigned int ubrm_mem_ecc_bypass); +int iSetBRM_MEM_CTRL_BUS_CFG0_brm_mem_ctrl_bus_0(unsigned int ubrm_mem_ctrl_bus_0); +int iSetBRM_MEM_CTRL_BUS_CFG1_brm_mem_ctrl_bus_1(unsigned int ubrm_mem_ctrl_bus_1); +int iSetBRM_MEM_CTRL_BUS_CFG2_brm_mem_ctrl_bus_2(unsigned int ubrm_mem_ctrl_bus_2); +int iSetBRM_MEM_CTRL_BUS_CFG3_brm_mem_ctrl_bus_3(unsigned int ubrm_mem_ctrl_bus_3); +int iSetBRM_MEM_CTRL_BUS_CFG4_brm_mem_ctrl_bus_4(unsigned int ubrm_mem_ctrl_bus_4); +int iSetBRM_ECC_1BIT_ERR_CNT_brm_ecc_1bit_err_cnt(unsigned int ubrm_ecc_1bit_err_cnt); +int iSetBRM_ECC_2BIT_ERR_CNT_brm_ecc_2bit_err_cnt(unsigned int ubrm_ecc_2bit_err_cnt); + +/* Define the union csr_iqm_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rw_rsv0_u; + +/* Define the union csr_iqm_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rw_rsv1_u; + +/* Define the union csr_iqm_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rw_rsv2_u; + +/* Define the union csr_iqm_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rw_rsv3_u; + +/* Define the union csr_iqm_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_indrect_addr : 14; /* [13:0] */ + u32 rsv_0 : 10; /* [23:14] */ + u32 iqm_indrect_tab : 4; /* [27:24] */ + u32 iqm_indrect_status : 2; /* [29:28] */ + u32 iqm_indrect_mode : 1; /* [30] */ + u32 iqm_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_indrect_ctrl_u; + +/* Define the union csr_iqm_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_indrect_timeout_u; + +/* Define the union csr_iqm_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_indrect_data_0_u; + +/* Define the union csr_iqm_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_indrect_data_1_u; + +/* Define the union csr_iqm_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cpi_int_index : 24; /* [23:0] */ + u32 rsv_1 : 3; /* [26:24] */ + u32 iqm_enable : 1; /* [27] */ + u32 iqm_int_issue : 1; /* [28] */ + u32 rsv_2 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_int_vector_u; + +/* Define the union csr_iqm_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_int_data : 9; /* [8:0] */ + u32 rsv_3 : 7; /* [15:9] */ + u32 iqm_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_int_u; + +/* Define the union csr_iqm_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_int_en : 9; /* [8:0] */ + u32 rsv_4 : 7; /* [15:9] */ + u32 iqm_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_int_en_u; + +/* Define the union csr_iqm_mem_ecc0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ecc0_err : 1; /* [0] */ + u32 iqm_ecc0_err_insert : 1; /* [1] */ + u32 iqm_ecc0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ecc0_u; + +/* Define the union csr_iqm_mem_ecc1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ecc1_err : 1; /* [0] */ + u32 iqm_ecc1_err_insert : 1; /* [1] */ + u32 iqm_ecc1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ecc1_u; + +/* Define the union csr_iqm_aging_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_aging_int_err : 1; /* [0] */ + u32 iqm_aging_int_err_insert : 1; /* [1] */ + u32 iqm_aging_int_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_int_u; + +/* Define the union csr_iqm_cmq_deq_empty_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_deq_empty_err : 1; /* [0] */ + u32 iqm_cmq_deq_empty_err_insert : 1; /* [1] */ + u32 iqm_cmq_deq_empty_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_deq_empty_int_u; + +/* Define the union csr_iqm_fifo_wr_ovfl_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_fifo_wr_ovfl_err : 1; /* [0] */ + u32 iqm_fifo_wr_ovfl_err_insert : 1; /* [1] */ + u32 iqm_fifo_wr_ovfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_wr_ovfl_int_u; + +/* Define the union csr_iqm_fifo_rd_udfl_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_fifo_rd_udfl_err : 1; /* [0] */ + u32 iqm_fifo_rd_udfl_err_insert : 1; /* [1] */ + u32 iqm_fifo_rd_udfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_rd_udfl_int_u; + +/* Define the union csr_iqm_free_rsc_bmp_overflow_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_free_rsc_bmp_ovfl_err : 1; /* [0] */ + u32 iqm_free_rsc_bmp_ovfl_err_insert : 1; /* [1] */ + u32 iqm_free_rsc_bmp_ovfl_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_free_rsc_bmp_overflow_int_u; + +/* Define the union csr_iqm_cll_deq_empty_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmqnfmq_deq_empty_err : 1; /* [0] */ + u32 iqm_nmqnfmq_deq_empty_err_insert : 1; /* [1] */ + u32 iqm_nmqnfmq_deq_empty_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cll_deq_empty_int_u; + +/* Define the union csr_iqm_uxmq_deq_empty_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_uxmq_deq_empty_err : 1; /* [0] */ + u32 iqm_uxmq_deq_empty_err_insert : 1; /* [1] */ + u32 iqm_uxmq_deq_empty_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_uxmq_deq_empty_int_u; + +/* Define the union csr_iqm_fifo_int_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_shallow_fifo_rd_udfl_insert0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req1_u; + +/* Define the union csr_iqm_fifo_int_req2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_rd_udfl_insert2 : 8; /* [7:0] */ + u32 sm_shallow_fifo_rd_udfl_insert1 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req2_u; + +/* Define the union csr_iqm_fifo_int_req3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_rd_udfl_insert0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req3_u; + +/* Define the union csr_iqm_fifo_int_req4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_rd_udfl_insert1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req4_u; + +/* Define the union csr_iqm_mem_ecc_req0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cll_head_mem_err_req : 2; /* [1:0] */ + u32 cll_tail_mem_err_req : 2; /* [3:2] */ + u32 cll_mqle_mem_err_req : 2; /* [5:4] */ + u32 cll_ckll_mem_err_req : 2; /* [7:6] */ + u32 mq2vf_mem_err_req : 2; /* [9:8] */ + u32 cll_faptab_mem_err_req : 2; /* [11:10] */ + u32 pre_enq_qlen_mem_err_req : 2; /* [13:12] */ + u32 que_pro_map_mem_err_req : 2; /* [15:14] */ + u32 pre_enq_hec_len_mem_err_req : 2; /* [17:16] */ + u32 cmq_ll_head_mem_err_req : 2; /* [19:18] */ + u32 cmq_ll_tail_mem_err_req : 2; /* [21:20] */ + u32 cmq_queue_len_mem_err_req : 2; /* [23:22] */ + u32 cmq_ll_mem_err_req : 2; /* [25:24] */ + u32 cmq_hec_len_mem_err_req : 2; /* [27:26] */ + u32 ill_soc_ll_err_req : 2; /* [29:28] */ + u32 rsv_5 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ecc_req0_u; + +/* Define the union csr_iqm_mem_ecc_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soc_qd_err_req : 2; /* [1:0] */ + u32 deq_sm_fifo_mem_err_req : 2; /* [3:2] */ + u32 deq_qu_fifo_mem_err_req : 2; /* [5:4] */ + u32 iqm_agcnt_err_req : 2; /* [7:6] */ + u32 iqm_agvld_err_req : 2; /* [9:8] */ + u32 rsv_6 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ecc_req1_u; + +/* Define the union csr_iqm_uncrt_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cll_rsc_overflow_uncrt_int_en : 1; /* [0] */ + u32 cll_deq_empty_uncrt_int_en : 1; /* [1] */ + u32 cmq_deq_empty_uncrt_int_en : 1; /* [2] */ + u32 uxmq_deq_empty_uncrt_int_en : 1; /* [3] */ + u32 rsv_7 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_uncrt_int_en_u; + +/* Define the union csr_iqm_fifo_int_req5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_shallow_fifo_wr_ovfl_insert0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req5_u; + +/* Define the union csr_iqm_fifo_int_req6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_wr_ovfl_insert2 : 8; /* [7:0] */ + u32 sm_shallow_fifo_wr_ovfl_insert1 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req6_u; + +/* Define the union csr_iqm_fifo_int_req7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_wr_ovfl_insert0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req7_u; + +/* Define the union csr_iqm_fifo_int_req8_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_wr_ovfl_insert1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req8_u; + +/* Define the union csr_iqm_fifo_int_req9_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq_fifo_wr_ovfl_insert : 1; /* [0] */ + u32 enqc_enq_fifo_rd_udfl_insert : 1; /* [1] */ + u32 eqm_enq_fifo_wr_ovfl_insert : 1; /* [2] */ + u32 eqm_enq_fifo_rd_udfl_insert : 1; /* [3] */ + u32 deqc_enq_fifo_wr_ovfl_insert : 1; /* [4] */ + u32 deqc_enq_fifo_rd_udfl_insert : 1; /* [5] */ + u32 enqc_enq_soc_fifo_wr_ovfl_insert : 1; /* [6] */ + u32 enqc_enq_soc_fifo_rd_udfl_insert : 1; /* [7] */ + u32 sm_dp_out_fifo_wr_ovfl_insert : 1; /* [8] */ + u32 sm_dp_out_fifo_rd_udfl_insert : 1; /* [9] */ + u32 sm_cp_out_fifo_wr_ovfl_insert : 1; /* [10] */ + u32 sm_cp_out_fifo_rd_udfl_insert : 1; /* [11] */ + u32 cpi_ep_sge_fifo_wr_ovfl_insert : 1; /* [12] */ + u32 cpi_ep_sge_fifo_rd_udfl_insert : 1; /* [13] */ + u32 cpi_host_sge_fifo_wr_ovfl_insert : 1; /* [14] */ + u32 cpi_host_sge_fifo_rd_udfl_insert : 1; /* [15] */ + u32 cpi_data_fifo_wr_ovfl_insert : 1; /* [16] */ + u32 cpi_data_fifo_rd_udfl_insert : 1; /* [17] */ + u32 sm_data_fifo_wr_ovfl_insert : 1; /* [18] */ + u32 sm_data_fifo_rd_udfl_insert : 1; /* [19] */ + u32 sm_sge_fifo_wr_ovfl_insert : 1; /* [20] */ + u32 sm_sge_fifo_rd_udfl_insert : 1; /* [21] */ + u32 qu_ep_fifo_wr_ovfl_insert : 1; /* [22] */ + u32 qu_ep_fifo_rd_udfl_insert : 1; /* [23] */ + u32 rsv_8 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_fifo_int_req9_u; + +/* Define the union csr_iqm_chunk_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 chunk_size : 2; /* [1:0] */ + u32 rsv_9 : 2; /* [3:2] */ + u32 icll_bitmap_critical_depth : 11; /* [14:4] */ + u32 rsv_10 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_chunk_u; + +/* Define the union csr_iqm_out_fifo_th_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_deq_sm_ctrl_plane_aful_gap : 4; /* [3:0] */ + u32 rsv_11 : 4; /* [7:4] */ + u32 iqm_deq_sm_data_plane_aful_gap : 4; /* [11:8] */ + u32 rsv_12 : 4; /* [15:12] */ + u32 iqm_qu_shallow_fifo_gap : 4; /* [19:16] */ + u32 rsv_13 : 4; /* [23:20] */ + u32 iqm_sm_shallow_fifo_gap : 4; /* [27:24] */ + u32 rsv_14 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_out_fifo_th_gap_u; + +/* Define the union csr_iqm_enq_fifo_aful_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq_fifo_afull_gap : 2; /* [1:0] */ + u32 rsv_15 : 2; /* [3:2] */ + u32 eqm_enq_fifo_afull_gap : 3; /* [6:4] */ + u32 rsv_16 : 1; /* [7] */ + u32 deqc_enq_fifo_afull_gap : 3; /* [10:8] */ + u32 rsv_17 : 1; /* [11] */ + u32 enqc_enq_soc_fifo_afull_gap : 2; /* [13:12] */ + u32 rsv_18 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_enq_fifo_aful_gap_u; + +/* Define the union csr_iqm_crdt_comp_fifo_gap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_data_aful_gap : 3; /* [2:0] */ + u32 rsv_19 : 1; /* [3] */ + u32 sm_sge_aful_gap : 3; /* [6:4] */ + u32 rsv_20 : 1; /* [7] */ + u32 cpi_data_aful_gap : 6; /* [13:8] */ + u32 rsv_21 : 2; /* [15:14] */ + u32 cpi_host_sge_aful_gap : 6; /* [21:16] */ + u32 rsv_22 : 2; /* [23:22] */ + u32 cpi_ep_sge_aful_gap : 6; /* [29:24] */ + u32 rsv_23 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_crdt_comp_fifo_gap_cfg_u; + +/* Define the union csr_iqm_aging_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_aging_en : 1; /* [0] */ + u32 rsv_24 : 3; /* [3:1] */ + u32 nfmq_aging_en : 1; /* [4] */ + u32 rsv_25 : 3; /* [7:5] */ + u32 aging_intval : 16; /* [23:8] */ + u32 aging_dest : 1; /* [24] */ + u32 rsv_26 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_cfg_u; + +/* Define the union csr_iqm_des_que_deq_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 des_que_deq_mqid : 13; /* [12:0] */ + u32 rsv_27 : 3; /* [15:13] */ + u32 des_que_deq_qa : 1; /* [16] */ + u32 des_que_deq_src : 1; /* [17] */ + u32 rsv_28 : 2; /* [19:18] */ + u32 des_que_deq_hid : 2; /* [21:20] */ + u32 rsv_29 : 2; /* [23:22] */ + u32 des_que_deq_cos : 3; /* [26:24] */ + u32 rsv_30 : 1; /* [27] */ + u32 des_que_deq_ep : 3; /* [30:28] */ + u32 rsv_31 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_des_que_deq_cfg0_u; + +/* Define the union csr_iqm_des_que_deq_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_des_que_deq_vld : 1; /* [0] */ + u32 rsv_32 : 3; /* [3:1] */ + u32 des_que_deq_vfid : 13; /* [16:4] */ + u32 rsv_33 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_des_que_deq_cfg1_u; + +/* Define the union csr_iqm_root_thr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_total_fl_static_th : 16; /* [15:0] */ + u32 root_total_sl_static_th : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_root_thr_cfg_u; + +/* Define the union csr_iqm_root_hthr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_hth_parm_nmq : 6; /* [5:0] */ + u32 rsv_34 : 2; /* [7:6] */ + u32 root_hth_parm_nfmq : 6; /* [13:8] */ + u32 rsv_35 : 2; /* [15:14] */ + u32 root_total_hth_parm : 6; /* [21:16] */ + u32 rsv_36 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_root_hthr_cfg_u; + +/* Define the union csr_iqm_nmq_root_thr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_fl_static_th_nmq : 16; /* [15:0] */ + u32 root_sl_static_th_nmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_root_thr_cfg_u; + +/* Define the union csr_iqm_nfmq_root_thr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_fl_static_th_nfmq : 16; /* [15:0] */ + u32 root_sl_static_th_nfmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_root_thr_cfg_u; + +/* Define the union csr_iqm_nmq_host0_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid0_fl_static_th_nmq : 16; /* [15:0] */ + u32 hid0_sl_static_th_nmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_host0_th_u; + +/* Define the union csr_iqm_nmq_host1_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid1_fl_static_th_nmq : 16; /* [15:0] */ + u32 hid1_sl_static_th_nmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_host1_th_u; + +/* Define the union csr_iqm_nmq_host2_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid2_fl_static_th_nmq : 16; /* [15:0] */ + u32 hid2_sl_static_th_nmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_host2_th_u; + +/* Define the union csr_iqm_nmq_host3_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid3_fl_static_th_nmq : 16; /* [15:0] */ + u32 hid3_sl_static_th_nmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_host3_th_u; + +/* Define the union csr_iqm_nmq_host_hth_pa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid0_hth_parm_nmq : 6; /* [5:0] */ + u32 rsv_37 : 2; /* [7:6] */ + u32 hid1_hth_parm_nmq : 6; /* [13:8] */ + u32 rsv_38 : 2; /* [15:14] */ + u32 hid2_hth_parm_nmq : 6; /* [21:16] */ + u32 rsv_39 : 2; /* [23:22] */ + u32 hid3_hth_parm_nmq : 6; /* [29:24] */ + u32 rsv_40 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_host_hth_pa_u; + +/* Define the union csr_iqm_nfmq_host0_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid0_fl_static_th_nfmq : 16; /* [15:0] */ + u32 hid0_sl_static_th_nfmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_host0_th_u; + +/* Define the union csr_iqm_nfmq_host1_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid1_fl_static_th_nfmq : 16; /* [15:0] */ + u32 hid1_sl_static_th_nfmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_host1_th_u; + +/* Define the union csr_iqm_nfmq_host2_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid2_fl_static_th_nfmq : 16; /* [15:0] */ + u32 hid2_sl_static_th_nfmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_host2_th_u; + +/* Define the union csr_iqm_nfmq_host3_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid3_fl_static_th_nfmq : 16; /* [15:0] */ + u32 hid3_sl_static_th_nfmq : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_host3_th_u; + +/* Define the union csr_iqm_nfmq_host_hth_pa_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hid0_hth_parm_nfmq : 6; /* [5:0] */ + u32 rsv_41 : 2; /* [7:6] */ + u32 hid1_hth_parm_nfmq : 6; /* [13:8] */ + u32 rsv_42 : 2; /* [15:14] */ + u32 hid2_hth_parm_nfmq : 6; /* [21:16] */ + u32 rsv_43 : 2; /* [23:22] */ + u32 hid3_hth_parm_nfmq : 6; /* [29:24] */ + u32 rsv_44 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_host_hth_pa_u; + +/* Define the union csr_iqm_nmq_hex_pro_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 he_pro_map_nmq_0 : 4; /* [3:0] */ + u32 he_pro_map_nmq_1 : 4; /* [7:4] */ + u32 he_pro_map_nmq_2 : 4; /* [11:8] */ + u32 he_pro_map_nmq_3 : 4; /* [15:12] */ + u32 he_pro_map_nmq_4 : 4; /* [19:16] */ + u32 he_pro_map_nmq_5 : 4; /* [23:20] */ + u32 he_pro_map_nmq_6 : 4; /* [27:24] */ + u32 he_pro_map_nmq_7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_hex_pro_map_u; + +/* Define the union csr_iqm_nfmq_hex_pro_map_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 he_pro_map_nfmq_0 : 4; /* [3:0] */ + u32 he_pro_map_nfmq_1 : 4; /* [7:4] */ + u32 he_pro_map_nfmq_2 : 4; /* [11:8] */ + u32 he_pro_map_nfmq_3 : 4; /* [15:12] */ + u32 he_pro_map_nfmq_4 : 4; /* [19:16] */ + u32 he_pro_map_nfmq_5 : 4; /* [23:20] */ + u32 he_pro_map_nfmq_6 : 4; /* [27:24] */ + u32 he_pro_map_nfmq_7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_hex_pro_map_u; + +/* Define the union csr_iqm_he_th_pro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 he_fl_static_th_pro : 16; /* [15:0] */ + u32 he_sl_static_th_pro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_he_th_pro_u; + +/* Define the union csr_iqm_he_fac_pro_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_ep_fl_a_fact_pro : 7; /* [6:0] */ + u32 rsv_45 : 1; /* [7] */ + u32 host_ep_sl_a_fact_pro : 7; /* [14:8] */ + u32 rsv_46 : 1; /* [15] */ + u32 host_ep_hth_parm_pro : 6; /* [21:16] */ + u32 rsv_47 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_he_fac_pro_u; + +/* Define the union csr_iqm_qtss_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qtsc_fl : 16; /* [15:0] */ + u32 qtsc_sl : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qtss_cfg_u; + +/* Define the union csr_iqm_hetss_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 he_tsc_fl : 16; /* [15:0] */ + u32 he_tsc_sl : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_hetss_cfg_u; + +/* Define the union csr_iqm_hectss_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hec_tsc_fl : 16; /* [15:0] */ + u32 hec_tsc_sl : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_hectss_cfg_u; + +/* Define the union csr_iqm_sm_host_credit_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_host_credit_data_th : 10; /* [9:0] */ + u32 rsv_48 : 6; /* [15:10] */ + u32 iqm_sm_host_credit_sge_th : 10; /* [25:16] */ + u32 rsv_49 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_host_credit_th_u; + +/* Define the union csr_iqm_sm_credit_tss_cfg_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_cp_credit_tss_data : 10; /* [9:0] */ + u32 rsv_50 : 6; /* [15:10] */ + u32 iqm_sm_ep_dp_credit_tss_data : 10; /* [25:16] */ + u32 rsv_51 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_credit_tss_cfg_data_u; + +/* Define the union csr_iqm_sm_credit_tss_cfg_sge_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_cp_credit_tss_sge : 10; /* [9:0] */ + u32 rsv_52 : 6; /* [15:10] */ + u32 iqm_sm_ep_dp_credit_tss_sge : 10; /* [25:16] */ + u32 rsv_53 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_credit_tss_cfg_sge_u; + +/* Define the union csr_iqm_qu_credit_tss_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_cp_credit_tss : 10; /* [9:0] */ + u32 rsv_54 : 6; /* [15:10] */ + u32 iqm_qu_ep_dp_credit_tss : 10; /* [25:16] */ + u32 rsv_55 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_credit_tss_cfg_u; + +/* Define the union csr_iqm_crr_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_dp_crr_wgt : 3; /* [2:0] */ + u32 rsv_56 : 5; /* [7:3] */ + u32 iqm_sm_cp_crr_wgt : 3; /* [10:8] */ + u32 rsv_57 : 5; /* [15:11] */ + u32 iqm_qu_dp_crr_wgt : 3; /* [18:16] */ + u32 rsv_58 : 5; /* [23:19] */ + u32 iqm_qu_cp_crr_wgt : 3; /* [26:24] */ + u32 rsv_59 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_crr_wgt_cfg_u; + +/* Define the union csr_iqm_db_merger_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_db_merger_en : 1; /* [0] */ + u32 rsv_60 : 3; /* [3:1] */ + u32 iqm_db_merger_num : 3; /* [6:4] */ + u32 rsv_61 : 1; /* [7] */ + u32 iqm_db_merger_num_sum : 7; /* [14:8] */ + u32 rsv_62 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_db_merger_cfg_u; + +/* Define the union csr_smf_dst_hash_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smf_pg_cfg : 4; /* [3:0] */ + u32 rsv_63 : 12; /* [15:4] */ + u32 lbf_mode_sel_cfg : 2; /* [17:16] */ + u32 rsv_64 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smf_dst_hash_cfg_u; + +/* Define the union csr_iqm_aging_clr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mq_ag_clr_mqid : 13; /* [12:0] */ + u32 rsv_65 : 3; /* [15:13] */ + u32 mq_ag_clr_qa : 1; /* [16] */ + u32 rsv_66 : 7; /* [23:17] */ + u32 mq_ag_clr_vld : 1; /* [24] */ + u32 rsv_67 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_clr_cfg_u; + +/* Define the union csr_iqm_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_68 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ecc_bypass_en_u; + +/* Define the union csr_iqm_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_iqm_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_iqm_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_iqm_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_iqm_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_69 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_iqm_sm_shallow_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_shallow_fifo_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_shallow_fifo_status_u; + +/* Define the union csr_iqm_qu_shallow_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_shallow_fifo_status : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_shallow_fifo_status_u; + +/* Define the union csr_iqm_cmq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_root_cnt : 15; /* [14:0] */ + u32 rsv_70 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_cnt_u; + +/* Define the union csr_iqm_cmq_host_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_host0_cnt : 15; /* [14:0] */ + u32 rsv_71 : 1; /* [15] */ + u32 iqm_cmq_host1_cnt : 15; /* [30:16] */ + u32 rsv_72 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_host_cnt0_u; + +/* Define the union csr_iqm_cmq_host_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_host2_cnt : 15; /* [14:0] */ + u32 rsv_73 : 1; /* [15] */ + u32 iqm_cmq_host3_cnt : 15; /* [30:16] */ + u32 rsv_74 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_host_cnt1_u; + +/* Define the union csr_iqm_cmq_hostepx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_hostep_cnt : 15; /* [14:0] */ + u32 rsv_75 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_hostepx_cnt_u; + +/* Define the union csr_iqm_rootx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmq_cnt : 16; /* [15:0] */ + u32 iqm_nfmq_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rootx_cnt_u; + +/* Define the union csr_iqm_nmq_hostx_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmq_host0_cnt : 16; /* [15:0] */ + u32 iqm_nmq_host1_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_hostx_cnt0_u; + +/* Define the union csr_iqm_nmq_hostx_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmq_host2_cnt : 16; /* [15:0] */ + u32 iqm_nmq_host3_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmq_hostx_cnt1_u; + +/* Define the union csr_iqm_nfmq_hostx_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nfmq_host0_cnt : 16; /* [15:0] */ + u32 iqm_nfmq_host1_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_hostx_cnt0_u; + +/* Define the union csr_iqm_nfmq_hostx_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nfmq_host2_cnt : 16; /* [15:0] */ + u32 iqm_nfmq_host3_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nfmq_hostx_cnt1_u; + +/* Define the union csr_iqm_mq_hex_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmq_he_cnt : 16; /* [15:0] */ + u32 iqm_nfmq_he_cnt : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_mq_hex_cnt_u; + +/* Define the union csr_iqm_ucmq_root_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ucmq_root_cnt : 11; /* [10:0] */ + u32 rsv_76 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_ucmq_root_cnt_u; + +/* Define the union csr_iqm_unmq_root_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_unmq_root_cnt : 9; /* [8:0] */ + u32 rsv_77 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_unmq_root_cnt_u; + +/* Define the union csr_iqm_uxmq_ep_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 unmq_qlen_ep : 9; /* [8:0] */ + u32 rsv_78 : 3; /* [11:9] */ + u32 ucmq_qlen_ep : 11; /* [22:12] */ + u32 rsv_79 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_uxmq_ep_cnt_u; + +/* Define the union csr_iqm_uxmq_queue_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_unmqid_cnt : 11; /* [10:0] */ + u32 rsv_80 : 5; /* [15:11] */ + u32 iqm_ucmqid_cnt : 11; /* [26:16] */ + u32 rsv_81 : 5; /* [31:27] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_uxmq_queue_cnt_u; + +/* Define the union csr_eqm_enq_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_enq_fifo_cnt : 4; /* [3:0] */ + u32 rsv_82 : 12; /* [15:4] */ + u32 eqm_enq_fifo_full : 1; /* [16] */ + u32 rsv_83 : 3; /* [19:17] */ + u32 eqm_enq_fifo_aful : 1; /* [20] */ + u32 rsv_84 : 3; /* [23:21] */ + u32 eqm_enq_fifo_empt : 1; /* [24] */ + u32 rsv_85 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_enq_fifo_status_u; + +/* Define the union csr_deqc_enq_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_enq_fifo_cnt : 4; /* [3:0] */ + u32 rsv_86 : 4; /* [7:4] */ + u32 deqc_enq_fifo_full : 1; /* [8] */ + u32 rsv_87 : 3; /* [11:9] */ + u32 deqc_enq_fifo_empt : 1; /* [12] */ + u32 rsv_88 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_enq_fifo_status_u; + +/* Define the union csr_iqm_enqc_enq_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_enq_fifo_cnt : 3; /* [2:0] */ + u32 rsv_89 : 5; /* [7:3] */ + u32 enqc_enq_fifo_full : 1; /* [8] */ + u32 rsv_90 : 3; /* [11:9] */ + u32 enqc_enq_fifo_empt : 1; /* [12] */ + u32 rsv_91 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_enqc_enq_fifo_status_u; + +/* Define the union csr_iqm_enqc_soc_enq_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 enqc_soc_enq_fifo_cnt : 3; /* [2:0] */ + u32 rsv_92 : 5; /* [7:3] */ + u32 enqc_soc_enq_fifo_full : 1; /* [8] */ + u32 rsv_93 : 3; /* [11:9] */ + u32 enqc_soc_enq_fifo_empt : 1; /* [12] */ + u32 rsv_94 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_enqc_soc_enq_fifo_status_u; + +/* Define the union csr_iqm_cpi_sge_crdt_comp_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_host_sge_fifo_cnt : 7; /* [6:0] */ + u32 rsv_95 : 1; /* [7] */ + u32 cpi_host_sge_empt : 1; /* [8] */ + u32 cpi_host_sge_full : 1; /* [9] */ + u32 rsv_96 : 2; /* [11:10] */ + u32 cpi_ep_sge_fifo_cnt : 7; /* [18:12] */ + u32 rsv_97 : 1; /* [19] */ + u32 cpi_ep_sge_empt : 1; /* [20] */ + u32 cpi_ep_sge_full : 1; /* [21] */ + u32 rsv_98 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cpi_sge_crdt_comp_fifo_status_u; + +/* Define the union csr_iqm_cpi_data_crdt_comp_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_data_fifo_cnt : 7; /* [6:0] */ + u32 rsv_99 : 1; /* [7] */ + u32 cpi_data_empt : 1; /* [8] */ + u32 cpi_data_full : 1; /* [9] */ + u32 rsv_100 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cpi_data_crdt_comp_fifo_status_u; + +/* Define the union csr_iqm_sm_crdt_comp_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_data_fifo_cnt : 4; /* [3:0] */ + u32 rsv_101 : 4; /* [7:4] */ + u32 sm_data_empt : 1; /* [8] */ + u32 sm_data_full : 1; /* [9] */ + u32 rsv_102 : 2; /* [11:10] */ + u32 sm_sge_fifo_cnt : 4; /* [15:12] */ + u32 rsv_103 : 4; /* [19:16] */ + u32 sm_sge_empt : 1; /* [20] */ + u32 sm_sge_full : 1; /* [21] */ + u32 rsv_104 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_crdt_comp_fifo_status_u; + +/* Define the union csr_iqm_sm_out_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_cp_out_fifo_cnt : 5; /* [4:0] */ + u32 rsv_105 : 3; /* [7:5] */ + u32 sm_cp_out_fifo_empt : 1; /* [8] */ + u32 sm_cp_out_fifo_full : 1; /* [9] */ + u32 rsv_106 : 2; /* [11:10] */ + u32 sm_dp_out_fifo_cnt : 5; /* [16:12] */ + u32 rsv_107 : 3; /* [19:17] */ + u32 sm_dp_out_fifo_empt : 1; /* [20] */ + u32 sm_dp_out_fifo_full : 1; /* [21] */ + u32 rsv_108 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_out_fifo_status_u; + +/* Define the union csr_iqm_qu_crdt_comp_fifo_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_ep_crdt_fifo_cnt : 4; /* [3:0] */ + u32 rsv_109 : 4; /* [7:4] */ + u32 qu_ep_crdt_fifo_empt : 1; /* [8] */ + u32 qu_ep_crdt_fifo_full : 1; /* [9] */ + u32 rsv_110 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_crdt_comp_fifo_status_u; + +/* Define the union csr_icll_free_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 icll_free_rsc_cnt : 16; /* [15:0] */ + u32 rsv_111 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_icll_free_cnt_u; + +/* Define the union csr_iqm_sm_total_cam_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_total_thread_cnt : 7; /* [6:0] */ + u32 rsv_112 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_total_cam_cnt_u; + +/* Define the union csr_iqm_sm_host_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_host_sge_crdt_bp : 5; /* [4:0] */ + u32 rsv_113 : 3; /* [7:5] */ + u32 iqm_sm_host_dat_crdt_bp : 5; /* [12:8] */ + u32 rsv_114 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_host_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_dp_rr_sge_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_dp_rr_sge_crdt_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_dp_rr_sge_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_dp_rr_dat_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_dp_rr_dat_crdt_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_dp_rr_dat_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_dp_sge_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_dp_sge_crdt_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_dp_sge_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_dp_dat_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_dp_data_crdt_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_dp_dat_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_cp_rr_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_cp_rr_sge_crdt_bp : 8; /* [7:0] */ + u32 iqm_sm_ep_host_cp_rr_dat_crdt_bp : 8; /* [15:8] */ + u32 rsv_115 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_cp_rr_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_soc_rr_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_soc_dp_rr_sge_crdt_bp : 8; /* [7:0] */ + u32 iqm_sm_ep_soc_cp_rr_sge_crdt_bp : 8; /* [15:8] */ + u32 iqm_sm_ep_soc_dp_rr_dat_crdt_bp : 8; /* [23:16] */ + u32 iqm_sm_ep_soc_cp_rr_dat_crdt_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_soc_rr_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_host_cp_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_host_cp_sge_crdt_bp : 8; /* [7:0] */ + u32 iqm_sm_ep_host_cp_dat_crdt_bp : 8; /* [15:8] */ + u32 rsv_116 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_host_cp_crdt_bp_u; + +/* Define the union csr_iqm_sm_ep_soc_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_sm_ep_soc_dp_sge_crdt_bp : 8; /* [7:0] */ + u32 iqm_sm_ep_soc_cp_sge_crdt_bp : 8; /* [15:8] */ + u32 iqm_sm_ep_soc_dp_dat_crdt_bp : 8; /* [23:16] */ + u32 iqm_sm_ep_soc_cp_dat_crdt_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_sm_ep_soc_crdt_bp_u; + +/* Define the union csr_iqm_qu_ep_dp_crdt_bp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_dp_crdt_bp0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_dp_crdt_bp0_u; + +/* Define the union csr_iqm_qu_ep_dp_crdt_bp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_dp_crdt_bp1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_dp_crdt_bp1_u; + +/* Define the union csr_iqm_qu_ep_cp_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_cp_crdt_bp : 8; /* [7:0] */ + u32 rsv_117 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_cp_crdt_bp_u; + +/* Define the union csr_iqm_qu_ep_dp_rr_crdt_bp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_dp_rr_crdt_bp0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_dp_rr_crdt_bp0_u; + +/* Define the union csr_iqm_qu_ep_dp_rr_crdt_bp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_dp_rr_crdt_bp1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_dp_rr_crdt_bp1_u; + +/* Define the union csr_iqm_qu_ep_cp_rr_crdt_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_qu_ep_cp_rr_crdt_bp : 8; /* [7:0] */ + u32 rsv_118 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_qu_ep_cp_rr_crdt_bp_u; + +/* Define the union csr_iqm_flush_icll_cam_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_nmq_cll_flush_done : 1; /* [0] */ + u32 host_nfmq_cll_flush_done : 1; /* [1] */ + u32 host_cmq_ll_flush_done : 1; /* [2] */ + u32 soc_mq_ll_flush_done : 1; /* [3] */ + u32 sm_cam_flush_done : 1; /* [4] */ + u32 iqm_qu_sl_fifo_flush_done : 1; /* [5] */ + u32 iqm_sm_sl_fifo_flush_done : 1; /* [6] */ + u32 iqm_sm_cp_crr_fifo_flush_done : 1; /* [7] */ + u32 iqm_sm_dp_crr_fifo_flush_done : 1; /* [8] */ + u32 rsv_119 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_flush_icll_cam_done_u; + +/* Define the union csr_iqm_aging_nmq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_aging_nmq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_nmq_cnt_u; + +/* Define the union csr_iqm_aging_nfmq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_aging_nfmq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_nfmq_cnt_u; + +/* Define the union csr_iqm_aging_discard_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_aging_discard_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_aging_discard_cnt_u; + +/* Define the union csr_iqm_to_eqm_qd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_to_eqm_qd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_to_eqm_qd_cnt_u; + +/* Define the union csr_iqm_deq_sm_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_deq_to_sm_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_deq_sm_cnt_u; + +/* Define the union csr_iqm_deq_qu_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_deq_to_qu_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_deq_qu_cnt_u; + +/* Define the union csr_msc_iqm_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_iqm_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_iqm_deq_cnt_u; + +/* Define the union csr_iqm_nmqnfmq_enq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmqnfmq_enq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmqnfmq_enq_cnt_u; + +/* Define the union csr_iqm_nmqnfmq_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_nmqnfmq_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_nmqnfmq_deq_cnt_u; + +/* Define the union csr_iqm_cmq_enq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_enq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_enq_cnt_u; + +/* Define the union csr_iqm_cmq_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_cmq_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_cmq_deq_cnt_u; + +/* Define the union csr_soc_msc_iqm_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soc_msc_iqm_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_msc_iqm_deq_cnt_u; + +/* Define the union csr_iqm_unmq_enq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_unmq_enq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_unmq_enq_cnt_u; + +/* Define the union csr_iqm_unmq_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_unmq_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_unmq_deq_cnt_u; + +/* Define the union csr_iqm_ucmq_enq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ucmq_enq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_ucmq_enq_cnt_u; + +/* Define the union csr_iqm_ucmq_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ucmq_deq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_ucmq_deq_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_host_sge_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_host_sge_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_host_sge_crdt_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_host_dat_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_host_dat_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_host_dat_crdt_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_ep_dp_sge_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_ep_dp_sge_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_ep_dp_sge_crdt_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_ep_cp_sge_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_ep_cp_sge_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_ep_cp_sge_crdt_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_ep_dp_dat_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_ep_dp_dat_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_ep_dp_dat_crdt_cnt_u; + +/* Define the union csr_iqm_rx_cpi_comp_ep_cp_dat_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_cpi_ep_cp_dat_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_cpi_comp_ep_cp_dat_crdt_cnt_u; + +/* Define the union csr_iqm_rx_qu_comp_ep_dp_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_qu_ep_dp_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_qu_comp_ep_dp_crdt_cnt_u; + +/* Define the union csr_iqm_rx_qu_comp_ep_cp_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_rx_qu_ep_cp_comp_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_rx_qu_comp_ep_cp_crdt_cnt_u; + +/* Define the union csr_iqm_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_ecc_1bit_err_cnt_u; + +/* Define the union csr_iqm_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_iqm_ecc_2bit_err_cnt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_iqm_rw_rsv0_u iqm_rw_rsv0; /* 0 */ + volatile csr_iqm_rw_rsv1_u iqm_rw_rsv1; /* 4 */ + volatile csr_iqm_rw_rsv2_u iqm_rw_rsv2; /* 8 */ + volatile csr_iqm_rw_rsv3_u iqm_rw_rsv3; /* C */ + volatile csr_iqm_indrect_ctrl_u iqm_indrect_ctrl; /* 10 */ + volatile csr_iqm_indrect_timeout_u iqm_indrect_timeout; /* 14 */ + volatile csr_iqm_indrect_data_0_u iqm_indrect_data_0; /* 18 */ + volatile csr_iqm_indrect_data_1_u iqm_indrect_data_1; /* 1C */ + volatile csr_iqm_int_vector_u iqm_int_vector; /* 20 */ + volatile csr_iqm_int_u iqm_int; /* 24 */ + volatile csr_iqm_int_en_u iqm_int_en; /* 28 */ + volatile csr_iqm_mem_ecc0_u iqm_mem_ecc0; /* 2C */ + volatile csr_iqm_mem_ecc1_u iqm_mem_ecc1; /* 30 */ + volatile csr_iqm_aging_int_u iqm_aging_int; /* 34 */ + volatile csr_iqm_cmq_deq_empty_int_u iqm_cmq_deq_empty_int; /* 38 */ + volatile csr_iqm_fifo_wr_ovfl_int_u iqm_fifo_wr_ovfl_int; /* 3C */ + volatile csr_iqm_fifo_rd_udfl_int_u iqm_fifo_rd_udfl_int; /* 40 */ + volatile csr_iqm_free_rsc_bmp_overflow_int_u iqm_free_rsc_bmp_overflow_int; /* 44 */ + volatile csr_iqm_cll_deq_empty_int_u iqm_cll_deq_empty_int; /* 48 */ + volatile csr_iqm_uxmq_deq_empty_int_u iqm_uxmq_deq_empty_int; /* 4C */ + volatile csr_iqm_fifo_int_req1_u iqm_fifo_int_req1; /* 50 */ + volatile csr_iqm_fifo_int_req2_u iqm_fifo_int_req2; /* 54 */ + volatile csr_iqm_fifo_int_req3_u iqm_fifo_int_req3; /* 58 */ + volatile csr_iqm_fifo_int_req4_u iqm_fifo_int_req4; /* 5C */ + volatile csr_iqm_mem_ecc_req0_u iqm_mem_ecc_req0; /* 60 */ + volatile csr_iqm_mem_ecc_req1_u iqm_mem_ecc_req1; /* 64 */ + volatile csr_iqm_uncrt_int_en_u iqm_uncrt_int_en; /* 68 */ + volatile csr_iqm_fifo_int_req5_u iqm_fifo_int_req5; /* 6C */ + volatile csr_iqm_fifo_int_req6_u iqm_fifo_int_req6; /* 70 */ + volatile csr_iqm_fifo_int_req7_u iqm_fifo_int_req7; /* 74 */ + volatile csr_iqm_fifo_int_req8_u iqm_fifo_int_req8; /* 78 */ + volatile csr_iqm_fifo_int_req9_u iqm_fifo_int_req9; /* 7C */ + volatile csr_iqm_chunk_u iqm_chunk; /* 80 */ + volatile csr_iqm_out_fifo_th_gap_u iqm_out_fifo_th_gap; /* 84 */ + volatile csr_iqm_enq_fifo_aful_gap_u iqm_enq_fifo_aful_gap; /* 88 */ + volatile csr_iqm_crdt_comp_fifo_gap_cfg_u iqm_crdt_comp_fifo_gap_cfg; /* 8C */ + volatile csr_iqm_aging_cfg_u iqm_aging_cfg; /* 90 */ + volatile csr_iqm_des_que_deq_cfg0_u iqm_des_que_deq_cfg0; /* 94 */ + volatile csr_iqm_des_que_deq_cfg1_u iqm_des_que_deq_cfg1; /* 98 */ + volatile csr_iqm_root_thr_cfg_u iqm_root_thr_cfg; /* 9C */ + volatile csr_iqm_root_hthr_cfg_u iqm_root_hthr_cfg; /* A0 */ + volatile csr_iqm_nmq_root_thr_cfg_u iqm_nmq_root_thr_cfg; /* A4 */ + volatile csr_iqm_nfmq_root_thr_cfg_u iqm_nfmq_root_thr_cfg; /* A8 */ + volatile csr_iqm_nmq_host0_th_u iqm_nmq_host0_th; /* AC */ + volatile csr_iqm_nmq_host1_th_u iqm_nmq_host1_th; /* B0 */ + volatile csr_iqm_nmq_host2_th_u iqm_nmq_host2_th; /* B4 */ + volatile csr_iqm_nmq_host3_th_u iqm_nmq_host3_th; /* B8 */ + volatile csr_iqm_nmq_host_hth_pa_u iqm_nmq_host_hth_pa; /* BC */ + volatile csr_iqm_nfmq_host0_th_u iqm_nfmq_host0_th; /* C0 */ + volatile csr_iqm_nfmq_host1_th_u iqm_nfmq_host1_th; /* C4 */ + volatile csr_iqm_nfmq_host2_th_u iqm_nfmq_host2_th; /* C8 */ + volatile csr_iqm_nfmq_host3_th_u iqm_nfmq_host3_th; /* CC */ + volatile csr_iqm_nfmq_host_hth_pa_u iqm_nfmq_host_hth_pa; /* D0 */ + volatile csr_iqm_nmq_hex_pro_map_u iqm_nmq_hex_pro_map[4]; /* D4 */ + volatile csr_iqm_nfmq_hex_pro_map_u iqm_nfmq_hex_pro_map[4]; /* E4 */ + volatile csr_iqm_he_th_pro_u iqm_he_th_pro[16]; /* F4 */ + volatile csr_iqm_he_fac_pro_u iqm_he_fac_pro[16]; /* 134 */ + volatile csr_iqm_qtss_cfg_u iqm_qtss_cfg; /* 174 */ + volatile csr_iqm_hetss_cfg_u iqm_hetss_cfg; /* 178 */ + volatile csr_iqm_hectss_cfg_u iqm_hectss_cfg; /* 17C */ + volatile csr_iqm_sm_host_credit_th_u iqm_sm_host_credit_th[5]; /* 180 */ + volatile csr_iqm_sm_credit_tss_cfg_data_u iqm_sm_credit_tss_cfg_data; /* 194 */ + volatile csr_iqm_sm_credit_tss_cfg_sge_u iqm_sm_credit_tss_cfg_sge; /* 198 */ + volatile csr_iqm_qu_credit_tss_cfg_u iqm_qu_credit_tss_cfg; /* 19C */ + volatile csr_iqm_crr_wgt_cfg_u iqm_crr_wgt_cfg; /* 1A0 */ + volatile csr_iqm_db_merger_cfg_u iqm_db_merger_cfg; /* 1A4 */ + volatile csr_smf_dst_hash_cfg_u smf_dst_hash_cfg; /* 1A8 */ + volatile csr_iqm_aging_clr_cfg_u iqm_aging_clr_cfg; /* 1AC */ + volatile csr_iqm_mem_ecc_bypass_en_u iqm_mem_ecc_bypass_en; /* 1B0 */ + volatile csr_iqm_mem_ctrl_bus_cfg0_u iqm_mem_ctrl_bus_cfg0; /* 1B4 */ + volatile csr_iqm_mem_ctrl_bus_cfg1_u iqm_mem_ctrl_bus_cfg1; /* 1B8 */ + volatile csr_iqm_mem_ctrl_bus_cfg2_u iqm_mem_ctrl_bus_cfg2; /* 1BC */ + volatile csr_iqm_mem_ctrl_bus_cfg3_u iqm_mem_ctrl_bus_cfg3; /* 1C0 */ + volatile csr_iqm_mem_ctrl_bus_cfg4_u iqm_mem_ctrl_bus_cfg4; /* 1C4 */ + volatile csr_iqm_sm_shallow_fifo_status_u iqm_sm_shallow_fifo_status[14]; /* 1E0 */ + volatile csr_iqm_qu_shallow_fifo_status_u iqm_qu_shallow_fifo_status[18]; /* 218 */ + volatile csr_iqm_cmq_cnt_u iqm_cmq_cnt; /* 260 */ + volatile csr_iqm_cmq_host_cnt0_u iqm_cmq_host_cnt0; /* 264 */ + volatile csr_iqm_cmq_host_cnt1_u iqm_cmq_host_cnt1; /* 268 */ + volatile csr_iqm_cmq_hostepx_cnt_u iqm_cmq_hostepx_cnt[32]; /* 26C */ + volatile csr_iqm_rootx_cnt_u iqm_rootx_cnt; /* 2EC */ + volatile csr_iqm_nmq_hostx_cnt0_u iqm_nmq_hostx_cnt0; /* 2F0 */ + volatile csr_iqm_nmq_hostx_cnt1_u iqm_nmq_hostx_cnt1; /* 2F4 */ + volatile csr_iqm_nfmq_hostx_cnt0_u iqm_nfmq_hostx_cnt0; /* 2F8 */ + volatile csr_iqm_nfmq_hostx_cnt1_u iqm_nfmq_hostx_cnt1; /* 2FC */ + volatile csr_iqm_mq_hex_cnt_u iqm_mq_hex_cnt[32]; /* 300 */ + volatile csr_iqm_ucmq_root_cnt_u iqm_ucmq_root_cnt; /* 380 */ + volatile csr_iqm_unmq_root_cnt_u iqm_unmq_root_cnt; /* 384 */ + volatile csr_iqm_uxmq_ep_cnt_u iqm_uxmq_ep_cnt[8]; /* 388 */ + volatile csr_iqm_uxmq_queue_cnt_u iqm_uxmq_queue_cnt[64]; /* 3A8 */ + volatile csr_eqm_enq_fifo_status_u eqm_enq_fifo_status; /* 4A8 */ + volatile csr_deqc_enq_fifo_status_u deqc_enq_fifo_status; /* 4AC */ + volatile csr_iqm_enqc_enq_fifo_status_u iqm_enqc_enq_fifo_status; /* 4B0 */ + volatile csr_iqm_enqc_soc_enq_fifo_status_u iqm_enqc_soc_enq_fifo_status; /* 4B4 */ + volatile csr_iqm_cpi_sge_crdt_comp_fifo_status_u iqm_cpi_sge_crdt_comp_fifo_status; /* 4B8 */ + volatile csr_iqm_cpi_data_crdt_comp_fifo_status_u iqm_cpi_data_crdt_comp_fifo_status; /* 4BC */ + volatile csr_iqm_sm_crdt_comp_fifo_status_u iqm_sm_crdt_comp_fifo_status; /* 4C0 */ + volatile csr_iqm_sm_out_fifo_status_u iqm_sm_out_fifo_status; /* 4C4 */ + volatile csr_iqm_qu_crdt_comp_fifo_status_u iqm_qu_crdt_comp_fifo_status; /* 4C8 */ + volatile csr_icll_free_cnt_u icll_free_cnt; /* 4CC */ + volatile csr_iqm_sm_total_cam_cnt_u iqm_sm_total_cam_cnt; /* 4D0 */ + volatile csr_iqm_sm_host_crdt_bp_u iqm_sm_host_crdt_bp; /* 4D4 */ + volatile csr_iqm_sm_ep_host_dp_rr_sge_crdt_bp_u iqm_sm_ep_host_dp_rr_sge_crdt_bp; /* 4D8 */ + volatile csr_iqm_sm_ep_host_dp_rr_dat_crdt_bp_u iqm_sm_ep_host_dp_rr_dat_crdt_bp; /* 4DC */ + volatile csr_iqm_sm_ep_host_dp_sge_crdt_bp_u iqm_sm_ep_host_dp_sge_crdt_bp; /* 4E0 */ + volatile csr_iqm_sm_ep_host_dp_dat_crdt_bp_u iqm_sm_ep_host_dp_dat_crdt_bp; /* 4E4 */ + volatile csr_iqm_sm_ep_host_cp_rr_crdt_bp_u iqm_sm_ep_host_cp_rr_crdt_bp; /* 4E8 */ + volatile csr_iqm_sm_ep_soc_rr_crdt_bp_u iqm_sm_ep_soc_rr_crdt_bp; /* 4EC */ + volatile csr_iqm_sm_ep_host_cp_crdt_bp_u iqm_sm_ep_host_cp_crdt_bp; /* 4F0 */ + volatile csr_iqm_sm_ep_soc_crdt_bp_u iqm_sm_ep_soc_crdt_bp; /* 4F4 */ + volatile csr_iqm_qu_ep_dp_crdt_bp0_u iqm_qu_ep_dp_crdt_bp0; /* 4F8 */ + volatile csr_iqm_qu_ep_dp_crdt_bp1_u iqm_qu_ep_dp_crdt_bp1; /* 4FC */ + volatile csr_iqm_qu_ep_cp_crdt_bp_u iqm_qu_ep_cp_crdt_bp; /* 500 */ + volatile csr_iqm_qu_ep_dp_rr_crdt_bp0_u iqm_qu_ep_dp_rr_crdt_bp0; /* 504 */ + volatile csr_iqm_qu_ep_dp_rr_crdt_bp1_u iqm_qu_ep_dp_rr_crdt_bp1; /* 508 */ + volatile csr_iqm_qu_ep_cp_rr_crdt_bp_u iqm_qu_ep_cp_rr_crdt_bp; /* 50C */ + volatile csr_iqm_flush_icll_cam_done_u iqm_flush_icll_cam_done; /* 510 */ + volatile csr_iqm_aging_nmq_cnt_u iqm_aging_nmq_cnt; /* B38 */ + volatile csr_iqm_aging_nfmq_cnt_u iqm_aging_nfmq_cnt; /* B3C */ + volatile csr_iqm_aging_discard_cnt_u iqm_aging_discard_cnt; /* B40 */ + volatile csr_iqm_to_eqm_qd_cnt_u iqm_to_eqm_qd_cnt; /* B44 */ + volatile csr_iqm_deq_sm_cnt_u iqm_deq_sm_cnt; /* B48 */ + volatile csr_iqm_deq_qu_cnt_u iqm_deq_qu_cnt; /* B4C */ + volatile csr_msc_iqm_deq_cnt_u msc_iqm_deq_cnt; /* B50 */ + volatile csr_iqm_nmqnfmq_enq_cnt_u iqm_nmqnfmq_enq_cnt; /* B54 */ + volatile csr_iqm_nmqnfmq_deq_cnt_u iqm_nmqnfmq_deq_cnt; /* B58 */ + volatile csr_iqm_cmq_enq_cnt_u iqm_cmq_enq_cnt; /* B5C */ + volatile csr_iqm_cmq_deq_cnt_u iqm_cmq_deq_cnt; /* B60 */ + volatile csr_soc_msc_iqm_deq_cnt_u soc_msc_iqm_deq_cnt; /* B64 */ + volatile csr_iqm_unmq_enq_cnt_u iqm_unmq_enq_cnt; /* B68 */ + volatile csr_iqm_unmq_deq_cnt_u iqm_unmq_deq_cnt; /* B6C */ + volatile csr_iqm_ucmq_enq_cnt_u iqm_ucmq_enq_cnt; /* B70 */ + volatile csr_iqm_ucmq_deq_cnt_u iqm_ucmq_deq_cnt; /* B74 */ + volatile csr_iqm_rx_cpi_comp_host_sge_crdt_cnt_u iqm_rx_cpi_comp_host_sge_crdt_cnt; /* B78 */ + volatile csr_iqm_rx_cpi_comp_host_dat_crdt_cnt_u iqm_rx_cpi_comp_host_dat_crdt_cnt; /* B7C */ + volatile csr_iqm_rx_cpi_comp_ep_dp_sge_crdt_cnt_u iqm_rx_cpi_comp_ep_dp_sge_crdt_cnt; /* B80 */ + volatile csr_iqm_rx_cpi_comp_ep_cp_sge_crdt_cnt_u iqm_rx_cpi_comp_ep_cp_sge_crdt_cnt; /* B84 */ + volatile csr_iqm_rx_cpi_comp_ep_dp_dat_crdt_cnt_u iqm_rx_cpi_comp_ep_dp_dat_crdt_cnt; /* B88 */ + volatile csr_iqm_rx_cpi_comp_ep_cp_dat_crdt_cnt_u iqm_rx_cpi_comp_ep_cp_dat_crdt_cnt; /* B8C */ + volatile csr_iqm_rx_qu_comp_ep_dp_crdt_cnt_u iqm_rx_qu_comp_ep_dp_crdt_cnt; /* B90 */ + volatile csr_iqm_rx_qu_comp_ep_cp_crdt_cnt_u iqm_rx_qu_comp_ep_cp_crdt_cnt; /* B94 */ + volatile csr_iqm_ecc_1bit_err_cnt_u iqm_ecc_1bit_err_cnt; /* B98 */ + volatile csr_iqm_ecc_2bit_err_cnt_u iqm_ecc_2bit_err_cnt; /* B9C */ +} S_mqm_iqm_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_iqm */ +extern volatile S_mqm_iqm_REGS_TYPE *gopmqm_iqmAllReg; + +/* Declare the functions that set the member value */ +int iSetIQM_RW_RSV0_iqm_rw_rsv0(unsigned int uiqm_rw_rsv0); +int iSetIQM_RW_RSV1_iqm_rw_rsv1(unsigned int uiqm_rw_rsv1); +int iSetIQM_RW_RSV2_iqm_rw_rsv2(unsigned int uiqm_rw_rsv2); +int iSetIQM_RW_RSV3_iqm_rw_rsv3(unsigned int uiqm_rw_rsv3); +int iSetIQM_INDRECT_CTRL_iqm_indrect_addr(unsigned int uiqm_indrect_addr); +int iSetIQM_INDRECT_CTRL_iqm_indrect_tab(unsigned int uiqm_indrect_tab); +int iSetIQM_INDRECT_CTRL_iqm_indrect_status(unsigned int uiqm_indrect_status); +int iSetIQM_INDRECT_CTRL_iqm_indrect_mode(unsigned int uiqm_indrect_mode); +int iSetIQM_INDRECT_CTRL_iqm_indrect_vld(unsigned int uiqm_indrect_vld); +int iSetIQM_INDRECT_TIMEOUT_iqm_indrect_timeout(unsigned int uiqm_indrect_timeout); +int iSetIQM_INDRECT_DATA_0_iqm_indrect_data_0(unsigned int uiqm_indrect_data_0); +int iSetIQM_INDRECT_DATA_1_iqm_indrect_data_1(unsigned int uiqm_indrect_data_1); +int iSetIQM_INT_VECTOR_iqm_cpi_int_index(unsigned int uiqm_cpi_int_index); +int iSetIQM_INT_VECTOR_iqm_enable(unsigned int uiqm_enable); +int iSetIQM_INT_VECTOR_iqm_int_issue(unsigned int uiqm_int_issue); +int iSetIQM_INT_iqm_int_data(unsigned int uiqm_int_data); +int iSetIQM_INT_iqm_program_csr_id_ro(unsigned int uiqm_program_csr_id_ro); +int iSetIQM_INT_EN_iqm_int_en(unsigned int uiqm_int_en); +int iSetIQM_INT_EN_iqm_program_csr_id(unsigned int uiqm_program_csr_id); +int iSetIQM_MEM_ECC0_iqm_ecc0_err(unsigned int uiqm_ecc0_err); +int iSetIQM_MEM_ECC0_iqm_ecc0_err_insert(unsigned int uiqm_ecc0_err_insert); +int iSetIQM_MEM_ECC0_iqm_ecc0_err_info(unsigned int uiqm_ecc0_err_info); +int iSetIQM_MEM_ECC1_iqm_ecc1_err(unsigned int uiqm_ecc1_err); +int iSetIQM_MEM_ECC1_iqm_ecc1_err_insert(unsigned int uiqm_ecc1_err_insert); +int iSetIQM_MEM_ECC1_iqm_ecc1_err_info(unsigned int uiqm_ecc1_err_info); +int iSetIQM_AGING_INT_iqm_aging_int_err(unsigned int uiqm_aging_int_err); +int iSetIQM_AGING_INT_iqm_aging_int_err_insert(unsigned int uiqm_aging_int_err_insert); +int iSetIQM_AGING_INT_iqm_aging_int_err_info(unsigned int uiqm_aging_int_err_info); +int iSetIQM_CMQ_DEQ_EMPTY_INT_iqm_cmq_deq_empty_err(unsigned int uiqm_cmq_deq_empty_err); +int iSetIQM_CMQ_DEQ_EMPTY_INT_iqm_cmq_deq_empty_err_insert(unsigned int uiqm_cmq_deq_empty_err_insert); +int iSetIQM_CMQ_DEQ_EMPTY_INT_iqm_cmq_deq_empty_err_info(unsigned int uiqm_cmq_deq_empty_err_info); +int iSetIQM_FIFO_WR_OVFL_INT_iqm_fifo_wr_ovfl_err(unsigned int uiqm_fifo_wr_ovfl_err); +int iSetIQM_FIFO_WR_OVFL_INT_iqm_fifo_wr_ovfl_err_insert(unsigned int uiqm_fifo_wr_ovfl_err_insert); +int iSetIQM_FIFO_WR_OVFL_INT_iqm_fifo_wr_ovfl_err_info(unsigned int uiqm_fifo_wr_ovfl_err_info); +int iSetIQM_FIFO_RD_UDFL_INT_iqm_fifo_rd_udfl_err(unsigned int uiqm_fifo_rd_udfl_err); +int iSetIQM_FIFO_RD_UDFL_INT_iqm_fifo_rd_udfl_err_insert(unsigned int uiqm_fifo_rd_udfl_err_insert); +int iSetIQM_FIFO_RD_UDFL_INT_iqm_fifo_rd_udfl_err_info(unsigned int uiqm_fifo_rd_udfl_err_info); +int iSetIQM_FREE_RSC_BMP_OVERFLOW_INT_iqm_free_rsc_bmp_ovfl_err(unsigned int uiqm_free_rsc_bmp_ovfl_err); +int iSetIQM_FREE_RSC_BMP_OVERFLOW_INT_iqm_free_rsc_bmp_ovfl_err_insert(unsigned int uiqm_free_rsc_bmp_ovfl_err_insert); +int iSetIQM_FREE_RSC_BMP_OVERFLOW_INT_iqm_free_rsc_bmp_ovfl_err_info(unsigned int uiqm_free_rsc_bmp_ovfl_err_info); +int iSetIQM_CLL_DEQ_EMPTY_INT_iqm_nmqnfmq_deq_empty_err(unsigned int uiqm_nmqnfmq_deq_empty_err); +int iSetIQM_CLL_DEQ_EMPTY_INT_iqm_nmqnfmq_deq_empty_err_insert(unsigned int uiqm_nmqnfmq_deq_empty_err_insert); +int iSetIQM_CLL_DEQ_EMPTY_INT_iqm_nmqnfmq_deq_empty_err_info(unsigned int uiqm_nmqnfmq_deq_empty_err_info); +int iSetIQM_UXMQ_DEQ_EMPTY_INT_iqm_uxmq_deq_empty_err(unsigned int uiqm_uxmq_deq_empty_err); +int iSetIQM_UXMQ_DEQ_EMPTY_INT_iqm_uxmq_deq_empty_err_insert(unsigned int uiqm_uxmq_deq_empty_err_insert); +int iSetIQM_UXMQ_DEQ_EMPTY_INT_iqm_uxmq_deq_empty_err_info(unsigned int uiqm_uxmq_deq_empty_err_info); +int iSetIQM_FIFO_INT_REQ1_sm_shallow_fifo_rd_udfl_insert0(unsigned int usm_shallow_fifo_rd_udfl_insert0); +int iSetIQM_FIFO_INT_REQ2_qu_shallow_fifo_rd_udfl_insert2(unsigned int uqu_shallow_fifo_rd_udfl_insert2); +int iSetIQM_FIFO_INT_REQ2_sm_shallow_fifo_rd_udfl_insert1(unsigned int usm_shallow_fifo_rd_udfl_insert1); +int iSetIQM_FIFO_INT_REQ3_qu_shallow_fifo_rd_udfl_insert0(unsigned int uqu_shallow_fifo_rd_udfl_insert0); +int iSetIQM_FIFO_INT_REQ4_qu_shallow_fifo_rd_udfl_insert1(unsigned int uqu_shallow_fifo_rd_udfl_insert1); +int iSetIQM_MEM_ECC_REQ0_cll_head_mem_err_req(unsigned int ucll_head_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cll_tail_mem_err_req(unsigned int ucll_tail_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cll_mqle_mem_err_req(unsigned int ucll_mqle_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cll_ckll_mem_err_req(unsigned int ucll_ckll_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_mq2vf_mem_err_req(unsigned int umq2vf_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cll_faptab_mem_err_req(unsigned int ucll_faptab_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_pre_enq_qlen_mem_err_req(unsigned int upre_enq_qlen_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_que_pro_map_mem_err_req(unsigned int uque_pro_map_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_pre_enq_hec_len_mem_err_req(unsigned int upre_enq_hec_len_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cmq_ll_head_mem_err_req(unsigned int ucmq_ll_head_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cmq_ll_tail_mem_err_req(unsigned int ucmq_ll_tail_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cmq_queue_len_mem_err_req(unsigned int ucmq_queue_len_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cmq_ll_mem_err_req(unsigned int ucmq_ll_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_cmq_hec_len_mem_err_req(unsigned int ucmq_hec_len_mem_err_req); +int iSetIQM_MEM_ECC_REQ0_ill_soc_ll_err_req(unsigned int uill_soc_ll_err_req); +int iSetIQM_MEM_ECC_REQ1_soc_qd_err_req(unsigned int usoc_qd_err_req); +int iSetIQM_MEM_ECC_REQ1_deq_sm_fifo_mem_err_req(unsigned int udeq_sm_fifo_mem_err_req); +int iSetIQM_MEM_ECC_REQ1_deq_qu_fifo_mem_err_req(unsigned int udeq_qu_fifo_mem_err_req); +int iSetIQM_MEM_ECC_REQ1_iqm_agcnt_err_req(unsigned int uiqm_agcnt_err_req); +int iSetIQM_MEM_ECC_REQ1_iqm_agvld_err_req(unsigned int uiqm_agvld_err_req); +int iSetIQM_UNCRT_INT_EN_cll_rsc_overflow_uncrt_int_en(unsigned int ucll_rsc_overflow_uncrt_int_en); +int iSetIQM_UNCRT_INT_EN_cll_deq_empty_uncrt_int_en(unsigned int ucll_deq_empty_uncrt_int_en); +int iSetIQM_UNCRT_INT_EN_cmq_deq_empty_uncrt_int_en(unsigned int ucmq_deq_empty_uncrt_int_en); +int iSetIQM_UNCRT_INT_EN_uxmq_deq_empty_uncrt_int_en(unsigned int uuxmq_deq_empty_uncrt_int_en); +int iSetIQM_FIFO_INT_REQ5_sm_shallow_fifo_wr_ovfl_insert0(unsigned int usm_shallow_fifo_wr_ovfl_insert0); +int iSetIQM_FIFO_INT_REQ6_qu_shallow_fifo_wr_ovfl_insert2(unsigned int uqu_shallow_fifo_wr_ovfl_insert2); +int iSetIQM_FIFO_INT_REQ6_sm_shallow_fifo_wr_ovfl_insert1(unsigned int usm_shallow_fifo_wr_ovfl_insert1); +int iSetIQM_FIFO_INT_REQ7_qu_shallow_fifo_wr_ovfl_insert0(unsigned int uqu_shallow_fifo_wr_ovfl_insert0); +int iSetIQM_FIFO_INT_REQ8_qu_shallow_fifo_wr_ovfl_insert1(unsigned int uqu_shallow_fifo_wr_ovfl_insert1); +int iSetIQM_FIFO_INT_REQ9_enqc_enq_fifo_wr_ovfl_insert(unsigned int uenqc_enq_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_enqc_enq_fifo_rd_udfl_insert(unsigned int uenqc_enq_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_eqm_enq_fifo_wr_ovfl_insert(unsigned int ueqm_enq_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_eqm_enq_fifo_rd_udfl_insert(unsigned int ueqm_enq_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_deqc_enq_fifo_wr_ovfl_insert(unsigned int udeqc_enq_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_deqc_enq_fifo_rd_udfl_insert(unsigned int udeqc_enq_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_enqc_enq_soc_fifo_wr_ovfl_insert(unsigned int uenqc_enq_soc_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_enqc_enq_soc_fifo_rd_udfl_insert(unsigned int uenqc_enq_soc_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_dp_out_fifo_wr_ovfl_insert(unsigned int usm_dp_out_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_dp_out_fifo_rd_udfl_insert(unsigned int usm_dp_out_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_cp_out_fifo_wr_ovfl_insert(unsigned int usm_cp_out_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_cp_out_fifo_rd_udfl_insert(unsigned int usm_cp_out_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_ep_sge_fifo_wr_ovfl_insert(unsigned int ucpi_ep_sge_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_ep_sge_fifo_rd_udfl_insert(unsigned int ucpi_ep_sge_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_host_sge_fifo_wr_ovfl_insert(unsigned int ucpi_host_sge_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_host_sge_fifo_rd_udfl_insert(unsigned int ucpi_host_sge_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_data_fifo_wr_ovfl_insert(unsigned int ucpi_data_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_cpi_data_fifo_rd_udfl_insert(unsigned int ucpi_data_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_data_fifo_wr_ovfl_insert(unsigned int usm_data_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_data_fifo_rd_udfl_insert(unsigned int usm_data_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_sge_fifo_wr_ovfl_insert(unsigned int usm_sge_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_sm_sge_fifo_rd_udfl_insert(unsigned int usm_sge_fifo_rd_udfl_insert); +int iSetIQM_FIFO_INT_REQ9_qu_ep_fifo_wr_ovfl_insert(unsigned int uqu_ep_fifo_wr_ovfl_insert); +int iSetIQM_FIFO_INT_REQ9_qu_ep_fifo_rd_udfl_insert(unsigned int uqu_ep_fifo_rd_udfl_insert); +int iSetIQM_CHUNK_chunk_size(unsigned int uchunk_size); +int iSetIQM_CHUNK_icll_bitmap_critical_depth(unsigned int uicll_bitmap_critical_depth); +int iSetIQM_OUT_FIFO_TH_GAP_iqm_deq_sm_ctrl_plane_aful_gap(unsigned int uiqm_deq_sm_ctrl_plane_aful_gap); +int iSetIQM_OUT_FIFO_TH_GAP_iqm_deq_sm_data_plane_aful_gap(unsigned int uiqm_deq_sm_data_plane_aful_gap); +int iSetIQM_OUT_FIFO_TH_GAP_iqm_qu_shallow_fifo_gap(unsigned int uiqm_qu_shallow_fifo_gap); +int iSetIQM_OUT_FIFO_TH_GAP_iqm_sm_shallow_fifo_gap(unsigned int uiqm_sm_shallow_fifo_gap); +int iSetIQM_ENQ_FIFO_AFUL_GAP_enqc_enq_fifo_afull_gap(unsigned int uenqc_enq_fifo_afull_gap); +int iSetIQM_ENQ_FIFO_AFUL_GAP_eqm_enq_fifo_afull_gap(unsigned int ueqm_enq_fifo_afull_gap); +int iSetIQM_ENQ_FIFO_AFUL_GAP_deqc_enq_fifo_afull_gap(unsigned int udeqc_enq_fifo_afull_gap); +int iSetIQM_ENQ_FIFO_AFUL_GAP_enqc_enq_soc_fifo_afull_gap(unsigned int uenqc_enq_soc_fifo_afull_gap); +int iSetIQM_CRDT_COMP_FIFO_GAP_CFG_sm_data_aful_gap(unsigned int usm_data_aful_gap); +int iSetIQM_CRDT_COMP_FIFO_GAP_CFG_sm_sge_aful_gap(unsigned int usm_sge_aful_gap); +int iSetIQM_CRDT_COMP_FIFO_GAP_CFG_cpi_data_aful_gap(unsigned int ucpi_data_aful_gap); +int iSetIQM_CRDT_COMP_FIFO_GAP_CFG_cpi_host_sge_aful_gap(unsigned int ucpi_host_sge_aful_gap); +int iSetIQM_CRDT_COMP_FIFO_GAP_CFG_cpi_ep_sge_aful_gap(unsigned int ucpi_ep_sge_aful_gap); +int iSetIQM_AGING_CFG_nmq_aging_en(unsigned int unmq_aging_en); +int iSetIQM_AGING_CFG_nfmq_aging_en(unsigned int unfmq_aging_en); +int iSetIQM_AGING_CFG_aging_intval(unsigned int uaging_intval); +int iSetIQM_AGING_CFG_aging_dest(unsigned int uaging_dest); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_mqid(unsigned int udes_que_deq_mqid); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_qa(unsigned int udes_que_deq_qa); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_src(unsigned int udes_que_deq_src); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_hid(unsigned int udes_que_deq_hid); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_cos(unsigned int udes_que_deq_cos); +int iSetIQM_DES_QUE_DEQ_CFG0_des_que_deq_ep(unsigned int udes_que_deq_ep); +int iSetIQM_DES_QUE_DEQ_CFG1_iqm_des_que_deq_vld(unsigned int uiqm_des_que_deq_vld); +int iSetIQM_DES_QUE_DEQ_CFG1_des_que_deq_vfid(unsigned int udes_que_deq_vfid); +int iSetIQM_ROOT_THR_CFG_root_total_fl_static_th(unsigned int uroot_total_fl_static_th); +int iSetIQM_ROOT_THR_CFG_root_total_sl_static_th(unsigned int uroot_total_sl_static_th); +int iSetIQM_ROOT_HTHR_CFG_root_hth_parm_nmq(unsigned int uroot_hth_parm_nmq); +int iSetIQM_ROOT_HTHR_CFG_root_hth_parm_nfmq(unsigned int uroot_hth_parm_nfmq); +int iSetIQM_ROOT_HTHR_CFG_root_total_hth_parm(unsigned int uroot_total_hth_parm); +int iSetIQM_NMQ_ROOT_THR_CFG_root_fl_static_th_nmq(unsigned int uroot_fl_static_th_nmq); +int iSetIQM_NMQ_ROOT_THR_CFG_root_sl_static_th_nmq(unsigned int uroot_sl_static_th_nmq); +int iSetIQM_NFMQ_ROOT_THR_CFG_root_fl_static_th_nfmq(unsigned int uroot_fl_static_th_nfmq); +int iSetIQM_NFMQ_ROOT_THR_CFG_root_sl_static_th_nfmq(unsigned int uroot_sl_static_th_nfmq); +int iSetIQM_NMQ_HOST0_TH_hid0_fl_static_th_nmq(unsigned int uhid0_fl_static_th_nmq); +int iSetIQM_NMQ_HOST0_TH_hid0_sl_static_th_nmq(unsigned int uhid0_sl_static_th_nmq); +int iSetIQM_NMQ_HOST1_TH_hid1_fl_static_th_nmq(unsigned int uhid1_fl_static_th_nmq); +int iSetIQM_NMQ_HOST1_TH_hid1_sl_static_th_nmq(unsigned int uhid1_sl_static_th_nmq); +int iSetIQM_NMQ_HOST2_TH_hid2_fl_static_th_nmq(unsigned int uhid2_fl_static_th_nmq); +int iSetIQM_NMQ_HOST2_TH_hid2_sl_static_th_nmq(unsigned int uhid2_sl_static_th_nmq); +int iSetIQM_NMQ_HOST3_TH_hid3_fl_static_th_nmq(unsigned int uhid3_fl_static_th_nmq); +int iSetIQM_NMQ_HOST3_TH_hid3_sl_static_th_nmq(unsigned int uhid3_sl_static_th_nmq); +int iSetIQM_NMQ_HOST_HTH_PA_hid0_hth_parm_nmq(unsigned int uhid0_hth_parm_nmq); +int iSetIQM_NMQ_HOST_HTH_PA_hid1_hth_parm_nmq(unsigned int uhid1_hth_parm_nmq); +int iSetIQM_NMQ_HOST_HTH_PA_hid2_hth_parm_nmq(unsigned int uhid2_hth_parm_nmq); +int iSetIQM_NMQ_HOST_HTH_PA_hid3_hth_parm_nmq(unsigned int uhid3_hth_parm_nmq); +int iSetIQM_NFMQ_HOST0_TH_hid0_fl_static_th_nfmq(unsigned int uhid0_fl_static_th_nfmq); +int iSetIQM_NFMQ_HOST0_TH_hid0_sl_static_th_nfmq(unsigned int uhid0_sl_static_th_nfmq); +int iSetIQM_NFMQ_HOST1_TH_hid1_fl_static_th_nfmq(unsigned int uhid1_fl_static_th_nfmq); +int iSetIQM_NFMQ_HOST1_TH_hid1_sl_static_th_nfmq(unsigned int uhid1_sl_static_th_nfmq); +int iSetIQM_NFMQ_HOST2_TH_hid2_fl_static_th_nfmq(unsigned int uhid2_fl_static_th_nfmq); +int iSetIQM_NFMQ_HOST2_TH_hid2_sl_static_th_nfmq(unsigned int uhid2_sl_static_th_nfmq); +int iSetIQM_NFMQ_HOST3_TH_hid3_fl_static_th_nfmq(unsigned int uhid3_fl_static_th_nfmq); +int iSetIQM_NFMQ_HOST3_TH_hid3_sl_static_th_nfmq(unsigned int uhid3_sl_static_th_nfmq); +int iSetIQM_NFMQ_HOST_HTH_PA_hid0_hth_parm_nfmq(unsigned int uhid0_hth_parm_nfmq); +int iSetIQM_NFMQ_HOST_HTH_PA_hid1_hth_parm_nfmq(unsigned int uhid1_hth_parm_nfmq); +int iSetIQM_NFMQ_HOST_HTH_PA_hid2_hth_parm_nfmq(unsigned int uhid2_hth_parm_nfmq); +int iSetIQM_NFMQ_HOST_HTH_PA_hid3_hth_parm_nfmq(unsigned int uhid3_hth_parm_nfmq); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_0(unsigned int uhe_pro_map_nmq_0); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_1(unsigned int uhe_pro_map_nmq_1); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_2(unsigned int uhe_pro_map_nmq_2); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_3(unsigned int uhe_pro_map_nmq_3); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_4(unsigned int uhe_pro_map_nmq_4); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_5(unsigned int uhe_pro_map_nmq_5); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_6(unsigned int uhe_pro_map_nmq_6); +int iSetIQM_NMQ_HEX_PRO_MAP_he_pro_map_nmq_7(unsigned int uhe_pro_map_nmq_7); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_0(unsigned int uhe_pro_map_nfmq_0); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_1(unsigned int uhe_pro_map_nfmq_1); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_2(unsigned int uhe_pro_map_nfmq_2); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_3(unsigned int uhe_pro_map_nfmq_3); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_4(unsigned int uhe_pro_map_nfmq_4); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_5(unsigned int uhe_pro_map_nfmq_5); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_6(unsigned int uhe_pro_map_nfmq_6); +int iSetIQM_NFMQ_HEX_PRO_MAP_he_pro_map_nfmq_7(unsigned int uhe_pro_map_nfmq_7); +int iSetIQM_HE_TH_PRO_he_fl_static_th_pro(unsigned int uhe_fl_static_th_pro); +int iSetIQM_HE_TH_PRO_he_sl_static_th_pro(unsigned int uhe_sl_static_th_pro); +int iSetIQM_HE_FAC_PRO_host_ep_fl_a_fact_pro(unsigned int uhost_ep_fl_a_fact_pro); +int iSetIQM_HE_FAC_PRO_host_ep_sl_a_fact_pro(unsigned int uhost_ep_sl_a_fact_pro); +int iSetIQM_HE_FAC_PRO_host_ep_hth_parm_pro(unsigned int uhost_ep_hth_parm_pro); +int iSetIQM_QTSS_CFG_qtsc_fl(unsigned int uqtsc_fl); +int iSetIQM_QTSS_CFG_qtsc_sl(unsigned int uqtsc_sl); +int iSetIQM_HETSS_CFG_he_tsc_fl(unsigned int uhe_tsc_fl); +int iSetIQM_HETSS_CFG_he_tsc_sl(unsigned int uhe_tsc_sl); +int iSetIQM_HECTSS_CFG_hec_tsc_fl(unsigned int uhec_tsc_fl); +int iSetIQM_HECTSS_CFG_hec_tsc_sl(unsigned int uhec_tsc_sl); +int iSetIQM_SM_HOST_CREDIT_TH_iqm_sm_host_credit_data_th(unsigned int uiqm_sm_host_credit_data_th); +int iSetIQM_SM_HOST_CREDIT_TH_iqm_sm_host_credit_sge_th(unsigned int uiqm_sm_host_credit_sge_th); +int iSetIQM_SM_CREDIT_TSS_CFG_DATA_iqm_sm_ep_cp_credit_tss_data(unsigned int uiqm_sm_ep_cp_credit_tss_data); +int iSetIQM_SM_CREDIT_TSS_CFG_DATA_iqm_sm_ep_dp_credit_tss_data(unsigned int uiqm_sm_ep_dp_credit_tss_data); +int iSetIQM_SM_CREDIT_TSS_CFG_SGE_iqm_sm_ep_cp_credit_tss_sge(unsigned int uiqm_sm_ep_cp_credit_tss_sge); +int iSetIQM_SM_CREDIT_TSS_CFG_SGE_iqm_sm_ep_dp_credit_tss_sge(unsigned int uiqm_sm_ep_dp_credit_tss_sge); +int iSetIQM_QU_CREDIT_TSS_CFG_iqm_qu_ep_cp_credit_tss(unsigned int uiqm_qu_ep_cp_credit_tss); +int iSetIQM_QU_CREDIT_TSS_CFG_iqm_qu_ep_dp_credit_tss(unsigned int uiqm_qu_ep_dp_credit_tss); +int iSetIQM_CRR_WGT_CFG_iqm_sm_dp_crr_wgt(unsigned int uiqm_sm_dp_crr_wgt); +int iSetIQM_CRR_WGT_CFG_iqm_sm_cp_crr_wgt(unsigned int uiqm_sm_cp_crr_wgt); +int iSetIQM_CRR_WGT_CFG_iqm_qu_dp_crr_wgt(unsigned int uiqm_qu_dp_crr_wgt); +int iSetIQM_CRR_WGT_CFG_iqm_qu_cp_crr_wgt(unsigned int uiqm_qu_cp_crr_wgt); +int iSetIQM_DB_MERGER_CFG_iqm_db_merger_en(unsigned int uiqm_db_merger_en); +int iSetIQM_DB_MERGER_CFG_iqm_db_merger_num(unsigned int uiqm_db_merger_num); +int iSetIQM_DB_MERGER_CFG_iqm_db_merger_num_sum(unsigned int uiqm_db_merger_num_sum); +int iSetSMF_DST_HASH_CFG_smf_pg_cfg(unsigned int usmf_pg_cfg); +int iSetSMF_DST_HASH_CFG_lbf_mode_sel_cfg(unsigned int ulbf_mode_sel_cfg); +int iSetIQM_AGING_CLR_CFG_mq_ag_clr_mqid(unsigned int umq_ag_clr_mqid); +int iSetIQM_AGING_CLR_CFG_mq_ag_clr_qa(unsigned int umq_ag_clr_qa); +int iSetIQM_AGING_CLR_CFG_mq_ag_clr_vld(unsigned int umq_ag_clr_vld); +int iSetIQM_MEM_ECC_BYPASS_EN_iqm_mem_ecc_bypass(unsigned int uiqm_mem_ecc_bypass); +int iSetIQM_MEM_CTRL_BUS_CFG0_iqm_mem_ctrl_bus_0(unsigned int uiqm_mem_ctrl_bus_0); +int iSetIQM_MEM_CTRL_BUS_CFG1_iqm_mem_ctrl_bus_1(unsigned int uiqm_mem_ctrl_bus_1); +int iSetIQM_MEM_CTRL_BUS_CFG2_iqm_mem_ctrl_bus_2(unsigned int uiqm_mem_ctrl_bus_2); +int iSetIQM_MEM_CTRL_BUS_CFG3_iqm_mem_ctrl_bus_3(unsigned int uiqm_mem_ctrl_bus_3); +int iSetIQM_MEM_CTRL_BUS_CFG4_iqm_mem_ctrl_bus_4(unsigned int uiqm_mem_ctrl_bus_4); +int iSetIQM_SM_SHALLOW_FIFO_STATUS_sm_shallow_fifo_status(unsigned int usm_shallow_fifo_status); +int iSetIQM_QU_SHALLOW_FIFO_STATUS_qu_shallow_fifo_status(unsigned int uqu_shallow_fifo_status); +int iSetIQM_CMQ_CNT_iqm_cmq_root_cnt(unsigned int uiqm_cmq_root_cnt); +int iSetIQM_CMQ_HOST_CNT0_iqm_cmq_host0_cnt(unsigned int uiqm_cmq_host0_cnt); +int iSetIQM_CMQ_HOST_CNT0_iqm_cmq_host1_cnt(unsigned int uiqm_cmq_host1_cnt); +int iSetIQM_CMQ_HOST_CNT1_iqm_cmq_host2_cnt(unsigned int uiqm_cmq_host2_cnt); +int iSetIQM_CMQ_HOST_CNT1_iqm_cmq_host3_cnt(unsigned int uiqm_cmq_host3_cnt); +int iSetIQM_CMQ_HOSTEPX_CNT_iqm_cmq_hostep_cnt(unsigned int uiqm_cmq_hostep_cnt); +int iSetIQM_ROOTX_CNT_iqm_nmq_cnt(unsigned int uiqm_nmq_cnt); +int iSetIQM_ROOTX_CNT_iqm_nfmq_cnt(unsigned int uiqm_nfmq_cnt); +int iSetIQM_NMQ_HOSTX_CNT0_iqm_nmq_host0_cnt(unsigned int uiqm_nmq_host0_cnt); +int iSetIQM_NMQ_HOSTX_CNT0_iqm_nmq_host1_cnt(unsigned int uiqm_nmq_host1_cnt); +int iSetIQM_NMQ_HOSTX_CNT1_iqm_nmq_host2_cnt(unsigned int uiqm_nmq_host2_cnt); +int iSetIQM_NMQ_HOSTX_CNT1_iqm_nmq_host3_cnt(unsigned int uiqm_nmq_host3_cnt); +int iSetIQM_NFMQ_HOSTX_CNT0_iqm_nfmq_host0_cnt(unsigned int uiqm_nfmq_host0_cnt); +int iSetIQM_NFMQ_HOSTX_CNT0_iqm_nfmq_host1_cnt(unsigned int uiqm_nfmq_host1_cnt); +int iSetIQM_NFMQ_HOSTX_CNT1_iqm_nfmq_host2_cnt(unsigned int uiqm_nfmq_host2_cnt); +int iSetIQM_NFMQ_HOSTX_CNT1_iqm_nfmq_host3_cnt(unsigned int uiqm_nfmq_host3_cnt); +int iSetIQM_MQ_HEX_CNT_iqm_nmq_he_cnt(unsigned int uiqm_nmq_he_cnt); +int iSetIQM_MQ_HEX_CNT_iqm_nfmq_he_cnt(unsigned int uiqm_nfmq_he_cnt); +int iSetIQM_UCMQ_ROOT_CNT_iqm_ucmq_root_cnt(unsigned int uiqm_ucmq_root_cnt); +int iSetIQM_UNMQ_ROOT_CNT_iqm_unmq_root_cnt(unsigned int uiqm_unmq_root_cnt); +int iSetIQM_UXMQ_EP_CNT_unmq_qlen_ep(unsigned int uunmq_qlen_ep); +int iSetIQM_UXMQ_EP_CNT_ucmq_qlen_ep(unsigned int uucmq_qlen_ep); +int iSetIQM_UXMQ_QUEUE_CNT_iqm_unmqid_cnt(unsigned int uiqm_unmqid_cnt); +int iSetIQM_UXMQ_QUEUE_CNT_iqm_ucmqid_cnt(unsigned int uiqm_ucmqid_cnt); +int iSetEQM_ENQ_FIFO_STATUS_eqm_enq_fifo_cnt(unsigned int ueqm_enq_fifo_cnt); +int iSetEQM_ENQ_FIFO_STATUS_eqm_enq_fifo_full(unsigned int ueqm_enq_fifo_full); +int iSetEQM_ENQ_FIFO_STATUS_eqm_enq_fifo_aful(unsigned int ueqm_enq_fifo_aful); +int iSetEQM_ENQ_FIFO_STATUS_eqm_enq_fifo_empt(unsigned int ueqm_enq_fifo_empt); +int iSetDEQC_ENQ_FIFO_STATUS_deqc_enq_fifo_cnt(unsigned int udeqc_enq_fifo_cnt); +int iSetDEQC_ENQ_FIFO_STATUS_deqc_enq_fifo_full(unsigned int udeqc_enq_fifo_full); +int iSetDEQC_ENQ_FIFO_STATUS_deqc_enq_fifo_empt(unsigned int udeqc_enq_fifo_empt); +int iSetIQM_ENQC_ENQ_FIFO_STATUS_enqc_enq_fifo_cnt(unsigned int uenqc_enq_fifo_cnt); +int iSetIQM_ENQC_ENQ_FIFO_STATUS_enqc_enq_fifo_full(unsigned int uenqc_enq_fifo_full); +int iSetIQM_ENQC_ENQ_FIFO_STATUS_enqc_enq_fifo_empt(unsigned int uenqc_enq_fifo_empt); +int iSetIQM_ENQC_SOC_ENQ_FIFO_STATUS_enqc_soc_enq_fifo_cnt(unsigned int uenqc_soc_enq_fifo_cnt); +int iSetIQM_ENQC_SOC_ENQ_FIFO_STATUS_enqc_soc_enq_fifo_full(unsigned int uenqc_soc_enq_fifo_full); +int iSetIQM_ENQC_SOC_ENQ_FIFO_STATUS_enqc_soc_enq_fifo_empt(unsigned int uenqc_soc_enq_fifo_empt); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_host_sge_fifo_cnt(unsigned int ucpi_host_sge_fifo_cnt); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_host_sge_empt(unsigned int ucpi_host_sge_empt); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_host_sge_full(unsigned int ucpi_host_sge_full); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_ep_sge_fifo_cnt(unsigned int ucpi_ep_sge_fifo_cnt); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_ep_sge_empt(unsigned int ucpi_ep_sge_empt); +int iSetIQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_cpi_ep_sge_full(unsigned int ucpi_ep_sge_full); +int iSetIQM_CPI_DATA_CRDT_COMP_FIFO_STATUS_cpi_data_fifo_cnt(unsigned int ucpi_data_fifo_cnt); +int iSetIQM_CPI_DATA_CRDT_COMP_FIFO_STATUS_cpi_data_empt(unsigned int ucpi_data_empt); +int iSetIQM_CPI_DATA_CRDT_COMP_FIFO_STATUS_cpi_data_full(unsigned int ucpi_data_full); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_data_fifo_cnt(unsigned int usm_data_fifo_cnt); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_data_empt(unsigned int usm_data_empt); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_data_full(unsigned int usm_data_full); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_sge_fifo_cnt(unsigned int usm_sge_fifo_cnt); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_sge_empt(unsigned int usm_sge_empt); +int iSetIQM_SM_CRDT_COMP_FIFO_STATUS_sm_sge_full(unsigned int usm_sge_full); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_cp_out_fifo_cnt(unsigned int usm_cp_out_fifo_cnt); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_cp_out_fifo_empt(unsigned int usm_cp_out_fifo_empt); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_cp_out_fifo_full(unsigned int usm_cp_out_fifo_full); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_dp_out_fifo_cnt(unsigned int usm_dp_out_fifo_cnt); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_dp_out_fifo_empt(unsigned int usm_dp_out_fifo_empt); +int iSetIQM_SM_OUT_FIFO_STATUS_sm_dp_out_fifo_full(unsigned int usm_dp_out_fifo_full); +int iSetIQM_QU_CRDT_COMP_FIFO_STATUS_qu_ep_crdt_fifo_cnt(unsigned int uqu_ep_crdt_fifo_cnt); +int iSetIQM_QU_CRDT_COMP_FIFO_STATUS_qu_ep_crdt_fifo_empt(unsigned int uqu_ep_crdt_fifo_empt); +int iSetIQM_QU_CRDT_COMP_FIFO_STATUS_qu_ep_crdt_fifo_full(unsigned int uqu_ep_crdt_fifo_full); +int iSetICLL_FREE_CNT_icll_free_rsc_cnt(unsigned int uicll_free_rsc_cnt); +int iSetIQM_SM_TOTAL_CAM_CNT_iqm_sm_total_thread_cnt(unsigned int uiqm_sm_total_thread_cnt); +int iSetIQM_SM_HOST_CRDT_BP_iqm_sm_host_sge_crdt_bp(unsigned int uiqm_sm_host_sge_crdt_bp); +int iSetIQM_SM_HOST_CRDT_BP_iqm_sm_host_dat_crdt_bp(unsigned int uiqm_sm_host_dat_crdt_bp); +int iSetIQM_SM_EP_HOST_DP_RR_SGE_CRDT_BP_iqm_sm_ep_host_dp_rr_sge_crdt_bp( + unsigned int uiqm_sm_ep_host_dp_rr_sge_crdt_bp); +int iSetIQM_SM_EP_HOST_DP_RR_DAT_CRDT_BP_iqm_sm_ep_host_dp_rr_dat_crdt_bp( + unsigned int uiqm_sm_ep_host_dp_rr_dat_crdt_bp); +int iSetIQM_SM_EP_HOST_DP_SGE_CRDT_BP_iqm_sm_ep_host_dp_sge_crdt_bp(unsigned int uiqm_sm_ep_host_dp_sge_crdt_bp); +int iSetIQM_SM_EP_HOST_DP_DAT_CRDT_BP_iqm_sm_ep_host_dp_data_crdt_bp(unsigned int uiqm_sm_ep_host_dp_data_crdt_bp); +int iSetIQM_SM_EP_HOST_CP_RR_CRDT_BP_iqm_sm_ep_host_cp_rr_sge_crdt_bp(unsigned int uiqm_sm_ep_host_cp_rr_sge_crdt_bp); +int iSetIQM_SM_EP_HOST_CP_RR_CRDT_BP_iqm_sm_ep_host_cp_rr_dat_crdt_bp(unsigned int uiqm_sm_ep_host_cp_rr_dat_crdt_bp); +int iSetIQM_SM_EP_SOC_RR_CRDT_BP_iqm_sm_ep_soc_dp_rr_sge_crdt_bp(unsigned int uiqm_sm_ep_soc_dp_rr_sge_crdt_bp); +int iSetIQM_SM_EP_SOC_RR_CRDT_BP_iqm_sm_ep_soc_cp_rr_sge_crdt_bp(unsigned int uiqm_sm_ep_soc_cp_rr_sge_crdt_bp); +int iSetIQM_SM_EP_SOC_RR_CRDT_BP_iqm_sm_ep_soc_dp_rr_dat_crdt_bp(unsigned int uiqm_sm_ep_soc_dp_rr_dat_crdt_bp); +int iSetIQM_SM_EP_SOC_RR_CRDT_BP_iqm_sm_ep_soc_cp_rr_dat_crdt_bp(unsigned int uiqm_sm_ep_soc_cp_rr_dat_crdt_bp); +int iSetIQM_SM_EP_HOST_CP_CRDT_BP_iqm_sm_ep_host_cp_sge_crdt_bp(unsigned int uiqm_sm_ep_host_cp_sge_crdt_bp); +int iSetIQM_SM_EP_HOST_CP_CRDT_BP_iqm_sm_ep_host_cp_dat_crdt_bp(unsigned int uiqm_sm_ep_host_cp_dat_crdt_bp); +int iSetIQM_SM_EP_SOC_CRDT_BP_iqm_sm_ep_soc_dp_sge_crdt_bp(unsigned int uiqm_sm_ep_soc_dp_sge_crdt_bp); +int iSetIQM_SM_EP_SOC_CRDT_BP_iqm_sm_ep_soc_cp_sge_crdt_bp(unsigned int uiqm_sm_ep_soc_cp_sge_crdt_bp); +int iSetIQM_SM_EP_SOC_CRDT_BP_iqm_sm_ep_soc_dp_dat_crdt_bp(unsigned int uiqm_sm_ep_soc_dp_dat_crdt_bp); +int iSetIQM_SM_EP_SOC_CRDT_BP_iqm_sm_ep_soc_cp_dat_crdt_bp(unsigned int uiqm_sm_ep_soc_cp_dat_crdt_bp); +int iSetIQM_QU_EP_DP_CRDT_BP0_iqm_qu_ep_dp_crdt_bp0(unsigned int uiqm_qu_ep_dp_crdt_bp0); +int iSetIQM_QU_EP_DP_CRDT_BP1_iqm_qu_ep_dp_crdt_bp1(unsigned int uiqm_qu_ep_dp_crdt_bp1); +int iSetIQM_QU_EP_CP_CRDT_BP_iqm_qu_ep_cp_crdt_bp(unsigned int uiqm_qu_ep_cp_crdt_bp); +int iSetIQM_QU_EP_DP_RR_CRDT_BP0_iqm_qu_ep_dp_rr_crdt_bp0(unsigned int uiqm_qu_ep_dp_rr_crdt_bp0); +int iSetIQM_QU_EP_DP_RR_CRDT_BP1_iqm_qu_ep_dp_rr_crdt_bp1(unsigned int uiqm_qu_ep_dp_rr_crdt_bp1); +int iSetIQM_QU_EP_CP_RR_CRDT_BP_iqm_qu_ep_cp_rr_crdt_bp(unsigned int uiqm_qu_ep_cp_rr_crdt_bp); +int iSetIQM_FLUSH_ICLL_CAM_DONE_host_nmq_cll_flush_done(unsigned int uhost_nmq_cll_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_host_nfmq_cll_flush_done(unsigned int uhost_nfmq_cll_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_host_cmq_ll_flush_done(unsigned int uhost_cmq_ll_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_soc_mq_ll_flush_done(unsigned int usoc_mq_ll_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_sm_cam_flush_done(unsigned int usm_cam_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_iqm_qu_sl_fifo_flush_done(unsigned int uiqm_qu_sl_fifo_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_iqm_sm_sl_fifo_flush_done(unsigned int uiqm_sm_sl_fifo_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_iqm_sm_cp_crr_fifo_flush_done(unsigned int uiqm_sm_cp_crr_fifo_flush_done); +int iSetIQM_FLUSH_ICLL_CAM_DONE_iqm_sm_dp_crr_fifo_flush_done(unsigned int uiqm_sm_dp_crr_fifo_flush_done); +int iSetIQM_AGING_NMQ_CNT_iqm_aging_nmq_cnt(unsigned int uiqm_aging_nmq_cnt); +int iSetIQM_AGING_NFMQ_CNT_iqm_aging_nfmq_cnt(unsigned int uiqm_aging_nfmq_cnt); +int iSetIQM_AGING_DISCARD_CNT_iqm_aging_discard_cnt(unsigned int uiqm_aging_discard_cnt); +int iSetIQM_TO_EQM_QD_CNT_iqm_to_eqm_qd_cnt(unsigned int uiqm_to_eqm_qd_cnt); +int iSetIQM_DEQ_SM_CNT_iqm_deq_to_sm_cnt(unsigned int uiqm_deq_to_sm_cnt); +int iSetIQM_DEQ_QU_CNT_iqm_deq_to_qu_cnt(unsigned int uiqm_deq_to_qu_cnt); +int iSetMSC_IQM_DEQ_CNT_msc_iqm_deq_cnt(unsigned int umsc_iqm_deq_cnt); +int iSetIQM_NMQNFMQ_ENQ_CNT_iqm_nmqnfmq_enq_cnt(unsigned int uiqm_nmqnfmq_enq_cnt); +int iSetIQM_NMQNFMQ_DEQ_CNT_iqm_nmqnfmq_deq_cnt(unsigned int uiqm_nmqnfmq_deq_cnt); +int iSetIQM_CMQ_ENQ_CNT_iqm_cmq_enq_cnt(unsigned int uiqm_cmq_enq_cnt); +int iSetIQM_CMQ_DEQ_CNT_iqm_cmq_deq_cnt(unsigned int uiqm_cmq_deq_cnt); +int iSetSOC_MSC_IQM_DEQ_CNT_soc_msc_iqm_deq_cnt(unsigned int usoc_msc_iqm_deq_cnt); +int iSetIQM_UNMQ_ENQ_CNT_iqm_unmq_enq_cnt(unsigned int uiqm_unmq_enq_cnt); +int iSetIQM_UNMQ_DEQ_CNT_iqm_unmq_deq_cnt(unsigned int uiqm_unmq_deq_cnt); +int iSetIQM_UCMQ_ENQ_CNT_iqm_ucmq_enq_cnt(unsigned int uiqm_ucmq_enq_cnt); +int iSetIQM_UCMQ_DEQ_CNT_iqm_ucmq_deq_cnt(unsigned int uiqm_ucmq_deq_cnt); +int iSetIQM_RX_CPI_COMP_HOST_SGE_CRDT_CNT_iqm_rx_cpi_host_sge_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_host_sge_comp_crdt_cnt); +int iSetIQM_RX_CPI_COMP_HOST_DAT_CRDT_CNT_iqm_rx_cpi_host_dat_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_host_dat_comp_crdt_cnt); +int iSetIQM_RX_CPI_COMP_EP_DP_SGE_CRDT_CNT_iqm_rx_cpi_ep_dp_sge_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_ep_dp_sge_comp_crdt_cnt); +int iSetIQM_RX_CPI_COMP_EP_CP_SGE_CRDT_CNT_iqm_rx_cpi_ep_cp_sge_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_ep_cp_sge_comp_crdt_cnt); +int iSetIQM_RX_CPI_COMP_EP_DP_DAT_CRDT_CNT_iqm_rx_cpi_ep_dp_dat_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_ep_dp_dat_comp_crdt_cnt); +int iSetIQM_RX_CPI_COMP_EP_CP_DAT_CRDT_CNT_iqm_rx_cpi_ep_cp_dat_comp_crdt_cnt( + unsigned int uiqm_rx_cpi_ep_cp_dat_comp_crdt_cnt); +int iSetIQM_RX_QU_COMP_EP_DP_CRDT_CNT_iqm_rx_qu_ep_dp_comp_crdt_cnt(unsigned int uiqm_rx_qu_ep_dp_comp_crdt_cnt); +int iSetIQM_RX_QU_COMP_EP_CP_CRDT_CNT_iqm_rx_qu_ep_cp_comp_crdt_cnt(unsigned int uiqm_rx_qu_ep_cp_comp_crdt_cnt); +int iSetIQM_ECC_1BIT_ERR_CNT_iqm_ecc_1bit_err_cnt(unsigned int uiqm_ecc_1bit_err_cnt); +int iSetIQM_ECC_2BIT_ERR_CNT_iqm_ecc_2bit_err_cnt(unsigned int uiqm_ecc_2bit_err_cnt); + +/* Define the union csr_eqm_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_rw_rsv0_u; + +/* Define the union csr_eqm_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_rw_rsv1_u; + +/* Define the union csr_eqm_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_rw_rsv2_u; + +/* Define the union csr_eqm_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_rw_rsv3_u; + +/* Define the union csr_eqm_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_indrect_addr : 14; /* [13:0] */ + u32 rsv_0 : 10; /* [23:14] */ + u32 eqm_indrect_tab : 4; /* [27:24] */ + u32 eqm_indrect_status : 2; /* [29:28] */ + u32 eqm_indrect_mode : 1; /* [30] */ + u32 eqm_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_indrect_ctrl_u; + +/* Define the union csr_eqm_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_indrect_timeout_u; + +/* Define the union csr_eqm_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_indrect_data_u; + +/* Define the union csr_eqm_ecqm_bp_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecqm_hfifo_bp_bypass : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecqm_bp_bypass_u; + +/* Define the union csr_eqm_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ecc_bypass_en : 1; /* [0] */ + u32 rsv_2 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ecc_bypass_en_u; + +/* Define the union csr_eqm_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_eqm_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_eqm_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_eqm_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_eqm_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_3 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_eqm_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_cpi_int_index : 24; /* [23:0] */ + u32 rsv_4 : 3; /* [26:24] */ + u32 eqm_enable : 1; /* [27] */ + u32 eqm_int_issue : 1; /* [28] */ + u32 rsv_5 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_int_vector_u; + +/* Define the union csr_eqm_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 10; /* [9:0] */ + u32 rsv_6 : 6; /* [15:10] */ + u32 eqm_int_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_int_u; + +/* Define the union csr_eqm_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_int_err_en : 10; /* [9:0] */ + u32 rsv_7 : 6; /* [15:10] */ + u32 eqm_int_en_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_int_en_u; + +/* Define the union csr_eqm_mem_ecc_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_dwq_free_rsc_err_req : 2; /* [1:0] */ + u32 host_link_err_req : 2; /* [3:2] */ + u32 hfifo_mem_err_req : 2; /* [5:4] */ + u32 host0_ecll_mem_err_req : 2; /* [7:6] */ + u32 host1_ecll_mem_err_req : 2; /* [9:8] */ + u32 host2_ecll_mem_err_req : 2; /* [11:10] */ + u32 host3_ecll_mem_err_req : 2; /* [13:12] */ + u32 head_mem_err_req : 2; /* [15:14] */ + u32 tail_mem_err_req : 2; /* [17:16] */ + u32 link_list_mem_err_req : 2; /* [19:18] */ + u32 ecll_mqlen_err_req : 2; /* [21:20] */ + u32 dmacmd_mem_err_req : 2; /* [23:22] */ + u32 dmard_mem_err_req : 2; /* [25:24] */ + u32 dmawr_mem_err_req : 2; /* [27:26] */ + u32 rsv_8 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_ecc_req_u; + +/* Define the union csr_eqm_mem_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_1bit_err : 1; /* [0] */ + u32 eqm_mem_1bit_err_insrt : 1; /* [1] */ + u32 eqm_mem_1bit_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_1bit_err_u; + +/* Define the union csr_eqm_mem_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_mem_2bit_err : 1; /* [0] */ + u32 eqm_mem_2bit_err_insrt : 1; /* [1] */ + u32 eqm_mem_2bit_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_mem_2bit_err_u; + +/* Define the union csr_eqm_ql_deq_empty_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_ql_deq_empty_err : 1; /* [0] */ + u32 eqm_ql_deq_empty_err_insrt : 1; /* [1] */ + u32 eqm_ql_deq_empty_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ql_deq_empty_int_u; + +/* Define the union csr_eqm_cll_fap_exhausted_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_cll_fap_exhuasted_err : 1; /* [0] */ + u32 eqm_cll_fap_exhuasted_err_insrt : 1; /* [1] */ + u32 eqm_cll_fap_exhuasted_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_cll_fap_exhausted_int_u; + +/* Define the union csr_eqm_fifo_wr_ovfl_int0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_ovfl_err0 : 1; /* [0] */ + u32 fifo_ovfl_err_insrt0 : 1; /* [1] */ + u32 fifo_ovfl_err1 : 1; /* [2] */ + u32 fifo_ovfl_err_insrt1 : 1; /* [3] */ + u32 fifo_ovfl_err2 : 1; /* [4] */ + u32 fifo_ovfl_err_insrt2 : 1; /* [5] */ + u32 fifo_ovfl_err3 : 1; /* [6] */ + u32 fifo_ovfl_err_insrt3 : 1; /* [7] */ + u32 fifo_ovfl_err4 : 1; /* [8] */ + u32 fifo_ovfl_err_insrt4 : 1; /* [9] */ + u32 fifo_ovfl_err5 : 1; /* [10] */ + u32 fifo_ovfl_err_insrt5 : 1; /* [11] */ + u32 fifo_ovfl_err6 : 1; /* [12] */ + u32 fifo_ovfl_err_insrt6 : 1; /* [13] */ + u32 fifo_ovfl_err7 : 1; /* [14] */ + u32 fifo_ovfl_err_insrt7 : 1; /* [15] */ + u32 fifo_ovfl_err8 : 1; /* [16] */ + u32 fifo_ovfl_err_insrt8 : 1; /* [17] */ + u32 fifo_ovfl_err9 : 1; /* [18] */ + u32 fifo_ovfl_err_insrt9 : 1; /* [19] */ + u32 fifo_ovfl_err10 : 1; /* [20] */ + u32 fifo_ovfl_err_insrt10 : 1; /* [21] */ + u32 fifo_ovfl_err11 : 1; /* [22] */ + u32 fifo_ovfl_err_insrt11 : 1; /* [23] */ + u32 fifo_ovfl_err12 : 1; /* [24] */ + u32 fifo_ovfl_err_insrt12 : 1; /* [25] */ + u32 fifo_ovfl_err13 : 1; /* [26] */ + u32 fifo_ovfl_err_insrt13 : 1; /* [27] */ + u32 fifo_ovfl_err14 : 1; /* [28] */ + u32 fifo_ovfl_err_insrt14 : 1; /* [29] */ + u32 fifo_ovfl_err15 : 1; /* [30] */ + u32 fifo_ovfl_err_insrt15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_wr_ovfl_int0_u; + +/* Define the union csr_eqm_fifo_wr_ovfl_int0_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_ovfl_err0_en : 1; /* [0] */ + u32 fifo_ovfl_err1_en : 1; /* [1] */ + u32 fifo_ovfl_err2_en : 1; /* [2] */ + u32 fifo_ovfl_err3_en : 1; /* [3] */ + u32 fifo_ovfl_err4_en : 1; /* [4] */ + u32 fifo_ovfl_err5_en : 1; /* [5] */ + u32 fifo_ovfl_err6_en : 1; /* [6] */ + u32 fifo_ovfl_err7_en : 1; /* [7] */ + u32 fifo_ovfl_err8_en : 1; /* [8] */ + u32 fifo_ovfl_err9_en : 1; /* [9] */ + u32 fifo_ovfl_err10_en : 1; /* [10] */ + u32 fifo_ovfl_err11_en : 1; /* [11] */ + u32 fifo_ovfl_err12_en : 1; /* [12] */ + u32 fifo_ovfl_err13_en : 1; /* [13] */ + u32 fifo_ovfl_err14_en : 1; /* [14] */ + u32 fifo_ovfl_err15_en : 1; /* [15] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_wr_ovfl_int0_en_u; + +/* Define the union csr_eqm_fifo_wr_ovfl_int1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_ovfl_err16 : 1; /* [0] */ + u32 fifo_ovfl_err_insrt16 : 1; /* [1] */ + u32 fifo_ovfl_err17 : 1; /* [2] */ + u32 fifo_ovfl_err_insrt17 : 1; /* [3] */ + u32 fifo_ovfl_err18 : 1; /* [4] */ + u32 fifo_ovfl_err_insrt18 : 1; /* [5] */ + u32 fifo_ovfl_err19 : 1; /* [6] */ + u32 fifo_ovfl_err_insrt19 : 1; /* [7] */ + u32 fifo_ovfl_err20 : 1; /* [8] */ + u32 fifo_ovfl_err_insrt20 : 1; /* [9] */ + u32 fifo_ovfl_err21 : 1; /* [10] */ + u32 fifo_ovfl_err_insrt21 : 1; /* [11] */ + u32 fifo_ovfl_err22 : 1; /* [12] */ + u32 fifo_ovfl_err_insrt22 : 1; /* [13] */ + u32 fifo_ovfl_err23 : 1; /* [14] */ + u32 fifo_ovfl_err_insrt23 : 1; /* [15] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_wr_ovfl_int1_u; + +/* Define the union csr_eqm_fifo_wr_ovfl_int1_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_ovfl_err16_en : 1; /* [0] */ + u32 fifo_ovfl_err17_en : 1; /* [1] */ + u32 fifo_ovfl_err18_en : 1; /* [2] */ + u32 fifo_ovfl_err19_en : 1; /* [3] */ + u32 fifo_ovfl_err20_en : 1; /* [4] */ + u32 fifo_ovfl_err21_en : 1; /* [5] */ + u32 fifo_ovfl_err22_en : 1; /* [6] */ + u32 fifo_ovfl_err23_en : 1; /* [7] */ + u32 rsv_11 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_wr_ovfl_int1_en_u; + +/* Define the union csr_eqm_fifo_rd_undel_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_underfl_err0 : 1; /* [0] */ + u32 fifo_underfl_err_insrt0 : 1; /* [1] */ + u32 fifo_underfl_err1 : 1; /* [2] */ + u32 fifo_underfl_err_insrt1 : 1; /* [3] */ + u32 fifo_underfl_err2 : 1; /* [4] */ + u32 fifo_underfl_err_insrt2 : 1; /* [5] */ + u32 fifo_underfl_err3 : 1; /* [6] */ + u32 fifo_underfl_err_insrt3 : 1; /* [7] */ + u32 fifo_underfl_err4 : 1; /* [8] */ + u32 fifo_underfl_err_insrt4 : 1; /* [9] */ + u32 fifo_underfl_err5 : 1; /* [10] */ + u32 fifo_underfl_err_insrt5 : 1; /* [11] */ + u32 fifo_underfl_err6 : 1; /* [12] */ + u32 fifo_underfl_err_insrt6 : 1; /* [13] */ + u32 fifo_underfl_err7 : 1; /* [14] */ + u32 fifo_underfl_err_insrt7 : 1; /* [15] */ + u32 fifo_underfl_err8 : 1; /* [16] */ + u32 fifo_underfl_err_insrt8 : 1; /* [17] */ + u32 fifo_underfl_err9 : 1; /* [18] */ + u32 fifo_underfl_err_insrt9 : 1; /* [19] */ + u32 fifo_underfl_err10 : 1; /* [20] */ + u32 fifo_underfl_err_insrt10 : 1; /* [21] */ + u32 fifo_underfl_err11 : 1; /* [22] */ + u32 fifo_underfl_err_insrt11 : 1; /* [23] */ + u32 fifo_underfl_err12 : 1; /* [24] */ + u32 fifo_underfl_err_insrt12 : 1; /* [25] */ + u32 fifo_underfl_err13 : 1; /* [26] */ + u32 fifo_underfl_err_insrt13 : 1; /* [27] */ + u32 fifo_underfl_err14 : 1; /* [28] */ + u32 fifo_underfl_err_insrt14 : 1; /* [29] */ + u32 fifo_underfl_err15 : 1; /* [30] */ + u32 fifo_underfl_err_insrt15 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_rd_undel_int_u; + +/* Define the union csr_eqm_fifo_rd_undel_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fifo_underfl_err0_en : 1; /* [0] */ + u32 fifo_underfl_err1_en : 1; /* [1] */ + u32 fifo_underfl_err2_en : 1; /* [2] */ + u32 fifo_underfl_err3_en : 1; /* [3] */ + u32 fifo_underfl_err4_en : 1; /* [4] */ + u32 fifo_underfl_err5_en : 1; /* [5] */ + u32 fifo_underfl_err6_en : 1; /* [6] */ + u32 fifo_underfl_err7_en : 1; /* [7] */ + u32 fifo_underfl_err8_en : 1; /* [8] */ + u32 fifo_underfl_err9_en : 1; /* [9] */ + u32 fifo_underfl_err10_en : 1; /* [10] */ + u32 fifo_underfl_err11_en : 1; /* [11] */ + u32 fifo_underfl_err12_en : 1; /* [12] */ + u32 fifo_underfl_err13_en : 1; /* [13] */ + u32 fifo_underfl_err14_en : 1; /* [14] */ + u32 fifo_underfl_err15_en : 1; /* [15] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_rd_undel_int_en_u; + +/* Define the union csr_eqm_ring_dfx_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_ring_dfx_err : 1; /* [0] */ + u32 eqm_ring_dfx_err_insrt : 1; /* [1] */ + u32 eqm_ring_dfx_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_dfx_err_int_u; + +/* Define the union csr_eqm_brmatt_rd_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_brmatt_rd_err : 1; /* [0] */ + u32 eqm_brmatt_rd_err_insrt : 1; /* [1] */ + u32 eqm_brmatt_rd_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_brmatt_rd_int_u; + +/* Define the union csr_eqm_ring_dfx_err_int1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_ring_dfx_err1 : 1; /* [0] */ + u32 eqm_ring_dfx_err1_insrt : 1; /* [1] */ + u32 eqm_ring_dfx_err1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_dfx_err_int1_u; + +/* Define the union csr_eqm_uncrt_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 addrtran_rd_uncrt_int_en : 1; /* [0] */ + u32 rsc_exhausted_uncrt_int_en : 1; /* [1] */ + u32 ql_deq_empty_uncrt_int_en : 1; /* [2] */ + u32 rsv_13 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_uncrt_int_en_u; + +/* Define the union csr_eqm_dwq_rsc_dep_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_free_rsc_depth : 9; /* [8:0] */ + u32 rsv_14 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_rsc_dep_cfg_u; + +/* Define the union csr_eqm_pack_channel_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 packing_en : 1; /* [0] */ + u32 packing_num : 3; /* [3:1] */ + u32 packing_pri_en : 8; /* [11:4] */ + u32 packing_aging_time : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_pack_channel_cfg_u; + +/* Define the union csr_eqm_db_store_space_sel_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 db_overflow_mode : 1; /* [0] */ + u32 rsv_15 : 3; /* [3:1] */ + u32 usr_appoint_host_id : 2; /* [5:4] */ + u32 rsv_16 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_db_store_space_sel_u; + +/* Define the union csr_eqm_host_chunk_num_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_chunk_num : 16; /* [15:0] */ + u32 host1_chunk_num : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_chunk_num_cfg0_u; + +/* Define the union csr_eqm_host_chunk_num_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_chunk_num : 16; /* [15:0] */ + u32 host3_chunk_num : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_chunk_num_cfg1_u; + +/* Define the union csr_eqm_page_size_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_page_size : 2; /* [1:0] */ + u32 host1_page_size : 2; /* [3:2] */ + u32 host2_page_size : 2; /* [5:4] */ + u32 host3_page_size : 2; /* [7:6] */ + u32 rsv_17 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_page_size_cfg_u; + +/* Define the union csr_eqm_hostx_dma_channel_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dmard_so_ro : 2; /* [1:0] */ + u32 hostx_dmawr_so_ro : 2; /* [3:2] */ + u32 hostx_dmard_attr_offset : 6; /* [9:4] */ + u32 hostx_dmawr_attr_offset : 6; /* [15:10] */ + u32 hostx_pf_id : 5; /* [20:16] */ + u32 rsv_18 : 3; /* [23:21] */ + u32 hostx_dmard_c_chl : 2; /* [25:24] */ + u32 hostx_dmawr_c_chl : 2; /* [27:26] */ + u32 rsv_19 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_hostx_dma_channel_cfg_u; + +/* Define the union csr_eqm_host_search_gpa_baddr_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_search_gpa_baddr : 15; /* [14:0] */ + u32 rsv_20 : 1; /* [15] */ + u32 host1_search_gpa_baddr : 15; /* [30:16] */ + u32 rsv_21 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_search_gpa_baddr_cfg0_u; + +/* Define the union csr_eqm_host_search_gpa_baddr_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_search_gpa_baddr : 15; /* [14:0] */ + u32 rsv_22 : 1; /* [15] */ + u32 host3_search_gpa_baddr : 15; /* [30:16] */ + u32 rsv_23 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_search_gpa_baddr_cfg1_u; + +/* Define the union csr_eqm_dma_outstd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_outstd_num : 7; /* [6:0] */ + u32 rsv_24 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dma_outstd_num_u; + +/* Define the union csr_eqm_host_dma_outstd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_outstd_num : 7; /* [6:0] */ + u32 rsv_25 : 1; /* [7] */ + u32 host1_outstd_num : 7; /* [14:8] */ + u32 rsv_26 : 1; /* [15] */ + u32 host2_outstd_num : 7; /* [22:16] */ + u32 rsv_27 : 1; /* [23] */ + u32 host3_outstd_num : 7; /* [30:24] */ + u32 rsv_28 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_dma_outstd_num_u; + +/* Define the union csr_eqm_fifo_gap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_enq_aful_gap : 3; /* [2:0] */ + u32 rsv_29 : 1; /* [3] */ + u32 enqc_enq_aful_gap : 3; /* [6:4] */ + u32 rsv_30 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_gap_cfg_u; + +/* Define the union csr_eqm_dwq_inf_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_smm_bp_th : 14; /* [13:0] */ + u32 rsv_31 : 2; /* [15:14] */ + u32 dwq_til_bp_th : 14; /* [29:16] */ + u32 rsv_32 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_inf_th_cfg0_u; + +/* Define the union csr_eqm_dwq_inf_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_cpi_bp_th : 14; /* [13:0] */ + u32 rsv_33 : 2; /* [15:14] */ + u32 dwq_qu_bp_th : 14; /* [29:16] */ + u32 rsv_34 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_inf_th_cfg1_u; + +/* Define the union csr_eqm_dwq_inf_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_sch_bp_th : 14; /* [13:0] */ + u32 rsv_35 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_inf_th_cfg2_u; + +/* Define the union csr_eqm_hostx_cpi_halt_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_cpi_halt_lth : 14; /* [13:0] */ + u32 rsv_36 : 2; /* [15:14] */ + u32 hostx_cpi_halt_hth : 14; /* [29:16] */ + u32 rsv_37 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_hostx_cpi_halt_th_cfg_u; + +/* Define the union csr_eqm_host_fifo_depth_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_hfifo_depth : 8; /* [7:0] */ + u32 host1_hfifo_depth : 8; /* [15:8] */ + u32 host2_hfifo_depth : 8; /* [23:16] */ + u32 host3_hfifo_depth : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_host_fifo_depth_cfg_u; + +/* Define the union csr_eqm_dmard_fifo_bp_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmard_fifo_bp_th : 8; /* [7:0] */ + u32 host1_dmard_fifo_bp_th : 8; /* [15:8] */ + u32 host2_dmard_fifo_bp_th : 8; /* [23:16] */ + u32 host3_dmard_fifo_bp_th : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmard_fifo_bp_th_u; + +/* Define the union csr_eqm_dmard_fifo_depth0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmard_fifo_depth : 9; /* [8:0] */ + u32 rsv_38 : 7; /* [15:9] */ + u32 host1_dmard_fifo_depth : 9; /* [24:16] */ + u32 rsv_39 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmard_fifo_depth0_u; + +/* Define the union csr_eqm_dmard_fifo_depth1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_dmard_fifo_depth : 9; /* [8:0] */ + u32 rsv_40 : 7; /* [15:9] */ + u32 host3_dmard_fifo_depth : 9; /* [24:16] */ + u32 rsv_41 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmard_fifo_depth1_u; + +/* Define the union csr_eqm_dmawr_fifo_depth0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmawr_fifo_depth : 9; /* [8:0] */ + u32 rsv_42 : 7; /* [15:9] */ + u32 host1_dmawr_fifo_depth : 9; /* [24:16] */ + u32 rsv_43 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmawr_fifo_depth0_u; + +/* Define the union csr_eqm_dmawr_fifo_depth1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_dmawr_fifo_depth : 9; /* [8:0] */ + u32 rsv_44 : 7; /* [15:9] */ + u32 host3_dmawr_fifo_depth : 9; /* [24:16] */ + u32 rsv_45 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmawr_fifo_depth1_u; + +/* Define the union csr_eqm_dmacmd_fifo_depth0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmacmd_fifo_depth : 10; /* [9:0] */ + u32 rsv_46 : 6; /* [15:10] */ + u32 host1_dmacmd_fifo_depth : 10; /* [25:16] */ + u32 rsv_47 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_fifo_depth0_u; + +/* Define the union csr_eqm_dmacmd_fifo_depth1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_dmacmd_fifo_depth : 10; /* [9:0] */ + u32 rsv_48 : 6; /* [15:10] */ + u32 host3_dmacmd_fifo_depth : 10; /* [25:16] */ + u32 rsv_49 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_fifo_depth1_u; + +/* Define the union csr_eqm_dmacmd_rdfifo_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmardcmd_fifo_th : 7; /* [6:0] */ + u32 rsv_50 : 1; /* [7] */ + u32 host1_dmardcmd_fifo_th : 7; /* [14:8] */ + u32 rsv_51 : 1; /* [15] */ + u32 host2_dmardcmd_fifo_th : 7; /* [22:16] */ + u32 rsv_52 : 1; /* [23] */ + u32 host3_dmardcmd_fifo_th : 7; /* [30:24] */ + u32 rsv_53 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_rdfifo_th_u; + +/* Define the union csr_eqm_dmacmd_wrfifo_th0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmawrcmd_fifo_aful_th : 9; /* [8:0] */ + u32 rsv_54 : 7; /* [15:9] */ + u32 host1_dmawrcmd_fifo_aful_th : 9; /* [24:16] */ + u32 rsv_55 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_wrfifo_th0_u; + +/* Define the union csr_eqm_dmacmd_wrfifo_th1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_dmawrcmd_fifo_aful_th : 9; /* [8:0] */ + u32 rsv_56 : 7; /* [15:9] */ + u32 host3_dmawrcmd_fifo_aful_th : 9; /* [24:16] */ + u32 rsv_57 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_wrfifo_th1_u; + +/* Define the union csr_eqm_outstd_fifo_alempty_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 outstd_fifo_ampt_th : 7; /* [6:0] */ + u32 rsv_58 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_outstd_fifo_alempty_th_u; + +/* Define the union csr_eqm_dmacmd_fifo_af_gap0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmacmd_fifo_af_gap : 10; /* [9:0] */ + u32 rsv_59 : 6; /* [15:10] */ + u32 host1_dmacmd_fifo_af_gap : 10; /* [25:16] */ + u32 rsv_60 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_fifo_af_gap0_u; + +/* Define the union csr_eqm_dmacmd_fifo_af_gap1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host2_dmacmd_fifo_af_gap : 10; /* [9:0] */ + u32 rsv_61 : 6; /* [15:10] */ + u32 host3_dmacmd_fifo_af_gap : 10; /* [25:16] */ + u32 rsv_62 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmacmd_fifo_af_gap1_u; + +/* Define the union csr_eqm_dmawr_fifo_bp_gap_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dmawr_fifo_bp_gap : 8; /* [7:0] */ + u32 host1_dmawr_fifo_bp_gap : 8; /* [15:8] */ + u32 host2_dmawr_fifo_bp_gap : 8; /* [23:16] */ + u32 host3_dmawr_fifo_bp_gap : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmawr_fifo_bp_gap_u; + +/* Define the union csr_eqm_inner_bp_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_enqc_cpi_bp : 1; /* [0] */ + u32 eqm_enqc_tile_bp : 1; /* [1] */ + u32 eqm_enqc_qu_bp : 1; /* [2] */ + u32 rsv_63 : 1; /* [3] */ + u32 mqm_cpi_halt_port : 4; /* [7:4] */ + u32 hfifo_dwqm_bp : 4; /* [11:8] */ + u32 dmacmd_fifo_aful : 4; /* [15:12] */ + u32 host_rdcmd_cnt_aful : 4; /* [19:16] */ + u32 host_wrcmd_cnt_aful : 4; /* [23:20] */ + u32 dmard_fifo_bp : 4; /* [27:24] */ + u32 dmawd_fifo_aful : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_inner_bp_status0_u; + +/* Define the union csr_eqm_inner_bp_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_deqc_root_bp : 1; /* [0] */ + u32 rsv_64 : 3; /* [3:1] */ + u32 eqm_deqc_host_bp : 4; /* [7:4] */ + u32 host_dmard_outstand_bp : 4; /* [11:8] */ + u32 eqm_ring_fifo_aful : 1; /* [12] */ + u32 ring_eqm_fifo_aful : 1; /* [13] */ + u32 eqm_iqm_enq_xoff : 1; /* [14] */ + u32 host_chunk_aempty : 4; /* [18:15] */ + u32 rsv_65 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_inner_bp_status1_u; + +/* Define the union csr_eqm_fifo_status0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iqm_enq_fifo_dfx : 2; /* [1:0] */ + u32 enqc_enq_fifo_dfx : 2; /* [3:2] */ + u32 dwq_deq_fifo_dfx : 2; /* [5:4] */ + u32 pack_enq_fifo_dfx : 2; /* [7:6] */ + u32 host0_fifo_dfx : 2; /* [9:8] */ + u32 host1_fifo_dfx : 2; /* [11:10] */ + u32 host2_fifo_dfx : 2; /* [13:12] */ + u32 host3_fifo_dfx : 2; /* [15:14] */ + u32 ring_eqm_fifo_dfx : 2; /* [17:16] */ + u32 eqm_ring_fifo_dfx : 2; /* [19:18] */ + u32 dmacmd_infifo_dfx : 2; /* [21:20] */ + u32 rsv_66 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_status0_u; + +/* Define the union csr_eqm_fifo_status1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dma_wdfifo_dfx : 2; /* [1:0] */ + u32 host1_dma_wdfifo_dfx : 2; /* [3:2] */ + u32 host2_dma_wdfifo_dfx : 2; /* [5:4] */ + u32 host3_dma_wdfifo_dfx : 2; /* [7:6] */ + u32 host0_dma_rdfifo_dfx : 2; /* [9:8] */ + u32 host1_dma_rdfifo_dfx : 2; /* [11:10] */ + u32 host2_dma_rdfifo_dfx : 2; /* [13:12] */ + u32 host3_dma_rdfifo_dfx : 2; /* [15:14] */ + u32 host0_dma_cmdfifo_dfx : 2; /* [17:16] */ + u32 host1_dma_cmdfifo_dfx : 2; /* [19:18] */ + u32 host2_dma_cmdfifo_dfx : 2; /* [21:20] */ + u32 host3_dma_cmdfifo_dfx : 2; /* [23:22] */ + u32 outstd_fifo_dfx : 2; /* [25:24] */ + u32 rsv_67 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_fifo_status1_u; + +/* Define the union csr_eqm_ring_dfx_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ring_dfx_err_cnt : 16; /* [15:0] */ + u32 rsv_68 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_dfx_err_cnt_u; + +/* Define the union csr_eqm_sm_ovfl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_ovfl_cnt : 16; /* [15:0] */ + u32 rsv_69 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_sm_ovfl_cnt_u; + +/* Define the union csr_eqm_dwq_free_addr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_free_addr_cnt : 14; /* [13:0] */ + u32 rsv_70 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_free_addr_cnt_u; + +/* Define the union csr_eqm_dwq_list_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_list_db_cnt : 14; /* [13:0] */ + u32 rsv_71 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_list_db_cnt_u; + +/* Define the union csr_eqm_dwq_hostx_list_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_hostx_list_len : 14; /* [13:0] */ + u32 rsv_72 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_hostx_list_len_u; + +/* Define the union csr_eqm_brmfap_hostx_db_eop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 brmfap_hostx_wr_eop_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_brmfap_hostx_db_eop_cnt_u; + +/* Define the union csr_eqm_nmq_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_db_cnt : 23; /* [22:0] */ + u32 rsv_73 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_nmq_db_cnt_u; + +/* Define the union csr_eqm_nmq_hostx_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_hostx_db_cnt : 23; /* [22:0] */ + u32 rsv_74 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_nmq_hostx_db_cnt_u; + +/* Define the union csr_eqm_nfmq_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_db_cnt : 23; /* [22:0] */ + u32 rsv_75 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_nfmq_db_cnt_u; + +/* Define the union csr_eqm_nfmq_hostx_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_hostx_db_cnt : 23; /* [22:0] */ + u32 rsv_76 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_nfmq_hostx_db_cnt_u; + +/* Define the union csr_eqm_hostx_dma_free_addr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dma_free_rsc_cnt : 16; /* [15:0] */ + u32 rsv_77 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_hostx_dma_free_addr_cnt_u; + +/* Define the union csr_eqm_dwq_tile_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_tile_cnt : 14; /* [13:0] */ + u32 rsv_78 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_tile_cnt_u; + +/* Define the union csr_eqm_dwq_sm_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_sm_cnt : 14; /* [13:0] */ + u32 rsv_79 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_sm_cnt_u; + +/* Define the union csr_eqm_dwq_qu_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_qu_cnt : 14; /* [13:0] */ + u32 rsv_80 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_qu_cnt_u; + +/* Define the union csr_eqm_dwq_cpi_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dwq_cpi_cnt : 14; /* [13:0] */ + u32 rsv_81 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_cpi_cnt_u; + +/* Define the union csr_eqm_dwq_cpi_hostx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dwq_cpi_cnt : 14; /* [13:0] */ + u32 rsv_82 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dwq_cpi_hostx_cnt_u; + +/* Define the union csr_eqm_ecqm_hostx_enq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecqm_hostx_enq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecqm_hostx_enq_cmd_cnt_u; + +/* Define the union csr_eqm_ecqm_hostx_deq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecqm_hostx_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecqm_hostx_deq_cmd_cnt_u; + +/* Define the union csr_eqm_ecqm_hostx_sec_deq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecqm_hostx_sec_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecqm_hostx_sec_deq_cmd_cnt_u; + +/* Define the union csr_eqm_dmagen_hostx_wr_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmagen_hostx_enq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmagen_hostx_wr_cmd_cnt_u; + +/* Define the union csr_eqm_dmagen_hostx_rd_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dmagen_hostx_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dmagen_hostx_rd_cmd_cnt_u; + +/* Define the union csr_eqm_ring_hostx_wr_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dma_wr_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_hostx_wr_db_cnt_u; + +/* Define the union csr_eqm_ring_hostx_rd_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dma_rd_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_hostx_rd_db_cnt_u; + +/* Define the union csr_eqm_hostx_enq_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_hostx_enq_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_hostx_enq_db_cnt_u; + +/* Define the union csr_eqm_iqm_send_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eqm_iqm_send_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_iqm_send_db_cnt_u; + +/* Define the union csr_eqm_ring_hostx_pre_rd_db_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hostx_dma_pre_rd_db_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ring_hostx_pre_rd_db_cnt_u; + +/* Define the union csr_eqm_dma_outstand_dfx0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dma_outstand_fifo_cnt : 7; /* [6:0] */ + u32 rsv_83 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dma_outstand_dfx0_u; + +/* Define the union csr_eqm_dma_outstand_dfx1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host0_dma_outstand_fifo_cnt : 8; /* [7:0] */ + u32 host1_dma_outstand_fifo_cnt : 8; /* [15:8] */ + u32 host2_dma_outstand_fifo_cnt : 8; /* [23:16] */ + u32 host3_dma_outstand_fifo_cnt : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_dma_outstand_dfx1_u; + +/* Define the union csr_eqm_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecc_1bit_err_cnt_u; + +/* Define the union csr_eqm_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_eqm_ecc_2bit_err_cnt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_eqm_rw_rsv0_u eqm_rw_rsv0; /* 0 */ + volatile csr_eqm_rw_rsv1_u eqm_rw_rsv1; /* 4 */ + volatile csr_eqm_rw_rsv2_u eqm_rw_rsv2; /* 8 */ + volatile csr_eqm_rw_rsv3_u eqm_rw_rsv3; /* C */ + volatile csr_eqm_indrect_ctrl_u eqm_indrect_ctrl; /* 10 */ + volatile csr_eqm_indrect_timeout_u eqm_indrect_timeout; /* 14 */ + volatile csr_eqm_indrect_data_u eqm_indrect_data; /* 18 */ + volatile csr_eqm_ecqm_bp_bypass_u eqm_ecqm_bp_bypass; /* 1C */ + volatile csr_eqm_mem_ecc_bypass_en_u eqm_mem_ecc_bypass_en; /* 20 */ + volatile csr_eqm_mem_ctrl_bus_cfg0_u eqm_mem_ctrl_bus_cfg0; /* 24 */ + volatile csr_eqm_mem_ctrl_bus_cfg1_u eqm_mem_ctrl_bus_cfg1; /* 28 */ + volatile csr_eqm_mem_ctrl_bus_cfg2_u eqm_mem_ctrl_bus_cfg2; /* 2C */ + volatile csr_eqm_mem_ctrl_bus_cfg3_u eqm_mem_ctrl_bus_cfg3; /* 30 */ + volatile csr_eqm_mem_ctrl_bus_cfg4_u eqm_mem_ctrl_bus_cfg4; /* 34 */ + volatile csr_eqm_int_vector_u eqm_int_vector; /* 40 */ + volatile csr_eqm_int_u eqm_int; /* 44 */ + volatile csr_eqm_int_en_u eqm_int_en; /* 48 */ + volatile csr_eqm_mem_ecc_req_u eqm_mem_ecc_req; /* 4C */ + volatile csr_eqm_mem_1bit_err_u eqm_mem_1bit_err; /* 50 */ + volatile csr_eqm_mem_2bit_err_u eqm_mem_2bit_err; /* 54 */ + volatile csr_eqm_ql_deq_empty_int_u eqm_ql_deq_empty_int; /* 58 */ + volatile csr_eqm_cll_fap_exhausted_int_u eqm_cll_fap_exhausted_int; /* 5C */ + volatile csr_eqm_fifo_wr_ovfl_int0_u eqm_fifo_wr_ovfl_int0; /* 60 */ + volatile csr_eqm_fifo_wr_ovfl_int0_en_u eqm_fifo_wr_ovfl_int0_en; /* 64 */ + volatile csr_eqm_fifo_wr_ovfl_int1_u eqm_fifo_wr_ovfl_int1; /* 68 */ + volatile csr_eqm_fifo_wr_ovfl_int1_en_u eqm_fifo_wr_ovfl_int1_en; /* 6C */ + volatile csr_eqm_fifo_rd_undel_int_u eqm_fifo_rd_undel_int; /* 70 */ + volatile csr_eqm_fifo_rd_undel_int_en_u eqm_fifo_rd_undel_int_en; /* 74 */ + volatile csr_eqm_ring_dfx_err_int_u eqm_ring_dfx_err_int; /* 78 */ + volatile csr_eqm_brmatt_rd_int_u eqm_brmatt_rd_int; /* 7C */ + volatile csr_eqm_ring_dfx_err_int1_u eqm_ring_dfx_err_int1; /* 80 */ + volatile csr_eqm_uncrt_int_en_u eqm_uncrt_int_en; /* 84 */ + volatile csr_eqm_dwq_rsc_dep_cfg_u eqm_dwq_rsc_dep_cfg; /* 800 */ + volatile csr_eqm_pack_channel_cfg_u eqm_pack_channel_cfg; /* 804 */ + volatile csr_eqm_db_store_space_sel_u eqm_db_store_space_sel; /* 808 */ + volatile csr_eqm_host_chunk_num_cfg0_u eqm_host_chunk_num_cfg0; /* 80C */ + volatile csr_eqm_host_chunk_num_cfg1_u eqm_host_chunk_num_cfg1; /* 810 */ + volatile csr_eqm_page_size_cfg_u eqm_page_size_cfg; /* 814 */ + volatile csr_eqm_hostx_dma_channel_cfg_u eqm_hostx_dma_channel_cfg[4]; /* 820 */ + volatile csr_eqm_host_search_gpa_baddr_cfg0_u eqm_host_search_gpa_baddr_cfg0; /* 830 */ + volatile csr_eqm_host_search_gpa_baddr_cfg1_u eqm_host_search_gpa_baddr_cfg1; /* 834 */ + volatile csr_eqm_dma_outstd_num_u eqm_dma_outstd_num; /* 838 */ + volatile csr_eqm_host_dma_outstd_num_u eqm_host_dma_outstd_num; /* 83C */ + volatile csr_eqm_fifo_gap_cfg_u eqm_fifo_gap_cfg; /* 840 */ + volatile csr_eqm_dwq_inf_th_cfg0_u eqm_dwq_inf_th_cfg0; /* 844 */ + volatile csr_eqm_dwq_inf_th_cfg1_u eqm_dwq_inf_th_cfg1; /* 848 */ + volatile csr_eqm_dwq_inf_th_cfg2_u eqm_dwq_inf_th_cfg2; /* 84C */ + volatile csr_eqm_hostx_cpi_halt_th_cfg_u eqm_hostx_cpi_halt_th_cfg[4]; /* 850 */ + volatile csr_eqm_host_fifo_depth_cfg_u eqm_host_fifo_depth_cfg; /* 860 */ + volatile csr_eqm_dmard_fifo_bp_th_u eqm_dmard_fifo_bp_th; /* 864 */ + volatile csr_eqm_dmard_fifo_depth0_u eqm_dmard_fifo_depth0; /* 868 */ + volatile csr_eqm_dmard_fifo_depth1_u eqm_dmard_fifo_depth1; /* 86C */ + volatile csr_eqm_dmawr_fifo_depth0_u eqm_dmawr_fifo_depth0; /* 870 */ + volatile csr_eqm_dmawr_fifo_depth1_u eqm_dmawr_fifo_depth1; /* 874 */ + volatile csr_eqm_dmacmd_fifo_depth0_u eqm_dmacmd_fifo_depth0; /* 878 */ + volatile csr_eqm_dmacmd_fifo_depth1_u eqm_dmacmd_fifo_depth1; /* 87C */ + volatile csr_eqm_dmacmd_rdfifo_th_u eqm_dmacmd_rdfifo_th; /* 880 */ + volatile csr_eqm_dmacmd_wrfifo_th0_u eqm_dmacmd_wrfifo_th0; /* 884 */ + volatile csr_eqm_dmacmd_wrfifo_th1_u eqm_dmacmd_wrfifo_th1; /* 888 */ + volatile csr_eqm_outstd_fifo_alempty_th_u eqm_outstd_fifo_alempty_th; /* 88C */ + volatile csr_eqm_dmacmd_fifo_af_gap0_u eqm_dmacmd_fifo_af_gap0; /* 890 */ + volatile csr_eqm_dmacmd_fifo_af_gap1_u eqm_dmacmd_fifo_af_gap1; /* 894 */ + volatile csr_eqm_dmawr_fifo_bp_gap_u eqm_dmawr_fifo_bp_gap; /* 898 */ + volatile csr_eqm_inner_bp_status0_u eqm_inner_bp_status0; /* 1000 */ + volatile csr_eqm_inner_bp_status1_u eqm_inner_bp_status1; /* 1004 */ + volatile csr_eqm_fifo_status0_u eqm_fifo_status0; /* 1008 */ + volatile csr_eqm_fifo_status1_u eqm_fifo_status1; /* 100C */ + volatile csr_eqm_ring_dfx_err_cnt_u eqm_ring_dfx_err_cnt; /* 1800 */ + volatile csr_eqm_sm_ovfl_cnt_u eqm_sm_ovfl_cnt; /* 1804 */ + volatile csr_eqm_dwq_free_addr_cnt_u eqm_dwq_free_addr_cnt; /* 1808 */ + volatile csr_eqm_dwq_list_db_cnt_u eqm_dwq_list_db_cnt; /* 180C */ + volatile csr_eqm_dwq_hostx_list_len_u eqm_dwq_hostx_list_len[4]; /* 1810 */ + volatile csr_eqm_brmfap_hostx_db_eop_cnt_u eqm_brmfap_hostx_db_eop_cnt[4]; /* 1820 */ + volatile csr_eqm_nmq_db_cnt_u eqm_nmq_db_cnt; /* 1830 */ + volatile csr_eqm_nmq_hostx_db_cnt_u eqm_nmq_hostx_db_cnt[4]; /* 1840 */ + volatile csr_eqm_nfmq_db_cnt_u eqm_nfmq_db_cnt; /* 1850 */ + volatile csr_eqm_nfmq_hostx_db_cnt_u eqm_nfmq_hostx_db_cnt[4]; /* 1860 */ + volatile csr_eqm_hostx_dma_free_addr_cnt_u eqm_hostx_dma_free_addr_cnt[4]; /* 1870 */ + volatile csr_eqm_dwq_tile_cnt_u eqm_dwq_tile_cnt; /* 1880 */ + volatile csr_eqm_dwq_sm_cnt_u eqm_dwq_sm_cnt; /* 1884 */ + volatile csr_eqm_dwq_qu_cnt_u eqm_dwq_qu_cnt; /* 1888 */ + volatile csr_eqm_dwq_cpi_cnt_u eqm_dwq_cpi_cnt; /* 188C */ + volatile csr_eqm_dwq_cpi_hostx_cnt_u eqm_dwq_cpi_hostx_cnt[4]; /* 1890 */ + volatile csr_eqm_ecqm_hostx_enq_cmd_cnt_u eqm_ecqm_hostx_enq_cmd_cnt[4]; /* 18A0 */ + volatile csr_eqm_ecqm_hostx_deq_cmd_cnt_u eqm_ecqm_hostx_deq_cmd_cnt[4]; /* 18B0 */ + volatile csr_eqm_ecqm_hostx_sec_deq_cmd_cnt_u eqm_ecqm_hostx_sec_deq_cmd_cnt[4]; /* 18C0 */ + volatile csr_eqm_dmagen_hostx_wr_cmd_cnt_u eqm_dmagen_hostx_wr_cmd_cnt[4]; /* 18D0 */ + volatile csr_eqm_dmagen_hostx_rd_cmd_cnt_u eqm_dmagen_hostx_rd_cmd_cnt[4]; /* 18E0 */ + volatile csr_eqm_ring_hostx_wr_db_cnt_u eqm_ring_hostx_wr_db_cnt[4]; /* 18F0 */ + volatile csr_eqm_ring_hostx_rd_db_cnt_u eqm_ring_hostx_rd_db_cnt[4]; /* 1900 */ + volatile csr_eqm_hostx_enq_db_cnt_u eqm_hostx_enq_db_cnt[4]; /* 1910 */ + volatile csr_eqm_iqm_send_db_cnt_u eqm_iqm_send_db_cnt; /* 1920 */ + volatile csr_eqm_ring_hostx_pre_rd_db_cnt_u eqm_ring_hostx_pre_rd_db_cnt[4]; /* 1930 */ + volatile csr_eqm_dma_outstand_dfx0_u eqm_dma_outstand_dfx0; /* 1940 */ + volatile csr_eqm_dma_outstand_dfx1_u eqm_dma_outstand_dfx1; /* 1944 */ + volatile csr_eqm_ecc_1bit_err_cnt_u eqm_ecc_1bit_err_cnt; /* 1948 */ + volatile csr_eqm_ecc_2bit_err_cnt_u eqm_ecc_2bit_err_cnt; /* 194C */ +} S_mqm_eqm_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_eqm */ +extern volatile S_mqm_eqm_REGS_TYPE *gopmqm_eqmAllReg; + +/* Declare the functions that set the member value */ +int iSetEQM_RW_RSV0_eqm_rw_rsv0(unsigned int ueqm_rw_rsv0); +int iSetEQM_RW_RSV1_eqm_rw_rsv1(unsigned int ueqm_rw_rsv1); +int iSetEQM_RW_RSV2_eqm_rw_rsv2(unsigned int ueqm_rw_rsv2); +int iSetEQM_RW_RSV3_eqm_rw_rsv3(unsigned int ueqm_rw_rsv3); +int iSetEQM_INDRECT_CTRL_eqm_indrect_addr(unsigned int ueqm_indrect_addr); +int iSetEQM_INDRECT_CTRL_eqm_indrect_tab(unsigned int ueqm_indrect_tab); +int iSetEQM_INDRECT_CTRL_eqm_indrect_status(unsigned int ueqm_indrect_status); +int iSetEQM_INDRECT_CTRL_eqm_indrect_mode(unsigned int ueqm_indrect_mode); +int iSetEQM_INDRECT_CTRL_eqm_indrect_vld(unsigned int ueqm_indrect_vld); +int iSetEQM_INDRECT_TIMEOUT_eqm_indrect_timeout(unsigned int ueqm_indrect_timeout); +int iSetEQM_INDRECT_DATA_eqm_indrect_data(unsigned int ueqm_indrect_data); +int iSetEQM_ECQM_BP_BYPASS_ecqm_hfifo_bp_bypass(unsigned int uecqm_hfifo_bp_bypass); +int iSetEQM_MEM_ECC_BYPASS_EN_eqm_mem_ecc_bypass_en(unsigned int ueqm_mem_ecc_bypass_en); +int iSetEQM_MEM_CTRL_BUS_CFG0_eqm_mem_ctrl_bus_0(unsigned int ueqm_mem_ctrl_bus_0); +int iSetEQM_MEM_CTRL_BUS_CFG1_eqm_mem_ctrl_bus_1(unsigned int ueqm_mem_ctrl_bus_1); +int iSetEQM_MEM_CTRL_BUS_CFG2_eqm_mem_ctrl_bus_2(unsigned int ueqm_mem_ctrl_bus_2); +int iSetEQM_MEM_CTRL_BUS_CFG3_eqm_mem_ctrl_bus_3(unsigned int ueqm_mem_ctrl_bus_3); +int iSetEQM_MEM_CTRL_BUS_CFG4_eqm_mem_ctrl_bus_4(unsigned int ueqm_mem_ctrl_bus_4); +int iSetEQM_INT_VECTOR_eqm_cpi_int_index(unsigned int ueqm_cpi_int_index); +int iSetEQM_INT_VECTOR_eqm_enable(unsigned int ueqm_enable); +int iSetEQM_INT_VECTOR_eqm_int_issue(unsigned int ueqm_int_issue); +int iSetEQM_INT_int_data(unsigned int uint_data); +int iSetEQM_INT_eqm_int_program_csr_id_ro(unsigned int ueqm_int_program_csr_id_ro); +int iSetEQM_INT_EN_eqm_int_err_en(unsigned int ueqm_int_err_en); +int iSetEQM_INT_EN_eqm_int_en_program_csr_id(unsigned int ueqm_int_en_program_csr_id); +int iSetEQM_MEM_ECC_REQ_eqm_dwq_free_rsc_err_req(unsigned int ueqm_dwq_free_rsc_err_req); +int iSetEQM_MEM_ECC_REQ_host_link_err_req(unsigned int uhost_link_err_req); +int iSetEQM_MEM_ECC_REQ_hfifo_mem_err_req(unsigned int uhfifo_mem_err_req); +int iSetEQM_MEM_ECC_REQ_host0_ecll_mem_err_req(unsigned int uhost0_ecll_mem_err_req); +int iSetEQM_MEM_ECC_REQ_host1_ecll_mem_err_req(unsigned int uhost1_ecll_mem_err_req); +int iSetEQM_MEM_ECC_REQ_host2_ecll_mem_err_req(unsigned int uhost2_ecll_mem_err_req); +int iSetEQM_MEM_ECC_REQ_host3_ecll_mem_err_req(unsigned int uhost3_ecll_mem_err_req); +int iSetEQM_MEM_ECC_REQ_head_mem_err_req(unsigned int uhead_mem_err_req); +int iSetEQM_MEM_ECC_REQ_tail_mem_err_req(unsigned int utail_mem_err_req); +int iSetEQM_MEM_ECC_REQ_link_list_mem_err_req(unsigned int ulink_list_mem_err_req); +int iSetEQM_MEM_ECC_REQ_ecll_mqlen_err_req(unsigned int uecll_mqlen_err_req); +int iSetEQM_MEM_ECC_REQ_dmacmd_mem_err_req(unsigned int udmacmd_mem_err_req); +int iSetEQM_MEM_ECC_REQ_dmard_mem_err_req(unsigned int udmard_mem_err_req); +int iSetEQM_MEM_ECC_REQ_dmawr_mem_err_req(unsigned int udmawr_mem_err_req); +int iSetEQM_MEM_1BIT_ERR_eqm_mem_1bit_err(unsigned int ueqm_mem_1bit_err); +int iSetEQM_MEM_1BIT_ERR_eqm_mem_1bit_err_insrt(unsigned int ueqm_mem_1bit_err_insrt); +int iSetEQM_MEM_1BIT_ERR_eqm_mem_1bit_err_sticky(unsigned int ueqm_mem_1bit_err_sticky); +int iSetEQM_MEM_2BIT_ERR_eqm_mem_2bit_err(unsigned int ueqm_mem_2bit_err); +int iSetEQM_MEM_2BIT_ERR_eqm_mem_2bit_err_insrt(unsigned int ueqm_mem_2bit_err_insrt); +int iSetEQM_MEM_2BIT_ERR_eqm_mem_2bit_err_sticky(unsigned int ueqm_mem_2bit_err_sticky); +int iSetEQM_QL_DEQ_EMPTY_INT_eqm_ql_deq_empty_err(unsigned int ueqm_ql_deq_empty_err); +int iSetEQM_QL_DEQ_EMPTY_INT_eqm_ql_deq_empty_err_insrt(unsigned int ueqm_ql_deq_empty_err_insrt); +int iSetEQM_QL_DEQ_EMPTY_INT_eqm_ql_deq_empty_err_sticky(unsigned int ueqm_ql_deq_empty_err_sticky); +int iSetEQM_CLL_FAP_EXHAUSTED_INT_eqm_cll_fap_exhuasted_err(unsigned int ueqm_cll_fap_exhuasted_err); +int iSetEQM_CLL_FAP_EXHAUSTED_INT_eqm_cll_fap_exhuasted_err_insrt(unsigned int ueqm_cll_fap_exhuasted_err_insrt); +int iSetEQM_CLL_FAP_EXHAUSTED_INT_eqm_cll_fap_exhuasted_err_sticky(unsigned int ueqm_cll_fap_exhuasted_err_sticky); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err0(unsigned int ufifo_ovfl_err0); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt0(unsigned int ufifo_ovfl_err_insrt0); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err1(unsigned int ufifo_ovfl_err1); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt1(unsigned int ufifo_ovfl_err_insrt1); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err2(unsigned int ufifo_ovfl_err2); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt2(unsigned int ufifo_ovfl_err_insrt2); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err3(unsigned int ufifo_ovfl_err3); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt3(unsigned int ufifo_ovfl_err_insrt3); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err4(unsigned int ufifo_ovfl_err4); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt4(unsigned int ufifo_ovfl_err_insrt4); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err5(unsigned int ufifo_ovfl_err5); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt5(unsigned int ufifo_ovfl_err_insrt5); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err6(unsigned int ufifo_ovfl_err6); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt6(unsigned int ufifo_ovfl_err_insrt6); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err7(unsigned int ufifo_ovfl_err7); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt7(unsigned int ufifo_ovfl_err_insrt7); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err8(unsigned int ufifo_ovfl_err8); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt8(unsigned int ufifo_ovfl_err_insrt8); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err9(unsigned int ufifo_ovfl_err9); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt9(unsigned int ufifo_ovfl_err_insrt9); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err10(unsigned int ufifo_ovfl_err10); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt10(unsigned int ufifo_ovfl_err_insrt10); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err11(unsigned int ufifo_ovfl_err11); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt11(unsigned int ufifo_ovfl_err_insrt11); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err12(unsigned int ufifo_ovfl_err12); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt12(unsigned int ufifo_ovfl_err_insrt12); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err13(unsigned int ufifo_ovfl_err13); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt13(unsigned int ufifo_ovfl_err_insrt13); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err14(unsigned int ufifo_ovfl_err14); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt14(unsigned int ufifo_ovfl_err_insrt14); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err15(unsigned int ufifo_ovfl_err15); +int iSetEQM_FIFO_WR_OVFL_INT0_fifo_ovfl_err_insrt15(unsigned int ufifo_ovfl_err_insrt15); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err0_en(unsigned int ufifo_ovfl_err0_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err1_en(unsigned int ufifo_ovfl_err1_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err2_en(unsigned int ufifo_ovfl_err2_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err3_en(unsigned int ufifo_ovfl_err3_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err4_en(unsigned int ufifo_ovfl_err4_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err5_en(unsigned int ufifo_ovfl_err5_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err6_en(unsigned int ufifo_ovfl_err6_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err7_en(unsigned int ufifo_ovfl_err7_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err8_en(unsigned int ufifo_ovfl_err8_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err9_en(unsigned int ufifo_ovfl_err9_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err10_en(unsigned int ufifo_ovfl_err10_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err11_en(unsigned int ufifo_ovfl_err11_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err12_en(unsigned int ufifo_ovfl_err12_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err13_en(unsigned int ufifo_ovfl_err13_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err14_en(unsigned int ufifo_ovfl_err14_en); +int iSetEQM_FIFO_WR_OVFL_INT0_EN_fifo_ovfl_err15_en(unsigned int ufifo_ovfl_err15_en); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err16(unsigned int ufifo_ovfl_err16); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt16(unsigned int ufifo_ovfl_err_insrt16); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err17(unsigned int ufifo_ovfl_err17); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt17(unsigned int ufifo_ovfl_err_insrt17); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err18(unsigned int ufifo_ovfl_err18); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt18(unsigned int ufifo_ovfl_err_insrt18); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err19(unsigned int ufifo_ovfl_err19); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt19(unsigned int ufifo_ovfl_err_insrt19); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err20(unsigned int ufifo_ovfl_err20); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt20(unsigned int ufifo_ovfl_err_insrt20); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err21(unsigned int ufifo_ovfl_err21); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt21(unsigned int ufifo_ovfl_err_insrt21); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err22(unsigned int ufifo_ovfl_err22); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt22(unsigned int ufifo_ovfl_err_insrt22); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err23(unsigned int ufifo_ovfl_err23); +int iSetEQM_FIFO_WR_OVFL_INT1_fifo_ovfl_err_insrt23(unsigned int ufifo_ovfl_err_insrt23); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err16_en(unsigned int ufifo_ovfl_err16_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err17_en(unsigned int ufifo_ovfl_err17_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err18_en(unsigned int ufifo_ovfl_err18_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err19_en(unsigned int ufifo_ovfl_err19_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err20_en(unsigned int ufifo_ovfl_err20_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err21_en(unsigned int ufifo_ovfl_err21_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err22_en(unsigned int ufifo_ovfl_err22_en); +int iSetEQM_FIFO_WR_OVFL_INT1_EN_fifo_ovfl_err23_en(unsigned int ufifo_ovfl_err23_en); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err0(unsigned int ufifo_underfl_err0); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt0(unsigned int ufifo_underfl_err_insrt0); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err1(unsigned int ufifo_underfl_err1); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt1(unsigned int ufifo_underfl_err_insrt1); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err2(unsigned int ufifo_underfl_err2); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt2(unsigned int ufifo_underfl_err_insrt2); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err3(unsigned int ufifo_underfl_err3); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt3(unsigned int ufifo_underfl_err_insrt3); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err4(unsigned int ufifo_underfl_err4); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt4(unsigned int ufifo_underfl_err_insrt4); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err5(unsigned int ufifo_underfl_err5); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt5(unsigned int ufifo_underfl_err_insrt5); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err6(unsigned int ufifo_underfl_err6); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt6(unsigned int ufifo_underfl_err_insrt6); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err7(unsigned int ufifo_underfl_err7); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt7(unsigned int ufifo_underfl_err_insrt7); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err8(unsigned int ufifo_underfl_err8); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt8(unsigned int ufifo_underfl_err_insrt8); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err9(unsigned int ufifo_underfl_err9); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt9(unsigned int ufifo_underfl_err_insrt9); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err10(unsigned int ufifo_underfl_err10); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt10(unsigned int ufifo_underfl_err_insrt10); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err11(unsigned int ufifo_underfl_err11); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt11(unsigned int ufifo_underfl_err_insrt11); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err12(unsigned int ufifo_underfl_err12); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt12(unsigned int ufifo_underfl_err_insrt12); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err13(unsigned int ufifo_underfl_err13); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt13(unsigned int ufifo_underfl_err_insrt13); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err14(unsigned int ufifo_underfl_err14); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt14(unsigned int ufifo_underfl_err_insrt14); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err15(unsigned int ufifo_underfl_err15); +int iSetEQM_FIFO_RD_UNDEL_INT_fifo_underfl_err_insrt15(unsigned int ufifo_underfl_err_insrt15); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err0_en(unsigned int ufifo_underfl_err0_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err1_en(unsigned int ufifo_underfl_err1_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err2_en(unsigned int ufifo_underfl_err2_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err3_en(unsigned int ufifo_underfl_err3_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err4_en(unsigned int ufifo_underfl_err4_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err5_en(unsigned int ufifo_underfl_err5_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err6_en(unsigned int ufifo_underfl_err6_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err7_en(unsigned int ufifo_underfl_err7_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err8_en(unsigned int ufifo_underfl_err8_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err9_en(unsigned int ufifo_underfl_err9_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err10_en(unsigned int ufifo_underfl_err10_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err11_en(unsigned int ufifo_underfl_err11_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err12_en(unsigned int ufifo_underfl_err12_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err13_en(unsigned int ufifo_underfl_err13_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err14_en(unsigned int ufifo_underfl_err14_en); +int iSetEQM_FIFO_RD_UNDEL_INT_EN_fifo_underfl_err15_en(unsigned int ufifo_underfl_err15_en); +int iSetEQM_RING_DFX_ERR_INT_eqm_ring_dfx_err(unsigned int ueqm_ring_dfx_err); +int iSetEQM_RING_DFX_ERR_INT_eqm_ring_dfx_err_insrt(unsigned int ueqm_ring_dfx_err_insrt); +int iSetEQM_RING_DFX_ERR_INT_eqm_ring_dfx_err_sticky(unsigned int ueqm_ring_dfx_err_sticky); +int iSetEQM_BRMATT_RD_INT_eqm_brmatt_rd_err(unsigned int ueqm_brmatt_rd_err); +int iSetEQM_BRMATT_RD_INT_eqm_brmatt_rd_err_insrt(unsigned int ueqm_brmatt_rd_err_insrt); +int iSetEQM_BRMATT_RD_INT_eqm_brmatt_rd_err_sticky(unsigned int ueqm_brmatt_rd_err_sticky); +int iSetEQM_RING_DFX_ERR_INT1_eqm_ring_dfx_err1(unsigned int ueqm_ring_dfx_err1); +int iSetEQM_RING_DFX_ERR_INT1_eqm_ring_dfx_err1_insrt(unsigned int ueqm_ring_dfx_err1_insrt); +int iSetEQM_RING_DFX_ERR_INT1_eqm_ring_dfx_err1_sticky(unsigned int ueqm_ring_dfx_err1_sticky); +int iSetEQM_UNCRT_INT_EN_addrtran_rd_uncrt_int_en(unsigned int uaddrtran_rd_uncrt_int_en); +int iSetEQM_UNCRT_INT_EN_rsc_exhausted_uncrt_int_en(unsigned int ursc_exhausted_uncrt_int_en); +int iSetEQM_UNCRT_INT_EN_ql_deq_empty_uncrt_int_en(unsigned int uql_deq_empty_uncrt_int_en); +int iSetEQM_DWQ_RSC_DEP_CFG_dwq_free_rsc_depth(unsigned int udwq_free_rsc_depth); +int iSetEQM_PACK_CHANNEL_CFG_packing_en(unsigned int upacking_en); +int iSetEQM_PACK_CHANNEL_CFG_packing_num(unsigned int upacking_num); +int iSetEQM_PACK_CHANNEL_CFG_packing_pri_en(unsigned int upacking_pri_en); +int iSetEQM_PACK_CHANNEL_CFG_packing_aging_time(unsigned int upacking_aging_time); +int iSetEQM_DB_STORE_SPACE_SEL_db_overflow_mode(unsigned int udb_overflow_mode); +int iSetEQM_DB_STORE_SPACE_SEL_usr_appoint_host_id(unsigned int uusr_appoint_host_id); +int iSetEQM_HOST_CHUNK_NUM_CFG0_host0_chunk_num(unsigned int uhost0_chunk_num); +int iSetEQM_HOST_CHUNK_NUM_CFG0_host1_chunk_num(unsigned int uhost1_chunk_num); +int iSetEQM_HOST_CHUNK_NUM_CFG1_host2_chunk_num(unsigned int uhost2_chunk_num); +int iSetEQM_HOST_CHUNK_NUM_CFG1_host3_chunk_num(unsigned int uhost3_chunk_num); +int iSetEQM_PAGE_SIZE_CFG_host0_page_size(unsigned int uhost0_page_size); +int iSetEQM_PAGE_SIZE_CFG_host1_page_size(unsigned int uhost1_page_size); +int iSetEQM_PAGE_SIZE_CFG_host2_page_size(unsigned int uhost2_page_size); +int iSetEQM_PAGE_SIZE_CFG_host3_page_size(unsigned int uhost3_page_size); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmard_so_ro(unsigned int uhostx_dmard_so_ro); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmawr_so_ro(unsigned int uhostx_dmawr_so_ro); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmard_attr_offset(unsigned int uhostx_dmard_attr_offset); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmawr_attr_offset(unsigned int uhostx_dmawr_attr_offset); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_pf_id(unsigned int uhostx_pf_id); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmard_c_chl(unsigned int uhostx_dmard_c_chl); +int iSetEQM_HOSTX_DMA_CHANNEL_CFG_hostx_dmawr_c_chl(unsigned int uhostx_dmawr_c_chl); +int iSetEQM_HOST_SEARCH_GPA_BADDR_CFG0_host0_search_gpa_baddr(unsigned int uhost0_search_gpa_baddr); +int iSetEQM_HOST_SEARCH_GPA_BADDR_CFG0_host1_search_gpa_baddr(unsigned int uhost1_search_gpa_baddr); +int iSetEQM_HOST_SEARCH_GPA_BADDR_CFG1_host2_search_gpa_baddr(unsigned int uhost2_search_gpa_baddr); +int iSetEQM_HOST_SEARCH_GPA_BADDR_CFG1_host3_search_gpa_baddr(unsigned int uhost3_search_gpa_baddr); +int iSetEQM_DMA_OUTSTD_NUM_dma_outstd_num(unsigned int udma_outstd_num); +int iSetEQM_HOST_DMA_OUTSTD_NUM_host0_outstd_num(unsigned int uhost0_outstd_num); +int iSetEQM_HOST_DMA_OUTSTD_NUM_host1_outstd_num(unsigned int uhost1_outstd_num); +int iSetEQM_HOST_DMA_OUTSTD_NUM_host2_outstd_num(unsigned int uhost2_outstd_num); +int iSetEQM_HOST_DMA_OUTSTD_NUM_host3_outstd_num(unsigned int uhost3_outstd_num); +int iSetEQM_FIFO_GAP_CFG_iqm_enq_aful_gap(unsigned int uiqm_enq_aful_gap); +int iSetEQM_FIFO_GAP_CFG_enqc_enq_aful_gap(unsigned int uenqc_enq_aful_gap); +int iSetEQM_DWQ_INF_TH_CFG0_dwq_smm_bp_th(unsigned int udwq_smm_bp_th); +int iSetEQM_DWQ_INF_TH_CFG0_dwq_til_bp_th(unsigned int udwq_til_bp_th); +int iSetEQM_DWQ_INF_TH_CFG1_dwq_cpi_bp_th(unsigned int udwq_cpi_bp_th); +int iSetEQM_DWQ_INF_TH_CFG1_dwq_qu_bp_th(unsigned int udwq_qu_bp_th); +int iSetEQM_DWQ_INF_TH_CFG2_dwq_sch_bp_th(unsigned int udwq_sch_bp_th); +int iSetEQM_HOSTX_CPI_HALT_TH_CFG_hostx_cpi_halt_lth(unsigned int uhostx_cpi_halt_lth); +int iSetEQM_HOSTX_CPI_HALT_TH_CFG_hostx_cpi_halt_hth(unsigned int uhostx_cpi_halt_hth); +int iSetEQM_HOST_FIFO_DEPTH_CFG_host0_hfifo_depth(unsigned int uhost0_hfifo_depth); +int iSetEQM_HOST_FIFO_DEPTH_CFG_host1_hfifo_depth(unsigned int uhost1_hfifo_depth); +int iSetEQM_HOST_FIFO_DEPTH_CFG_host2_hfifo_depth(unsigned int uhost2_hfifo_depth); +int iSetEQM_HOST_FIFO_DEPTH_CFG_host3_hfifo_depth(unsigned int uhost3_hfifo_depth); +int iSetEQM_DMARD_FIFO_BP_TH_host0_dmard_fifo_bp_th(unsigned int uhost0_dmard_fifo_bp_th); +int iSetEQM_DMARD_FIFO_BP_TH_host1_dmard_fifo_bp_th(unsigned int uhost1_dmard_fifo_bp_th); +int iSetEQM_DMARD_FIFO_BP_TH_host2_dmard_fifo_bp_th(unsigned int uhost2_dmard_fifo_bp_th); +int iSetEQM_DMARD_FIFO_BP_TH_host3_dmard_fifo_bp_th(unsigned int uhost3_dmard_fifo_bp_th); +int iSetEQM_DMARD_FIFO_DEPTH0_host0_dmard_fifo_depth(unsigned int uhost0_dmard_fifo_depth); +int iSetEQM_DMARD_FIFO_DEPTH0_host1_dmard_fifo_depth(unsigned int uhost1_dmard_fifo_depth); +int iSetEQM_DMARD_FIFO_DEPTH1_host2_dmard_fifo_depth(unsigned int uhost2_dmard_fifo_depth); +int iSetEQM_DMARD_FIFO_DEPTH1_host3_dmard_fifo_depth(unsigned int uhost3_dmard_fifo_depth); +int iSetEQM_DMAWR_FIFO_DEPTH0_host0_dmawr_fifo_depth(unsigned int uhost0_dmawr_fifo_depth); +int iSetEQM_DMAWR_FIFO_DEPTH0_host1_dmawr_fifo_depth(unsigned int uhost1_dmawr_fifo_depth); +int iSetEQM_DMAWR_FIFO_DEPTH1_host2_dmawr_fifo_depth(unsigned int uhost2_dmawr_fifo_depth); +int iSetEQM_DMAWR_FIFO_DEPTH1_host3_dmawr_fifo_depth(unsigned int uhost3_dmawr_fifo_depth); +int iSetEQM_DMACMD_FIFO_DEPTH0_host0_dmacmd_fifo_depth(unsigned int uhost0_dmacmd_fifo_depth); +int iSetEQM_DMACMD_FIFO_DEPTH0_host1_dmacmd_fifo_depth(unsigned int uhost1_dmacmd_fifo_depth); +int iSetEQM_DMACMD_FIFO_DEPTH1_host2_dmacmd_fifo_depth(unsigned int uhost2_dmacmd_fifo_depth); +int iSetEQM_DMACMD_FIFO_DEPTH1_host3_dmacmd_fifo_depth(unsigned int uhost3_dmacmd_fifo_depth); +int iSetEQM_DMACMD_RDFIFO_TH_host0_dmardcmd_fifo_th(unsigned int uhost0_dmardcmd_fifo_th); +int iSetEQM_DMACMD_RDFIFO_TH_host1_dmardcmd_fifo_th(unsigned int uhost1_dmardcmd_fifo_th); +int iSetEQM_DMACMD_RDFIFO_TH_host2_dmardcmd_fifo_th(unsigned int uhost2_dmardcmd_fifo_th); +int iSetEQM_DMACMD_RDFIFO_TH_host3_dmardcmd_fifo_th(unsigned int uhost3_dmardcmd_fifo_th); +int iSetEQM_DMACMD_WRFIFO_TH0_host0_dmawrcmd_fifo_aful_th(unsigned int uhost0_dmawrcmd_fifo_aful_th); +int iSetEQM_DMACMD_WRFIFO_TH0_host1_dmawrcmd_fifo_aful_th(unsigned int uhost1_dmawrcmd_fifo_aful_th); +int iSetEQM_DMACMD_WRFIFO_TH1_host2_dmawrcmd_fifo_aful_th(unsigned int uhost2_dmawrcmd_fifo_aful_th); +int iSetEQM_DMACMD_WRFIFO_TH1_host3_dmawrcmd_fifo_aful_th(unsigned int uhost3_dmawrcmd_fifo_aful_th); +int iSetEQM_OUTSTD_FIFO_ALEMPTY_TH_outstd_fifo_ampt_th(unsigned int uoutstd_fifo_ampt_th); +int iSetEQM_DMACMD_FIFO_AF_GAP0_host0_dmacmd_fifo_af_gap(unsigned int uhost0_dmacmd_fifo_af_gap); +int iSetEQM_DMACMD_FIFO_AF_GAP0_host1_dmacmd_fifo_af_gap(unsigned int uhost1_dmacmd_fifo_af_gap); +int iSetEQM_DMACMD_FIFO_AF_GAP1_host2_dmacmd_fifo_af_gap(unsigned int uhost2_dmacmd_fifo_af_gap); +int iSetEQM_DMACMD_FIFO_AF_GAP1_host3_dmacmd_fifo_af_gap(unsigned int uhost3_dmacmd_fifo_af_gap); +int iSetEQM_DMAWR_FIFO_BP_GAP_host0_dmawr_fifo_bp_gap(unsigned int uhost0_dmawr_fifo_bp_gap); +int iSetEQM_DMAWR_FIFO_BP_GAP_host1_dmawr_fifo_bp_gap(unsigned int uhost1_dmawr_fifo_bp_gap); +int iSetEQM_DMAWR_FIFO_BP_GAP_host2_dmawr_fifo_bp_gap(unsigned int uhost2_dmawr_fifo_bp_gap); +int iSetEQM_DMAWR_FIFO_BP_GAP_host3_dmawr_fifo_bp_gap(unsigned int uhost3_dmawr_fifo_bp_gap); +int iSetEQM_INNER_BP_STATUS0_eqm_enqc_cpi_bp(unsigned int ueqm_enqc_cpi_bp); +int iSetEQM_INNER_BP_STATUS0_eqm_enqc_tile_bp(unsigned int ueqm_enqc_tile_bp); +int iSetEQM_INNER_BP_STATUS0_eqm_enqc_qu_bp(unsigned int ueqm_enqc_qu_bp); +int iSetEQM_INNER_BP_STATUS0_mqm_cpi_halt_port(unsigned int umqm_cpi_halt_port); +int iSetEQM_INNER_BP_STATUS0_hfifo_dwqm_bp(unsigned int uhfifo_dwqm_bp); +int iSetEQM_INNER_BP_STATUS0_dmacmd_fifo_aful(unsigned int udmacmd_fifo_aful); +int iSetEQM_INNER_BP_STATUS0_host_rdcmd_cnt_aful(unsigned int uhost_rdcmd_cnt_aful); +int iSetEQM_INNER_BP_STATUS0_host_wrcmd_cnt_aful(unsigned int uhost_wrcmd_cnt_aful); +int iSetEQM_INNER_BP_STATUS0_dmard_fifo_bp(unsigned int udmard_fifo_bp); +int iSetEQM_INNER_BP_STATUS0_dmawd_fifo_aful(unsigned int udmawd_fifo_aful); +int iSetEQM_INNER_BP_STATUS1_eqm_deqc_root_bp(unsigned int ueqm_deqc_root_bp); +int iSetEQM_INNER_BP_STATUS1_eqm_deqc_host_bp(unsigned int ueqm_deqc_host_bp); +int iSetEQM_INNER_BP_STATUS1_host_dmard_outstand_bp(unsigned int uhost_dmard_outstand_bp); +int iSetEQM_INNER_BP_STATUS1_eqm_ring_fifo_aful(unsigned int ueqm_ring_fifo_aful); +int iSetEQM_INNER_BP_STATUS1_ring_eqm_fifo_aful(unsigned int uring_eqm_fifo_aful); +int iSetEQM_INNER_BP_STATUS1_eqm_iqm_enq_xoff(unsigned int ueqm_iqm_enq_xoff); +int iSetEQM_INNER_BP_STATUS1_host_chunk_aempty(unsigned int uhost_chunk_aempty); +int iSetEQM_FIFO_STATUS0_iqm_enq_fifo_dfx(unsigned int uiqm_enq_fifo_dfx); +int iSetEQM_FIFO_STATUS0_enqc_enq_fifo_dfx(unsigned int uenqc_enq_fifo_dfx); +int iSetEQM_FIFO_STATUS0_dwq_deq_fifo_dfx(unsigned int udwq_deq_fifo_dfx); +int iSetEQM_FIFO_STATUS0_pack_enq_fifo_dfx(unsigned int upack_enq_fifo_dfx); +int iSetEQM_FIFO_STATUS0_host0_fifo_dfx(unsigned int uhost0_fifo_dfx); +int iSetEQM_FIFO_STATUS0_host1_fifo_dfx(unsigned int uhost1_fifo_dfx); +int iSetEQM_FIFO_STATUS0_host2_fifo_dfx(unsigned int uhost2_fifo_dfx); +int iSetEQM_FIFO_STATUS0_host3_fifo_dfx(unsigned int uhost3_fifo_dfx); +int iSetEQM_FIFO_STATUS0_ring_eqm_fifo_dfx(unsigned int uring_eqm_fifo_dfx); +int iSetEQM_FIFO_STATUS0_eqm_ring_fifo_dfx(unsigned int ueqm_ring_fifo_dfx); +int iSetEQM_FIFO_STATUS0_dmacmd_infifo_dfx(unsigned int udmacmd_infifo_dfx); +int iSetEQM_FIFO_STATUS1_host0_dma_wdfifo_dfx(unsigned int uhost0_dma_wdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host1_dma_wdfifo_dfx(unsigned int uhost1_dma_wdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host2_dma_wdfifo_dfx(unsigned int uhost2_dma_wdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host3_dma_wdfifo_dfx(unsigned int uhost3_dma_wdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host0_dma_rdfifo_dfx(unsigned int uhost0_dma_rdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host1_dma_rdfifo_dfx(unsigned int uhost1_dma_rdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host2_dma_rdfifo_dfx(unsigned int uhost2_dma_rdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host3_dma_rdfifo_dfx(unsigned int uhost3_dma_rdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host0_dma_cmdfifo_dfx(unsigned int uhost0_dma_cmdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host1_dma_cmdfifo_dfx(unsigned int uhost1_dma_cmdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host2_dma_cmdfifo_dfx(unsigned int uhost2_dma_cmdfifo_dfx); +int iSetEQM_FIFO_STATUS1_host3_dma_cmdfifo_dfx(unsigned int uhost3_dma_cmdfifo_dfx); +int iSetEQM_FIFO_STATUS1_outstd_fifo_dfx(unsigned int uoutstd_fifo_dfx); +int iSetEQM_RING_DFX_ERR_CNT_ring_dfx_err_cnt(unsigned int uring_dfx_err_cnt); +int iSetEQM_SM_OVFL_CNT_sm_ovfl_cnt(unsigned int usm_ovfl_cnt); +int iSetEQM_DWQ_FREE_ADDR_CNT_dwq_free_addr_cnt(unsigned int udwq_free_addr_cnt); +int iSetEQM_DWQ_LIST_DB_CNT_dwq_list_db_cnt(unsigned int udwq_list_db_cnt); +int iSetEQM_DWQ_HOSTX_LIST_LEN_dwq_hostx_list_len(unsigned int udwq_hostx_list_len); +int iSetEQM_BRMFAP_HOSTX_DB_EOP_CNT_brmfap_hostx_wr_eop_cnt(unsigned int ubrmfap_hostx_wr_eop_cnt); +int iSetEQM_NMQ_DB_CNT_nmq_db_cnt(unsigned int unmq_db_cnt); +int iSetEQM_NMQ_HOSTX_DB_CNT_nmq_hostx_db_cnt(unsigned int unmq_hostx_db_cnt); +int iSetEQM_NFMQ_DB_CNT_nfmq_db_cnt(unsigned int unfmq_db_cnt); +int iSetEQM_NFMQ_HOSTX_DB_CNT_nfmq_hostx_db_cnt(unsigned int unfmq_hostx_db_cnt); +int iSetEQM_HOSTX_DMA_FREE_ADDR_CNT_hostx_dma_free_rsc_cnt(unsigned int uhostx_dma_free_rsc_cnt); +int iSetEQM_DWQ_TILE_CNT_dwq_tile_cnt(unsigned int udwq_tile_cnt); +int iSetEQM_DWQ_SM_CNT_dwq_sm_cnt(unsigned int udwq_sm_cnt); +int iSetEQM_DWQ_QU_CNT_dwq_qu_cnt(unsigned int udwq_qu_cnt); +int iSetEQM_DWQ_CPI_CNT_dwq_cpi_cnt(unsigned int udwq_cpi_cnt); +int iSetEQM_DWQ_CPI_HOSTX_CNT_hostx_dwq_cpi_cnt(unsigned int uhostx_dwq_cpi_cnt); +int iSetEQM_ECQM_HOSTX_ENQ_CMD_CNT_ecqm_hostx_enq_cmd_cnt(unsigned int uecqm_hostx_enq_cmd_cnt); +int iSetEQM_ECQM_HOSTX_DEQ_CMD_CNT_ecqm_hostx_deq_cmd_cnt(unsigned int uecqm_hostx_deq_cmd_cnt); +int iSetEQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_ecqm_hostx_sec_deq_cmd_cnt(unsigned int uecqm_hostx_sec_deq_cmd_cnt); +int iSetEQM_DMAGEN_HOSTX_WR_CMD_CNT_dmagen_hostx_enq_cmd_cnt(unsigned int udmagen_hostx_enq_cmd_cnt); +int iSetEQM_DMAGEN_HOSTX_RD_CMD_CNT_dmagen_hostx_deq_cmd_cnt(unsigned int udmagen_hostx_deq_cmd_cnt); +int iSetEQM_RING_HOSTX_WR_DB_CNT_hostx_dma_wr_db_cnt(unsigned int uhostx_dma_wr_db_cnt); +int iSetEQM_RING_HOSTX_RD_DB_CNT_hostx_dma_rd_db_cnt(unsigned int uhostx_dma_rd_db_cnt); +int iSetEQM_HOSTX_ENQ_DB_CNT_eqm_hostx_enq_db_cnt(unsigned int ueqm_hostx_enq_db_cnt); +int iSetEQM_IQM_SEND_DB_CNT_eqm_iqm_send_db_cnt(unsigned int ueqm_iqm_send_db_cnt); +int iSetEQM_RING_HOSTX_PRE_RD_DB_CNT_hostx_dma_pre_rd_db_cnt(unsigned int uhostx_dma_pre_rd_db_cnt); +int iSetEQM_DMA_OUTSTAND_DFX0_dma_outstand_fifo_cnt(unsigned int udma_outstand_fifo_cnt); +int iSetEQM_DMA_OUTSTAND_DFX1_host0_dma_outstand_fifo_cnt(unsigned int uhost0_dma_outstand_fifo_cnt); +int iSetEQM_DMA_OUTSTAND_DFX1_host1_dma_outstand_fifo_cnt(unsigned int uhost1_dma_outstand_fifo_cnt); +int iSetEQM_DMA_OUTSTAND_DFX1_host2_dma_outstand_fifo_cnt(unsigned int uhost2_dma_outstand_fifo_cnt); +int iSetEQM_DMA_OUTSTAND_DFX1_host3_dma_outstand_fifo_cnt(unsigned int uhost3_dma_outstand_fifo_cnt); +int iSetEQM_ECC_1BIT_ERR_CNT_ecc_1bit_err_cnt(unsigned int uecc_1bit_err_cnt); +int iSetEQM_ECC_2BIT_ERR_CNT_ecc_2bit_err_cnt(unsigned int uecc_2bit_err_cnt); + +/* Define the union csr_msc_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_rw_rsv0_u; + +/* Define the union csr_msc_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_rw_rsv1_u; + +/* Define the union csr_msc_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_rw_rsv2_u; + +/* Define the union csr_msc_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_rw_rsv3_u; + +/* Define the union csr_msc_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_indrect_addr : 20; /* [19:0] */ + u32 msc_indrect_tab : 8; /* [27:20] */ + u32 msc_indrect_stat : 2; /* [29:28] */ + u32 msc_indrect_mode : 1; /* [30] */ + u32 msc_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_indrect_ctrl_u; + +/* Define the union csr_msc_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_indrect_timeout_u; + +/* Define the union csr_msc_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_indrect_data_0_u; + +/* Define the union csr_msc_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_indrect_data_1_u; + +/* Define the union csr_msc_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ecc_bypass_en_u; + +/* Define the union csr_msc_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_msc_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_msc_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_msc_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_msc_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_1 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_msc_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 msc_enable : 1; /* [27] */ + u32 msc_int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_int_vector_u; + +/* Define the union csr_msc_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_int_data : 15; /* [14:0] */ + u32 rsv_4 : 1; /* [15] */ + u32 msc_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_int_u; + +/* Define the union csr_msc_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_int_en : 15; /* [14:0] */ + u32 rsv_5 : 1; /* [15] */ + u32 msc_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_int_en_u; + +/* Define the union csr_msc_mem_err_req0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_err_req_0 : 1; /* [0] */ + u32 msc_mem_err_req_1 : 1; /* [1] */ + u32 msc_mem_err_req_2 : 1; /* [2] */ + u32 msc_mem_err_req_3 : 1; /* [3] */ + u32 msc_mem_err_req_4 : 1; /* [4] */ + u32 msc_mem_err_req_5 : 1; /* [5] */ + u32 msc_mem_err_req_6 : 1; /* [6] */ + u32 msc_mem_err_req_7 : 1; /* [7] */ + u32 msc_mem_err_req_8 : 1; /* [8] */ + u32 msc_mem_err_req_9 : 1; /* [9] */ + u32 msc_mem_err_req_10 : 1; /* [10] */ + u32 msc_mem_err_req_11 : 1; /* [11] */ + u32 msc_mem_err_req_12 : 1; /* [12] */ + u32 msc_mem_err_req_13 : 1; /* [13] */ + u32 msc_mem_err_req_14 : 1; /* [14] */ + u32 msc_mem_err_req_15 : 1; /* [15] */ + u32 msc_mem_err_req_16 : 1; /* [16] */ + u32 msc_mem_err_req_17 : 1; /* [17] */ + u32 msc_mem_err_req_18 : 1; /* [18] */ + u32 msc_mem_err_req_19 : 1; /* [19] */ + u32 msc_mem_err_req_20 : 1; /* [20] */ + u32 msc_mem_err_req_21 : 1; /* [21] */ + u32 msc_mem_err_req_22 : 1; /* [22] */ + u32 msc_mem_err_req_23 : 1; /* [23] */ + u32 msc_mem_err_req_24 : 1; /* [24] */ + u32 msc_mem_err_req_25 : 1; /* [25] */ + u32 msc_mem_err_req_26 : 1; /* [26] */ + u32 msc_mem_err_req_27 : 1; /* [27] */ + u32 msc_mem_err_req_28 : 1; /* [28] */ + u32 msc_mem_err_req_29 : 1; /* [29] */ + u32 rsv_6 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_err_req0_u; + +/* Define the union csr_msc_mem_err_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_err_req_32 : 1; /* [0] */ + u32 msc_mem_err_req_33 : 1; /* [1] */ + u32 msc_mem_err_req_34 : 1; /* [2] */ + u32 msc_mem_err_req_35 : 1; /* [3] */ + u32 msc_mem_err_req_36 : 1; /* [4] */ + u32 msc_mem_err_req_37 : 1; /* [5] */ + u32 msc_mem_err_req_38 : 1; /* [6] */ + u32 msc_mem_err_req_39 : 1; /* [7] */ + u32 msc_mem_err_req_40 : 1; /* [8] */ + u32 msc_mem_err_req_41 : 1; /* [9] */ + u32 msc_mem_err_req_42 : 1; /* [10] */ + u32 msc_mem_err_req_43 : 1; /* [11] */ + u32 msc_mem_err_req_44 : 1; /* [12] */ + u32 msc_mem_err_req_45 : 1; /* [13] */ + u32 msc_mem_err_req_46 : 1; /* [14] */ + u32 msc_mem_err_req_47 : 1; /* [15] */ + u32 msc_mem_err_req_48 : 1; /* [16] */ + u32 msc_mem_err_req_49 : 1; /* [17] */ + u32 msc_mem_err_req_50 : 1; /* [18] */ + u32 msc_mem_err_req_51 : 1; /* [19] */ + u32 msc_mem_err_req_52 : 1; /* [20] */ + u32 msc_mem_err_req_53 : 1; /* [21] */ + u32 msc_mem_err_req_54 : 1; /* [22] */ + u32 msc_mem_err_req_55 : 1; /* [23] */ + u32 rsv_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_err_req1_u; + +/* Define the union csr_msc_mem_err_req2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_err_req_64 : 1; /* [0] */ + u32 msc_mem_err_req_65 : 1; /* [1] */ + u32 msc_mem_err_req_66 : 1; /* [2] */ + u32 msc_mem_err_req_67 : 1; /* [3] */ + u32 msc_mem_err_req_68 : 1; /* [4] */ + u32 msc_mem_err_req_69 : 1; /* [5] */ + u32 msc_mem_err_req_70 : 1; /* [6] */ + u32 msc_mem_err_req_71 : 1; /* [7] */ + u32 msc_mem_err_req_72 : 1; /* [8] */ + u32 msc_mem_err_req_73 : 1; /* [9] */ + u32 msc_mem_err_req_74 : 1; /* [10] */ + u32 msc_mem_err_req_75 : 1; /* [11] */ + u32 msc_mem_err_req_76 : 1; /* [12] */ + u32 msc_mem_err_req_77 : 1; /* [13] */ + u32 msc_mem_err_req_78 : 1; /* [14] */ + u32 msc_mem_err_req_79 : 1; /* [15] */ + u32 msc_mem_err_req_80 : 1; /* [16] */ + u32 msc_mem_err_req_81 : 1; /* [17] */ + u32 msc_mem_err_req_82 : 1; /* [18] */ + u32 msc_mem_err_req_83 : 1; /* [19] */ + u32 msc_mem_err_req_84 : 1; /* [20] */ + u32 msc_mem_err_req_85 : 1; /* [21] */ + u32 msc_mem_err_req_86 : 1; /* [22] */ + u32 msc_mem_err_req_87 : 1; /* [23] */ + u32 msc_mem_err_req_88 : 1; /* [24] */ + u32 msc_mem_err_req_89 : 1; /* [25] */ + u32 msc_mem_err_req_90 : 1; /* [26] */ + u32 msc_mem_err_req_91 : 1; /* [27] */ + u32 msc_mem_err_req_92 : 1; /* [28] */ + u32 msc_mem_err_req_93 : 1; /* [29] */ + u32 msc_mem_err_req_94 : 1; /* [30] */ + u32 msc_mem_err_req_95 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_err_req2_u; + +/* Define the union csr_msc_mem_err_req3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_err_req_96 : 1; /* [0] */ + u32 msc_mem_err_req_97 : 1; /* [1] */ + u32 msc_mem_err_req_98 : 1; /* [2] */ + u32 msc_mem_err_req_99 : 1; /* [3] */ + u32 msc_mem_err_req_100 : 1; /* [4] */ + u32 msc_mem_err_req_101 : 1; /* [5] */ + u32 msc_mem_err_req_102 : 1; /* [6] */ + u32 msc_mem_err_req_103 : 1; /* [7] */ + u32 msc_mem_err_req_104 : 1; /* [8] */ + u32 msc_mem_err_req_105 : 1; /* [9] */ + u32 msc_mem_err_req_106 : 1; /* [10] */ + u32 msc_mem_err_req_107 : 1; /* [11] */ + u32 msc_mem_err_req_108 : 1; /* [12] */ + u32 msc_mem_err_req_109 : 1; /* [13] */ + u32 msc_mem_err_req_110 : 1; /* [14] */ + u32 msc_mem_err_req_111 : 1; /* [15] */ + u32 msc_mem_err_req_112 : 1; /* [16] */ + u32 msc_mem_err_req_113 : 1; /* [17] */ + u32 msc_mem_err_req_114 : 1; /* [18] */ + u32 msc_mem_err_req_115 : 1; /* [19] */ + u32 msc_mem_err_req_116 : 1; /* [20] */ + u32 msc_mem_err_req_117 : 1; /* [21] */ + u32 msc_mem_err_req_118 : 1; /* [22] */ + u32 msc_mem_err_req_119 : 1; /* [23] */ + u32 msc_mem_err_req_120 : 1; /* [24] */ + u32 msc_mem_err_req_121 : 1; /* [25] */ + u32 msc_mem_err_req_122 : 1; /* [26] */ + u32 msc_mem_err_req_123 : 1; /* [27] */ + u32 msc_mem_err_req_124 : 1; /* [28] */ + u32 msc_mem_err_req_125 : 1; /* [29] */ + u32 msc_mem_err_req_126 : 1; /* [30] */ + u32 msc_mem_err_req_127 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_err_req3_u; + +/* Define the union csr_msc_mem_err_req4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mem_err_req_128 : 1; /* [0] */ + u32 msc_mem_err_req_129 : 1; /* [1] */ + u32 msc_mem_err_req_130 : 1; /* [2] */ + u32 msc_mem_err_req_131 : 1; /* [3] */ + u32 msc_mem_err_req_132 : 1; /* [4] */ + u32 msc_mem_err_req_133 : 1; /* [5] */ + u32 msc_mem_err_req_134 : 1; /* [6] */ + u32 msc_mem_err_req_135 : 1; /* [7] */ + u32 msc_mem_err_req_136 : 1; /* [8] */ + u32 msc_mem_err_req_137 : 1; /* [9] */ + u32 msc_mem_err_req_138 : 1; /* [10] */ + u32 msc_mem_err_req_139 : 1; /* [11] */ + u32 msc_mem_err_req_140 : 1; /* [12] */ + u32 msc_mem_err_req_141 : 1; /* [13] */ + u32 msc_mem_err_req_142 : 1; /* [14] */ + u32 msc_mem_err_req_143 : 1; /* [15] */ + u32 msc_mem_err_req_144 : 1; /* [16] */ + u32 msc_mem_err_req_145 : 1; /* [17] */ + u32 msc_mem_err_req_146 : 1; /* [18] */ + u32 msc_mem_err_req_147 : 1; /* [19] */ + u32 msc_mem_err_req_148 : 1; /* [20] */ + u32 msc_mem_err_req_149 : 1; /* [21] */ + u32 msc_mem_err_req_150 : 1; /* [22] */ + u32 msc_mem_err_req_151 : 1; /* [23] */ + u32 msc_mem_err_req_152 : 1; /* [24] */ + u32 msc_mem_err_req_153 : 1; /* [25] */ + u32 msc_mem_err_req_154 : 1; /* [26] */ + u32 msc_mem_err_req_155 : 1; /* [27] */ + u32 msc_mem_err_req_156 : 1; /* [28] */ + u32 msc_mem_err_req_157 : 1; /* [29] */ + u32 rsv_8 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mem_err_req4_u; + +/* Define the union csr_msc_ecc_one_bit_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ecc_1bit_err : 1; /* [0] */ + u32 msc_ecc_1bit_err_insrt : 1; /* [1] */ + u32 msc_ecc_1bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ecc_one_bit_int_u; + +/* Define the union csr_msc_ecc_two_bit_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ecc_2bit_err : 1; /* [0] */ + u32 msc_ecc_2bit_err_insrt : 1; /* [1] */ + u32 msc_ecc_2bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ecc_two_bit_int_u; + +/* Define the union csr_msc_mq_bind_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_bind_cfg_err : 1; /* [0] */ + u32 msc_bind_cfg_err_insrt : 1; /* [1] */ + u32 msc_bind_cfg_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_mq_bind_int_u; + +/* Define the union csr_msc_vnic_spcnt_inf_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_vf_sp_cnt_inf_err : 1; /* [0] */ + u32 msc_vf_sp_cnt_inf_err_insrt : 1; /* [1] */ + u32 msc_vf_sp_cnt_inf_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_vnic_spcnt_inf_int_u; + +/* Define the union csr_msc_vnic_spcnt_cal_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_vf_sp_cnt_cal_err : 1; /* [0] */ + u32 msc_vf_sp_cnt_cal_err_insrt : 1; /* [1] */ + u32 msc_vf_sp_cnt_cal_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_vnic_spcnt_cal_int_u; + +/* Define the union csr_msc_socep_spcnt_inf_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_socep_sp_cnt_inf_err : 1; /* [0] */ + u32 msc_socep_sp_cnt_inf_err_insrt : 1; /* [1] */ + u32 msc_socep_sp_cnt_inf_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_socep_spcnt_inf_int_u; + +/* Define the union csr_msc_socep_spcnt_cal_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_socep_sp_cnt_cal_err : 1; /* [0] */ + u32 msc_socep_sp_cnt_cal_err_insrt : 1; /* [1] */ + u32 msc_socep_sp_cnt_cal_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_socep_spcnt_cal_int_u; + +/* Define the union csr_msc_fifo_int0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int0_err0 : 1; /* [0] */ + u32 msc_fifo_int0_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int0_err1 : 1; /* [2] */ + u32 msc_fifo_int0_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int0_err2 : 1; /* [4] */ + u32 msc_fifo_int0_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int0_err3 : 1; /* [6] */ + u32 msc_fifo_int0_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int0_err4 : 1; /* [8] */ + u32 msc_fifo_int0_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int0_err5 : 1; /* [10] */ + u32 msc_fifo_int0_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int0_err6 : 1; /* [12] */ + u32 msc_fifo_int0_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int0_err7 : 1; /* [14] */ + u32 msc_fifo_int0_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int0_err8 : 1; /* [16] */ + u32 msc_fifo_int0_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int0_err9 : 1; /* [18] */ + u32 msc_fifo_int0_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int0_err10 : 1; /* [20] */ + u32 msc_fifo_int0_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int0_err11 : 1; /* [22] */ + u32 msc_fifo_int0_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int0_err12 : 1; /* [24] */ + u32 msc_fifo_int0_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int0_err13 : 1; /* [26] */ + u32 msc_fifo_int0_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int0_err14 : 1; /* [28] */ + u32 msc_fifo_int0_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int0_err15 : 1; /* [30] */ + u32 msc_fifo_int0_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int0_u; + +/* Define the union csr_msc_fifo_int0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int0_err0_en : 1; /* [0] */ + u32 msc_fifo_int0_err1_en : 1; /* [1] */ + u32 msc_fifo_int0_err2_en : 1; /* [2] */ + u32 msc_fifo_int0_err3_en : 1; /* [3] */ + u32 msc_fifo_int0_err4_en : 1; /* [4] */ + u32 msc_fifo_int0_err5_en : 1; /* [5] */ + u32 msc_fifo_int0_err6_en : 1; /* [6] */ + u32 msc_fifo_int0_err7_en : 1; /* [7] */ + u32 msc_fifo_int0_err8_en : 1; /* [8] */ + u32 msc_fifo_int0_err9_en : 1; /* [9] */ + u32 msc_fifo_int0_err10_en : 1; /* [10] */ + u32 msc_fifo_int0_err11_en : 1; /* [11] */ + u32 msc_fifo_int0_err12_en : 1; /* [12] */ + u32 msc_fifo_int0_err13_en : 1; /* [13] */ + u32 msc_fifo_int0_err14_en : 1; /* [14] */ + u32 msc_fifo_int0_err15_en : 1; /* [15] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int0_mask_u; + +/* Define the union csr_msc_fifo_int1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int1_err0 : 1; /* [0] */ + u32 msc_fifo_int1_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int1_err1 : 1; /* [2] */ + u32 msc_fifo_int1_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int1_err2 : 1; /* [4] */ + u32 msc_fifo_int1_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int1_err3 : 1; /* [6] */ + u32 msc_fifo_int1_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int1_err4 : 1; /* [8] */ + u32 msc_fifo_int1_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int1_err5 : 1; /* [10] */ + u32 msc_fifo_int1_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int1_err6 : 1; /* [12] */ + u32 msc_fifo_int1_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int1_err7 : 1; /* [14] */ + u32 msc_fifo_int1_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int1_err8 : 1; /* [16] */ + u32 msc_fifo_int1_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int1_err9 : 1; /* [18] */ + u32 msc_fifo_int1_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int1_err10 : 1; /* [20] */ + u32 msc_fifo_int1_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int1_err11 : 1; /* [22] */ + u32 msc_fifo_int1_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int1_err12 : 1; /* [24] */ + u32 msc_fifo_int1_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int1_err13 : 1; /* [26] */ + u32 msc_fifo_int1_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int1_err14 : 1; /* [28] */ + u32 msc_fifo_int1_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int1_err15 : 1; /* [30] */ + u32 msc_fifo_int1_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int1_u; + +/* Define the union csr_msc_fifo_int1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int1_err0_en : 1; /* [0] */ + u32 msc_fifo_int1_err1_en : 1; /* [1] */ + u32 msc_fifo_int1_err2_en : 1; /* [2] */ + u32 msc_fifo_int1_err3_en : 1; /* [3] */ + u32 msc_fifo_int1_err4_en : 1; /* [4] */ + u32 msc_fifo_int1_err5_en : 1; /* [5] */ + u32 msc_fifo_int1_err6_en : 1; /* [6] */ + u32 msc_fifo_int1_err7_en : 1; /* [7] */ + u32 msc_fifo_int1_err8_en : 1; /* [8] */ + u32 msc_fifo_int1_err9_en : 1; /* [9] */ + u32 msc_fifo_int1_err10_en : 1; /* [10] */ + u32 msc_fifo_int1_err11_en : 1; /* [11] */ + u32 msc_fifo_int1_err12_en : 1; /* [12] */ + u32 msc_fifo_int1_err13_en : 1; /* [13] */ + u32 msc_fifo_int1_err14_en : 1; /* [14] */ + u32 msc_fifo_int1_err15_en : 1; /* [15] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int1_mask_u; + +/* Define the union csr_msc_fifo_int2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int2_err0 : 1; /* [0] */ + u32 msc_fifo_int2_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int2_err1 : 1; /* [2] */ + u32 msc_fifo_int2_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int2_err2 : 1; /* [4] */ + u32 msc_fifo_int2_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int2_err3 : 1; /* [6] */ + u32 msc_fifo_int2_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int2_err4 : 1; /* [8] */ + u32 msc_fifo_int2_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int2_err5 : 1; /* [10] */ + u32 msc_fifo_int2_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int2_err6 : 1; /* [12] */ + u32 msc_fifo_int2_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int2_err7 : 1; /* [14] */ + u32 msc_fifo_int2_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int2_err8 : 1; /* [16] */ + u32 msc_fifo_int2_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int2_err9 : 1; /* [18] */ + u32 msc_fifo_int2_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int2_err10 : 1; /* [20] */ + u32 msc_fifo_int2_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int2_err11 : 1; /* [22] */ + u32 msc_fifo_int2_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int2_err12 : 1; /* [24] */ + u32 msc_fifo_int2_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int2_err13 : 1; /* [26] */ + u32 msc_fifo_int2_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int2_err14 : 1; /* [28] */ + u32 msc_fifo_int2_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int2_err15 : 1; /* [30] */ + u32 msc_fifo_int2_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int2_u; + +/* Define the union csr_msc_fifo_int2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int2_err0_en : 1; /* [0] */ + u32 msc_fifo_int2_err1_en : 1; /* [1] */ + u32 msc_fifo_int2_err2_en : 1; /* [2] */ + u32 msc_fifo_int2_err3_en : 1; /* [3] */ + u32 msc_fifo_int2_err4_en : 1; /* [4] */ + u32 msc_fifo_int2_err5_en : 1; /* [5] */ + u32 msc_fifo_int2_err6_en : 1; /* [6] */ + u32 msc_fifo_int2_err7_en : 1; /* [7] */ + u32 msc_fifo_int2_err8_en : 1; /* [8] */ + u32 msc_fifo_int2_err9_en : 1; /* [9] */ + u32 msc_fifo_int2_err10_en : 1; /* [10] */ + u32 msc_fifo_int2_err11_en : 1; /* [11] */ + u32 msc_fifo_int2_err12_en : 1; /* [12] */ + u32 msc_fifo_int2_err13_en : 1; /* [13] */ + u32 msc_fifo_int2_err14_en : 1; /* [14] */ + u32 msc_fifo_int2_err15_en : 1; /* [15] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int2_mask_u; + +/* Define the union csr_msc_fifo_int3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int3_err0 : 1; /* [0] */ + u32 msc_fifo_int3_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int3_err1 : 1; /* [2] */ + u32 msc_fifo_int3_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int3_err2 : 1; /* [4] */ + u32 msc_fifo_int3_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int3_err3 : 1; /* [6] */ + u32 msc_fifo_int3_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int3_err4 : 1; /* [8] */ + u32 msc_fifo_int3_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int3_err5 : 1; /* [10] */ + u32 msc_fifo_int3_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int3_err6 : 1; /* [12] */ + u32 msc_fifo_int3_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int3_err7 : 1; /* [14] */ + u32 msc_fifo_int3_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int3_err8 : 1; /* [16] */ + u32 msc_fifo_int3_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int3_err9 : 1; /* [18] */ + u32 msc_fifo_int3_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int3_err10 : 1; /* [20] */ + u32 msc_fifo_int3_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int3_err11 : 1; /* [22] */ + u32 msc_fifo_int3_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int3_err12 : 1; /* [24] */ + u32 msc_fifo_int3_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int3_err13 : 1; /* [26] */ + u32 msc_fifo_int3_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int3_err14 : 1; /* [28] */ + u32 msc_fifo_int3_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int3_err15 : 1; /* [30] */ + u32 msc_fifo_int3_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int3_u; + +/* Define the union csr_msc_fifo_int3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int3_err0_en : 1; /* [0] */ + u32 msc_fifo_int3_err1_en : 1; /* [1] */ + u32 msc_fifo_int3_err2_en : 1; /* [2] */ + u32 msc_fifo_int3_err3_en : 1; /* [3] */ + u32 msc_fifo_int3_err4_en : 1; /* [4] */ + u32 msc_fifo_int3_err5_en : 1; /* [5] */ + u32 msc_fifo_int3_err6_en : 1; /* [6] */ + u32 msc_fifo_int3_err7_en : 1; /* [7] */ + u32 msc_fifo_int3_err8_en : 1; /* [8] */ + u32 msc_fifo_int3_err9_en : 1; /* [9] */ + u32 msc_fifo_int3_err10_en : 1; /* [10] */ + u32 msc_fifo_int3_err11_en : 1; /* [11] */ + u32 msc_fifo_int3_err12_en : 1; /* [12] */ + u32 msc_fifo_int3_err13_en : 1; /* [13] */ + u32 msc_fifo_int3_err14_en : 1; /* [14] */ + u32 msc_fifo_int3_err15_en : 1; /* [15] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int3_mask_u; + +/* Define the union csr_msc_fifo_int4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int4_err0 : 1; /* [0] */ + u32 msc_fifo_int4_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int4_err1 : 1; /* [2] */ + u32 msc_fifo_int4_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int4_err2 : 1; /* [4] */ + u32 msc_fifo_int4_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int4_err3 : 1; /* [6] */ + u32 msc_fifo_int4_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int4_err4 : 1; /* [8] */ + u32 msc_fifo_int4_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int4_err5 : 1; /* [10] */ + u32 msc_fifo_int4_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int4_err6 : 1; /* [12] */ + u32 msc_fifo_int4_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int4_err7 : 1; /* [14] */ + u32 msc_fifo_int4_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int4_err8 : 1; /* [16] */ + u32 msc_fifo_int4_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int4_err9 : 1; /* [18] */ + u32 msc_fifo_int4_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int4_err10 : 1; /* [20] */ + u32 msc_fifo_int4_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int4_err11 : 1; /* [22] */ + u32 msc_fifo_int4_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int4_err12 : 1; /* [24] */ + u32 msc_fifo_int4_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int4_err13 : 1; /* [26] */ + u32 msc_fifo_int4_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int4_err14 : 1; /* [28] */ + u32 msc_fifo_int4_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int4_err15 : 1; /* [30] */ + u32 msc_fifo_int4_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int4_u; + +/* Define the union csr_msc_fifo_int4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int4_err0_en : 1; /* [0] */ + u32 msc_fifo_int4_err1_en : 1; /* [1] */ + u32 msc_fifo_int4_err2_en : 1; /* [2] */ + u32 msc_fifo_int4_err3_en : 1; /* [3] */ + u32 msc_fifo_int4_err4_en : 1; /* [4] */ + u32 msc_fifo_int4_err5_en : 1; /* [5] */ + u32 msc_fifo_int4_err6_en : 1; /* [6] */ + u32 msc_fifo_int4_err7_en : 1; /* [7] */ + u32 msc_fifo_int4_err8_en : 1; /* [8] */ + u32 msc_fifo_int4_err9_en : 1; /* [9] */ + u32 msc_fifo_int4_err10_en : 1; /* [10] */ + u32 msc_fifo_int4_err11_en : 1; /* [11] */ + u32 msc_fifo_int4_err12_en : 1; /* [12] */ + u32 msc_fifo_int4_err13_en : 1; /* [13] */ + u32 msc_fifo_int4_err14_en : 1; /* [14] */ + u32 msc_fifo_int4_err15_en : 1; /* [15] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int4_mask_u; + +/* Define the union csr_msc_fifo_int5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int5_err0 : 1; /* [0] */ + u32 msc_fifo_int5_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int5_err1 : 1; /* [2] */ + u32 msc_fifo_int5_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int5_err2 : 1; /* [4] */ + u32 msc_fifo_int5_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int5_err3 : 1; /* [6] */ + u32 msc_fifo_int5_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int5_err4 : 1; /* [8] */ + u32 msc_fifo_int5_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int5_err5 : 1; /* [10] */ + u32 msc_fifo_int5_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int5_err6 : 1; /* [12] */ + u32 msc_fifo_int5_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int5_err7 : 1; /* [14] */ + u32 msc_fifo_int5_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int5_err8 : 1; /* [16] */ + u32 msc_fifo_int5_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int5_err9 : 1; /* [18] */ + u32 msc_fifo_int5_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int5_err10 : 1; /* [20] */ + u32 msc_fifo_int5_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int5_err11 : 1; /* [22] */ + u32 msc_fifo_int5_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int5_err12 : 1; /* [24] */ + u32 msc_fifo_int5_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int5_err13 : 1; /* [26] */ + u32 msc_fifo_int5_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int5_err14 : 1; /* [28] */ + u32 msc_fifo_int5_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int5_err15 : 1; /* [30] */ + u32 msc_fifo_int5_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int5_u; + +/* Define the union csr_msc_fifo_int5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int5_err0_en : 1; /* [0] */ + u32 msc_fifo_int5_err1_en : 1; /* [1] */ + u32 msc_fifo_int5_err2_en : 1; /* [2] */ + u32 msc_fifo_int5_err3_en : 1; /* [3] */ + u32 msc_fifo_int5_err4_en : 1; /* [4] */ + u32 msc_fifo_int5_err5_en : 1; /* [5] */ + u32 msc_fifo_int5_err6_en : 1; /* [6] */ + u32 msc_fifo_int5_err7_en : 1; /* [7] */ + u32 msc_fifo_int5_err8_en : 1; /* [8] */ + u32 msc_fifo_int5_err9_en : 1; /* [9] */ + u32 msc_fifo_int5_err10_en : 1; /* [10] */ + u32 msc_fifo_int5_err11_en : 1; /* [11] */ + u32 msc_fifo_int5_err12_en : 1; /* [12] */ + u32 msc_fifo_int5_err13_en : 1; /* [13] */ + u32 msc_fifo_int5_err14_en : 1; /* [14] */ + u32 msc_fifo_int5_err15_en : 1; /* [15] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int5_mask_u; + +/* Define the union csr_msc_fifo_int6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int6_err0 : 1; /* [0] */ + u32 msc_fifo_int6_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int6_err1 : 1; /* [2] */ + u32 msc_fifo_int6_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int6_err2 : 1; /* [4] */ + u32 msc_fifo_int6_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int6_err3 : 1; /* [6] */ + u32 msc_fifo_int6_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int6_err4 : 1; /* [8] */ + u32 msc_fifo_int6_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int6_err5 : 1; /* [10] */ + u32 msc_fifo_int6_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int6_err6 : 1; /* [12] */ + u32 msc_fifo_int6_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int6_err7 : 1; /* [14] */ + u32 msc_fifo_int6_err7_insrt : 1; /* [15] */ + u32 msc_fifo_int6_err8 : 1; /* [16] */ + u32 msc_fifo_int6_err8_insrt : 1; /* [17] */ + u32 msc_fifo_int6_err9 : 1; /* [18] */ + u32 msc_fifo_int6_err9_insrt : 1; /* [19] */ + u32 msc_fifo_int6_err10 : 1; /* [20] */ + u32 msc_fifo_int6_err10_insrt : 1; /* [21] */ + u32 msc_fifo_int6_err11 : 1; /* [22] */ + u32 msc_fifo_int6_err11_insrt : 1; /* [23] */ + u32 msc_fifo_int6_err12 : 1; /* [24] */ + u32 msc_fifo_int6_err12_insrt : 1; /* [25] */ + u32 msc_fifo_int6_err13 : 1; /* [26] */ + u32 msc_fifo_int6_err13_insrt : 1; /* [27] */ + u32 msc_fifo_int6_err14 : 1; /* [28] */ + u32 msc_fifo_int6_err14_insrt : 1; /* [29] */ + u32 msc_fifo_int6_err15 : 1; /* [30] */ + u32 msc_fifo_int6_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int6_u; + +/* Define the union csr_msc_fifo_int6_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int6_err0_en : 1; /* [0] */ + u32 msc_fifo_int6_err1_en : 1; /* [1] */ + u32 msc_fifo_int6_err2_en : 1; /* [2] */ + u32 msc_fifo_int6_err3_en : 1; /* [3] */ + u32 msc_fifo_int6_err4_en : 1; /* [4] */ + u32 msc_fifo_int6_err5_en : 1; /* [5] */ + u32 msc_fifo_int6_err6_en : 1; /* [6] */ + u32 msc_fifo_int6_err7_en : 1; /* [7] */ + u32 msc_fifo_int6_err8_en : 1; /* [8] */ + u32 msc_fifo_int6_err9_en : 1; /* [9] */ + u32 msc_fifo_int6_err10_en : 1; /* [10] */ + u32 msc_fifo_int6_err11_en : 1; /* [11] */ + u32 msc_fifo_int6_err12_en : 1; /* [12] */ + u32 msc_fifo_int6_err13_en : 1; /* [13] */ + u32 msc_fifo_int6_err14_en : 1; /* [14] */ + u32 msc_fifo_int6_err15_en : 1; /* [15] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int6_mask_u; + +/* Define the union csr_msc_fifo_int7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int7_err0 : 1; /* [0] */ + u32 msc_fifo_int7_err0_insrt : 1; /* [1] */ + u32 msc_fifo_int7_err1 : 1; /* [2] */ + u32 msc_fifo_int7_err1_insrt : 1; /* [3] */ + u32 msc_fifo_int7_err2 : 1; /* [4] */ + u32 msc_fifo_int7_err2_insrt : 1; /* [5] */ + u32 msc_fifo_int7_err3 : 1; /* [6] */ + u32 msc_fifo_int7_err3_insrt : 1; /* [7] */ + u32 msc_fifo_int7_err4 : 1; /* [8] */ + u32 msc_fifo_int7_err4_insrt : 1; /* [9] */ + u32 msc_fifo_int7_err5 : 1; /* [10] */ + u32 msc_fifo_int7_err5_insrt : 1; /* [11] */ + u32 msc_fifo_int7_err6 : 1; /* [12] */ + u32 msc_fifo_int7_err6_insrt : 1; /* [13] */ + u32 msc_fifo_int7_err7 : 1; /* [14] */ + u32 msc_fifo_int7_err7_insrt : 1; /* [15] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int7_u; + +/* Define the union csr_msc_fifo_int7_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo_int7_err0_en : 1; /* [0] */ + u32 msc_fifo_int7_err1_en : 1; /* [1] */ + u32 msc_fifo_int7_err2_en : 1; /* [2] */ + u32 msc_fifo_int7_err3_en : 1; /* [3] */ + u32 msc_fifo_int7_err4_en : 1; /* [4] */ + u32 msc_fifo_int7_err5_en : 1; /* [5] */ + u32 msc_fifo_int7_err6_en : 1; /* [6] */ + u32 msc_fifo_int7_err7_en : 1; /* [7] */ + u32 rsv_17 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_int7_mask_u; + +/* Define the union csr_msc_bp_delay_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_bp_delay_cnt : 16; /* [15:0] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_bp_delay_cnt_u; + +/* Define the union csr_msc_vf_sp_cnt_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vf_sp_cnt_flag_en : 1; /* [0] */ + u32 rsv_19 : 3; /* [3:1] */ + u32 socep_sp_cnt_flag_en : 1; /* [4] */ + u32 rsv_20 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_vf_sp_cnt_en_u; + +/* Define the union csr_presub_pktlen_ns_stf_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktlen_ns_stf : 18; /* [17:0] */ + u32 rsv_21 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktlen_ns_stf_u; + +/* Define the union csr_presub_pktlen_ns_stl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktlen_ns_stl : 18; /* [17:0] */ + u32 rsv_22 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktlen_ns_stl_u; + +/* Define the union csr_cmq_presub_pktlen_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmq_presub_pktlen_cs : 18; /* [17:0] */ + u32 rsv_23 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmq_presub_pktlen_cs_u; + +/* Define the union csr_nfmq_presub_pktlen_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_presub_pktlen_cs : 18; /* [17:0] */ + u32 rsv_24 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nfmq_presub_pktlen_cs_u; + +/* Define the union csr_presub_pktnum_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktnum_ns_stl : 8; /* [7:0] */ + u32 presub_pktnum_ns_stf : 8; /* [15:8] */ + u32 presub_pktnum_cs_cmq : 8; /* [23:16] */ + u32 presub_pktnum_cs_nfmq : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktnum_u; + +/* Define the union csr_presub_pktlen_socnmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktlen_socnmq : 18; /* [17:0] */ + u32 rsv_25 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktlen_socnmq_u; + +/* Define the union csr_presub_pktlen_soccmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktlen_soccmq : 18; /* [17:0] */ + u32 rsv_26 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktlen_soccmq_u; + +/* Define the union csr_presub_pktnum_soc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 presub_pktnum_socnmq : 8; /* [7:0] */ + u32 presub_pktnum_soccmq : 8; /* [15:8] */ + u32 rsv_27 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_presub_pktnum_soc_u; + +/* Define the union csr_msc_pps_shaper_cfg_pktlen_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_pps_typical_pktlen_cfg : 3; /* [2:0] */ + u32 rsv_28 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_pps_shaper_cfg_pktlen_u; + +/* Define the union csr_msc_root_crr_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_crr_weight_cfg_ns : 3; /* [2:0] */ + u32 rsv_29 : 5; /* [7:3] */ + u32 msc_crr_weight_cfg_cs : 3; /* [10:8] */ + u32 rsv_30 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_root_crr_weight_cfg_u; + +/* Define the union csr_socmsc_root_sch_wgt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_rt_sch_wgt_cfg : 3; /* [2:0] */ + u32 rsv_31 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_root_sch_wgt_cfg_u; + +/* Define the union csr_weight_ns_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_weight_ns_offset : 5; /* [4:0] */ + u32 rsv_32 : 3; /* [7:5] */ + u32 ep_weight_ns_offset : 5; /* [12:8] */ + u32 rsv_33 : 3; /* [15:13] */ + u32 host_weight_ns_offset : 5; /* [20:16] */ + u32 rsv_34 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_weight_ns_offset_u; + +/* Define the union csr_weight_cs_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_cos_weight_cs_offset : 5; /* [4:0] */ + u32 rsv_35 : 3; /* [7:5] */ + u32 cmq_cos_weight_cs_offset : 5; /* [12:8] */ + u32 rsv_36 : 3; /* [15:13] */ + u32 ep_weight_cs_offset : 5; /* [20:16] */ + u32 rsv_37 : 3; /* [23:21] */ + u32 host_weight_cs_offset : 5; /* [28:24] */ + u32 rsv_38 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_weight_cs_offset_u; + +/* Define the union csr_weight_mscsoc_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soc_mq_weight_offset : 5; /* [4:0] */ + u32 rsv_39 : 3; /* [7:5] */ + u32 soc_ep_weight_offset : 5; /* [12:8] */ + u32 rsv_40 : 3; /* [15:13] */ + u32 soc_serv_weight_offset : 5; /* [20:16] */ + u32 rsv_41 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_weight_mscsoc_offset_u; + +/* Define the union csr_host_weight_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_weight_ns_0 : 8; /* [7:0] */ + u32 host_weight_ns_1 : 8; /* [15:8] */ + u32 host_weight_ns_2 : 8; /* [23:16] */ + u32 host_weight_ns_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_weight_ns_u; + +/* Define the union csr_host_weight_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_weight_cs_0 : 8; /* [7:0] */ + u32 host_weight_cs_1 : 8; /* [15:8] */ + u32 host_weight_cs_2 : 8; /* [23:16] */ + u32 host_weight_cs_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_weight_cs_u; + +/* Define the union csr_qa_weight_cfg_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_qa_weight_cfg_cs : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_qa_weight_cfg_cs_u; + +/* Define the union csr_ep_weight_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mscep_weight_cfg_ns : 8; /* [7:0] */ + u32 rsv_43 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_weight_cfg_ns_u; + +/* Define the union csr_ep_weight_cfg_cmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mscep_weight_cfg_cmq : 8; /* [7:0] */ + u32 rsv_44 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_weight_cfg_cmq_u; + +/* Define the union csr_ep_weight_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mscep_weight_cfg_nfmq : 8; /* [7:0] */ + u32 rsv_45 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_weight_cfg_nfmq_u; + +/* Define the union csr_soc_mq_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmq_weight_cfg : 8; /* [7:0] */ + u32 rsv_46 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_mq_weight_cfg_u; + +/* Define the union csr_soc_ep_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socep_weight_cfg : 8; /* [7:0] */ + u32 rsv_47 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_ep_weight_cfg_u; + +/* Define the union csr_soc_serv_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socserv_weight_cfg : 8; /* [7:0] */ + u32 rsv_48 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soc_serv_weight_cfg_u; + +/* Define the union csr_host_shap_bps_cfg_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_bps_cfg_cs : 25; /* [24:0] */ + u32 rsv_49 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_bps_cfg_cs_u; + +/* Define the union csr_host_shap_pps_cfg_cs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_pps_cfg_cs : 25; /* [24:0] */ + u32 rsv_50 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_pps_cfg_cs_u; + +/* Define the union csr_host_shap_bps_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_bps_cfg_ns : 25; /* [24:0] */ + u32 rsv_51 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_bps_cfg_ns_u; + +/* Define the union csr_host_shap_pps_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_pps_cfg_ns : 25; /* [24:0] */ + u32 rsv_52 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_pps_cfg_ns_u; + +/* Define the union csr_ep_shap_bps_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_bps_cfg_ns : 25; /* [24:0] */ + u32 rsv_53 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_bps_cfg_ns_u; + +/* Define the union csr_ep_shap_pps_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_pps_cfg_ns : 25; /* [24:0] */ + u32 rsv_54 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_pps_cfg_ns_u; + +/* Define the union csr_ep_shap_bps_cfg_cmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_bps_cfg_cmq : 25; /* [24:0] */ + u32 rsv_55 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_bps_cfg_cmq_u; + +/* Define the union csr_ep_shap_pps_cfg_cmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_pps_cfg_cmq : 25; /* [24:0] */ + u32 rsv_56 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_pps_cfg_cmq_u; + +/* Define the union csr_ep_shap_bps_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_bps_cfg_nfmq : 25; /* [24:0] */ + u32 rsv_57 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_bps_cfg_nfmq_u; + +/* Define the union csr_ep_shap_pps_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_pps_cfg_nfmq : 25; /* [24:0] */ + u32 rsv_58 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_pps_cfg_nfmq_u; + +/* Define the union csr_socmq_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmq_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_59 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmq_shap_bps_cfg_u; + +/* Define the union csr_socmq_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmq_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_60 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmq_shap_pps_cfg_u; + +/* Define the union csr_socep_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socep_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_61 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socep_shap_bps_cfg_u; + +/* Define the union csr_socep_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socep_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_62 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socep_shap_pps_cfg_u; + +/* Define the union csr_socserv_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socserv_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_63 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socserv_shap_bps_cfg_u; + +/* Define the union csr_socserv_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socserv_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_64 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socserv_shap_pps_cfg_u; + +/* Define the union csr_socrt_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socrt_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_65 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socrt_shap_bps_cfg_u; + +/* Define the union csr_socrt_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socrt_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_66 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socrt_shap_pps_cfg_u; + +/* Define the union csr_msc_shap_bypass_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_nmq_shap_byp_vld : 1; /* [0] */ + u32 msc_ns_vnic_shap_byp_vld : 1; /* [1] */ + u32 msc_ns_vnicgrp_shap_byp_vld : 1; /* [2] */ + u32 msc_ns_ep_shap_byp_vld : 1; /* [3] */ + u32 msc_ns_host_shap_byp_vld : 1; /* [4] */ + u32 rsv_67 : 3; /* [7:5] */ + u32 msc_cmq_shap_byp_vld : 1; /* [8] */ + u32 msc_nfmq_vnic_shap_byp_vld : 1; /* [9] */ + u32 msc_cs_ep_shap_byp_vld : 1; /* [10] */ + u32 msc_cs_host_shap_byp_vld : 1; /* [11] */ + u32 rsv_68 : 4; /* [15:12] */ + u32 socmsc_mq_shap_byp_vld : 1; /* [16] */ + u32 socmsc_ep_shap_byp_vld : 1; /* [17] */ + u32 socmsc_serv_shap_byp_vld : 1; /* [18] */ + u32 socmsc_rt_shap_byp_vld : 1; /* [19] */ + u32 rsv_69 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_shap_bypass_cfg_u; + +/* Define the union csr_msc_host_root_xon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_xon_cfg_ns : 4; /* [3:0] */ + u32 msc_host_xon_cfg_cs : 4; /* [7:4] */ + u32 msc_root_xon_cfg_ns : 1; /* [8] */ + u32 msc_root_xon_cfg_cs : 1; /* [9] */ + u32 rsv_70 : 2; /* [11:10] */ + u32 msc_root_xon_cfg : 1; /* [12] */ + u32 rsv_71 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_host_root_xon_cfg_u; + +/* Define the union csr_msc_soc_root_xon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ep_xon_cfg_ns : 8; /* [7:0] */ + u32 socmsc_ep_xon_cfg_cs : 8; /* [15:8] */ + u32 socmsc_root_xon_cfg_ns : 1; /* [16] */ + u32 socmsc_root_xon_cfg_cs : 1; /* [17] */ + u32 rsv_72 : 6; /* [23:18] */ + u32 socmsc_root_xon_cfg : 1; /* [24] */ + u32 rsv_73 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_soc_root_xon_cfg_u; + +/* Define the union csr_msc_host_ep_xon_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_hostep_xon_cfg_ns : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_host_ep_xon_cfg_ns_u; + +/* Define the union csr_msc_host_ep_xon_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_hostep_xon_cfg_nfmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_host_ep_xon_cfg_nfmq_u; + +/* Define the union csr_msc_host_ep_xon_cfg_cmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_hostep_xon_cfg_cmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_host_ep_xon_cfg_cmq_u; + +/* Define the union csr_socmsc_mq_xon_cfg_ns_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_mq_xon_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_mq_xon_cfg_ns_u; + +/* Define the union csr_msc_prm_port_bp_sta0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_mqm_dp_ep_bp : 8; /* [7:0] */ + u32 prm_mqm_cp_ep_bp : 8; /* [15:8] */ + u32 prm_mqm_dp_root_bp : 1; /* [16] */ + u32 prm_mqm_cp_root_bp : 1; /* [17] */ + u32 prm_mqm_root_bp : 1; /* [18] */ + u32 rsv_74 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_prm_port_bp_sta0_u; + +/* Define the union csr_msc_prm_port_bp_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_mqm_soc_dp_cos_bp : 8; /* [7:0] */ + u32 prm_mqm_soc_cp_cos_bp : 8; /* [15:8] */ + u32 prm_mqm_soc_dp_root_bp : 1; /* [16] */ + u32 prm_mqm_soc_cp_root_bp : 1; /* [17] */ + u32 rsv_75 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_prm_port_bp_sta1_u; + +/* Define the union csr_msc_qu_cos_bp_sta0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_mqm_dp_ep_cos_bp0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_qu_cos_bp_sta0_u; + +/* Define the union csr_msc_qu_cos_bp_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_mqm_dp_ep_cos_bp1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_qu_cos_bp_sta1_u; + +/* Define the union csr_socmsc_rt_ep_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_el_bp : 16; /* [15:0] */ + u32 socmsc_sl_bp : 2; /* [17:16] */ + u32 socmsc_rl_bp : 1; /* [18] */ + u32 rsv_76 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_rt_ep_bp_sta_u; + +/* Define the union csr_socmsc_queue_bp_sta0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_bp0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_bp_sta0_u; + +/* Define the union csr_socmsc_queue_bp_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_bp1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_bp_sta1_u; + +/* Define the union csr_socmsc_queue_bp_sta2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_bp2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_bp_sta2_u; + +/* Define the union csr_socmsc_queue_bp_sta3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_bp3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_bp_sta3_u; + +/* Define the union csr_socmsc_queue_eligible_sta0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_eligible0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_eligible_sta0_u; + +/* Define the union csr_socmsc_queue_eligible_sta1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_eligible1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_eligible_sta1_u; + +/* Define the union csr_socmsc_queue_eligible_sta2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_eligible2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_eligible_sta2_u; + +/* Define the union csr_socmsc_queue_eligible_sta3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_ql_eligible3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_queue_eligible_sta3_u; + +/* Define the union csr_msc_rt_host_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ns_hl_bp : 4; /* [3:0] */ + u32 msc_cs_hl_bp : 4; /* [7:4] */ + u32 msc_ns_sl_bp : 1; /* [8] */ + u32 msc_cs_sl_bp : 1; /* [9] */ + u32 msc_rl_bp : 1; /* [10] */ + u32 enqc_msc_dp_bp : 1; /* [11] */ + u32 enqc_msc_cp_bp : 1; /* [12] */ + u32 rsv_77 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_rt_host_bp_sta_u; + +/* Define the union csr_msc_hostep_ns_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_ep_ns_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_hostep_ns_bp_sta_u; + +/* Define the union csr_msc_hostep_nfmq_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_ep_nfmq_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_hostep_nfmq_bp_sta_u; + +/* Define the union csr_msc_hostep_cmq_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_ep_cmq_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_hostep_cmq_bp_sta_u; + +/* Define the union csr_msc_fifo_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ns_du_fifo_gap : 4; /* [3:0] */ + u32 msc_cs_du_fifo_gap : 4; /* [7:4] */ + u32 socmsc_du_fifo_gap : 3; /* [10:8] */ + u32 rsv_78 : 1; /* [11] */ + u32 msc_fast_cnp_fifo_gap : 4; /* [15:12] */ + u32 rsv_79 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_th_cfg_u; + +/* Define the union csr_msc_fifo_st0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo0_st0 : 2; /* [1:0] */ + u32 msc_fifo1_st0 : 2; /* [3:2] */ + u32 msc_fifo2_st0 : 2; /* [5:4] */ + u32 msc_fifo3_st0 : 2; /* [7:6] */ + u32 msc_fifo4_st0 : 2; /* [9:8] */ + u32 msc_fifo5_st0 : 2; /* [11:10] */ + u32 msc_fifo6_st0 : 2; /* [13:12] */ + u32 msc_fifo7_st0 : 2; /* [15:14] */ + u32 msc_fifo8_st0 : 2; /* [17:16] */ + u32 msc_fifo9_st0 : 2; /* [19:18] */ + u32 msc_fifo10_st0 : 2; /* [21:20] */ + u32 msc_fifo11_st0 : 2; /* [23:22] */ + u32 msc_fifo12_st0 : 2; /* [25:24] */ + u32 msc_fifo13_st0 : 2; /* [27:26] */ + u32 msc_fifo14_st0 : 2; /* [29:28] */ + u32 msc_fifo15_st0 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_st0_u; + +/* Define the union csr_msc_fifo_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo0_st1 : 2; /* [1:0] */ + u32 msc_fifo1_st1 : 2; /* [3:2] */ + u32 msc_fifo2_st1 : 2; /* [5:4] */ + u32 msc_fifo3_st1 : 2; /* [7:6] */ + u32 msc_fifo4_st1 : 2; /* [9:8] */ + u32 msc_fifo5_st1 : 2; /* [11:10] */ + u32 msc_fifo6_st1 : 2; /* [13:12] */ + u32 msc_fifo7_st1 : 2; /* [15:14] */ + u32 msc_fifo8_st1 : 2; /* [17:16] */ + u32 msc_fifo9_st1 : 2; /* [19:18] */ + u32 msc_fifo10_st1 : 2; /* [21:20] */ + u32 msc_fifo11_st1 : 2; /* [23:22] */ + u32 msc_fifo12_st1 : 2; /* [25:24] */ + u32 msc_fifo13_st1 : 2; /* [27:26] */ + u32 msc_fifo14_st1 : 2; /* [29:28] */ + u32 msc_fifo15_st1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_st1_u; + +/* Define the union csr_msc_fifo_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo0_st2 : 2; /* [1:0] */ + u32 msc_fifo1_st2 : 2; /* [3:2] */ + u32 msc_fifo2_st2 : 2; /* [5:4] */ + u32 msc_fifo3_st2 : 2; /* [7:6] */ + u32 msc_fifo4_st2 : 2; /* [9:8] */ + u32 msc_fifo5_st2 : 2; /* [11:10] */ + u32 msc_fifo6_st2 : 2; /* [13:12] */ + u32 msc_fifo7_st2 : 2; /* [15:14] */ + u32 msc_fifo8_st2 : 2; /* [17:16] */ + u32 msc_fifo9_st2 : 2; /* [19:18] */ + u32 msc_fifo10_st2 : 2; /* [21:20] */ + u32 msc_fifo11_st2 : 2; /* [23:22] */ + u32 msc_fifo12_st2 : 2; /* [25:24] */ + u32 msc_fifo13_st2 : 2; /* [27:26] */ + u32 msc_fifo14_st2 : 2; /* [29:28] */ + u32 msc_fifo15_st2 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_st2_u; + +/* Define the union csr_msc_fifo_st3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_fifo0_st3 : 2; /* [1:0] */ + u32 msc_fifo1_st3 : 2; /* [3:2] */ + u32 msc_fifo2_st3 : 2; /* [5:4] */ + u32 msc_fifo3_st3 : 2; /* [7:6] */ + u32 msc_fifo4_st3 : 2; /* [9:8] */ + u32 msc_fifo5_st3 : 2; /* [11:10] */ + u32 msc_fifo6_st3 : 2; /* [13:12] */ + u32 msc_fifo7_st3 : 2; /* [15:14] */ + u32 msc_fifo8_st3 : 2; /* [17:16] */ + u32 msc_fifo9_st3 : 2; /* [19:18] */ + u32 msc_fifo10_st3 : 2; /* [21:20] */ + u32 msc_fifo11_st3 : 2; /* [23:22] */ + u32 rsv_80 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_fifo_st3_u; + +/* Define the union csr_cmq_rx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmq_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmq_rx_up_cnt_u; + +/* Define the union csr_nfmq_rx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nfmq_rx_up_cnt_u; + +/* Define the union csr_nmq_rx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nmq_rx_up_cnt_u; + +/* Define the union csr_cmq_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmq_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmq_sch_cnt_u; + +/* Define the union csr_nfmq_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nfmq_sch_cnt_u; + +/* Define the union csr_nmq_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nmq_sch_cnt_u; + +/* Define the union csr_soccmq_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soccmq_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soccmq_up_cnt_u; + +/* Define the union csr_socnmq_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socnmq_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socnmq_up_cnt_u; + +/* Define the union csr_soccmq_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soccmq_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soccmq_sch_cnt_u; + +/* Define the union csr_socnmq_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socnmq_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socnmq_sch_cnt_u; + +/* Define the union csr_cmq_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmq_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmq_empt_sch_cnt_u; + +/* Define the union csr_nfmq_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nfmq_empt_sch_cnt_u; + +/* Define the union csr_nmq_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nmq_empt_sch_cnt_u; + +/* Define the union csr_cmq_rx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cmq_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cmq_rx_du_cnt_u; + +/* Define the union csr_nfmq_rx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nfmq_rx_du_cnt_u; + +/* Define the union csr_nmq_rx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_nmq_rx_du_cnt_u; + +/* Define the union csr_soccmq_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 soccmq_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_soccmq_du_cnt_u; + +/* Define the union csr_socnmq_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socnmq_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socnmq_du_cnt_u; + +/* Define the union csr_msc_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ecc_1bit_err_cnt_u; + +/* Define the union csr_msc_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ecc_2bit_err_cnt_u; + +/* Define the union csr_sch_mq_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_mq_dfx_cfg : 13; /* [12:0] */ + u32 rsv_81 : 3; /* [15:13] */ + u32 sch_mq_qa_dfx_cfg : 2; /* [17:16] */ + u32 rsv_82 : 2; /* [19:18] */ + u32 sch_mq_dfx_cfg_vld : 1; /* [20] */ + u32 rsv_83 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_mq_dfx_cfg_u; + +/* Define the union csr_sch_mq_dfx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_mq_dfx_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_mq_dfx_up_cnt_u; + +/* Define the union csr_sch_mq_dfx_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_mq_dfx_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_mq_dfx_sch_cnt_u; + +/* Define the union csr_sch_mq_dfx_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_mq_dfx_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_mq_dfx_empt_sch_cnt_u; + +/* Define the union csr_sch_mq_dfx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_mq_dfx_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_mq_dfx_du_cnt_u; + +/* Define the union csr_sch_socmq_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_socmq_dfx_cfg : 7; /* [6:0] */ + u32 rsv_84 : 1; /* [7] */ + u32 sch_socmq_dfx_cfg_vld : 1; /* [8] */ + u32 rsv_85 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_socmq_dfx_cfg_u; + +/* Define the union csr_sch_socmq_dfx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_socmq_dfx_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_socmq_dfx_up_cnt_u; + +/* Define the union csr_sch_socmq_dfx_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_socmq_dfx_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_socmq_dfx_sch_cnt_u; + +/* Define the union csr_sch_socmq_dfx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_socmq_dfx_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_socmq_dfx_du_cnt_u; + +/* Define the union csr_socmsc_mcd_du_info_ptr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_mcd_len_info : 26; /* [25:0] */ + u32 rsv_86 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_mcd_du_info_ptr0_u; + +/* Define the union csr_socmsc_mcd_du_info_ptr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 socmsc_mcd_id_info : 10; /* [9:0] */ + u32 rsv_87 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_socmsc_mcd_du_info_ptr1_u; + +/* Define the union csr_msc_cs_mcd_du_info_ptr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_cs_len_info : 26; /* [25:0] */ + u32 rsv_88 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_cs_mcd_du_info_ptr0_u; + +/* Define the union csr_msc_cs_mcd_du_info_ptr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_cs_id_info_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_cs_mcd_du_info_ptr1_u; + +/* Define the union csr_msc_cs_mcd_du_info_ptr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_cs_id_info_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_cs_mcd_du_info_ptr2_u; + +/* Define the union csr_msc_ns_mcd_du_info_ptr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_ns_len_info : 26; /* [25:0] */ + u32 rsv_89 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ns_mcd_du_info_ptr0_u; + +/* Define the union csr_msc_ns_mcd_du_info_ptr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_ns_id_info_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ns_mcd_du_info_ptr1_u; + +/* Define the union csr_msc_ns_mcd_du_info_ptr2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_mcd_ns_id_info_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_msc_ns_mcd_du_info_ptr2_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_msc_rw_rsv0_u msc_rw_rsv0; /* 0 */ + volatile csr_msc_rw_rsv1_u msc_rw_rsv1; /* 4 */ + volatile csr_msc_rw_rsv2_u msc_rw_rsv2; /* 8 */ + volatile csr_msc_rw_rsv3_u msc_rw_rsv3; /* C */ + volatile csr_msc_indrect_ctrl_u msc_indrect_ctrl; /* 10 */ + volatile csr_msc_indrect_timeout_u msc_indrect_timeout; /* 14 */ + volatile csr_msc_indrect_data_0_u msc_indrect_data_0; /* 18 */ + volatile csr_msc_indrect_data_1_u msc_indrect_data_1; /* 1C */ + volatile csr_msc_mem_ecc_bypass_en_u msc_mem_ecc_bypass_en; /* 20 */ + volatile csr_msc_mem_ctrl_bus_cfg0_u msc_mem_ctrl_bus_cfg0; /* 24 */ + volatile csr_msc_mem_ctrl_bus_cfg1_u msc_mem_ctrl_bus_cfg1; /* 28 */ + volatile csr_msc_mem_ctrl_bus_cfg2_u msc_mem_ctrl_bus_cfg2; /* 2C */ + volatile csr_msc_mem_ctrl_bus_cfg3_u msc_mem_ctrl_bus_cfg3; /* 30 */ + volatile csr_msc_mem_ctrl_bus_cfg4_u msc_mem_ctrl_bus_cfg4; /* 34 */ + volatile csr_msc_int_vector_u msc_int_vector; /* 100 */ + volatile csr_msc_int_u msc_int; /* 104 */ + volatile csr_msc_int_en_u msc_int_en; /* 108 */ + volatile csr_msc_mem_err_req0_u msc_mem_err_req0; /* 10C */ + volatile csr_msc_mem_err_req1_u msc_mem_err_req1; /* 110 */ + volatile csr_msc_mem_err_req2_u msc_mem_err_req2; /* 114 */ + volatile csr_msc_mem_err_req3_u msc_mem_err_req3; /* 118 */ + volatile csr_msc_mem_err_req4_u msc_mem_err_req4; /* 11C */ + volatile csr_msc_ecc_one_bit_int_u msc_ecc_one_bit_int; /* 120 */ + volatile csr_msc_ecc_two_bit_int_u msc_ecc_two_bit_int; /* 124 */ + volatile csr_msc_mq_bind_int_u msc_mq_bind_int; /* 128 */ + volatile csr_msc_vnic_spcnt_inf_int_u msc_vnic_spcnt_inf_int; /* 12C */ + volatile csr_msc_vnic_spcnt_cal_int_u msc_vnic_spcnt_cal_int; /* 130 */ + volatile csr_msc_socep_spcnt_inf_int_u msc_socep_spcnt_inf_int; /* 134 */ + volatile csr_msc_socep_spcnt_cal_int_u msc_socep_spcnt_cal_int; /* 138 */ + volatile csr_msc_fifo_int0_u msc_fifo_int0; /* 150 */ + volatile csr_msc_fifo_int0_mask_u msc_fifo_int0_mask; /* 154 */ + volatile csr_msc_fifo_int1_u msc_fifo_int1; /* 158 */ + volatile csr_msc_fifo_int1_mask_u msc_fifo_int1_mask; /* 15C */ + volatile csr_msc_fifo_int2_u msc_fifo_int2; /* 160 */ + volatile csr_msc_fifo_int2_mask_u msc_fifo_int2_mask; /* 164 */ + volatile csr_msc_fifo_int3_u msc_fifo_int3; /* 168 */ + volatile csr_msc_fifo_int3_mask_u msc_fifo_int3_mask; /* 16C */ + volatile csr_msc_fifo_int4_u msc_fifo_int4; /* 170 */ + volatile csr_msc_fifo_int4_mask_u msc_fifo_int4_mask; /* 174 */ + volatile csr_msc_fifo_int5_u msc_fifo_int5; /* 178 */ + volatile csr_msc_fifo_int5_mask_u msc_fifo_int5_mask; /* 17C */ + volatile csr_msc_fifo_int6_u msc_fifo_int6; /* 180 */ + volatile csr_msc_fifo_int6_mask_u msc_fifo_int6_mask; /* 184 */ + volatile csr_msc_fifo_int7_u msc_fifo_int7; /* 188 */ + volatile csr_msc_fifo_int7_mask_u msc_fifo_int7_mask; /* 18C */ + volatile csr_msc_bp_delay_cnt_u msc_bp_delay_cnt; /* 200 */ + volatile csr_msc_vf_sp_cnt_en_u msc_vf_sp_cnt_en; /* 204 */ + volatile csr_presub_pktlen_ns_stf_u presub_pktlen_ns_stf; /* 250 */ + volatile csr_presub_pktlen_ns_stl_u presub_pktlen_ns_stl; /* 254 */ + volatile csr_cmq_presub_pktlen_cs_u cmq_presub_pktlen_cs; /* 258 */ + volatile csr_nfmq_presub_pktlen_cs_u nfmq_presub_pktlen_cs; /* 25C */ + volatile csr_presub_pktnum_u presub_pktnum; /* 260 */ + volatile csr_presub_pktlen_socnmq_u presub_pktlen_socnmq; /* 264 */ + volatile csr_presub_pktlen_soccmq_u presub_pktlen_soccmq; /* 268 */ + volatile csr_presub_pktnum_soc_u presub_pktnum_soc; /* 26C */ + volatile csr_msc_pps_shaper_cfg_pktlen_u msc_pps_shaper_cfg_pktlen; /* 270 */ + volatile csr_msc_root_crr_weight_cfg_u msc_root_crr_weight_cfg; /* 274 */ + volatile csr_socmsc_root_sch_wgt_cfg_u socmsc_root_sch_wgt_cfg; /* 278 */ + volatile csr_weight_ns_offset_u weight_ns_offset; /* 27C */ + volatile csr_weight_cs_offset_u weight_cs_offset; /* 280 */ + volatile csr_weight_mscsoc_offset_u weight_mscsoc_offset; /* 284 */ + volatile csr_host_weight_ns_u host_weight_ns; /* 288 */ + volatile csr_host_weight_cs_u host_weight_cs; /* 28C */ + volatile csr_qa_weight_cfg_cs_u qa_weight_cfg_cs[4]; /* 2F0 */ + volatile csr_ep_weight_cfg_ns_u ep_weight_cfg_ns[32]; /* 300 */ + volatile csr_ep_weight_cfg_cmq_u ep_weight_cfg_cmq[32]; /* 380 */ + volatile csr_ep_weight_cfg_nfmq_u ep_weight_cfg_nfmq[32]; /* 400 */ + volatile csr_soc_mq_weight_cfg_u soc_mq_weight_cfg[128]; /* 500 */ + volatile csr_soc_ep_weight_cfg_u soc_ep_weight_cfg[16]; /* 700 */ + volatile csr_soc_serv_weight_cfg_u soc_serv_weight_cfg[2]; /* 740 */ + volatile csr_host_shap_bps_cfg_cs_u host_shap_bps_cfg_cs[4]; /* 750 */ + volatile csr_host_shap_pps_cfg_cs_u host_shap_pps_cfg_cs[4]; /* 760 */ + volatile csr_host_shap_bps_cfg_ns_u host_shap_bps_cfg_ns[4]; /* 770 */ + volatile csr_host_shap_pps_cfg_ns_u host_shap_pps_cfg_ns[4]; /* 780 */ + volatile csr_ep_shap_bps_cfg_ns_u ep_shap_bps_cfg_ns[32]; /* 790 */ + volatile csr_ep_shap_pps_cfg_ns_u ep_shap_pps_cfg_ns[32]; /* 810 */ + volatile csr_ep_shap_bps_cfg_cmq_u ep_shap_bps_cfg_cmq[32]; /* 890 */ + volatile csr_ep_shap_pps_cfg_cmq_u ep_shap_pps_cfg_cmq[32]; /* 910 */ + volatile csr_ep_shap_bps_cfg_nfmq_u ep_shap_bps_cfg_nfmq[32]; /* 990 */ + volatile csr_ep_shap_pps_cfg_nfmq_u ep_shap_pps_cfg_nfmq[32]; /* A10 */ + volatile csr_socmq_shap_bps_cfg_u socmq_shap_bps_cfg[128]; /* B00 */ + volatile csr_socmq_shap_pps_cfg_u socmq_shap_pps_cfg[128]; /* D00 */ + volatile csr_socep_shap_bps_cfg_u socep_shap_bps_cfg[16]; /* F00 */ + volatile csr_socep_shap_pps_cfg_u socep_shap_pps_cfg[16]; /* F40 */ + volatile csr_socserv_shap_bps_cfg_u socserv_shap_bps_cfg[2]; /* F80 */ + volatile csr_socserv_shap_pps_cfg_u socserv_shap_pps_cfg[2]; /* F88 */ + volatile csr_socrt_shap_bps_cfg_u socrt_shap_bps_cfg; /* F90 */ + volatile csr_socrt_shap_pps_cfg_u socrt_shap_pps_cfg; /* F94 */ + volatile csr_msc_shap_bypass_cfg_u msc_shap_bypass_cfg; /* 1200 */ + volatile csr_msc_host_root_xon_cfg_u msc_host_root_xon_cfg; /* 1204 */ + volatile csr_msc_soc_root_xon_cfg_u msc_soc_root_xon_cfg; /* 1208 */ + volatile csr_msc_host_ep_xon_cfg_ns_u msc_host_ep_xon_cfg_ns; /* 120C */ + volatile csr_msc_host_ep_xon_cfg_nfmq_u msc_host_ep_xon_cfg_nfmq; /* 1210 */ + volatile csr_msc_host_ep_xon_cfg_cmq_u msc_host_ep_xon_cfg_cmq; /* 1214 */ + volatile csr_socmsc_mq_xon_cfg_ns_u socmsc_mq_xon_cfg_ns[4]; /* 1220 */ + volatile csr_msc_prm_port_bp_sta0_u msc_prm_port_bp_sta0; /* 1230 */ + volatile csr_msc_prm_port_bp_sta1_u msc_prm_port_bp_sta1; /* 1234 */ + volatile csr_msc_qu_cos_bp_sta0_u msc_qu_cos_bp_sta0; /* 1238 */ + volatile csr_msc_qu_cos_bp_sta1_u msc_qu_cos_bp_sta1; /* 123C */ + volatile csr_socmsc_rt_ep_bp_sta_u socmsc_rt_ep_bp_sta; /* 1240 */ + volatile csr_socmsc_queue_bp_sta0_u socmsc_queue_bp_sta0; /* 1244 */ + volatile csr_socmsc_queue_bp_sta1_u socmsc_queue_bp_sta1; /* 1248 */ + volatile csr_socmsc_queue_bp_sta2_u socmsc_queue_bp_sta2; /* 124C */ + volatile csr_socmsc_queue_bp_sta3_u socmsc_queue_bp_sta3; /* 1250 */ + volatile csr_socmsc_queue_eligible_sta0_u socmsc_queue_eligible_sta0; /* 1254 */ + volatile csr_socmsc_queue_eligible_sta1_u socmsc_queue_eligible_sta1; /* 1258 */ + volatile csr_socmsc_queue_eligible_sta2_u socmsc_queue_eligible_sta2; /* 125C */ + volatile csr_socmsc_queue_eligible_sta3_u socmsc_queue_eligible_sta3; /* 1260 */ + volatile csr_msc_rt_host_bp_sta_u msc_rt_host_bp_sta; /* 1264 */ + volatile csr_msc_hostep_ns_bp_sta_u msc_hostep_ns_bp_sta; /* 1268 */ + volatile csr_msc_hostep_nfmq_bp_sta_u msc_hostep_nfmq_bp_sta; /* 126C */ + volatile csr_msc_hostep_cmq_bp_sta_u msc_hostep_cmq_bp_sta; /* 1270 */ + volatile csr_msc_fifo_th_cfg_u msc_fifo_th_cfg; /* 1274 */ + volatile csr_msc_fifo_st0_u msc_fifo_st0; /* 1290 */ + volatile csr_msc_fifo_st1_u msc_fifo_st1; /* 1294 */ + volatile csr_msc_fifo_st2_u msc_fifo_st2; /* 1298 */ + volatile csr_msc_fifo_st3_u msc_fifo_st3; /* 129C */ + volatile csr_cmq_rx_up_cnt_u cmq_rx_up_cnt; /* 12A0 */ + volatile csr_nfmq_rx_up_cnt_u nfmq_rx_up_cnt; /* 12A4 */ + volatile csr_nmq_rx_up_cnt_u nmq_rx_up_cnt; /* 12A8 */ + volatile csr_cmq_sch_cnt_u cmq_sch_cnt; /* 12AC */ + volatile csr_nfmq_sch_cnt_u nfmq_sch_cnt; /* 12B0 */ + volatile csr_nmq_sch_cnt_u nmq_sch_cnt; /* 12B4 */ + volatile csr_soccmq_up_cnt_u soccmq_up_cnt; /* 12B8 */ + volatile csr_socnmq_up_cnt_u socnmq_up_cnt; /* 12BC */ + volatile csr_soccmq_sch_cnt_u soccmq_sch_cnt; /* 12C0 */ + volatile csr_socnmq_sch_cnt_u socnmq_sch_cnt; /* 12C4 */ + volatile csr_cmq_empt_sch_cnt_u cmq_empt_sch_cnt; /* 12C8 */ + volatile csr_nfmq_empt_sch_cnt_u nfmq_empt_sch_cnt; /* 12CC */ + volatile csr_nmq_empt_sch_cnt_u nmq_empt_sch_cnt; /* 12D0 */ + volatile csr_cmq_rx_du_cnt_u cmq_rx_du_cnt; /* 12D4 */ + volatile csr_nfmq_rx_du_cnt_u nfmq_rx_du_cnt; /* 12D8 */ + volatile csr_nmq_rx_du_cnt_u nmq_rx_du_cnt; /* 12DC */ + volatile csr_soccmq_du_cnt_u soccmq_du_cnt; /* 12E0 */ + volatile csr_socnmq_du_cnt_u socnmq_du_cnt; /* 12E4 */ + volatile csr_msc_ecc_1bit_err_cnt_u msc_ecc_1bit_err_cnt; /* 12E8 */ + volatile csr_msc_ecc_2bit_err_cnt_u msc_ecc_2bit_err_cnt; /* 12EC */ + volatile csr_sch_mq_dfx_cfg_u sch_mq_dfx_cfg; /* 1320 */ + volatile csr_sch_mq_dfx_up_cnt_u sch_mq_dfx_up_cnt; /* 1324 */ + volatile csr_sch_mq_dfx_sch_cnt_u sch_mq_dfx_sch_cnt; /* 1328 */ + volatile csr_sch_mq_dfx_empt_sch_cnt_u sch_mq_dfx_empt_sch_cnt; /* 132C */ + volatile csr_sch_mq_dfx_du_cnt_u sch_mq_dfx_du_cnt; /* 1330 */ + volatile csr_sch_socmq_dfx_cfg_u sch_socmq_dfx_cfg; /* 1334 */ + volatile csr_sch_socmq_dfx_up_cnt_u sch_socmq_dfx_up_cnt; /* 1338 */ + volatile csr_sch_socmq_dfx_sch_cnt_u sch_socmq_dfx_sch_cnt; /* 133C */ + volatile csr_sch_socmq_dfx_du_cnt_u sch_socmq_dfx_du_cnt; /* 1340 */ + volatile csr_socmsc_mcd_du_info_ptr0_u socmsc_mcd_du_info_ptr0; /* 1344 */ + volatile csr_socmsc_mcd_du_info_ptr1_u socmsc_mcd_du_info_ptr1; /* 1348 */ + volatile csr_msc_cs_mcd_du_info_ptr0_u msc_cs_mcd_du_info_ptr0; /* 134C */ + volatile csr_msc_cs_mcd_du_info_ptr1_u msc_cs_mcd_du_info_ptr1; /* 1350 */ + volatile csr_msc_cs_mcd_du_info_ptr2_u msc_cs_mcd_du_info_ptr2; /* 1354 */ + volatile csr_msc_ns_mcd_du_info_ptr0_u msc_ns_mcd_du_info_ptr0; /* 1358 */ + volatile csr_msc_ns_mcd_du_info_ptr1_u msc_ns_mcd_du_info_ptr1; /* 135C */ + volatile csr_msc_ns_mcd_du_info_ptr2_u msc_ns_mcd_du_info_ptr2; /* 1360 */ +} S_mqm_msc_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_msc */ +extern volatile S_mqm_msc_REGS_TYPE *gopmqm_mscAllReg; + +/* Declare the functions that set the member value */ +int iSetMSC_RW_RSV0_msc_rw_rsv0(unsigned int umsc_rw_rsv0); +int iSetMSC_RW_RSV1_msc_rw_rsv1(unsigned int umsc_rw_rsv1); +int iSetMSC_RW_RSV2_msc_rw_rsv2(unsigned int umsc_rw_rsv2); +int iSetMSC_RW_RSV3_msc_rw_rsv3(unsigned int umsc_rw_rsv3); +int iSetMSC_INDRECT_CTRL_msc_indrect_addr(unsigned int umsc_indrect_addr); +int iSetMSC_INDRECT_CTRL_msc_indrect_tab(unsigned int umsc_indrect_tab); +int iSetMSC_INDRECT_CTRL_msc_indrect_stat(unsigned int umsc_indrect_stat); +int iSetMSC_INDRECT_CTRL_msc_indrect_mode(unsigned int umsc_indrect_mode); +int iSetMSC_INDRECT_CTRL_msc_indrect_vld(unsigned int umsc_indrect_vld); +int iSetMSC_INDRECT_TIMEOUT_msc_indrect_timeout(unsigned int umsc_indrect_timeout); +int iSetMSC_INDRECT_DATA_0_msc_indrect_data_0(unsigned int umsc_indrect_data_0); +int iSetMSC_INDRECT_DATA_1_msc_indrect_data_1(unsigned int umsc_indrect_data_1); +int iSetMSC_MEM_ECC_BYPASS_EN_msc_mem_ecc_bypass(unsigned int umsc_mem_ecc_bypass); +int iSetMSC_MEM_CTRL_BUS_CFG0_msc_mem_ctrl_bus_0(unsigned int umsc_mem_ctrl_bus_0); +int iSetMSC_MEM_CTRL_BUS_CFG1_msc_mem_ctrl_bus_1(unsigned int umsc_mem_ctrl_bus_1); +int iSetMSC_MEM_CTRL_BUS_CFG2_msc_mem_ctrl_bus_2(unsigned int umsc_mem_ctrl_bus_2); +int iSetMSC_MEM_CTRL_BUS_CFG3_msc_mem_ctrl_bus_3(unsigned int umsc_mem_ctrl_bus_3); +int iSetMSC_MEM_CTRL_BUS_CFG4_msc_mem_ctrl_bus_4(unsigned int umsc_mem_ctrl_bus_4); +int iSetMSC_INT_VECTOR_msc_cpi_int_index(unsigned int umsc_cpi_int_index); +int iSetMSC_INT_VECTOR_msc_enable(unsigned int umsc_enable); +int iSetMSC_INT_VECTOR_msc_int_issue(unsigned int umsc_int_issue); +int iSetMSC_INT_msc_int_data(unsigned int umsc_int_data); +int iSetMSC_INT_msc_program_csr_id_ro(unsigned int umsc_program_csr_id_ro); +int iSetMSC_INT_EN_msc_int_en(unsigned int umsc_int_en); +int iSetMSC_INT_EN_msc_program_csr_id(unsigned int umsc_program_csr_id); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_0(unsigned int umsc_mem_err_req_0); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_1(unsigned int umsc_mem_err_req_1); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_2(unsigned int umsc_mem_err_req_2); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_3(unsigned int umsc_mem_err_req_3); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_4(unsigned int umsc_mem_err_req_4); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_5(unsigned int umsc_mem_err_req_5); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_6(unsigned int umsc_mem_err_req_6); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_7(unsigned int umsc_mem_err_req_7); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_8(unsigned int umsc_mem_err_req_8); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_9(unsigned int umsc_mem_err_req_9); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_10(unsigned int umsc_mem_err_req_10); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_11(unsigned int umsc_mem_err_req_11); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_12(unsigned int umsc_mem_err_req_12); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_13(unsigned int umsc_mem_err_req_13); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_14(unsigned int umsc_mem_err_req_14); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_15(unsigned int umsc_mem_err_req_15); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_16(unsigned int umsc_mem_err_req_16); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_17(unsigned int umsc_mem_err_req_17); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_18(unsigned int umsc_mem_err_req_18); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_19(unsigned int umsc_mem_err_req_19); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_20(unsigned int umsc_mem_err_req_20); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_21(unsigned int umsc_mem_err_req_21); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_22(unsigned int umsc_mem_err_req_22); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_23(unsigned int umsc_mem_err_req_23); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_24(unsigned int umsc_mem_err_req_24); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_25(unsigned int umsc_mem_err_req_25); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_26(unsigned int umsc_mem_err_req_26); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_27(unsigned int umsc_mem_err_req_27); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_28(unsigned int umsc_mem_err_req_28); +int iSetMSC_MEM_ERR_REQ0_msc_mem_err_req_29(unsigned int umsc_mem_err_req_29); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_32(unsigned int umsc_mem_err_req_32); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_33(unsigned int umsc_mem_err_req_33); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_34(unsigned int umsc_mem_err_req_34); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_35(unsigned int umsc_mem_err_req_35); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_36(unsigned int umsc_mem_err_req_36); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_37(unsigned int umsc_mem_err_req_37); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_38(unsigned int umsc_mem_err_req_38); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_39(unsigned int umsc_mem_err_req_39); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_40(unsigned int umsc_mem_err_req_40); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_41(unsigned int umsc_mem_err_req_41); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_42(unsigned int umsc_mem_err_req_42); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_43(unsigned int umsc_mem_err_req_43); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_44(unsigned int umsc_mem_err_req_44); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_45(unsigned int umsc_mem_err_req_45); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_46(unsigned int umsc_mem_err_req_46); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_47(unsigned int umsc_mem_err_req_47); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_48(unsigned int umsc_mem_err_req_48); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_49(unsigned int umsc_mem_err_req_49); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_50(unsigned int umsc_mem_err_req_50); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_51(unsigned int umsc_mem_err_req_51); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_52(unsigned int umsc_mem_err_req_52); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_53(unsigned int umsc_mem_err_req_53); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_54(unsigned int umsc_mem_err_req_54); +int iSetMSC_MEM_ERR_REQ1_msc_mem_err_req_55(unsigned int umsc_mem_err_req_55); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_64(unsigned int umsc_mem_err_req_64); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_65(unsigned int umsc_mem_err_req_65); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_66(unsigned int umsc_mem_err_req_66); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_67(unsigned int umsc_mem_err_req_67); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_68(unsigned int umsc_mem_err_req_68); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_69(unsigned int umsc_mem_err_req_69); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_70(unsigned int umsc_mem_err_req_70); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_71(unsigned int umsc_mem_err_req_71); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_72(unsigned int umsc_mem_err_req_72); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_73(unsigned int umsc_mem_err_req_73); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_74(unsigned int umsc_mem_err_req_74); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_75(unsigned int umsc_mem_err_req_75); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_76(unsigned int umsc_mem_err_req_76); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_77(unsigned int umsc_mem_err_req_77); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_78(unsigned int umsc_mem_err_req_78); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_79(unsigned int umsc_mem_err_req_79); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_80(unsigned int umsc_mem_err_req_80); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_81(unsigned int umsc_mem_err_req_81); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_82(unsigned int umsc_mem_err_req_82); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_83(unsigned int umsc_mem_err_req_83); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_84(unsigned int umsc_mem_err_req_84); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_85(unsigned int umsc_mem_err_req_85); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_86(unsigned int umsc_mem_err_req_86); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_87(unsigned int umsc_mem_err_req_87); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_88(unsigned int umsc_mem_err_req_88); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_89(unsigned int umsc_mem_err_req_89); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_90(unsigned int umsc_mem_err_req_90); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_91(unsigned int umsc_mem_err_req_91); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_92(unsigned int umsc_mem_err_req_92); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_93(unsigned int umsc_mem_err_req_93); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_94(unsigned int umsc_mem_err_req_94); +int iSetMSC_MEM_ERR_REQ2_msc_mem_err_req_95(unsigned int umsc_mem_err_req_95); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_96(unsigned int umsc_mem_err_req_96); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_97(unsigned int umsc_mem_err_req_97); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_98(unsigned int umsc_mem_err_req_98); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_99(unsigned int umsc_mem_err_req_99); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_100(unsigned int umsc_mem_err_req_100); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_101(unsigned int umsc_mem_err_req_101); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_102(unsigned int umsc_mem_err_req_102); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_103(unsigned int umsc_mem_err_req_103); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_104(unsigned int umsc_mem_err_req_104); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_105(unsigned int umsc_mem_err_req_105); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_106(unsigned int umsc_mem_err_req_106); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_107(unsigned int umsc_mem_err_req_107); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_108(unsigned int umsc_mem_err_req_108); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_109(unsigned int umsc_mem_err_req_109); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_110(unsigned int umsc_mem_err_req_110); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_111(unsigned int umsc_mem_err_req_111); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_112(unsigned int umsc_mem_err_req_112); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_113(unsigned int umsc_mem_err_req_113); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_114(unsigned int umsc_mem_err_req_114); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_115(unsigned int umsc_mem_err_req_115); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_116(unsigned int umsc_mem_err_req_116); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_117(unsigned int umsc_mem_err_req_117); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_118(unsigned int umsc_mem_err_req_118); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_119(unsigned int umsc_mem_err_req_119); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_120(unsigned int umsc_mem_err_req_120); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_121(unsigned int umsc_mem_err_req_121); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_122(unsigned int umsc_mem_err_req_122); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_123(unsigned int umsc_mem_err_req_123); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_124(unsigned int umsc_mem_err_req_124); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_125(unsigned int umsc_mem_err_req_125); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_126(unsigned int umsc_mem_err_req_126); +int iSetMSC_MEM_ERR_REQ3_msc_mem_err_req_127(unsigned int umsc_mem_err_req_127); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_128(unsigned int umsc_mem_err_req_128); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_129(unsigned int umsc_mem_err_req_129); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_130(unsigned int umsc_mem_err_req_130); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_131(unsigned int umsc_mem_err_req_131); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_132(unsigned int umsc_mem_err_req_132); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_133(unsigned int umsc_mem_err_req_133); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_134(unsigned int umsc_mem_err_req_134); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_135(unsigned int umsc_mem_err_req_135); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_136(unsigned int umsc_mem_err_req_136); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_137(unsigned int umsc_mem_err_req_137); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_138(unsigned int umsc_mem_err_req_138); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_139(unsigned int umsc_mem_err_req_139); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_140(unsigned int umsc_mem_err_req_140); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_141(unsigned int umsc_mem_err_req_141); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_142(unsigned int umsc_mem_err_req_142); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_143(unsigned int umsc_mem_err_req_143); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_144(unsigned int umsc_mem_err_req_144); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_145(unsigned int umsc_mem_err_req_145); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_146(unsigned int umsc_mem_err_req_146); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_147(unsigned int umsc_mem_err_req_147); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_148(unsigned int umsc_mem_err_req_148); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_149(unsigned int umsc_mem_err_req_149); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_150(unsigned int umsc_mem_err_req_150); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_151(unsigned int umsc_mem_err_req_151); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_152(unsigned int umsc_mem_err_req_152); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_153(unsigned int umsc_mem_err_req_153); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_154(unsigned int umsc_mem_err_req_154); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_155(unsigned int umsc_mem_err_req_155); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_156(unsigned int umsc_mem_err_req_156); +int iSetMSC_MEM_ERR_REQ4_msc_mem_err_req_157(unsigned int umsc_mem_err_req_157); +int iSetMSC_ECC_ONE_BIT_INT_msc_ecc_1bit_err(unsigned int umsc_ecc_1bit_err); +int iSetMSC_ECC_ONE_BIT_INT_msc_ecc_1bit_err_insrt(unsigned int umsc_ecc_1bit_err_insrt); +int iSetMSC_ECC_ONE_BIT_INT_msc_ecc_1bit_err_info(unsigned int umsc_ecc_1bit_err_info); +int iSetMSC_ECC_TWO_BIT_INT_msc_ecc_2bit_err(unsigned int umsc_ecc_2bit_err); +int iSetMSC_ECC_TWO_BIT_INT_msc_ecc_2bit_err_insrt(unsigned int umsc_ecc_2bit_err_insrt); +int iSetMSC_ECC_TWO_BIT_INT_msc_ecc_2bit_err_info(unsigned int umsc_ecc_2bit_err_info); +int iSetMSC_MQ_BIND_INT_msc_bind_cfg_err(unsigned int umsc_bind_cfg_err); +int iSetMSC_MQ_BIND_INT_msc_bind_cfg_err_insrt(unsigned int umsc_bind_cfg_err_insrt); +int iSetMSC_MQ_BIND_INT_msc_bind_cfg_err_info(unsigned int umsc_bind_cfg_err_info); +int iSetMSC_VNIC_SPCNT_INF_INT_msc_vf_sp_cnt_inf_err(unsigned int umsc_vf_sp_cnt_inf_err); +int iSetMSC_VNIC_SPCNT_INF_INT_msc_vf_sp_cnt_inf_err_insrt(unsigned int umsc_vf_sp_cnt_inf_err_insrt); +int iSetMSC_VNIC_SPCNT_INF_INT_msc_vf_sp_cnt_inf_err_info(unsigned int umsc_vf_sp_cnt_inf_err_info); +int iSetMSC_VNIC_SPCNT_CAL_INT_msc_vf_sp_cnt_cal_err(unsigned int umsc_vf_sp_cnt_cal_err); +int iSetMSC_VNIC_SPCNT_CAL_INT_msc_vf_sp_cnt_cal_err_insrt(unsigned int umsc_vf_sp_cnt_cal_err_insrt); +int iSetMSC_VNIC_SPCNT_CAL_INT_msc_vf_sp_cnt_cal_err_info(unsigned int umsc_vf_sp_cnt_cal_err_info); +int iSetMSC_SOCEP_SPCNT_INF_INT_msc_socep_sp_cnt_inf_err(unsigned int umsc_socep_sp_cnt_inf_err); +int iSetMSC_SOCEP_SPCNT_INF_INT_msc_socep_sp_cnt_inf_err_insrt(unsigned int umsc_socep_sp_cnt_inf_err_insrt); +int iSetMSC_SOCEP_SPCNT_INF_INT_msc_socep_sp_cnt_inf_err_info(unsigned int umsc_socep_sp_cnt_inf_err_info); +int iSetMSC_SOCEP_SPCNT_CAL_INT_msc_socep_sp_cnt_cal_err(unsigned int umsc_socep_sp_cnt_cal_err); +int iSetMSC_SOCEP_SPCNT_CAL_INT_msc_socep_sp_cnt_cal_err_insrt(unsigned int umsc_socep_sp_cnt_cal_err_insrt); +int iSetMSC_SOCEP_SPCNT_CAL_INT_msc_socep_sp_cnt_cal_err_info(unsigned int umsc_socep_sp_cnt_cal_err_info); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err0(unsigned int umsc_fifo_int0_err0); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err0_insrt(unsigned int umsc_fifo_int0_err0_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err1(unsigned int umsc_fifo_int0_err1); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err1_insrt(unsigned int umsc_fifo_int0_err1_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err2(unsigned int umsc_fifo_int0_err2); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err2_insrt(unsigned int umsc_fifo_int0_err2_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err3(unsigned int umsc_fifo_int0_err3); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err3_insrt(unsigned int umsc_fifo_int0_err3_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err4(unsigned int umsc_fifo_int0_err4); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err4_insrt(unsigned int umsc_fifo_int0_err4_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err5(unsigned int umsc_fifo_int0_err5); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err5_insrt(unsigned int umsc_fifo_int0_err5_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err6(unsigned int umsc_fifo_int0_err6); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err6_insrt(unsigned int umsc_fifo_int0_err6_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err7(unsigned int umsc_fifo_int0_err7); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err7_insrt(unsigned int umsc_fifo_int0_err7_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err8(unsigned int umsc_fifo_int0_err8); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err8_insrt(unsigned int umsc_fifo_int0_err8_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err9(unsigned int umsc_fifo_int0_err9); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err9_insrt(unsigned int umsc_fifo_int0_err9_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err10(unsigned int umsc_fifo_int0_err10); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err10_insrt(unsigned int umsc_fifo_int0_err10_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err11(unsigned int umsc_fifo_int0_err11); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err11_insrt(unsigned int umsc_fifo_int0_err11_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err12(unsigned int umsc_fifo_int0_err12); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err12_insrt(unsigned int umsc_fifo_int0_err12_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err13(unsigned int umsc_fifo_int0_err13); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err13_insrt(unsigned int umsc_fifo_int0_err13_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err14(unsigned int umsc_fifo_int0_err14); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err14_insrt(unsigned int umsc_fifo_int0_err14_insrt); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err15(unsigned int umsc_fifo_int0_err15); +int iSetMSC_FIFO_INT0_msc_fifo_int0_err15_insrt(unsigned int umsc_fifo_int0_err15_insrt); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err0_en(unsigned int umsc_fifo_int0_err0_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err1_en(unsigned int umsc_fifo_int0_err1_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err2_en(unsigned int umsc_fifo_int0_err2_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err3_en(unsigned int umsc_fifo_int0_err3_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err4_en(unsigned int umsc_fifo_int0_err4_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err5_en(unsigned int umsc_fifo_int0_err5_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err6_en(unsigned int umsc_fifo_int0_err6_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err7_en(unsigned int umsc_fifo_int0_err7_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err8_en(unsigned int umsc_fifo_int0_err8_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err9_en(unsigned int umsc_fifo_int0_err9_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err10_en(unsigned int umsc_fifo_int0_err10_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err11_en(unsigned int umsc_fifo_int0_err11_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err12_en(unsigned int umsc_fifo_int0_err12_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err13_en(unsigned int umsc_fifo_int0_err13_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err14_en(unsigned int umsc_fifo_int0_err14_en); +int iSetMSC_FIFO_INT0_MASK_msc_fifo_int0_err15_en(unsigned int umsc_fifo_int0_err15_en); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err0(unsigned int umsc_fifo_int1_err0); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err0_insrt(unsigned int umsc_fifo_int1_err0_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err1(unsigned int umsc_fifo_int1_err1); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err1_insrt(unsigned int umsc_fifo_int1_err1_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err2(unsigned int umsc_fifo_int1_err2); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err2_insrt(unsigned int umsc_fifo_int1_err2_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err3(unsigned int umsc_fifo_int1_err3); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err3_insrt(unsigned int umsc_fifo_int1_err3_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err4(unsigned int umsc_fifo_int1_err4); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err4_insrt(unsigned int umsc_fifo_int1_err4_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err5(unsigned int umsc_fifo_int1_err5); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err5_insrt(unsigned int umsc_fifo_int1_err5_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err6(unsigned int umsc_fifo_int1_err6); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err6_insrt(unsigned int umsc_fifo_int1_err6_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err7(unsigned int umsc_fifo_int1_err7); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err7_insrt(unsigned int umsc_fifo_int1_err7_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err8(unsigned int umsc_fifo_int1_err8); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err8_insrt(unsigned int umsc_fifo_int1_err8_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err9(unsigned int umsc_fifo_int1_err9); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err9_insrt(unsigned int umsc_fifo_int1_err9_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err10(unsigned int umsc_fifo_int1_err10); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err10_insrt(unsigned int umsc_fifo_int1_err10_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err11(unsigned int umsc_fifo_int1_err11); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err11_insrt(unsigned int umsc_fifo_int1_err11_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err12(unsigned int umsc_fifo_int1_err12); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err12_insrt(unsigned int umsc_fifo_int1_err12_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err13(unsigned int umsc_fifo_int1_err13); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err13_insrt(unsigned int umsc_fifo_int1_err13_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err14(unsigned int umsc_fifo_int1_err14); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err14_insrt(unsigned int umsc_fifo_int1_err14_insrt); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err15(unsigned int umsc_fifo_int1_err15); +int iSetMSC_FIFO_INT1_msc_fifo_int1_err15_insrt(unsigned int umsc_fifo_int1_err15_insrt); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err0_en(unsigned int umsc_fifo_int1_err0_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err1_en(unsigned int umsc_fifo_int1_err1_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err2_en(unsigned int umsc_fifo_int1_err2_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err3_en(unsigned int umsc_fifo_int1_err3_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err4_en(unsigned int umsc_fifo_int1_err4_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err5_en(unsigned int umsc_fifo_int1_err5_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err6_en(unsigned int umsc_fifo_int1_err6_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err7_en(unsigned int umsc_fifo_int1_err7_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err8_en(unsigned int umsc_fifo_int1_err8_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err9_en(unsigned int umsc_fifo_int1_err9_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err10_en(unsigned int umsc_fifo_int1_err10_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err11_en(unsigned int umsc_fifo_int1_err11_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err12_en(unsigned int umsc_fifo_int1_err12_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err13_en(unsigned int umsc_fifo_int1_err13_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err14_en(unsigned int umsc_fifo_int1_err14_en); +int iSetMSC_FIFO_INT1_MASK_msc_fifo_int1_err15_en(unsigned int umsc_fifo_int1_err15_en); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err0(unsigned int umsc_fifo_int2_err0); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err0_insrt(unsigned int umsc_fifo_int2_err0_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err1(unsigned int umsc_fifo_int2_err1); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err1_insrt(unsigned int umsc_fifo_int2_err1_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err2(unsigned int umsc_fifo_int2_err2); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err2_insrt(unsigned int umsc_fifo_int2_err2_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err3(unsigned int umsc_fifo_int2_err3); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err3_insrt(unsigned int umsc_fifo_int2_err3_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err4(unsigned int umsc_fifo_int2_err4); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err4_insrt(unsigned int umsc_fifo_int2_err4_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err5(unsigned int umsc_fifo_int2_err5); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err5_insrt(unsigned int umsc_fifo_int2_err5_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err6(unsigned int umsc_fifo_int2_err6); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err6_insrt(unsigned int umsc_fifo_int2_err6_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err7(unsigned int umsc_fifo_int2_err7); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err7_insrt(unsigned int umsc_fifo_int2_err7_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err8(unsigned int umsc_fifo_int2_err8); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err8_insrt(unsigned int umsc_fifo_int2_err8_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err9(unsigned int umsc_fifo_int2_err9); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err9_insrt(unsigned int umsc_fifo_int2_err9_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err10(unsigned int umsc_fifo_int2_err10); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err10_insrt(unsigned int umsc_fifo_int2_err10_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err11(unsigned int umsc_fifo_int2_err11); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err11_insrt(unsigned int umsc_fifo_int2_err11_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err12(unsigned int umsc_fifo_int2_err12); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err12_insrt(unsigned int umsc_fifo_int2_err12_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err13(unsigned int umsc_fifo_int2_err13); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err13_insrt(unsigned int umsc_fifo_int2_err13_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err14(unsigned int umsc_fifo_int2_err14); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err14_insrt(unsigned int umsc_fifo_int2_err14_insrt); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err15(unsigned int umsc_fifo_int2_err15); +int iSetMSC_FIFO_INT2_msc_fifo_int2_err15_insrt(unsigned int umsc_fifo_int2_err15_insrt); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err0_en(unsigned int umsc_fifo_int2_err0_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err1_en(unsigned int umsc_fifo_int2_err1_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err2_en(unsigned int umsc_fifo_int2_err2_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err3_en(unsigned int umsc_fifo_int2_err3_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err4_en(unsigned int umsc_fifo_int2_err4_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err5_en(unsigned int umsc_fifo_int2_err5_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err6_en(unsigned int umsc_fifo_int2_err6_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err7_en(unsigned int umsc_fifo_int2_err7_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err8_en(unsigned int umsc_fifo_int2_err8_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err9_en(unsigned int umsc_fifo_int2_err9_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err10_en(unsigned int umsc_fifo_int2_err10_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err11_en(unsigned int umsc_fifo_int2_err11_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err12_en(unsigned int umsc_fifo_int2_err12_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err13_en(unsigned int umsc_fifo_int2_err13_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err14_en(unsigned int umsc_fifo_int2_err14_en); +int iSetMSC_FIFO_INT2_MASK_msc_fifo_int2_err15_en(unsigned int umsc_fifo_int2_err15_en); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err0(unsigned int umsc_fifo_int3_err0); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err0_insrt(unsigned int umsc_fifo_int3_err0_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err1(unsigned int umsc_fifo_int3_err1); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err1_insrt(unsigned int umsc_fifo_int3_err1_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err2(unsigned int umsc_fifo_int3_err2); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err2_insrt(unsigned int umsc_fifo_int3_err2_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err3(unsigned int umsc_fifo_int3_err3); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err3_insrt(unsigned int umsc_fifo_int3_err3_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err4(unsigned int umsc_fifo_int3_err4); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err4_insrt(unsigned int umsc_fifo_int3_err4_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err5(unsigned int umsc_fifo_int3_err5); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err5_insrt(unsigned int umsc_fifo_int3_err5_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err6(unsigned int umsc_fifo_int3_err6); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err6_insrt(unsigned int umsc_fifo_int3_err6_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err7(unsigned int umsc_fifo_int3_err7); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err7_insrt(unsigned int umsc_fifo_int3_err7_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err8(unsigned int umsc_fifo_int3_err8); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err8_insrt(unsigned int umsc_fifo_int3_err8_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err9(unsigned int umsc_fifo_int3_err9); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err9_insrt(unsigned int umsc_fifo_int3_err9_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err10(unsigned int umsc_fifo_int3_err10); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err10_insrt(unsigned int umsc_fifo_int3_err10_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err11(unsigned int umsc_fifo_int3_err11); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err11_insrt(unsigned int umsc_fifo_int3_err11_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err12(unsigned int umsc_fifo_int3_err12); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err12_insrt(unsigned int umsc_fifo_int3_err12_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err13(unsigned int umsc_fifo_int3_err13); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err13_insrt(unsigned int umsc_fifo_int3_err13_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err14(unsigned int umsc_fifo_int3_err14); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err14_insrt(unsigned int umsc_fifo_int3_err14_insrt); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err15(unsigned int umsc_fifo_int3_err15); +int iSetMSC_FIFO_INT3_msc_fifo_int3_err15_insrt(unsigned int umsc_fifo_int3_err15_insrt); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err0_en(unsigned int umsc_fifo_int3_err0_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err1_en(unsigned int umsc_fifo_int3_err1_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err2_en(unsigned int umsc_fifo_int3_err2_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err3_en(unsigned int umsc_fifo_int3_err3_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err4_en(unsigned int umsc_fifo_int3_err4_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err5_en(unsigned int umsc_fifo_int3_err5_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err6_en(unsigned int umsc_fifo_int3_err6_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err7_en(unsigned int umsc_fifo_int3_err7_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err8_en(unsigned int umsc_fifo_int3_err8_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err9_en(unsigned int umsc_fifo_int3_err9_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err10_en(unsigned int umsc_fifo_int3_err10_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err11_en(unsigned int umsc_fifo_int3_err11_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err12_en(unsigned int umsc_fifo_int3_err12_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err13_en(unsigned int umsc_fifo_int3_err13_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err14_en(unsigned int umsc_fifo_int3_err14_en); +int iSetMSC_FIFO_INT3_MASK_msc_fifo_int3_err15_en(unsigned int umsc_fifo_int3_err15_en); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err0(unsigned int umsc_fifo_int4_err0); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err0_insrt(unsigned int umsc_fifo_int4_err0_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err1(unsigned int umsc_fifo_int4_err1); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err1_insrt(unsigned int umsc_fifo_int4_err1_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err2(unsigned int umsc_fifo_int4_err2); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err2_insrt(unsigned int umsc_fifo_int4_err2_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err3(unsigned int umsc_fifo_int4_err3); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err3_insrt(unsigned int umsc_fifo_int4_err3_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err4(unsigned int umsc_fifo_int4_err4); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err4_insrt(unsigned int umsc_fifo_int4_err4_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err5(unsigned int umsc_fifo_int4_err5); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err5_insrt(unsigned int umsc_fifo_int4_err5_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err6(unsigned int umsc_fifo_int4_err6); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err6_insrt(unsigned int umsc_fifo_int4_err6_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err7(unsigned int umsc_fifo_int4_err7); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err7_insrt(unsigned int umsc_fifo_int4_err7_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err8(unsigned int umsc_fifo_int4_err8); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err8_insrt(unsigned int umsc_fifo_int4_err8_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err9(unsigned int umsc_fifo_int4_err9); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err9_insrt(unsigned int umsc_fifo_int4_err9_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err10(unsigned int umsc_fifo_int4_err10); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err10_insrt(unsigned int umsc_fifo_int4_err10_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err11(unsigned int umsc_fifo_int4_err11); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err11_insrt(unsigned int umsc_fifo_int4_err11_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err12(unsigned int umsc_fifo_int4_err12); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err12_insrt(unsigned int umsc_fifo_int4_err12_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err13(unsigned int umsc_fifo_int4_err13); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err13_insrt(unsigned int umsc_fifo_int4_err13_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err14(unsigned int umsc_fifo_int4_err14); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err14_insrt(unsigned int umsc_fifo_int4_err14_insrt); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err15(unsigned int umsc_fifo_int4_err15); +int iSetMSC_FIFO_INT4_msc_fifo_int4_err15_insrt(unsigned int umsc_fifo_int4_err15_insrt); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err0_en(unsigned int umsc_fifo_int4_err0_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err1_en(unsigned int umsc_fifo_int4_err1_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err2_en(unsigned int umsc_fifo_int4_err2_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err3_en(unsigned int umsc_fifo_int4_err3_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err4_en(unsigned int umsc_fifo_int4_err4_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err5_en(unsigned int umsc_fifo_int4_err5_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err6_en(unsigned int umsc_fifo_int4_err6_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err7_en(unsigned int umsc_fifo_int4_err7_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err8_en(unsigned int umsc_fifo_int4_err8_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err9_en(unsigned int umsc_fifo_int4_err9_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err10_en(unsigned int umsc_fifo_int4_err10_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err11_en(unsigned int umsc_fifo_int4_err11_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err12_en(unsigned int umsc_fifo_int4_err12_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err13_en(unsigned int umsc_fifo_int4_err13_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err14_en(unsigned int umsc_fifo_int4_err14_en); +int iSetMSC_FIFO_INT4_MASK_msc_fifo_int4_err15_en(unsigned int umsc_fifo_int4_err15_en); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err0(unsigned int umsc_fifo_int5_err0); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err0_insrt(unsigned int umsc_fifo_int5_err0_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err1(unsigned int umsc_fifo_int5_err1); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err1_insrt(unsigned int umsc_fifo_int5_err1_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err2(unsigned int umsc_fifo_int5_err2); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err2_insrt(unsigned int umsc_fifo_int5_err2_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err3(unsigned int umsc_fifo_int5_err3); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err3_insrt(unsigned int umsc_fifo_int5_err3_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err4(unsigned int umsc_fifo_int5_err4); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err4_insrt(unsigned int umsc_fifo_int5_err4_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err5(unsigned int umsc_fifo_int5_err5); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err5_insrt(unsigned int umsc_fifo_int5_err5_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err6(unsigned int umsc_fifo_int5_err6); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err6_insrt(unsigned int umsc_fifo_int5_err6_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err7(unsigned int umsc_fifo_int5_err7); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err7_insrt(unsigned int umsc_fifo_int5_err7_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err8(unsigned int umsc_fifo_int5_err8); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err8_insrt(unsigned int umsc_fifo_int5_err8_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err9(unsigned int umsc_fifo_int5_err9); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err9_insrt(unsigned int umsc_fifo_int5_err9_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err10(unsigned int umsc_fifo_int5_err10); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err10_insrt(unsigned int umsc_fifo_int5_err10_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err11(unsigned int umsc_fifo_int5_err11); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err11_insrt(unsigned int umsc_fifo_int5_err11_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err12(unsigned int umsc_fifo_int5_err12); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err12_insrt(unsigned int umsc_fifo_int5_err12_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err13(unsigned int umsc_fifo_int5_err13); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err13_insrt(unsigned int umsc_fifo_int5_err13_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err14(unsigned int umsc_fifo_int5_err14); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err14_insrt(unsigned int umsc_fifo_int5_err14_insrt); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err15(unsigned int umsc_fifo_int5_err15); +int iSetMSC_FIFO_INT5_msc_fifo_int5_err15_insrt(unsigned int umsc_fifo_int5_err15_insrt); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err0_en(unsigned int umsc_fifo_int5_err0_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err1_en(unsigned int umsc_fifo_int5_err1_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err2_en(unsigned int umsc_fifo_int5_err2_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err3_en(unsigned int umsc_fifo_int5_err3_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err4_en(unsigned int umsc_fifo_int5_err4_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err5_en(unsigned int umsc_fifo_int5_err5_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err6_en(unsigned int umsc_fifo_int5_err6_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err7_en(unsigned int umsc_fifo_int5_err7_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err8_en(unsigned int umsc_fifo_int5_err8_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err9_en(unsigned int umsc_fifo_int5_err9_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err10_en(unsigned int umsc_fifo_int5_err10_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err11_en(unsigned int umsc_fifo_int5_err11_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err12_en(unsigned int umsc_fifo_int5_err12_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err13_en(unsigned int umsc_fifo_int5_err13_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err14_en(unsigned int umsc_fifo_int5_err14_en); +int iSetMSC_FIFO_INT5_MASK_msc_fifo_int5_err15_en(unsigned int umsc_fifo_int5_err15_en); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err0(unsigned int umsc_fifo_int6_err0); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err0_insrt(unsigned int umsc_fifo_int6_err0_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err1(unsigned int umsc_fifo_int6_err1); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err1_insrt(unsigned int umsc_fifo_int6_err1_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err2(unsigned int umsc_fifo_int6_err2); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err2_insrt(unsigned int umsc_fifo_int6_err2_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err3(unsigned int umsc_fifo_int6_err3); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err3_insrt(unsigned int umsc_fifo_int6_err3_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err4(unsigned int umsc_fifo_int6_err4); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err4_insrt(unsigned int umsc_fifo_int6_err4_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err5(unsigned int umsc_fifo_int6_err5); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err5_insrt(unsigned int umsc_fifo_int6_err5_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err6(unsigned int umsc_fifo_int6_err6); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err6_insrt(unsigned int umsc_fifo_int6_err6_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err7(unsigned int umsc_fifo_int6_err7); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err7_insrt(unsigned int umsc_fifo_int6_err7_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err8(unsigned int umsc_fifo_int6_err8); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err8_insrt(unsigned int umsc_fifo_int6_err8_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err9(unsigned int umsc_fifo_int6_err9); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err9_insrt(unsigned int umsc_fifo_int6_err9_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err10(unsigned int umsc_fifo_int6_err10); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err10_insrt(unsigned int umsc_fifo_int6_err10_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err11(unsigned int umsc_fifo_int6_err11); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err11_insrt(unsigned int umsc_fifo_int6_err11_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err12(unsigned int umsc_fifo_int6_err12); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err12_insrt(unsigned int umsc_fifo_int6_err12_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err13(unsigned int umsc_fifo_int6_err13); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err13_insrt(unsigned int umsc_fifo_int6_err13_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err14(unsigned int umsc_fifo_int6_err14); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err14_insrt(unsigned int umsc_fifo_int6_err14_insrt); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err15(unsigned int umsc_fifo_int6_err15); +int iSetMSC_FIFO_INT6_msc_fifo_int6_err15_insrt(unsigned int umsc_fifo_int6_err15_insrt); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err0_en(unsigned int umsc_fifo_int6_err0_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err1_en(unsigned int umsc_fifo_int6_err1_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err2_en(unsigned int umsc_fifo_int6_err2_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err3_en(unsigned int umsc_fifo_int6_err3_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err4_en(unsigned int umsc_fifo_int6_err4_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err5_en(unsigned int umsc_fifo_int6_err5_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err6_en(unsigned int umsc_fifo_int6_err6_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err7_en(unsigned int umsc_fifo_int6_err7_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err8_en(unsigned int umsc_fifo_int6_err8_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err9_en(unsigned int umsc_fifo_int6_err9_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err10_en(unsigned int umsc_fifo_int6_err10_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err11_en(unsigned int umsc_fifo_int6_err11_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err12_en(unsigned int umsc_fifo_int6_err12_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err13_en(unsigned int umsc_fifo_int6_err13_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err14_en(unsigned int umsc_fifo_int6_err14_en); +int iSetMSC_FIFO_INT6_MASK_msc_fifo_int6_err15_en(unsigned int umsc_fifo_int6_err15_en); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err0(unsigned int umsc_fifo_int7_err0); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err0_insrt(unsigned int umsc_fifo_int7_err0_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err1(unsigned int umsc_fifo_int7_err1); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err1_insrt(unsigned int umsc_fifo_int7_err1_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err2(unsigned int umsc_fifo_int7_err2); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err2_insrt(unsigned int umsc_fifo_int7_err2_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err3(unsigned int umsc_fifo_int7_err3); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err3_insrt(unsigned int umsc_fifo_int7_err3_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err4(unsigned int umsc_fifo_int7_err4); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err4_insrt(unsigned int umsc_fifo_int7_err4_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err5(unsigned int umsc_fifo_int7_err5); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err5_insrt(unsigned int umsc_fifo_int7_err5_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err6(unsigned int umsc_fifo_int7_err6); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err6_insrt(unsigned int umsc_fifo_int7_err6_insrt); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err7(unsigned int umsc_fifo_int7_err7); +int iSetMSC_FIFO_INT7_msc_fifo_int7_err7_insrt(unsigned int umsc_fifo_int7_err7_insrt); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err0_en(unsigned int umsc_fifo_int7_err0_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err1_en(unsigned int umsc_fifo_int7_err1_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err2_en(unsigned int umsc_fifo_int7_err2_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err3_en(unsigned int umsc_fifo_int7_err3_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err4_en(unsigned int umsc_fifo_int7_err4_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err5_en(unsigned int umsc_fifo_int7_err5_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err6_en(unsigned int umsc_fifo_int7_err6_en); +int iSetMSC_FIFO_INT7_MASK_msc_fifo_int7_err7_en(unsigned int umsc_fifo_int7_err7_en); +int iSetMSC_BP_DELAY_CNT_msc_bp_delay_cnt(unsigned int umsc_bp_delay_cnt); +int iSetMSC_VF_SP_CNT_EN_vf_sp_cnt_flag_en(unsigned int uvf_sp_cnt_flag_en); +int iSetMSC_VF_SP_CNT_EN_socep_sp_cnt_flag_en(unsigned int usocep_sp_cnt_flag_en); +int iSetPRESUB_PKTLEN_NS_STF_presub_pktlen_ns_stf(unsigned int upresub_pktlen_ns_stf); +int iSetPRESUB_PKTLEN_NS_STL_presub_pktlen_ns_stl(unsigned int upresub_pktlen_ns_stl); +int iSetCMQ_PRESUB_PKTLEN_CS_cmq_presub_pktlen_cs(unsigned int ucmq_presub_pktlen_cs); +int iSetNFMQ_PRESUB_PKTLEN_CS_nfmq_presub_pktlen_cs(unsigned int unfmq_presub_pktlen_cs); +int iSetPRESUB_PKTNUM_presub_pktnum_ns_stl(unsigned int upresub_pktnum_ns_stl); +int iSetPRESUB_PKTNUM_presub_pktnum_ns_stf(unsigned int upresub_pktnum_ns_stf); +int iSetPRESUB_PKTNUM_presub_pktnum_cs_cmq(unsigned int upresub_pktnum_cs_cmq); +int iSetPRESUB_PKTNUM_presub_pktnum_cs_nfmq(unsigned int upresub_pktnum_cs_nfmq); +int iSetPRESUB_PKTLEN_SOCNMQ_presub_pktlen_socnmq(unsigned int upresub_pktlen_socnmq); +int iSetPRESUB_PKTLEN_SOCCMQ_presub_pktlen_soccmq(unsigned int upresub_pktlen_soccmq); +int iSetPRESUB_PKTNUM_SOC_presub_pktnum_socnmq(unsigned int upresub_pktnum_socnmq); +int iSetPRESUB_PKTNUM_SOC_presub_pktnum_soccmq(unsigned int upresub_pktnum_soccmq); +int iSetMSC_PPS_SHAPER_CFG_PKTLEN_msc_pps_typical_pktlen_cfg(unsigned int umsc_pps_typical_pktlen_cfg); +int iSetMSC_ROOT_CRR_WEIGHT_CFG_msc_crr_weight_cfg_ns(unsigned int umsc_crr_weight_cfg_ns); +int iSetMSC_ROOT_CRR_WEIGHT_CFG_msc_crr_weight_cfg_cs(unsigned int umsc_crr_weight_cfg_cs); +int iSetSOCMSC_ROOT_SCH_WGT_CFG_socmsc_rt_sch_wgt_cfg(unsigned int usocmsc_rt_sch_wgt_cfg); +int iSetWEIGHT_NS_OFFSET_cos_weight_ns_offset(unsigned int ucos_weight_ns_offset); +int iSetWEIGHT_NS_OFFSET_ep_weight_ns_offset(unsigned int uep_weight_ns_offset); +int iSetWEIGHT_NS_OFFSET_host_weight_ns_offset(unsigned int uhost_weight_ns_offset); +int iSetWEIGHT_CS_OFFSET_nfmq_cos_weight_cs_offset(unsigned int unfmq_cos_weight_cs_offset); +int iSetWEIGHT_CS_OFFSET_cmq_cos_weight_cs_offset(unsigned int ucmq_cos_weight_cs_offset); +int iSetWEIGHT_CS_OFFSET_ep_weight_cs_offset(unsigned int uep_weight_cs_offset); +int iSetWEIGHT_CS_OFFSET_host_weight_cs_offset(unsigned int uhost_weight_cs_offset); +int iSetWEIGHT_MSCSOC_OFFSET_soc_mq_weight_offset(unsigned int usoc_mq_weight_offset); +int iSetWEIGHT_MSCSOC_OFFSET_soc_ep_weight_offset(unsigned int usoc_ep_weight_offset); +int iSetWEIGHT_MSCSOC_OFFSET_soc_serv_weight_offset(unsigned int usoc_serv_weight_offset); +int iSetHOST_WEIGHT_NS_host_weight_ns_0(unsigned int uhost_weight_ns_0); +int iSetHOST_WEIGHT_NS_host_weight_ns_1(unsigned int uhost_weight_ns_1); +int iSetHOST_WEIGHT_NS_host_weight_ns_2(unsigned int uhost_weight_ns_2); +int iSetHOST_WEIGHT_NS_host_weight_ns_3(unsigned int uhost_weight_ns_3); +int iSetHOST_WEIGHT_CS_host_weight_cs_0(unsigned int uhost_weight_cs_0); +int iSetHOST_WEIGHT_CS_host_weight_cs_1(unsigned int uhost_weight_cs_1); +int iSetHOST_WEIGHT_CS_host_weight_cs_2(unsigned int uhost_weight_cs_2); +int iSetHOST_WEIGHT_CS_host_weight_cs_3(unsigned int uhost_weight_cs_3); +int iSetQA_WEIGHT_CFG_CS_msc_qa_weight_cfg_cs(unsigned int umsc_qa_weight_cfg_cs); +int iSetEP_WEIGHT_CFG_NS_mscep_weight_cfg_ns(unsigned int umscep_weight_cfg_ns); +int iSetEP_WEIGHT_CFG_CMQ_mscep_weight_cfg_cmq(unsigned int umscep_weight_cfg_cmq); +int iSetEP_WEIGHT_CFG_NFMQ_mscep_weight_cfg_nfmq(unsigned int umscep_weight_cfg_nfmq); +int iSetSOC_MQ_WEIGHT_CFG_socmq_weight_cfg(unsigned int usocmq_weight_cfg); +int iSetSOC_EP_WEIGHT_CFG_socep_weight_cfg(unsigned int usocep_weight_cfg); +int iSetSOC_SERV_WEIGHT_CFG_socserv_weight_cfg(unsigned int usocserv_weight_cfg); +int iSetHOST_SHAP_BPS_CFG_CS_host_shap_bps_cfg_cs(unsigned int uhost_shap_bps_cfg_cs); +int iSetHOST_SHAP_PPS_CFG_CS_host_shap_pps_cfg_cs(unsigned int uhost_shap_pps_cfg_cs); +int iSetHOST_SHAP_BPS_CFG_NS_host_shap_bps_cfg_ns(unsigned int uhost_shap_bps_cfg_ns); +int iSetHOST_SHAP_PPS_CFG_NS_host_shap_pps_cfg_ns(unsigned int uhost_shap_pps_cfg_ns); +int iSetEP_SHAP_BPS_CFG_NS_ep_shap_bps_cfg_ns(unsigned int uep_shap_bps_cfg_ns); +int iSetEP_SHAP_PPS_CFG_NS_ep_shap_pps_cfg_ns(unsigned int uep_shap_pps_cfg_ns); +int iSetEP_SHAP_BPS_CFG_CMQ_ep_shap_bps_cfg_cmq(unsigned int uep_shap_bps_cfg_cmq); +int iSetEP_SHAP_PPS_CFG_CMQ_ep_shap_pps_cfg_cmq(unsigned int uep_shap_pps_cfg_cmq); +int iSetEP_SHAP_BPS_CFG_NFMQ_ep_shap_bps_cfg_nfmq(unsigned int uep_shap_bps_cfg_nfmq); +int iSetEP_SHAP_PPS_CFG_NFMQ_ep_shap_pps_cfg_nfmq(unsigned int uep_shap_pps_cfg_nfmq); +int iSetSOCMQ_SHAP_BPS_CFG_socmq_shap_bps_cfg(unsigned int usocmq_shap_bps_cfg); +int iSetSOCMQ_SHAP_PPS_CFG_socmq_shap_pps_cfg(unsigned int usocmq_shap_pps_cfg); +int iSetSOCEP_SHAP_BPS_CFG_socep_shap_bps_cfg(unsigned int usocep_shap_bps_cfg); +int iSetSOCEP_SHAP_PPS_CFG_socep_shap_pps_cfg(unsigned int usocep_shap_pps_cfg); +int iSetSOCSERV_SHAP_BPS_CFG_socserv_shap_bps_cfg(unsigned int usocserv_shap_bps_cfg); +int iSetSOCSERV_SHAP_PPS_CFG_socserv_shap_pps_cfg(unsigned int usocserv_shap_pps_cfg); +int iSetSOCRT_SHAP_BPS_CFG_socrt_shap_bps_cfg(unsigned int usocrt_shap_bps_cfg); +int iSetSOCRT_SHAP_PPS_CFG_socrt_shap_pps_cfg(unsigned int usocrt_shap_pps_cfg); +int iSetMSC_SHAP_BYPASS_CFG_msc_nmq_shap_byp_vld(unsigned int umsc_nmq_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_ns_vnic_shap_byp_vld(unsigned int umsc_ns_vnic_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_ns_vnicgrp_shap_byp_vld(unsigned int umsc_ns_vnicgrp_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_ns_ep_shap_byp_vld(unsigned int umsc_ns_ep_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_ns_host_shap_byp_vld(unsigned int umsc_ns_host_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_cmq_shap_byp_vld(unsigned int umsc_cmq_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_nfmq_vnic_shap_byp_vld(unsigned int umsc_nfmq_vnic_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_cs_ep_shap_byp_vld(unsigned int umsc_cs_ep_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_msc_cs_host_shap_byp_vld(unsigned int umsc_cs_host_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_socmsc_mq_shap_byp_vld(unsigned int usocmsc_mq_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_socmsc_ep_shap_byp_vld(unsigned int usocmsc_ep_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_socmsc_serv_shap_byp_vld(unsigned int usocmsc_serv_shap_byp_vld); +int iSetMSC_SHAP_BYPASS_CFG_socmsc_rt_shap_byp_vld(unsigned int usocmsc_rt_shap_byp_vld); +int iSetMSC_HOST_ROOT_XON_CFG_msc_host_xon_cfg_ns(unsigned int umsc_host_xon_cfg_ns); +int iSetMSC_HOST_ROOT_XON_CFG_msc_host_xon_cfg_cs(unsigned int umsc_host_xon_cfg_cs); +int iSetMSC_HOST_ROOT_XON_CFG_msc_root_xon_cfg_ns(unsigned int umsc_root_xon_cfg_ns); +int iSetMSC_HOST_ROOT_XON_CFG_msc_root_xon_cfg_cs(unsigned int umsc_root_xon_cfg_cs); +int iSetMSC_HOST_ROOT_XON_CFG_msc_root_xon_cfg(unsigned int umsc_root_xon_cfg); +int iSetMSC_SOC_ROOT_XON_CFG_socmsc_ep_xon_cfg_ns(unsigned int usocmsc_ep_xon_cfg_ns); +int iSetMSC_SOC_ROOT_XON_CFG_socmsc_ep_xon_cfg_cs(unsigned int usocmsc_ep_xon_cfg_cs); +int iSetMSC_SOC_ROOT_XON_CFG_socmsc_root_xon_cfg_ns(unsigned int usocmsc_root_xon_cfg_ns); +int iSetMSC_SOC_ROOT_XON_CFG_socmsc_root_xon_cfg_cs(unsigned int usocmsc_root_xon_cfg_cs); +int iSetMSC_SOC_ROOT_XON_CFG_socmsc_root_xon_cfg(unsigned int usocmsc_root_xon_cfg); +int iSetMSC_HOST_EP_XON_CFG_NS_msc_hostep_xon_cfg_ns(unsigned int umsc_hostep_xon_cfg_ns); +int iSetMSC_HOST_EP_XON_CFG_NFMQ_msc_hostep_xon_cfg_nfmq(unsigned int umsc_hostep_xon_cfg_nfmq); +int iSetMSC_HOST_EP_XON_CFG_CMQ_msc_hostep_xon_cfg_cmq(unsigned int umsc_hostep_xon_cfg_cmq); +int iSetSOCMSC_MQ_XON_CFG_NS_socmsc_mq_xon_cfg(unsigned int usocmsc_mq_xon_cfg); +int iSetMSC_PRM_PORT_BP_STA0_prm_mqm_dp_ep_bp(unsigned int uprm_mqm_dp_ep_bp); +int iSetMSC_PRM_PORT_BP_STA0_prm_mqm_cp_ep_bp(unsigned int uprm_mqm_cp_ep_bp); +int iSetMSC_PRM_PORT_BP_STA0_prm_mqm_dp_root_bp(unsigned int uprm_mqm_dp_root_bp); +int iSetMSC_PRM_PORT_BP_STA0_prm_mqm_cp_root_bp(unsigned int uprm_mqm_cp_root_bp); +int iSetMSC_PRM_PORT_BP_STA0_prm_mqm_root_bp(unsigned int uprm_mqm_root_bp); +int iSetMSC_PRM_PORT_BP_STA1_prm_mqm_soc_dp_cos_bp(unsigned int uprm_mqm_soc_dp_cos_bp); +int iSetMSC_PRM_PORT_BP_STA1_prm_mqm_soc_cp_cos_bp(unsigned int uprm_mqm_soc_cp_cos_bp); +int iSetMSC_PRM_PORT_BP_STA1_prm_mqm_soc_dp_root_bp(unsigned int uprm_mqm_soc_dp_root_bp); +int iSetMSC_PRM_PORT_BP_STA1_prm_mqm_soc_cp_root_bp(unsigned int uprm_mqm_soc_cp_root_bp); +int iSetMSC_QU_COS_BP_STA0_prm_mqm_dp_ep_cos_bp0(unsigned int uprm_mqm_dp_ep_cos_bp0); +int iSetMSC_QU_COS_BP_STA1_prm_mqm_dp_ep_cos_bp1(unsigned int uprm_mqm_dp_ep_cos_bp1); +int iSetSOCMSC_RT_EP_BP_STA_socmsc_el_bp(unsigned int usocmsc_el_bp); +int iSetSOCMSC_RT_EP_BP_STA_socmsc_sl_bp(unsigned int usocmsc_sl_bp); +int iSetSOCMSC_RT_EP_BP_STA_socmsc_rl_bp(unsigned int usocmsc_rl_bp); +int iSetSOCMSC_QUEUE_BP_STA0_socmsc_ql_bp0(unsigned int usocmsc_ql_bp0); +int iSetSOCMSC_QUEUE_BP_STA1_socmsc_ql_bp1(unsigned int usocmsc_ql_bp1); +int iSetSOCMSC_QUEUE_BP_STA2_socmsc_ql_bp2(unsigned int usocmsc_ql_bp2); +int iSetSOCMSC_QUEUE_BP_STA3_socmsc_ql_bp3(unsigned int usocmsc_ql_bp3); +int iSetSOCMSC_QUEUE_ELIGIBLE_STA0_socmsc_ql_eligible0(unsigned int usocmsc_ql_eligible0); +int iSetSOCMSC_QUEUE_ELIGIBLE_STA1_socmsc_ql_eligible1(unsigned int usocmsc_ql_eligible1); +int iSetSOCMSC_QUEUE_ELIGIBLE_STA2_socmsc_ql_eligible2(unsigned int usocmsc_ql_eligible2); +int iSetSOCMSC_QUEUE_ELIGIBLE_STA3_socmsc_ql_eligible3(unsigned int usocmsc_ql_eligible3); +int iSetMSC_RT_HOST_BP_STA_msc_ns_hl_bp(unsigned int umsc_ns_hl_bp); +int iSetMSC_RT_HOST_BP_STA_msc_cs_hl_bp(unsigned int umsc_cs_hl_bp); +int iSetMSC_RT_HOST_BP_STA_msc_ns_sl_bp(unsigned int umsc_ns_sl_bp); +int iSetMSC_RT_HOST_BP_STA_msc_cs_sl_bp(unsigned int umsc_cs_sl_bp); +int iSetMSC_RT_HOST_BP_STA_msc_rl_bp(unsigned int umsc_rl_bp); +int iSetMSC_RT_HOST_BP_STA_enqc_msc_dp_bp(unsigned int uenqc_msc_dp_bp); +int iSetMSC_RT_HOST_BP_STA_enqc_msc_cp_bp(unsigned int uenqc_msc_cp_bp); +int iSetMSC_HOSTEP_NS_BP_STA_msc_host_ep_ns_bp(unsigned int umsc_host_ep_ns_bp); +int iSetMSC_HOSTEP_NFMQ_BP_STA_msc_host_ep_nfmq_bp(unsigned int umsc_host_ep_nfmq_bp); +int iSetMSC_HOSTEP_CMQ_BP_STA_msc_host_ep_cmq_bp(unsigned int umsc_host_ep_cmq_bp); +int iSetMSC_FIFO_TH_CFG_msc_ns_du_fifo_gap(unsigned int umsc_ns_du_fifo_gap); +int iSetMSC_FIFO_TH_CFG_msc_cs_du_fifo_gap(unsigned int umsc_cs_du_fifo_gap); +int iSetMSC_FIFO_TH_CFG_socmsc_du_fifo_gap(unsigned int usocmsc_du_fifo_gap); +int iSetMSC_FIFO_TH_CFG_msc_fast_cnp_fifo_gap(unsigned int umsc_fast_cnp_fifo_gap); +int iSetMSC_FIFO_ST0_msc_fifo0_st0(unsigned int umsc_fifo0_st0); +int iSetMSC_FIFO_ST0_msc_fifo1_st0(unsigned int umsc_fifo1_st0); +int iSetMSC_FIFO_ST0_msc_fifo2_st0(unsigned int umsc_fifo2_st0); +int iSetMSC_FIFO_ST0_msc_fifo3_st0(unsigned int umsc_fifo3_st0); +int iSetMSC_FIFO_ST0_msc_fifo4_st0(unsigned int umsc_fifo4_st0); +int iSetMSC_FIFO_ST0_msc_fifo5_st0(unsigned int umsc_fifo5_st0); +int iSetMSC_FIFO_ST0_msc_fifo6_st0(unsigned int umsc_fifo6_st0); +int iSetMSC_FIFO_ST0_msc_fifo7_st0(unsigned int umsc_fifo7_st0); +int iSetMSC_FIFO_ST0_msc_fifo8_st0(unsigned int umsc_fifo8_st0); +int iSetMSC_FIFO_ST0_msc_fifo9_st0(unsigned int umsc_fifo9_st0); +int iSetMSC_FIFO_ST0_msc_fifo10_st0(unsigned int umsc_fifo10_st0); +int iSetMSC_FIFO_ST0_msc_fifo11_st0(unsigned int umsc_fifo11_st0); +int iSetMSC_FIFO_ST0_msc_fifo12_st0(unsigned int umsc_fifo12_st0); +int iSetMSC_FIFO_ST0_msc_fifo13_st0(unsigned int umsc_fifo13_st0); +int iSetMSC_FIFO_ST0_msc_fifo14_st0(unsigned int umsc_fifo14_st0); +int iSetMSC_FIFO_ST0_msc_fifo15_st0(unsigned int umsc_fifo15_st0); +int iSetMSC_FIFO_ST1_msc_fifo0_st1(unsigned int umsc_fifo0_st1); +int iSetMSC_FIFO_ST1_msc_fifo1_st1(unsigned int umsc_fifo1_st1); +int iSetMSC_FIFO_ST1_msc_fifo2_st1(unsigned int umsc_fifo2_st1); +int iSetMSC_FIFO_ST1_msc_fifo3_st1(unsigned int umsc_fifo3_st1); +int iSetMSC_FIFO_ST1_msc_fifo4_st1(unsigned int umsc_fifo4_st1); +int iSetMSC_FIFO_ST1_msc_fifo5_st1(unsigned int umsc_fifo5_st1); +int iSetMSC_FIFO_ST1_msc_fifo6_st1(unsigned int umsc_fifo6_st1); +int iSetMSC_FIFO_ST1_msc_fifo7_st1(unsigned int umsc_fifo7_st1); +int iSetMSC_FIFO_ST1_msc_fifo8_st1(unsigned int umsc_fifo8_st1); +int iSetMSC_FIFO_ST1_msc_fifo9_st1(unsigned int umsc_fifo9_st1); +int iSetMSC_FIFO_ST1_msc_fifo10_st1(unsigned int umsc_fifo10_st1); +int iSetMSC_FIFO_ST1_msc_fifo11_st1(unsigned int umsc_fifo11_st1); +int iSetMSC_FIFO_ST1_msc_fifo12_st1(unsigned int umsc_fifo12_st1); +int iSetMSC_FIFO_ST1_msc_fifo13_st1(unsigned int umsc_fifo13_st1); +int iSetMSC_FIFO_ST1_msc_fifo14_st1(unsigned int umsc_fifo14_st1); +int iSetMSC_FIFO_ST1_msc_fifo15_st1(unsigned int umsc_fifo15_st1); +int iSetMSC_FIFO_ST2_msc_fifo0_st2(unsigned int umsc_fifo0_st2); +int iSetMSC_FIFO_ST2_msc_fifo1_st2(unsigned int umsc_fifo1_st2); +int iSetMSC_FIFO_ST2_msc_fifo2_st2(unsigned int umsc_fifo2_st2); +int iSetMSC_FIFO_ST2_msc_fifo3_st2(unsigned int umsc_fifo3_st2); +int iSetMSC_FIFO_ST2_msc_fifo4_st2(unsigned int umsc_fifo4_st2); +int iSetMSC_FIFO_ST2_msc_fifo5_st2(unsigned int umsc_fifo5_st2); +int iSetMSC_FIFO_ST2_msc_fifo6_st2(unsigned int umsc_fifo6_st2); +int iSetMSC_FIFO_ST2_msc_fifo7_st2(unsigned int umsc_fifo7_st2); +int iSetMSC_FIFO_ST2_msc_fifo8_st2(unsigned int umsc_fifo8_st2); +int iSetMSC_FIFO_ST2_msc_fifo9_st2(unsigned int umsc_fifo9_st2); +int iSetMSC_FIFO_ST2_msc_fifo10_st2(unsigned int umsc_fifo10_st2); +int iSetMSC_FIFO_ST2_msc_fifo11_st2(unsigned int umsc_fifo11_st2); +int iSetMSC_FIFO_ST2_msc_fifo12_st2(unsigned int umsc_fifo12_st2); +int iSetMSC_FIFO_ST2_msc_fifo13_st2(unsigned int umsc_fifo13_st2); +int iSetMSC_FIFO_ST2_msc_fifo14_st2(unsigned int umsc_fifo14_st2); +int iSetMSC_FIFO_ST2_msc_fifo15_st2(unsigned int umsc_fifo15_st2); +int iSetMSC_FIFO_ST3_msc_fifo0_st3(unsigned int umsc_fifo0_st3); +int iSetMSC_FIFO_ST3_msc_fifo1_st3(unsigned int umsc_fifo1_st3); +int iSetMSC_FIFO_ST3_msc_fifo2_st3(unsigned int umsc_fifo2_st3); +int iSetMSC_FIFO_ST3_msc_fifo3_st3(unsigned int umsc_fifo3_st3); +int iSetMSC_FIFO_ST3_msc_fifo4_st3(unsigned int umsc_fifo4_st3); +int iSetMSC_FIFO_ST3_msc_fifo5_st3(unsigned int umsc_fifo5_st3); +int iSetMSC_FIFO_ST3_msc_fifo6_st3(unsigned int umsc_fifo6_st3); +int iSetMSC_FIFO_ST3_msc_fifo7_st3(unsigned int umsc_fifo7_st3); +int iSetMSC_FIFO_ST3_msc_fifo8_st3(unsigned int umsc_fifo8_st3); +int iSetMSC_FIFO_ST3_msc_fifo9_st3(unsigned int umsc_fifo9_st3); +int iSetMSC_FIFO_ST3_msc_fifo10_st3(unsigned int umsc_fifo10_st3); +int iSetMSC_FIFO_ST3_msc_fifo11_st3(unsigned int umsc_fifo11_st3); +int iSetCMQ_RX_UP_CNT_cmq_up_cnt(unsigned int ucmq_up_cnt); +int iSetNFMQ_RX_UP_CNT_nfmq_up_cnt(unsigned int unfmq_up_cnt); +int iSetNMQ_RX_UP_CNT_nmq_up_cnt(unsigned int unmq_up_cnt); +int iSetCMQ_SCH_CNT_cmq_sch_cnt(unsigned int ucmq_sch_cnt); +int iSetNFMQ_SCH_CNT_nfmq_sch_cnt(unsigned int unfmq_sch_cnt); +int iSetNMQ_SCH_CNT_nmq_sch_cnt(unsigned int unmq_sch_cnt); +int iSetSOCCMQ_UP_CNT_soccmq_up_cnt(unsigned int usoccmq_up_cnt); +int iSetSOCNMQ_UP_CNT_socnmq_up_cnt(unsigned int usocnmq_up_cnt); +int iSetSOCCMQ_SCH_CNT_soccmq_sch_cnt(unsigned int usoccmq_sch_cnt); +int iSetSOCNMQ_SCH_CNT_socnmq_sch_cnt(unsigned int usocnmq_sch_cnt); +int iSetCMQ_EMPT_SCH_CNT_cmq_empt_sch_cnt(unsigned int ucmq_empt_sch_cnt); +int iSetNFMQ_EMPT_SCH_CNT_nfmq_empt_sch_cnt(unsigned int unfmq_empt_sch_cnt); +int iSetNMQ_EMPT_SCH_CNT_nmq_empt_sch_cnt(unsigned int unmq_empt_sch_cnt); +int iSetCMQ_RX_DU_CNT_cmq_du_cnt(unsigned int ucmq_du_cnt); +int iSetNFMQ_RX_DU_CNT_nfmq_du_cnt(unsigned int unfmq_du_cnt); +int iSetNMQ_RX_DU_CNT_nmq_du_cnt(unsigned int unmq_du_cnt); +int iSetSOCCMQ_DU_CNT_soccmq_du_cnt(unsigned int usoccmq_du_cnt); +int iSetSOCNMQ_DU_CNT_socnmq_du_cnt(unsigned int usocnmq_du_cnt); +int iSetMSC_ECC_1BIT_ERR_CNT_msc_ecc_1bit_err_cnt(unsigned int umsc_ecc_1bit_err_cnt); +int iSetMSC_ECC_2BIT_ERR_CNT_msc_ecc_2bit_err_cnt(unsigned int umsc_ecc_2bit_err_cnt); +int iSetSCH_MQ_DFX_CFG_sch_mq_dfx_cfg(unsigned int usch_mq_dfx_cfg); +int iSetSCH_MQ_DFX_CFG_sch_mq_qa_dfx_cfg(unsigned int usch_mq_qa_dfx_cfg); +int iSetSCH_MQ_DFX_CFG_sch_mq_dfx_cfg_vld(unsigned int usch_mq_dfx_cfg_vld); +int iSetSCH_MQ_DFX_UP_CNT_sch_mq_dfx_up_cnt(unsigned int usch_mq_dfx_up_cnt); +int iSetSCH_MQ_DFX_SCH_CNT_sch_mq_dfx_sch_cnt(unsigned int usch_mq_dfx_sch_cnt); +int iSetSCH_MQ_DFX_EMPT_SCH_CNT_sch_mq_dfx_empt_sch_cnt(unsigned int usch_mq_dfx_empt_sch_cnt); +int iSetSCH_MQ_DFX_DU_CNT_sch_mq_dfx_du_cnt(unsigned int usch_mq_dfx_du_cnt); +int iSetSCH_SOCMQ_DFX_CFG_sch_socmq_dfx_cfg(unsigned int usch_socmq_dfx_cfg); +int iSetSCH_SOCMQ_DFX_CFG_sch_socmq_dfx_cfg_vld(unsigned int usch_socmq_dfx_cfg_vld); +int iSetSCH_SOCMQ_DFX_UP_CNT_sch_socmq_dfx_up_cnt(unsigned int usch_socmq_dfx_up_cnt); +int iSetSCH_SOCMQ_DFX_SCH_CNT_sch_socmq_dfx_sch_cnt(unsigned int usch_socmq_dfx_sch_cnt); +int iSetSCH_SOCMQ_DFX_DU_CNT_sch_socmq_dfx_du_cnt(unsigned int usch_socmq_dfx_du_cnt); +int iSetSOCMSC_MCD_DU_INFO_PTR0_socmsc_mcd_len_info(unsigned int usocmsc_mcd_len_info); +int iSetSOCMSC_MCD_DU_INFO_PTR1_socmsc_mcd_id_info(unsigned int usocmsc_mcd_id_info); +int iSetMSC_CS_MCD_DU_INFO_PTR0_msc_mcd_cs_len_info(unsigned int umsc_mcd_cs_len_info); +int iSetMSC_CS_MCD_DU_INFO_PTR1_msc_mcd_cs_id_info_0(unsigned int umsc_mcd_cs_id_info_0); +int iSetMSC_CS_MCD_DU_INFO_PTR2_msc_mcd_cs_id_info_1(unsigned int umsc_mcd_cs_id_info_1); +int iSetMSC_NS_MCD_DU_INFO_PTR0_msc_mcd_ns_len_info(unsigned int umsc_mcd_ns_len_info); +int iSetMSC_NS_MCD_DU_INFO_PTR1_msc_mcd_ns_id_info_0(unsigned int umsc_mcd_ns_id_info_0); +int iSetMSC_NS_MCD_DU_INFO_PTR2_msc_mcd_ns_id_info_1(unsigned int umsc_mcd_ns_id_info_1); + +/* Define the union csr_deqc_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_rw_rsv0_u; + +/* Define the union csr_deqc_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_rw_rsv1_u; + +/* Define the union csr_deqc_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_rw_rsv2_u; + +/* Define the union csr_deqc_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_rw_rsv3_u; + +/* Define the union csr_deqc_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_indrect_addr : 24; /* [23:0] */ + u32 deqc_indrect_tab : 4; /* [27:24] */ + u32 deqc_indrect_stat : 2; /* [29:28] */ + u32 deqc_indrect_mode : 1; /* [30] */ + u32 deqc_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_indrect_ctrl_u; + +/* Define the union csr_deqc_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_indrect_timeout_u; + +/* Define the union csr_deqc_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_indrect_data_u; + +/* Define the union csr_deqc_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ecc_bypass_en_u; + +/* Define the union csr_deqc_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_deqc_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_deqc_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_deqc_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_deqc_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_1 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_deqc_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 deqc_enable : 1; /* [27] */ + u32 deqc_int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_int_vector_u; + +/* Define the union csr_deqc_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_int_data : 5; /* [4:0] */ + u32 rsv_4 : 11; /* [15:5] */ + u32 deqc_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_int_u; + +/* Define the union csr_deqc_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_int_en : 5; /* [4:0] */ + u32 rsv_5 : 11; /* [15:5] */ + u32 deqc_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_int_en_u; + +/* Define the union csr_deqc_mem_1bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ecc_1bit_err : 1; /* [0] */ + u32 deqc_ecc_1bit_err_insrt : 1; /* [1] */ + u32 deqc_ecc_1bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_1bit_err_u; + +/* Define the union csr_deqc_mem_2bit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ecc_2bit_err : 1; /* [0] */ + u32 deqc_ecc_2bit_err_insrt : 1; /* [1] */ + u32 deqc_ecc_2bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_2bit_err_u; + +/* Define the union csr_deqc_enmq_bind_config_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_enmq_bind_cfg_err : 1; /* [0] */ + u32 deqc_enmq_bind_cfg_err_insrt : 1; /* [1] */ + u32 deqc_enmq_bind_cfg_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_enmq_bind_config_err_u; + +/* Define the union csr_deqc_enfmq_bind_config_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_enfmq_bind_cfg_err : 1; /* [0] */ + u32 deqc_enfmq_bind_cfg_err_insrt : 1; /* [1] */ + u32 deqc_enfmq_bind_cfg_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_enfmq_bind_config_err_u; + +/* Define the union csr_deqc_mem_err_req_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_mem_err_req_0 : 1; /* [0] */ + u32 deqc_mem_err_req_1 : 1; /* [1] */ + u32 deqc_mem_err_req_2 : 1; /* [2] */ + u32 deqc_mem_err_req_3 : 1; /* [3] */ + u32 deqc_mem_err_req_4 : 1; /* [4] */ + u32 deqc_mem_err_req_5 : 1; /* [5] */ + u32 deqc_mem_err_req_6 : 1; /* [6] */ + u32 deqc_mem_err_req_7 : 1; /* [7] */ + u32 deqc_mem_err_req_8 : 1; /* [8] */ + u32 deqc_mem_err_req_9 : 1; /* [9] */ + u32 deqc_mem_err_req_10 : 1; /* [10] */ + u32 deqc_mem_err_req_11 : 1; /* [11] */ + u32 deqc_mem_err_req_12 : 1; /* [12] */ + u32 deqc_mem_err_req_13 : 1; /* [13] */ + u32 deqc_mem_err_req_14 : 1; /* [14] */ + u32 deqc_mem_err_req_15 : 1; /* [15] */ + u32 deqc_mem_err_req_16 : 1; /* [16] */ + u32 deqc_mem_err_req_17 : 1; /* [17] */ + u32 deqc_mem_err_req_18 : 1; /* [18] */ + u32 deqc_mem_err_req_19 : 1; /* [19] */ + u32 deqc_mem_err_req_20 : 1; /* [20] */ + u32 deqc_mem_err_req_21 : 1; /* [21] */ + u32 deqc_mem_err_req_22 : 1; /* [22] */ + u32 deqc_mem_err_req_23 : 1; /* [23] */ + u32 rsv_6 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_mem_err_req_u; + +/* Define the union csr_deqc_fifo_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_fifo_int0_err0 : 1; /* [0] */ + u32 deqc_fifo_int0_err0_insrt : 1; /* [1] */ + u32 deqc_fifo_int0_err1 : 1; /* [2] */ + u32 deqc_fifo_int0_err1_insrt : 1; /* [3] */ + u32 deqc_fifo_int0_err2 : 1; /* [4] */ + u32 deqc_fifo_int0_err2_insrt : 1; /* [5] */ + u32 deqc_fifo_int0_err3 : 1; /* [6] */ + u32 deqc_fifo_int0_err3_insrt : 1; /* [7] */ + u32 deqc_fifo_int0_err4 : 1; /* [8] */ + u32 deqc_fifo_int0_err4_insrt : 1; /* [9] */ + u32 deqc_fifo_int0_err5 : 1; /* [10] */ + u32 deqc_fifo_int0_err5_insrt : 1; /* [11] */ + u32 deqc_fifo_int0_err6 : 1; /* [12] */ + u32 deqc_fifo_int0_err6_insrt : 1; /* [13] */ + u32 deqc_fifo_int0_err7 : 1; /* [14] */ + u32 deqc_fifo_int0_err7_insrt : 1; /* [15] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_fifo_int_u; + +/* Define the union csr_deqc_fifo_wr_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_fifo_int0_err0_en : 1; /* [0] */ + u32 deqc_fifo_int0_err1_en : 1; /* [1] */ + u32 deqc_fifo_int0_err2_en : 1; /* [2] */ + u32 deqc_fifo_int0_err3_en : 1; /* [3] */ + u32 deqc_fifo_int0_err4_en : 1; /* [4] */ + u32 deqc_fifo_int0_err5_en : 1; /* [5] */ + u32 deqc_fifo_int0_err6_en : 1; /* [6] */ + u32 deqc_fifo_int0_err7_en : 1; /* [7] */ + u32 rsv_8 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_fifo_wr_int_mask_u; + +/* Define the union csr_deqc_times_count_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deq_times_count : 4; /* [3:0] */ + u32 rsv_9 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_times_count_cfg_u; + +/* Define the union csr_deqc_blk_data_len0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 blk_data_len_0 : 8; /* [7:0] */ + u32 blk_data_len_1 : 8; /* [15:8] */ + u32 blk_data_len_2 : 8; /* [23:16] */ + u32 blk_data_len_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_blk_data_len0_u; + +/* Define the union csr_deqc_blk_data_len1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 blk_data_len_4 : 8; /* [7:0] */ + u32 blk_data_len_5 : 8; /* [15:8] */ + u32 blk_data_len_6 : 8; /* [23:16] */ + u32 blk_data_len_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_blk_data_len1_u; + +/* Define the union csr_deqc_root_crr_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_crr_weight_cfg_ns : 3; /* [2:0] */ + u32 rsv_10 : 5; /* [7:3] */ + u32 deqc_crr_weight_cfg_cs : 3; /* [10:8] */ + u32 rsv_11 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_root_crr_weight_cfg_u; + +/* Define the union csr_deqc_weight_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 weight_offset : 2; /* [1:0] */ + u32 rsv_12 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_weight_offset_u; + +/* Define the union csr_deqc_nmq_ep_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_ep_weight : 8; /* [7:0] */ + u32 rsv_13 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_ep_weight_u; + +/* Define the union csr_deqc_nfmq_ep_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_ep_weight : 8; /* [7:0] */ + u32 rsv_14 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_ep_weight_u; + +/* Define the union csr_deqc_nmq_host_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_weight : 8; /* [7:0] */ + u32 rsv_15 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_weight_u; + +/* Define the union csr_deqc_nfmq_host_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_weight : 8; /* [7:0] */ + u32 rsv_16 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_weight_u; + +/* Define the union csr_deqc_nmq_host_shap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_shap_cfg : 25; /* [24:0] */ + u32 rsv_17 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_shap_cfg_u; + +/* Define the union csr_deqc_nfmq_host_shap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_shap_cfg : 25; /* [24:0] */ + u32 rsv_18 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_shap_cfg_u; + +/* Define the union csr_deqc_serv_shap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 service_shap_cfg : 25; /* [24:0] */ + u32 rsv_19 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_serv_shap_cfg_u; + +/* Define the union csr_deqc_root_shap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_shap_cfg : 25; /* [24:0] */ + u32 rsv_20 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_root_shap_cfg_u; + +/* Define the union csr_deqc_shap_bypass_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ns_host_shap_byp_vld : 1; /* [0] */ + u32 rsv_21 : 3; /* [3:1] */ + u32 deqc_cs_host_shap_byp_vld : 1; /* [4] */ + u32 rsv_22 : 3; /* [7:5] */ + u32 deqc_serv_shap_byp_vld : 1; /* [8] */ + u32 rsv_23 : 3; /* [11:9] */ + u32 deqc_rt_shap_byp_vld : 1; /* [12] */ + u32 rsv_24 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_shap_bypass_cfg_u; + +/* Define the union csr_deqc_spcos_share_rsc_xon_rsp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_spcos_rsc_xon_resp_en : 1; /* [0] */ + u32 rsv_25 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_spcos_share_rsc_xon_rsp_cfg_u; + +/* Define the union csr_deqc_rh_xon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_root_xon_cfg : 1; /* [0] */ + u32 rsv_26 : 7; /* [7:1] */ + u32 deqc_service_xon_cfg_nmq : 1; /* [8] */ + u32 deqc_service_xon_cfg_nfmq : 1; /* [9] */ + u32 rsv_27 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_rh_xon_cfg_u; + +/* Define the union csr_deqc_host_xon_cfg_nmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_host_xon_cfg_nmq : 4; /* [3:0] */ + u32 rsv_28 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_host_xon_cfg_nmq_u; + +/* Define the union csr_deqc_host_xon_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_host_xon_cfg_nfmq : 4; /* [3:0] */ + u32 rsv_29 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_host_xon_cfg_nfmq_u; + +/* Define the union csr_deqc_ep_xon_cfg_nmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ep_xon_cfg_nmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_ep_xon_cfg_nmq_u; + +/* Define the union csr_deqc_ep_xon_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ep_xon_cfg_nfmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_ep_xon_cfg_nfmq_u; + +/* Define the union csr_deqc_cos_xon_cfg_nmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_cos_xon_cfg_nmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_cos_xon_cfg_nmq_u; + +/* Define the union csr_deqc_cos_xon_cfg_nfmq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_cos_xon_cfg_nfmq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_cos_xon_cfg_nfmq_u; + +/* Define the union csr_deqc_root_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 root_xon_st : 1; /* [0] */ + u32 rsv_30 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_root_xon_st_u; + +/* Define the union csr_deqc_nmq_service_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_serve_xon_st : 1; /* [0] */ + u32 rsv_31 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_service_xon_st_u; + +/* Define the union csr_deqc_nfmq_service_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_serve_xon_st : 1; /* [0] */ + u32 rsv_32 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_service_xon_st_u; + +/* Define the union csr_deqc_nmq_host_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_xon_st : 4; /* [3:0] */ + u32 rsv_33 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_xon_st_u; + +/* Define the union csr_deqc_nfmq_host_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_xon_st : 4; /* [3:0] */ + u32 rsv_34 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_xon_st_u; + +/* Define the union csr_deqc_nmq_host_ep_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_ep_xon_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_ep_xon_st_u; + +/* Define the union csr_deqc_nfmq_host_ep_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_ep_xon_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_ep_xon_st_u; + +/* Define the union csr_deqc_nmq_host_spass_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_spass_st : 4; /* [3:0] */ + u32 rsv_35 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_spass_st_u; + +/* Define the union csr_deqc_nfmq_host_shap_pass_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_spass_st : 4; /* [3:0] */ + u32 rsv_36 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_shap_pass_st_u; + +/* Define the union csr_deqc_fifo_dfx_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_cs_shap_sch_fifo_dfx : 2; /* [1:0] */ + u32 host_ns_shap_sch_fifo_dfx : 2; /* [3:2] */ + u32 serv_shap_sch_fifo_dfx : 2; /* [5:4] */ + u32 root_shap_sch_fifo_dfx : 2; /* [7:6] */ + u32 rsv_37 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_fifo_dfx_u; + +/* Define the union csr_deqc_nmq_up_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nmq_up_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_up_pkt_cnt_u; + +/* Define the union csr_deqc_nfmq_up_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nfmq_up_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_up_pkt_cnt_u; + +/* Define the union csr_deqc_nmq_deq_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nmq_deq_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_deq_pkt_cnt_u; + +/* Define the union csr_deqc_nfmq_deq_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nfmq_deq_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_deq_pkt_cnt_u; + +/* Define the union csr_deqc_nmq_deq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nmq_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_deq_cmd_cnt_u; + +/* Define the union csr_deqc_nfmq_deq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nfmq_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_deq_cmd_cnt_u; + +/* Define the union csr_deqc_nfmq_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nfmq_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_empt_sch_cnt_u; + +/* Define the union csr_deqc_nmq_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_nmq_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_empt_sch_cnt_u; + +/* Define the union csr_deqc_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_ecc_1bit_err_cnt_u; + +/* Define the union csr_deqc_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_ecc_2bit_err_cnt_u; + +/* Define the union csr_deqc_sch_mq_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_sch_mq_dfx_cfg : 13; /* [12:0] */ + u32 rsv_38 : 3; /* [15:13] */ + u32 deqc_sch_mq_qa_dfx_cfg : 1; /* [16] */ + u32 rsv_39 : 3; /* [19:17] */ + u32 deqc_sch_mq_dfx_cfg_vld : 1; /* [20] */ + u32 rsv_40 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_sch_mq_dfx_cfg_u; + +/* Define the union csr_deqc_sch_mq_dfx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_sch_mq_dfx_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_sch_mq_dfx_up_cnt_u; + +/* Define the union csr_deqc_sch_mq_dfx_deq_cmd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_sch_mq_dfx_deq_cmd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_sch_mq_dfx_deq_cmd_cnt_u; + +/* Define the union csr_deqc_sch_mq_dfx_deq_num_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_sch_mq_dfx_deq_num_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_sch_mq_dfx_deq_num_cnt_u; + +/* Define the union csr_deqc_sch_mq_dfx_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 deqc_sch_mq_dfx_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_sch_mq_dfx_empt_sch_cnt_u; + +/* Define the union csr_deqc_nmq_host_ep_cos_xon_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nmq_host_ep_cos_xon_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nmq_host_ep_cos_xon_st_u; + +/* Define the union csr_deqc_nfmq_host_ep_cos_xon_st0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 nfmq_host_ep_cos_xon_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_deqc_nfmq_host_ep_cos_xon_st0_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_deqc_rw_rsv0_u deqc_rw_rsv0; /* 0 */ + volatile csr_deqc_rw_rsv1_u deqc_rw_rsv1; /* 4 */ + volatile csr_deqc_rw_rsv2_u deqc_rw_rsv2; /* 8 */ + volatile csr_deqc_rw_rsv3_u deqc_rw_rsv3; /* C */ + volatile csr_deqc_indrect_ctrl_u deqc_indrect_ctrl; /* 10 */ + volatile csr_deqc_indrect_timeout_u deqc_indrect_timeout; /* 14 */ + volatile csr_deqc_indrect_data_u deqc_indrect_data; /* 18 */ + volatile csr_deqc_mem_ecc_bypass_en_u deqc_mem_ecc_bypass_en; /* 20 */ + volatile csr_deqc_mem_ctrl_bus_cfg0_u deqc_mem_ctrl_bus_cfg0; /* 24 */ + volatile csr_deqc_mem_ctrl_bus_cfg1_u deqc_mem_ctrl_bus_cfg1; /* 28 */ + volatile csr_deqc_mem_ctrl_bus_cfg2_u deqc_mem_ctrl_bus_cfg2; /* 2C */ + volatile csr_deqc_mem_ctrl_bus_cfg3_u deqc_mem_ctrl_bus_cfg3; /* 30 */ + volatile csr_deqc_mem_ctrl_bus_cfg4_u deqc_mem_ctrl_bus_cfg4; /* 34 */ + volatile csr_deqc_int_vector_u deqc_int_vector; /* 100 */ + volatile csr_deqc_int_u deqc_int; /* 104 */ + volatile csr_deqc_int_en_u deqc_int_en; /* 108 */ + volatile csr_deqc_mem_1bit_err_u deqc_mem_1bit_err; /* 10C */ + volatile csr_deqc_mem_2bit_err_u deqc_mem_2bit_err; /* 110 */ + volatile csr_deqc_enmq_bind_config_err_u deqc_enmq_bind_config_err; /* 114 */ + volatile csr_deqc_enfmq_bind_config_err_u deqc_enfmq_bind_config_err; /* 118 */ + volatile csr_deqc_mem_err_req_u deqc_mem_err_req; /* 150 */ + volatile csr_deqc_fifo_int_u deqc_fifo_int; /* 154 */ + volatile csr_deqc_fifo_wr_int_mask_u deqc_fifo_wr_int_mask; /* 158 */ + volatile csr_deqc_times_count_cfg_u deqc_times_count_cfg; /* 200 */ + volatile csr_deqc_blk_data_len0_u deqc_blk_data_len0; /* 204 */ + volatile csr_deqc_blk_data_len1_u deqc_blk_data_len1; /* 208 */ + volatile csr_deqc_root_crr_weight_cfg_u deqc_root_crr_weight_cfg; /* 20C */ + volatile csr_deqc_weight_offset_u deqc_weight_offset; /* 210 */ + volatile csr_deqc_nmq_ep_weight_u deqc_nmq_ep_weight[32]; /* 300 */ + volatile csr_deqc_nfmq_ep_weight_u deqc_nfmq_ep_weight[32]; /* 380 */ + volatile csr_deqc_nmq_host_weight_u deqc_nmq_host_weight[4]; /* 400 */ + volatile csr_deqc_nfmq_host_weight_u deqc_nfmq_host_weight[4]; /* 410 */ + volatile csr_deqc_nmq_host_shap_cfg_u deqc_nmq_host_shap_cfg[4]; /* 420 */ + volatile csr_deqc_nfmq_host_shap_cfg_u deqc_nfmq_host_shap_cfg[4]; /* 430 */ + volatile csr_deqc_serv_shap_cfg_u deqc_serv_shap_cfg[2]; /* 440 */ + volatile csr_deqc_root_shap_cfg_u deqc_root_shap_cfg; /* 450 */ + volatile csr_deqc_shap_bypass_cfg_u deqc_shap_bypass_cfg; /* 500 */ + volatile csr_deqc_spcos_share_rsc_xon_rsp_cfg_u deqc_spcos_share_rsc_xon_rsp_cfg; /* 504 */ + volatile csr_deqc_rh_xon_cfg_u deqc_rh_xon_cfg; /* 508 */ + volatile csr_deqc_host_xon_cfg_nmq_u deqc_host_xon_cfg_nmq; /* 50C */ + volatile csr_deqc_host_xon_cfg_nfmq_u deqc_host_xon_cfg_nfmq; /* 510 */ + volatile csr_deqc_ep_xon_cfg_nmq_u deqc_ep_xon_cfg_nmq; /* 514 */ + volatile csr_deqc_ep_xon_cfg_nfmq_u deqc_ep_xon_cfg_nfmq; /* 518 */ + volatile csr_deqc_cos_xon_cfg_nmq_u deqc_cos_xon_cfg_nmq[8]; /* 520 */ + volatile csr_deqc_cos_xon_cfg_nfmq_u deqc_cos_xon_cfg_nfmq[8]; /* 540 */ + volatile csr_deqc_root_xon_st_u deqc_root_xon_st; /* 560 */ + volatile csr_deqc_nmq_service_xon_st_u deqc_nmq_service_xon_st; /* 564 */ + volatile csr_deqc_nfmq_service_xon_st_u deqc_nfmq_service_xon_st; /* 568 */ + volatile csr_deqc_nmq_host_xon_st_u deqc_nmq_host_xon_st; /* 56C */ + volatile csr_deqc_nfmq_host_xon_st_u deqc_nfmq_host_xon_st; /* 570 */ + volatile csr_deqc_nmq_host_ep_xon_st_u deqc_nmq_host_ep_xon_st; /* 574 */ + volatile csr_deqc_nfmq_host_ep_xon_st_u deqc_nfmq_host_ep_xon_st; /* 578 */ + volatile csr_deqc_nmq_host_spass_st_u deqc_nmq_host_spass_st; /* 57C */ + volatile csr_deqc_nfmq_host_shap_pass_st_u deqc_nfmq_host_shap_pass_st; /* 580 */ + volatile csr_deqc_fifo_dfx_u deqc_fifo_dfx; /* 584 */ + volatile csr_deqc_nmq_up_pkt_cnt_u deqc_nmq_up_pkt_cnt; /* 5C0 */ + volatile csr_deqc_nfmq_up_pkt_cnt_u deqc_nfmq_up_pkt_cnt; /* 5C4 */ + volatile csr_deqc_nmq_deq_pkt_cnt_u deqc_nmq_deq_pkt_cnt; /* 5C8 */ + volatile csr_deqc_nfmq_deq_pkt_cnt_u deqc_nfmq_deq_pkt_cnt; /* 5CC */ + volatile csr_deqc_nmq_deq_cmd_cnt_u deqc_nmq_deq_cmd_cnt; /* 5D0 */ + volatile csr_deqc_nfmq_deq_cmd_cnt_u deqc_nfmq_deq_cmd_cnt; /* 5D4 */ + volatile csr_deqc_nfmq_empt_sch_cnt_u deqc_nfmq_empt_sch_cnt; /* 5D8 */ + volatile csr_deqc_nmq_empt_sch_cnt_u deqc_nmq_empt_sch_cnt; /* 5DC */ + volatile csr_deqc_ecc_1bit_err_cnt_u deqc_ecc_1bit_err_cnt; /* 5E0 */ + volatile csr_deqc_ecc_2bit_err_cnt_u deqc_ecc_2bit_err_cnt; /* 5E4 */ + volatile csr_deqc_sch_mq_dfx_cfg_u deqc_sch_mq_dfx_cfg; /* 5E8 */ + volatile csr_deqc_sch_mq_dfx_up_cnt_u deqc_sch_mq_dfx_up_cnt; /* 5EC */ + volatile csr_deqc_sch_mq_dfx_deq_cmd_cnt_u deqc_sch_mq_dfx_deq_cmd_cnt; /* 5F0 */ + volatile csr_deqc_sch_mq_dfx_deq_num_cnt_u deqc_sch_mq_dfx_deq_num_cnt; /* 5F4 */ + volatile csr_deqc_sch_mq_dfx_empt_sch_cnt_u deqc_sch_mq_dfx_empt_sch_cnt; /* 5F8 */ + volatile csr_deqc_nmq_host_ep_cos_xon_st_u deqc_nmq_host_ep_cos_xon_st[8]; /* 600 */ + volatile csr_deqc_nfmq_host_ep_cos_xon_st0_u deqc_nfmq_host_ep_cos_xon_st0[8]; /* 620 */ +} S_mqm_deqc_REGS_TYPE; + +/* Declare the struct pointor of the module mqm_deqc */ +extern volatile S_mqm_deqc_REGS_TYPE *gopmqm_deqcAllReg; + +/* Declare the functions that set the member value */ +int iSetDEQC_RW_RSV0_deqc_rw_rsv0(unsigned int udeqc_rw_rsv0); +int iSetDEQC_RW_RSV1_deqc_rw_rsv1(unsigned int udeqc_rw_rsv1); +int iSetDEQC_RW_RSV2_deqc_rw_rsv2(unsigned int udeqc_rw_rsv2); +int iSetDEQC_RW_RSV3_deqc_rw_rsv3(unsigned int udeqc_rw_rsv3); +int iSetDEQC_INDRECT_CTRL_deqc_indrect_addr(unsigned int udeqc_indrect_addr); +int iSetDEQC_INDRECT_CTRL_deqc_indrect_tab(unsigned int udeqc_indrect_tab); +int iSetDEQC_INDRECT_CTRL_deqc_indrect_stat(unsigned int udeqc_indrect_stat); +int iSetDEQC_INDRECT_CTRL_deqc_indrect_mode(unsigned int udeqc_indrect_mode); +int iSetDEQC_INDRECT_CTRL_deqc_indrect_vld(unsigned int udeqc_indrect_vld); +int iSetDEQC_INDRECT_TIMEOUT_deqc_indrect_timeout(unsigned int udeqc_indrect_timeout); +int iSetDEQC_INDRECT_DATA_deqc_indrect_data(unsigned int udeqc_indrect_data); +int iSetDEQC_MEM_ECC_BYPASS_EN_deqc_mem_ecc_bypass(unsigned int udeqc_mem_ecc_bypass); +int iSetDEQC_MEM_CTRL_BUS_CFG0_deqc_mem_ctrl_bus_0(unsigned int udeqc_mem_ctrl_bus_0); +int iSetDEQC_MEM_CTRL_BUS_CFG1_deqc_mem_ctrl_bus_1(unsigned int udeqc_mem_ctrl_bus_1); +int iSetDEQC_MEM_CTRL_BUS_CFG2_deqc_mem_ctrl_bus_2(unsigned int udeqc_mem_ctrl_bus_2); +int iSetDEQC_MEM_CTRL_BUS_CFG3_deqc_mem_ctrl_bus_3(unsigned int udeqc_mem_ctrl_bus_3); +int iSetDEQC_MEM_CTRL_BUS_CFG4_deqc_mem_ctrl_bus_4(unsigned int udeqc_mem_ctrl_bus_4); +int iSetDEQC_INT_VECTOR_deqc_cpi_int_index(unsigned int udeqc_cpi_int_index); +int iSetDEQC_INT_VECTOR_deqc_enable(unsigned int udeqc_enable); +int iSetDEQC_INT_VECTOR_deqc_int_issue(unsigned int udeqc_int_issue); +int iSetDEQC_INT_deqc_int_data(unsigned int udeqc_int_data); +int iSetDEQC_INT_deqc_program_csr_id_ro(unsigned int udeqc_program_csr_id_ro); +int iSetDEQC_INT_EN_deqc_int_en(unsigned int udeqc_int_en); +int iSetDEQC_INT_EN_deqc_program_csr_id(unsigned int udeqc_program_csr_id); +int iSetDEQC_MEM_1BIT_ERR_deqc_ecc_1bit_err(unsigned int udeqc_ecc_1bit_err); +int iSetDEQC_MEM_1BIT_ERR_deqc_ecc_1bit_err_insrt(unsigned int udeqc_ecc_1bit_err_insrt); +int iSetDEQC_MEM_1BIT_ERR_deqc_ecc_1bit_err_info(unsigned int udeqc_ecc_1bit_err_info); +int iSetDEQC_MEM_2BIT_ERR_deqc_ecc_2bit_err(unsigned int udeqc_ecc_2bit_err); +int iSetDEQC_MEM_2BIT_ERR_deqc_ecc_2bit_err_insrt(unsigned int udeqc_ecc_2bit_err_insrt); +int iSetDEQC_MEM_2BIT_ERR_deqc_ecc_2bit_err_info(unsigned int udeqc_ecc_2bit_err_info); +int iSetDEQC_ENMQ_BIND_CONFIG_ERR_deqc_enmq_bind_cfg_err(unsigned int udeqc_enmq_bind_cfg_err); +int iSetDEQC_ENMQ_BIND_CONFIG_ERR_deqc_enmq_bind_cfg_err_insrt(unsigned int udeqc_enmq_bind_cfg_err_insrt); +int iSetDEQC_ENMQ_BIND_CONFIG_ERR_deqc_enmq_bind_cfg_err_info(unsigned int udeqc_enmq_bind_cfg_err_info); +int iSetDEQC_ENFMQ_BIND_CONFIG_ERR_deqc_enfmq_bind_cfg_err(unsigned int udeqc_enfmq_bind_cfg_err); +int iSetDEQC_ENFMQ_BIND_CONFIG_ERR_deqc_enfmq_bind_cfg_err_insrt(unsigned int udeqc_enfmq_bind_cfg_err_insrt); +int iSetDEQC_ENFMQ_BIND_CONFIG_ERR_deqc_enfmq_bind_cfg_err_info(unsigned int udeqc_enfmq_bind_cfg_err_info); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_0(unsigned int udeqc_mem_err_req_0); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_1(unsigned int udeqc_mem_err_req_1); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_2(unsigned int udeqc_mem_err_req_2); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_3(unsigned int udeqc_mem_err_req_3); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_4(unsigned int udeqc_mem_err_req_4); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_5(unsigned int udeqc_mem_err_req_5); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_6(unsigned int udeqc_mem_err_req_6); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_7(unsigned int udeqc_mem_err_req_7); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_8(unsigned int udeqc_mem_err_req_8); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_9(unsigned int udeqc_mem_err_req_9); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_10(unsigned int udeqc_mem_err_req_10); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_11(unsigned int udeqc_mem_err_req_11); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_12(unsigned int udeqc_mem_err_req_12); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_13(unsigned int udeqc_mem_err_req_13); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_14(unsigned int udeqc_mem_err_req_14); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_15(unsigned int udeqc_mem_err_req_15); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_16(unsigned int udeqc_mem_err_req_16); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_17(unsigned int udeqc_mem_err_req_17); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_18(unsigned int udeqc_mem_err_req_18); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_19(unsigned int udeqc_mem_err_req_19); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_20(unsigned int udeqc_mem_err_req_20); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_21(unsigned int udeqc_mem_err_req_21); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_22(unsigned int udeqc_mem_err_req_22); +int iSetDEQC_MEM_ERR_REQ_deqc_mem_err_req_23(unsigned int udeqc_mem_err_req_23); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err0(unsigned int udeqc_fifo_int0_err0); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err0_insrt(unsigned int udeqc_fifo_int0_err0_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err1(unsigned int udeqc_fifo_int0_err1); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err1_insrt(unsigned int udeqc_fifo_int0_err1_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err2(unsigned int udeqc_fifo_int0_err2); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err2_insrt(unsigned int udeqc_fifo_int0_err2_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err3(unsigned int udeqc_fifo_int0_err3); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err3_insrt(unsigned int udeqc_fifo_int0_err3_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err4(unsigned int udeqc_fifo_int0_err4); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err4_insrt(unsigned int udeqc_fifo_int0_err4_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err5(unsigned int udeqc_fifo_int0_err5); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err5_insrt(unsigned int udeqc_fifo_int0_err5_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err6(unsigned int udeqc_fifo_int0_err6); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err6_insrt(unsigned int udeqc_fifo_int0_err6_insrt); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err7(unsigned int udeqc_fifo_int0_err7); +int iSetDEQC_FIFO_INT_deqc_fifo_int0_err7_insrt(unsigned int udeqc_fifo_int0_err7_insrt); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err0_en(unsigned int udeqc_fifo_int0_err0_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err1_en(unsigned int udeqc_fifo_int0_err1_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err2_en(unsigned int udeqc_fifo_int0_err2_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err3_en(unsigned int udeqc_fifo_int0_err3_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err4_en(unsigned int udeqc_fifo_int0_err4_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err5_en(unsigned int udeqc_fifo_int0_err5_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err6_en(unsigned int udeqc_fifo_int0_err6_en); +int iSetDEQC_FIFO_WR_INT_MASK_deqc_fifo_int0_err7_en(unsigned int udeqc_fifo_int0_err7_en); +int iSetDEQC_TIMES_COUNT_CFG_deq_times_count(unsigned int udeq_times_count); +int iSetDEQC_BLK_DATA_LEN0_blk_data_len_0(unsigned int ublk_data_len_0); +int iSetDEQC_BLK_DATA_LEN0_blk_data_len_1(unsigned int ublk_data_len_1); +int iSetDEQC_BLK_DATA_LEN0_blk_data_len_2(unsigned int ublk_data_len_2); +int iSetDEQC_BLK_DATA_LEN0_blk_data_len_3(unsigned int ublk_data_len_3); +int iSetDEQC_BLK_DATA_LEN1_blk_data_len_4(unsigned int ublk_data_len_4); +int iSetDEQC_BLK_DATA_LEN1_blk_data_len_5(unsigned int ublk_data_len_5); +int iSetDEQC_BLK_DATA_LEN1_blk_data_len_6(unsigned int ublk_data_len_6); +int iSetDEQC_BLK_DATA_LEN1_blk_data_len_7(unsigned int ublk_data_len_7); +int iSetDEQC_ROOT_CRR_WEIGHT_CFG_deqc_crr_weight_cfg_ns(unsigned int udeqc_crr_weight_cfg_ns); +int iSetDEQC_ROOT_CRR_WEIGHT_CFG_deqc_crr_weight_cfg_cs(unsigned int udeqc_crr_weight_cfg_cs); +int iSetDEQC_WEIGHT_OFFSET_weight_offset(unsigned int uweight_offset); +int iSetDEQC_NMQ_EP_WEIGHT_nmq_ep_weight(unsigned int unmq_ep_weight); +int iSetDEQC_NFMQ_EP_WEIGHT_nfmq_ep_weight(unsigned int unfmq_ep_weight); +int iSetDEQC_NMQ_HOST_WEIGHT_nmq_host_weight(unsigned int unmq_host_weight); +int iSetDEQC_NFMQ_HOST_WEIGHT_nfmq_host_weight(unsigned int unfmq_host_weight); +int iSetDEQC_NMQ_HOST_SHAP_CFG_nmq_host_shap_cfg(unsigned int unmq_host_shap_cfg); +int iSetDEQC_NFMQ_HOST_SHAP_CFG_nfmq_host_shap_cfg(unsigned int unfmq_host_shap_cfg); +int iSetDEQC_SERV_SHAP_CFG_service_shap_cfg(unsigned int uservice_shap_cfg); +int iSetDEQC_ROOT_SHAP_CFG_root_shap_cfg(unsigned int uroot_shap_cfg); +int iSetDEQC_SHAP_BYPASS_CFG_deqc_ns_host_shap_byp_vld(unsigned int udeqc_ns_host_shap_byp_vld); +int iSetDEQC_SHAP_BYPASS_CFG_deqc_cs_host_shap_byp_vld(unsigned int udeqc_cs_host_shap_byp_vld); +int iSetDEQC_SHAP_BYPASS_CFG_deqc_serv_shap_byp_vld(unsigned int udeqc_serv_shap_byp_vld); +int iSetDEQC_SHAP_BYPASS_CFG_deqc_rt_shap_byp_vld(unsigned int udeqc_rt_shap_byp_vld); +int iSetDEQC_SPCOS_SHARE_RSC_XON_RSP_CFG_deqc_spcos_rsc_xon_resp_en(unsigned int udeqc_spcos_rsc_xon_resp_en); +int iSetDEQC_RH_XON_CFG_deqc_root_xon_cfg(unsigned int udeqc_root_xon_cfg); +int iSetDEQC_RH_XON_CFG_deqc_service_xon_cfg_nmq(unsigned int udeqc_service_xon_cfg_nmq); +int iSetDEQC_RH_XON_CFG_deqc_service_xon_cfg_nfmq(unsigned int udeqc_service_xon_cfg_nfmq); +int iSetDEQC_HOST_XON_CFG_NMQ_deqc_host_xon_cfg_nmq(unsigned int udeqc_host_xon_cfg_nmq); +int iSetDEQC_HOST_XON_CFG_NFMQ_deqc_host_xon_cfg_nfmq(unsigned int udeqc_host_xon_cfg_nfmq); +int iSetDEQC_EP_XON_CFG_NMQ_deqc_ep_xon_cfg_nmq(unsigned int udeqc_ep_xon_cfg_nmq); +int iSetDEQC_EP_XON_CFG_NFMQ_deqc_ep_xon_cfg_nfmq(unsigned int udeqc_ep_xon_cfg_nfmq); +int iSetDEQC_COS_XON_CFG_NMQ_deqc_cos_xon_cfg_nmq(unsigned int udeqc_cos_xon_cfg_nmq); +int iSetDEQC_COS_XON_CFG_NFMQ_deqc_cos_xon_cfg_nfmq(unsigned int udeqc_cos_xon_cfg_nfmq); +int iSetDEQC_ROOT_XON_ST_root_xon_st(unsigned int uroot_xon_st); +int iSetDEQC_NMQ_SERVICE_XON_ST_nmq_serve_xon_st(unsigned int unmq_serve_xon_st); +int iSetDEQC_NFMQ_SERVICE_XON_ST_nfmq_serve_xon_st(unsigned int unfmq_serve_xon_st); +int iSetDEQC_NMQ_HOST_XON_ST_nmq_host_xon_st(unsigned int unmq_host_xon_st); +int iSetDEQC_NFMQ_HOST_XON_ST_nfmq_host_xon_st(unsigned int unfmq_host_xon_st); +int iSetDEQC_NMQ_HOST_EP_XON_ST_nmq_host_ep_xon_st(unsigned int unmq_host_ep_xon_st); +int iSetDEQC_NFMQ_HOST_EP_XON_ST_nfmq_host_ep_xon_st(unsigned int unfmq_host_ep_xon_st); +int iSetDEQC_NMQ_HOST_SPASS_ST_nmq_host_spass_st(unsigned int unmq_host_spass_st); +int iSetDEQC_NFMQ_HOST_SHAP_PASS_ST_nfmq_host_spass_st(unsigned int unfmq_host_spass_st); +int iSetDEQC_FIFO_DFX_host_cs_shap_sch_fifo_dfx(unsigned int uhost_cs_shap_sch_fifo_dfx); +int iSetDEQC_FIFO_DFX_host_ns_shap_sch_fifo_dfx(unsigned int uhost_ns_shap_sch_fifo_dfx); +int iSetDEQC_FIFO_DFX_serv_shap_sch_fifo_dfx(unsigned int userv_shap_sch_fifo_dfx); +int iSetDEQC_FIFO_DFX_root_shap_sch_fifo_dfx(unsigned int uroot_shap_sch_fifo_dfx); +int iSetDEQC_NMQ_UP_PKT_CNT_deqc_nmq_up_pkt_cnt(unsigned int udeqc_nmq_up_pkt_cnt); +int iSetDEQC_NFMQ_UP_PKT_CNT_deqc_nfmq_up_pkt_cnt(unsigned int udeqc_nfmq_up_pkt_cnt); +int iSetDEQC_NMQ_DEQ_PKT_CNT_deqc_nmq_deq_pkt_cnt(unsigned int udeqc_nmq_deq_pkt_cnt); +int iSetDEQC_NFMQ_DEQ_PKT_CNT_deqc_nfmq_deq_pkt_cnt(unsigned int udeqc_nfmq_deq_pkt_cnt); +int iSetDEQC_NMQ_DEQ_CMD_CNT_deqc_nmq_deq_cmd_cnt(unsigned int udeqc_nmq_deq_cmd_cnt); +int iSetDEQC_NFMQ_DEQ_CMD_CNT_deqc_nfmq_deq_cmd_cnt(unsigned int udeqc_nfmq_deq_cmd_cnt); +int iSetDEQC_NFMQ_EMPT_SCH_CNT_deqc_nfmq_empt_sch_cnt(unsigned int udeqc_nfmq_empt_sch_cnt); +int iSetDEQC_NMQ_EMPT_SCH_CNT_deqc_nmq_empt_sch_cnt(unsigned int udeqc_nmq_empt_sch_cnt); +int iSetDEQC_ECC_1BIT_ERR_CNT_deqc_ecc_1bit_err_cnt(unsigned int udeqc_ecc_1bit_err_cnt); +int iSetDEQC_ECC_2BIT_ERR_CNT_deqc_ecc_2bit_err_cnt(unsigned int udeqc_ecc_2bit_err_cnt); +int iSetDEQC_SCH_MQ_DFX_CFG_deqc_sch_mq_dfx_cfg(unsigned int udeqc_sch_mq_dfx_cfg); +int iSetDEQC_SCH_MQ_DFX_CFG_deqc_sch_mq_qa_dfx_cfg(unsigned int udeqc_sch_mq_qa_dfx_cfg); +int iSetDEQC_SCH_MQ_DFX_CFG_deqc_sch_mq_dfx_cfg_vld(unsigned int udeqc_sch_mq_dfx_cfg_vld); +int iSetDEQC_SCH_MQ_DFX_UP_CNT_deqc_sch_mq_dfx_up_cnt(unsigned int udeqc_sch_mq_dfx_up_cnt); +int iSetDEQC_SCH_MQ_DFX_DEQ_CMD_CNT_deqc_sch_mq_dfx_deq_cmd_cnt(unsigned int udeqc_sch_mq_dfx_deq_cmd_cnt); +int iSetDEQC_SCH_MQ_DFX_DEQ_NUM_CNT_deqc_sch_mq_dfx_deq_num_cnt(unsigned int udeqc_sch_mq_dfx_deq_num_cnt); +int iSetDEQC_SCH_MQ_DFX_EMPT_SCH_CNT_deqc_sch_mq_dfx_empt_sch_cnt(unsigned int udeqc_sch_mq_dfx_empt_sch_cnt); +int iSetDEQC_NMQ_HOST_EP_COS_XON_ST_nmq_host_ep_cos_xon_st(unsigned int unmq_host_ep_cos_xon_st); +int iSetDEQC_NFMQ_HOST_EP_COS_XON_ST0_nfmq_host_ep_cos_xon_st(unsigned int unfmq_host_ep_cos_xon_st); + + +#endif // MQM_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_reg_offset.h new file mode 100644 index 000000000..04cb4aba9 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/mqm_reg_offset.h @@ -0,0 +1,3696 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : mqm_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:55:25 Create file +// ****************************************************************************** + +#ifndef MQM_REG_OFFSET_H +#define MQM_REG_OFFSET_H + +/* MQM_TOP Base address of Module's Register */ +#define CSR_MQM_TOP_BASE (0x2000) + +/* **************************************************************************** */ +/* MQM_TOP Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_TOP_MQM_EDITION_REG (CSR_MQM_TOP_BASE + 0x0) /* Version Register */ +#define CSR_MQM_TOP_MQM_INITCTAB_START_REG (CSR_MQM_TOP_BASE + 0x4) /* 配置表初始化使能寄存器 */ +#define CSR_MQM_TOP_MQM_INITCTAB_DONE_REG (CSR_MQM_TOP_BASE + 0x8) /* 配置表初始化状态寄存器 */ +#define CSR_MQM_TOP_MQM_CFG_OK_REG (CSR_MQM_TOP_BASE + 0xC) /* MQM 配置完成寄存器 */ +#define CSR_MQM_TOP_MQM_INITLOGIC_DONE_REG (CSR_MQM_TOP_BASE + 0x10) /* 芯片逻辑初始化状态寄存器 */ +#define CSR_MQM_TOP_MQM_TOP_INT_VECTOR_REG (CSR_MQM_TOP_BASE + 0x30) /* MQM Interrupt Vector Register */ +#define CSR_MQM_TOP_MQM_TOP_INT_REG (CSR_MQM_TOP_BASE + 0x34) /* MQM Interrupt Register */ +#define CSR_MQM_TOP_MQM_TOP_INT_EN_REG (CSR_MQM_TOP_BASE + 0x38) /* MQM Interrupt Mask Register */ +#define CSR_MQM_TOP_VF_FLUSH_DONE_INT_REG (CSR_MQM_TOP_BASE + 0x3C) /* VF FLUSH finish done Interrupt register. */ +#define CSR_MQM_TOP_MQM_RX_CNP_E0_ERR_INT_REG (CSR_MQM_TOP_BASE + 0x40) /* Receive Ring CNP E0 error int */ +#define CSR_MQM_TOP_MQM_RX_CNP_E1_ERR_INT_REG (CSR_MQM_TOP_BASE + 0x44) /* Receive Ring CNP E1 error int */ +#define CSR_MQM_TOP_MQM_TOP_FIFO_INT_REG (CSR_MQM_TOP_BASE + 0x48) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_TOP_MQM_TOP_FIFO_INT_MASK_REG \ + (CSR_MQM_TOP_BASE + 0x4C) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_TOP_USE_HOST_BITMAP_REG (CSR_MQM_TOP_BASE + 0x80) /* HOST使用指示寄存器 */ +#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB0_REG (CSR_MQM_TOP_BASE + 0x84) /* DB TYPE映射表0 */ +#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB1_REG (CSR_MQM_TOP_BASE + 0x88) /* DB TYPE映射表1 */ +#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB2_REG (CSR_MQM_TOP_BASE + 0x8C) /* DB TYPE映射表2 */ +#define CSR_MQM_TOP_DB_TYPE_MAPING_TAB3_REG (CSR_MQM_TOP_BASE + 0x90) /* DB TYPE映射表3 */ +#define CSR_MQM_TOP_MQM_CMQ_ENQ_MODE_CFG_REG (CSR_MQM_TOP_BASE + 0x94) /* MQM CMQ ENQ MODE CFG */ +#define CSR_MQM_TOP_MQM_MAX_DMA_CRDT_CFG_REG (CSR_MQM_TOP_BASE + 0x98) /* Config value for dma credit */ +#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_0_REG (CSR_MQM_TOP_BASE + 0x9C) /* MQM SOC QUEUE USE PF 31 To 0 CFG */ +#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_1_REG (CSR_MQM_TOP_BASE + 0xA0) /* MQM SOC QUEUE USE PF 31 To 0 CFG */ +#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_2_REG (CSR_MQM_TOP_BASE + 0xA4) /* MQM SOC QUEUE USE PF 31 To 0 CFG */ +#define CSR_MQM_TOP_MQM_SOC_USE_PF_CFG_3_REG (CSR_MQM_TOP_BASE + 0xA8) /* MQM SOC QUEUE USE PF 31 To 0 CFG */ +#define CSR_MQM_TOP_MQM_PF_CFG_REG (CSR_MQM_TOP_BASE + 0xAC) /* MQM PF CFG */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_CFG_REG (CSR_MQM_TOP_BASE + 0x100) /* VF FLUSH配置寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_0_REG (CSR_MQM_TOP_BASE + 0x104) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_1_REG (CSR_MQM_TOP_BASE + 0x108) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_2_REG (CSR_MQM_TOP_BASE + 0x10C) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_3_REG (CSR_MQM_TOP_BASE + 0x110) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_4_REG (CSR_MQM_TOP_BASE + 0x114) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_5_REG (CSR_MQM_TOP_BASE + 0x118) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_6_REG (CSR_MQM_TOP_BASE + 0x11C) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NMQ_ID_CFG_7_REG (CSR_MQM_TOP_BASE + 0x120) /* VF FLUSH NMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_0_REG (CSR_MQM_TOP_BASE + 0x124) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_1_REG (CSR_MQM_TOP_BASE + 0x128) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_2_REG (CSR_MQM_TOP_BASE + 0x12C) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_3_REG (CSR_MQM_TOP_BASE + 0x130) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_4_REG (CSR_MQM_TOP_BASE + 0x134) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_5_REG (CSR_MQM_TOP_BASE + 0x138) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_6_REG (CSR_MQM_TOP_BASE + 0x13C) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_NFMQ_ID_CFG_7_REG (CSR_MQM_TOP_BASE + 0x140) /* VF FLUSH NFMQ 对应配置ID寄存器 */ +#define CSR_MQM_TOP_VF_FLUSH_R_TXQ_NUM_REG \ + (CSR_MQM_TOP_BASE + 0x144) /* The number of Remote RDMA Read VF flush txqid */ +#define CSR_MQM_TOP_VF_FLUSH_R_TXQ_BADDR_REG \ + (CSR_MQM_TOP_BASE + 0x148) /* The base address of Remote RDMA Read VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_S_TXQ_NUM_REG (CSR_MQM_TOP_BASE + 0x14C) /* The number of Send Queue VF flush txqid */ +#define CSR_MQM_TOP_VF_FLUSH_S_TXQ_BADDR_REG (CSR_MQM_TOP_BASE + 0x150) /* The base address of Send Queue VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_F_TXQ_NUM_REG \ + (CSR_MQM_TOP_BASE + 0x154) /* The number of Filterable stateful RQ queue VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_F_TXQ_BADDR_REG \ + (CSR_MQM_TOP_BASE + 0x158) /* The base address of Filterable stateful RQ queue VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_U_TXQ_NUM_REG (CSR_MQM_TOP_BASE + 0x15C) /* The number of uCode CMQ VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_U_TXQ_BADDR_REG (CSR_MQM_TOP_BASE + 0x160) /* The base address of uCode CMQ VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_LNIC_SQ_TXQ_INFO_REG \ + (CSR_MQM_TOP_BASE + 0x164) /* The information of L2NIC SQ Queue VF flush */ +#define CSR_MQM_TOP_VF_FLUSH_LNIC_RQ_TXQ_INFO_REG \ + (CSR_MQM_TOP_BASE + 0x168) /* The information of L2NIC RQ Queue VF flush */ +#define CSR_MQM_TOP_MQM_VF_FLUSH_DONE_REG (CSR_MQM_TOP_BASE + 0x174) /* Record the status for flush when VF Flush */ +#define CSR_MQM_TOP_MQM_UNCRT_ERR_MASK_REG (CSR_MQM_TOP_BASE + 0x200) /* MQM Urgency Interrupt Mask Register。 */ +#define CSR_MQM_TOP_MQM_UNCRT_ERR_CLR_REG (CSR_MQM_TOP_BASE + 0x204) /* MQM Urgency Interrupt Clear Register。 */ +#define CSR_MQM_TOP_MQM_VF_COUNT_CFG_REG \ + (CSR_MQM_TOP_BASE + \ + 0x304) /* cfg vfid that mqm need statistics the number of doorbell which is belong to designated vfid */ +#define CSR_MQM_TOP_MQM_RX_DESIGNATE_VFID_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x308) /* Statics the number of doorbell which mqm received and belongs to the designate vfid \ + */ +#define CSR_MQM_TOP_MQM_FILT_DESIGNATE_VFID_CNT_REG \ + (CSR_MQM_TOP_BASE + \ + 0x30C) /* Statics the number of doorbell which filted by mqm and belongs to the designate vfid */ +#define CSR_MQM_TOP_MQM_TX_SM_DESIGNATE_VFID_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x310) /* Statics the number of doorbell which send to sm and belongs to the designate vfid */ +#define CSR_MQM_TOP_MQM_TX_QU_DESIGNATE_VFID_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x314) /* Statics the number of doorbell which send to qu and belongs to the designate vfid */ +#define CSR_MQM_TOP_MQM_RCV_TILE_API_OP_ERR_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x318) /* Statics the number of API from tile with opid err */ +#define CSR_MQM_TOP_MQM_RCV_TILE_FAST_CNP_API_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x31C) /* Statics the number of FAST CNP API from Tile */ +#define CSR_MQM_TOP_MQM_RCV_TILE_CNP_API_E0E1_CNT_REG \ + (CSR_MQM_TOP_BASE + 0x320) /* Statics the number of FAST CNP E0E1 API from Tile */ +#define CSR_MQM_TOP_MQM_ND_RS_RQST_CREDIT_REG \ + (CSR_MQM_TOP_BASE + 0x324) /* MQM node interface with Ring credit request cnt */ +#define CSR_MQM_TOP_MQM_TOP_FIFO_ST_REG (CSR_MQM_TOP_BASE + 0x328) /* MQM TOP fifo full and empt state */ + +/* MQM_ENQC Base address of Module's Register */ +#define CSR_MQM_ENQC_BASE (0x4000) + +/* **************************************************************************** */ +/* MQM_ENQC Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_ENQC_ENQC_RW_RSV0_REG (CSR_MQM_ENQC_BASE + 0x0) /* enqc rw reserved register 0 */ +#define CSR_MQM_ENQC_ENQC_RW_RSV1_REG (CSR_MQM_ENQC_BASE + 0x4) /* enqc rw reserved register 1 */ +#define CSR_MQM_ENQC_ENQC_RW_RSV2_REG (CSR_MQM_ENQC_BASE + 0x8) /* enqc rw reserved register 2 */ +#define CSR_MQM_ENQC_ENQC_RW_RSV3_REG (CSR_MQM_ENQC_BASE + 0xC) /* enqc rw reserved register 3 */ +#define CSR_MQM_ENQC_ENQC_INDRECT_CTRL_REG (CSR_MQM_ENQC_BASE + 0x10) /* ENQC Indirect access ctrl Register */ +#define CSR_MQM_ENQC_ENQC_INDRECT_TIMEOUT_REG (CSR_MQM_ENQC_BASE + 0x14) /* ENQC Indirect Access Timeout Register */ +#define CSR_MQM_ENQC_ENQC_INDRECT_DATA_0_REG (CSR_MQM_ENQC_BASE + 0x18) /* ENQC Indirect Access Data Register0 */ +#define CSR_MQM_ENQC_ENQC_INDRECT_DATA_1_REG (CSR_MQM_ENQC_BASE + 0x1C) /* ENQC Indirect Access Data Register1 */ +#define CSR_MQM_ENQC_ENQC_INT_VECTOR_REG (CSR_MQM_ENQC_BASE + 0x20) /* enqc int vector */ +#define CSR_MQM_ENQC_ENQC_INT_REG (CSR_MQM_ENQC_BASE + 0x24) /* enqc int */ +#define CSR_MQM_ENQC_ENQC_INT_EN_REG (CSR_MQM_ENQC_BASE + 0x28) /* enqc int mask */ +#define CSR_MQM_ENQC_ENQC_MEM_ECC_ERR0_REG (CSR_MQM_ENQC_BASE + 0x2C) /* RAM ECC ONE BIT ERR */ +#define CSR_MQM_ENQC_ENQC_MEM_ECC_ERR1_REG (CSR_MQM_ENQC_BASE + 0x30) /* RAM ECC TWO BIT ERR */ +#define CSR_MQM_ENQC_TABLE_RD_INVLD_INT_REG (CSR_MQM_ENQC_BASE + 0x34) /* table read invalid */ +#define CSR_MQM_ENQC_VFPF_TO_HOST_ID_INT_REG (CSR_MQM_ENQC_BASE + 0x38) /* VF or PF map to HOST ID err */ +#define CSR_MQM_ENQC_QU_ENQC_DB_IF_INT_REG (CSR_MQM_ENQC_BASE + 0x3C) /* QU to ENQC db interface err */ +#define CSR_MQM_ENQC_CPI_DISCARD_INT_REG (CSR_MQM_ENQC_BASE + 0x40) /* this int indicate cpi discard doorbell */ +#define CSR_MQM_ENQC_ENQC_FIFO_INT_REG (CSR_MQM_ENQC_BASE + 0x44) /* enqc fifo write overflow and read underflow */ +#define CSR_MQM_ENQC_ENQC_FIFO_INT_EN_REG \ + (CSR_MQM_ENQC_BASE + 0x48) /* enqc fifo write overflow mask and read overflow */ +#define CSR_MQM_ENQC_ENQC_QF_INT_REG (CSR_MQM_ENQC_BASE + 0x4C) /* enqc queue filter error int */ +#define CSR_MQM_ENQC_RX_RING_E0_ERR_INT_REG (CSR_MQM_ENQC_BASE + 0x50) /* Receive Ring E0 error int */ +#define CSR_MQM_ENQC_RX_RING_E1_ERR_INT_REG (CSR_MQM_ENQC_BASE + 0x54) /* Receive Ring E1 error int */ +#define CSR_MQM_ENQC_ENQC_TXQID_OVFL_VF_RANGE_INT_REG \ + (CSR_MQM_ENQC_BASE + 0x58) /* The int that filter doorbell's txqid overflow the range of VF */ +#define CSR_MQM_ENQC_ENQC_NONF_NUM_OVFL_THR_INT_REG \ + (CSR_MQM_ENQC_BASE + 0x5C) /* The int that The number of non-filter doorbell overflow the threshold */ +#define CSR_MQM_ENQC_ENQC_ERR_TYP_DB_INT_REG (CSR_MQM_ENQC_BASE + 0x60) /* The int that error type doorbell for mqm */ +#define CSR_MQM_ENQC_ENQC_MEM_ECC_REQ0_REG (CSR_MQM_ENQC_BASE + 0x80) /* ENQC memory ecc insert request Register0 */ +#define CSR_MQM_ENQC_ENQC_MEM_ECC_REQ1_REG (CSR_MQM_ENQC_BASE + 0x84) /* ENQC memory ecc insert request Register1 */ +#define CSR_MQM_ENQC_ENQC_QU_DB_IF_UNCRT_INT_EN_REG (CSR_MQM_ENQC_BASE + 0x88) /* qu to enqc uncorrect int enable */ +#define CSR_MQM_ENQC_ENQC_UNCRT_INT_EN_REG (CSR_MQM_ENQC_BASE + 0x8C) /* enqc uncorrect int enable */ +#define CSR_MQM_ENQC_ENQC_SENDQ_BASE_ADDR_REG \ + (CSR_MQM_ENQC_BASE + 0xB0) /* SQ TXQID filter base address in filter space */ +#define CSR_MQM_ENQC_ENQC_SENDQ_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xB4) /* SQ TXQID filter limite in filter space */ +#define CSR_MQM_ENQC_ENQC_TASKIO_BASE_ADDR_REG \ + (CSR_MQM_ENQC_BASE + 0xB8) /* TASKIO TXQID filter base address in filter space */ +#define CSR_MQM_ENQC_ENQC_TASKIO_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xBC) /* TASKIO TXQID filter limite in filter space */ +#define CSR_MQM_ENQC_ENQC_RDMA_BASE_ADDR_REG \ + (CSR_MQM_ENQC_BASE + 0xC0) /* RDMA TXQID filter base address in filter space */ +#define CSR_MQM_ENQC_ENQC_RDMA_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xC4) /* RDMA TXQID filter limite in filter space */ +#define CSR_MQM_ENQC_ENQC_FTXQID_BASE_ADDR_REG \ + (CSR_MQM_ENQC_BASE + 0xC8) /* RQ TXQID filter base address in filter space */ +#define CSR_MQM_ENQC_ENQC_FTXQID_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xCC) /* RQ TXQID filter limite in filter space */ +#define CSR_MQM_ENQC_ENQC_UTXQID_BASE_ADDR_REG \ + (CSR_MQM_ENQC_BASE + 0xD0) /* uCode TXQID filter base address in filter space */ +#define CSR_MQM_ENQC_ENQC_UTXQID_SCOPE_REG (CSR_MQM_ENQC_BASE + 0xD4) /* uCode TXQID filter limite in filter space */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_0_REG \ + (CSR_MQM_ENQC_BASE + 0xD8) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_1_REG \ + (CSR_MQM_ENQC_BASE + 0xDC) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_2_REG \ + (CSR_MQM_ENQC_BASE + 0xE0) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_3_REG \ + (CSR_MQM_ENQC_BASE + 0xE4) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_4_REG \ + (CSR_MQM_ENQC_BASE + 0xE8) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_5_REG \ + (CSR_MQM_ENQC_BASE + 0xEC) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_6_REG \ + (CSR_MQM_ENQC_BASE + 0xF0) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_BASE_LNIC_7_REG \ + (CSR_MQM_ENQC_BASE + 0xF4) /* soc pf0~7 filter base address for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_0_REG \ + (CSR_MQM_ENQC_BASE + 0xF8) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_1_REG \ + (CSR_MQM_ENQC_BASE + 0xFC) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_2_REG \ + (CSR_MQM_ENQC_BASE + 0x100) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_3_REG \ + (CSR_MQM_ENQC_BASE + 0x104) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_4_REG \ + (CSR_MQM_ENQC_BASE + 0x108) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_5_REG \ + (CSR_MQM_ENQC_BASE + 0x10C) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_6_REG \ + (CSR_MQM_ENQC_BASE + 0x110) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_SOC_PF_RANGE_LNIC_7_REG \ + (CSR_MQM_ENQC_BASE + 0x114) /* soc pf based TXQID range for l2nic sq and l2nic rq */ +#define CSR_MQM_ENQC_ENQC_HOST_LNIC_SQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x118) /* Host L2NIC SQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_HOST_LNIC_SQ_CNT_LIMIT_REG \ + (CSR_MQM_ENQC_BASE + 0x11C) /* Host L2NIC SQ PI store limite in pi store space */ +#define CSR_MQM_ENQC_ENQC_HOST_LNIC_RQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x120) /* Host L2NIC RQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_HOST_LNIC_RQ_CNT_LIMIT_REG \ + (CSR_MQM_ENQC_BASE + 0x124) /* Host L2NIC RQ PI store limite in pi store space */ +#define CSR_MQM_ENQC_ENQC_SQ_CNT_BADDR_REG (CSR_MQM_ENQC_BASE + 0x128) /* SQ PI store base address in pi store space \ + */ +#define CSR_MQM_ENQC_ENQC_SQ_CNT_LIMIT_REG (CSR_MQM_ENQC_BASE + 0x12C) /* SQ PI store limite in pi store space */ +#define CSR_MQM_ENQC_ENQC_HOST_CMQ_CNT_LIMIT_REG \ + (CSR_MQM_ENQC_BASE + 0x130) /* Host L2NIC CMQ PI store limite in pi store space */ +#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_0_REG (CSR_MQM_ENQC_BASE + 0x134) /* enqc pf range map to port */ +#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_1_REG (CSR_MQM_ENQC_BASE + 0x138) /* enqc pf range map to port */ +#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_2_REG (CSR_MQM_ENQC_BASE + 0x13C) /* enqc pf range map to port */ +#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_3_REG (CSR_MQM_ENQC_BASE + 0x140) /* enqc pf range map to port */ +#define CSR_MQM_ENQC_ENQC_PF_RANGE_PORTX_4_REG (CSR_MQM_ENQC_BASE + 0x144) /* enqc pf range map to port */ +#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_0_REG (CSR_MQM_ENQC_BASE + 0x148) /* enqc vf range map to port */ +#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_1_REG (CSR_MQM_ENQC_BASE + 0x14C) /* enqc vf range map to port */ +#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_2_REG (CSR_MQM_ENQC_BASE + 0x150) /* enqc vf range map to port */ +#define CSR_MQM_ENQC_ENQC_VF_RANGE_PORTX_3_REG (CSR_MQM_ENQC_BASE + 0x154) /* enqc vf range map to port */ +#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_0_REG (CSR_MQM_ENQC_BASE + 0x158) /* enqc lvf range map to port */ +#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_1_REG (CSR_MQM_ENQC_BASE + 0x15C) /* enqc lvf range map to port */ +#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_2_REG (CSR_MQM_ENQC_BASE + 0x160) /* enqc lvf range map to port */ +#define CSR_MQM_ENQC_ENQC_LVF_RANGE_PORTX_3_REG (CSR_MQM_ENQC_BASE + 0x164) /* enqc lvf range map to port */ +#define CSR_MQM_ENQC_ENQC_ENQC_CFG_REG (CSR_MQM_ENQC_BASE + 0x168) /* ENQC module configuration */ +#define CSR_MQM_ENQC_SOC_STATEFUL_DB_MAP_HID_REG (CSR_MQM_ENQC_BASE + 0x16C) /* soc stateful db map host id */ +#define CSR_MQM_ENQC_ENQC_IN_FIFO_GAP_REG (CSR_MQM_ENQC_BASE + 0x170) /* MQM input interface backpress threshold cfg \ + */ +#define CSR_MQM_ENQC_ENQC_EQM_PT_FIFO_GAP_REG \ + (CSR_MQM_ENQC_BASE + 0x174) /* MQM passthrough fifo and eqm enq fifo backpress threshold cfg */ +#define CSR_MQM_ENQC_ENQC_MRF_FIFO_BP_TH_REG \ + (CSR_MQM_ENQC_BASE + 0x178) /* MRF FIFO backpress threshold configuration */ +#define CSR_MQM_ENQC_ENQC_DURF_FIFO_BP_TH_REG \ + (CSR_MQM_ENQC_BASE + 0x17C) /* DURF FIFO backpress threshold configuration */ +#define CSR_MQM_ENQC_ENQC_WRR_WEIGHT0_REG (CSR_MQM_ENQC_BASE + 0x180) /* WRR weight configuration for SM/Tile/CPI */ +#define CSR_MQM_ENQC_ENQC_WRR_WEIGHT1_REG (CSR_MQM_ENQC_BASE + 0x184) /* WRR weight configuration */ +#define CSR_MQM_ENQC_ENQC_RX_DU_LEN_CLR_REG (CSR_MQM_ENQC_BASE + 0x188) /* Clr ENQC rx du length cnt */ +#define CSR_MQM_ENQC_ENQC_MEM_ECC_BYPASS_EN_REG (CSR_MQM_ENQC_BASE + 0x18C) /* ENQC RAM ECC BYPASS ctrl en */ +#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_ENQC_BASE + 0x190) /* ENQC RAM ctrl bus cfg reg0 */ +#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_ENQC_BASE + 0x194) /* ENQC RAM ctrl bus cfg reg1 */ +#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_ENQC_BASE + 0x198) /* ENQC RAM ctrl bus cfg reg2 */ +#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_ENQC_BASE + 0x19C) /* ENQC RAM ctrl bus cfg reg3 */ +#define CSR_MQM_ENQC_ENQC_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_ENQC_BASE + 0x1A0) /* ENQC RAM ctrl bus cfg reg4 */ +#define CSR_MQM_ENQC_ENQC_HOST_CMQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x1A4) /* HOST L2NIC CMQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_SOC_LNIC_SQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x1A8) /* SOC L2NIC SQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_SOC_LNIC_RQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x1AC) /* SOC L2NIC RQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_SOC_CMQ_CNT_BADDR_REG \ + (CSR_MQM_ENQC_BASE + 0x1B0) /* SOC L2NIC CMQ PI store base address in pi store space */ +#define CSR_MQM_ENQC_ENQC_SOC_DB_CNT_LIMIT_REG \ + (CSR_MQM_ENQC_BASE + 0x1B4) /* SOC L2NIC SQ/RQ/CMQ PI store limite in pi store space */ +#define CSR_MQM_ENQC_PASS_THROUGH_CFG_REG (CSR_MQM_ENQC_BASE + 0x1B8) /* Pass through function enable register. */ +#define CSR_MQM_ENQC_ENQC_ROOT_HOST_XON_STA_REG (CSR_MQM_ENQC_BASE + 0x1C0) /* HOST and Root level backpress status */ +#define CSR_MQM_ENQC_ENQC_HOSTEP_INMQ_XON_STA_REG (CSR_MQM_ENQC_BASE + 0x1C4) /* INMQ HOST EP level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_HOSTEP_INFMQ_XON_STA_REG \ + (CSR_MQM_ENQC_BASE + 0x1C8) /* INFMQ HOST EP level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_0_REG \ + (CSR_MQM_ENQC_BASE + 0x1CC) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_1_REG \ + (CSR_MQM_ENQC_BASE + 0x1D0) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_2_REG \ + (CSR_MQM_ENQC_BASE + 0x1D4) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_3_REG \ + (CSR_MQM_ENQC_BASE + 0x1D8) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_4_REG \ + (CSR_MQM_ENQC_BASE + 0x1DC) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_5_REG \ + (CSR_MQM_ENQC_BASE + 0x1E0) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_6_REG \ + (CSR_MQM_ENQC_BASE + 0x1E4) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INMQ_XON_STA_7_REG \ + (CSR_MQM_ENQC_BASE + 0x1E8) /* INMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_0_REG \ + (CSR_MQM_ENQC_BASE + 0x1EC) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_1_REG \ + (CSR_MQM_ENQC_BASE + 0x1F0) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_2_REG \ + (CSR_MQM_ENQC_BASE + 0x1F4) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_3_REG \ + (CSR_MQM_ENQC_BASE + 0x1F8) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_4_REG \ + (CSR_MQM_ENQC_BASE + 0x1FC) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_5_REG \ + (CSR_MQM_ENQC_BASE + 0x200) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_6_REG \ + (CSR_MQM_ENQC_BASE + 0x204) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_HEC_INFMQ_XON_STA_7_REG \ + (CSR_MQM_ENQC_BASE + 0x208) /* INFMQ Host_EP_COS level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_0_REG (CSR_MQM_ENQC_BASE + 0x20C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_1_REG (CSR_MQM_ENQC_BASE + 0x210) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_2_REG (CSR_MQM_ENQC_BASE + 0x214) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_3_REG (CSR_MQM_ENQC_BASE + 0x218) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_4_REG (CSR_MQM_ENQC_BASE + 0x21C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_5_REG (CSR_MQM_ENQC_BASE + 0x220) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_6_REG (CSR_MQM_ENQC_BASE + 0x224) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_7_REG (CSR_MQM_ENQC_BASE + 0x228) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_8_REG (CSR_MQM_ENQC_BASE + 0x22C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_9_REG (CSR_MQM_ENQC_BASE + 0x230) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_10_REG (CSR_MQM_ENQC_BASE + 0x234) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_11_REG (CSR_MQM_ENQC_BASE + 0x238) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_12_REG (CSR_MQM_ENQC_BASE + 0x23C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_13_REG (CSR_MQM_ENQC_BASE + 0x240) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_14_REG (CSR_MQM_ENQC_BASE + 0x244) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_15_REG (CSR_MQM_ENQC_BASE + 0x248) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_16_REG (CSR_MQM_ENQC_BASE + 0x24C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_17_REG (CSR_MQM_ENQC_BASE + 0x250) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_18_REG (CSR_MQM_ENQC_BASE + 0x254) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_19_REG (CSR_MQM_ENQC_BASE + 0x258) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_20_REG (CSR_MQM_ENQC_BASE + 0x25C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_21_REG (CSR_MQM_ENQC_BASE + 0x260) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_22_REG (CSR_MQM_ENQC_BASE + 0x264) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_23_REG (CSR_MQM_ENQC_BASE + 0x268) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_24_REG (CSR_MQM_ENQC_BASE + 0x26C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_25_REG (CSR_MQM_ENQC_BASE + 0x270) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_26_REG (CSR_MQM_ENQC_BASE + 0x274) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_27_REG (CSR_MQM_ENQC_BASE + 0x278) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_28_REG (CSR_MQM_ENQC_BASE + 0x27C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_29_REG (CSR_MQM_ENQC_BASE + 0x280) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_30_REG (CSR_MQM_ENQC_BASE + 0x284) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_31_REG (CSR_MQM_ENQC_BASE + 0x288) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_32_REG (CSR_MQM_ENQC_BASE + 0x28C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_33_REG (CSR_MQM_ENQC_BASE + 0x290) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_34_REG (CSR_MQM_ENQC_BASE + 0x294) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_35_REG (CSR_MQM_ENQC_BASE + 0x298) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_36_REG (CSR_MQM_ENQC_BASE + 0x29C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_37_REG (CSR_MQM_ENQC_BASE + 0x2A0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_38_REG (CSR_MQM_ENQC_BASE + 0x2A4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_39_REG (CSR_MQM_ENQC_BASE + 0x2A8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_40_REG (CSR_MQM_ENQC_BASE + 0x2AC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_41_REG (CSR_MQM_ENQC_BASE + 0x2B0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_42_REG (CSR_MQM_ENQC_BASE + 0x2B4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_43_REG (CSR_MQM_ENQC_BASE + 0x2B8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_44_REG (CSR_MQM_ENQC_BASE + 0x2BC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_45_REG (CSR_MQM_ENQC_BASE + 0x2C0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_46_REG (CSR_MQM_ENQC_BASE + 0x2C4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_47_REG (CSR_MQM_ENQC_BASE + 0x2C8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_48_REG (CSR_MQM_ENQC_BASE + 0x2CC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_49_REG (CSR_MQM_ENQC_BASE + 0x2D0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_50_REG (CSR_MQM_ENQC_BASE + 0x2D4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_51_REG (CSR_MQM_ENQC_BASE + 0x2D8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_52_REG (CSR_MQM_ENQC_BASE + 0x2DC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_53_REG (CSR_MQM_ENQC_BASE + 0x2E0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_54_REG (CSR_MQM_ENQC_BASE + 0x2E4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_55_REG (CSR_MQM_ENQC_BASE + 0x2E8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_56_REG (CSR_MQM_ENQC_BASE + 0x2EC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_57_REG (CSR_MQM_ENQC_BASE + 0x2F0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_58_REG (CSR_MQM_ENQC_BASE + 0x2F4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_59_REG (CSR_MQM_ENQC_BASE + 0x2F8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_60_REG (CSR_MQM_ENQC_BASE + 0x2FC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_61_REG (CSR_MQM_ENQC_BASE + 0x300) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_62_REG (CSR_MQM_ENQC_BASE + 0x304) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_63_REG (CSR_MQM_ENQC_BASE + 0x308) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_64_REG (CSR_MQM_ENQC_BASE + 0x30C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_65_REG (CSR_MQM_ENQC_BASE + 0x310) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_66_REG (CSR_MQM_ENQC_BASE + 0x314) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_67_REG (CSR_MQM_ENQC_BASE + 0x318) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_68_REG (CSR_MQM_ENQC_BASE + 0x31C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_69_REG (CSR_MQM_ENQC_BASE + 0x320) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_70_REG (CSR_MQM_ENQC_BASE + 0x324) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_71_REG (CSR_MQM_ENQC_BASE + 0x328) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_72_REG (CSR_MQM_ENQC_BASE + 0x32C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_73_REG (CSR_MQM_ENQC_BASE + 0x330) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_74_REG (CSR_MQM_ENQC_BASE + 0x334) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_75_REG (CSR_MQM_ENQC_BASE + 0x338) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_76_REG (CSR_MQM_ENQC_BASE + 0x33C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_77_REG (CSR_MQM_ENQC_BASE + 0x340) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_78_REG (CSR_MQM_ENQC_BASE + 0x344) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_79_REG (CSR_MQM_ENQC_BASE + 0x348) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_80_REG (CSR_MQM_ENQC_BASE + 0x34C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_81_REG (CSR_MQM_ENQC_BASE + 0x350) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_82_REG (CSR_MQM_ENQC_BASE + 0x354) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_83_REG (CSR_MQM_ENQC_BASE + 0x358) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_84_REG (CSR_MQM_ENQC_BASE + 0x35C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_85_REG (CSR_MQM_ENQC_BASE + 0x360) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_86_REG (CSR_MQM_ENQC_BASE + 0x364) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_87_REG (CSR_MQM_ENQC_BASE + 0x368) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_88_REG (CSR_MQM_ENQC_BASE + 0x36C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_89_REG (CSR_MQM_ENQC_BASE + 0x370) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_90_REG (CSR_MQM_ENQC_BASE + 0x374) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_91_REG (CSR_MQM_ENQC_BASE + 0x378) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_92_REG (CSR_MQM_ENQC_BASE + 0x37C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_93_REG (CSR_MQM_ENQC_BASE + 0x380) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_94_REG (CSR_MQM_ENQC_BASE + 0x384) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_95_REG (CSR_MQM_ENQC_BASE + 0x388) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_96_REG (CSR_MQM_ENQC_BASE + 0x38C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_97_REG (CSR_MQM_ENQC_BASE + 0x390) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_98_REG (CSR_MQM_ENQC_BASE + 0x394) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_99_REG (CSR_MQM_ENQC_BASE + 0x398) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_100_REG (CSR_MQM_ENQC_BASE + 0x39C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_101_REG (CSR_MQM_ENQC_BASE + 0x3A0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_102_REG (CSR_MQM_ENQC_BASE + 0x3A4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_103_REG (CSR_MQM_ENQC_BASE + 0x3A8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_104_REG (CSR_MQM_ENQC_BASE + 0x3AC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_105_REG (CSR_MQM_ENQC_BASE + 0x3B0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_106_REG (CSR_MQM_ENQC_BASE + 0x3B4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_107_REG (CSR_MQM_ENQC_BASE + 0x3B8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_108_REG (CSR_MQM_ENQC_BASE + 0x3BC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_109_REG (CSR_MQM_ENQC_BASE + 0x3C0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_110_REG (CSR_MQM_ENQC_BASE + 0x3C4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_111_REG (CSR_MQM_ENQC_BASE + 0x3C8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_112_REG (CSR_MQM_ENQC_BASE + 0x3CC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_113_REG (CSR_MQM_ENQC_BASE + 0x3D0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_114_REG (CSR_MQM_ENQC_BASE + 0x3D4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_115_REG (CSR_MQM_ENQC_BASE + 0x3D8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_116_REG (CSR_MQM_ENQC_BASE + 0x3DC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_117_REG (CSR_MQM_ENQC_BASE + 0x3E0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_118_REG (CSR_MQM_ENQC_BASE + 0x3E4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_119_REG (CSR_MQM_ENQC_BASE + 0x3E8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_120_REG (CSR_MQM_ENQC_BASE + 0x3EC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_121_REG (CSR_MQM_ENQC_BASE + 0x3F0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_122_REG (CSR_MQM_ENQC_BASE + 0x3F4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_123_REG (CSR_MQM_ENQC_BASE + 0x3F8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_124_REG (CSR_MQM_ENQC_BASE + 0x3FC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_125_REG (CSR_MQM_ENQC_BASE + 0x400) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_126_REG (CSR_MQM_ENQC_BASE + 0x404) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_127_REG (CSR_MQM_ENQC_BASE + 0x408) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_128_REG (CSR_MQM_ENQC_BASE + 0x40C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_129_REG (CSR_MQM_ENQC_BASE + 0x410) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_130_REG (CSR_MQM_ENQC_BASE + 0x414) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_131_REG (CSR_MQM_ENQC_BASE + 0x418) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_132_REG (CSR_MQM_ENQC_BASE + 0x41C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_133_REG (CSR_MQM_ENQC_BASE + 0x420) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_134_REG (CSR_MQM_ENQC_BASE + 0x424) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_135_REG (CSR_MQM_ENQC_BASE + 0x428) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_136_REG (CSR_MQM_ENQC_BASE + 0x42C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_137_REG (CSR_MQM_ENQC_BASE + 0x430) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_138_REG (CSR_MQM_ENQC_BASE + 0x434) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_139_REG (CSR_MQM_ENQC_BASE + 0x438) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_140_REG (CSR_MQM_ENQC_BASE + 0x43C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_141_REG (CSR_MQM_ENQC_BASE + 0x440) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_142_REG (CSR_MQM_ENQC_BASE + 0x444) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_143_REG (CSR_MQM_ENQC_BASE + 0x448) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_144_REG (CSR_MQM_ENQC_BASE + 0x44C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_145_REG (CSR_MQM_ENQC_BASE + 0x450) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_146_REG (CSR_MQM_ENQC_BASE + 0x454) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_147_REG (CSR_MQM_ENQC_BASE + 0x458) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_148_REG (CSR_MQM_ENQC_BASE + 0x45C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_149_REG (CSR_MQM_ENQC_BASE + 0x460) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_150_REG (CSR_MQM_ENQC_BASE + 0x464) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_151_REG (CSR_MQM_ENQC_BASE + 0x468) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_152_REG (CSR_MQM_ENQC_BASE + 0x46C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_153_REG (CSR_MQM_ENQC_BASE + 0x470) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_154_REG (CSR_MQM_ENQC_BASE + 0x474) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_155_REG (CSR_MQM_ENQC_BASE + 0x478) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_156_REG (CSR_MQM_ENQC_BASE + 0x47C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_157_REG (CSR_MQM_ENQC_BASE + 0x480) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_158_REG (CSR_MQM_ENQC_BASE + 0x484) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_159_REG (CSR_MQM_ENQC_BASE + 0x488) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_160_REG (CSR_MQM_ENQC_BASE + 0x48C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_161_REG (CSR_MQM_ENQC_BASE + 0x490) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_162_REG (CSR_MQM_ENQC_BASE + 0x494) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_163_REG (CSR_MQM_ENQC_BASE + 0x498) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_164_REG (CSR_MQM_ENQC_BASE + 0x49C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_165_REG (CSR_MQM_ENQC_BASE + 0x4A0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_166_REG (CSR_MQM_ENQC_BASE + 0x4A4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_167_REG (CSR_MQM_ENQC_BASE + 0x4A8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_168_REG (CSR_MQM_ENQC_BASE + 0x4AC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_169_REG (CSR_MQM_ENQC_BASE + 0x4B0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_170_REG (CSR_MQM_ENQC_BASE + 0x4B4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_171_REG (CSR_MQM_ENQC_BASE + 0x4B8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_172_REG (CSR_MQM_ENQC_BASE + 0x4BC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_173_REG (CSR_MQM_ENQC_BASE + 0x4C0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_174_REG (CSR_MQM_ENQC_BASE + 0x4C4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_175_REG (CSR_MQM_ENQC_BASE + 0x4C8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_176_REG (CSR_MQM_ENQC_BASE + 0x4CC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_177_REG (CSR_MQM_ENQC_BASE + 0x4D0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_178_REG (CSR_MQM_ENQC_BASE + 0x4D4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_179_REG (CSR_MQM_ENQC_BASE + 0x4D8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_180_REG (CSR_MQM_ENQC_BASE + 0x4DC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_181_REG (CSR_MQM_ENQC_BASE + 0x4E0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_182_REG (CSR_MQM_ENQC_BASE + 0x4E4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_183_REG (CSR_MQM_ENQC_BASE + 0x4E8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_184_REG (CSR_MQM_ENQC_BASE + 0x4EC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_185_REG (CSR_MQM_ENQC_BASE + 0x4F0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_186_REG (CSR_MQM_ENQC_BASE + 0x4F4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_187_REG (CSR_MQM_ENQC_BASE + 0x4F8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_188_REG (CSR_MQM_ENQC_BASE + 0x4FC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_189_REG (CSR_MQM_ENQC_BASE + 0x500) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_190_REG (CSR_MQM_ENQC_BASE + 0x504) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_191_REG (CSR_MQM_ENQC_BASE + 0x508) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_192_REG (CSR_MQM_ENQC_BASE + 0x50C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_193_REG (CSR_MQM_ENQC_BASE + 0x510) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_194_REG (CSR_MQM_ENQC_BASE + 0x514) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_195_REG (CSR_MQM_ENQC_BASE + 0x518) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_196_REG (CSR_MQM_ENQC_BASE + 0x51C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_197_REG (CSR_MQM_ENQC_BASE + 0x520) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_198_REG (CSR_MQM_ENQC_BASE + 0x524) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_199_REG (CSR_MQM_ENQC_BASE + 0x528) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_200_REG (CSR_MQM_ENQC_BASE + 0x52C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_201_REG (CSR_MQM_ENQC_BASE + 0x530) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_202_REG (CSR_MQM_ENQC_BASE + 0x534) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_203_REG (CSR_MQM_ENQC_BASE + 0x538) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_204_REG (CSR_MQM_ENQC_BASE + 0x53C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_205_REG (CSR_MQM_ENQC_BASE + 0x540) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_206_REG (CSR_MQM_ENQC_BASE + 0x544) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_207_REG (CSR_MQM_ENQC_BASE + 0x548) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_208_REG (CSR_MQM_ENQC_BASE + 0x54C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_209_REG (CSR_MQM_ENQC_BASE + 0x550) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_210_REG (CSR_MQM_ENQC_BASE + 0x554) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_211_REG (CSR_MQM_ENQC_BASE + 0x558) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_212_REG (CSR_MQM_ENQC_BASE + 0x55C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_213_REG (CSR_MQM_ENQC_BASE + 0x560) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_214_REG (CSR_MQM_ENQC_BASE + 0x564) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_215_REG (CSR_MQM_ENQC_BASE + 0x568) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_216_REG (CSR_MQM_ENQC_BASE + 0x56C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_217_REG (CSR_MQM_ENQC_BASE + 0x570) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_218_REG (CSR_MQM_ENQC_BASE + 0x574) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_219_REG (CSR_MQM_ENQC_BASE + 0x578) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_220_REG (CSR_MQM_ENQC_BASE + 0x57C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_221_REG (CSR_MQM_ENQC_BASE + 0x580) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_222_REG (CSR_MQM_ENQC_BASE + 0x584) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_223_REG (CSR_MQM_ENQC_BASE + 0x588) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_224_REG (CSR_MQM_ENQC_BASE + 0x58C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_225_REG (CSR_MQM_ENQC_BASE + 0x590) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_226_REG (CSR_MQM_ENQC_BASE + 0x594) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_227_REG (CSR_MQM_ENQC_BASE + 0x598) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_228_REG (CSR_MQM_ENQC_BASE + 0x59C) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_229_REG (CSR_MQM_ENQC_BASE + 0x5A0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_230_REG (CSR_MQM_ENQC_BASE + 0x5A4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_231_REG (CSR_MQM_ENQC_BASE + 0x5A8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_232_REG (CSR_MQM_ENQC_BASE + 0x5AC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_233_REG (CSR_MQM_ENQC_BASE + 0x5B0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_234_REG (CSR_MQM_ENQC_BASE + 0x5B4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_235_REG (CSR_MQM_ENQC_BASE + 0x5B8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_236_REG (CSR_MQM_ENQC_BASE + 0x5BC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_237_REG (CSR_MQM_ENQC_BASE + 0x5C0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_238_REG (CSR_MQM_ENQC_BASE + 0x5C4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_239_REG (CSR_MQM_ENQC_BASE + 0x5C8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_240_REG (CSR_MQM_ENQC_BASE + 0x5CC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_241_REG (CSR_MQM_ENQC_BASE + 0x5D0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_242_REG (CSR_MQM_ENQC_BASE + 0x5D4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_243_REG (CSR_MQM_ENQC_BASE + 0x5D8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_244_REG (CSR_MQM_ENQC_BASE + 0x5DC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_245_REG (CSR_MQM_ENQC_BASE + 0x5E0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_246_REG (CSR_MQM_ENQC_BASE + 0x5E4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_247_REG (CSR_MQM_ENQC_BASE + 0x5E8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_248_REG (CSR_MQM_ENQC_BASE + 0x5EC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_249_REG (CSR_MQM_ENQC_BASE + 0x5F0) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_250_REG (CSR_MQM_ENQC_BASE + 0x5F4) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_251_REG (CSR_MQM_ENQC_BASE + 0x5F8) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_252_REG (CSR_MQM_ENQC_BASE + 0x5FC) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_253_REG (CSR_MQM_ENQC_BASE + 0x600) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_254_REG (CSR_MQM_ENQC_BASE + 0x604) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INMQ_XON_STA_255_REG (CSR_MQM_ENQC_BASE + 0x608) /* INMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_0_REG (CSR_MQM_ENQC_BASE + 0x60C) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_1_REG (CSR_MQM_ENQC_BASE + 0x610) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_2_REG (CSR_MQM_ENQC_BASE + 0x614) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_3_REG (CSR_MQM_ENQC_BASE + 0x618) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_4_REG (CSR_MQM_ENQC_BASE + 0x61C) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_5_REG (CSR_MQM_ENQC_BASE + 0x620) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_6_REG (CSR_MQM_ENQC_BASE + 0x624) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_7_REG (CSR_MQM_ENQC_BASE + 0x628) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_8_REG (CSR_MQM_ENQC_BASE + 0x62C) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_9_REG (CSR_MQM_ENQC_BASE + 0x630) /* INFMQ Queue level backpress status */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_10_REG (CSR_MQM_ENQC_BASE + 0x634) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_11_REG (CSR_MQM_ENQC_BASE + 0x638) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_12_REG (CSR_MQM_ENQC_BASE + 0x63C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_13_REG (CSR_MQM_ENQC_BASE + 0x640) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_14_REG (CSR_MQM_ENQC_BASE + 0x644) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_15_REG (CSR_MQM_ENQC_BASE + 0x648) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_16_REG (CSR_MQM_ENQC_BASE + 0x64C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_17_REG (CSR_MQM_ENQC_BASE + 0x650) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_18_REG (CSR_MQM_ENQC_BASE + 0x654) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_19_REG (CSR_MQM_ENQC_BASE + 0x658) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_20_REG (CSR_MQM_ENQC_BASE + 0x65C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_21_REG (CSR_MQM_ENQC_BASE + 0x660) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_22_REG (CSR_MQM_ENQC_BASE + 0x664) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_23_REG (CSR_MQM_ENQC_BASE + 0x668) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_24_REG (CSR_MQM_ENQC_BASE + 0x66C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_25_REG (CSR_MQM_ENQC_BASE + 0x670) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_26_REG (CSR_MQM_ENQC_BASE + 0x674) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_27_REG (CSR_MQM_ENQC_BASE + 0x678) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_28_REG (CSR_MQM_ENQC_BASE + 0x67C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_29_REG (CSR_MQM_ENQC_BASE + 0x680) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_30_REG (CSR_MQM_ENQC_BASE + 0x684) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_31_REG (CSR_MQM_ENQC_BASE + 0x688) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_32_REG (CSR_MQM_ENQC_BASE + 0x68C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_33_REG (CSR_MQM_ENQC_BASE + 0x690) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_34_REG (CSR_MQM_ENQC_BASE + 0x694) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_35_REG (CSR_MQM_ENQC_BASE + 0x698) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_36_REG (CSR_MQM_ENQC_BASE + 0x69C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_37_REG (CSR_MQM_ENQC_BASE + 0x6A0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_38_REG (CSR_MQM_ENQC_BASE + 0x6A4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_39_REG (CSR_MQM_ENQC_BASE + 0x6A8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_40_REG (CSR_MQM_ENQC_BASE + 0x6AC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_41_REG (CSR_MQM_ENQC_BASE + 0x6B0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_42_REG (CSR_MQM_ENQC_BASE + 0x6B4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_43_REG (CSR_MQM_ENQC_BASE + 0x6B8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_44_REG (CSR_MQM_ENQC_BASE + 0x6BC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_45_REG (CSR_MQM_ENQC_BASE + 0x6C0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_46_REG (CSR_MQM_ENQC_BASE + 0x6C4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_47_REG (CSR_MQM_ENQC_BASE + 0x6C8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_48_REG (CSR_MQM_ENQC_BASE + 0x6CC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_49_REG (CSR_MQM_ENQC_BASE + 0x6D0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_50_REG (CSR_MQM_ENQC_BASE + 0x6D4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_51_REG (CSR_MQM_ENQC_BASE + 0x6D8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_52_REG (CSR_MQM_ENQC_BASE + 0x6DC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_53_REG (CSR_MQM_ENQC_BASE + 0x6E0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_54_REG (CSR_MQM_ENQC_BASE + 0x6E4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_55_REG (CSR_MQM_ENQC_BASE + 0x6E8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_56_REG (CSR_MQM_ENQC_BASE + 0x6EC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_57_REG (CSR_MQM_ENQC_BASE + 0x6F0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_58_REG (CSR_MQM_ENQC_BASE + 0x6F4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_59_REG (CSR_MQM_ENQC_BASE + 0x6F8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_60_REG (CSR_MQM_ENQC_BASE + 0x6FC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_61_REG (CSR_MQM_ENQC_BASE + 0x700) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_62_REG (CSR_MQM_ENQC_BASE + 0x704) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_63_REG (CSR_MQM_ENQC_BASE + 0x708) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_64_REG (CSR_MQM_ENQC_BASE + 0x70C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_65_REG (CSR_MQM_ENQC_BASE + 0x710) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_66_REG (CSR_MQM_ENQC_BASE + 0x714) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_67_REG (CSR_MQM_ENQC_BASE + 0x718) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_68_REG (CSR_MQM_ENQC_BASE + 0x71C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_69_REG (CSR_MQM_ENQC_BASE + 0x720) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_70_REG (CSR_MQM_ENQC_BASE + 0x724) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_71_REG (CSR_MQM_ENQC_BASE + 0x728) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_72_REG (CSR_MQM_ENQC_BASE + 0x72C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_73_REG (CSR_MQM_ENQC_BASE + 0x730) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_74_REG (CSR_MQM_ENQC_BASE + 0x734) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_75_REG (CSR_MQM_ENQC_BASE + 0x738) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_76_REG (CSR_MQM_ENQC_BASE + 0x73C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_77_REG (CSR_MQM_ENQC_BASE + 0x740) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_78_REG (CSR_MQM_ENQC_BASE + 0x744) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_79_REG (CSR_MQM_ENQC_BASE + 0x748) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_80_REG (CSR_MQM_ENQC_BASE + 0x74C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_81_REG (CSR_MQM_ENQC_BASE + 0x750) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_82_REG (CSR_MQM_ENQC_BASE + 0x754) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_83_REG (CSR_MQM_ENQC_BASE + 0x758) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_84_REG (CSR_MQM_ENQC_BASE + 0x75C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_85_REG (CSR_MQM_ENQC_BASE + 0x760) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_86_REG (CSR_MQM_ENQC_BASE + 0x764) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_87_REG (CSR_MQM_ENQC_BASE + 0x768) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_88_REG (CSR_MQM_ENQC_BASE + 0x76C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_89_REG (CSR_MQM_ENQC_BASE + 0x770) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_90_REG (CSR_MQM_ENQC_BASE + 0x774) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_91_REG (CSR_MQM_ENQC_BASE + 0x778) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_92_REG (CSR_MQM_ENQC_BASE + 0x77C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_93_REG (CSR_MQM_ENQC_BASE + 0x780) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_94_REG (CSR_MQM_ENQC_BASE + 0x784) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_95_REG (CSR_MQM_ENQC_BASE + 0x788) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_96_REG (CSR_MQM_ENQC_BASE + 0x78C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_97_REG (CSR_MQM_ENQC_BASE + 0x790) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_98_REG (CSR_MQM_ENQC_BASE + 0x794) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_99_REG (CSR_MQM_ENQC_BASE + 0x798) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_100_REG (CSR_MQM_ENQC_BASE + 0x79C) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_101_REG (CSR_MQM_ENQC_BASE + 0x7A0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_102_REG (CSR_MQM_ENQC_BASE + 0x7A4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_103_REG (CSR_MQM_ENQC_BASE + 0x7A8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_104_REG (CSR_MQM_ENQC_BASE + 0x7AC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_105_REG (CSR_MQM_ENQC_BASE + 0x7B0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_106_REG (CSR_MQM_ENQC_BASE + 0x7B4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_107_REG (CSR_MQM_ENQC_BASE + 0x7B8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_108_REG (CSR_MQM_ENQC_BASE + 0x7BC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_109_REG (CSR_MQM_ENQC_BASE + 0x7C0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_110_REG (CSR_MQM_ENQC_BASE + 0x7C4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_111_REG (CSR_MQM_ENQC_BASE + 0x7C8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_112_REG (CSR_MQM_ENQC_BASE + 0x7CC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_113_REG (CSR_MQM_ENQC_BASE + 0x7D0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_114_REG (CSR_MQM_ENQC_BASE + 0x7D4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_115_REG (CSR_MQM_ENQC_BASE + 0x7D8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_116_REG (CSR_MQM_ENQC_BASE + 0x7DC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_117_REG (CSR_MQM_ENQC_BASE + 0x7E0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_118_REG (CSR_MQM_ENQC_BASE + 0x7E4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_119_REG (CSR_MQM_ENQC_BASE + 0x7E8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_120_REG (CSR_MQM_ENQC_BASE + 0x7EC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_121_REG (CSR_MQM_ENQC_BASE + 0x7F0) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_122_REG (CSR_MQM_ENQC_BASE + 0x7F4) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_123_REG (CSR_MQM_ENQC_BASE + 0x7F8) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_124_REG (CSR_MQM_ENQC_BASE + 0x7FC) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_125_REG (CSR_MQM_ENQC_BASE + 0x800) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_126_REG (CSR_MQM_ENQC_BASE + 0x804) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_QUE_INFMQ_XON_STA_127_REG (CSR_MQM_ENQC_BASE + 0x808) /* INFMQ Queue level backpress status \ + */ +#define CSR_MQM_ENQC_ENQC_FLUSH_QF_EMQCNT_DONE_REG (CSR_MQM_ENQC_BASE + 0x80C) /* enqc flush qf done and emq cnt done \ + */ +#define CSR_MQM_ENQC_ENQC_ECC_1BIT_ERR_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x810) /* statistics counter of ENQC memory ECC 1bit ERR */ +#define CSR_MQM_ENQC_ENQC_ECC_2BIT_ERR_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x814) /* statistics counter of ENQC memory ECC 2bit ERR */ +#define CSR_MQM_ENQC_ENQC_RX_DU_PACKET_REG \ + (CSR_MQM_ENQC_BASE + 0x830) /* statistics of the number of delay-update packet received by mqm */ +#define CSR_MQM_ENQC_ENQC_RX_DU_LENGTH_REG \ + (CSR_MQM_ENQC_BASE + 0x834) /* statistics of the length that delay-update packet received by MQM */ +#define CSR_MQM_ENQC_CPI_IN_EMQCNT_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x838) /* the status of cpi input fifo */ +#define CSR_MQM_ENQC_SM_IN_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x83C) /* the status of sm input fifo */ +#define CSR_MQM_ENQC_TILE_QU_IN_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x840) /* the status of tile and qu input fifo */ +#define CSR_MQM_ENQC_ENQC_MRF_DU_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x844) /* the status of message receive fifo */ +#define CSR_MQM_ENQC_ENQC_PASSTHRU_FIFO_STATUS_REG (CSR_MQM_ENQC_BASE + 0x848) /* enqc passthrough fifo status */ +#define CSR_MQM_ENQC_ENQC_INPUT_BP_REG (CSR_MQM_ENQC_BASE + 0x84C) /* the backpress enqc to cpi doorbell interface */ +#define CSR_MQM_ENQC_ENQC_EQM_QD_CNT_REG (CSR_MQM_ENQC_BASE + 0x850) /* EQM QD cnt */ +#define CSR_MQM_ENQC_ENQC_RX_CPI_PKT_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x854) /* statistics of the number of doorbell receive from CPI */ +#define CSR_MQM_ENQC_ENQC_RX_SM_PKT_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x858) /* statistics of the number of doorbell receive from SM */ +#define CSR_MQM_ENQC_ENQC_RX_TILE_PKT_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x85C) /* statistics of the number of doorbell receive from Tile */ +#define CSR_MQM_ENQC_ENQC_RX_QU_PKT_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x860) /* statistics of the number of doorbell receive from QU */ +#define CSR_MQM_ENQC_ENQC_DIS_CPI_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x864) /* statistics of the number of doorbell discard by mqm which come from CPI */ +#define CSR_MQM_ENQC_ENQC_RX_RING_ERR_DB_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x868) /* statistics of the number of doorbell which is ring error */ +#define CSR_MQM_ENQC_ENQC_ENQ_IQM_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x86C) /* statistics of the number of doobell en-queue to IQM */ +#define CSR_MQM_ENQC_ENQC_ENQ_EQM_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x870) /* statistics of the number of doorbell en-queue to EQM */ +#define CSR_MQM_ENQC_ENQC_FILTERD_DB_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x874) /* statistics of the number of doorbell which is filterd by queue filter function */ +#define CSR_MQM_ENQC_ENQC_RX_SM_CP_SGE_CRDT_REG (CSR_MQM_ENQC_BASE + 0x878) /* enqc rx sm cp sge comp crdt cnt */ +#define CSR_MQM_ENQC_ENQC_RX_SM_DP_SGE_CRDT_REG (CSR_MQM_ENQC_BASE + 0x87C) /* enqc rx sm dp sge comp crdt cnt */ +#define CSR_MQM_ENQC_ENQC_RX_SM_CP_DATA_CRDT_REG (CSR_MQM_ENQC_BASE + 0x880) /* enqc rx sm cp comp data crdt cnt */ +#define CSR_MQM_ENQC_ENQC_RX_SM_DP_DATA_CRDT_REG (CSR_MQM_ENQC_BASE + 0x884) /* enqc rx sm dp comp data crdt cnt */ +#define CSR_MQM_ENQC_ENQC_RX_DP_NOFL_DB_REG (CSR_MQM_ENQC_BASE + 0x888) /* enqc rx dp nonfilter db cnt */ +#define CSR_MQM_ENQC_DB_OVFL_VF_RANGE_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x88C) /* Statics the number of doorbell's txqid overflow range of VF */ +#define CSR_MQM_ENQC_NONF_DB_NUM_OVFL_THR_CNT_REG \ + (CSR_MQM_ENQC_BASE + 0x890) /* Statics the number of non-filter doorbell overflow threshold of VF */ +#define CSR_MQM_ENQC_MQM_ERR_TYP_DB_CNT_REG (CSR_MQM_ENQC_BASE + 0x894) /* Static the number of error type doorbell */ +#define CSR_MQM_ENQC_PASS_THROUGH_STA_REG (CSR_MQM_ENQC_BASE + 0x898) /* Pass through function status register. */ + +/* MQM_BRM Base address of Module's Register */ +#define CSR_MQM_BRM_BASE (0x6000) + +/* **************************************************************************** */ +/* MQM_BRM Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_BRM_BRM_RW_RSV0_REG (CSR_MQM_BRM_BASE + 0x0) /* brm rw reserved register 0 */ +#define CSR_MQM_BRM_BRM_RW_RSV1_REG (CSR_MQM_BRM_BASE + 0x4) /* brm rw reserved register 1 */ +#define CSR_MQM_BRM_BRM_RW_RSV2_REG (CSR_MQM_BRM_BASE + 0x8) /* brm rw reserved register 2 */ +#define CSR_MQM_BRM_BRM_RW_RSV3_REG (CSR_MQM_BRM_BASE + 0xC) /* brm rw reserved register 3 */ +#define CSR_MQM_BRM_BRM_INDRECT_CTRL_REG (CSR_MQM_BRM_BASE + 0x10) /* BRM Indirect access ctrl Register。 */ +#define CSR_MQM_BRM_BRM_INDRECT_TIMEOUT_REG (CSR_MQM_BRM_BASE + 0x14) /* BRM Indirect Access Timeout Register。 */ +#define CSR_MQM_BRM_BRM_INDRECT_DATA_0_REG (CSR_MQM_BRM_BASE + 0x18) /* BRM Indirect Access Data Register0 */ +#define CSR_MQM_BRM_BRM_INDRECT_DATA_1_REG (CSR_MQM_BRM_BASE + 0x1C) /* BRM Indirect Access Data Register1 */ +#define CSR_MQM_BRM_BRM_INT_VECTOR_REG (CSR_MQM_BRM_BASE + 0x20) /* brm int vector */ +#define CSR_MQM_BRM_BRM_INT_REG (CSR_MQM_BRM_BASE + 0x24) /* brm int */ +#define CSR_MQM_BRM_BRM_INT_EN_REG (CSR_MQM_BRM_BASE + 0x28) /* brm int enable */ +#define CSR_MQM_BRM_BRM_MEM_ECC0_REG (CSR_MQM_BRM_BASE + 0x2C) /* RAM ECC ONE BIT ERR */ +#define CSR_MQM_BRM_BRM_MEM_ECC1_REG (CSR_MQM_BRM_BASE + 0x30) /* RAM ECC TWO BIT ERR */ +#define CSR_MQM_BRM_BRM_DB_FLT_ADDR_OVFL_INT_REG \ + (CSR_MQM_BRM_BASE + 0x34) /* BRM Doorbell Fliter Address Overflow Int */ +#define CSR_MQM_BRM_BRM_CNT_ADDR_OVFL_INT_REG (CSR_MQM_BRM_BASE + 0x38) /* BRM PI Store Address Overflow cfg Int */ +#define CSR_MQM_BRM_BRM_ATT_CNT_MEM_ECC_REQ_REG \ + (CSR_MQM_BRM_BASE + 0x50) /* BRM PI/ATT memory ecc insert request Register */ +#define CSR_MQM_BRM_BRM_QF_QD_MEM_ECC_REQ_REG \ + (CSR_MQM_BRM_BASE + 0x54) /* BRM QF/QD memory ecc insert request Register */ +#define CSR_MQM_BRM_BRM_QUE_FILT_SPA_REG \ + (CSR_MQM_BRM_BASE + 0x80) /* the space of queue filter and queue description cfg */ +#define CSR_MQM_BRM_BRM_ATT_SIZE_REG \ + (CSR_MQM_BRM_BASE + 0x84) /* the space of GPA address translation and PI store space cfg */ +#define CSR_MQM_BRM_BRM_MEM_ECC_BYPASS_EN_REG (CSR_MQM_BRM_BASE + 0x88) /* BRM RAM ECC BYPASS ctrl en */ +#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_BRM_BASE + 0x8C) /* BRM RAM ctrl bus cfg reg0 */ +#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_BRM_BASE + 0x90) /* BRM RAM ctrl bus cfg reg1 */ +#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_BRM_BASE + 0x94) /* BRM RAM ctrl bus cfg reg2 */ +#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_BRM_BASE + 0x98) /* BRM RAM ctrl bus cfg reg3 */ +#define CSR_MQM_BRM_BRM_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_BRM_BASE + 0x9C) /* BRM RAM ctrl bus cfg reg4 */ +#define CSR_MQM_BRM_BRM_ECC_1BIT_ERR_CNT_REG \ + (CSR_MQM_BRM_BASE + 0xB0) /* statistics counter of BRM memory ECC 1bit ERR */ +#define CSR_MQM_BRM_BRM_ECC_2BIT_ERR_CNT_REG \ + (CSR_MQM_BRM_BASE + 0xB4) /* statistics counter of BRM memory ECC 2bit ERR */ + +/* MQM_IQM Base address of Module's Register */ +#define CSR_MQM_IQM_BASE (0x8000) + +/* **************************************************************************** */ +/* MQM_IQM Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_IQM_IQM_RW_RSV0_REG (CSR_MQM_IQM_BASE + 0x0) /* iqm rw reserved register 0 */ +#define CSR_MQM_IQM_IQM_RW_RSV1_REG (CSR_MQM_IQM_BASE + 0x4) /* iqm rw reserved register 1 */ +#define CSR_MQM_IQM_IQM_RW_RSV2_REG (CSR_MQM_IQM_BASE + 0x8) /* iqm rw reserved register 2 */ +#define CSR_MQM_IQM_IQM_RW_RSV3_REG (CSR_MQM_IQM_BASE + 0xC) /* iqm rw reserved register 3 */ +#define CSR_MQM_IQM_IQM_INDRECT_CTRL_REG (CSR_MQM_IQM_BASE + 0x10) /* IQM Indirect access ctrl Register。 */ +#define CSR_MQM_IQM_IQM_INDRECT_TIMEOUT_REG (CSR_MQM_IQM_BASE + 0x14) /* IQM Indirect Access Timeout Register。 */ +#define CSR_MQM_IQM_IQM_INDRECT_DATA_0_REG (CSR_MQM_IQM_BASE + 0x18) /* IQM Indirect Access Data Register0 */ +#define CSR_MQM_IQM_IQM_INDRECT_DATA_1_REG (CSR_MQM_IQM_BASE + 0x1C) /* IQM Indirect Access Data Register1 */ +#define CSR_MQM_IQM_IQM_INT_VECTOR_REG (CSR_MQM_IQM_BASE + 0x20) /* iqm int vector */ +#define CSR_MQM_IQM_IQM_INT_REG (CSR_MQM_IQM_BASE + 0x24) /* iqm int */ +#define CSR_MQM_IQM_IQM_INT_EN_REG (CSR_MQM_IQM_BASE + 0x28) /* iqm int enable */ +#define CSR_MQM_IQM_IQM_MEM_ECC0_REG (CSR_MQM_IQM_BASE + 0x2C) /* RAM ECC ONE BIT ERR */ +#define CSR_MQM_IQM_IQM_MEM_ECC1_REG (CSR_MQM_IQM_BASE + 0x30) /* RAM ECC TWO BIT ERR */ +#define CSR_MQM_IQM_IQM_AGING_INT_REG (CSR_MQM_IQM_BASE + 0x34) /* iqm aging int */ +#define CSR_MQM_IQM_IQM_CMQ_DEQ_EMPTY_INT_REG (CSR_MQM_IQM_BASE + 0x38) /* iqm cmq link list deq emtpy int */ +#define CSR_MQM_IQM_IQM_FIFO_WR_OVFL_INT_REG (CSR_MQM_IQM_BASE + 0x3C) /* iqm fifo write overflow int */ +#define CSR_MQM_IQM_IQM_FIFO_RD_UDFL_INT_REG (CSR_MQM_IQM_BASE + 0x40) /* iqm fifo read underflow int */ +#define CSR_MQM_IQM_IQM_FREE_RSC_BMP_OVERFLOW_INT_REG \ + (CSR_MQM_IQM_BASE + 0x44) /* iqm free resource bitmap ovfl int err */ +#define CSR_MQM_IQM_IQM_CLL_DEQ_EMPTY_INT_REG (CSR_MQM_IQM_BASE + 0x48) /* iqm nmq/nfmq chunk link list deq emtpy int \ + */ +#define CSR_MQM_IQM_IQM_UXMQ_DEQ_EMPTY_INT_REG (CSR_MQM_IQM_BASE + 0x4C) /* iqm unmq or ucmq link list deq empty int \ + */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ1_REG (CSR_MQM_IQM_BASE + 0x50) /* IQM FIFO INT REQ1 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ2_REG (CSR_MQM_IQM_BASE + 0x54) /* IQM FIFO INT REQ2 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ3_REG (CSR_MQM_IQM_BASE + 0x58) /* IQM FIFO INT REQ3 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ4_REG (CSR_MQM_IQM_BASE + 0x5C) /* IQM FIFO INT REQ4 */ +#define CSR_MQM_IQM_IQM_MEM_ECC_REQ0_REG (CSR_MQM_IQM_BASE + 0x60) /* IQM memory ecc insert request Register0 */ +#define CSR_MQM_IQM_IQM_MEM_ECC_REQ1_REG (CSR_MQM_IQM_BASE + 0x64) /* IQM memory ecc insert request Register1 */ +#define CSR_MQM_IQM_IQM_UNCRT_INT_EN_REG (CSR_MQM_IQM_BASE + 0x68) /* IQM uncorect int mask */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ5_REG (CSR_MQM_IQM_BASE + 0x6C) /* IQM FIFO INT REQ5 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ6_REG (CSR_MQM_IQM_BASE + 0x70) /* IQM FIFO INT REQ6 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ7_REG (CSR_MQM_IQM_BASE + 0x74) /* IQM FIFO INT REQ7 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ8_REG (CSR_MQM_IQM_BASE + 0x78) /* IQM FIFO INT REQ8 */ +#define CSR_MQM_IQM_IQM_FIFO_INT_REQ9_REG (CSR_MQM_IQM_BASE + 0x7C) /* IQM FIFO INT REQ9 */ +#define CSR_MQM_IQM_IQM_CHUNK_REG (CSR_MQM_IQM_BASE + 0x80) /* chunk configuration register */ +#define CSR_MQM_IQM_IQM_OUT_FIFO_TH_GAP_REG (CSR_MQM_IQM_BASE + 0x84) /* IQM fifo threshold configuration */ +#define CSR_MQM_IQM_IQM_ENQ_FIFO_AFUL_GAP_REG \ + (CSR_MQM_IQM_BASE + 0x88) /* IQM en-queue almost full threshold config register */ +#define CSR_MQM_IQM_IQM_CRDT_COMP_FIFO_GAP_CFG_REG (CSR_MQM_IQM_BASE + 0x8C) /* iqm credit comp fifo gap */ +#define CSR_MQM_IQM_IQM_AGING_CFG_REG (CSR_MQM_IQM_BASE + 0x90) /* aging configuration register */ +#define CSR_MQM_IQM_IQM_DES_QUE_DEQ_CFG0_REG (CSR_MQM_IQM_BASE + 0x94) /* IQM designate Queue De-queue cfg register */ +#define CSR_MQM_IQM_IQM_DES_QUE_DEQ_CFG1_REG (CSR_MQM_IQM_BASE + 0x98) /* IQM designate queue De-queue vld and VF ID \ + */ +#define CSR_MQM_IQM_IQM_ROOT_THR_CFG_REG \ + (CSR_MQM_IQM_BASE + 0x9C) /* the static threshold for root level config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_ROOT_HTHR_CFG_REG \ + (CSR_MQM_IQM_BASE + 0xA0) /* the high threshold offset parameter for root config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_ROOT_THR_CFG_REG \ + (CSR_MQM_IQM_BASE + 0xA4) /* the static threshold of root level nmq config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_ROOT_THR_CFG_REG \ + (CSR_MQM_IQM_BASE + 0xA8) /* the static threshold of root level nfmq config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HOST0_TH_REG \ + (CSR_MQM_IQM_BASE + 0xAC) /* the static threshold of nmq host0 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HOST1_TH_REG \ + (CSR_MQM_IQM_BASE + 0xB0) /* the static threshold of nmq host1 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HOST2_TH_REG \ + (CSR_MQM_IQM_BASE + 0xB4) /* the static threshold of nmq host2 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HOST3_TH_REG \ + (CSR_MQM_IQM_BASE + 0xB8) /* the static threshold of nmq host3 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HOST_HTH_PA_REG \ + (CSR_MQM_IQM_BASE + 0xBC) /* the nmq high threshold offset parameter config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HOST0_TH_REG \ + (CSR_MQM_IQM_BASE + 0xC0) /* the static threshold of nfmq host0 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HOST1_TH_REG \ + (CSR_MQM_IQM_BASE + 0xC4) /* the static threshold of nfmq host1 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HOST2_TH_REG \ + (CSR_MQM_IQM_BASE + 0xC8) /* the static threshold of nfmq host2 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HOST3_TH_REG \ + (CSR_MQM_IQM_BASE + 0xCC) /* the static threshold of nfmq host3 config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HOST_HTH_PA_REG \ + (CSR_MQM_IQM_BASE + 0xD0) /* the nfmq high threshold offset parameter config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_0_REG \ + (CSR_MQM_IQM_BASE + 0xD4) /* host_ep nmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_1_REG \ + (CSR_MQM_IQM_BASE + 0xD8) /* host_ep nmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_2_REG \ + (CSR_MQM_IQM_BASE + 0xDC) /* host_ep nmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NMQ_HEX_PRO_MAP_3_REG \ + (CSR_MQM_IQM_BASE + 0xE0) /* host_ep nmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_0_REG \ + (CSR_MQM_IQM_BASE + 0xE4) /* host_ep nfmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_1_REG \ + (CSR_MQM_IQM_BASE + 0xE8) /* host_ep nfmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_2_REG \ + (CSR_MQM_IQM_BASE + 0xEC) /* host_ep nfmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_NFMQ_HEX_PRO_MAP_3_REG \ + (CSR_MQM_IQM_BASE + 0xF0) /* host_ep nfmq profile mapping number config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_0_REG \ + (CSR_MQM_IQM_BASE + 0xF4) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_1_REG \ + (CSR_MQM_IQM_BASE + 0xF8) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_2_REG \ + (CSR_MQM_IQM_BASE + 0xFC) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_3_REG \ + (CSR_MQM_IQM_BASE + 0x100) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_4_REG \ + (CSR_MQM_IQM_BASE + 0x104) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_5_REG \ + (CSR_MQM_IQM_BASE + 0x108) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_6_REG \ + (CSR_MQM_IQM_BASE + 0x10C) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_7_REG \ + (CSR_MQM_IQM_BASE + 0x110) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_8_REG \ + (CSR_MQM_IQM_BASE + 0x114) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_9_REG \ + (CSR_MQM_IQM_BASE + 0x118) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_10_REG \ + (CSR_MQM_IQM_BASE + 0x11C) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_11_REG \ + (CSR_MQM_IQM_BASE + 0x120) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_12_REG \ + (CSR_MQM_IQM_BASE + 0x124) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_13_REG \ + (CSR_MQM_IQM_BASE + 0x128) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_14_REG \ + (CSR_MQM_IQM_BASE + 0x12C) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_TH_PRO_15_REG \ + (CSR_MQM_IQM_BASE + 0x130) /* host_ep threshold profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_0_REG \ + (CSR_MQM_IQM_BASE + 0x134) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_1_REG \ + (CSR_MQM_IQM_BASE + 0x138) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_2_REG \ + (CSR_MQM_IQM_BASE + 0x13C) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_3_REG \ + (CSR_MQM_IQM_BASE + 0x140) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_4_REG \ + (CSR_MQM_IQM_BASE + 0x144) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_5_REG \ + (CSR_MQM_IQM_BASE + 0x148) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_6_REG \ + (CSR_MQM_IQM_BASE + 0x14C) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_7_REG \ + (CSR_MQM_IQM_BASE + 0x150) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_8_REG \ + (CSR_MQM_IQM_BASE + 0x154) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_9_REG \ + (CSR_MQM_IQM_BASE + 0x158) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_10_REG \ + (CSR_MQM_IQM_BASE + 0x15C) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_11_REG \ + (CSR_MQM_IQM_BASE + 0x160) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_12_REG \ + (CSR_MQM_IQM_BASE + 0x164) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_13_REG \ + (CSR_MQM_IQM_BASE + 0x168) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_14_REG \ + (CSR_MQM_IQM_BASE + 0x16C) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HE_FAC_PRO_15_REG \ + (CSR_MQM_IQM_BASE + 0x170) /* host_ep factor and parameter profile config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_QTSS_CFG_REG \ + (CSR_MQM_IQM_BASE + 0x174) /* queue level share space config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HETSS_CFG_REG \ + (CSR_MQM_IQM_BASE + 0x178) /* host_ep level share space config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_HECTSS_CFG_REG \ + (CSR_MQM_IQM_BASE + 0x17C) /* host_ep_cos level share space config register for flow_ctrl */ +#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_0_REG \ + (CSR_MQM_IQM_BASE + 0x180) /* the host level static credit threshold for sm */ +#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_1_REG \ + (CSR_MQM_IQM_BASE + 0x184) /* the host level static credit threshold for sm */ +#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_2_REG \ + (CSR_MQM_IQM_BASE + 0x188) /* the host level static credit threshold for sm */ +#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_3_REG \ + (CSR_MQM_IQM_BASE + 0x18C) /* the host level static credit threshold for sm */ +#define CSR_MQM_IQM_IQM_SM_HOST_CREDIT_TH_4_REG \ + (CSR_MQM_IQM_BASE + 0x190) /* the host level static credit threshold for sm */ +#define CSR_MQM_IQM_IQM_SM_CREDIT_TSS_CFG_DATA_REG \ + (CSR_MQM_IQM_BASE + 0x194) /* the total share data ep credit space of sm */ +#define CSR_MQM_IQM_IQM_SM_CREDIT_TSS_CFG_SGE_REG \ + (CSR_MQM_IQM_BASE + 0x198) /* the total share sge ep credit space of sm */ +#define CSR_MQM_IQM_IQM_QU_CREDIT_TSS_CFG_REG (CSR_MQM_IQM_BASE + 0x19C) /* the total share ep credit space of qu */ +#define CSR_MQM_IQM_IQM_CRR_WGT_CFG_REG (CSR_MQM_IQM_BASE + 0x1A0) /* out to sm or qu crr weight cfg */ +#define CSR_MQM_IQM_IQM_DB_MERGER_CFG_REG (CSR_MQM_IQM_BASE + 0x1A4) /* IQM DB Merger conctrl Register */ +#define CSR_MQM_IQM_SMF_DST_HASH_CFG_REG (CSR_MQM_IQM_BASE + 0x1A8) /* SMF destination hash cfg */ +#define CSR_MQM_IQM_IQM_AGING_CLR_CFG_REG (CSR_MQM_IQM_BASE + 0x1AC) /* aging cnt and vld clr register */ +#define CSR_MQM_IQM_IQM_MEM_ECC_BYPASS_EN_REG (CSR_MQM_IQM_BASE + 0x1B0) /* IQM RAM ECC BYPASS ctrl en */ +#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_IQM_BASE + 0x1B4) /* IQM RAM ctrl bus cfg reg0 */ +#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_IQM_BASE + 0x1B8) /* IQM RAM ctrl bus cfg reg1 */ +#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_IQM_BASE + 0x1BC) /* IQM RAM ctrl bus cfg reg2 */ +#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_IQM_BASE + 0x1C0) /* IQM RAM ctrl bus cfg reg3 */ +#define CSR_MQM_IQM_IQM_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_IQM_BASE + 0x1C4) /* IQM RAM ctrl bus cfg reg4 */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_0_REG (CSR_MQM_IQM_BASE + 0x1E0) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_1_REG (CSR_MQM_IQM_BASE + 0x1E4) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_2_REG (CSR_MQM_IQM_BASE + 0x1E8) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_3_REG (CSR_MQM_IQM_BASE + 0x1EC) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_4_REG (CSR_MQM_IQM_BASE + 0x1F0) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_5_REG (CSR_MQM_IQM_BASE + 0x1F4) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_6_REG (CSR_MQM_IQM_BASE + 0x1F8) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_7_REG (CSR_MQM_IQM_BASE + 0x1FC) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_8_REG (CSR_MQM_IQM_BASE + 0x200) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_9_REG (CSR_MQM_IQM_BASE + 0x204) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_10_REG (CSR_MQM_IQM_BASE + 0x208) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_11_REG (CSR_MQM_IQM_BASE + 0x20C) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_12_REG (CSR_MQM_IQM_BASE + 0x210) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_SM_SHALLOW_FIFO_STATUS_13_REG (CSR_MQM_IQM_BASE + 0x214) /* iqm sm shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_0_REG (CSR_MQM_IQM_BASE + 0x218) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_1_REG (CSR_MQM_IQM_BASE + 0x21C) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_2_REG (CSR_MQM_IQM_BASE + 0x220) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_3_REG (CSR_MQM_IQM_BASE + 0x224) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_4_REG (CSR_MQM_IQM_BASE + 0x228) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_5_REG (CSR_MQM_IQM_BASE + 0x22C) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_6_REG (CSR_MQM_IQM_BASE + 0x230) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_7_REG (CSR_MQM_IQM_BASE + 0x234) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_8_REG (CSR_MQM_IQM_BASE + 0x238) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_9_REG (CSR_MQM_IQM_BASE + 0x23C) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_10_REG (CSR_MQM_IQM_BASE + 0x240) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_11_REG (CSR_MQM_IQM_BASE + 0x244) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_12_REG (CSR_MQM_IQM_BASE + 0x248) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_13_REG (CSR_MQM_IQM_BASE + 0x24C) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_14_REG (CSR_MQM_IQM_BASE + 0x250) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_15_REG (CSR_MQM_IQM_BASE + 0x254) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_16_REG (CSR_MQM_IQM_BASE + 0x258) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_QU_SHALLOW_FIFO_STATUS_17_REG (CSR_MQM_IQM_BASE + 0x25C) /* iqm qu shallow fifo status */ +#define CSR_MQM_IQM_IQM_CMQ_CNT_REG (CSR_MQM_IQM_BASE + 0x260) /* the number of CMQ queue descriptor store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOST_CNT0_REG \ + (CSR_MQM_IQM_BASE + 0x264) /* the number of queue descriptor belone to CMQ host0 and CMQ host1 store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOST_CNT1_REG \ + (CSR_MQM_IQM_BASE + 0x268) /* the number of queue descriptor belone to CMQ host2 and cmq host3 store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_0_REG \ + (CSR_MQM_IQM_BASE + 0x26C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_1_REG \ + (CSR_MQM_IQM_BASE + 0x270) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_2_REG \ + (CSR_MQM_IQM_BASE + 0x274) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_3_REG \ + (CSR_MQM_IQM_BASE + 0x278) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_4_REG \ + (CSR_MQM_IQM_BASE + 0x27C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_5_REG \ + (CSR_MQM_IQM_BASE + 0x280) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_6_REG \ + (CSR_MQM_IQM_BASE + 0x284) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_7_REG \ + (CSR_MQM_IQM_BASE + 0x288) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_8_REG \ + (CSR_MQM_IQM_BASE + 0x28C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_9_REG \ + (CSR_MQM_IQM_BASE + 0x290) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_10_REG \ + (CSR_MQM_IQM_BASE + 0x294) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_11_REG \ + (CSR_MQM_IQM_BASE + 0x298) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_12_REG \ + (CSR_MQM_IQM_BASE + 0x29C) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_13_REG \ + (CSR_MQM_IQM_BASE + 0x2A0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_14_REG \ + (CSR_MQM_IQM_BASE + 0x2A4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_15_REG \ + (CSR_MQM_IQM_BASE + 0x2A8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_16_REG \ + (CSR_MQM_IQM_BASE + 0x2AC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_17_REG \ + (CSR_MQM_IQM_BASE + 0x2B0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_18_REG \ + (CSR_MQM_IQM_BASE + 0x2B4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_19_REG \ + (CSR_MQM_IQM_BASE + 0x2B8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_20_REG \ + (CSR_MQM_IQM_BASE + 0x2BC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_21_REG \ + (CSR_MQM_IQM_BASE + 0x2C0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_22_REG \ + (CSR_MQM_IQM_BASE + 0x2C4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_23_REG \ + (CSR_MQM_IQM_BASE + 0x2C8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_24_REG \ + (CSR_MQM_IQM_BASE + 0x2CC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_25_REG \ + (CSR_MQM_IQM_BASE + 0x2D0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_26_REG \ + (CSR_MQM_IQM_BASE + 0x2D4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_27_REG \ + (CSR_MQM_IQM_BASE + 0x2D8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_28_REG \ + (CSR_MQM_IQM_BASE + 0x2DC) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_29_REG \ + (CSR_MQM_IQM_BASE + 0x2E0) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_30_REG \ + (CSR_MQM_IQM_BASE + 0x2E4) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_CMQ_HOSTEPX_CNT_31_REG \ + (CSR_MQM_IQM_BASE + 0x2E8) /* the number of queue descriptor belone to host_ep level CMQ store in IQM */ +#define CSR_MQM_IQM_IQM_ROOTX_CNT_REG \ + (CSR_MQM_IQM_BASE + 0x2EC) /* statistics of the number of root level NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_NMQ_HOSTX_CNT0_REG \ + (CSR_MQM_IQM_BASE + 0x2F0) /* statistics of the number of host0 and host1 NMQ store in IQM */ +#define CSR_MQM_IQM_IQM_NMQ_HOSTX_CNT1_REG \ + (CSR_MQM_IQM_BASE + 0x2F4) /* statistics of the number of host2 and host3 NMQ store in IQM */ +#define CSR_MQM_IQM_IQM_NFMQ_HOSTX_CNT0_REG \ + (CSR_MQM_IQM_BASE + 0x2F8) /* statistics of the number of host0 and host1 NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_NFMQ_HOSTX_CNT1_REG \ + (CSR_MQM_IQM_BASE + 0x2FC) /* statistics of the number of host2 and host3 NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_0_REG \ + (CSR_MQM_IQM_BASE + \ + 0x300) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_1_REG \ + (CSR_MQM_IQM_BASE + \ + 0x304) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_2_REG \ + (CSR_MQM_IQM_BASE + \ + 0x308) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_3_REG \ + (CSR_MQM_IQM_BASE + \ + 0x30C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_4_REG \ + (CSR_MQM_IQM_BASE + \ + 0x310) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_5_REG \ + (CSR_MQM_IQM_BASE + \ + 0x314) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_6_REG \ + (CSR_MQM_IQM_BASE + \ + 0x318) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_7_REG \ + (CSR_MQM_IQM_BASE + \ + 0x31C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_8_REG \ + (CSR_MQM_IQM_BASE + \ + 0x320) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_9_REG \ + (CSR_MQM_IQM_BASE + \ + 0x324) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_10_REG \ + (CSR_MQM_IQM_BASE + \ + 0x328) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_11_REG \ + (CSR_MQM_IQM_BASE + \ + 0x32C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_12_REG \ + (CSR_MQM_IQM_BASE + \ + 0x330) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_13_REG \ + (CSR_MQM_IQM_BASE + \ + 0x334) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_14_REG \ + (CSR_MQM_IQM_BASE + \ + 0x338) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_15_REG \ + (CSR_MQM_IQM_BASE + \ + 0x33C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_16_REG \ + (CSR_MQM_IQM_BASE + \ + 0x340) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_17_REG \ + (CSR_MQM_IQM_BASE + \ + 0x344) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_18_REG \ + (CSR_MQM_IQM_BASE + \ + 0x348) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_19_REG \ + (CSR_MQM_IQM_BASE + \ + 0x34C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_20_REG \ + (CSR_MQM_IQM_BASE + \ + 0x350) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_21_REG \ + (CSR_MQM_IQM_BASE + \ + 0x354) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_22_REG \ + (CSR_MQM_IQM_BASE + \ + 0x358) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_23_REG \ + (CSR_MQM_IQM_BASE + \ + 0x35C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_24_REG \ + (CSR_MQM_IQM_BASE + \ + 0x360) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_25_REG \ + (CSR_MQM_IQM_BASE + \ + 0x364) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_26_REG \ + (CSR_MQM_IQM_BASE + \ + 0x368) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_27_REG \ + (CSR_MQM_IQM_BASE + \ + 0x36C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_28_REG \ + (CSR_MQM_IQM_BASE + \ + 0x370) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_29_REG \ + (CSR_MQM_IQM_BASE + \ + 0x374) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_30_REG \ + (CSR_MQM_IQM_BASE + \ + 0x378) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_MQ_HEX_CNT_31_REG \ + (CSR_MQM_IQM_BASE + \ + 0x37C) /* statistics of the number of queue descriptor belones to host_ep NMQ or NFMQ store in IQM */ +#define CSR_MQM_IQM_IQM_UCMQ_ROOT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0x380) /* statistics of the number of root level ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UNMQ_ROOT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0x384) /* statistics of the number of root level unmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_0_REG \ + (CSR_MQM_IQM_BASE + 0x388) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_1_REG \ + (CSR_MQM_IQM_BASE + 0x38C) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_2_REG \ + (CSR_MQM_IQM_BASE + 0x390) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_3_REG \ + (CSR_MQM_IQM_BASE + 0x394) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_4_REG \ + (CSR_MQM_IQM_BASE + 0x398) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_5_REG \ + (CSR_MQM_IQM_BASE + 0x39C) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_6_REG \ + (CSR_MQM_IQM_BASE + 0x3A0) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_EP_CNT_7_REG \ + (CSR_MQM_IQM_BASE + 0x3A4) /* the number of unmq and ucmq for EP7~0 store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_0_REG \ + (CSR_MQM_IQM_BASE + 0x3A8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_1_REG \ + (CSR_MQM_IQM_BASE + 0x3AC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_2_REG \ + (CSR_MQM_IQM_BASE + 0x3B0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_3_REG \ + (CSR_MQM_IQM_BASE + 0x3B4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_4_REG \ + (CSR_MQM_IQM_BASE + 0x3B8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_5_REG \ + (CSR_MQM_IQM_BASE + 0x3BC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_6_REG \ + (CSR_MQM_IQM_BASE + 0x3C0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_7_REG \ + (CSR_MQM_IQM_BASE + 0x3C4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_8_REG \ + (CSR_MQM_IQM_BASE + 0x3C8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_9_REG \ + (CSR_MQM_IQM_BASE + 0x3CC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_10_REG \ + (CSR_MQM_IQM_BASE + 0x3D0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_11_REG \ + (CSR_MQM_IQM_BASE + 0x3D4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_12_REG \ + (CSR_MQM_IQM_BASE + 0x3D8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_13_REG \ + (CSR_MQM_IQM_BASE + 0x3DC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_14_REG \ + (CSR_MQM_IQM_BASE + 0x3E0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_15_REG \ + (CSR_MQM_IQM_BASE + 0x3E4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_16_REG \ + (CSR_MQM_IQM_BASE + 0x3E8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_17_REG \ + (CSR_MQM_IQM_BASE + 0x3EC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_18_REG \ + (CSR_MQM_IQM_BASE + 0x3F0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_19_REG \ + (CSR_MQM_IQM_BASE + 0x3F4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_20_REG \ + (CSR_MQM_IQM_BASE + 0x3F8) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_21_REG \ + (CSR_MQM_IQM_BASE + 0x3FC) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_22_REG \ + (CSR_MQM_IQM_BASE + 0x400) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_23_REG \ + (CSR_MQM_IQM_BASE + 0x404) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_24_REG \ + (CSR_MQM_IQM_BASE + 0x408) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_25_REG \ + (CSR_MQM_IQM_BASE + 0x40C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_26_REG \ + (CSR_MQM_IQM_BASE + 0x410) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_27_REG \ + (CSR_MQM_IQM_BASE + 0x414) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_28_REG \ + (CSR_MQM_IQM_BASE + 0x418) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_29_REG \ + (CSR_MQM_IQM_BASE + 0x41C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_30_REG \ + (CSR_MQM_IQM_BASE + 0x420) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_31_REG \ + (CSR_MQM_IQM_BASE + 0x424) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_32_REG \ + (CSR_MQM_IQM_BASE + 0x428) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_33_REG \ + (CSR_MQM_IQM_BASE + 0x42C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_34_REG \ + (CSR_MQM_IQM_BASE + 0x430) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_35_REG \ + (CSR_MQM_IQM_BASE + 0x434) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_36_REG \ + (CSR_MQM_IQM_BASE + 0x438) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_37_REG \ + (CSR_MQM_IQM_BASE + 0x43C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_38_REG \ + (CSR_MQM_IQM_BASE + 0x440) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_39_REG \ + (CSR_MQM_IQM_BASE + 0x444) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_40_REG \ + (CSR_MQM_IQM_BASE + 0x448) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_41_REG \ + (CSR_MQM_IQM_BASE + 0x44C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_42_REG \ + (CSR_MQM_IQM_BASE + 0x450) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_43_REG \ + (CSR_MQM_IQM_BASE + 0x454) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_44_REG \ + (CSR_MQM_IQM_BASE + 0x458) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_45_REG \ + (CSR_MQM_IQM_BASE + 0x45C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_46_REG \ + (CSR_MQM_IQM_BASE + 0x460) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_47_REG \ + (CSR_MQM_IQM_BASE + 0x464) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_48_REG \ + (CSR_MQM_IQM_BASE + 0x468) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_49_REG \ + (CSR_MQM_IQM_BASE + 0x46C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_50_REG \ + (CSR_MQM_IQM_BASE + 0x470) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_51_REG \ + (CSR_MQM_IQM_BASE + 0x474) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_52_REG \ + (CSR_MQM_IQM_BASE + 0x478) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_53_REG \ + (CSR_MQM_IQM_BASE + 0x47C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_54_REG \ + (CSR_MQM_IQM_BASE + 0x480) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_55_REG \ + (CSR_MQM_IQM_BASE + 0x484) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_56_REG \ + (CSR_MQM_IQM_BASE + 0x488) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_57_REG \ + (CSR_MQM_IQM_BASE + 0x48C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_58_REG \ + (CSR_MQM_IQM_BASE + 0x490) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_59_REG \ + (CSR_MQM_IQM_BASE + 0x494) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_60_REG \ + (CSR_MQM_IQM_BASE + 0x498) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_61_REG \ + (CSR_MQM_IQM_BASE + 0x49C) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_62_REG \ + (CSR_MQM_IQM_BASE + 0x4A0) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_IQM_UXMQ_QUEUE_CNT_63_REG \ + (CSR_MQM_IQM_BASE + 0x4A4) /* statistics of the number of queue level unmq or ucmq store in IQM */ +#define CSR_MQM_IQM_EQM_ENQ_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4A8) /* THE STATUS OF EQM EN_QUEUE FIFO */ +#define CSR_MQM_IQM_DEQC_ENQ_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4AC) /* THE STATUS OF DEQC EN_QUEUE FIFO */ +#define CSR_MQM_IQM_IQM_ENQC_ENQ_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4B0) /* THE STATUS OF ENQC EN_QUEUE FIFO */ +#define CSR_MQM_IQM_IQM_ENQC_SOC_ENQ_FIFO_STATUS_REG \ + (CSR_MQM_IQM_BASE + 0x4B4) /* the status of enqc soc enq_queue fifo */ +#define CSR_MQM_IQM_IQM_CPI_SGE_CRDT_COMP_FIFO_STATUS_REG \ + (CSR_MQM_IQM_BASE + 0x4B8) /* iqm cpi sge credit comp fifo status */ +#define CSR_MQM_IQM_IQM_CPI_DATA_CRDT_COMP_FIFO_STATUS_REG \ + (CSR_MQM_IQM_BASE + 0x4BC) /* iqm cpi data credit comp fifo status */ +#define CSR_MQM_IQM_IQM_SM_CRDT_COMP_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4C0) /* sm credit comp fifo status */ +#define CSR_MQM_IQM_IQM_SM_OUT_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4C4) /* sm out fifo status */ +#define CSR_MQM_IQM_IQM_QU_CRDT_COMP_FIFO_STATUS_REG (CSR_MQM_IQM_BASE + 0x4C8) /* iqm qu credit comp fifo status */ +#define CSR_MQM_IQM_ICLL_FREE_CNT_REG (CSR_MQM_IQM_BASE + 0x4CC) /* report the free resource in IQM */ +#define CSR_MQM_IQM_IQM_SM_TOTAL_CAM_CNT_REG (CSR_MQM_IQM_BASE + 0x4D0) /* iqm sm total cam counter */ +#define CSR_MQM_IQM_IQM_SM_HOST_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4D4) /* iqm sm host credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_RR_SGE_CRDT_BP_REG \ + (CSR_MQM_IQM_BASE + 0x4D8) /* iqm sm ep host dp rr sge credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_RR_DAT_CRDT_BP_REG \ + (CSR_MQM_IQM_BASE + 0x4DC) /* iqm sm ep host dp rr data credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_SGE_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4E0) /* iqm sm ep host dp sge credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_DP_DAT_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4E4) /* iqm sm ep host dp data credit bp \ + */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_CP_RR_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4E8) /* iqm sm ep host cp rr credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_SOC_RR_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4EC) /* iqm sm ep soc dp/cp rr credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_HOST_CP_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4F0) /* iqm sm ep host cp credit bp */ +#define CSR_MQM_IQM_IQM_SM_EP_SOC_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x4F4) /* iqm sm ep soc dp/cp credit bp */ +#define CSR_MQM_IQM_IQM_QU_EP_DP_CRDT_BP0_REG (CSR_MQM_IQM_BASE + 0x4F8) /* iqm qu ep dp credit resource 0-31 bp */ +#define CSR_MQM_IQM_IQM_QU_EP_DP_CRDT_BP1_REG (CSR_MQM_IQM_BASE + 0x4FC) /* iqm qu ep dp credit resource 32-63 bp */ +#define CSR_MQM_IQM_IQM_QU_EP_CP_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x500) /* iqm qu ep cp credit bp */ +#define CSR_MQM_IQM_IQM_QU_EP_DP_RR_CRDT_BP0_REG \ + (CSR_MQM_IQM_BASE + 0x504) /* iqm qu ep dp credit resource 0-31 rr bp */ +#define CSR_MQM_IQM_IQM_QU_EP_DP_RR_CRDT_BP1_REG \ + (CSR_MQM_IQM_BASE + 0x508) /* iqm qu ep dp credit resource 32-63 rr bp */ +#define CSR_MQM_IQM_IQM_QU_EP_CP_RR_CRDT_BP_REG (CSR_MQM_IQM_BASE + 0x50C) /* iqm qu ep cp credit rr bp */ +#define CSR_MQM_IQM_IQM_FLUSH_ICLL_CAM_DONE_REG \ + (CSR_MQM_IQM_BASE + 0x510) /* iqm flush soc and host mq done and cam flush done */ +#define CSR_MQM_IQM_IQM_AGING_NMQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB38) /* times of iqm nmq hardware aging nmq */ +#define CSR_MQM_IQM_IQM_AGING_NFMQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB3C) /* times of iqm nfmq hardware aging nmq */ +#define CSR_MQM_IQM_IQM_AGING_DISCARD_CNT_REG (CSR_MQM_IQM_BASE + 0xB40) /* iqm aging discard queue descriptor cnt */ +#define CSR_MQM_IQM_IQM_TO_EQM_QD_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB44) /* iqm aging or designated deq to eqm queue descriptor cnt */ +#define CSR_MQM_IQM_IQM_DEQ_SM_CNT_REG (CSR_MQM_IQM_BASE + 0xB48) /* statistics of the nunber de-queue to sm */ +#define CSR_MQM_IQM_IQM_DEQ_QU_CNT_REG (CSR_MQM_IQM_BASE + 0xB4C) /* statistics of the nunber de-queue to qu */ +#define CSR_MQM_IQM_MSC_IQM_DEQ_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB50) /* the number of de-queue operation that msc send to iqm */ +#define CSR_MQM_IQM_IQM_NMQNFMQ_ENQ_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB54) /* the number of iqm en-queue operation for nmq and nfmq */ +#define CSR_MQM_IQM_IQM_NMQNFMQ_DEQ_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB58) /* the number of iqm de-queue operation for nmq and nfmq */ +#define CSR_MQM_IQM_IQM_CMQ_ENQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB5C) /* the number of iqm en-queue operation for cmq */ +#define CSR_MQM_IQM_IQM_CMQ_DEQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB60) /* the number of iqm de-queue operation for cmq */ +#define CSR_MQM_IQM_SOC_MSC_IQM_DEQ_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB64) /* the number of de-queue operation that soc msc send to iqm */ +#define CSR_MQM_IQM_IQM_UNMQ_ENQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB68) /* the number of iqm en-queue operation for unmq \ + */ +#define CSR_MQM_IQM_IQM_UNMQ_DEQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB6C) /* the number of iqm de-queue operation for unmq \ + */ +#define CSR_MQM_IQM_IQM_UCMQ_ENQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB70) /* the number of iqm en-queue operation for ucmq \ + */ +#define CSR_MQM_IQM_IQM_UCMQ_DEQ_CNT_REG (CSR_MQM_IQM_BASE + 0xB74) /* the number of iqm de-queue operation for ucmq \ + */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_HOST_SGE_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB78) /* iqm rx cpi comp host sge credit cnt */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_HOST_DAT_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB7C) /* iqm rx cpi comp host data credit cnt */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_DP_SGE_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB80) /* iqm rx cpi comp ep dp sge credit cnt */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_CP_SGE_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB84) /* iqm rx cpi comp ep cp sge credit cnt */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_DP_DAT_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB88) /* iqm rx cpi comp ep dp data credit cnt */ +#define CSR_MQM_IQM_IQM_RX_CPI_COMP_EP_CP_DAT_CRDT_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB8C) /* iqm rx cpi comp ep cp data credit cnt */ +#define CSR_MQM_IQM_IQM_RX_QU_COMP_EP_DP_CRDT_CNT_REG (CSR_MQM_IQM_BASE + 0xB90) /* iqm rx qu comp ep dp credit cnt */ +#define CSR_MQM_IQM_IQM_RX_QU_COMP_EP_CP_CRDT_CNT_REG (CSR_MQM_IQM_BASE + 0xB94) /* iqm rx qu comp ep cp credit cnt */ +#define CSR_MQM_IQM_IQM_ECC_1BIT_ERR_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB98) /* statistics counter of IQM memory ECC 1bit ERR */ +#define CSR_MQM_IQM_IQM_ECC_2BIT_ERR_CNT_REG \ + (CSR_MQM_IQM_BASE + 0xB9C) /* statistics counter of IQM memory ECC 2bit ERR */ + +/* MQM_EQM Base address of Module's Register */ +#define CSR_MQM_EQM_BASE (0xA000) + +/* **************************************************************************** */ +/* MQM_EQM Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_EQM_EQM_RW_RSV0_REG (CSR_MQM_EQM_BASE + 0x0) /* EQM rw reserved 0 */ +#define CSR_MQM_EQM_EQM_RW_RSV1_REG (CSR_MQM_EQM_BASE + 0x4) /* EQM rw reserved 1 */ +#define CSR_MQM_EQM_EQM_RW_RSV2_REG (CSR_MQM_EQM_BASE + 0x8) /* EQM rw reserved 2 */ +#define CSR_MQM_EQM_EQM_RW_RSV3_REG (CSR_MQM_EQM_BASE + 0xC) /* EQM rw reserved 3 */ +#define CSR_MQM_EQM_EQM_INDRECT_CTRL_REG (CSR_MQM_EQM_BASE + 0x10) /* EQM Indirect access ctrl Register。 */ +#define CSR_MQM_EQM_EQM_INDRECT_TIMEOUT_REG (CSR_MQM_EQM_BASE + 0x14) /* EQM Indirect Access Timeout Register。 */ +#define CSR_MQM_EQM_EQM_INDRECT_DATA_REG (CSR_MQM_EQM_BASE + 0x18) /* EQM Indirect Access Data Register. */ +#define CSR_MQM_EQM_EQM_ECQM_BP_BYPASS_REG (CSR_MQM_EQM_BASE + 0x1C) /* EQM ECQM_HFIFO Backpresssure Bypass */ +#define CSR_MQM_EQM_EQM_MEM_ECC_BYPASS_EN_REG (CSR_MQM_EQM_BASE + 0x20) /* EQM RAM ECC Bypass控制寄存器 */ +#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_EQM_BASE + 0x24) /* EQM RAM ctrl bus cfg reg0 */ +#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_EQM_BASE + 0x28) /* EQM RAM ctrl bus cfg reg1 */ +#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_EQM_BASE + 0x2C) /* EQM RAM ctrl bus cfg reg2 */ +#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_EQM_BASE + 0x30) /* EQM RAM ctrl bus cfg reg3 */ +#define CSR_MQM_EQM_EQM_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_EQM_BASE + 0x34) /* EQM RAM ctrl bus cfg reg4 */ +#define CSR_MQM_EQM_EQM_INT_VECTOR_REG (CSR_MQM_EQM_BASE + 0x40) /* EQM Internal ERR Interrupt Vector Register. */ +#define CSR_MQM_EQM_EQM_INT_REG (CSR_MQM_EQM_BASE + 0x44) /* EQM Internal ERR Interrupt Register. */ +#define CSR_MQM_EQM_EQM_INT_EN_REG (CSR_MQM_EQM_BASE + 0x48) /* EQM Internal ERR Interrupt Mask Register. */ +#define CSR_MQM_EQM_EQM_MEM_ECC_REQ_REG (CSR_MQM_EQM_BASE + 0x4C) /* EQM memory ecc insert request Register */ +#define CSR_MQM_EQM_EQM_MEM_1BIT_ERR_REG (CSR_MQM_EQM_BASE + 0x50) /* EQM 1Bit ECC Check Err Register. */ +#define CSR_MQM_EQM_EQM_MEM_2BIT_ERR_REG (CSR_MQM_EQM_BASE + 0x54) /* EQM 2Bit ECC Check Err Register. */ +#define CSR_MQM_EQM_EQM_QL_DEQ_EMPTY_INT_REG \ + (CSR_MQM_EQM_BASE + 0x58) /* EQM Queue Deq Interrupt Register When Queue Empty */ +#define CSR_MQM_EQM_EQM_CLL_FAP_EXHAUSTED_INT_REG \ + (CSR_MQM_EQM_BASE + 0x5C) /* EQM CHUNK Link List Interrupt Register When Free Addr Pool Resource Exhausted。 */ +#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT0_REG \ + (CSR_MQM_EQM_BASE + 0x60) /* EQM FIFO Write Interrupt Register When Full */ +#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT0_EN_REG \ + (CSR_MQM_EQM_BASE + 0x64) /* EQM FIFO Write Interrupt Mask Register When Full */ +#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT1_REG \ + (CSR_MQM_EQM_BASE + 0x68) /* EQM FIFO Write Interrupt Register Whenable Full */ +#define CSR_MQM_EQM_EQM_FIFO_WR_OVFL_INT1_EN_REG \ + (CSR_MQM_EQM_BASE + 0x6C) /* EQM FIFO Write Interrupt Mask Register When Full */ +#define CSR_MQM_EQM_EQM_FIFO_RD_UNDEL_INT_REG \ + (CSR_MQM_EQM_BASE + 0x70) /* EQM FIFO Read Interrupt Register When Empty */ +#define CSR_MQM_EQM_EQM_FIFO_RD_UNDEL_INT_EN_REG \ + (CSR_MQM_EQM_BASE + 0x74) /* EQM FIFO Read Interrupt Mask Register When Empty */ +#define CSR_MQM_EQM_EQM_RING_DFX_ERR_INT_REG \ + (CSR_MQM_EQM_BASE + 0x78) /* EQM Receive E0 Interrupt Register From RING Interface */ +#define CSR_MQM_EQM_EQM_BRMATT_RD_INT_REG (CSR_MQM_EQM_BASE + 0x7C) /* EQM Read ATT Error Interrupt from BRM */ +#define CSR_MQM_EQM_EQM_RING_DFX_ERR_INT1_REG \ + (CSR_MQM_EQM_BASE + 0x80) /* EQM Receive E1 Interrupt Register From RING Interface */ +#define CSR_MQM_EQM_EQM_UNCRT_INT_EN_REG (CSR_MQM_EQM_BASE + 0x84) /* enqc uncorrect int en */ +#define CSR_MQM_EQM_EQM_DWQ_RSC_DEP_CFG_REG \ + (CSR_MQM_EQM_BASE + 0x800) /* EQM DWQ Space Addr Pool Depth config Register. */ +#define CSR_MQM_EQM_EQM_PACK_CHANNEL_CFG_REG (CSR_MQM_EQM_BASE + 0x804) /* EQM Packing Channel Config Register. */ +#define CSR_MQM_EQM_EQM_DB_STORE_SPACE_SEL_REG (CSR_MQM_EQM_BASE + 0x808) /* DB溢出空间选择 */ +#define CSR_MQM_EQM_EQM_HOST_CHUNK_NUM_CFG0_REG \ + (CSR_MQM_EQM_BASE + 0x80C) /* EQM HOST0~1 chunk number Config Register. */ +#define CSR_MQM_EQM_EQM_HOST_CHUNK_NUM_CFG1_REG \ + (CSR_MQM_EQM_BASE + 0x810) /* EQM HOST2~3 chunk number Config Register. */ +#define CSR_MQM_EQM_EQM_PAGE_SIZE_CFG_REG (CSR_MQM_EQM_BASE + 0x814) /* EQM HOST MEM page size Register. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_0_REG (CSR_MQM_EQM_BASE + 0x820) /* EQM DMA Channel config Register. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_1_REG (CSR_MQM_EQM_BASE + 0x824) /* EQM DMA Channel config Register. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_2_REG (CSR_MQM_EQM_BASE + 0x828) /* EQM DMA Channel config Register. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_CHANNEL_CFG_3_REG (CSR_MQM_EQM_BASE + 0x82C) /* EQM DMA Channel config Register. */ +#define CSR_MQM_EQM_EQM_HOST_SEARCH_GPA_BADDR_CFG0_REG \ + (CSR_MQM_EQM_BASE + 0x830) /* EQM HOST search the BRM(10K GPA) Base Address Config Register0 */ +#define CSR_MQM_EQM_EQM_HOST_SEARCH_GPA_BADDR_CFG1_REG \ + (CSR_MQM_EQM_BASE + 0x834) /* EQM HOST search the BRM(10K GPA) Base Address Config Register1 */ +#define CSR_MQM_EQM_EQM_DMA_OUTSTD_NUM_REG \ + (CSR_MQM_EQM_BASE + 0x838) /* EQM Outstanding config Register for every Host */ +#define CSR_MQM_EQM_EQM_HOST_DMA_OUTSTD_NUM_REG \ + (CSR_MQM_EQM_BASE + 0x83C) /* EQM Outstanding config Register for every Host */ +#define CSR_MQM_EQM_EQM_FIFO_GAP_CFG_REG (CSR_MQM_EQM_BASE + 0x840) /* EQM FIFO Back Press Threshold config register. \ + */ +#define CSR_MQM_EQM_EQM_DWQ_INF_TH_CFG0_REG \ + (CSR_MQM_EQM_BASE + 0x844) /* EQM DWQ Interface Back Press Threshold config Register. */ +#define CSR_MQM_EQM_EQM_DWQ_INF_TH_CFG1_REG \ + (CSR_MQM_EQM_BASE + 0x848) /* EQM DWQ Interface Back Press Threshold config Register. */ +#define CSR_MQM_EQM_EQM_DWQ_INF_TH_CFG2_REG \ + (CSR_MQM_EQM_BASE + 0x84C) /* EQM DWQ Interface Back Press Threshold config Register. */ +#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_0_REG \ + (CSR_MQM_EQM_BASE + 0x850) /* EQM HOSTx Halt Threshold Config Register for CPI */ +#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_1_REG \ + (CSR_MQM_EQM_BASE + 0x854) /* EQM HOSTx Halt Threshold Config Register for CPI */ +#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_2_REG \ + (CSR_MQM_EQM_BASE + 0x858) /* EQM HOSTx Halt Threshold Config Register for CPI */ +#define CSR_MQM_EQM_EQM_HOSTX_CPI_HALT_TH_CFG_3_REG \ + (CSR_MQM_EQM_BASE + 0x85C) /* EQM HOSTx Halt Threshold Config Register for CPI */ +#define CSR_MQM_EQM_EQM_HOST_FIFO_DEPTH_CFG_REG (CSR_MQM_EQM_BASE + 0x860) /* EQM Host FIFO Depth Config Register */ +#define CSR_MQM_EQM_EQM_DMARD_FIFO_BP_TH_REG \ + (CSR_MQM_EQM_BASE + 0x864) /* EQM DMA Read fifo Backpress threshold config register */ +#define CSR_MQM_EQM_EQM_DMARD_FIFO_DEPTH0_REG \ + (CSR_MQM_EQM_BASE + 0x868) /* EQM DMA Read fifo Backpress threshold config register */ +#define CSR_MQM_EQM_EQM_DMARD_FIFO_DEPTH1_REG \ + (CSR_MQM_EQM_BASE + 0x86C) /* EQM DMA Read fifo Backpress threshold config register */ +#define CSR_MQM_EQM_EQM_DMAWR_FIFO_DEPTH0_REG \ + (CSR_MQM_EQM_BASE + 0x870) /* EQM DMA Write fifo Backpress threshold config register */ +#define CSR_MQM_EQM_EQM_DMAWR_FIFO_DEPTH1_REG \ + (CSR_MQM_EQM_BASE + 0x874) /* EQM DMA Write fifo Backpress threshold config register */ +#define CSR_MQM_EQM_EQM_DMACMD_FIFO_DEPTH0_REG \ + (CSR_MQM_EQM_BASE + 0x878) /* EQM HOST0 DMA Channel FIFO Config Register */ +#define CSR_MQM_EQM_EQM_DMACMD_FIFO_DEPTH1_REG \ + (CSR_MQM_EQM_BASE + 0x87C) /* EQM HOST0 DMA Channel FIFO Config Register */ +#define CSR_MQM_EQM_EQM_DMACMD_RDFIFO_TH_REG (CSR_MQM_EQM_BASE + 0x880) /* EQM HOST0 DMA Channel FIFO Config Register \ + */ +#define CSR_MQM_EQM_EQM_DMACMD_WRFIFO_TH0_REG \ + (CSR_MQM_EQM_BASE + 0x884) /* EQM HOST0 DMA Channel FIFO Config Register */ +#define CSR_MQM_EQM_EQM_DMACMD_WRFIFO_TH1_REG \ + (CSR_MQM_EQM_BASE + 0x888) /* EQM HOST0 DMA Channel FIFO Config Register */ +#define CSR_MQM_EQM_EQM_OUTSTD_FIFO_ALEMPTY_TH_REG (CSR_MQM_EQM_BASE + 0x88C) /* outstand fifo 将空水线 */ +#define CSR_MQM_EQM_EQM_DMACMD_FIFO_AF_GAP0_REG (CSR_MQM_EQM_BASE + 0x890) /* EQM Host0 Host1 DMA CMD FIFO ALFUL GAP \ + */ +#define CSR_MQM_EQM_EQM_DMACMD_FIFO_AF_GAP1_REG (CSR_MQM_EQM_BASE + 0x894) /* EQM Host2 Host3 DMA CMD FIFO ALFUL GAP \ + */ +#define CSR_MQM_EQM_EQM_DMAWR_FIFO_BP_GAP_REG \ + (CSR_MQM_EQM_BASE + 0x898) /* EQM DMA Write fifo Backpress gap threshold config register */ +#define CSR_MQM_EQM_EQM_INNER_BP_STATUS0_REG (CSR_MQM_EQM_BASE + 0x1000) /* EQM Inner backpress status Register0 */ +#define CSR_MQM_EQM_EQM_INNER_BP_STATUS1_REG (CSR_MQM_EQM_BASE + 0x1004) /* EQM Inner backpress status Register1 */ +#define CSR_MQM_EQM_EQM_FIFO_STATUS0_REG \ + (CSR_MQM_EQM_BASE + 0x1008) /* EQM Internal FIFO DFX Register.(including full、empty) */ +#define CSR_MQM_EQM_EQM_FIFO_STATUS1_REG \ + (CSR_MQM_EQM_BASE + 0x100C) /* EQM Internal FIFO DFX Register.(including full、empty) */ +#define CSR_MQM_EQM_EQM_RING_DFX_ERR_CNT_REG \ + (CSR_MQM_EQM_BASE + 0x1800) /* EQM Receive E0/E1 Interrupt Count Register. */ +#define CSR_MQM_EQM_EQM_SM_OVFL_CNT_REG (CSR_MQM_EQM_BASE + 0x1804) /* The redundant DoorBell number overflow form SM \ + */ +#define CSR_MQM_EQM_EQM_DWQ_FREE_ADDR_CNT_REG (CSR_MQM_EQM_BASE + 0x1808) /* EQM DWQ Free Addr Count Register. */ +#define CSR_MQM_EQM_EQM_DWQ_LIST_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x180C) /* DWQ LIST DB Count Register */ +#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_0_REG (CSR_MQM_EQM_BASE + 0x1810) /* DWQ HOSTx LIST DB Count Register */ +#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_1_REG (CSR_MQM_EQM_BASE + 0x1814) /* DWQ HOSTx LIST DB Count Register */ +#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_2_REG (CSR_MQM_EQM_BASE + 0x1818) /* DWQ HOSTx LIST DB Count Register */ +#define CSR_MQM_EQM_EQM_DWQ_HOSTX_LIST_LEN_3_REG (CSR_MQM_EQM_BASE + 0x181C) /* DWQ HOSTx LIST DB Count Register */ +#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1820) /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */ +#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1824) /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */ +#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1828) /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */ +#define CSR_MQM_EQM_EQM_BRMFAP_HOSTX_DB_EOP_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x182C) /* Brmfap向HFIFO写入Doorbell时按Host 统计的EOP个数 */ +#define CSR_MQM_EQM_EQM_NMQ_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x1830) /* EQM NMQ DB Count Register. */ +#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_0_REG (CSR_MQM_EQM_BASE + 0x1840) /* EQM NMQ HOSTx DB Count Register. */ +#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_1_REG (CSR_MQM_EQM_BASE + 0x1844) /* EQM NMQ HOSTx DB Count Register. */ +#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_2_REG (CSR_MQM_EQM_BASE + 0x1848) /* EQM NMQ HOSTx DB Count Register. */ +#define CSR_MQM_EQM_EQM_NMQ_HOSTX_DB_CNT_3_REG (CSR_MQM_EQM_BASE + 0x184C) /* EQM NMQ HOSTx DB Count Register. */ +#define CSR_MQM_EQM_EQM_NFMQ_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x1850) /* EQM NFMQ DB Count Register. */ +#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_0_REG (CSR_MQM_EQM_BASE + 0x1860) /* EQM NFMQ HOSTx DB Count Register */ +#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_1_REG (CSR_MQM_EQM_BASE + 0x1864) /* EQM NFMQ HOSTx DB Count Register */ +#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_2_REG (CSR_MQM_EQM_BASE + 0x1868) /* EQM NFMQ HOSTx DB Count Register */ +#define CSR_MQM_EQM_EQM_NFMQ_HOSTX_DB_CNT_3_REG (CSR_MQM_EQM_BASE + 0x186C) /* EQM NFMQ HOSTx DB Count Register */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1870) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1874) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1878) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */ +#define CSR_MQM_EQM_EQM_HOSTX_DMA_FREE_ADDR_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x187C) /* EQM HOSTx DMA Operate Free Addr Count Register In Host Memory. */ +#define CSR_MQM_EQM_EQM_DWQ_TILE_CNT_REG (CSR_MQM_EQM_BASE + 0x1880) /* EQM DWQ Space Count Register For TILE. */ +#define CSR_MQM_EQM_EQM_DWQ_SM_CNT_REG (CSR_MQM_EQM_BASE + 0x1884) /* EQM DWQ Space Count Register For Small-Memory. \ + */ +#define CSR_MQM_EQM_EQM_DWQ_QU_CNT_REG (CSR_MQM_EQM_BASE + 0x1888) /* EQM DWQ Space Count Register For QU. */ +#define CSR_MQM_EQM_EQM_DWQ_CPI_CNT_REG (CSR_MQM_EQM_BASE + 0x188C) /* EQM DWQ Space Count Register For CPI. */ +#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1890) /* EQM HOSTx DWQ Space Count Register For CPI. */ +#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1894) /* EQM HOSTx DWQ Space Count Register For CPI. */ +#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1898) /* EQM HOSTx DWQ Space Count Register For CPI. */ +#define CSR_MQM_EQM_EQM_DWQ_CPI_HOSTX_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x189C) /* EQM HOSTx DWQ Space Count Register For CPI. */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_0_REG (CSR_MQM_EQM_BASE + 0x18A0) /* ECQM发出的Hostx 入队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_1_REG (CSR_MQM_EQM_BASE + 0x18A4) /* ECQM发出的Hostx 入队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_2_REG (CSR_MQM_EQM_BASE + 0x18A8) /* ECQM发出的Hostx 入队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_ENQ_CMD_CNT_3_REG (CSR_MQM_EQM_BASE + 0x18AC) /* ECQM发出的Hostx 入队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_0_REG (CSR_MQM_EQM_BASE + 0x18B0) /* ECQM发出的Hostx 出队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_1_REG (CSR_MQM_EQM_BASE + 0x18B4) /* ECQM发出的Hostx 出队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_2_REG (CSR_MQM_EQM_BASE + 0x18B8) /* ECQM发出的Hostx 出队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_DEQ_CMD_CNT_3_REG (CSR_MQM_EQM_BASE + 0x18BC) /* ECQM发出的Hostx 出队命令个数统计 \ + */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x18C0) /* ECQM发出的Hostx 二次出队命令个数统计 */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x18C4) /* ECQM发出的Hostx 二次出队命令个数统计 */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x18C8) /* ECQM发出的Hostx 二次出队命令个数统计 */ +#define CSR_MQM_EQM_EQM_ECQM_HOSTX_SEC_DEQ_CMD_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x18CC) /* ECQM发出的Hostx 二次出队命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x18D0) /* DMAGen发出的Hostx 溢出命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x18D4) /* DMAGen发出的Hostx 溢出命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x18D8) /* DMAGen发出的Hostx 溢出命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_WR_CMD_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x18DC) /* DMAGen发出的Hostx 溢出命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x18E0) /* DMAGen发出的Hostx 回读命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x18E4) /* DMAGen发出的Hostx 回读命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x18E8) /* DMAGen发出的Hostx 回读命令个数统计 */ +#define CSR_MQM_EQM_EQM_DMAGEN_HOSTX_RD_CMD_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x18EC) /* DMAGen发出的Hostx 回读命令个数统计 */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x18F0) /* EQM HOSTx Write DB Count Sended to RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x18F4) /* EQM HOSTx Write DB Count Sended to RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x18F8) /* EQM HOSTx Write DB Count Sended to RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_WR_DB_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x18FC) /* EQM HOSTx Write DB Count Sended to RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1900) /* EQM HOSTx Read DB Count Recieved from RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1904) /* EQM HOSTx Read DB Count Recieved from RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1908) /* EQM HOSTx Read DB Count Recieved from RING. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_RD_DB_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x190C) /* EQM HOSTx Read DB Count Recieved from RING. */ +#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1910) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */ +#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1914) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */ +#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1918) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */ +#define CSR_MQM_EQM_EQM_HOSTX_ENQ_DB_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x191C) /* EQM HOSTx En-queue DB Count from ENQC and IQM. */ +#define CSR_MQM_EQM_EQM_IQM_SEND_DB_CNT_REG (CSR_MQM_EQM_BASE + 0x1920) /* EQM DB Count that be sended to IQM. */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_0_REG \ + (CSR_MQM_EQM_BASE + 0x1930) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \ + CPI,the DB information be recorded to the Count Register). */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_1_REG \ + (CSR_MQM_EQM_BASE + 0x1934) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \ + CPI,the DB information be recorded to the Count Register). */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_2_REG \ + (CSR_MQM_EQM_BASE + 0x1938) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \ + CPI,the DB information be recorded to the Count Register). */ +#define CSR_MQM_EQM_EQM_RING_HOSTX_PRE_RD_DB_CNT_3_REG \ + (CSR_MQM_EQM_BASE + 0x193C) /* EQM HOSTx Pre-Read DB Count Sended from EQM.(When EQM DMA send Read command to \ + CPI,the DB information be recorded to the Count Register). */ +#define CSR_MQM_EQM_EQM_DMA_OUTSTAND_DFX0_REG \ + (CSR_MQM_EQM_BASE + 0x1940) /* EQM Outstand Count Register for DMA Operate. */ +#define CSR_MQM_EQM_EQM_DMA_OUTSTAND_DFX1_REG \ + (CSR_MQM_EQM_BASE + 0x1944) /* EQM Host Outstand Count Register for DMA Operate. */ +#define CSR_MQM_EQM_EQM_ECC_1BIT_ERR_CNT_REG (CSR_MQM_EQM_BASE + 0x1948) /* EQM Memory ECC 1bit count */ +#define CSR_MQM_EQM_EQM_ECC_2BIT_ERR_CNT_REG (CSR_MQM_EQM_BASE + 0x194C) /* EQM Memory ECC 2bit count */ + +/* MQM_MSC Base address of Module's Register */ +#define CSR_MQM_MSC_BASE (0xC000) + +/* **************************************************************************** */ +/* MQM_MSC Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_MSC_MSC_RW_RSV0_REG (CSR_MQM_MSC_BASE + 0x0) /* MSC reserved rw register. */ +#define CSR_MQM_MSC_MSC_RW_RSV1_REG (CSR_MQM_MSC_BASE + 0x4) /* MSC reserved rw register. */ +#define CSR_MQM_MSC_MSC_RW_RSV2_REG (CSR_MQM_MSC_BASE + 0x8) /* MSC reserved rw register. */ +#define CSR_MQM_MSC_MSC_RW_RSV3_REG (CSR_MQM_MSC_BASE + 0xC) /* MSC reserved rw register. */ +#define CSR_MQM_MSC_MSC_INDRECT_CTRL_REG (CSR_MQM_MSC_BASE + 0x10) /* Indirect access ctrl Register。 */ +#define CSR_MQM_MSC_MSC_INDRECT_TIMEOUT_REG (CSR_MQM_MSC_BASE + 0x14) /* Indirect Access Timeout Register。 */ +#define CSR_MQM_MSC_MSC_INDRECT_DATA_0_REG (CSR_MQM_MSC_BASE + 0x18) /* Indirect Access Data Register BIT63_32 */ +#define CSR_MQM_MSC_MSC_INDRECT_DATA_1_REG (CSR_MQM_MSC_BASE + 0x1C) /* Indirect Access Data Register BIT31_0 */ +#define CSR_MQM_MSC_MSC_MEM_ECC_BYPASS_EN_REG (CSR_MQM_MSC_BASE + 0x20) /* RAM ECC BYPASS控制寄存器 */ +#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_MSC_BASE + 0x24) /* RAM CTRL_BUS寄存器0 */ +#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_MSC_BASE + 0x28) /* RAM CTRL_BUS寄存器1 */ +#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_MSC_BASE + 0x2C) /* RAM CTRL_BUS寄存器2 */ +#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_MSC_BASE + 0x30) /* RAM CTRL_BUS寄存器3 */ +#define CSR_MQM_MSC_MSC_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_MSC_BASE + 0x34) /* RAM CTRL_BUS寄存器4 */ +#define CSR_MQM_MSC_MSC_INT_VECTOR_REG (CSR_MQM_MSC_BASE + 0x100) /* MSC ERROR INT VECTOR */ +#define CSR_MQM_MSC_MSC_INT_REG (CSR_MQM_MSC_BASE + 0x104) /* MSC ERROR INT */ +#define CSR_MQM_MSC_MSC_INT_EN_REG (CSR_MQM_MSC_BASE + 0x108) /* MSC ERROR ENABLE */ +#define CSR_MQM_MSC_MSC_MEM_ERR_REQ0_REG (CSR_MQM_MSC_BASE + 0x10C) /* Msc mem Error Request register0. */ +#define CSR_MQM_MSC_MSC_MEM_ERR_REQ1_REG (CSR_MQM_MSC_BASE + 0x110) /* Msc mem Error Request registe1. */ +#define CSR_MQM_MSC_MSC_MEM_ERR_REQ2_REG (CSR_MQM_MSC_BASE + 0x114) /* Msc mem Error Request registe2. */ +#define CSR_MQM_MSC_MSC_MEM_ERR_REQ3_REG (CSR_MQM_MSC_BASE + 0x118) /* Msc mem Error Request registe3. */ +#define CSR_MQM_MSC_MSC_MEM_ERR_REQ4_REG (CSR_MQM_MSC_BASE + 0x11C) /* Msc mem Error Request registe4. */ +#define CSR_MQM_MSC_MSC_ECC_ONE_BIT_INT_REG (CSR_MQM_MSC_BASE + 0x120) /* RAM ECC ONE BIT ERROR */ +#define CSR_MQM_MSC_MSC_ECC_TWO_BIT_INT_REG (CSR_MQM_MSC_BASE + 0x124) /* RAM ECC TWO BIT ERROR */ +#define CSR_MQM_MSC_MSC_MQ_BIND_INT_REG (CSR_MQM_MSC_BASE + 0x128) /* MQ MAPPING CONFIG ERROR */ +#define CSR_MQM_MSC_MSC_VNIC_SPCNT_INF_INT_REG (CSR_MQM_MSC_BASE + 0x12C) /* VF SPCNT Interface ERROR */ +#define CSR_MQM_MSC_MSC_VNIC_SPCNT_CAL_INT_REG (CSR_MQM_MSC_BASE + 0x130) /* VF SPCNT Calculation ERROR */ +#define CSR_MQM_MSC_MSC_SOCEP_SPCNT_INF_INT_REG (CSR_MQM_MSC_BASE + 0x134) /* SOCEP SPCNT Interface ERROR */ +#define CSR_MQM_MSC_MSC_SOCEP_SPCNT_CAL_INT_REG (CSR_MQM_MSC_BASE + 0x138) /* SOCEP SPCNT Calculation ERROR */ +#define CSR_MQM_MSC_MSC_FIFO_INT0_REG (CSR_MQM_MSC_BASE + 0x150) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT0_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x154) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT1_REG (CSR_MQM_MSC_BASE + 0x158) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT1_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x15C) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT2_REG (CSR_MQM_MSC_BASE + 0x160) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT2_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x164) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT3_REG (CSR_MQM_MSC_BASE + 0x168) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT3_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x16C) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT4_REG (CSR_MQM_MSC_BASE + 0x170) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT4_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x174) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT5_REG (CSR_MQM_MSC_BASE + 0x178) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT5_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x17C) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT6_REG (CSR_MQM_MSC_BASE + 0x180) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT6_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x184) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_FIFO_INT7_REG (CSR_MQM_MSC_BASE + 0x188) /* FIFO interrupt,include write int and read int */ +#define CSR_MQM_MSC_MSC_FIFO_INT7_MASK_REG \ + (CSR_MQM_MSC_BASE + 0x18C) /* FIFO interrupt,include write int and read init mask */ +#define CSR_MQM_MSC_MSC_BP_DELAY_CNT_REG (CSR_MQM_MSC_BASE + 0x200) /* MSC EP and Cos backpress delay cnt */ +#define CSR_MQM_MSC_MSC_VF_SP_CNT_EN_REG (CSR_MQM_MSC_BASE + 0x204) /* MSC VF SP CNT EN */ +#define CSR_MQM_MSC_PRESUB_PKTLEN_NS_STF_REG (CSR_MQM_MSC_BASE + 0x250) /* Normal Service pre-subtract the pktlen */ +#define CSR_MQM_MSC_PRESUB_PKTLEN_NS_STL_REG (CSR_MQM_MSC_BASE + 0x254) /* Normal Service pre-subtract the pktlen */ +#define CSR_MQM_MSC_CMQ_PRESUB_PKTLEN_CS_REG (CSR_MQM_MSC_BASE + 0x258) /* CMQ pre-subtract the pktlen */ +#define CSR_MQM_MSC_NFMQ_PRESUB_PKTLEN_CS_REG (CSR_MQM_MSC_BASE + 0x25C) /* NFMQ pre-subtract the pktlen */ +#define CSR_MQM_MSC_PRESUB_PKTNUM_REG (CSR_MQM_MSC_BASE + 0x260) /* MSC pre-subtract the pktnum */ +#define CSR_MQM_MSC_PRESUB_PKTLEN_SOCNMQ_REG \ + (CSR_MQM_MSC_BASE + 0x264) /* Normal Service pre-subtract the pktlen For SOCMSC */ +#define CSR_MQM_MSC_PRESUB_PKTLEN_SOCCMQ_REG \ + (CSR_MQM_MSC_BASE + 0x268) /* Command Service pre-subtract the pktlen For SOCMSC */ +#define CSR_MQM_MSC_PRESUB_PKTNUM_SOC_REG (CSR_MQM_MSC_BASE + 0x26C) /* MSC pre-subtract the pktnum for SOCMSC */ +#define CSR_MQM_MSC_MSC_PPS_SHAPER_CFG_PKTLEN_REG (CSR_MQM_MSC_BASE + 0x270) /* MSC Shaper Config Pktlen */ +#define CSR_MQM_MSC_MSC_ROOT_CRR_WEIGHT_CFG_REG (CSR_MQM_MSC_BASE + 0x274) /* MSC ROOT CRR WEIGHT Config */ +#define CSR_MQM_MSC_SOCMSC_ROOT_SCH_WGT_CFG_REG (CSR_MQM_MSC_BASE + 0x278) /* SOC MSC ROOT SCH Weight Config */ +#define CSR_MQM_MSC_WEIGHT_NS_OFFSET_REG (CSR_MQM_MSC_BASE + 0x27C) /* Normal queue weight offset */ +#define CSR_MQM_MSC_WEIGHT_CS_OFFSET_REG (CSR_MQM_MSC_BASE + 0x280) /* Command queue weight offset */ +#define CSR_MQM_MSC_WEIGHT_MSCSOC_OFFSET_REG (CSR_MQM_MSC_BASE + 0x284) /* SOC MSCl queue weight offset */ +#define CSR_MQM_MSC_HOST_WEIGHT_NS_REG (CSR_MQM_MSC_BASE + 0x288) /* Normal MQ host weight */ +#define CSR_MQM_MSC_HOST_WEIGHT_CS_REG (CSR_MQM_MSC_BASE + 0x28C) /* CMQ Host Node Weight Configuration Table */ +#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_0_REG (CSR_MQM_MSC_BASE + 0x2F0) /* CS QA Node Weight Configuration Table for CS \ + */ +#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_1_REG (CSR_MQM_MSC_BASE + 0x2F4) /* CS QA Node Weight Configuration Table for CS \ + */ +#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_2_REG (CSR_MQM_MSC_BASE + 0x2F8) /* CS QA Node Weight Configuration Table for CS \ + */ +#define CSR_MQM_MSC_QA_WEIGHT_CFG_CS_3_REG (CSR_MQM_MSC_BASE + 0x2FC) /* CS QA Node Weight Configuration Table for CS \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_0_REG (CSR_MQM_MSC_BASE + 0x300) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_1_REG (CSR_MQM_MSC_BASE + 0x304) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_2_REG (CSR_MQM_MSC_BASE + 0x308) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_3_REG (CSR_MQM_MSC_BASE + 0x30C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_4_REG (CSR_MQM_MSC_BASE + 0x310) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_5_REG (CSR_MQM_MSC_BASE + 0x314) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_6_REG (CSR_MQM_MSC_BASE + 0x318) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_7_REG (CSR_MQM_MSC_BASE + 0x31C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_8_REG (CSR_MQM_MSC_BASE + 0x320) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_9_REG (CSR_MQM_MSC_BASE + 0x324) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_10_REG (CSR_MQM_MSC_BASE + 0x328) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_11_REG (CSR_MQM_MSC_BASE + 0x32C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_12_REG (CSR_MQM_MSC_BASE + 0x330) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_13_REG (CSR_MQM_MSC_BASE + 0x334) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_14_REG (CSR_MQM_MSC_BASE + 0x338) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_15_REG (CSR_MQM_MSC_BASE + 0x33C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_16_REG (CSR_MQM_MSC_BASE + 0x340) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_17_REG (CSR_MQM_MSC_BASE + 0x344) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_18_REG (CSR_MQM_MSC_BASE + 0x348) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_19_REG (CSR_MQM_MSC_BASE + 0x34C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_20_REG (CSR_MQM_MSC_BASE + 0x350) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_21_REG (CSR_MQM_MSC_BASE + 0x354) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_22_REG (CSR_MQM_MSC_BASE + 0x358) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_23_REG (CSR_MQM_MSC_BASE + 0x35C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_24_REG (CSR_MQM_MSC_BASE + 0x360) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_25_REG (CSR_MQM_MSC_BASE + 0x364) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_26_REG (CSR_MQM_MSC_BASE + 0x368) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_27_REG (CSR_MQM_MSC_BASE + 0x36C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_28_REG (CSR_MQM_MSC_BASE + 0x370) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_29_REG (CSR_MQM_MSC_BASE + 0x374) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_30_REG (CSR_MQM_MSC_BASE + 0x378) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NS_31_REG (CSR_MQM_MSC_BASE + 0x37C) /* EP Node Weight Configuration Table for NS */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_0_REG (CSR_MQM_MSC_BASE + 0x380) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_1_REG (CSR_MQM_MSC_BASE + 0x384) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_2_REG (CSR_MQM_MSC_BASE + 0x388) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_3_REG (CSR_MQM_MSC_BASE + 0x38C) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_4_REG (CSR_MQM_MSC_BASE + 0x390) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_5_REG (CSR_MQM_MSC_BASE + 0x394) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_6_REG (CSR_MQM_MSC_BASE + 0x398) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_7_REG (CSR_MQM_MSC_BASE + 0x39C) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_8_REG (CSR_MQM_MSC_BASE + 0x3A0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_9_REG (CSR_MQM_MSC_BASE + 0x3A4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_10_REG (CSR_MQM_MSC_BASE + 0x3A8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_11_REG (CSR_MQM_MSC_BASE + 0x3AC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_12_REG (CSR_MQM_MSC_BASE + 0x3B0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_13_REG (CSR_MQM_MSC_BASE + 0x3B4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_14_REG (CSR_MQM_MSC_BASE + 0x3B8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_15_REG (CSR_MQM_MSC_BASE + 0x3BC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_16_REG (CSR_MQM_MSC_BASE + 0x3C0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_17_REG (CSR_MQM_MSC_BASE + 0x3C4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_18_REG (CSR_MQM_MSC_BASE + 0x3C8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_19_REG (CSR_MQM_MSC_BASE + 0x3CC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_20_REG (CSR_MQM_MSC_BASE + 0x3D0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_21_REG (CSR_MQM_MSC_BASE + 0x3D4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_22_REG (CSR_MQM_MSC_BASE + 0x3D8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_23_REG (CSR_MQM_MSC_BASE + 0x3DC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_24_REG (CSR_MQM_MSC_BASE + 0x3E0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_25_REG (CSR_MQM_MSC_BASE + 0x3E4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_26_REG (CSR_MQM_MSC_BASE + 0x3E8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_27_REG (CSR_MQM_MSC_BASE + 0x3EC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_28_REG (CSR_MQM_MSC_BASE + 0x3F0) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_29_REG (CSR_MQM_MSC_BASE + 0x3F4) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_30_REG (CSR_MQM_MSC_BASE + 0x3F8) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_CMQ_31_REG (CSR_MQM_MSC_BASE + 0x3FC) /* EP Node Weight Configuration Table for CMQ \ + */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_0_REG \ + (CSR_MQM_MSC_BASE + 0x400) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_1_REG \ + (CSR_MQM_MSC_BASE + 0x404) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_2_REG \ + (CSR_MQM_MSC_BASE + 0x408) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_3_REG \ + (CSR_MQM_MSC_BASE + 0x40C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_4_REG \ + (CSR_MQM_MSC_BASE + 0x410) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_5_REG \ + (CSR_MQM_MSC_BASE + 0x414) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_6_REG \ + (CSR_MQM_MSC_BASE + 0x418) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_7_REG \ + (CSR_MQM_MSC_BASE + 0x41C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_8_REG \ + (CSR_MQM_MSC_BASE + 0x420) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_9_REG \ + (CSR_MQM_MSC_BASE + 0x424) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_10_REG \ + (CSR_MQM_MSC_BASE + 0x428) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_11_REG \ + (CSR_MQM_MSC_BASE + 0x42C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_12_REG \ + (CSR_MQM_MSC_BASE + 0x430) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_13_REG \ + (CSR_MQM_MSC_BASE + 0x434) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_14_REG \ + (CSR_MQM_MSC_BASE + 0x438) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_15_REG \ + (CSR_MQM_MSC_BASE + 0x43C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_16_REG \ + (CSR_MQM_MSC_BASE + 0x440) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_17_REG \ + (CSR_MQM_MSC_BASE + 0x444) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_18_REG \ + (CSR_MQM_MSC_BASE + 0x448) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_19_REG \ + (CSR_MQM_MSC_BASE + 0x44C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_20_REG \ + (CSR_MQM_MSC_BASE + 0x450) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_21_REG \ + (CSR_MQM_MSC_BASE + 0x454) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_22_REG \ + (CSR_MQM_MSC_BASE + 0x458) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_23_REG \ + (CSR_MQM_MSC_BASE + 0x45C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_24_REG \ + (CSR_MQM_MSC_BASE + 0x460) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_25_REG \ + (CSR_MQM_MSC_BASE + 0x464) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_26_REG \ + (CSR_MQM_MSC_BASE + 0x468) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_27_REG \ + (CSR_MQM_MSC_BASE + 0x46C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_28_REG \ + (CSR_MQM_MSC_BASE + 0x470) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_29_REG \ + (CSR_MQM_MSC_BASE + 0x474) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_30_REG \ + (CSR_MQM_MSC_BASE + 0x478) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_WEIGHT_CFG_NFMQ_31_REG \ + (CSR_MQM_MSC_BASE + 0x47C) /* EP Node Weight Configuration Table for NFMQ */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_0_REG (CSR_MQM_MSC_BASE + 0x500) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_1_REG (CSR_MQM_MSC_BASE + 0x504) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_2_REG (CSR_MQM_MSC_BASE + 0x508) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_3_REG (CSR_MQM_MSC_BASE + 0x50C) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_4_REG (CSR_MQM_MSC_BASE + 0x510) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_5_REG (CSR_MQM_MSC_BASE + 0x514) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_6_REG (CSR_MQM_MSC_BASE + 0x518) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_7_REG (CSR_MQM_MSC_BASE + 0x51C) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_8_REG (CSR_MQM_MSC_BASE + 0x520) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_9_REG (CSR_MQM_MSC_BASE + 0x524) /* SOCMSC MQ Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_10_REG (CSR_MQM_MSC_BASE + 0x528) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_11_REG (CSR_MQM_MSC_BASE + 0x52C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_12_REG (CSR_MQM_MSC_BASE + 0x530) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_13_REG (CSR_MQM_MSC_BASE + 0x534) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_14_REG (CSR_MQM_MSC_BASE + 0x538) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_15_REG (CSR_MQM_MSC_BASE + 0x53C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_16_REG (CSR_MQM_MSC_BASE + 0x540) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_17_REG (CSR_MQM_MSC_BASE + 0x544) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_18_REG (CSR_MQM_MSC_BASE + 0x548) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_19_REG (CSR_MQM_MSC_BASE + 0x54C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_20_REG (CSR_MQM_MSC_BASE + 0x550) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_21_REG (CSR_MQM_MSC_BASE + 0x554) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_22_REG (CSR_MQM_MSC_BASE + 0x558) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_23_REG (CSR_MQM_MSC_BASE + 0x55C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_24_REG (CSR_MQM_MSC_BASE + 0x560) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_25_REG (CSR_MQM_MSC_BASE + 0x564) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_26_REG (CSR_MQM_MSC_BASE + 0x568) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_27_REG (CSR_MQM_MSC_BASE + 0x56C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_28_REG (CSR_MQM_MSC_BASE + 0x570) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_29_REG (CSR_MQM_MSC_BASE + 0x574) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_30_REG (CSR_MQM_MSC_BASE + 0x578) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_31_REG (CSR_MQM_MSC_BASE + 0x57C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_32_REG (CSR_MQM_MSC_BASE + 0x580) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_33_REG (CSR_MQM_MSC_BASE + 0x584) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_34_REG (CSR_MQM_MSC_BASE + 0x588) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_35_REG (CSR_MQM_MSC_BASE + 0x58C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_36_REG (CSR_MQM_MSC_BASE + 0x590) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_37_REG (CSR_MQM_MSC_BASE + 0x594) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_38_REG (CSR_MQM_MSC_BASE + 0x598) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_39_REG (CSR_MQM_MSC_BASE + 0x59C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_40_REG (CSR_MQM_MSC_BASE + 0x5A0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_41_REG (CSR_MQM_MSC_BASE + 0x5A4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_42_REG (CSR_MQM_MSC_BASE + 0x5A8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_43_REG (CSR_MQM_MSC_BASE + 0x5AC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_44_REG (CSR_MQM_MSC_BASE + 0x5B0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_45_REG (CSR_MQM_MSC_BASE + 0x5B4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_46_REG (CSR_MQM_MSC_BASE + 0x5B8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_47_REG (CSR_MQM_MSC_BASE + 0x5BC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_48_REG (CSR_MQM_MSC_BASE + 0x5C0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_49_REG (CSR_MQM_MSC_BASE + 0x5C4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_50_REG (CSR_MQM_MSC_BASE + 0x5C8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_51_REG (CSR_MQM_MSC_BASE + 0x5CC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_52_REG (CSR_MQM_MSC_BASE + 0x5D0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_53_REG (CSR_MQM_MSC_BASE + 0x5D4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_54_REG (CSR_MQM_MSC_BASE + 0x5D8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_55_REG (CSR_MQM_MSC_BASE + 0x5DC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_56_REG (CSR_MQM_MSC_BASE + 0x5E0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_57_REG (CSR_MQM_MSC_BASE + 0x5E4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_58_REG (CSR_MQM_MSC_BASE + 0x5E8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_59_REG (CSR_MQM_MSC_BASE + 0x5EC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_60_REG (CSR_MQM_MSC_BASE + 0x5F0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_61_REG (CSR_MQM_MSC_BASE + 0x5F4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_62_REG (CSR_MQM_MSC_BASE + 0x5F8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_63_REG (CSR_MQM_MSC_BASE + 0x5FC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_64_REG (CSR_MQM_MSC_BASE + 0x600) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_65_REG (CSR_MQM_MSC_BASE + 0x604) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_66_REG (CSR_MQM_MSC_BASE + 0x608) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_67_REG (CSR_MQM_MSC_BASE + 0x60C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_68_REG (CSR_MQM_MSC_BASE + 0x610) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_69_REG (CSR_MQM_MSC_BASE + 0x614) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_70_REG (CSR_MQM_MSC_BASE + 0x618) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_71_REG (CSR_MQM_MSC_BASE + 0x61C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_72_REG (CSR_MQM_MSC_BASE + 0x620) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_73_REG (CSR_MQM_MSC_BASE + 0x624) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_74_REG (CSR_MQM_MSC_BASE + 0x628) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_75_REG (CSR_MQM_MSC_BASE + 0x62C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_76_REG (CSR_MQM_MSC_BASE + 0x630) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_77_REG (CSR_MQM_MSC_BASE + 0x634) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_78_REG (CSR_MQM_MSC_BASE + 0x638) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_79_REG (CSR_MQM_MSC_BASE + 0x63C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_80_REG (CSR_MQM_MSC_BASE + 0x640) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_81_REG (CSR_MQM_MSC_BASE + 0x644) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_82_REG (CSR_MQM_MSC_BASE + 0x648) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_83_REG (CSR_MQM_MSC_BASE + 0x64C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_84_REG (CSR_MQM_MSC_BASE + 0x650) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_85_REG (CSR_MQM_MSC_BASE + 0x654) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_86_REG (CSR_MQM_MSC_BASE + 0x658) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_87_REG (CSR_MQM_MSC_BASE + 0x65C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_88_REG (CSR_MQM_MSC_BASE + 0x660) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_89_REG (CSR_MQM_MSC_BASE + 0x664) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_90_REG (CSR_MQM_MSC_BASE + 0x668) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_91_REG (CSR_MQM_MSC_BASE + 0x66C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_92_REG (CSR_MQM_MSC_BASE + 0x670) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_93_REG (CSR_MQM_MSC_BASE + 0x674) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_94_REG (CSR_MQM_MSC_BASE + 0x678) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_95_REG (CSR_MQM_MSC_BASE + 0x67C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_96_REG (CSR_MQM_MSC_BASE + 0x680) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_97_REG (CSR_MQM_MSC_BASE + 0x684) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_98_REG (CSR_MQM_MSC_BASE + 0x688) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_99_REG (CSR_MQM_MSC_BASE + 0x68C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_100_REG (CSR_MQM_MSC_BASE + 0x690) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_101_REG (CSR_MQM_MSC_BASE + 0x694) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_102_REG (CSR_MQM_MSC_BASE + 0x698) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_103_REG (CSR_MQM_MSC_BASE + 0x69C) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_104_REG (CSR_MQM_MSC_BASE + 0x6A0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_105_REG (CSR_MQM_MSC_BASE + 0x6A4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_106_REG (CSR_MQM_MSC_BASE + 0x6A8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_107_REG (CSR_MQM_MSC_BASE + 0x6AC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_108_REG (CSR_MQM_MSC_BASE + 0x6B0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_109_REG (CSR_MQM_MSC_BASE + 0x6B4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_110_REG (CSR_MQM_MSC_BASE + 0x6B8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_111_REG (CSR_MQM_MSC_BASE + 0x6BC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_112_REG (CSR_MQM_MSC_BASE + 0x6C0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_113_REG (CSR_MQM_MSC_BASE + 0x6C4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_114_REG (CSR_MQM_MSC_BASE + 0x6C8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_115_REG (CSR_MQM_MSC_BASE + 0x6CC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_116_REG (CSR_MQM_MSC_BASE + 0x6D0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_117_REG (CSR_MQM_MSC_BASE + 0x6D4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_118_REG (CSR_MQM_MSC_BASE + 0x6D8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_119_REG (CSR_MQM_MSC_BASE + 0x6DC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_120_REG (CSR_MQM_MSC_BASE + 0x6E0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_121_REG (CSR_MQM_MSC_BASE + 0x6E4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_122_REG (CSR_MQM_MSC_BASE + 0x6E8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_123_REG (CSR_MQM_MSC_BASE + 0x6EC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_124_REG (CSR_MQM_MSC_BASE + 0x6F0) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_125_REG (CSR_MQM_MSC_BASE + 0x6F4) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_126_REG (CSR_MQM_MSC_BASE + 0x6F8) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_MQ_WEIGHT_CFG_127_REG (CSR_MQM_MSC_BASE + 0x6FC) /* SOCMSC MQ Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_0_REG (CSR_MQM_MSC_BASE + 0x700) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_1_REG (CSR_MQM_MSC_BASE + 0x704) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_2_REG (CSR_MQM_MSC_BASE + 0x708) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_3_REG (CSR_MQM_MSC_BASE + 0x70C) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_4_REG (CSR_MQM_MSC_BASE + 0x710) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_5_REG (CSR_MQM_MSC_BASE + 0x714) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_6_REG (CSR_MQM_MSC_BASE + 0x718) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_7_REG (CSR_MQM_MSC_BASE + 0x71C) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_8_REG (CSR_MQM_MSC_BASE + 0x720) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_9_REG (CSR_MQM_MSC_BASE + 0x724) /* SOCMSC EP Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_10_REG (CSR_MQM_MSC_BASE + 0x728) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_11_REG (CSR_MQM_MSC_BASE + 0x72C) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_12_REG (CSR_MQM_MSC_BASE + 0x730) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_13_REG (CSR_MQM_MSC_BASE + 0x734) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_14_REG (CSR_MQM_MSC_BASE + 0x738) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_EP_WEIGHT_CFG_15_REG (CSR_MQM_MSC_BASE + 0x73C) /* SOCMSC EP Node Weight Configuration Table \ + */ +#define CSR_MQM_MSC_SOC_SERV_WEIGHT_CFG_0_REG \ + (CSR_MQM_MSC_BASE + 0x740) /* SOCMSC SERVICE Node Weight Configuration Table */ +#define CSR_MQM_MSC_SOC_SERV_WEIGHT_CFG_1_REG \ + (CSR_MQM_MSC_BASE + 0x744) /* SOCMSC SERVICE Node Weight Configuration Table */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_0_REG \ + (CSR_MQM_MSC_BASE + 0x750) /* HOST Node Shaper BPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_1_REG \ + (CSR_MQM_MSC_BASE + 0x754) /* HOST Node Shaper BPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_2_REG \ + (CSR_MQM_MSC_BASE + 0x758) /* HOST Node Shaper BPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_CS_3_REG \ + (CSR_MQM_MSC_BASE + 0x75C) /* HOST Node Shaper BPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_0_REG \ + (CSR_MQM_MSC_BASE + 0x760) /* HOST Node Shaper PPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_1_REG \ + (CSR_MQM_MSC_BASE + 0x764) /* HOST Node Shaper PPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_2_REG \ + (CSR_MQM_MSC_BASE + 0x768) /* HOST Node Shaper PPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_CS_3_REG \ + (CSR_MQM_MSC_BASE + 0x76C) /* HOST Node Shaper PPS Configuration Table for CS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_0_REG \ + (CSR_MQM_MSC_BASE + 0x770) /* HOST Node Shaper BPS_Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_1_REG \ + (CSR_MQM_MSC_BASE + 0x774) /* HOST Node Shaper BPS_Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_2_REG \ + (CSR_MQM_MSC_BASE + 0x778) /* HOST Node Shaper BPS_Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_BPS_CFG_NS_3_REG \ + (CSR_MQM_MSC_BASE + 0x77C) /* HOST Node Shaper BPS_Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_0_REG \ + (CSR_MQM_MSC_BASE + 0x780) /* HOST Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_1_REG \ + (CSR_MQM_MSC_BASE + 0x784) /* HOST Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_2_REG \ + (CSR_MQM_MSC_BASE + 0x788) /* HOST Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_HOST_SHAP_PPS_CFG_NS_3_REG \ + (CSR_MQM_MSC_BASE + 0x78C) /* HOST Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_0_REG \ + (CSR_MQM_MSC_BASE + 0x790) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_1_REG \ + (CSR_MQM_MSC_BASE + 0x794) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_2_REG \ + (CSR_MQM_MSC_BASE + 0x798) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_3_REG \ + (CSR_MQM_MSC_BASE + 0x79C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_4_REG \ + (CSR_MQM_MSC_BASE + 0x7A0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_5_REG \ + (CSR_MQM_MSC_BASE + 0x7A4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_6_REG \ + (CSR_MQM_MSC_BASE + 0x7A8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_7_REG \ + (CSR_MQM_MSC_BASE + 0x7AC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_8_REG \ + (CSR_MQM_MSC_BASE + 0x7B0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_9_REG \ + (CSR_MQM_MSC_BASE + 0x7B4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_10_REG \ + (CSR_MQM_MSC_BASE + 0x7B8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_11_REG \ + (CSR_MQM_MSC_BASE + 0x7BC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_12_REG \ + (CSR_MQM_MSC_BASE + 0x7C0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_13_REG \ + (CSR_MQM_MSC_BASE + 0x7C4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_14_REG \ + (CSR_MQM_MSC_BASE + 0x7C8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_15_REG \ + (CSR_MQM_MSC_BASE + 0x7CC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_16_REG \ + (CSR_MQM_MSC_BASE + 0x7D0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_17_REG \ + (CSR_MQM_MSC_BASE + 0x7D4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_18_REG \ + (CSR_MQM_MSC_BASE + 0x7D8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_19_REG \ + (CSR_MQM_MSC_BASE + 0x7DC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_20_REG \ + (CSR_MQM_MSC_BASE + 0x7E0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_21_REG \ + (CSR_MQM_MSC_BASE + 0x7E4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_22_REG \ + (CSR_MQM_MSC_BASE + 0x7E8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_23_REG \ + (CSR_MQM_MSC_BASE + 0x7EC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_24_REG \ + (CSR_MQM_MSC_BASE + 0x7F0) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_25_REG \ + (CSR_MQM_MSC_BASE + 0x7F4) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_26_REG \ + (CSR_MQM_MSC_BASE + 0x7F8) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_27_REG \ + (CSR_MQM_MSC_BASE + 0x7FC) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_28_REG \ + (CSR_MQM_MSC_BASE + 0x800) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_29_REG \ + (CSR_MQM_MSC_BASE + 0x804) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_30_REG \ + (CSR_MQM_MSC_BASE + 0x808) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NS_31_REG \ + (CSR_MQM_MSC_BASE + 0x80C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_0_REG \ + (CSR_MQM_MSC_BASE + 0x810) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_1_REG \ + (CSR_MQM_MSC_BASE + 0x814) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_2_REG \ + (CSR_MQM_MSC_BASE + 0x818) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_3_REG \ + (CSR_MQM_MSC_BASE + 0x81C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_4_REG \ + (CSR_MQM_MSC_BASE + 0x820) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_5_REG \ + (CSR_MQM_MSC_BASE + 0x824) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_6_REG \ + (CSR_MQM_MSC_BASE + 0x828) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_7_REG \ + (CSR_MQM_MSC_BASE + 0x82C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_8_REG \ + (CSR_MQM_MSC_BASE + 0x830) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_9_REG \ + (CSR_MQM_MSC_BASE + 0x834) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_10_REG \ + (CSR_MQM_MSC_BASE + 0x838) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_11_REG \ + (CSR_MQM_MSC_BASE + 0x83C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_12_REG \ + (CSR_MQM_MSC_BASE + 0x840) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_13_REG \ + (CSR_MQM_MSC_BASE + 0x844) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_14_REG \ + (CSR_MQM_MSC_BASE + 0x848) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_15_REG \ + (CSR_MQM_MSC_BASE + 0x84C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_16_REG \ + (CSR_MQM_MSC_BASE + 0x850) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_17_REG \ + (CSR_MQM_MSC_BASE + 0x854) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_18_REG \ + (CSR_MQM_MSC_BASE + 0x858) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_19_REG \ + (CSR_MQM_MSC_BASE + 0x85C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_20_REG \ + (CSR_MQM_MSC_BASE + 0x860) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_21_REG \ + (CSR_MQM_MSC_BASE + 0x864) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_22_REG \ + (CSR_MQM_MSC_BASE + 0x868) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_23_REG \ + (CSR_MQM_MSC_BASE + 0x86C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_24_REG \ + (CSR_MQM_MSC_BASE + 0x870) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_25_REG \ + (CSR_MQM_MSC_BASE + 0x874) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_26_REG \ + (CSR_MQM_MSC_BASE + 0x878) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_27_REG \ + (CSR_MQM_MSC_BASE + 0x87C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_28_REG \ + (CSR_MQM_MSC_BASE + 0x880) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_29_REG \ + (CSR_MQM_MSC_BASE + 0x884) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_30_REG \ + (CSR_MQM_MSC_BASE + 0x888) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NS_31_REG \ + (CSR_MQM_MSC_BASE + 0x88C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_0_REG \ + (CSR_MQM_MSC_BASE + 0x890) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_1_REG \ + (CSR_MQM_MSC_BASE + 0x894) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_2_REG \ + (CSR_MQM_MSC_BASE + 0x898) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_3_REG \ + (CSR_MQM_MSC_BASE + 0x89C) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_4_REG \ + (CSR_MQM_MSC_BASE + 0x8A0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_5_REG \ + (CSR_MQM_MSC_BASE + 0x8A4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_6_REG \ + (CSR_MQM_MSC_BASE + 0x8A8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_7_REG \ + (CSR_MQM_MSC_BASE + 0x8AC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_8_REG \ + (CSR_MQM_MSC_BASE + 0x8B0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_9_REG \ + (CSR_MQM_MSC_BASE + 0x8B4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_10_REG \ + (CSR_MQM_MSC_BASE + 0x8B8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_11_REG \ + (CSR_MQM_MSC_BASE + 0x8BC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_12_REG \ + (CSR_MQM_MSC_BASE + 0x8C0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_13_REG \ + (CSR_MQM_MSC_BASE + 0x8C4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_14_REG \ + (CSR_MQM_MSC_BASE + 0x8C8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_15_REG \ + (CSR_MQM_MSC_BASE + 0x8CC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_16_REG \ + (CSR_MQM_MSC_BASE + 0x8D0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_17_REG \ + (CSR_MQM_MSC_BASE + 0x8D4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_18_REG \ + (CSR_MQM_MSC_BASE + 0x8D8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_19_REG \ + (CSR_MQM_MSC_BASE + 0x8DC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_20_REG \ + (CSR_MQM_MSC_BASE + 0x8E0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_21_REG \ + (CSR_MQM_MSC_BASE + 0x8E4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_22_REG \ + (CSR_MQM_MSC_BASE + 0x8E8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_23_REG \ + (CSR_MQM_MSC_BASE + 0x8EC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_24_REG \ + (CSR_MQM_MSC_BASE + 0x8F0) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_25_REG \ + (CSR_MQM_MSC_BASE + 0x8F4) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_26_REG \ + (CSR_MQM_MSC_BASE + 0x8F8) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_27_REG \ + (CSR_MQM_MSC_BASE + 0x8FC) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_28_REG \ + (CSR_MQM_MSC_BASE + 0x900) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_29_REG \ + (CSR_MQM_MSC_BASE + 0x904) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_30_REG \ + (CSR_MQM_MSC_BASE + 0x908) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_CMQ_31_REG \ + (CSR_MQM_MSC_BASE + 0x90C) /* EP Node Shaper BPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_0_REG \ + (CSR_MQM_MSC_BASE + 0x910) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_1_REG \ + (CSR_MQM_MSC_BASE + 0x914) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_2_REG \ + (CSR_MQM_MSC_BASE + 0x918) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_3_REG \ + (CSR_MQM_MSC_BASE + 0x91C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_4_REG \ + (CSR_MQM_MSC_BASE + 0x920) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_5_REG \ + (CSR_MQM_MSC_BASE + 0x924) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_6_REG \ + (CSR_MQM_MSC_BASE + 0x928) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_7_REG \ + (CSR_MQM_MSC_BASE + 0x92C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_8_REG \ + (CSR_MQM_MSC_BASE + 0x930) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_9_REG \ + (CSR_MQM_MSC_BASE + 0x934) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_10_REG \ + (CSR_MQM_MSC_BASE + 0x938) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_11_REG \ + (CSR_MQM_MSC_BASE + 0x93C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_12_REG \ + (CSR_MQM_MSC_BASE + 0x940) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_13_REG \ + (CSR_MQM_MSC_BASE + 0x944) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_14_REG \ + (CSR_MQM_MSC_BASE + 0x948) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_15_REG \ + (CSR_MQM_MSC_BASE + 0x94C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_16_REG \ + (CSR_MQM_MSC_BASE + 0x950) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_17_REG \ + (CSR_MQM_MSC_BASE + 0x954) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_18_REG \ + (CSR_MQM_MSC_BASE + 0x958) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_19_REG \ + (CSR_MQM_MSC_BASE + 0x95C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_20_REG \ + (CSR_MQM_MSC_BASE + 0x960) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_21_REG \ + (CSR_MQM_MSC_BASE + 0x964) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_22_REG \ + (CSR_MQM_MSC_BASE + 0x968) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_23_REG \ + (CSR_MQM_MSC_BASE + 0x96C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_24_REG \ + (CSR_MQM_MSC_BASE + 0x970) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_25_REG \ + (CSR_MQM_MSC_BASE + 0x974) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_26_REG \ + (CSR_MQM_MSC_BASE + 0x978) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_27_REG \ + (CSR_MQM_MSC_BASE + 0x97C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_28_REG \ + (CSR_MQM_MSC_BASE + 0x980) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_29_REG \ + (CSR_MQM_MSC_BASE + 0x984) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_30_REG \ + (CSR_MQM_MSC_BASE + 0x988) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_CMQ_31_REG \ + (CSR_MQM_MSC_BASE + 0x98C) /* EP Node Shaper PPS Configuration Table for CMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_0_REG \ + (CSR_MQM_MSC_BASE + 0x990) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_1_REG \ + (CSR_MQM_MSC_BASE + 0x994) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_2_REG \ + (CSR_MQM_MSC_BASE + 0x998) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_3_REG \ + (CSR_MQM_MSC_BASE + 0x99C) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_4_REG \ + (CSR_MQM_MSC_BASE + 0x9A0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_5_REG \ + (CSR_MQM_MSC_BASE + 0x9A4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_6_REG \ + (CSR_MQM_MSC_BASE + 0x9A8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_7_REG \ + (CSR_MQM_MSC_BASE + 0x9AC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_8_REG \ + (CSR_MQM_MSC_BASE + 0x9B0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_9_REG \ + (CSR_MQM_MSC_BASE + 0x9B4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_10_REG \ + (CSR_MQM_MSC_BASE + 0x9B8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_11_REG \ + (CSR_MQM_MSC_BASE + 0x9BC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_12_REG \ + (CSR_MQM_MSC_BASE + 0x9C0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_13_REG \ + (CSR_MQM_MSC_BASE + 0x9C4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_14_REG \ + (CSR_MQM_MSC_BASE + 0x9C8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_15_REG \ + (CSR_MQM_MSC_BASE + 0x9CC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_16_REG \ + (CSR_MQM_MSC_BASE + 0x9D0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_17_REG \ + (CSR_MQM_MSC_BASE + 0x9D4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_18_REG \ + (CSR_MQM_MSC_BASE + 0x9D8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_19_REG \ + (CSR_MQM_MSC_BASE + 0x9DC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_20_REG \ + (CSR_MQM_MSC_BASE + 0x9E0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_21_REG \ + (CSR_MQM_MSC_BASE + 0x9E4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_22_REG \ + (CSR_MQM_MSC_BASE + 0x9E8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_23_REG \ + (CSR_MQM_MSC_BASE + 0x9EC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_24_REG \ + (CSR_MQM_MSC_BASE + 0x9F0) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_25_REG \ + (CSR_MQM_MSC_BASE + 0x9F4) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_26_REG \ + (CSR_MQM_MSC_BASE + 0x9F8) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_27_REG \ + (CSR_MQM_MSC_BASE + 0x9FC) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_28_REG \ + (CSR_MQM_MSC_BASE + 0xA00) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_29_REG \ + (CSR_MQM_MSC_BASE + 0xA04) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_30_REG \ + (CSR_MQM_MSC_BASE + 0xA08) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_BPS_CFG_NFMQ_31_REG \ + (CSR_MQM_MSC_BASE + 0xA0C) /* EP Node Shaper BPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_0_REG \ + (CSR_MQM_MSC_BASE + 0xA10) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_1_REG \ + (CSR_MQM_MSC_BASE + 0xA14) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_2_REG \ + (CSR_MQM_MSC_BASE + 0xA18) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_3_REG \ + (CSR_MQM_MSC_BASE + 0xA1C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_4_REG \ + (CSR_MQM_MSC_BASE + 0xA20) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_5_REG \ + (CSR_MQM_MSC_BASE + 0xA24) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_6_REG \ + (CSR_MQM_MSC_BASE + 0xA28) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_7_REG \ + (CSR_MQM_MSC_BASE + 0xA2C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_8_REG \ + (CSR_MQM_MSC_BASE + 0xA30) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_9_REG \ + (CSR_MQM_MSC_BASE + 0xA34) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_10_REG \ + (CSR_MQM_MSC_BASE + 0xA38) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_11_REG \ + (CSR_MQM_MSC_BASE + 0xA3C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_12_REG \ + (CSR_MQM_MSC_BASE + 0xA40) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_13_REG \ + (CSR_MQM_MSC_BASE + 0xA44) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_14_REG \ + (CSR_MQM_MSC_BASE + 0xA48) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_15_REG \ + (CSR_MQM_MSC_BASE + 0xA4C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_16_REG \ + (CSR_MQM_MSC_BASE + 0xA50) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_17_REG \ + (CSR_MQM_MSC_BASE + 0xA54) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_18_REG \ + (CSR_MQM_MSC_BASE + 0xA58) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_19_REG \ + (CSR_MQM_MSC_BASE + 0xA5C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_20_REG \ + (CSR_MQM_MSC_BASE + 0xA60) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_21_REG \ + (CSR_MQM_MSC_BASE + 0xA64) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_22_REG \ + (CSR_MQM_MSC_BASE + 0xA68) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_23_REG \ + (CSR_MQM_MSC_BASE + 0xA6C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_24_REG \ + (CSR_MQM_MSC_BASE + 0xA70) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_25_REG \ + (CSR_MQM_MSC_BASE + 0xA74) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_26_REG \ + (CSR_MQM_MSC_BASE + 0xA78) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_27_REG \ + (CSR_MQM_MSC_BASE + 0xA7C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_28_REG \ + (CSR_MQM_MSC_BASE + 0xA80) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_29_REG \ + (CSR_MQM_MSC_BASE + 0xA84) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_30_REG \ + (CSR_MQM_MSC_BASE + 0xA88) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_EP_SHAP_PPS_CFG_NFMQ_31_REG \ + (CSR_MQM_MSC_BASE + 0xA8C) /* EP Node Shaper PPS Configuration Table for NFMQ */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xB00) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xB04) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xB08) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xB0C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xB10) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xB14) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xB18) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xB1C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xB20) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xB24) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xB28) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xB2C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xB30) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xB34) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xB38) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xB3C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_16_REG (CSR_MQM_MSC_BASE + 0xB40) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_17_REG (CSR_MQM_MSC_BASE + 0xB44) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_18_REG (CSR_MQM_MSC_BASE + 0xB48) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_19_REG (CSR_MQM_MSC_BASE + 0xB4C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_20_REG (CSR_MQM_MSC_BASE + 0xB50) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_21_REG (CSR_MQM_MSC_BASE + 0xB54) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_22_REG (CSR_MQM_MSC_BASE + 0xB58) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_23_REG (CSR_MQM_MSC_BASE + 0xB5C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_24_REG (CSR_MQM_MSC_BASE + 0xB60) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_25_REG (CSR_MQM_MSC_BASE + 0xB64) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_26_REG (CSR_MQM_MSC_BASE + 0xB68) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_27_REG (CSR_MQM_MSC_BASE + 0xB6C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_28_REG (CSR_MQM_MSC_BASE + 0xB70) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_29_REG (CSR_MQM_MSC_BASE + 0xB74) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_30_REG (CSR_MQM_MSC_BASE + 0xB78) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_31_REG (CSR_MQM_MSC_BASE + 0xB7C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_32_REG (CSR_MQM_MSC_BASE + 0xB80) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_33_REG (CSR_MQM_MSC_BASE + 0xB84) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_34_REG (CSR_MQM_MSC_BASE + 0xB88) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_35_REG (CSR_MQM_MSC_BASE + 0xB8C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_36_REG (CSR_MQM_MSC_BASE + 0xB90) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_37_REG (CSR_MQM_MSC_BASE + 0xB94) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_38_REG (CSR_MQM_MSC_BASE + 0xB98) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_39_REG (CSR_MQM_MSC_BASE + 0xB9C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_40_REG (CSR_MQM_MSC_BASE + 0xBA0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_41_REG (CSR_MQM_MSC_BASE + 0xBA4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_42_REG (CSR_MQM_MSC_BASE + 0xBA8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_43_REG (CSR_MQM_MSC_BASE + 0xBAC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_44_REG (CSR_MQM_MSC_BASE + 0xBB0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_45_REG (CSR_MQM_MSC_BASE + 0xBB4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_46_REG (CSR_MQM_MSC_BASE + 0xBB8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_47_REG (CSR_MQM_MSC_BASE + 0xBBC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_48_REG (CSR_MQM_MSC_BASE + 0xBC0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_49_REG (CSR_MQM_MSC_BASE + 0xBC4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_50_REG (CSR_MQM_MSC_BASE + 0xBC8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_51_REG (CSR_MQM_MSC_BASE + 0xBCC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_52_REG (CSR_MQM_MSC_BASE + 0xBD0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_53_REG (CSR_MQM_MSC_BASE + 0xBD4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_54_REG (CSR_MQM_MSC_BASE + 0xBD8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_55_REG (CSR_MQM_MSC_BASE + 0xBDC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_56_REG (CSR_MQM_MSC_BASE + 0xBE0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_57_REG (CSR_MQM_MSC_BASE + 0xBE4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_58_REG (CSR_MQM_MSC_BASE + 0xBE8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_59_REG (CSR_MQM_MSC_BASE + 0xBEC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_60_REG (CSR_MQM_MSC_BASE + 0xBF0) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_61_REG (CSR_MQM_MSC_BASE + 0xBF4) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_62_REG (CSR_MQM_MSC_BASE + 0xBF8) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_63_REG (CSR_MQM_MSC_BASE + 0xBFC) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_64_REG (CSR_MQM_MSC_BASE + 0xC00) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_65_REG (CSR_MQM_MSC_BASE + 0xC04) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_66_REG (CSR_MQM_MSC_BASE + 0xC08) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_67_REG (CSR_MQM_MSC_BASE + 0xC0C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_68_REG (CSR_MQM_MSC_BASE + 0xC10) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_69_REG (CSR_MQM_MSC_BASE + 0xC14) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_70_REG (CSR_MQM_MSC_BASE + 0xC18) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_71_REG (CSR_MQM_MSC_BASE + 0xC1C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_72_REG (CSR_MQM_MSC_BASE + 0xC20) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_73_REG (CSR_MQM_MSC_BASE + 0xC24) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_74_REG (CSR_MQM_MSC_BASE + 0xC28) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_75_REG (CSR_MQM_MSC_BASE + 0xC2C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_76_REG (CSR_MQM_MSC_BASE + 0xC30) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_77_REG (CSR_MQM_MSC_BASE + 0xC34) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_78_REG (CSR_MQM_MSC_BASE + 0xC38) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_79_REG (CSR_MQM_MSC_BASE + 0xC3C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_80_REG (CSR_MQM_MSC_BASE + 0xC40) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_81_REG (CSR_MQM_MSC_BASE + 0xC44) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_82_REG (CSR_MQM_MSC_BASE + 0xC48) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_83_REG (CSR_MQM_MSC_BASE + 0xC4C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_84_REG (CSR_MQM_MSC_BASE + 0xC50) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_85_REG (CSR_MQM_MSC_BASE + 0xC54) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_86_REG (CSR_MQM_MSC_BASE + 0xC58) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_87_REG (CSR_MQM_MSC_BASE + 0xC5C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_88_REG (CSR_MQM_MSC_BASE + 0xC60) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_89_REG (CSR_MQM_MSC_BASE + 0xC64) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_90_REG (CSR_MQM_MSC_BASE + 0xC68) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_91_REG (CSR_MQM_MSC_BASE + 0xC6C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_92_REG (CSR_MQM_MSC_BASE + 0xC70) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_93_REG (CSR_MQM_MSC_BASE + 0xC74) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_94_REG (CSR_MQM_MSC_BASE + 0xC78) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_95_REG (CSR_MQM_MSC_BASE + 0xC7C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_96_REG (CSR_MQM_MSC_BASE + 0xC80) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_97_REG (CSR_MQM_MSC_BASE + 0xC84) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_98_REG (CSR_MQM_MSC_BASE + 0xC88) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_99_REG (CSR_MQM_MSC_BASE + 0xC8C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_100_REG \ + (CSR_MQM_MSC_BASE + 0xC90) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_101_REG \ + (CSR_MQM_MSC_BASE + 0xC94) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_102_REG \ + (CSR_MQM_MSC_BASE + 0xC98) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_103_REG \ + (CSR_MQM_MSC_BASE + 0xC9C) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_104_REG \ + (CSR_MQM_MSC_BASE + 0xCA0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_105_REG \ + (CSR_MQM_MSC_BASE + 0xCA4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_106_REG \ + (CSR_MQM_MSC_BASE + 0xCA8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_107_REG \ + (CSR_MQM_MSC_BASE + 0xCAC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_108_REG \ + (CSR_MQM_MSC_BASE + 0xCB0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_109_REG \ + (CSR_MQM_MSC_BASE + 0xCB4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_110_REG \ + (CSR_MQM_MSC_BASE + 0xCB8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_111_REG \ + (CSR_MQM_MSC_BASE + 0xCBC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_112_REG \ + (CSR_MQM_MSC_BASE + 0xCC0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_113_REG \ + (CSR_MQM_MSC_BASE + 0xCC4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_114_REG \ + (CSR_MQM_MSC_BASE + 0xCC8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_115_REG \ + (CSR_MQM_MSC_BASE + 0xCCC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_116_REG \ + (CSR_MQM_MSC_BASE + 0xCD0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_117_REG \ + (CSR_MQM_MSC_BASE + 0xCD4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_118_REG \ + (CSR_MQM_MSC_BASE + 0xCD8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_119_REG \ + (CSR_MQM_MSC_BASE + 0xCDC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_120_REG \ + (CSR_MQM_MSC_BASE + 0xCE0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_121_REG \ + (CSR_MQM_MSC_BASE + 0xCE4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_122_REG \ + (CSR_MQM_MSC_BASE + 0xCE8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_123_REG \ + (CSR_MQM_MSC_BASE + 0xCEC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_124_REG \ + (CSR_MQM_MSC_BASE + 0xCF0) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_125_REG \ + (CSR_MQM_MSC_BASE + 0xCF4) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_126_REG \ + (CSR_MQM_MSC_BASE + 0xCF8) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_BPS_CFG_127_REG \ + (CSR_MQM_MSC_BASE + 0xCFC) /* SOCMQ Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xD00) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xD04) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xD08) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xD0C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xD10) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xD14) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xD18) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xD1C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xD20) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xD24) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xD28) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xD2C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xD30) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xD34) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xD38) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xD3C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_16_REG (CSR_MQM_MSC_BASE + 0xD40) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_17_REG (CSR_MQM_MSC_BASE + 0xD44) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_18_REG (CSR_MQM_MSC_BASE + 0xD48) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_19_REG (CSR_MQM_MSC_BASE + 0xD4C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_20_REG (CSR_MQM_MSC_BASE + 0xD50) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_21_REG (CSR_MQM_MSC_BASE + 0xD54) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_22_REG (CSR_MQM_MSC_BASE + 0xD58) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_23_REG (CSR_MQM_MSC_BASE + 0xD5C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_24_REG (CSR_MQM_MSC_BASE + 0xD60) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_25_REG (CSR_MQM_MSC_BASE + 0xD64) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_26_REG (CSR_MQM_MSC_BASE + 0xD68) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_27_REG (CSR_MQM_MSC_BASE + 0xD6C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_28_REG (CSR_MQM_MSC_BASE + 0xD70) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_29_REG (CSR_MQM_MSC_BASE + 0xD74) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_30_REG (CSR_MQM_MSC_BASE + 0xD78) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_31_REG (CSR_MQM_MSC_BASE + 0xD7C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_32_REG (CSR_MQM_MSC_BASE + 0xD80) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_33_REG (CSR_MQM_MSC_BASE + 0xD84) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_34_REG (CSR_MQM_MSC_BASE + 0xD88) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_35_REG (CSR_MQM_MSC_BASE + 0xD8C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_36_REG (CSR_MQM_MSC_BASE + 0xD90) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_37_REG (CSR_MQM_MSC_BASE + 0xD94) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_38_REG (CSR_MQM_MSC_BASE + 0xD98) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_39_REG (CSR_MQM_MSC_BASE + 0xD9C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_40_REG (CSR_MQM_MSC_BASE + 0xDA0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_41_REG (CSR_MQM_MSC_BASE + 0xDA4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_42_REG (CSR_MQM_MSC_BASE + 0xDA8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_43_REG (CSR_MQM_MSC_BASE + 0xDAC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_44_REG (CSR_MQM_MSC_BASE + 0xDB0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_45_REG (CSR_MQM_MSC_BASE + 0xDB4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_46_REG (CSR_MQM_MSC_BASE + 0xDB8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_47_REG (CSR_MQM_MSC_BASE + 0xDBC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_48_REG (CSR_MQM_MSC_BASE + 0xDC0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_49_REG (CSR_MQM_MSC_BASE + 0xDC4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_50_REG (CSR_MQM_MSC_BASE + 0xDC8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_51_REG (CSR_MQM_MSC_BASE + 0xDCC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_52_REG (CSR_MQM_MSC_BASE + 0xDD0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_53_REG (CSR_MQM_MSC_BASE + 0xDD4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_54_REG (CSR_MQM_MSC_BASE + 0xDD8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_55_REG (CSR_MQM_MSC_BASE + 0xDDC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_56_REG (CSR_MQM_MSC_BASE + 0xDE0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_57_REG (CSR_MQM_MSC_BASE + 0xDE4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_58_REG (CSR_MQM_MSC_BASE + 0xDE8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_59_REG (CSR_MQM_MSC_BASE + 0xDEC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_60_REG (CSR_MQM_MSC_BASE + 0xDF0) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_61_REG (CSR_MQM_MSC_BASE + 0xDF4) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_62_REG (CSR_MQM_MSC_BASE + 0xDF8) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_63_REG (CSR_MQM_MSC_BASE + 0xDFC) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_64_REG (CSR_MQM_MSC_BASE + 0xE00) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_65_REG (CSR_MQM_MSC_BASE + 0xE04) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_66_REG (CSR_MQM_MSC_BASE + 0xE08) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_67_REG (CSR_MQM_MSC_BASE + 0xE0C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_68_REG (CSR_MQM_MSC_BASE + 0xE10) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_69_REG (CSR_MQM_MSC_BASE + 0xE14) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_70_REG (CSR_MQM_MSC_BASE + 0xE18) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_71_REG (CSR_MQM_MSC_BASE + 0xE1C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_72_REG (CSR_MQM_MSC_BASE + 0xE20) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_73_REG (CSR_MQM_MSC_BASE + 0xE24) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_74_REG (CSR_MQM_MSC_BASE + 0xE28) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_75_REG (CSR_MQM_MSC_BASE + 0xE2C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_76_REG (CSR_MQM_MSC_BASE + 0xE30) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_77_REG (CSR_MQM_MSC_BASE + 0xE34) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_78_REG (CSR_MQM_MSC_BASE + 0xE38) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_79_REG (CSR_MQM_MSC_BASE + 0xE3C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_80_REG (CSR_MQM_MSC_BASE + 0xE40) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_81_REG (CSR_MQM_MSC_BASE + 0xE44) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_82_REG (CSR_MQM_MSC_BASE + 0xE48) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_83_REG (CSR_MQM_MSC_BASE + 0xE4C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_84_REG (CSR_MQM_MSC_BASE + 0xE50) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_85_REG (CSR_MQM_MSC_BASE + 0xE54) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_86_REG (CSR_MQM_MSC_BASE + 0xE58) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_87_REG (CSR_MQM_MSC_BASE + 0xE5C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_88_REG (CSR_MQM_MSC_BASE + 0xE60) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_89_REG (CSR_MQM_MSC_BASE + 0xE64) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_90_REG (CSR_MQM_MSC_BASE + 0xE68) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_91_REG (CSR_MQM_MSC_BASE + 0xE6C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_92_REG (CSR_MQM_MSC_BASE + 0xE70) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_93_REG (CSR_MQM_MSC_BASE + 0xE74) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_94_REG (CSR_MQM_MSC_BASE + 0xE78) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_95_REG (CSR_MQM_MSC_BASE + 0xE7C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_96_REG (CSR_MQM_MSC_BASE + 0xE80) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_97_REG (CSR_MQM_MSC_BASE + 0xE84) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_98_REG (CSR_MQM_MSC_BASE + 0xE88) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_99_REG (CSR_MQM_MSC_BASE + 0xE8C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_100_REG \ + (CSR_MQM_MSC_BASE + 0xE90) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_101_REG \ + (CSR_MQM_MSC_BASE + 0xE94) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_102_REG \ + (CSR_MQM_MSC_BASE + 0xE98) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_103_REG \ + (CSR_MQM_MSC_BASE + 0xE9C) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_104_REG \ + (CSR_MQM_MSC_BASE + 0xEA0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_105_REG \ + (CSR_MQM_MSC_BASE + 0xEA4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_106_REG \ + (CSR_MQM_MSC_BASE + 0xEA8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_107_REG \ + (CSR_MQM_MSC_BASE + 0xEAC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_108_REG \ + (CSR_MQM_MSC_BASE + 0xEB0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_109_REG \ + (CSR_MQM_MSC_BASE + 0xEB4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_110_REG \ + (CSR_MQM_MSC_BASE + 0xEB8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_111_REG \ + (CSR_MQM_MSC_BASE + 0xEBC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_112_REG \ + (CSR_MQM_MSC_BASE + 0xEC0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_113_REG \ + (CSR_MQM_MSC_BASE + 0xEC4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_114_REG \ + (CSR_MQM_MSC_BASE + 0xEC8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_115_REG \ + (CSR_MQM_MSC_BASE + 0xECC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_116_REG \ + (CSR_MQM_MSC_BASE + 0xED0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_117_REG \ + (CSR_MQM_MSC_BASE + 0xED4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_118_REG \ + (CSR_MQM_MSC_BASE + 0xED8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_119_REG \ + (CSR_MQM_MSC_BASE + 0xEDC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_120_REG \ + (CSR_MQM_MSC_BASE + 0xEE0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_121_REG \ + (CSR_MQM_MSC_BASE + 0xEE4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_122_REG \ + (CSR_MQM_MSC_BASE + 0xEE8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_123_REG \ + (CSR_MQM_MSC_BASE + 0xEEC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_124_REG \ + (CSR_MQM_MSC_BASE + 0xEF0) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_125_REG \ + (CSR_MQM_MSC_BASE + 0xEF4) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_126_REG \ + (CSR_MQM_MSC_BASE + 0xEF8) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCMQ_SHAP_PPS_CFG_127_REG \ + (CSR_MQM_MSC_BASE + 0xEFC) /* SOCMQ Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xF00) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xF04) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xF08) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xF0C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xF10) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xF14) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xF18) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xF1C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xF20) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xF24) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xF28) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xF2C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xF30) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xF34) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xF38) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_BPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xF3C) /* SOCMQ Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_0_REG (CSR_MQM_MSC_BASE + 0xF40) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_1_REG (CSR_MQM_MSC_BASE + 0xF44) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_2_REG (CSR_MQM_MSC_BASE + 0xF48) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_3_REG (CSR_MQM_MSC_BASE + 0xF4C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_4_REG (CSR_MQM_MSC_BASE + 0xF50) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_5_REG (CSR_MQM_MSC_BASE + 0xF54) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_6_REG (CSR_MQM_MSC_BASE + 0xF58) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_7_REG (CSR_MQM_MSC_BASE + 0xF5C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_8_REG (CSR_MQM_MSC_BASE + 0xF60) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_9_REG (CSR_MQM_MSC_BASE + 0xF64) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_10_REG (CSR_MQM_MSC_BASE + 0xF68) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_11_REG (CSR_MQM_MSC_BASE + 0xF6C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_12_REG (CSR_MQM_MSC_BASE + 0xF70) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_13_REG (CSR_MQM_MSC_BASE + 0xF74) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_14_REG (CSR_MQM_MSC_BASE + 0xF78) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCEP_SHAP_PPS_CFG_15_REG (CSR_MQM_MSC_BASE + 0xF7C) /* SOCMQ Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCSERV_SHAP_BPS_CFG_0_REG \ + (CSR_MQM_MSC_BASE + 0xF80) /* SOC Service Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCSERV_SHAP_BPS_CFG_1_REG \ + (CSR_MQM_MSC_BASE + 0xF84) /* SOC Service Node Shaper BPS Configuration Table */ +#define CSR_MQM_MSC_SOCSERV_SHAP_PPS_CFG_0_REG \ + (CSR_MQM_MSC_BASE + 0xF88) /* SOC Service Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCSERV_SHAP_PPS_CFG_1_REG \ + (CSR_MQM_MSC_BASE + 0xF8C) /* SOC Service Node Shaper PPS Configuration Table */ +#define CSR_MQM_MSC_SOCRT_SHAP_BPS_CFG_REG (CSR_MQM_MSC_BASE + 0xF90) /* SOC Root Node Shaper BPS Configuration Table \ + */ +#define CSR_MQM_MSC_SOCRT_SHAP_PPS_CFG_REG (CSR_MQM_MSC_BASE + 0xF94) /* SOC Root Node Shaper PPS Configuration Table \ + */ +#define CSR_MQM_MSC_MSC_SHAP_BYPASS_CFG_REG (CSR_MQM_MSC_BASE + 0x1200) /* MSC Shaper Bypass Configuration */ +#define CSR_MQM_MSC_MSC_HOST_ROOT_XON_CFG_REG \ + (CSR_MQM_MSC_BASE + 0x1204) /* The XON Configuration of the HOST ROOT node */ +#define CSR_MQM_MSC_MSC_SOC_ROOT_XON_CFG_REG \ + (CSR_MQM_MSC_BASE + 0x1208) /* The XON Configuration of the SOC ROOT node */ +#define CSR_MQM_MSC_MSC_HOST_EP_XON_CFG_NS_REG \ + (CSR_MQM_MSC_BASE + 0x120C) /* The XON Configuration of the NS HOST EP node */ +#define CSR_MQM_MSC_MSC_HOST_EP_XON_CFG_NFMQ_REG \ + (CSR_MQM_MSC_BASE + 0x1210) /* The XON Configuration of the NFMQ HOST EP node */ +#define CSR_MQM_MSC_MSC_HOST_EP_XON_CFG_CMQ_REG \ + (CSR_MQM_MSC_BASE + 0x1214) /* The XON Configuration of the CMQ HOST EP node */ +#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_0_REG \ + (CSR_MQM_MSC_BASE + 0x1220) /* The XON Configuration of the SOCMSC NS MQ node */ +#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_1_REG \ + (CSR_MQM_MSC_BASE + 0x1224) /* The XON Configuration of the SOCMSC NS MQ node */ +#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_2_REG \ + (CSR_MQM_MSC_BASE + 0x1228) /* The XON Configuration of the SOCMSC NS MQ node */ +#define CSR_MQM_MSC_SOCMSC_MQ_XON_CFG_NS_3_REG \ + (CSR_MQM_MSC_BASE + 0x122C) /* The XON Configuration of the SOCMSC NS MQ node */ +#define CSR_MQM_MSC_MSC_PRM_PORT_BP_STA0_REG \ + (CSR_MQM_MSC_BASE + 0x1230) /* MSC Port backpress status Register 0 from PRM */ +#define CSR_MQM_MSC_MSC_PRM_PORT_BP_STA1_REG \ + (CSR_MQM_MSC_BASE + 0x1234) /* MSC Port backpress status Register 1 from PRM */ +#define CSR_MQM_MSC_MSC_QU_COS_BP_STA0_REG \ + (CSR_MQM_MSC_BASE + 0x1238) /* MSC COS Level backpress status Register for NMQ EP0~EP3 */ +#define CSR_MQM_MSC_MSC_QU_COS_BP_STA1_REG \ + (CSR_MQM_MSC_BASE + 0x123C) /* MSC COS Level backpress status Register for NMQ EP4~EP7 */ +#define CSR_MQM_MSC_SOCMSC_RT_EP_BP_STA_REG (CSR_MQM_MSC_BASE + 0x1240) /* SOC MSC backpress status Register */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA0_REG \ + (CSR_MQM_MSC_BASE + 0x1244) /* SOCMSC QUEUE Level backpress status Register 0 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA1_REG \ + (CSR_MQM_MSC_BASE + 0x1248) /* SOCMSC QUEUE Level backpress status Register 1 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA2_REG \ + (CSR_MQM_MSC_BASE + 0x124C) /* SOCMSC QUEUE Level backpress status Register 2 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_BP_STA3_REG \ + (CSR_MQM_MSC_BASE + 0x1250) /* SOCMSC QUEUE Level backpress status Register 3 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA0_REG \ + (CSR_MQM_MSC_BASE + 0x1254) /* SOCMSC QUEUE Level eligible status Register 0 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA1_REG \ + (CSR_MQM_MSC_BASE + 0x1258) /* SOCMSC QUEUE Level eligible status Register 1 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA2_REG \ + (CSR_MQM_MSC_BASE + 0x125C) /* SOCMSC QUEUE Level eligible status Register 2 */ +#define CSR_MQM_MSC_SOCMSC_QUEUE_ELIGIBLE_STA3_REG \ + (CSR_MQM_MSC_BASE + 0x1260) /* SOCMSC QUEUE Level eligible status Register 3 */ +#define CSR_MQM_MSC_MSC_RT_HOST_BP_STA_REG (CSR_MQM_MSC_BASE + 0x1264) /* MSC root host backpress status Register */ +#define CSR_MQM_MSC_MSC_HOSTEP_NS_BP_STA_REG \ + (CSR_MQM_MSC_BASE + 0x1268) /* MSC NS HSOT_EP Level backpress status Register */ +#define CSR_MQM_MSC_MSC_HOSTEP_NFMQ_BP_STA_REG \ + (CSR_MQM_MSC_BASE + 0x126C) /* MSC NFMQ HSOT_EP Level backpress status Register */ +#define CSR_MQM_MSC_MSC_HOSTEP_CMQ_BP_STA_REG \ + (CSR_MQM_MSC_BASE + 0x1270) /* MSC CMQ HSOT_EP Level backpress status Register */ +#define CSR_MQM_MSC_MSC_FIFO_TH_CFG_REG (CSR_MQM_MSC_BASE + 0x1274) /* The Threshold Config Of MSC FIFO */ +#define CSR_MQM_MSC_MSC_FIFO_ST0_REG (CSR_MQM_MSC_BASE + 0x1290) /* fifo full and empt state */ +#define CSR_MQM_MSC_MSC_FIFO_ST1_REG (CSR_MQM_MSC_BASE + 0x1294) /* fifo full and empt state */ +#define CSR_MQM_MSC_MSC_FIFO_ST2_REG (CSR_MQM_MSC_BASE + 0x1298) /* fifo full and empt state */ +#define CSR_MQM_MSC_MSC_FIFO_ST3_REG (CSR_MQM_MSC_BASE + 0x129C) /* fifo full and empt state */ +#define CSR_MQM_MSC_CMQ_RX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12A0) /* Command MQ ENQ UP count */ +#define CSR_MQM_MSC_NFMQ_RX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12A4) /* Non-filter MQ ENQ UP count */ +#define CSR_MQM_MSC_NMQ_RX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12A8) /* Normal MQ ENQ UP count */ +#define CSR_MQM_MSC_CMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12AC) /* Command MQ schedule count */ +#define CSR_MQM_MSC_NFMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12B0) /* Non-filter MQ schedule count. */ +#define CSR_MQM_MSC_NMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12B4) /* Normal MQ schedule cnt numbers */ +#define CSR_MQM_MSC_SOCCMQ_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12B8) /* SOC Command MQ UP count */ +#define CSR_MQM_MSC_SOCNMQ_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x12BC) /* SOC NMQ UP count. */ +#define CSR_MQM_MSC_SOCCMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12C0) /* SOC Command MQ schedule count */ +#define CSR_MQM_MSC_SOCNMQ_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12C4) /* SOC NMQ schedule count. */ +#define CSR_MQM_MSC_CMQ_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12C8) /* Command MQ EMPT schedule count */ +#define CSR_MQM_MSC_NFMQ_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12CC) /* Non-filter MQ EMPT schedule count */ +#define CSR_MQM_MSC_NMQ_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x12D0) /* Normal MQ EMPT schedule count */ +#define CSR_MQM_MSC_CMQ_RX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12D4) /* Command MQ DU count */ +#define CSR_MQM_MSC_NFMQ_RX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12D8) /* Non-filter MQ DU count */ +#define CSR_MQM_MSC_NMQ_RX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12DC) /* Normal MQ DU count */ +#define CSR_MQM_MSC_SOCCMQ_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12E0) /* SOC Command MQ DU count */ +#define CSR_MQM_MSC_SOCNMQ_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x12E4) /* SOC NMQ DU count. */ +#define CSR_MQM_MSC_MSC_ECC_1BIT_ERR_CNT_REG (CSR_MQM_MSC_BASE + 0x12E8) /* MSC MEMORY ECC 1BIT ERR count */ +#define CSR_MQM_MSC_MSC_ECC_2BIT_ERR_CNT_REG (CSR_MQM_MSC_BASE + 0x12EC) /* MSC MEMORY ECC 2BIT ERR count */ +#define CSR_MQM_MSC_SCH_MQ_DFX_CFG_REG (CSR_MQM_MSC_BASE + 0x1320) /* MQ DFX NUM configure */ +#define CSR_MQM_MSC_SCH_MQ_DFX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x1324) /* MQ DFX NUM ENQ UP count */ +#define CSR_MQM_MSC_SCH_MQ_DFX_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x1328) /* MQ DFX NUM DEQ SCH count */ +#define CSR_MQM_MSC_SCH_MQ_DFX_EMPT_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x132C) /* MQ DFX NUM DEQ EMPT SCH count */ +#define CSR_MQM_MSC_SCH_MQ_DFX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x1330) /* MQ DFX NUM DU count */ +#define CSR_MQM_MSC_SCH_SOCMQ_DFX_CFG_REG (CSR_MQM_MSC_BASE + 0x1334) /* SOCMQ DFX NUM configure */ +#define CSR_MQM_MSC_SCH_SOCMQ_DFX_UP_CNT_REG (CSR_MQM_MSC_BASE + 0x1338) /* SOCMQ DFX NUM ENQ UP count */ +#define CSR_MQM_MSC_SCH_SOCMQ_DFX_SCH_CNT_REG (CSR_MQM_MSC_BASE + 0x133C) /* SOCMQ DFX NUM DEQ SCH count */ +#define CSR_MQM_MSC_SCH_SOCMQ_DFX_DU_CNT_REG (CSR_MQM_MSC_BASE + 0x1340) /* SOCMQ DFX NUM DU count */ +#define CSR_MQM_MSC_SOCMSC_MCD_DU_INFO_PTR0_REG \ + (CSR_MQM_MSC_BASE + 0x1344) /* MQM SOCMSC MCD DU INFO 0 status Register */ +#define CSR_MQM_MSC_SOCMSC_MCD_DU_INFO_PTR1_REG \ + (CSR_MQM_MSC_BASE + 0x1348) /* MQM SOCMSC MCD DU INFO 1 status Register */ +#define CSR_MQM_MSC_MSC_CS_MCD_DU_INFO_PTR0_REG \ + (CSR_MQM_MSC_BASE + 0x134C) /* MQM MSC CS MCD DU INFO 0 status Register */ +#define CSR_MQM_MSC_MSC_CS_MCD_DU_INFO_PTR1_REG \ + (CSR_MQM_MSC_BASE + 0x1350) /* MQM MSC CS MCD DU INFO 1 status Register */ +#define CSR_MQM_MSC_MSC_CS_MCD_DU_INFO_PTR2_REG \ + (CSR_MQM_MSC_BASE + 0x1354) /* MQM MSC CS MCD DU INFO 2 status Register */ +#define CSR_MQM_MSC_MSC_NS_MCD_DU_INFO_PTR0_REG \ + (CSR_MQM_MSC_BASE + 0x1358) /* MQM MSC NS MCD DU INFO 0 status Register */ +#define CSR_MQM_MSC_MSC_NS_MCD_DU_INFO_PTR1_REG \ + (CSR_MQM_MSC_BASE + 0x135C) /* MQM MSC NS MCD DU INFO 1 status Register */ +#define CSR_MQM_MSC_MSC_NS_MCD_DU_INFO_PTR2_REG \ + (CSR_MQM_MSC_BASE + 0x1360) /* MQM MSC NS MCD DU INFO 2 status Register */ + +/* MQM_DEQC Base address of Module's Register */ +#define CSR_MQM_DEQC_BASE (0xE000) + +/* **************************************************************************** */ +/* MQM_DEQC Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_MQM_DEQC_DEQC_RW_RSV0_REG (CSR_MQM_DEQC_BASE + 0x0) /* DEQC Read-Write Register0 for Reserve. */ +#define CSR_MQM_DEQC_DEQC_RW_RSV1_REG (CSR_MQM_DEQC_BASE + 0x4) /* DEQC Read-Write Register1 for Reserve. */ +#define CSR_MQM_DEQC_DEQC_RW_RSV2_REG (CSR_MQM_DEQC_BASE + 0x8) /* DEQC Read-Write Register2 for Reserve. */ +#define CSR_MQM_DEQC_DEQC_RW_RSV3_REG (CSR_MQM_DEQC_BASE + 0xC) /* DEQC Read-Write Register3 for Reserve. */ +#define CSR_MQM_DEQC_DEQC_INDRECT_CTRL_REG (CSR_MQM_DEQC_BASE + 0x10) /* DEQC Indirect access ctrl Register。 */ +#define CSR_MQM_DEQC_DEQC_INDRECT_TIMEOUT_REG (CSR_MQM_DEQC_BASE + 0x14) /* DEQC Indirect Access Timeout Register。 */ +#define CSR_MQM_DEQC_DEQC_INDRECT_DATA_REG (CSR_MQM_DEQC_BASE + 0x18) /* DEQC Indirect Access Data Register. */ +#define CSR_MQM_DEQC_DEQC_MEM_ECC_BYPASS_EN_REG (CSR_MQM_DEQC_BASE + 0x20) /* RAM ECC BYPASS控制寄存器 */ +#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG0_REG (CSR_MQM_DEQC_BASE + 0x24) /* RAM CTRL_BUS寄存器0 */ +#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG1_REG (CSR_MQM_DEQC_BASE + 0x28) /* RAM CTRL_BUS寄存器1 */ +#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG2_REG (CSR_MQM_DEQC_BASE + 0x2C) /* RAM CTRL_BUS寄存器2 */ +#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG3_REG (CSR_MQM_DEQC_BASE + 0x30) /* RAM CTRL_BUS寄存器3 */ +#define CSR_MQM_DEQC_DEQC_MEM_CTRL_BUS_CFG4_REG (CSR_MQM_DEQC_BASE + 0x34) /* RAM CTRL_BUS寄存器4 */ +#define CSR_MQM_DEQC_DEQC_INT_VECTOR_REG (CSR_MQM_DEQC_BASE + 0x100) /* DEQC Internal ERR Interrupt Vector Register. \ + */ +#define CSR_MQM_DEQC_DEQC_INT_REG (CSR_MQM_DEQC_BASE + 0x104) /* DEQC Internal ERR Interrupt Register. */ +#define CSR_MQM_DEQC_DEQC_INT_EN_REG (CSR_MQM_DEQC_BASE + 0x108) /* DEQC Internal ERR Interrupt Mask Register. */ +#define CSR_MQM_DEQC_DEQC_MEM_1BIT_ERR_REG (CSR_MQM_DEQC_BASE + 0x10C) /* DEQC 1Bit ECC Check Err Register. */ +#define CSR_MQM_DEQC_DEQC_MEM_2BIT_ERR_REG (CSR_MQM_DEQC_BASE + 0x110) /* DEQC 2Bit ECC Check Err Register. */ +#define CSR_MQM_DEQC_DEQC_ENMQ_BIND_CONFIG_ERR_REG (CSR_MQM_DEQC_BASE + 0x114) /* DEQC ENMQ BIND CONFIG Err Register. \ + */ +#define CSR_MQM_DEQC_DEQC_ENFMQ_BIND_CONFIG_ERR_REG \ + (CSR_MQM_DEQC_BASE + 0x118) /* DEQC ENFMQ BIND CONFIG Err Register. */ +#define CSR_MQM_DEQC_DEQC_MEM_ERR_REQ_REG (CSR_MQM_DEQC_BASE + 0x150) /* DEQC Internal Memory ERR Req Register. */ +#define CSR_MQM_DEQC_DEQC_FIFO_INT_REG (CSR_MQM_DEQC_BASE + 0x154) /* DEQC FIFO Write Interrupt Register. */ +#define CSR_MQM_DEQC_DEQC_FIFO_WR_INT_MASK_REG \ + (CSR_MQM_DEQC_BASE + 0x158) /* DEQC FIFO Write Interrupt Mask Register. */ +#define CSR_MQM_DEQC_DEQC_TIMES_COUNT_CFG_REG (CSR_MQM_DEQC_BASE + 0x200) /* DEQC TIMES Count Configuration Register \ + */ +#define CSR_MQM_DEQC_DEQC_BLK_DATA_LEN0_REG (CSR_MQM_DEQC_BASE + 0x204) /* DEQC Queue Descriptors Block Size. */ +#define CSR_MQM_DEQC_DEQC_BLK_DATA_LEN1_REG (CSR_MQM_DEQC_BASE + 0x208) /* DEQC Queue Descriptors Block Size. */ +#define CSR_MQM_DEQC_DEQC_ROOT_CRR_WEIGHT_CFG_REG (CSR_MQM_DEQC_BASE + 0x20C) /* DEQC ROOT CRR WEIGHT Config */ +#define CSR_MQM_DEQC_DEQC_WEIGHT_OFFSET_REG (CSR_MQM_DEQC_BASE + 0x210) /* DEQC Weight Offset Register. */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_0_REG \ + (CSR_MQM_DEQC_BASE + 0x300) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_1_REG \ + (CSR_MQM_DEQC_BASE + 0x304) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_2_REG \ + (CSR_MQM_DEQC_BASE + 0x308) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_3_REG \ + (CSR_MQM_DEQC_BASE + 0x30C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_4_REG \ + (CSR_MQM_DEQC_BASE + 0x310) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_5_REG \ + (CSR_MQM_DEQC_BASE + 0x314) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_6_REG \ + (CSR_MQM_DEQC_BASE + 0x318) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_7_REG \ + (CSR_MQM_DEQC_BASE + 0x31C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_8_REG \ + (CSR_MQM_DEQC_BASE + 0x320) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_9_REG \ + (CSR_MQM_DEQC_BASE + 0x324) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_10_REG \ + (CSR_MQM_DEQC_BASE + 0x328) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_11_REG \ + (CSR_MQM_DEQC_BASE + 0x32C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_12_REG \ + (CSR_MQM_DEQC_BASE + 0x330) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_13_REG \ + (CSR_MQM_DEQC_BASE + 0x334) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_14_REG \ + (CSR_MQM_DEQC_BASE + 0x338) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_15_REG \ + (CSR_MQM_DEQC_BASE + 0x33C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_16_REG \ + (CSR_MQM_DEQC_BASE + 0x340) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_17_REG \ + (CSR_MQM_DEQC_BASE + 0x344) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_18_REG \ + (CSR_MQM_DEQC_BASE + 0x348) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_19_REG \ + (CSR_MQM_DEQC_BASE + 0x34C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_20_REG \ + (CSR_MQM_DEQC_BASE + 0x350) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_21_REG \ + (CSR_MQM_DEQC_BASE + 0x354) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_22_REG \ + (CSR_MQM_DEQC_BASE + 0x358) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_23_REG \ + (CSR_MQM_DEQC_BASE + 0x35C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_24_REG \ + (CSR_MQM_DEQC_BASE + 0x360) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_25_REG \ + (CSR_MQM_DEQC_BASE + 0x364) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_26_REG \ + (CSR_MQM_DEQC_BASE + 0x368) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_27_REG \ + (CSR_MQM_DEQC_BASE + 0x36C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_28_REG \ + (CSR_MQM_DEQC_BASE + 0x370) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_29_REG \ + (CSR_MQM_DEQC_BASE + 0x374) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_30_REG \ + (CSR_MQM_DEQC_BASE + 0x378) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_EP_WEIGHT_31_REG \ + (CSR_MQM_DEQC_BASE + 0x37C) /* ENMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_0_REG \ + (CSR_MQM_DEQC_BASE + 0x380) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_1_REG \ + (CSR_MQM_DEQC_BASE + 0x384) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_2_REG \ + (CSR_MQM_DEQC_BASE + 0x388) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_3_REG \ + (CSR_MQM_DEQC_BASE + 0x38C) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_4_REG \ + (CSR_MQM_DEQC_BASE + 0x390) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_5_REG \ + (CSR_MQM_DEQC_BASE + 0x394) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_6_REG \ + (CSR_MQM_DEQC_BASE + 0x398) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_7_REG \ + (CSR_MQM_DEQC_BASE + 0x39C) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_8_REG \ + (CSR_MQM_DEQC_BASE + 0x3A0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_9_REG \ + (CSR_MQM_DEQC_BASE + 0x3A4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_10_REG \ + (CSR_MQM_DEQC_BASE + 0x3A8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_11_REG \ + (CSR_MQM_DEQC_BASE + 0x3AC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_12_REG \ + (CSR_MQM_DEQC_BASE + 0x3B0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_13_REG \ + (CSR_MQM_DEQC_BASE + 0x3B4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_14_REG \ + (CSR_MQM_DEQC_BASE + 0x3B8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_15_REG \ + (CSR_MQM_DEQC_BASE + 0x3BC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_16_REG \ + (CSR_MQM_DEQC_BASE + 0x3C0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_17_REG \ + (CSR_MQM_DEQC_BASE + 0x3C4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_18_REG \ + (CSR_MQM_DEQC_BASE + 0x3C8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_19_REG \ + (CSR_MQM_DEQC_BASE + 0x3CC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_20_REG \ + (CSR_MQM_DEQC_BASE + 0x3D0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_21_REG \ + (CSR_MQM_DEQC_BASE + 0x3D4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_22_REG \ + (CSR_MQM_DEQC_BASE + 0x3D8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_23_REG \ + (CSR_MQM_DEQC_BASE + 0x3DC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_24_REG \ + (CSR_MQM_DEQC_BASE + 0x3E0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_25_REG \ + (CSR_MQM_DEQC_BASE + 0x3E4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_26_REG \ + (CSR_MQM_DEQC_BASE + 0x3E8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_27_REG \ + (CSR_MQM_DEQC_BASE + 0x3EC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_28_REG \ + (CSR_MQM_DEQC_BASE + 0x3F0) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_29_REG \ + (CSR_MQM_DEQC_BASE + 0x3F4) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_30_REG \ + (CSR_MQM_DEQC_BASE + 0x3F8) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EP_WEIGHT_31_REG \ + (CSR_MQM_DEQC_BASE + 0x3FC) /* ENFMQ Priority Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_0_REG \ + (CSR_MQM_DEQC_BASE + 0x400) /* ENMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_1_REG \ + (CSR_MQM_DEQC_BASE + 0x404) /* ENMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_2_REG \ + (CSR_MQM_DEQC_BASE + 0x408) /* ENMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_WEIGHT_3_REG \ + (CSR_MQM_DEQC_BASE + 0x40C) /* ENMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_0_REG \ + (CSR_MQM_DEQC_BASE + 0x410) /* ENFMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_1_REG \ + (CSR_MQM_DEQC_BASE + 0x414) /* ENFMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_2_REG \ + (CSR_MQM_DEQC_BASE + 0x418) /* ENFMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_WEIGHT_3_REG \ + (CSR_MQM_DEQC_BASE + 0x41C) /* ENFMQ Host Node Weight Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_0_REG \ + (CSR_MQM_DEQC_BASE + 0x420) /* ENMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_1_REG \ + (CSR_MQM_DEQC_BASE + 0x424) /* ENMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_2_REG \ + (CSR_MQM_DEQC_BASE + 0x428) /* ENMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SHAP_CFG_3_REG \ + (CSR_MQM_DEQC_BASE + 0x42C) /* ENMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_0_REG \ + (CSR_MQM_DEQC_BASE + 0x430) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_1_REG \ + (CSR_MQM_DEQC_BASE + 0x434) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_2_REG \ + (CSR_MQM_DEQC_BASE + 0x438) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_CFG_3_REG \ + (CSR_MQM_DEQC_BASE + 0x43C) /* ENFMQ HOST Node Shaper Configuration Table Register 0 */ +#define CSR_MQM_DEQC_DEQC_SERV_SHAP_CFG_0_REG \ + (CSR_MQM_DEQC_BASE + 0x440) /* DEQC SERVICE Node Shaper Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_SERV_SHAP_CFG_1_REG \ + (CSR_MQM_DEQC_BASE + 0x444) /* DEQC SERVICE Node Shaper Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_ROOT_SHAP_CFG_REG \ + (CSR_MQM_DEQC_BASE + 0x450) /* DEQC ROOT Node Shaper Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_SHAP_BYPASS_CFG_REG (CSR_MQM_DEQC_BASE + 0x500) /* DEQC Shaper Bypass Configuration */ +#define CSR_MQM_DEQC_DEQC_SPCOS_SHARE_RSC_XON_RSP_CFG_REG \ + (CSR_MQM_DEQC_BASE + 0x504) /* DEQC Spcos Share Resource XON Response Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_RH_XON_CFG_REG \ + (CSR_MQM_DEQC_BASE + 0x508) /* NFMQ ROOT SERVICE Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_HOST_XON_CFG_NMQ_REG \ + (CSR_MQM_DEQC_BASE + 0x50C) /* NMQ HOST Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_HOST_XON_CFG_NFMQ_REG \ + (CSR_MQM_DEQC_BASE + 0x510) /* NFMQ HOST Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_EP_XON_CFG_NMQ_REG \ + (CSR_MQM_DEQC_BASE + 0x514) /* NMQ EP Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_EP_XON_CFG_NFMQ_REG \ + (CSR_MQM_DEQC_BASE + 0x518) /* NFMQ EP Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_0_REG \ + (CSR_MQM_DEQC_BASE + 0x520) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_1_REG \ + (CSR_MQM_DEQC_BASE + 0x524) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_2_REG \ + (CSR_MQM_DEQC_BASE + 0x528) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_3_REG \ + (CSR_MQM_DEQC_BASE + 0x52C) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_4_REG \ + (CSR_MQM_DEQC_BASE + 0x530) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_5_REG \ + (CSR_MQM_DEQC_BASE + 0x534) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_6_REG \ + (CSR_MQM_DEQC_BASE + 0x538) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NMQ_7_REG \ + (CSR_MQM_DEQC_BASE + 0x53C) /* NMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_0_REG \ + (CSR_MQM_DEQC_BASE + 0x540) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_1_REG \ + (CSR_MQM_DEQC_BASE + 0x544) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_2_REG \ + (CSR_MQM_DEQC_BASE + 0x548) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_3_REG \ + (CSR_MQM_DEQC_BASE + 0x54C) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_4_REG \ + (CSR_MQM_DEQC_BASE + 0x550) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_5_REG \ + (CSR_MQM_DEQC_BASE + 0x554) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_6_REG \ + (CSR_MQM_DEQC_BASE + 0x558) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_COS_XON_CFG_NFMQ_7_REG \ + (CSR_MQM_DEQC_BASE + 0x55C) /* NFMQ COS Node Xon Configuration Table Register */ +#define CSR_MQM_DEQC_DEQC_ROOT_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x560) /* Root Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_SERVICE_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x564) /* ENMQ Service Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NFMQ_SERVICE_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x568) /* ENFMQ Service Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x56C) /* ENMQ Host Node XON Table */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x570) /* ENFMQ Host Node XON Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x574) /* ENMQ host_ep Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_XON_ST_REG (CSR_MQM_DEQC_BASE + 0x578) /* ENFMQ host_ep Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_SPASS_ST_REG (CSR_MQM_DEQC_BASE + 0x57C) /* ENMQ Host Node Shaping Pass Flag Table \ + */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_SHAP_PASS_ST_REG \ + (CSR_MQM_DEQC_BASE + 0x580) /* ENFMQ Host Node Shaping Pass Flag Table */ +#define CSR_MQM_DEQC_DEQC_FIFO_DFX_REG (CSR_MQM_DEQC_BASE + 0x584) /* DEQC FIFO Empty and Full DFX Register. */ +#define CSR_MQM_DEQC_DEQC_NMQ_UP_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5C0) /* ENMQ UP descpt count Register. */ +#define CSR_MQM_DEQC_DEQC_NFMQ_UP_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5C4) /* ENFMQ UP descpt count Register. */ +#define CSR_MQM_DEQC_DEQC_NMQ_DEQ_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5C8) /* ENMQ Deq descpt count Register. */ +#define CSR_MQM_DEQC_DEQC_NFMQ_DEQ_PKT_CNT_REG (CSR_MQM_DEQC_BASE + 0x5CC) /* ENFMQ Deq descpt count Register. */ +#define CSR_MQM_DEQC_DEQC_NMQ_DEQ_CMD_CNT_REG (CSR_MQM_DEQC_BASE + 0x5D0) /* ENMQ Deq cmd count Register. */ +#define CSR_MQM_DEQC_DEQC_NFMQ_DEQ_CMD_CNT_REG (CSR_MQM_DEQC_BASE + 0x5D4) /* ENFMQ Deq cmd count Register. */ +#define CSR_MQM_DEQC_DEQC_NFMQ_EMPT_SCH_CNT_REG (CSR_MQM_DEQC_BASE + 0x5D8) /* DEQC Non-filter MQ EMPT schedule count \ + */ +#define CSR_MQM_DEQC_DEQC_NMQ_EMPT_SCH_CNT_REG (CSR_MQM_DEQC_BASE + 0x5DC) /* DEQC Normal MQ EMPT schedule count */ +#define CSR_MQM_DEQC_DEQC_ECC_1BIT_ERR_CNT_REG (CSR_MQM_DEQC_BASE + 0x5E0) /* DEQC MEMORY ECC 1BIT ERR count */ +#define CSR_MQM_DEQC_DEQC_ECC_2BIT_ERR_CNT_REG (CSR_MQM_DEQC_BASE + 0x5E4) /* DEQC MEMORY ECC 2BIT ERR count */ +#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_CFG_REG (CSR_MQM_DEQC_BASE + 0x5E8) /* DEQC_MQ DFX NUM configure */ +#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_UP_CNT_REG (CSR_MQM_DEQC_BASE + 0x5EC) /* DEQC_MQ DFX NUM ENQ UP count */ +#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_DEQ_CMD_CNT_REG (CSR_MQM_DEQC_BASE + 0x5F0) /* DEQC_MQ DFX NUM DEQ CMD count */ +#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_DEQ_NUM_CNT_REG (CSR_MQM_DEQC_BASE + 0x5F4) /* DEQC_MQ DFX NUM DEQ NUM count */ +#define CSR_MQM_DEQC_DEQC_SCH_MQ_DFX_EMPT_SCH_CNT_REG \ + (CSR_MQM_DEQC_BASE + 0x5F8) /* DEQC_MQ DFX NUM DEQ EMPT SCH count */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_0_REG \ + (CSR_MQM_DEQC_BASE + 0x600) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_1_REG \ + (CSR_MQM_DEQC_BASE + 0x604) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_2_REG \ + (CSR_MQM_DEQC_BASE + 0x608) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_3_REG \ + (CSR_MQM_DEQC_BASE + 0x60C) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_4_REG \ + (CSR_MQM_DEQC_BASE + 0x610) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_5_REG \ + (CSR_MQM_DEQC_BASE + 0x614) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_6_REG \ + (CSR_MQM_DEQC_BASE + 0x618) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NMQ_HOST_EP_COS_XON_ST_7_REG \ + (CSR_MQM_DEQC_BASE + 0x61C) /* ENMQ host_ep_cos Node XON State Table */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_0_REG \ + (CSR_MQM_DEQC_BASE + 0x620) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_1_REG \ + (CSR_MQM_DEQC_BASE + 0x624) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_2_REG \ + (CSR_MQM_DEQC_BASE + 0x628) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_3_REG \ + (CSR_MQM_DEQC_BASE + 0x62C) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_4_REG \ + (CSR_MQM_DEQC_BASE + 0x630) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_5_REG \ + (CSR_MQM_DEQC_BASE + 0x634) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_6_REG \ + (CSR_MQM_DEQC_BASE + 0x638) /* ENFMQ host_ep_cos Node XON State Table0 */ +#define CSR_MQM_DEQC_DEQC_NFMQ_HOST_EP_COS_XON_ST0_7_REG \ + (CSR_MQM_DEQC_BASE + 0x63C) /* ENFMQ host_ep_cos Node XON State Table0 */ + +#endif // MQM_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_c_union_define.h new file mode 100644 index 000000000..6f24eea08 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_c_union_define.h @@ -0,0 +1,2285 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : oq_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/01/20 15:07:14 Create file +// ****************************************************************************** + +#ifndef OQ_C_UNION_DEFINE_H +#define OQ_C_UNION_DEFINE_H + +/* Define the union csr_qu_versions_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_versions_u; + +/* Define the union csr_oq_mode_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 16; /* [15:0] */ + u32 csr_oq_other_uncrt_err2itf_en : 1; /* [16] */ + u32 csr_oq_ram_uncrt_err2itf_en : 1; /* [17] */ + u32 csr_oq_mem_init_start : 1; /* [18] */ + u32 csr_oq_mem_ecc_bypass : 1; /* [19] */ + u32 csr_oq_mem_ecc_req : 2; /* [21:20] */ + u32 csr_oq_net_loopback_pre_adj : 4; /* [25:22] */ + u32 csr_oq_net_loopback_prealloc_en : 1; /* [26] */ + u32 csr_oq_hst_dma_coalescing_en : 4; /* [30:27] */ + u32 csr_oq_dma_rcmd_prealloc_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_mode_u; + +/* Define the union csr_oq_mode1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_tpmem_timing_ctrl : 8; /* [7:0] */ + u32 csr_oq_spmem_timing_ctrl : 8; /* [15:8] */ + u32 csr_oq_tpmem_power_ctrl : 3; /* [18:16] */ + u32 csr_oq_spmem_power_ctrl : 3; /* [21:19] */ + u32 rsv_1 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_mode1_u; + +/* Define the union csr_oq_desenq_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_disenq_oqid : 16; /* [15:0] */ + u32 rsv_2 : 15; /* [30:16] */ + u32 csr_oq_disenq_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_desenq_cfg_u; + +/* Define the union csr_oq_pthru_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_port_pthru_nside : 8; /* [7:0] */ + u32 csr_oq_port_pthru_hside : 6; /* [13:8] */ + u32 csr_oq_pthu_bd_ctr_nside : 8; /* [21:14] */ + u32 csr_oq_pthu_bd_ctr_hside : 6; /* [27:22] */ + u32 csr_oq_dma_rcmd_pthu_en : 1; /* [28] */ + u32 rsv_3 : 2; /* [30:29] */ + u32 csr_oq_port_pthru_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_cfg_u; + +/* Define the union csr_oq_pthru_bd_ctr_win_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_win_len_nside : 10; /* [9:0] */ + u32 csr_oq_win_len_hside : 10; /* [19:10] */ + u32 rsv_4 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_win_cfg_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck0 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck1 : 12; /* [23:12] */ + u32 rsv_5 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg0_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck2 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck3 : 12; /* [23:12] */ + u32 rsv_6 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg1_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck4 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck5 : 12; /* [23:12] */ + u32 rsv_7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg2_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck6 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck7 : 12; /* [23:12] */ + u32 rsv_8 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg3_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck8 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck9 : 12; /* [23:12] */ + u32 rsv_9 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg4_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck10 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck11 : 12; /* [23:12] */ + u32 rsv_10 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg5_u; + +/* Define the union csr_oq_pthru_bd_ctr_max_pthu_cfg6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_max_pthu_pck12 : 12; /* [11:0] */ + u32 csr_oq_max_pthu_pck13 : 12; /* [23:12] */ + u32 rsv_11 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_pthru_bd_ctr_max_pthu_cfg6_u; + +/* Define the union csr_oq_fifo_af_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_nrq_af_th : 6; /* [5:0] */ + u32 csr_oq_sfifo_hrq_af_th : 6; /* [11:6] */ + u32 csr_oq_sfifo_mdp_drp_af_th : 5; /* [16:12] */ + u32 rsv_12 : 1; /* [17] */ + u32 csr_oq_sfifo_stlfq_fcnp_af_th : 5; /* [22:18] */ + u32 rsv_13 : 1; /* [23] */ + u32 csr_oq_sfifo_stffq0_fcnp_af_th : 5; /* [28:24] */ + u32 rsv_14 : 1; /* [29] */ + u32 rsv_15 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_af_cfg0_u; + +/* Define the union csr_oq_fifo_af_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_stffq1_fcnp_af_th : 5; /* [4:0] */ + u32 rsv_16 : 1; /* [5] */ + u32 csr_oq_sfifo_stlfq_dsp_af_th : 6; /* [11:6] */ + u32 csr_oq_sfifo_stffq0_dsp_af_th : 6; /* [17:12] */ + u32 csr_oq_sfifo_stffq1_dsp_af_th : 6; /* [23:18] */ + u32 csr_oq_sfifo_stliq_fp_af_th : 6; /* [29:24] */ + u32 rsv_17 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_af_cfg1_u; + +/* Define the union csr_oq_fifo_af_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_stfiq_fp_af_th : 6; /* [5:0] */ + u32 csr_oq_sfifo_stlfq_rep_af_th : 6; /* [11:6] */ + u32 rsv_18 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_af_cfg2_u; + +/* Define the union csr_oq_fifo_ae_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_nrq_ae_th : 6; /* [5:0] */ + u32 csr_oq_sfifo_hrq_ae_th : 6; /* [11:6] */ + u32 csr_oq_sfifo_mdp_drp_ae_th : 5; /* [16:12] */ + u32 rsv_19 : 1; /* [17] */ + u32 csr_oq_sfifo_stlfq_fcnp_ae_th : 5; /* [22:18] */ + u32 rsv_20 : 1; /* [23] */ + u32 csr_oq_sfifo_stffq0_fcnp_ae_th : 5; /* [28:24] */ + u32 rsv_21 : 1; /* [29] */ + u32 rsv_22 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_ae_cfg0_u; + +/* Define the union csr_oq_fifo_ae_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_stffq1_fcnp_ae_th : 5; /* [4:0] */ + u32 rsv_23 : 1; /* [5] */ + u32 csr_oq_sfifo_stlfq_dsp_ae_th : 6; /* [11:6] */ + u32 csr_oq_sfifo_stffq0_dsp_ae_th : 6; /* [17:12] */ + u32 csr_oq_sfifo_stffq1_dsp_ae_th : 6; /* [23:18] */ + u32 csr_oq_sfifo_stliq_fp_ae_th : 6; /* [29:24] */ + u32 rsv_24 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_ae_cfg1_u; + +/* Define the union csr_oq_fifo_ae_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sfifo_stfiq_fp_ae_th : 6; /* [5:0] */ + u32 csr_oq_sfifo_stlfq_rep_ae_th : 6; /* [11:6] */ + u32 rsv_25 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_ae_cfg2_u; + +/* Define the union csr_oq_hst01_coalescing_watermark_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst0_coalescing_watermark : 16; /* [15:0] */ + u32 csr_oq_hst1_coalescing_watermark : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst01_coalescing_watermark_u; + +/* Define the union csr_oq_hst23_coalescing_watermark_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst2_coalescing_watermark : 16; /* [15:0] */ + u32 csr_oq_hst3_coalescing_watermark : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst23_coalescing_watermark_u; + +/* Define the union csr_oq_hst0_coalescing_watchdog_exp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst0_coalescing_watchdog_exp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst0_coalescing_watchdog_exp_u; + +/* Define the union csr_oq_hst1_coalescing_watchdog_exp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst1_coalescing_watchdog_exp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst1_coalescing_watchdog_exp_u; + +/* Define the union csr_oq_hst2_coalescing_watchdog_exp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst2_coalescing_watchdog_exp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst2_coalescing_watchdog_exp_u; + +/* Define the union csr_oq_hst3_coalescing_watchdog_exp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_hst3_coalescing_watchdog_exp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_hst3_coalescing_watchdog_exp_u; + +/* Define the union csr_oq_aging_host_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_host_aging_rstep_len : 31; /* [30:0] */ + u32 csr_oq_host_aging_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_aging_host_cfg_u; + +/* Define the union csr_oq_aging_net_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_net_aging_rstep_len : 31; /* [30:0] */ + u32 csr_oq_net_aging_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_aging_net_cfg_u; + +/* Define the union csr_oq_wrr_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_wrr_stf_fq0_weight : 4; /* [3:0] */ + u32 csr_oq_wrr_stf_fq1_weight : 4; /* [7:4] */ + u32 csr_oq_wrr_stl_fq_weight : 4; /* [11:8] */ + u32 csr_oq_wrr_stf_iq_weight : 4; /* [15:12] */ + u32 csr_oq_wrr_stl_iq_weight : 4; /* [19:16] */ + u32 rsv_26 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_wrr_weight_cfg_u; + +/* Define the union csr_oq_nreal_deq_dpl_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_nreal_deq_dpl_len : 18; /* [17:0] */ + u32 rsv_27 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_nreal_deq_dpl_len_u; + +/* Define the union csr_oq_latency_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_sample_mode : 1; /* [0] */ + u32 csr_oq_spec_port_en : 1; /* [1] */ + u32 csr_oq_done_clr : 1; /* [2] */ + u32 rsv_28 : 1; /* [3] */ + u32 csr_oq_spec_port_num : 4; /* [7:4] */ + u32 csr_oq_spec_pptr_typ : 10; /* [17:8] */ + u32 rsv_29 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_latency_cfg_u; + +/* Define the union csr_oq_latency_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_sample_done : 1; /* [0] */ + u32 rsv_30 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_latency_sta_u; + +/* Define the union csr_oq_sample_tmr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_sample_tmr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_sample_tmr_u; + +/* Define the union csr_oq_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_31 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_32 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int_vector_u; + +/* Define the union csr_oq_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 7; /* [6:0] */ + u32 rsv_33 : 9; /* [15:7] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int_u; + +/* Define the union csr_oq_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 7; /* [6:0] */ + u32 rsv_34 : 9; /* [15:7] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int_en_u; + +/* Define the union csr_oq_int0_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_1bit_ecc_err : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 oq_int0_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int0_sticky_u; + +/* Define the union csr_oq_int1_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_2bit_ecc_err : 1; /* [0] */ + u32 int_insrt1 : 1; /* [1] */ + u32 oq_int1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int1_sticky_u; + +/* Define the union csr_oq_int2_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_fifo_overflow : 1; /* [0] */ + u32 int_insrt2 : 1; /* [1] */ + u32 oq_int2_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int2_sticky_u; + +/* Define the union csr_oq_int3_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_fifo_underflow : 1; /* [0] */ + u32 int_insrt3 : 1; /* [1] */ + u32 oq_int3_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int3_sticky_u; + +/* Define the union csr_oq_int4_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_host_age_happen : 1; /* [0] */ + u32 int_insrt4 : 1; /* [1] */ + u32 oq_int4_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int4_sticky_u; + +/* Define the union csr_oq_int5_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_network_age_happen : 1; /* [0] */ + u32 int_insrt5 : 1; /* [1] */ + u32 oq_int5_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int5_sticky_u; + +/* Define the union csr_oq_int6_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_empty_queue_deq_int : 1; /* [0] */ + u32 int_insrt6 : 1; /* [1] */ + u32 oq_int6_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_int6_sticky_u; + +/* Define the union csr_oq_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_ctrl_u; + +/* Define the union csr_oq_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_timeout_u; + +/* Define the union csr_oq_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_dat0_u; + +/* Define the union csr_oq_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_data1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_dat1_u; + +/* Define the union csr_oq_indrect_dat2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_data2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_dat2_u; + +/* Define the union csr_oq_indrect_dat3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_oq_indrect_data3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_indrect_dat3_u; + +/* Define the union csr_oq_fifo_fill0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_fp_fifo_fill : 6; /* [5:0] */ + u32 stfiq_fp_fifo_fill : 6; /* [11:6] */ + u32 stffq0_dsp_fifo_fill : 6; /* [17:12] */ + u32 stffq1_dsp_fifo_fill : 6; /* [23:18] */ + u32 stlfq_dsp_fifo_fill : 6; /* [29:24] */ + u32 rsv_35 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_fill0_u; + +/* Define the union csr_oq_fifo_fill1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stlfq_fcnp_fifo_fill : 5; /* [4:0] */ + u32 rsv_36 : 1; /* [5] */ + u32 mdp_fifo_fill : 5; /* [10:6] */ + u32 rsv_37 : 1; /* [11] */ + u32 nrq_fifo_fill : 6; /* [17:12] */ + u32 hrq_fifo_fill : 6; /* [23:18] */ + u32 stlfq_rep_fifo_fill : 6; /* [29:24] */ + u32 rsv_38 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_fill1_u; + +/* Define the union csr_oq_fifo_fill2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stffq0_fcnp_fifo_fill : 5; /* [4:0] */ + u32 rsv_39 : 1; /* [5] */ + u32 stffq1_fcnp_fifo_fill : 5; /* [10:6] */ + u32 rsv_40 : 1; /* [11] */ + u32 rsv_41 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_fifo_fill2_u; + +/* Define the union csr_oq_mem_init_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_init_done : 1; /* [0] */ + u32 rsv_42 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_mem_init_done_u; + +/* Define the union csr_oq_csr_stlfq_dsp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_packet_cnt_u; + +/* Define the union csr_oq_csr_stliq_fp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stliq_fp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stliq_fp_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_bi_dsp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_bi_dsp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_bi_dsp_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_bi_dsp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_bi_dsp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_bi_dsp_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_rep_info_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_rep_info_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_rep_info_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_tso12_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_tso12_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_tso12_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_tso12_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_tso12_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_tso12_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_tso12_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_tso12_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_tso12_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_tso12_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_tso12_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_tso12_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_lro12_network_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_lro12_network_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_lro12_network_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_lro12_network_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_lro12_network_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_lro12_network_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_lro12_network_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_lro12_network_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_lro12_network_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_lro12_network_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_lro12_network_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_lro12_network_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_lro12_host_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_lro12_host_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_lro12_host_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_lro12_host_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_lro12_host_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_lro12_host_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_lro12_host_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_lro12_host_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_lro12_host_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_lro12_host_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_lro12_host_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_lro12_host_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_tso3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_tso3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_tso3_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_tso3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_tso3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_tso3_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_tso3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_tso3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_tso3_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_tso3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_tso3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_tso3_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_lro3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_lro3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_lro3_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_lro3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_lro3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_lro3_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_lro3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_lro3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_lro3_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_lro3_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_lro3_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_lro3_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_rep_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_rep_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_rep_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_rep_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_rep_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_rep_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_rep_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_rep_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_rep_packet_cnt_u; + +/* Define the union csr_oq_csr_stlfq_dsp_lrep_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_dsp_lrep_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_dsp_lrep_cnt_u; + +/* Define the union csr_oq_csr_stffq0_dsp_lrep_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_dsp_lrep_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_dsp_lrep_cnt_u; + +/* Define the union csr_oq_csr_stffq1_dsp_lrep_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_dsp_lrep_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_dsp_lrep_cnt_u; + +/* Define the union csr_oq_csr_orep_rep_cnt_add_inc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_orep_rep_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_orep_rep_cnt_add_inc_u; + +/* Define the union csr_oq_csr_orep_lrep_inc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_orep_lrep_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_orep_lrep_inc_u; + +/* Define the union csr_oq_csr_stlfq_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq0_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_stffq1_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_stliq_fp_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stliq_fp_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stliq_fp_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_stfiq_fp_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_fp_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_fp_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_mdp_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_mdp_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_mdp_packet_cnt_u; + +/* Define the union csr_oq_csr_hrq_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_hrq_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_hrq_packet_cnt_u; + +/* Define the union csr_oq_csr_hrq_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_hrq_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_hrq_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_nrq_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_nrq_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_nrq_packet_cnt_u; + +/* Define the union csr_oq_csr_rqc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_rqc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_rqc_cnt_u; + +/* Define the union csr_oq_csr_rqc_rvld_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_rqc_rvld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_rqc_rvld_cnt_u; + +/* Define the union csr_oq_csr_host_pthru_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_host_pthru_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_host_pthru_cnt_u; + +/* Define the union csr_oq_csr_network_pthru_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_network_pthru_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_network_pthru_cnt_u; + +/* Define the union csr_oq_csr_network_check_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_network_check_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_network_check_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_network_dissenq_drop_packet_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_network_dissenq_drop_packet : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_network_dissenq_drop_packet_u; + +/* Define the union csr_oq_csr_pie_check_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_pie_check_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_pie_check_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_host_dissenq_drop_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_host_dissenq_drop_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_host_dissenq_drop_packet_cnt_u; + +/* Define the union csr_oq_csr_eqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_eqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_eqs_cnt_u; + +/* Define the union csr_oq_csr_dqr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_dqr_cnt_u; + +/* Define the union csr_oq_csr_not_real_deq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_not_real_deq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_not_real_deq_u; + +/* Define the union csr_oq_csr_deq_empty_queue_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_deq_empty_queue : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_deq_empty_queue_u; + +/* Define the union csr_oq_csr_deq_bp_by_prm_icd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_deq_bp_by_prm_icd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_deq_bp_by_prm_icd_u; + +/* Define the union csr_oq_csr_deq_bp_by_prm_dcd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_deq_bp_by_prm_dcd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_deq_bp_by_prm_dcd_u; + +/* Define the union csr_oq_csr_deq_bp_by_stfiq_lb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_deq_bp_by_stfiq_lb : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_deq_bp_by_stfiq_lb_u; + +/* Define the union csr_oq_csr_stfiq_oq_fcnp_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stfiq_oq_fcnp_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stfiq_oq_fcnp_bp_cnt_u; + +/* Define the union csr_oq_csr_cpbtx_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_cpbtx_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_cpbtx_bp_cnt_u; + +/* Define the union csr_oq_csr_cpbrx_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_cpbrx_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_cpbrx_bp_cnt_u; + +/* Define the union csr_oq_csr_dqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_dqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_dqs_cnt_u; + +/* Define the union csr_oq_csr_enq_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_host_2k_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_host_2k_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_host_2k_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_host_pie_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_host_pie_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_host_pie_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_host_ddr_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_host_ddr_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_host_ddr_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_host_loopback_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_host_loopback_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_host_loopback_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_network_4k_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_network_4k_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_network_4k_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_network_loopback_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_network_loopback_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_network_loopback_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_enq_drop_queue_packet_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_enq_drop_queue_packet_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_enq_drop_queue_packet_cnt_u; + +/* Define the union csr_oq_csr_tpd_to_citf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_tpd_to_citf_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_tpd_to_citf_cnt_u; + +/* Define the union csr_oq_csr_tid_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_tid_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_tid_cnt_u; + +/* Define the union csr_oq_csr_stp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stp_cnt_u; + +/* Define the union csr_oq_csr_stffq0_fcnp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq0_fcnp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq0_fcnp_u; + +/* Define the union csr_oq_csr_stffq1_fcnp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stffq1_fcnp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stffq1_fcnp_u; + +/* Define the union csr_oq_csr_stlfq_fcnp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_stlfq_fcnp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_stlfq_fcnp_u; + +/* Define the union csr_oq_csr_oq_esch_fcnp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_oq_esch_fcnp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_oq_esch_fcnp_u; + +/* Define the union csr_oq_csr_oq_stfiq_fcnp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_oq_stfiq_fcnp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_oq_stfiq_fcnp_u; + +/* Define the union csr_oq_csr_epd_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_tso12_to_network_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_tso12_to_network_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_tso12_to_network_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_lro12_to_network_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_lro12_to_network_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_lro12_to_network_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_lro12_to_host_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_lro12_to_host_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_lro12_to_host_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_tso3_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_tso3_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_tso3_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_lro3_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_lro3_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_lro3_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_tso12_piece_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_tso12_piece_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_tso12_piece_cnt_u; + +/* Define the union csr_oq_csr_epd_lro12_piece_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_lro12_piece_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_lro12_piece_cnt_u; + +/* Define the union csr_oq_csr_epd_dmarcnd_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_dmarcnd_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_dmarcnd_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_epd_rep_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_epd_rep_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_epd_rep_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_drop_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_drop_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_drop_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_dpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_dpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_dpl_cnt_u; + +/* Define the union csr_oq_csr_olb_to_iq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_olb_to_iq_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_olb_to_iq_cnt_u; + +/* Define the union csr_oq_csr_disable_epd_to_cpb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_disable_epd_to_cpb_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_disable_epd_to_cpb_cnt_u; + +/* Define the union csr_oq_csr_prls_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_prls_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_prls_cnt_u; + +/* Define the union csr_oq_csr_icd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_icd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_icd_cnt_u; + +/* Define the union csr_oq_csr_dcd_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_dcd_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_dcd_cnt_u; + +/* Define the union csr_oq_csr_pthru_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_pthru_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_pthru_cnt_u; + +/* Define the union csr_oq_mem_ecc_1bit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_mem_1bit_ecc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_mem_ecc_1bit_cnt_u; + +/* Define the union csr_oq_csr_drop_queue_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_csr_drop_queue_depth : 16; /* [15:0] */ + u32 rsv_43 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_csr_drop_queue_depth_u; + +/* Define the union csr_oq_bp_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_oq_orep_bp : 1; /* [0] */ + u32 esch_qu_epd_bp_dps : 14; /* [14:1] */ + u32 cpb_oq_tx_bp : 1; /* [15] */ + u32 cpb_oq_rx_bp : 1; /* [16] */ + u32 iq_oq_olb_bp : 1; /* [17] */ + u32 stfiq_oq_fcnp_bp : 1; /* [18] */ + u32 cpb_qu_drp_bp : 1; /* [19] */ + u32 prm_oq_prls_bp : 1; /* [20] */ + u32 prm_oq_icd_q_fc_mux : 1; /* [21] */ + u32 prm_oq_icd_afull : 1; /* [22] */ + u32 prm_oq_dcd_afull : 1; /* [23] */ + u32 rsv_44 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_bp_status_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_oq_versions_u qu_versions; /* 0 */ + volatile csr_oq_mode_u oq_mode; /* 4 */ + volatile csr_oq_mode1_u oq_mode1; /* 8 */ + volatile csr_oq_desenq_cfg_u oq_desenq_cfg; /* C */ + volatile csr_oq_pthru_cfg_u oq_pthru_cfg; /* 10 */ + volatile csr_oq_pthru_bd_ctr_win_cfg_u oq_pthru_bd_ctr_win_cfg; /* 14 */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg0_u oq_pthru_bd_ctr_max_pthu_cfg0; /* 18 */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg1_u oq_pthru_bd_ctr_max_pthu_cfg1; /* 1C */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg2_u oq_pthru_bd_ctr_max_pthu_cfg2; /* 20 */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg3_u oq_pthru_bd_ctr_max_pthu_cfg3; /* 24 */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg4_u oq_pthru_bd_ctr_max_pthu_cfg4; /* 28 */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg5_u oq_pthru_bd_ctr_max_pthu_cfg5; /* 2C */ + volatile csr_oq_pthru_bd_ctr_max_pthu_cfg6_u oq_pthru_bd_ctr_max_pthu_cfg6; /* 30 */ + volatile csr_oq_fifo_af_cfg0_u oq_fifo_af_cfg0; /* 34 */ + volatile csr_oq_fifo_af_cfg1_u oq_fifo_af_cfg1; /* 38 */ + volatile csr_oq_fifo_af_cfg2_u oq_fifo_af_cfg2; /* 3C */ + volatile csr_oq_fifo_ae_cfg0_u oq_fifo_ae_cfg0; /* 40 */ + volatile csr_oq_fifo_ae_cfg1_u oq_fifo_ae_cfg1; /* 44 */ + volatile csr_oq_fifo_ae_cfg2_u oq_fifo_ae_cfg2; /* 48 */ + volatile csr_oq_hst01_coalescing_watermark_u oq_hst01_coalescing_watermark; /* 4C */ + volatile csr_oq_hst23_coalescing_watermark_u oq_hst23_coalescing_watermark; /* 50 */ + volatile csr_oq_hst0_coalescing_watchdog_exp_u oq_hst0_coalescing_watchdog_exp; /* 54 */ + volatile csr_oq_hst1_coalescing_watchdog_exp_u oq_hst1_coalescing_watchdog_exp; /* 58 */ + volatile csr_oq_hst2_coalescing_watchdog_exp_u oq_hst2_coalescing_watchdog_exp; /* 5C */ + volatile csr_oq_hst3_coalescing_watchdog_exp_u oq_hst3_coalescing_watchdog_exp; /* 60 */ + volatile csr_oq_aging_host_cfg_u oq_aging_host_cfg; /* 64 */ + volatile csr_oq_aging_net_cfg_u oq_aging_net_cfg; /* 68 */ + volatile csr_oq_wrr_weight_cfg_u oq_wrr_weight_cfg; /* 6C */ + volatile csr_oq_nreal_deq_dpl_len_u oq_nreal_deq_dpl_len; /* 70 */ + volatile csr_oq_latency_cfg_u oq_latency_cfg; /* 74 */ + volatile csr_oq_latency_sta_u oq_latency_sta; /* 78 */ + volatile csr_oq_sample_tmr_u oq_sample_tmr; /* 7C */ + volatile csr_oq_int_vector_u oq_int_vector; /* 84 */ + volatile csr_oq_int_u oq_int; /* 88 */ + volatile csr_oq_int_en_u oq_int_en; /* 8C */ + volatile csr_oq_int0_sticky_u oq_int0_sticky; /* 90 */ + volatile csr_oq_int1_sticky_u oq_int1_sticky; /* 94 */ + volatile csr_oq_int2_sticky_u oq_int2_sticky; /* 98 */ + volatile csr_oq_int3_sticky_u oq_int3_sticky; /* 9C */ + volatile csr_oq_int4_sticky_u oq_int4_sticky; /* A0 */ + volatile csr_oq_int5_sticky_u oq_int5_sticky; /* A4 */ + volatile csr_oq_int6_sticky_u oq_int6_sticky; /* A8 */ + volatile csr_oq_indrect_ctrl_u oq_indrect_ctrl; /* AC */ + volatile csr_oq_indrect_timeout_u oq_indrect_timeout; /* B0 */ + volatile csr_oq_indrect_dat0_u oq_indrect_dat0; /* B4 */ + volatile csr_oq_indrect_dat1_u oq_indrect_dat1; /* B8 */ + volatile csr_oq_indrect_dat2_u oq_indrect_dat2; /* BC */ + volatile csr_oq_indrect_dat3_u oq_indrect_dat3; /* C0 */ + volatile csr_oq_fifo_fill0_u oq_fifo_fill0; /* C4 */ + volatile csr_oq_fifo_fill1_u oq_fifo_fill1; /* C8 */ + volatile csr_oq_fifo_fill2_u oq_fifo_fill2; /* CC */ + volatile csr_oq_mem_init_done_u oq_mem_init_done; /* D0 */ + volatile csr_oq_csr_stlfq_dsp_packet_cnt_u oq_csr_stlfq_dsp_packet_cnt; /* D4 */ + volatile csr_oq_csr_stffq0_dsp_packet_cnt_u oq_csr_stffq0_dsp_packet_cnt; /* D8 */ + volatile csr_oq_csr_stffq1_dsp_packet_cnt_u oq_csr_stffq1_dsp_packet_cnt; /* DC */ + volatile csr_oq_csr_stliq_fp_packet_cnt_u oq_csr_stliq_fp_packet_cnt; /* E0 */ + volatile csr_oq_csr_stfiq_fp_packet_cnt_u oq_csr_stfiq_fp_packet_cnt; /* E4 */ + volatile csr_oq_csr_stffq0_bi_dsp_packet_cnt_u oq_csr_stffq0_bi_dsp_packet_cnt; /* E8 */ + volatile csr_oq_csr_stffq1_bi_dsp_packet_cnt_u oq_csr_stffq1_bi_dsp_packet_cnt; /* EC */ + volatile csr_oq_csr_stlfq_rep_info_cnt_u oq_csr_stlfq_rep_info_cnt; /* F0 */ + volatile csr_oq_csr_stlfq_dsp_tso12_packet_cnt_u oq_csr_stlfq_dsp_tso12_packet_cnt; /* F4 */ + volatile csr_oq_csr_stffq0_dsp_tso12_packet_cnt_u oq_csr_stffq0_dsp_tso12_packet_cnt; /* F8 */ + volatile csr_oq_csr_stffq1_dsp_tso12_packet_cnt_u oq_csr_stffq1_dsp_tso12_packet_cnt; /* FC */ + volatile csr_oq_csr_stfiq_fp_tso12_packet_cnt_u oq_csr_stfiq_fp_tso12_packet_cnt; /* 100 */ + volatile csr_oq_csr_stlfq_dsp_lro12_network_packet_cnt_u oq_csr_stlfq_dsp_lro12_network_packet_cnt; /* 104 */ + volatile csr_oq_csr_stffq0_dsp_lro12_network_packet_cnt_u oq_csr_stffq0_dsp_lro12_network_packet_cnt; /* 108 */ + volatile csr_oq_csr_stffq1_dsp_lro12_network_packet_cnt_u oq_csr_stffq1_dsp_lro12_network_packet_cnt; /* 10C */ + volatile csr_oq_csr_stfiq_fp_lro12_network_packet_cnt_u oq_csr_stfiq_fp_lro12_network_packet_cnt; /* 110 */ + volatile csr_oq_csr_stlfq_dsp_lro12_host_packet_cnt_u oq_csr_stlfq_dsp_lro12_host_packet_cnt; /* 114 */ + volatile csr_oq_csr_stffq0_dsp_lro12_host_packet_cnt_u oq_csr_stffq0_dsp_lro12_host_packet_cnt; /* 118 */ + volatile csr_oq_csr_stffq1_dsp_lro12_host_packet_cnt_u oq_csr_stffq1_dsp_lro12_host_packet_cnt; /* 11C */ + volatile csr_oq_csr_stfiq_fp_lro12_host_packet_cnt_u oq_csr_stfiq_fp_lro12_host_packet_cnt; /* 120 */ + volatile csr_oq_csr_stlfq_dsp_tso3_packet_cnt_u oq_csr_stlfq_dsp_tso3_packet_cnt; /* 124 */ + volatile csr_oq_csr_stffq0_dsp_tso3_packet_cnt_u oq_csr_stffq0_dsp_tso3_packet_cnt; /* 128 */ + volatile csr_oq_csr_stffq1_dsp_tso3_packet_cnt_u oq_csr_stffq1_dsp_tso3_packet_cnt; /* 12C */ + volatile csr_oq_csr_stfiq_fp_tso3_packet_cnt_u oq_csr_stfiq_fp_tso3_packet_cnt; /* 130 */ + volatile csr_oq_csr_stlfq_dsp_lro3_packet_cnt_u oq_csr_stlfq_dsp_lro3_packet_cnt; /* 134 */ + volatile csr_oq_csr_stffq0_dsp_lro3_packet_cnt_u oq_csr_stffq0_dsp_lro3_packet_cnt; /* 138 */ + volatile csr_oq_csr_stffq1_dsp_lro3_packet_cnt_u oq_csr_stffq1_dsp_lro3_packet_cnt; /* 13C */ + volatile csr_oq_csr_stfiq_fp_lro3_packet_cnt_u oq_csr_stfiq_fp_lro3_packet_cnt; /* 140 */ + volatile csr_oq_csr_stlfq_dsp_rep_packet_cnt_u oq_csr_stlfq_dsp_rep_packet_cnt; /* 144 */ + volatile csr_oq_csr_stffq0_dsp_rep_packet_cnt_u oq_csr_stffq0_dsp_rep_packet_cnt; /* 148 */ + volatile csr_oq_csr_stffq1_dsp_rep_packet_cnt_u oq_csr_stffq1_dsp_rep_packet_cnt; /* 14C */ + volatile csr_oq_csr_stlfq_dsp_lrep_cnt_u oq_csr_stlfq_dsp_lrep_cnt; /* 150 */ + volatile csr_oq_csr_stffq0_dsp_lrep_cnt_u oq_csr_stffq0_dsp_lrep_cnt; /* 154 */ + volatile csr_oq_csr_stffq1_dsp_lrep_cnt_u oq_csr_stffq1_dsp_lrep_cnt; /* 158 */ + volatile csr_oq_csr_orep_rep_cnt_add_inc_u oq_csr_orep_rep_cnt_add_inc; /* 15C */ + volatile csr_oq_csr_orep_lrep_inc_u oq_csr_orep_lrep_inc; /* 160 */ + volatile csr_oq_csr_stlfq_drop_packet_cnt_u oq_csr_stlfq_drop_packet_cnt; /* 164 */ + volatile csr_oq_csr_stffq0_drop_packet_cnt_u oq_csr_stffq0_drop_packet_cnt; /* 168 */ + volatile csr_oq_csr_stffq1_drop_packet_cnt_u oq_csr_stffq1_drop_packet_cnt; /* 16C */ + volatile csr_oq_csr_stliq_fp_drop_packet_cnt_u oq_csr_stliq_fp_drop_packet_cnt; /* 170 */ + volatile csr_oq_csr_stfiq_fp_drop_packet_cnt_u oq_csr_stfiq_fp_drop_packet_cnt; /* 174 */ + volatile csr_oq_csr_mdp_packet_cnt_u oq_csr_mdp_packet_cnt; /* 178 */ + volatile csr_oq_csr_hrq_packet_cnt_u oq_csr_hrq_packet_cnt; /* 17C */ + volatile csr_oq_csr_hrq_drop_packet_cnt_u oq_csr_hrq_drop_packet_cnt; /* 180 */ + volatile csr_oq_csr_nrq_packet_cnt_u oq_csr_nrq_packet_cnt; /* 184 */ + volatile csr_oq_csr_rqc_cnt_u oq_csr_rqc_cnt; /* 188 */ + volatile csr_oq_csr_rqc_rvld_cnt_u oq_csr_rqc_rvld_cnt; /* 18C */ + volatile csr_oq_csr_host_pthru_cnt_u oq_csr_host_pthru_cnt; /* 190 */ + volatile csr_oq_csr_network_pthru_cnt_u oq_csr_network_pthru_cnt; /* 194 */ + volatile csr_oq_csr_network_check_drop_packet_cnt_u oq_csr_network_check_drop_packet_cnt; /* 198 */ + volatile csr_oq_csr_network_dissenq_drop_packet_u oq_csr_network_dissenq_drop_packet; /* 19C */ + volatile csr_oq_csr_pie_check_drop_packet_cnt_u oq_csr_pie_check_drop_packet_cnt; /* 1A0 */ + volatile csr_oq_csr_host_dissenq_drop_packet_cnt_u oq_csr_host_dissenq_drop_packet_cnt; /* 1A4 */ + volatile csr_oq_csr_eqs_cnt_u oq_csr_eqs_cnt; /* 1A8 */ + volatile csr_oq_csr_dqr_cnt_u oq_csr_dqr_cnt; /* 1AC */ + volatile csr_oq_csr_not_real_deq_u oq_csr_not_real_deq; /* 1B0 */ + volatile csr_oq_csr_deq_empty_queue_u oq_csr_deq_empty_queue; /* 1B4 */ + volatile csr_oq_csr_deq_bp_by_prm_icd_u oq_csr_deq_bp_by_prm_icd; /* 1B8 */ + volatile csr_oq_csr_deq_bp_by_prm_dcd_u oq_csr_deq_bp_by_prm_dcd; /* 1BC */ + volatile csr_oq_csr_deq_bp_by_stfiq_lb_u oq_csr_deq_bp_by_stfiq_lb; /* 1C0 */ + volatile csr_oq_csr_stfiq_oq_fcnp_bp_cnt_u oq_csr_stfiq_oq_fcnp_bp_cnt; /* 1C4 */ + volatile csr_oq_csr_cpbtx_bp_cnt_u oq_csr_cpbtx_bp_cnt; /* 1C8 */ + volatile csr_oq_csr_cpbrx_bp_cnt_u oq_csr_cpbrx_bp_cnt; /* 1CC */ + volatile csr_oq_csr_dqs_cnt_u oq_csr_dqs_cnt; /* 1D0 */ + volatile csr_oq_csr_enq_packet_cnt_u oq_csr_enq_packet_cnt; /* 1D4 */ + volatile csr_oq_csr_enq_host_2k_queue_packet_cnt_u oq_csr_enq_host_2k_queue_packet_cnt; /* 1D8 */ + volatile csr_oq_csr_enq_host_pie_queue_packet_cnt_u oq_csr_enq_host_pie_queue_packet_cnt; /* 1DC */ + volatile csr_oq_csr_enq_host_ddr_queue_packet_cnt_u oq_csr_enq_host_ddr_queue_packet_cnt; /* 1E0 */ + volatile csr_oq_csr_enq_host_loopback_queue_packet_cnt_u oq_csr_enq_host_loopback_queue_packet_cnt; /* 1E4 */ + volatile csr_oq_csr_enq_network_4k_queue_packet_cnt_u oq_csr_enq_network_4k_queue_packet_cnt; /* 1E8 */ + volatile csr_oq_csr_enq_network_loopback_queue_packet_cnt_u oq_csr_enq_network_loopback_queue_packet_cnt; /* 1EC */ + volatile csr_oq_csr_enq_drop_queue_packet_cnt_u oq_csr_enq_drop_queue_packet_cnt; /* 1F0 */ + volatile csr_oq_csr_tpd_to_citf_cnt_u oq_csr_tpd_to_citf_cnt; /* 1F4 */ + volatile csr_oq_csr_tid_cnt_u oq_csr_tid_cnt; /* 1F8 */ + volatile csr_oq_csr_stp_cnt_u oq_csr_stp_cnt; /* 1FC */ + volatile csr_oq_csr_stffq0_fcnp_u oq_csr_stffq0_fcnp; /* 200 */ + volatile csr_oq_csr_stffq1_fcnp_u oq_csr_stffq1_fcnp; /* 204 */ + volatile csr_oq_csr_stlfq_fcnp_u oq_csr_stlfq_fcnp; /* 208 */ + volatile csr_oq_csr_oq_esch_fcnp_u oq_csr_oq_esch_fcnp; /* 20C */ + volatile csr_oq_csr_oq_stfiq_fcnp_u oq_csr_oq_stfiq_fcnp; /* 210 */ + volatile csr_oq_csr_epd_to_cpb_cnt_u oq_csr_epd_to_cpb_cnt; /* 214 */ + volatile csr_oq_csr_epd_tso12_to_network_cpb_cnt_u oq_csr_epd_tso12_to_network_cpb_cnt; /* 218 */ + volatile csr_oq_csr_epd_lro12_to_network_cpb_cnt_u oq_csr_epd_lro12_to_network_cpb_cnt; /* 21C */ + volatile csr_oq_csr_epd_lro12_to_host_cpb_cnt_u oq_csr_epd_lro12_to_host_cpb_cnt; /* 220 */ + volatile csr_oq_csr_epd_tso3_to_cpb_cnt_u oq_csr_epd_tso3_to_cpb_cnt; /* 224 */ + volatile csr_oq_csr_epd_lro3_to_cpb_cnt_u oq_csr_epd_lro3_to_cpb_cnt; /* 228 */ + volatile csr_oq_csr_epd_tso12_piece_cnt_u oq_csr_epd_tso12_piece_cnt; /* 22C */ + volatile csr_oq_csr_epd_lro12_piece_cnt_u oq_csr_epd_lro12_piece_cnt; /* 230 */ + volatile csr_oq_csr_epd_dmarcnd_to_cpb_cnt_u oq_csr_epd_dmarcnd_to_cpb_cnt; /* 234 */ + volatile csr_oq_csr_epd_rep_to_cpb_cnt_u oq_csr_epd_rep_to_cpb_cnt; /* 238 */ + volatile csr_oq_csr_drop_to_cpb_cnt_u oq_csr_drop_to_cpb_cnt; /* 23C */ + volatile csr_oq_csr_dpl_cnt_u oq_csr_dpl_cnt; /* 240 */ + volatile csr_oq_csr_olb_to_iq_cnt_u oq_csr_olb_to_iq_cnt; /* 244 */ + volatile csr_oq_csr_disable_epd_to_cpb_cnt_u oq_csr_disable_epd_to_cpb_cnt; /* 248 */ + volatile csr_oq_csr_prls_cnt_u oq_csr_prls_cnt; /* 24C */ + volatile csr_oq_csr_icd_cnt_u oq_csr_icd_cnt; /* 250 */ + volatile csr_oq_csr_dcd_cnt_u oq_csr_dcd_cnt; /* 254 */ + volatile csr_oq_csr_pthru_cnt_u oq_csr_pthru_cnt; /* 258 */ + volatile csr_oq_mem_ecc_1bit_cnt_u oq_mem_ecc_1bit_cnt; /* 25C */ + volatile csr_oq_csr_drop_queue_depth_u oq_csr_drop_queue_depth; /* 260 */ + volatile csr_oq_bp_status_u oq_bp_status; /* 264 */ +} S_qu_oq_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_oq_csr */ +extern volatile S_qu_oq_csr_REGS_TYPE *gopqu_oq_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetQU_VERSIONS_qu_version(unsigned int uqu_version); +int iSetOQ_MODE_csr_oq_other_uncrt_err2itf_en(unsigned int ucsr_oq_other_uncrt_err2itf_en); +int iSetOQ_MODE_csr_oq_ram_uncrt_err2itf_en(unsigned int ucsr_oq_ram_uncrt_err2itf_en); +int iSetOQ_MODE_csr_oq_mem_init_start(unsigned int ucsr_oq_mem_init_start); +int iSetOQ_MODE_csr_oq_mem_ecc_bypass(unsigned int ucsr_oq_mem_ecc_bypass); +int iSetOQ_MODE_csr_oq_mem_ecc_req(unsigned int ucsr_oq_mem_ecc_req); +int iSetOQ_MODE_csr_oq_net_loopback_pre_adj(unsigned int ucsr_oq_net_loopback_pre_adj); +int iSetOQ_MODE_csr_oq_net_loopback_prealloc_en(unsigned int ucsr_oq_net_loopback_prealloc_en); +int iSetOQ_MODE_csr_oq_hst_dma_coalescing_en(unsigned int ucsr_oq_hst_dma_coalescing_en); +int iSetOQ_MODE_csr_oq_dma_rcmd_prealloc_en(unsigned int ucsr_oq_dma_rcmd_prealloc_en); +int iSetOQ_MODE1_csr_oq_tpmem_timing_ctrl(unsigned int ucsr_oq_tpmem_timing_ctrl); +int iSetOQ_MODE1_csr_oq_spmem_timing_ctrl(unsigned int ucsr_oq_spmem_timing_ctrl); +int iSetOQ_MODE1_csr_oq_tpmem_power_ctrl(unsigned int ucsr_oq_tpmem_power_ctrl); +int iSetOQ_MODE1_csr_oq_spmem_power_ctrl(unsigned int ucsr_oq_spmem_power_ctrl); +int iSetOQ_DESENQ_CFG_csr_oq_disenq_oqid(unsigned int ucsr_oq_disenq_oqid); +int iSetOQ_DESENQ_CFG_csr_oq_disenq_en(unsigned int ucsr_oq_disenq_en); +int iSetOQ_PTHRU_CFG_csr_oq_port_pthru_nside(unsigned int ucsr_oq_port_pthru_nside); +int iSetOQ_PTHRU_CFG_csr_oq_port_pthru_hside(unsigned int ucsr_oq_port_pthru_hside); +int iSetOQ_PTHRU_CFG_csr_oq_pthu_bd_ctr_nside(unsigned int ucsr_oq_pthu_bd_ctr_nside); +int iSetOQ_PTHRU_CFG_csr_oq_pthu_bd_ctr_hside(unsigned int ucsr_oq_pthu_bd_ctr_hside); +int iSetOQ_PTHRU_CFG_csr_oq_dma_rcmd_pthu_en(unsigned int ucsr_oq_dma_rcmd_pthu_en); +int iSetOQ_PTHRU_CFG_csr_oq_port_pthru_en(unsigned int ucsr_oq_port_pthru_en); +int iSetOQ_PTHRU_BD_CTR_WIN_CFG_csr_oq_win_len_nside(unsigned int ucsr_oq_win_len_nside); +int iSetOQ_PTHRU_BD_CTR_WIN_CFG_csr_oq_win_len_hside(unsigned int ucsr_oq_win_len_hside); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG0_csr_oq_max_pthu_pck0(unsigned int ucsr_oq_max_pthu_pck0); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG0_csr_oq_max_pthu_pck1(unsigned int ucsr_oq_max_pthu_pck1); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG1_csr_oq_max_pthu_pck2(unsigned int ucsr_oq_max_pthu_pck2); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG1_csr_oq_max_pthu_pck3(unsigned int ucsr_oq_max_pthu_pck3); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG2_csr_oq_max_pthu_pck4(unsigned int ucsr_oq_max_pthu_pck4); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG2_csr_oq_max_pthu_pck5(unsigned int ucsr_oq_max_pthu_pck5); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG3_csr_oq_max_pthu_pck6(unsigned int ucsr_oq_max_pthu_pck6); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG3_csr_oq_max_pthu_pck7(unsigned int ucsr_oq_max_pthu_pck7); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG4_csr_oq_max_pthu_pck8(unsigned int ucsr_oq_max_pthu_pck8); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG4_csr_oq_max_pthu_pck9(unsigned int ucsr_oq_max_pthu_pck9); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG5_csr_oq_max_pthu_pck10(unsigned int ucsr_oq_max_pthu_pck10); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG5_csr_oq_max_pthu_pck11(unsigned int ucsr_oq_max_pthu_pck11); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG6_csr_oq_max_pthu_pck12(unsigned int ucsr_oq_max_pthu_pck12); +int iSetOQ_PTHRU_BD_CTR_MAX_PTHU_CFG6_csr_oq_max_pthu_pck13(unsigned int ucsr_oq_max_pthu_pck13); +int iSetOQ_FIFO_AF_CFG0_csr_oq_sfifo_nrq_af_th(unsigned int ucsr_oq_sfifo_nrq_af_th); +int iSetOQ_FIFO_AF_CFG0_csr_oq_sfifo_hrq_af_th(unsigned int ucsr_oq_sfifo_hrq_af_th); +int iSetOQ_FIFO_AF_CFG0_csr_oq_sfifo_mdp_drp_af_th(unsigned int ucsr_oq_sfifo_mdp_drp_af_th); +int iSetOQ_FIFO_AF_CFG0_csr_oq_sfifo_stlfq_fcnp_af_th(unsigned int ucsr_oq_sfifo_stlfq_fcnp_af_th); +int iSetOQ_FIFO_AF_CFG0_csr_oq_sfifo_stffq0_fcnp_af_th(unsigned int ucsr_oq_sfifo_stffq0_fcnp_af_th); +int iSetOQ_FIFO_AF_CFG1_csr_oq_sfifo_stffq1_fcnp_af_th(unsigned int ucsr_oq_sfifo_stffq1_fcnp_af_th); +int iSetOQ_FIFO_AF_CFG1_csr_oq_sfifo_stlfq_dsp_af_th(unsigned int ucsr_oq_sfifo_stlfq_dsp_af_th); +int iSetOQ_FIFO_AF_CFG1_csr_oq_sfifo_stffq0_dsp_af_th(unsigned int ucsr_oq_sfifo_stffq0_dsp_af_th); +int iSetOQ_FIFO_AF_CFG1_csr_oq_sfifo_stffq1_dsp_af_th(unsigned int ucsr_oq_sfifo_stffq1_dsp_af_th); +int iSetOQ_FIFO_AF_CFG1_csr_oq_sfifo_stliq_fp_af_th(unsigned int ucsr_oq_sfifo_stliq_fp_af_th); +int iSetOQ_FIFO_AF_CFG2_csr_oq_sfifo_stfiq_fp_af_th(unsigned int ucsr_oq_sfifo_stfiq_fp_af_th); +int iSetOQ_FIFO_AF_CFG2_csr_oq_sfifo_stlfq_rep_af_th(unsigned int ucsr_oq_sfifo_stlfq_rep_af_th); +int iSetOQ_FIFO_AE_CFG0_csr_oq_sfifo_nrq_ae_th(unsigned int ucsr_oq_sfifo_nrq_ae_th); +int iSetOQ_FIFO_AE_CFG0_csr_oq_sfifo_hrq_ae_th(unsigned int ucsr_oq_sfifo_hrq_ae_th); +int iSetOQ_FIFO_AE_CFG0_csr_oq_sfifo_mdp_drp_ae_th(unsigned int ucsr_oq_sfifo_mdp_drp_ae_th); +int iSetOQ_FIFO_AE_CFG0_csr_oq_sfifo_stlfq_fcnp_ae_th(unsigned int ucsr_oq_sfifo_stlfq_fcnp_ae_th); +int iSetOQ_FIFO_AE_CFG0_csr_oq_sfifo_stffq0_fcnp_ae_th(unsigned int ucsr_oq_sfifo_stffq0_fcnp_ae_th); +int iSetOQ_FIFO_AE_CFG1_csr_oq_sfifo_stffq1_fcnp_ae_th(unsigned int ucsr_oq_sfifo_stffq1_fcnp_ae_th); +int iSetOQ_FIFO_AE_CFG1_csr_oq_sfifo_stlfq_dsp_ae_th(unsigned int ucsr_oq_sfifo_stlfq_dsp_ae_th); +int iSetOQ_FIFO_AE_CFG1_csr_oq_sfifo_stffq0_dsp_ae_th(unsigned int ucsr_oq_sfifo_stffq0_dsp_ae_th); +int iSetOQ_FIFO_AE_CFG1_csr_oq_sfifo_stffq1_dsp_ae_th(unsigned int ucsr_oq_sfifo_stffq1_dsp_ae_th); +int iSetOQ_FIFO_AE_CFG1_csr_oq_sfifo_stliq_fp_ae_th(unsigned int ucsr_oq_sfifo_stliq_fp_ae_th); +int iSetOQ_FIFO_AE_CFG2_csr_oq_sfifo_stfiq_fp_ae_th(unsigned int ucsr_oq_sfifo_stfiq_fp_ae_th); +int iSetOQ_FIFO_AE_CFG2_csr_oq_sfifo_stlfq_rep_ae_th(unsigned int ucsr_oq_sfifo_stlfq_rep_ae_th); +int iSetOQ_HST01_COALESCING_WATERMARK_csr_oq_hst0_coalescing_watermark(unsigned int ucsr_oq_hst0_coalescing_watermark); +int iSetOQ_HST01_COALESCING_WATERMARK_csr_oq_hst1_coalescing_watermark(unsigned int ucsr_oq_hst1_coalescing_watermark); +int iSetOQ_HST23_COALESCING_WATERMARK_csr_oq_hst2_coalescing_watermark(unsigned int ucsr_oq_hst2_coalescing_watermark); +int iSetOQ_HST23_COALESCING_WATERMARK_csr_oq_hst3_coalescing_watermark(unsigned int ucsr_oq_hst3_coalescing_watermark); +int iSetOQ_HST0_COALESCING_WATCHDOG_EXP_csr_oq_hst0_coalescing_watchdog_exp( + unsigned int ucsr_oq_hst0_coalescing_watchdog_exp); +int iSetOQ_HST1_COALESCING_WATCHDOG_EXP_csr_oq_hst1_coalescing_watchdog_exp( + unsigned int ucsr_oq_hst1_coalescing_watchdog_exp); +int iSetOQ_HST2_COALESCING_WATCHDOG_EXP_csr_oq_hst2_coalescing_watchdog_exp( + unsigned int ucsr_oq_hst2_coalescing_watchdog_exp); +int iSetOQ_HST3_COALESCING_WATCHDOG_EXP_csr_oq_hst3_coalescing_watchdog_exp( + unsigned int ucsr_oq_hst3_coalescing_watchdog_exp); +int iSetOQ_AGING_HOST_CFG_csr_oq_host_aging_rstep_len(unsigned int ucsr_oq_host_aging_rstep_len); +int iSetOQ_AGING_HOST_CFG_csr_oq_host_aging_en(unsigned int ucsr_oq_host_aging_en); +int iSetOQ_AGING_NET_CFG_csr_oq_net_aging_rstep_len(unsigned int ucsr_oq_net_aging_rstep_len); +int iSetOQ_AGING_NET_CFG_csr_oq_net_aging_en(unsigned int ucsr_oq_net_aging_en); +int iSetOQ_WRR_WEIGHT_CFG_csr_oq_wrr_stf_fq0_weight(unsigned int ucsr_oq_wrr_stf_fq0_weight); +int iSetOQ_WRR_WEIGHT_CFG_csr_oq_wrr_stf_fq1_weight(unsigned int ucsr_oq_wrr_stf_fq1_weight); +int iSetOQ_WRR_WEIGHT_CFG_csr_oq_wrr_stl_fq_weight(unsigned int ucsr_oq_wrr_stl_fq_weight); +int iSetOQ_WRR_WEIGHT_CFG_csr_oq_wrr_stf_iq_weight(unsigned int ucsr_oq_wrr_stf_iq_weight); +int iSetOQ_WRR_WEIGHT_CFG_csr_oq_wrr_stl_iq_weight(unsigned int ucsr_oq_wrr_stl_iq_weight); +int iSetOQ_NREAL_DEQ_DPL_LEN_csr_oq_nreal_deq_dpl_len(unsigned int ucsr_oq_nreal_deq_dpl_len); +int iSetOQ_LATENCY_CFG_csr_oq_sample_mode(unsigned int ucsr_oq_sample_mode); +int iSetOQ_LATENCY_CFG_csr_oq_spec_port_en(unsigned int ucsr_oq_spec_port_en); +int iSetOQ_LATENCY_CFG_csr_oq_done_clr(unsigned int ucsr_oq_done_clr); +int iSetOQ_LATENCY_CFG_csr_oq_spec_port_num(unsigned int ucsr_oq_spec_port_num); +int iSetOQ_LATENCY_CFG_csr_oq_spec_pptr_typ(unsigned int ucsr_oq_spec_pptr_typ); +int iSetOQ_LATENCY_STA_oq_csr_sample_done(unsigned int uoq_csr_sample_done); +int iSetOQ_SAMPLE_TMR_oq_csr_sample_tmr(unsigned int uoq_csr_sample_tmr); +int iSetOQ_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetOQ_INT_VECTOR_enable(unsigned int uenable); +int iSetOQ_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetOQ_INT_int_data(unsigned int uint_data); +int iSetOQ_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetOQ_INT_EN_int_en(unsigned int uint_en); +int iSetOQ_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetOQ_INT0_STICKY_oq_1bit_ecc_err(unsigned int uoq_1bit_ecc_err); +int iSetOQ_INT0_STICKY_int_insrt0(unsigned int uint_insrt0); +int iSetOQ_INT0_STICKY_oq_int0_sticky(unsigned int uoq_int0_sticky); +int iSetOQ_INT1_STICKY_oq_2bit_ecc_err(unsigned int uoq_2bit_ecc_err); +int iSetOQ_INT1_STICKY_int_insrt1(unsigned int uint_insrt1); +int iSetOQ_INT1_STICKY_oq_int1_sticky(unsigned int uoq_int1_sticky); +int iSetOQ_INT2_STICKY_oq_fifo_overflow(unsigned int uoq_fifo_overflow); +int iSetOQ_INT2_STICKY_int_insrt2(unsigned int uint_insrt2); +int iSetOQ_INT2_STICKY_oq_int2_sticky(unsigned int uoq_int2_sticky); +int iSetOQ_INT3_STICKY_oq_fifo_underflow(unsigned int uoq_fifo_underflow); +int iSetOQ_INT3_STICKY_int_insrt3(unsigned int uint_insrt3); +int iSetOQ_INT3_STICKY_oq_int3_sticky(unsigned int uoq_int3_sticky); +int iSetOQ_INT4_STICKY_oq_host_age_happen(unsigned int uoq_host_age_happen); +int iSetOQ_INT4_STICKY_int_insrt4(unsigned int uint_insrt4); +int iSetOQ_INT4_STICKY_oq_int4_sticky(unsigned int uoq_int4_sticky); +int iSetOQ_INT5_STICKY_oq_network_age_happen(unsigned int uoq_network_age_happen); +int iSetOQ_INT5_STICKY_int_insrt5(unsigned int uint_insrt5); +int iSetOQ_INT5_STICKY_oq_int5_sticky(unsigned int uoq_int5_sticky); +int iSetOQ_INT6_STICKY_oq_empty_queue_deq_int(unsigned int uoq_empty_queue_deq_int); +int iSetOQ_INT6_STICKY_int_insrt6(unsigned int uint_insrt6); +int iSetOQ_INT6_STICKY_oq_int6_sticky(unsigned int uoq_int6_sticky); +int iSetOQ_INDRECT_CTRL_csr_oq_indrect_ctrl(unsigned int ucsr_oq_indrect_ctrl); +int iSetOQ_INDRECT_TIMEOUT_csr_oq_indrect_timeout(unsigned int ucsr_oq_indrect_timeout); +int iSetOQ_INDRECT_DAT0_csr_oq_indrect_data0(unsigned int ucsr_oq_indrect_data0); +int iSetOQ_INDRECT_DAT1_csr_oq_indrect_data1(unsigned int ucsr_oq_indrect_data1); +int iSetOQ_INDRECT_DAT2_csr_oq_indrect_data2(unsigned int ucsr_oq_indrect_data2); +int iSetOQ_INDRECT_DAT3_csr_oq_indrect_data3(unsigned int ucsr_oq_indrect_data3); +int iSetOQ_FIFO_FILL0_stliq_fp_fifo_fill(unsigned int ustliq_fp_fifo_fill); +int iSetOQ_FIFO_FILL0_stfiq_fp_fifo_fill(unsigned int ustfiq_fp_fifo_fill); +int iSetOQ_FIFO_FILL0_stffq0_dsp_fifo_fill(unsigned int ustffq0_dsp_fifo_fill); +int iSetOQ_FIFO_FILL0_stffq1_dsp_fifo_fill(unsigned int ustffq1_dsp_fifo_fill); +int iSetOQ_FIFO_FILL0_stlfq_dsp_fifo_fill(unsigned int ustlfq_dsp_fifo_fill); +int iSetOQ_FIFO_FILL1_stlfq_fcnp_fifo_fill(unsigned int ustlfq_fcnp_fifo_fill); +int iSetOQ_FIFO_FILL1_mdp_fifo_fill(unsigned int umdp_fifo_fill); +int iSetOQ_FIFO_FILL1_nrq_fifo_fill(unsigned int unrq_fifo_fill); +int iSetOQ_FIFO_FILL1_hrq_fifo_fill(unsigned int uhrq_fifo_fill); +int iSetOQ_FIFO_FILL1_stlfq_rep_fifo_fill(unsigned int ustlfq_rep_fifo_fill); +int iSetOQ_FIFO_FILL2_stffq0_fcnp_fifo_fill(unsigned int ustffq0_fcnp_fifo_fill); +int iSetOQ_FIFO_FILL2_stffq1_fcnp_fifo_fill(unsigned int ustffq1_fcnp_fifo_fill); +int iSetOQ_MEM_INIT_DONE_mem_init_done(unsigned int umem_init_done); +int iSetOQ_CSR_STLFQ_DSP_PACKET_CNT_oq_csr_stlfq_dsp_packet_cnt(unsigned int uoq_csr_stlfq_dsp_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_PACKET_CNT_oq_csr_stffq0_dsp_packet_cnt(unsigned int uoq_csr_stffq0_dsp_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_PACKET_CNT_oq_csr_stffq1_dsp_packet_cnt(unsigned int uoq_csr_stffq1_dsp_packet_cnt); +int iSetOQ_CSR_STLIQ_FP_PACKET_CNT_oq_csr_stliq_fp_packet_cnt(unsigned int uoq_csr_stliq_fp_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_PACKET_CNT_oq_csr_stfiq_fp_packet_cnt(unsigned int uoq_csr_stfiq_fp_packet_cnt); +int iSetOQ_CSR_STFFQ0_BI_DSP_PACKET_CNT_oq_csr_stffq0_bi_dsp_packet_cnt(unsigned int uoq_csr_stffq0_bi_dsp_packet_cnt); +int iSetOQ_CSR_STFFQ1_BI_DSP_PACKET_CNT_oq_csr_stffq1_bi_dsp_packet_cnt(unsigned int uoq_csr_stffq1_bi_dsp_packet_cnt); +int iSetOQ_CSR_STLFQ_REP_INFO_CNT_oq_csr_stlfq_rep_info_cnt(unsigned int uoq_csr_stlfq_rep_info_cnt); +int iSetOQ_CSR_STLFQ_DSP_TSO12_PACKET_CNT_oq_csr_stlfq_dsp_tso12_packet_cnt( + unsigned int uoq_csr_stlfq_dsp_tso12_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_TSO12_PACKET_CNT_oq_csr_stffq0_dsp_tso12_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_tso12_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_TSO12_PACKET_CNT_oq_csr_stffq1_dsp_tso12_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_tso12_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_TSO12_PACKET_CNT_oq_csr_stfiq_fp_tso12_packet_cnt( + unsigned int uoq_csr_stfiq_fp_tso12_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_LRO12_NETWORK_PACKET_CNT_oq_csr_stlfq_dsp_lro12_network_packet_cnt( + unsigned int uoq_csr_stlfq_dsp_lro12_network_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_LRO12_NETWORK_PACKET_CNT_oq_csr_stffq0_dsp_lro12_network_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_lro12_network_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_LRO12_NETWORK_PACKET_CNT_oq_csr_stffq1_dsp_lro12_network_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_lro12_network_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_LRO12_NETWORK_PACKET_CNT_oq_csr_stfiq_fp_lro12_network_packet_cnt( + unsigned int uoq_csr_stfiq_fp_lro12_network_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_LRO12_HOST_PACKET_CNT_oq_csr_stlfq_dsp_lro12_host_packet_cnt( + unsigned int uoq_csr_stlfq_dsp_lro12_host_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_LRO12_HOST_PACKET_CNT_oq_csr_stffq0_dsp_lro12_host_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_lro12_host_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_LRO12_HOST_PACKET_CNT_oq_csr_stffq1_dsp_lro12_host_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_lro12_host_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_LRO12_HOST_PACKET_CNT_oq_csr_stfiq_fp_lro12_host_packet_cnt( + unsigned int uoq_csr_stfiq_fp_lro12_host_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_TSO3_PACKET_CNT_oq_csr_stlfq_dsp_tso3_packet_cnt( + unsigned int uoq_csr_stlfq_dsp_tso3_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_TSO3_PACKET_CNT_oq_csr_stffq0_dsp_tso3_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_tso3_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_TSO3_PACKET_CNT_oq_csr_stffq1_dsp_tso3_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_tso3_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_TSO3_PACKET_CNT_oq_csr_stfiq_fp_tso3_packet_cnt(unsigned int uoq_csr_stfiq_fp_tso3_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_LRO3_PACKET_CNT_oq_csr_stlfq_dsp_lro3_packet_cnt( + unsigned int uoq_csr_stlfq_dsp_lro3_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_LRO3_PACKET_CNT_oq_csr_stffq0_dsp_lro3_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_lro3_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_LRO3_PACKET_CNT_oq_csr_stffq1_dsp_lro3_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_lro3_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_LRO3_PACKET_CNT_oq_csr_stfiq_fp_lro3_packet_cnt(unsigned int uoq_csr_stfiq_fp_lro3_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_REP_PACKET_CNT_oq_csr_stlfq_dsp_rep_packet_cnt(unsigned int uoq_csr_stlfq_dsp_rep_packet_cnt); +int iSetOQ_CSR_STFFQ0_DSP_REP_PACKET_CNT_oq_csr_stffq0_dsp_rep_packet_cnt( + unsigned int uoq_csr_stffq0_dsp_rep_packet_cnt); +int iSetOQ_CSR_STFFQ1_DSP_REP_PACKET_CNT_oq_csr_stffq1_dsp_rep_packet_cnt( + unsigned int uoq_csr_stffq1_dsp_rep_packet_cnt); +int iSetOQ_CSR_STLFQ_DSP_LREP_CNT_oq_csr_stlfq_dsp_lrep_cnt(unsigned int uoq_csr_stlfq_dsp_lrep_cnt); +int iSetOQ_CSR_STFFQ0_DSP_LREP_CNT_oq_csr_stffq0_dsp_lrep_cnt(unsigned int uoq_csr_stffq0_dsp_lrep_cnt); +int iSetOQ_CSR_STFFQ1_DSP_LREP_CNT_oq_csr_stffq1_dsp_lrep_cnt(unsigned int uoq_csr_stffq1_dsp_lrep_cnt); +int iSetOQ_CSR_OREP_REP_CNT_ADD_INC_oq_csr_orep_rep_cnt(unsigned int uoq_csr_orep_rep_cnt); +int iSetOQ_CSR_OREP_LREP_INC_oq_csr_orep_lrep_cnt(unsigned int uoq_csr_orep_lrep_cnt); +int iSetOQ_CSR_STLFQ_DROP_PACKET_CNT_oq_csr_stlfq_drop_packet_cnt(unsigned int uoq_csr_stlfq_drop_packet_cnt); +int iSetOQ_CSR_STFFQ0_DROP_PACKET_CNT_oq_csr_stffq0_drop_packet_cnt(unsigned int uoq_csr_stffq0_drop_packet_cnt); +int iSetOQ_CSR_STFFQ1_DROP_PACKET_CNT_oq_csr_stffq1_drop_packet_cnt(unsigned int uoq_csr_stffq1_drop_packet_cnt); +int iSetOQ_CSR_STLIQ_FP_DROP_PACKET_CNT_oq_csr_stliq_fp_drop_packet_cnt(unsigned int uoq_csr_stliq_fp_drop_packet_cnt); +int iSetOQ_CSR_STFIQ_FP_DROP_PACKET_CNT_oq_csr_stfiq_fp_drop_packet_cnt(unsigned int uoq_csr_stfiq_fp_drop_packet_cnt); +int iSetOQ_CSR_MDP_PACKET_CNT_oq_csr_mdp_packet_cnt(unsigned int uoq_csr_mdp_packet_cnt); +int iSetOQ_CSR_HRQ_PACKET_CNT_oq_csr_hrq_packet_cnt(unsigned int uoq_csr_hrq_packet_cnt); +int iSetOQ_CSR_HRQ_DROP_PACKET_CNT_oq_csr_hrq_drop_packet_cnt(unsigned int uoq_csr_hrq_drop_packet_cnt); +int iSetOQ_CSR_NRQ_PACKET_CNT_oq_csr_nrq_packet_cnt(unsigned int uoq_csr_nrq_packet_cnt); +int iSetOQ_CSR_RQC_CNT_oq_csr_rqc_cnt(unsigned int uoq_csr_rqc_cnt); +int iSetOQ_CSR_RQC_RVLD_CNT_oq_csr_rqc_rvld_cnt(unsigned int uoq_csr_rqc_rvld_cnt); +int iSetOQ_CSR_HOST_PTHRU_CNT_oq_csr_host_pthru_cnt(unsigned int uoq_csr_host_pthru_cnt); +int iSetOQ_CSR_NETWORK_PTHRU_CNT_oq_csr_network_pthru_cnt(unsigned int uoq_csr_network_pthru_cnt); +int iSetOQ_CSR_NETWORK_CHECK_DROP_PACKET_CNT_oq_csr_network_check_drop_packet_cnt( + unsigned int uoq_csr_network_check_drop_packet_cnt); +int iSetOQ_CSR_NETWORK_DISSENQ_DROP_PACKET_oq_csr_network_dissenq_drop_packet( + unsigned int uoq_csr_network_dissenq_drop_packet); +int iSetOQ_CSR_PIE_CHECK_DROP_PACKET_CNT_oq_csr_pie_check_drop_packet_cnt( + unsigned int uoq_csr_pie_check_drop_packet_cnt); +int iSetOQ_CSR_HOST_DISSENQ_DROP_PACKET_CNT_oq_csr_host_dissenq_drop_packet_cnt( + unsigned int uoq_csr_host_dissenq_drop_packet_cnt); +int iSetOQ_CSR_EQS_CNT_oq_csr_eqs_cnt(unsigned int uoq_csr_eqs_cnt); +int iSetOQ_CSR_DQR_CNT_oq_csr_dqr_cnt(unsigned int uoq_csr_dqr_cnt); +int iSetOQ_CSR_NOT_REAL_DEQ_oq_csr_not_real_deq(unsigned int uoq_csr_not_real_deq); +int iSetOQ_CSR_DEQ_EMPTY_QUEUE_oq_csr_deq_empty_queue(unsigned int uoq_csr_deq_empty_queue); +int iSetOQ_CSR_DEQ_BP_BY_PRM_ICD_oq_csr_deq_bp_by_prm_icd(unsigned int uoq_csr_deq_bp_by_prm_icd); +int iSetOQ_CSR_DEQ_BP_BY_PRM_DCD_oq_csr_deq_bp_by_prm_dcd(unsigned int uoq_csr_deq_bp_by_prm_dcd); +int iSetOQ_CSR_DEQ_BP_BY_STFIQ_LB_oq_csr_deq_bp_by_stfiq_lb(unsigned int uoq_csr_deq_bp_by_stfiq_lb); +int iSetOQ_CSR_STFIQ_OQ_FCNP_BP_CNT_oq_csr_stfiq_oq_fcnp_bp_cnt(unsigned int uoq_csr_stfiq_oq_fcnp_bp_cnt); +int iSetOQ_CSR_CPBTX_BP_CNT_oq_csr_cpbtx_bp_cnt(unsigned int uoq_csr_cpbtx_bp_cnt); +int iSetOQ_CSR_CPBRX_BP_CNT_oq_csr_cpbrx_bp_cnt(unsigned int uoq_csr_cpbrx_bp_cnt); +int iSetOQ_CSR_DQS_CNT_oq_csr_dqs_cnt(unsigned int uoq_csr_dqs_cnt); +int iSetOQ_CSR_ENQ_PACKET_CNT_oq_csr_enq_packet_cnt(unsigned int uoq_csr_enq_packet_cnt); +int iSetOQ_CSR_ENQ_HOST_2K_QUEUE_PACKET_CNT_oq_csr_enq_host_2k_queue_packet_cnt( + unsigned int uoq_csr_enq_host_2k_queue_packet_cnt); +int iSetOQ_CSR_ENQ_HOST_PIE_QUEUE_PACKET_CNT_oq_csr_enq_host_pie_queue_packet_cnt( + unsigned int uoq_csr_enq_host_pie_queue_packet_cnt); +int iSetOQ_CSR_ENQ_HOST_DDR_QUEUE_PACKET_CNT_oq_csr_enq_host_ddr_queue_packet_cnt( + unsigned int uoq_csr_enq_host_ddr_queue_packet_cnt); +int iSetOQ_CSR_ENQ_HOST_LOOPBACK_QUEUE_PACKET_CNT_oq_csr_enq_host_loopback_queue_packet_cnt( + unsigned int uoq_csr_enq_host_loopback_queue_packet_cnt); +int iSetOQ_CSR_ENQ_NETWORK_4K_QUEUE_PACKET_CNT_oq_csr_enq_network_4k_queue_packet_cnt( + unsigned int uoq_csr_enq_network_4k_queue_packet_cnt); +int iSetOQ_CSR_ENQ_NETWORK_LOOPBACK_QUEUE_PACKET_CNT_oq_csr_enq_network_loopback_queue_packet_cnt( + unsigned int uoq_csr_enq_network_loopback_queue_packet_cnt); +int iSetOQ_CSR_ENQ_DROP_QUEUE_PACKET_CNT_oq_csr_enq_drop_queue_packet_cnt( + unsigned int uoq_csr_enq_drop_queue_packet_cnt); +int iSetOQ_CSR_TPD_TO_CITF_CNT_oq_csr_tpd_to_citf_cnt(unsigned int uoq_csr_tpd_to_citf_cnt); +int iSetOQ_CSR_TID_CNT_oq_csr_tid_cnt(unsigned int uoq_csr_tid_cnt); +int iSetOQ_CSR_STP_CNT_oq_csr_stp_cnt(unsigned int uoq_csr_stp_cnt); +int iSetOQ_CSR_STFFQ0_FCNP_oq_csr_stffq0_fcnp(unsigned int uoq_csr_stffq0_fcnp); +int iSetOQ_CSR_STFFQ1_FCNP_oq_csr_stffq1_fcnp(unsigned int uoq_csr_stffq1_fcnp); +int iSetOQ_CSR_STLFQ_FCNP_oq_csr_stlfq_fcnp(unsigned int uoq_csr_stlfq_fcnp); +int iSetOQ_CSR_OQ_ESCH_FCNP_oq_csr_oq_esch_fcnp(unsigned int uoq_csr_oq_esch_fcnp); +int iSetOQ_CSR_OQ_STFIQ_FCNP_oq_csr_oq_stfiq_fcnp(unsigned int uoq_csr_oq_stfiq_fcnp); +int iSetOQ_CSR_EPD_TO_CPB_CNT_oq_csr_epd_to_cpb_cnt(unsigned int uoq_csr_epd_to_cpb_cnt); +int iSetOQ_CSR_EPD_TSO12_TO_NETWORK_CPB_CNT_oq_csr_epd_tso12_to_network_cpb_cnt( + unsigned int uoq_csr_epd_tso12_to_network_cpb_cnt); +int iSetOQ_CSR_EPD_LRO12_TO_NETWORK_CPB_CNT_oq_csr_epd_lro12_to_network_cpb_cnt( + unsigned int uoq_csr_epd_lro12_to_network_cpb_cnt); +int iSetOQ_CSR_EPD_LRO12_TO_HOST_CPB_CNT_oq_csr_epd_lro12_to_host_cpb_cnt( + unsigned int uoq_csr_epd_lro12_to_host_cpb_cnt); +int iSetOQ_CSR_EPD_TSO3_TO_CPB_CNT_oq_csr_epd_tso3_to_cpb_cnt(unsigned int uoq_csr_epd_tso3_to_cpb_cnt); +int iSetOQ_CSR_EPD_LRO3_TO_CPB_CNT_oq_csr_epd_lro3_to_cpb_cnt(unsigned int uoq_csr_epd_lro3_to_cpb_cnt); +int iSetOQ_CSR_EPD_TSO12_PIECE_CNT_oq_csr_epd_tso12_piece_cnt(unsigned int uoq_csr_epd_tso12_piece_cnt); +int iSetOQ_CSR_EPD_LRO12_PIECE_CNT_oq_csr_epd_lro12_piece_cnt(unsigned int uoq_csr_epd_lro12_piece_cnt); +int iSetOQ_CSR_EPD_DMARCND_TO_CPB_CNT_oq_csr_epd_dmarcnd_to_cpb_cnt(unsigned int uoq_csr_epd_dmarcnd_to_cpb_cnt); +int iSetOQ_CSR_EPD_REP_TO_CPB_CNT_oq_csr_epd_rep_to_cpb_cnt(unsigned int uoq_csr_epd_rep_to_cpb_cnt); +int iSetOQ_CSR_DROP_TO_CPB_CNT_oq_csr_drop_to_cpb_cnt(unsigned int uoq_csr_drop_to_cpb_cnt); +int iSetOQ_CSR_DPL_CNT_oq_csr_dpl_cnt(unsigned int uoq_csr_dpl_cnt); +int iSetOQ_CSR_OLB_TO_IQ_CNT_oq_csr_olb_to_iq_cnt(unsigned int uoq_csr_olb_to_iq_cnt); +int iSetOQ_CSR_DISABLE_EPD_TO_CPB_CNT_oq_csr_disable_epd_to_cpb_cnt(unsigned int uoq_csr_disable_epd_to_cpb_cnt); +int iSetOQ_CSR_PRLS_CNT_oq_csr_prls_cnt(unsigned int uoq_csr_prls_cnt); +int iSetOQ_CSR_ICD_CNT_oq_csr_icd_cnt(unsigned int uoq_csr_icd_cnt); +int iSetOQ_CSR_DCD_CNT_oq_csr_dcd_cnt(unsigned int uoq_csr_dcd_cnt); +int iSetOQ_CSR_PTHRU_CNT_oq_csr_pthru_cnt(unsigned int uoq_csr_pthru_cnt); +int iSetOQ_MEM_ECC_1BIT_CNT_oq_csr_mem_1bit_ecc(unsigned int uoq_csr_mem_1bit_ecc); +int iSetOQ_CSR_DROP_QUEUE_DEPTH_oq_csr_drop_queue_depth(unsigned int uoq_csr_drop_queue_depth); +int iSetOQ_BP_STATUS_prm_oq_orep_bp(unsigned int uprm_oq_orep_bp); +int iSetOQ_BP_STATUS_esch_qu_epd_bp_dps(unsigned int uesch_qu_epd_bp_dps); +int iSetOQ_BP_STATUS_cpb_oq_tx_bp(unsigned int ucpb_oq_tx_bp); +int iSetOQ_BP_STATUS_cpb_oq_rx_bp(unsigned int ucpb_oq_rx_bp); +int iSetOQ_BP_STATUS_iq_oq_olb_bp(unsigned int uiq_oq_olb_bp); +int iSetOQ_BP_STATUS_stfiq_oq_fcnp_bp(unsigned int ustfiq_oq_fcnp_bp); +int iSetOQ_BP_STATUS_cpb_qu_drp_bp(unsigned int ucpb_qu_drp_bp); +int iSetOQ_BP_STATUS_prm_oq_prls_bp(unsigned int uprm_oq_prls_bp); +int iSetOQ_BP_STATUS_prm_oq_icd_q_fc_mux(unsigned int uprm_oq_icd_q_fc_mux); +int iSetOQ_BP_STATUS_prm_oq_icd_afull(unsigned int uprm_oq_icd_afull); +int iSetOQ_BP_STATUS_prm_oq_dcd_afull(unsigned int uprm_oq_dcd_afull); + + +#endif // OQ_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_reg_offset.h new file mode 100644 index 000000000..b76cbd6a6 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/oq_reg_offset.h @@ -0,0 +1,261 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : oq_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2013/3/10 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/01/20 15:07:14 Create file +// ****************************************************************************** + +#ifndef OQ_REG_OFFSET_H +#define OQ_REG_OFFSET_H + +/* QU_OQ_CSR Base address of Module's Register */ +#define CSR_QU_OQ_CSR_BASE (0x8000) + +/* **************************************************************************** */ +/* QU_OQ_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_OQ_CSR_QU_VERSIONS_REG (CSR_QU_OQ_CSR_BASE + 0x0) /* 版本寄存器 */ +#define CSR_QU_OQ_CSR_OQ_MODE_REG (CSR_QU_OQ_CSR_BASE + 0x4) /* OQ operation mode register */ +#define CSR_QU_OQ_CSR_OQ_MODE1_REG (CSR_QU_OQ_CSR_BASE + 0x8) /* OQ operation mode register */ +#define CSR_QU_OQ_CSR_OQ_DESENQ_CFG_REG (CSR_QU_OQ_CSR_BASE + 0xC) /* disable队列配置 */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x10) /* pass-through配置 */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_WIN_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x14) /* pass-through带宽限制窗口配置 */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG0_REG \ + (CSR_QU_OQ_CSR_BASE + 0x18) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG1_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1C) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG2_REG \ + (CSR_QU_OQ_CSR_BASE + 0x20) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG3_REG \ + (CSR_QU_OQ_CSR_BASE + 0x24) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG4_REG \ + (CSR_QU_OQ_CSR_BASE + 0x28) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG5_REG \ + (CSR_QU_OQ_CSR_BASE + 0x2C) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_PTHRU_BD_CTR_MAX_PTHU_CFG6_REG \ + (CSR_QU_OQ_CSR_BASE + 0x30) /* max pthu-paket in window config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AF_CFG0_REG (CSR_QU_OQ_CSR_BASE + 0x34) /* oq fifo almost-full waterline config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AF_CFG1_REG (CSR_QU_OQ_CSR_BASE + 0x38) /* oq fifo almost-full waterline config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AF_CFG2_REG (CSR_QU_OQ_CSR_BASE + 0x3C) /* oq fifo almost-full waterline config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AE_CFG0_REG (CSR_QU_OQ_CSR_BASE + 0x40) /* oq fifo almost-empty waterline config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AE_CFG1_REG (CSR_QU_OQ_CSR_BASE + 0x44) /* oq fifo almost-empty waterline config */ +#define CSR_QU_OQ_CSR_OQ_FIFO_AE_CFG2_REG (CSR_QU_OQ_CSR_BASE + 0x48) /* oq fifo almost-empty waterline config */ +#define CSR_QU_OQ_CSR_OQ_HST01_COALESCING_WATERMARK_REG (CSR_QU_OQ_CSR_BASE + 0x4C) /* OQ_HST01_COALESCING_WATERMARK \ + */ +#define CSR_QU_OQ_CSR_OQ_HST23_COALESCING_WATERMARK_REG (CSR_QU_OQ_CSR_BASE + 0x50) /* OQ_HST23_COALESCING_WATERMARK \ + */ +#define CSR_QU_OQ_CSR_OQ_HST0_COALESCING_WATCHDOG_EXP_REG \ + (CSR_QU_OQ_CSR_BASE + 0x54) /* OQ_HST0_COALESCING_WATCHDOG_EXP */ +#define CSR_QU_OQ_CSR_OQ_HST1_COALESCING_WATCHDOG_EXP_REG \ + (CSR_QU_OQ_CSR_BASE + 0x58) /* OQ_HST1_COALESCING_WATCHDOG_EXP */ +#define CSR_QU_OQ_CSR_OQ_HST2_COALESCING_WATCHDOG_EXP_REG \ + (CSR_QU_OQ_CSR_BASE + 0x5C) /* OQ_HST2_COALESCING_WATCHDOG_EXP */ +#define CSR_QU_OQ_CSR_OQ_HST3_COALESCING_WATCHDOG_EXP_REG \ + (CSR_QU_OQ_CSR_BASE + 0x60) /* OQ_HST3_COALESCING_WATCHDOG_EXP */ +#define CSR_QU_OQ_CSR_OQ_AGING_HOST_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x64) /* OQ_AGING_HOST_CFG */ +#define CSR_QU_OQ_CSR_OQ_AGING_NET_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x68) /* 网络侧队列老化配置 */ +#define CSR_QU_OQ_CSR_OQ_WRR_WEIGHT_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x6C) /* OQ入口的WRR权重配置 */ +#define CSR_QU_OQ_CSR_OQ_NREAL_DEQ_DPL_LEN_REG \ + (CSR_QU_OQ_CSR_BASE + 0x70) /* OQ出队DPL=0时，配置plen给ESCH，用于调度权重刷新。 */ +#define CSR_QU_OQ_CSR_OQ_LATENCY_CFG_REG (CSR_QU_OQ_CSR_BASE + 0x74) /* oq的时延采样DFX配置 */ +#define CSR_QU_OQ_CSR_OQ_LATENCY_STA_REG (CSR_QU_OQ_CSR_BASE + 0x78) /* oq的时延采样DFX状态 */ +#define CSR_QU_OQ_CSR_OQ_SAMPLE_TMR_REG (CSR_QU_OQ_CSR_BASE + 0x7C) /* oq的时延采样DFX时间 */ +#define CSR_QU_OQ_CSR_OQ_INT_VECTOR_REG (CSR_QU_OQ_CSR_BASE + 0x84) /* 中断向量 */ +#define CSR_QU_OQ_CSR_OQ_INT_REG (CSR_QU_OQ_CSR_BASE + 0x88) /* 中断状态 */ +#define CSR_QU_OQ_CSR_OQ_INT_EN_REG (CSR_QU_OQ_CSR_BASE + 0x8C) /* 中断使能 */ +#define CSR_QU_OQ_CSR_OQ_INT0_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0x90) /* 中断0的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT1_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0x94) /* 中断1的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT2_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0x98) /* 中断2的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT3_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0x9C) /* 中断3的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT4_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0xA0) /* 中断4的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT5_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0xA4) /* 中断5的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INT6_STICKY_REG (CSR_QU_OQ_CSR_BASE + 0xA8) /* 中断6的sticky信息 */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_CTRL_REG (CSR_QU_OQ_CSR_BASE + 0xAC) /* 间接寻址控制寄存器 */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_TIMEOUT_REG (CSR_QU_OQ_CSR_BASE + 0xB0) /* OQ间接寻址timeout水线配置 */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_DAT0_REG \ + (CSR_QU_OQ_CSR_BASE + 0xB4) /* OQ memory indirect access write data or read data. */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_DAT1_REG \ + (CSR_QU_OQ_CSR_BASE + 0xB8) /* OQ memory indirect access write data or read data. */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_DAT2_REG \ + (CSR_QU_OQ_CSR_BASE + 0xBC) /* OQ memory indirect access write data or read data. */ +#define CSR_QU_OQ_CSR_OQ_INDRECT_DAT3_REG \ + (CSR_QU_OQ_CSR_BASE + 0xC0) /* OQ memory indirect access write data or read data. */ +#define CSR_QU_OQ_CSR_OQ_FIFO_FILL0_REG (CSR_QU_OQ_CSR_BASE + 0xC4) /* FIFO内数据个数 */ +#define CSR_QU_OQ_CSR_OQ_FIFO_FILL1_REG (CSR_QU_OQ_CSR_BASE + 0xC8) /* FIFO内数据个数 */ +#define CSR_QU_OQ_CSR_OQ_FIFO_FILL2_REG (CSR_QU_OQ_CSR_BASE + 0xCC) /* FIFO内数据个数 */ +#define CSR_QU_OQ_CSR_OQ_MEM_INIT_DONE_REG (CSR_QU_OQ_CSR_BASE + 0xD0) /* 所有mem在init完成后拉高 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0xD4) /* 从stlfq进入OQ的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0xD8) /* 从stffq0进入OQ的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0xDC) /* 从stffq1进入OQ的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLIQ_FP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0xE0) /* 从stliq进入OQ的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0xE4) /* 从stfiq进入OQ的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_BI_DSP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xE8) /* 从stffq0进入OQ的bi_dsp报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_BI_DSP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xEC) /* 从stffq1进入OQ的bi_dsp报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_REP_INFO_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xF0) /* 从stlfq 通过复制报文进入OQ的指令个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_TSO12_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xF4) /* 从stlfq进入OQ的tso1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_TSO12_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xF8) /* 从stffq0进入OQ的tso1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_TSO12_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0xFC) /* 从stffq1进入OQ的tso1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_TSO12_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x100) /* 从stfiq进入OQ的tso1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_LRO12_NETWORK_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x104) /* 从stlfq进入OQ,到网络侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_LRO12_NETWORK_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x108) /* 从stffq0进入OQ,到网络侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_LRO12_NETWORK_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x10C) /* 从stffq1进入OQ,到网络侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_LRO12_NETWORK_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x110) /* 从stfiq进入OQ,到网络侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_LRO12_HOST_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x114) /* 从stlfq进入OQ,到主机侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_LRO12_HOST_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x118) /* 从stffq0进入OQ,到主机侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_LRO12_HOST_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x11C) /* 从stffq1进入OQ,到主机侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_LRO12_HOST_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x120) /* 从stfiq进入OQ,到主机侧队列的lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_TSO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x124) /* 从stlfq进入OQ的tso3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_TSO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x128) /* 从stffq0进入OQ的tso3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_TSO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x12C) /* 从stffq1进入OQ的tso3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_TSO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x130) /* 从stfiq进入OQ的tso3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_LRO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x134) /* 从stlfq进入OQ的lro3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_LRO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x138) /* 从stffq0进入OQ的lro3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_LRO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x13C) /* 从stffq1进入OQ的lro3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_LRO3_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x140) /* 从stfiq进入OQ的lro3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_REP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x144) /* 从stlfq进入OQ的复制报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_REP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x148) /* 从stffq0进入OQ的复制报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_REP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x14C) /* 从stffq1进入OQ的复制报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DSP_LREP_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x150) /* 从stlfq进入OQ的lrep指令个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DSP_LREP_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x154) /* 从stffq0进入OQ的lrep指令个数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DSP_LREP_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x158) /* 从stffq1进入OQ的lrep指令个数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_OREP_REP_CNT_ADD_INC_REG \ + (CSR_QU_OQ_CSR_BASE + 0x15C) /* oq通过orep接口向prm发送触发rep_cnt++的指令个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_OREP_LREP_INC_REG \ + (CSR_QU_OQ_CSR_BASE + 0x160) /* oq通过orep接口向prm发送的lrep指令个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x164) /* 从stlfq进入OQ的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x168) /* 从stffq0进入OQ的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x16C) /* 从stffq1进入OQ的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLIQ_FP_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x170) /* 从stliq进入OQ的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_FP_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x174) /* 从stfiq进入OQ的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_MDP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x178) /* oq通过mdp接口收到的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_HRQ_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x17C) /* oq通过hrq_fifo的主机侧报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_HRQ_DROP_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x180) /* oq通过hrq_fifo的丢弃报文个数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_NRQ_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x184) /* oq通过nrq_fifo的网络侧报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_RQC_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x188) /* oq通过RQC接口向ESCH请求查询的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_RQC_RVLD_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x18C) /* oq通过RQC接口收到ESCH查询结果的次数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_HOST_PTHRU_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x190) /* oq主机侧报文pass-through个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_NETWORK_PTHRU_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x194) /* oq网络侧报文pass-through个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_NETWORK_CHECK_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x198) /* oq网络侧通过drop-tail和wred丢弃的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_NETWORK_DISSENQ_DROP_PACKET_REG \ + (CSR_QU_OQ_CSR_BASE + 0x19C) /* oq网络侧由于disable队列丢弃的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_PIE_CHECK_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1A0) /* oq PIE接口由于drop-tail丢弃的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_HOST_DISSENQ_DROP_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1A4) /* oq主机侧由于disable队列丢弃的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EQS_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1A8) /* oq发起EQS次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DQR_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1AC) /* oq收到的DQR次数统计该次数=ESCH发起的调度次数 + OQ的drop报文个数； */ +#define CSR_QU_OQ_CSR_OQ_CSR_NOT_REAL_DEQ_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1B0) /* oq出队失败次数统计。oq假出队会影响调度带宽和调度shaper精度。 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DEQ_EMPTY_QUEUE_REG (CSR_QU_OQ_CSR_BASE + 0x1B4) /* ESCH对oq发起空调度的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DEQ_BP_BY_PRM_ICD_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1B8) /* 主机侧队列或者网络侧lb队列向PRM预扣被反压次数计数器。 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DEQ_BP_BY_PRM_DCD_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1BC) /* 主机侧队列换src时，向PRM释放资源被反压次数计数器。 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DEQ_BP_BY_STFIQ_LB_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1C0) /* 主机侧队列向STFIQ lb时，被STFIQ反压次数计数器。 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFIQ_OQ_FCNP_BP_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1C4) /* STFIQ对OQ的FCNP反压周期计数器，正常情况该计数器应当为0 */ +#define CSR_QU_OQ_CSR_OQ_CSR_CPBTX_BP_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1C8) /* CPB对OQ的TX方向反压周期计数器，正常情况该计数器应当为0 */ +#define CSR_QU_OQ_CSR_OQ_CSR_CPBRX_BP_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1CC) /* CPB对OQ的RX方向反压周期计数器，正常情况该计数器应当为0 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DQS_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1D0) /* oq发起DQS的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_PACKET_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1D4) /* oq发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_HOST_2K_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1D8) /* oq向主机侧2K个队列发起入队次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_HOST_PIE_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1DC) /* oq向PIE队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_HOST_DDR_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1E0) /* oq向DDR队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_HOST_LOOPBACK_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1E4) /* oq向主机侧loopback队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_NETWORK_4K_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1E8) /* oq向网络侧4K个队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_NETWORK_LOOPBACK_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1EC) /* oq向网络侧loopback队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_ENQ_DROP_QUEUE_PACKET_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x1F0) /* oq向丢弃队列发起入队的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_TPD_TO_CITF_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1F4) /* oqm向citf发送的pd次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_TID_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1F8) /* oqm发起tid操作的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STP_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x1FC) /* oqm发起stp操作的次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ0_FCNP_REG (CSR_QU_OQ_CSR_BASE + 0x200) /* stffq0发起fcnp操作次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STFFQ1_FCNP_REG (CSR_QU_OQ_CSR_BASE + 0x204) /* stffq1发起fcnp操作次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_STLFQ_FCNP_REG (CSR_QU_OQ_CSR_BASE + 0x208) /* stlfq发起fcnp操作次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_OQ_ESCH_FCNP_REG (CSR_QU_OQ_CSR_BASE + 0x20C) /* oq向ESCH发起fcnp指令次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_OQ_STFIQ_FCNP_REG \ + (CSR_QU_OQ_CSR_BASE + 0x210) /* oq向stfiq发起fcnp task-event队列入队的请求次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_TO_CPB_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x214) /* oq向cpb发送的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_TSO12_TO_NETWORK_CPB_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x218) /* oq向cpb发送的网络侧tso1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_LRO12_TO_NETWORK_CPB_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x21C) /* oq向cpb发送的网络侧lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_LRO12_TO_HOST_CPB_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x220) /* oq向cpb发送的主机侧lro1/2报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_TSO3_TO_CPB_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x224) /* oq向cpb发送的tso3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_LRO3_TO_CPB_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x228) /* oq向cpb发送的lro3报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_TSO12_PIECE_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x22C) /* oq向cpb发送的tso1/2分片个数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_LRO12_PIECE_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x230) /* oq向cpb发送的lro1/2分片个数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_DMARCND_TO_CPB_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x234) /* oq向cpb发送的dmarcmd报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_EPD_REP_TO_CPB_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x238) /* oq向cpb发送的复制报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DROP_TO_CPB_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x23C) /* oq向cpb发送的丢弃报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DPL_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x240) /* oq向ESCH发起的DPL次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_OLB_TO_IQ_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x244) /* oq向iq发送OLB的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DISABLE_EPD_TO_CPB_CNT_REG \ + (CSR_QU_OQ_CSR_BASE + 0x248) /* citf模块由于配置，没有发给cpb的报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_PRLS_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x24C) /* oq由于丢弃复制报文，向prm发起prls的次数统计 \ + */ +#define CSR_QU_OQ_CSR_OQ_CSR_ICD_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x250) /* oq向prm发起预扣次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DCD_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x254) /* oq向prm发起释放次数统计 */ +#define CSR_QU_OQ_CSR_OQ_CSR_PTHRU_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x258) /* citf模块收到的pass-through报文个数统计 */ +#define CSR_QU_OQ_CSR_OQ_MEM_ECC_1BIT_CNT_REG (CSR_QU_OQ_CSR_BASE + 0x25C) /* oq内部RAM发生1BIT ECC的次数 */ +#define CSR_QU_OQ_CSR_OQ_CSR_DROP_QUEUE_DEPTH_REG (CSR_QU_OQ_CSR_BASE + 0x260) /* DROP队列深度 */ +#define CSR_QU_OQ_CSR_OQ_BP_STATUS_REG (CSR_QU_OQ_CSR_BASE + 0x264) /* OQ受到的所有反压状态 */ + +#endif // OQ_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_c_union_define.h new file mode 100644 index 000000000..85da3628b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_c_union_define.h @@ -0,0 +1,1819 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : pe_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/12/05 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/08/10 14:30:28 Create file +// ****************************************************************************** + +#ifndef PE_C_UNION_DEFINE_H +#define PE_C_UNION_DEFINE_H + +/* Define the union csr_petx_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fpga_ver_u; + +/* Define the union csr_petx_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_emu_ver_u; + +/* Define the union csr_petx_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ini_cmd_ram_start : 1; /* [0] */ + u32 rsv_0 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_initctab_start_u; + +/* Define the union csr_petx_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ini_cmd_ram_done : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_initctab_done_u; + +/* Define the union csr_petx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 petx_int_enable : 1; /* [27] */ + u32 petx_int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_int_vector_u; + +/* Define the union csr_petx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_int_data : 5; /* [4:0] */ + u32 rsv_4 : 11; /* [15:5] */ + u32 petx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_int_u; + +/* Define the union csr_petx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_int_en : 5; /* [4:0] */ + u32 rsv_5 : 11; /* [15:5] */ + u32 petx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_int_en_u; + +/* Define the union csr_petx_cmd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_cmd_err : 1; /* [0] */ + u32 petx_cmd_inj_err : 1; /* [1] */ + u32 petx_cmd_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_cmd_err_u; + +/* Define the union csr_petx_ram_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_ucerr : 1; /* [0] */ + u32 petx_inj_ram_ucerr : 1; /* [1] */ + u32 petx_ram_ucerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_ucerr_u; + +/* Define the union csr_petx_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_cerr : 1; /* [0] */ + u32 petx_inj_ram_cerr : 1; /* [1] */ + u32 petx_ram_cerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_cerr_u; + +/* Define the union csr_petx_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_crdt_err : 1; /* [0] */ + u32 petx_crdt_inj_err : 1; /* [1] */ + u32 petx_crdt_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_crdt_err_u; + +/* Define the union csr_petx_fifo_ovf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_fifo_ovf_err : 1; /* [0] */ + u32 petx_fifo_ovf_inj_err : 1; /* [1] */ + u32 petx_fifo_ovf_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fifo_ovf_err_u; + +/* Define the union csr_petx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_indrect_addr : 24; /* [23:0] */ + u32 petx_indrect_tab : 4; /* [27:24] */ + u32 petx_indrect_state : 2; /* [29:28] */ + u32 petx_indrect_mode : 1; /* [30] */ + u32 petx_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_indrect_ctrl_u; + +/* Define the union csr_petx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_indrect_timeout_u; + +/* Define the union csr_petx_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_indrect_data_u; + +/* Define the union csr_petx_ucerr_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_cmd_ucerr_ctrl : 1; /* [0] */ + u32 petx_crdt_ucerr_ctrl : 1; /* [1] */ + u32 petx_cpsfo_ovf_ctrl : 1; /* [2] */ + u32 petx_hefo_ovf_ctrl : 1; /* [3] */ + u32 petx_gbfo_ovf_ctrl : 1; /* [4] */ + u32 rsv_6 : 3; /* [7:5] */ + u32 petx_cdf_ram_ucerr_ctrl : 1; /* [8] */ + u32 petx_cpsfo_ram_ucerr_ctrl : 1; /* [9] */ + u32 petx_gsope_ram_ucerr_ctrl : 1; /* [10] */ + u32 petx_he_ram_ucerr_ctrl : 1; /* [11] */ + u32 petx_cht_ram_ucerr_ctrl : 1; /* [12] */ + u32 petx_gbfo_ram_ucerr_ctrl : 1; /* [13] */ + u32 rsv_7 : 17; /* [30:14] */ + u32 petx_ucerr_ctrl : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ucerr_ctrl_u; + +/* Define the union csr_petx_ram_err_chk_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_err_chk_bypass : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_err_chk_bypass_u; + +/* Define the union csr_petx_inj_ram_err_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_inj_cdf_ram_cerr : 1; /* [0] */ + u32 petx_inj_cdf_ram_ucerr : 1; /* [1] */ + u32 petx_inj_cpsfo_ram_cerr : 1; /* [2] */ + u32 petx_inj_cpsfo_ram_ucerr : 1; /* [3] */ + u32 petx_inj_gsope_ram_cerr : 1; /* [4] */ + u32 petx_inj_gsope_ram_ucerr : 1; /* [5] */ + u32 petx_inj_he_ram_cerr : 1; /* [6] */ + u32 petx_inj_he_ram_ucerr : 1; /* [7] */ + u32 petx_inj_cht_ram_cerr : 1; /* [8] */ + u32 petx_inj_cht_ram_ucerr : 1; /* [9] */ + u32 petx_inj_gbfo_ram_cerr : 1; /* [10] */ + u32 petx_inj_gbfo_ram_ucerr : 1; /* [11] */ + u32 rsv_8 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_inj_ram_err_cfg_u; + +/* Define the union csr_petx_en_hcmd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_en_hcmd_num : 4; /* [3:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_en_hcmd_num_u; + +/* Define the union csr_petx_chnl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_chnl_hcmd_en : 1; /* [0] */ + u32 rsv_9 : 22; /* [22:1] */ + u32 petx_chnl_idle_th : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_chnl_cfg_u; + +/* Define the union csr_petx_pre_alc_pkt_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_pre_alc_pkt_crdt : 4; /* [3:0] */ + u32 petx_ertn_pkt_crdt_th : 4; /* [7:4] */ + u32 rsvd : 24; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_pre_alc_pkt_crdt_u; + +/* Define the union csr_petx_ecrc_ini0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ecrc_ini0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ecrc_ini0_u; + +/* Define the union csr_petx_ecrc_ini1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ecrc_ini1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ecrc_ini1_u; + +/* Define the union csr_petx_ecrc_msk0_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk0_h : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk0_h_u; + +/* Define the union csr_petx_ecrc_msk0_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk0_l : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk0_l_u; + +/* Define the union csr_petx_ecrc_msk1_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk1_h : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk1_h_u; + +/* Define the union csr_petx_ecrc_msk1_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk1_l : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk1_l_u; + +/* Define the union csr_petx_ecrc_msk2_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk2_h : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk2_h_u; + +/* Define the union csr_petx_ecrc_msk2_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk2_l : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk2_l_u; + +/* Define the union csr_petx_ecrc_msk3_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk3_h : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk3_h_u; + +/* Define the union csr_petx_ecrc_msk3_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ecrc_msk3_l : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ecrc_msk3_l_u; + +/* Define the union csr_petx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gbfo_af_th : 8; /* [7:0] */ + u32 petx_hefo_af_th : 7; /* [14:8] */ + u32 rsvd : 17; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fifo_af_th_u; + +/* Define the union csr_petx_n1588_clk_ofs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_n1588_clk_ofs : 31; /* [30:0] */ + u32 petx_n1588_clk_ofs_inc : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_n1588_clk_ofs_u; + +/* Define the union csr_petx_1588_clk_ofs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_1588_clk_ofs : 31; /* [30:0] */ + u32 petx_1588_clk_ofs_inc : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_1588_clk_ofs_u; + +/* Define the union csr_petx_vbs_hcrc_ini0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_vbs_hcrc_ini0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_vbs_hcrc_ini0_u; + +/* Define the union csr_petx_vbs_hcrc_ini1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_vbs_hcrc_ini1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_vbs_hcrc_ini1_u; + +/* Define the union csr_petx_gip0_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gip0_id : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_gip0_id_u; + +/* Define the union csr_petx_gip1_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gip1_id : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_gip1_id_u; + +/* Define the union csr_petx_gip2_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gip2_id : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_gip2_id_u; + +/* Define the union csr_petx_gip3_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gip3_id : 16; /* [15:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_gip3_id_u; + +/* Define the union csr_petx_ram_ctrl_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_ctrl_h : 6; /* [5:0] */ + u32 rsvd : 26; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_ctrl_h_u; + +/* Define the union csr_petx_ram_ctrl_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ram_ctrl_m : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ram_ctrl_m_u; + +/* Define the union csr_petx_ram_ctrl_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 petx_ram_ctrl_l : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_petx_ram_ctrl_l_u; + +/* Define the union csr_petx_clk_period_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_clk_period_fraction : 30; /* [29:0] */ + u32 petx_clk_period_integer : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_clk_period_u; + +/* Define the union csr_petx_chnl_sof_eof_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_chnl_sof_eof_st : 11; /* [10:0] */ + u32 rsvd : 21; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_chnl_sof_eof_st_u; + +/* Define the union csr_petx_chnl_crdt_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_chnl_crdt_st : 11; /* [10:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_chnl_crdt_st_u; + +/* Define the union csr_petx_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gbfo_cnt : 8; /* [7:0] */ + u32 petx_hefo_cnt : 7; /* [14:8] */ + u32 rsvd : 17; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fifo_cnt_u; + +/* Define the union csr_petx_fifo_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gbfo_ovf_cur : 1; /* [0] */ + u32 petx_gbfo_full_cur : 1; /* [1] */ + u32 petx_gbfo_empty_cur : 1; /* [2] */ + u32 rsv_10 : 1; /* [3] */ + u32 petx_hefo_ovf_cur : 1; /* [4] */ + u32 petx_hefo_full_cur : 1; /* [5] */ + u32 petx_hefo_empty_cur : 1; /* [6] */ + u32 rsv_11 : 1; /* [7] */ + u32 rsv_12 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fifo_cur_st_u; + +/* Define the union csr_petx_fifo_hst_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_gbfo_ovf_hst : 1; /* [0] */ + u32 petx_gbfo_full_hst : 1; /* [1] */ + u32 petx_hefo_ovf_hst : 1; /* [2] */ + u32 petx_hefo_full_hst : 1; /* [3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_fifo_hst_st_u; + +/* Define the union csr_petx_sof_eof_err_hst_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_sof_eof_err_hst : 11; /* [10:0] */ + u32 rsvd : 21; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_sof_eof_err_hst_st_u; + +/* Define the union csr_petx_cpb_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_cpb_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_cpb_pkt_cnt_u; + +/* Define the union csr_petx_mag_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_mag_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_mag_pkt_cnt_u; + +/* Define the union csr_petx_cpb_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_cpb_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_cpb_err_pkt_cnt_u; + +/* Define the union csr_petx_mag_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_mag_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_mag_err_pkt_cnt_u; + +/* Define the union csr_petx_ram_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_ucerr_cnt_u; + +/* Define the union csr_petx_ram_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_ram_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_ram_cerr_cnt_u; + +/* Define the union csr_petx_rcv_cpb_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rcv_cpb_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rcv_cpb_cyc_cnt_u; + +/* Define the union csr_petx_rtn_cpb_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rtn_cpb_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rtn_cpb_crdt_cnt_u; + +/* Define the union csr_petx_rtn_cpb_ififo_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rtn_cpb_ififo_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rtn_cpb_ififo_crdt_cnt_u; + +/* Define the union csr_petx_rtn_cpb_cmdidx_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rtn_cpb_cmdidx_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rtn_cpb_cmdidx_crdt_cnt_u; + +/* Define the union csr_petx_snt_mag_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_snt_mag_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_snt_mag_cyc_cnt_u; + +/* Define the union csr_petx_rcv_mag_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rcv_mag_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rcv_mag_crdt_cnt_u; + +/* Define the union csr_petx_rcv_mag_cmdidx_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 petx_rcv_mag_cmdidx_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_petx_rcv_mag_cmdidx_crdt_cnt_u; + + +/* Define the union csr_perx_fpga_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fpga_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fpga_ver_u; + +/* Define the union csr_perx_emu_ver_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_emu_ver : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_emu_ver_u; + +/* Define the union csr_perx_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ini_cmd_ram_start : 1; /* [0] */ + u32 perx_ini_dgst_ram_start : 1; /* [1] */ + u32 rsv_0 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_initctab_start_u; + +/* Define the union csr_perx_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ini_cmd_ram_done : 1; /* [0] */ + u32 perx_ini_dgst_ram_done : 1; /* [1] */ + u32 rsv_1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_initctab_done_u; + +/* Define the union csr_perx_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 perx_int_enable : 1; /* [27] */ + u32 perx_int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_int_vector_u; + +/* Define the union csr_perx_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_int_data : 5; /* [4:0] */ + u32 rsv_4 : 11; /* [15:5] */ + u32 perx_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_int_u; + +/* Define the union csr_perx_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_int_en : 5; /* [4:0] */ + u32 rsv_5 : 11; /* [15:5] */ + u32 perx_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_int_en_u; + +/* Define the union csr_perx_cmd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cmd_err : 1; /* [0] */ + u32 perx_cmd_inj_err : 1; /* [1] */ + u32 perx_cmd_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cmd_err_u; + +/* Define the union csr_perx_ram_ucerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_ucerr : 1; /* [0] */ + u32 perx_inj_ram_ucerr : 1; /* [1] */ + u32 perx_ram_ucerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_ucerr_u; + +/* Define the union csr_perx_ram_cerr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_cerr : 1; /* [0] */ + u32 perx_inj_ram_cerr : 1; /* [1] */ + u32 perx_ram_cerr_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_cerr_u; + +/* Define the union csr_perx_crdt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_crdt_err : 1; /* [0] */ + u32 perx_crdt_inj_err : 1; /* [1] */ + u32 perx_crdt_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_crdt_err_u; + +/* Define the union csr_perx_fifo_ovf_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fifo_ovf_err : 1; /* [0] */ + u32 perx_fifo_ovf_inj_err : 1; /* [1] */ + u32 perx_fifo_ovf_err_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fifo_ovf_err_u; + +/* Define the union csr_perx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_indrect_addr : 24; /* [23:0] */ + u32 perx_indrect_tab : 4; /* [27:24] */ + u32 perx_indrect_state : 2; /* [29:28] */ + u32 perx_indrect_mode : 1; /* [30] */ + u32 perx_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_indrect_ctrl_u; + +/* Define the union csr_perx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_indrect_timeout_u; + +/* Define the union csr_perx_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_indrect_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_indrect_data_u; + +/* Define the union csr_perx_ucerr_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cmd_ucerr_ctrl : 1; /* [0] */ + u32 perx_crdt_ucerr_ctrl : 1; /* [1] */ + u32 perx_cpb_ifo_ovf_ctrl : 1; /* [2] */ + u32 perx_dcry_ifo_ovf_ctrl : 1; /* [3] */ + u32 perx_hefo_ovf_ctrl : 1; /* [4] */ + u32 perx_fst_gbfo_ovf_ctrl : 1; /* [5] */ + u32 perx_difxoc_fifo_ovf_ctrl : 1; /* [6] */ + u32 rsv_6 : 1; /* [7] */ + u32 perx_cpb_cdf_ram_ucerr_ctrl : 1; /* [8] */ + u32 perx_cpb_ifo_ram_ucerr_ctrl : 1; /* [9] */ + u32 perx_dcry_cdf_ram_ucerr_ctrl : 1; /* [10] */ + u32 perx_dcry_ifo_ram_ucerr_ctrl : 1; /* [11] */ + u32 perx_cpsfo_ram_ucerr_ctrl : 1; /* [12] */ + u32 perx_he_ram_ucerr_ctrl : 1; /* [13] */ + u32 perx_fcht_ram_ucerr_ctrl : 1; /* [14] */ + u32 perx_fst_gbfo_ram_ucerr_ctrl : 1; /* [15] */ + u32 perx_dctx_ram_ucerr_ctrl : 1; /* [16] */ + u32 perx_difxpp_ram_ucerr_ctrl : 1; /* [17] */ + u32 perx_difx_ioc_ram_ucerr_ctrl : 1; /* [18] */ + u32 perx_difxoc_dram_ucerr_ctrl : 1; /* [19] */ + u32 perx_difxoc_smd_ram_ucerr_ctrl : 1; /* [20] */ + u32 perx_mpu_ipsurx_ram_ucerr_ctrl : 1; /* [21] */ + u32 perx_otcc_rocfo_ram_ucerr_ctrl : 1; /* [22] */ + u32 perx_otcc_rwcfo_ram_ucerr_ctrl : 1; /* [23] */ + u32 rsv_7 : 7; /* [30:24] */ + u32 perx_ucerr_ctrl : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ucerr_ctrl_u; + +/* Define the union csr_perx_ram_err_chk_bypass_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_err_chk_bypass : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_err_chk_bypass_u; + +/* Define the union csr_perx_inj_ram_err_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_inj_cpb_cdf_ram_cerr : 1; /* [0] */ + u32 perx_inj_cpb_cdf_ram_ucerr : 1; /* [1] */ + u32 perx_inj_cpb_ifo_ram_cerr : 1; /* [2] */ + u32 perx_inj_cpb_ifo_ram_ucerr : 1; /* [3] */ + u32 perx_inj_dcry_cdf_ram_cerr : 1; /* [4] */ + u32 perx_inj_dcry_cdf_ram_ucerr : 1; /* [5] */ + u32 perx_inj_dcry_ifo_ram_cerr : 1; /* [6] */ + u32 perx_inj_dcry_ifo_ram_ucerr : 1; /* [7] */ + u32 perx_inj_cpsfo_ram_cerr : 1; /* [8] */ + u32 perx_inj_cpsfo_ram_ucerr : 1; /* [9] */ + u32 perx_inj_he_ram_cerr : 1; /* [10] */ + u32 perx_inj_he_ram_ucerr : 1; /* [11] */ + u32 perx_inj_fcht_ram_cerr : 1; /* [12] */ + u32 perx_inj_fcht_ram_ucerr : 1; /* [13] */ + u32 perx_inj_fst_gbfo_ram_cerr : 1; /* [14] */ + u32 perx_inj_fst_gbfo_ram_ucerr : 1; /* [15] */ + u32 perx_inj_dctx_ram_cerr : 1; /* [16] */ + u32 perx_inj_dctx_ram_ucerr : 1; /* [17] */ + u32 perx_inj_difxpp_ram_cerr : 1; /* [18] */ + u32 perx_inj_difxpp_ram_ucerr : 1; /* [19] */ + u32 perx_inj_difx_ioc_ram_cerr : 1; /* [20] */ + u32 perx_inj_difx_ioc_ram_ucerr : 1; /* [21] */ + u32 perx_inj_difxoc_dat_ram_cerr : 1; /* [22] */ + u32 perx_inj_difxoc_dat_ram_ucerr : 1; /* [23] */ + u32 perx_inj_difxoc_smd_ram_cerr : 1; /* [24] */ + u32 perx_inj_difxoc_smd_ram_ucerr : 1; /* [25] */ + u32 perx_inj_mpu_ipsurx_ram_cerr : 1; /* [26] */ + u32 perx_inj_mpu_ipsurx_ram_ucerr : 1; /* [27] */ + u32 perx_inj_otcc_rocfo_ram_cerr : 1; /* [28] */ + u32 perx_inj_otcc_rocfo_ram_ucerr : 1; /* [29] */ + u32 perx_inj_otcc_rwcfo_ram_cerr : 1; /* [30] */ + u32 perx_inj_otcc_rwcfo_ram_ucerr : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_inj_ram_err_cfg_u; + +/* Define the union csr_perx_en_hcmd_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_en_hcmd_num : 4; /* [3:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_en_hcmd_num_u; + +/* Define the union csr_perx_chnl_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_chnl_hcmd_en : 1; /* [0] */ + u32 perx_chnl_dcry_en : 1; /* [1] */ + u32 perx_chnl_difxe_en : 1; /* [2] */ + u32 perx_dsgl_smd_num : 5; /* [7:3] */ + u32 rsv_8 : 15; /* [22:8] */ + u32 perx_chnl_idle_th : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_chnl_cfg_u; + +/* Define the union csr_perx_pre_alc_pkt_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_pre_alc_pkt_crdt0 : 4; /* [3:0] */ + u32 perx_pre_alc_pkt_crdt1 : 4; /* [7:4] */ + u32 perx_ertn_pkt_crdt_th : 4; /* [11:8] */ + u32 rsvd : 20; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_pre_alc_pkt_crdt_u; + +/* Define the union csr_perx_lp_mpu_chnl_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ipsurx_chnl1_crdt : 7; /* [6:0] */ + u32 rsv_9 : 1; /* [7] */ + u32 perx_ipsurx_chnl0_crdt : 7; /* [14:8] */ + u32 rsv_10 : 1; /* [15] */ + u32 perx_mpu_chnl_crdt : 7; /* [22:16] */ + u32 rsv_11 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_lp_mpu_chnl_crdt_u; + +/* Define the union csr_perx_icrc_ini0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_icrc_ini0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_icrc_ini0_u; + +/* Define the union csr_perx_icrc_ini1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_icrc_ini1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_icrc_ini1_u; + +/* Define the union csr_perx_icrc_mgc0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_icrc_mgc0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_icrc_mgc0_u; + +/* Define the union csr_perx_icrc_mgc1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_icrc_mgc1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_icrc_mgc1_u; + +/* Define the union csr_perx_difx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_grd_crc_ini : 16; /* [15:0] */ + u32 perx_grd_cs_ini : 16; /* [31:16] */ + u32 perx_difx_vrf_special_en : 1; /* [32] */ + u32 perx_difx_rev_ipcs_rslt : 1; /* [33] */ + u32 perx_difx_rev_ipcs_f1_rslt : 1; /* [34] */ + u32 perx_difx_rev_ipcs_f0_rslt : 1; /* [35] */ + u32 perx_difx_rev_crc16_rslt : 1; /* [36] */ + u32 perx_difx_crc16_rslt_odr : 1; /* [37] */ + u32 perx_difx_crc16_in_dat_odr : 1; /* [38] */ + u32 rsvd : 25; + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_perx_difx_cfg_u; + +/* Define the union csr_perx_fifo_af_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fgbfo_af_th : 8; /* [7:0] */ + u32 perx_hefo_af_th : 7; /* [14:8] */ + u32 rsv_12 : 1; /* [15] */ + u32 perx_difxoc_fifo_af_th : 7; /* [22:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fifo_af_th_u; + +/* Define the union csr_perx_1588_clk_ofs_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_1588_clk_ofs : 31; /* [30:0] */ + u32 perx_1588_clk_ofs_inc : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_1588_clk_ofs_u; + +/* Define the union csr_perx_ppop_chnl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ppop_ack_chnl : 5; /* [4:0] */ + u32 rsv_13 : 3; /* [7:5] */ + u32 perx_ppop_rqst_chnl : 5; /* [12:8] */ + u32 perx_ppop_en : 1; /* [13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ppop_chnl_u; + +/* Define the union csr_perx_ram_ctrl_h_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_ctrl_hh : 6; /* [5:0] */ + u32 rsvd : 26; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_ctrl_h_u; + +/* Define the union csr_perx_ram_ctrl_m_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 perx_ram_ctrl_hm : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_perx_ram_ctrl_m_u; + +/* Define the union csr_perx_ram_ctrl_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 perx_ram_ctrl_mm : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_perx_ram_ctrl_l_u; + +/* Define the union csr_perx_clk_period_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_clk_period_fraction : 30; /* [29:0] */ + u32 perx_clk_period_integer : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_clk_period_u; + +/* Define the union csr_perx_chnl_sop_eop_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpb_sop_eop_st : 23; /* [22:0] */ + u32 rsv_14 : 1; /* [23] */ + u32 perx_dcry_sop_eop_st : 18; /* [41:24] */ + u32 rsvd : 22; + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_perx_chnl_sop_eop_st_u; + +/* Define the union csr_perx_chnl_crdt_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpb_chnl_crdt_st : 23; /* [22:0] */ + u32 rsv_15 : 1; /* [23] */ + u32 perx_dcry_chnl_crdt_st : 3; /* [26:24] */ + u32 rsvd : 5; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_chnl_crdt_st_u; + +/* Define the union csr_perx_fifo_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fst_gbfo_cnt : 8; /* [7:0] */ + u32 perx_hefo_cnt : 7; /* [14:8] */ + u32 rsv_16 : 1; /* [15] */ + u32 perx_difxoc_fifo_cnt : 7; /* [22:16] */ + u32 rsvd : 9; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fifo_cnt_u; + +/* Define the union csr_perx_fifo_cur_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fst_gbfo_ovf_cur : 1; /* [0] */ + u32 perx_fst_gbfo_full_cur : 1; /* [1] */ + u32 perx_fst_gbfo_empty_cur : 1; /* [2] */ + u32 rsv_17 : 1; /* [3] */ + u32 perx_hefo_ovf_cur : 1; /* [4] */ + u32 perx_hefo_full_cur : 1; /* [5] */ + u32 perx_hefo_empty_cur : 1; /* [6] */ + u32 rsv_18 : 1; /* [7] */ + u32 perx_difxoc_fifo_ovf_cur : 1; /* [8] */ + u32 perx_difxoc_fifo_full_cur : 1; /* [9] */ + u32 perx_difxoc_fifo_empty_cur : 1; /* [10] */ + u32 rsv_19 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fifo_cur_st_u; + +/* Define the union csr_perx_fifo_hst_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_fst_gbfo_ovf_hst : 1; /* [0] */ + u32 perx_fst_gbfo_full_hst : 1; /* [1] */ + u32 perx_hefo_ovf_hst : 1; /* [2] */ + u32 perx_hefo_full_hst : 1; /* [3] */ + u32 perx_difxoc_fifo_ovf_hst : 1; /* [4] */ + u32 perx_difxoc_fifo_full_hst : 1; /* [5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_fifo_hst_st_u; + +/* Define the union csr_perx_sop_eop_err_hst_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpb_sop_eop_err_hst : 23; /* [22:0] */ + u32 rsv_20 : 1; /* [23] */ + u32 perx_dcry_sop_eop_err_hst : 18; /* [41:24] */ + u32 rsvd : 22; + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_sop_eop_err_hst_st_u; + +/* Define the union csr_perx_cpb_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpb_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cpb_pkt_cnt_u; + +/* Define the union csr_perx_s_dcry_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_s_dcry_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_s_dcry_pkt_cnt_u; + +/* Define the union csr_perx_r_dcry_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_r_dcry_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_r_dcry_pkt_cnt_u; + +/* Define the union csr_perx_cmi_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cmi_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cmi_pkt_cnt_u; + +/* Define the union csr_perx_ppop_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ppop_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ppop_pkt_cnt_u; + +/* Define the union csr_perx_drp_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_drp_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_drp_pkt_cnt_u; + +/* Define the union csr_perx_cpb_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpb_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cpb_err_pkt_cnt_u; + +/* Define the union csr_perx_s_dcry_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_s_dcry_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_s_dcry_err_pkt_cnt_u; + +/* Define the union csr_perx_r_dcry_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_r_dcry_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_r_dcry_err_pkt_cnt_u; + +/* Define the union csr_perx_cpi_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpi_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cpi_err_pkt_cnt_u; + +/* Define the union csr_perx_ipsurx_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ipsurx_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ipsurx_err_pkt_cnt_u; + +/* Define the union csr_perx_mpu_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_mpu_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_mpu_err_pkt_cnt_u; + +/* Define the union csr_perx_ppop_err_pkt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ppop_err_pkt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ppop_err_pkt_cnt_u; + +/* Define the union csr_perx_ram_ucerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_ucerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_ucerr_cnt_u; + +/* Define the union csr_perx_ram_cerr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_ram_cerr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_ram_cerr_cnt_u; + +/* Define the union csr_perx_cpi_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_cpi_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_cpi_bp_cnt_u; + +/* Define the union csr_perx_mpu_bp_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_mpu_bp_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_mpu_bp_cnt_u; + +/* Define the union csr_perx_rcv_cpb_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rcv_cpb_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rcv_cpb_cyc_cnt_u; + +/* Define the union csr_perx_rtn_cpb_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_cpb_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_cpb_crdt_cnt_u; + +/* Define the union csr_perx_rtn_cpb_ififo_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_cpb_ififo_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_cpb_ififo_crdt_cnt_u; + +/* Define the union csr_perx_rtn_cpb_cmdidx_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_cpb_cmdidx_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_cpb_cmdidx_crdt_cnt_u; + +/* Define the union csr_perx_snt_dcry_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_snt_dcry_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_snt_dcry_cyc_cnt_u; + +/* Define the union csr_perx_rcv_dcry_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rcv_dcry_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rcv_dcry_crdt_cnt_u; + +/* Define the union csr_perx_rcv_dcry_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rcv_dcry_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rcv_dcry_cyc_cnt_u; + +/* Define the union csr_perx_rtn_dcry_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_dcry_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_dcry_crdt_cnt_u; + +/* Define the union csr_perx_rtn_dcry_ififo_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_dcry_ififo_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_dcry_ififo_crdt_cnt_u; + +/* Define the union csr_perx_rtn_dcry_cmdidx_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rtn_dcry_cmdidx_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rtn_dcry_cmdidx_crdt_cnt_u; + +/* Define the union csr_perx_snt_cpi_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_snt_cpi_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_snt_cpi_cyc_cnt_u; + +/* Define the union csr_perx_snt_ipsurx_cyc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_snt_ipsurx_cyc_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_snt_ipsurx_cyc_cnt_u; + +/* Define the union csr_perx_rcv_ipsurx_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_rcv_ipsurx_crdt_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_rcv_ipsurx_crdt_cnt_u; + +/* Define the union csr_perx_dgst_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_dgst_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_dgst_err_cnt_u; + +/* Define the union csr_perx_sector_grd_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_sector_grd_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_sector_grd_ilgl_cnt_u; + +/* Define the union csr_perx_sector_ref_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_sector_ref_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_sector_ref_ilgl_cnt_u; + +/* Define the union csr_perx_sector_app_ilgl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_sector_app_ilgl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_sector_app_ilgl_cnt_u; + +/* Define the union csr_perx_difx_err_dfx_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_err_dfx_clr : 1; /* [0] */ + u32 rsv_21 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_dfx_clr_u; + +/* Define the union csr_perx_difx_err_info_dw0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_guard_err : 1; /* [0] */ + u32 perx_difx_app_err : 1; /* [1] */ + u32 perx_difx_ref_err : 1; /* [2] */ + u32 rsv_22 : 1; /* [3] */ + u32 perx_difx_vrf_type : 2; /* [5:4] */ + u32 rsv_23 : 2; /* [7:6] */ + u32 perx_difx_err_chnl : 5; /* [12:8] */ + u32 rsv_24 : 3; /* [15:13] */ + u32 perx_difx_task_tag : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_info_dw0_u; + +/* Define the union csr_perx_difx_err_info_dw1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_rcv_guard : 16; /* [15:0] */ + u32 perx_difx_rcv_app : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_info_dw1_u; + +/* Define the union csr_perx_difx_err_info_dw2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_rcv_ref : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_info_dw2_u; + +/* Define the union csr_perx_difx_err_info_dw3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_exp_guard : 16; /* [15:0] */ + u32 perx_difx_exp_app : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_info_dw3_u; + +/* Define the union csr_perx_difx_err_info_dw4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 perx_difx_exp_ref : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_perx_difx_err_info_dw4_u; + + +#endif // PE_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_reg_offset.h new file mode 100644 index 000000000..7b545e252 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pe_reg_offset.h @@ -0,0 +1,493 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2019, Hisilicon Technologies Co. Ltd. +// File name : pe_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2018/12/05 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2019/05/07 11:24:30 Create file +// ****************************************************************************** + +#ifndef PE_REG_OFFSET_H +#define PE_REG_OFFSET_H + +/* PETX_CSR Base address of Module's Register */ +#define CSR_PETX_CSR_BASE (0xA000) + +/* **************************************************************************** */ +/* PETX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_PETX_CSR_PETX_FPGA_VER_REG (CSR_PETX_CSR_BASE + 0x0) /* FPGA版本寄存器 */ +#define CSR_PETX_CSR_PETX_EMU_VER_REG (CSR_PETX_CSR_BASE + 0x8) /* EMU版本寄存器 */ +#define CSR_PETX_CSR_PETX_INITCTAB_START_REG (CSR_PETX_CSR_BASE + 0x10) /* 配置表初始化使能寄存器 */ +#define CSR_PETX_CSR_PETX_INITCTAB_DONE_REG (CSR_PETX_CSR_BASE + 0x18) /* 配置表初始化状态寄存器 */ +#define CSR_PETX_CSR_PETX_INT_VECTOR_REG (CSR_PETX_CSR_BASE + 0x20) /* 中断向量寄存器 */ +#define CSR_PETX_CSR_PETX_INT_REG (CSR_PETX_CSR_BASE + 0x28) /* 中断数据寄存器 */ +#define CSR_PETX_CSR_PETX_INT_EN_REG (CSR_PETX_CSR_BASE + 0x30) /* 中断使能寄存器 */ +#define CSR_PETX_CSR_PETX_CMD_ERR_REG (CSR_PETX_CSR_BASE + 0x38) /* CMD错误中断错误寄存器。 */ +#define CSR_PETX_CSR_PETX_RAM_UCERR_REG (CSR_PETX_CSR_BASE + 0x40) /* RAM 不可纠错误中断错误寄存器。 */ +#define CSR_PETX_CSR_PETX_RAM_CERR_REG (CSR_PETX_CSR_BASE + 0x48) /* RAM 可纠错误中断错误寄存器。 */ +#define CSR_PETX_CSR_PETX_CRDT_ERR_REG (CSR_PETX_CSR_BASE + 0x50) /* 信用错误中断错误寄存器。 */ +#define CSR_PETX_CSR_PETX_FIFO_OVF_ERR_REG (CSR_PETX_CSR_BASE + 0x58) /* FIFO溢出中断错误寄存器。 */ +#define CSR_PETX_CSR_PETX_INDRECT_CTRL_REG (CSR_PETX_CSR_BASE + 0x320) /* 间接寻址控制寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_TIMEOUT_REG (CSR_PETX_CSR_BASE + 0x328) /* 间接寻址TIMEOUT配置寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_0_REG (CSR_PETX_CSR_BASE + 0x330) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_1_REG (CSR_PETX_CSR_BASE + 0x334) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_2_REG (CSR_PETX_CSR_BASE + 0x338) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_3_REG (CSR_PETX_CSR_BASE + 0x33C) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_4_REG (CSR_PETX_CSR_BASE + 0x340) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_5_REG (CSR_PETX_CSR_BASE + 0x344) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_6_REG (CSR_PETX_CSR_BASE + 0x348) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_7_REG (CSR_PETX_CSR_BASE + 0x34C) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_8_REG (CSR_PETX_CSR_BASE + 0x350) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_9_REG (CSR_PETX_CSR_BASE + 0x354) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_10_REG (CSR_PETX_CSR_BASE + 0x358) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_11_REG (CSR_PETX_CSR_BASE + 0x35C) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_12_REG (CSR_PETX_CSR_BASE + 0x360) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_13_REG (CSR_PETX_CSR_BASE + 0x364) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_14_REG (CSR_PETX_CSR_BASE + 0x368) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_INDRECT_DATA_15_REG (CSR_PETX_CSR_BASE + 0x36C) /* 间接寻址数据寄存器 */ +#define CSR_PETX_CSR_PETX_UCERR_CTRL_REG (CSR_PETX_CSR_BASE + 0x400) /* petx致命错误控制寄存器 */ +#define CSR_PETX_CSR_PETX_RAM_ERR_CHK_BYPASS_REG (CSR_PETX_CSR_BASE + 0x410) /* petx模块RAM错误检查BYPASS寄存器 */ +#define CSR_PETX_CSR_PETX_INJ_RAM_ERR_CFG_REG (CSR_PETX_CSR_BASE + 0x418) /* petx模块RAM错误注入寄存器 */ +#define CSR_PETX_CSR_PETX_EN_HCMD_NUM_REG (CSR_PETX_CSR_BASE + 0x420) /* HDR_CMD使能寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_0_REG (CSR_PETX_CSR_BASE + 0x428) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_1_REG (CSR_PETX_CSR_BASE + 0x42C) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_2_REG (CSR_PETX_CSR_BASE + 0x430) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_3_REG (CSR_PETX_CSR_BASE + 0x434) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_4_REG (CSR_PETX_CSR_BASE + 0x438) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_5_REG (CSR_PETX_CSR_BASE + 0x43C) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_6_REG (CSR_PETX_CSR_BASE + 0x440) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_7_REG (CSR_PETX_CSR_BASE + 0x444) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_8_REG (CSR_PETX_CSR_BASE + 0x448) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_9_REG (CSR_PETX_CSR_BASE + 0x44C) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_CHNL_CFG_10_REG (CSR_PETX_CSR_BASE + 0x450) /* 通道配置寄存器 */ +#define CSR_PETX_CSR_PETX_PRE_ALC_PKT_CRDT_REG (CSR_PETX_CSR_BASE + 0x500) /* PKT预扣信用寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_INI0_REG (CSR_PETX_CSR_BASE + 0x508) /* FC/RoCE CRC初始值寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_INI1_REG (CSR_PETX_CSR_BASE + 0x510) /* FC/RoCE CRC初始值寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK0_H_REG (CSR_PETX_CSR_BASE + 0x518) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK0_L_REG (CSR_PETX_CSR_BASE + 0x520) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK1_H_REG (CSR_PETX_CSR_BASE + 0x528) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK1_L_REG (CSR_PETX_CSR_BASE + 0x530) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK2_H_REG (CSR_PETX_CSR_BASE + 0x538) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK2_L_REG (CSR_PETX_CSR_BASE + 0x540) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK3_H_REG (CSR_PETX_CSR_BASE + 0x548) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_ECRC_MSK3_L_REG (CSR_PETX_CSR_BASE + 0x550) /* ECRC MASK寄存器 */ +#define CSR_PETX_CSR_PETX_FIFO_AF_TH_REG (CSR_PETX_CSR_BASE + 0x558) /* FIFO配置寄存器 */ +#define CSR_PETX_CSR_PETX_N1588_CLK_OFS_REG (CSR_PETX_CSR_BASE + 0x560) /* EPTX 非1588时钟偏移配置寄存器 */ +#define CSR_PETX_CSR_PETX_1588_CLK_OFS_REG (CSR_PETX_CSR_BASE + 0x568) /* EPTX1588时钟偏移配置寄存器 */ +#define CSR_PETX_CSR_PETX_VBS_HCRC_INI0_REG (CSR_PETX_CSR_BASE + 0x570) /* VBS HDR CRC初始值寄存器 */ +#define CSR_PETX_CSR_PETX_VBS_HCRC_INI1_REG (CSR_PETX_CSR_BASE + 0x578) /* VBS HDR CRC初始值寄存器 */ +#define CSR_PETX_CSR_PETX_GIP0_ID_REG (CSR_PETX_CSR_BASE + 0x580) /* 全局IP HDR ID寄存器 */ +#define CSR_PETX_CSR_PETX_GIP1_ID_REG (CSR_PETX_CSR_BASE + 0x588) /* 全局IP HDR ID寄存器 */ +#define CSR_PETX_CSR_PETX_GIP2_ID_REG (CSR_PETX_CSR_BASE + 0x590) /* 全局IP HDR ID寄存器 */ +#define CSR_PETX_CSR_PETX_GIP3_ID_REG (CSR_PETX_CSR_BASE + 0x598) /* 全局IP HDR ID寄存器 */ +#define CSR_PETX_CSR_PETX_RAM_CTRL_H_REG (CSR_PETX_CSR_BASE + 0x5A0) /* RAM MOD控制寄存器 */ +#define CSR_PETX_CSR_PETX_RAM_CTRL_M_REG (CSR_PETX_CSR_BASE + 0x5A8) /* RAM MOD控制寄存器 */ +#define CSR_PETX_CSR_PETX_RAM_CTRL_L_REG (CSR_PETX_CSR_BASE + 0x5B0) /* RAM MOD控制寄存器 */ +#define CSR_PETX_CSR_PETX_CLK_PERIOD_REG \ + (CSR_PETX_CSR_BASE + 0x5B8) /* PETX时钟周期配置寄存器。用于在CPI提供的时钟基础上维护PETX本地时钟。 */ +#define CSR_PETX_CSR_PETX_CHNL_SOF_EOF_ST_REG (CSR_PETX_CSR_BASE + 0xF98) /* 通道SOF/EOF状态 */ +#define CSR_PETX_CSR_PETX_CHNL_CRDT_ST_REG (CSR_PETX_CSR_BASE + 0xFA0) /* 通道信用状态 */ +#define CSR_PETX_CSR_PETX_FIFO_CNT_REG (CSR_PETX_CSR_BASE + 0xFA8) /* FIFO当前深度计数寄存器 */ +#define CSR_PETX_CSR_PETX_FIFO_CUR_ST_REG (CSR_PETX_CSR_BASE + 0xFB0) /* FIFO当前状态寄存器 */ +#define CSR_PETX_CSR_PETX_FIFO_HST_ST_REG (CSR_PETX_CSR_BASE + 0xFB8) /* FIFO历史状态寄存器 */ +#define CSR_PETX_CSR_PETX_SOF_EOF_ERR_HST_ST_REG (CSR_PETX_CSR_BASE + 0xFC0) /* 通道SOF/EOF ERR历史寄存器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_0_REG (CSR_PETX_CSR_BASE + 0x12C0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_1_REG (CSR_PETX_CSR_BASE + 0x12C4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_2_REG (CSR_PETX_CSR_BASE + 0x12C8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_3_REG (CSR_PETX_CSR_BASE + 0x12CC) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_4_REG (CSR_PETX_CSR_BASE + 0x12D0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_5_REG (CSR_PETX_CSR_BASE + 0x12D4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_6_REG (CSR_PETX_CSR_BASE + 0x12D8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_7_REG (CSR_PETX_CSR_BASE + 0x12DC) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_8_REG (CSR_PETX_CSR_BASE + 0x12E0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_9_REG (CSR_PETX_CSR_BASE + 0x12E4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_PKT_CNT_10_REG (CSR_PETX_CSR_BASE + 0x12E8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_0_REG (CSR_PETX_CSR_BASE + 0x13C0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_1_REG (CSR_PETX_CSR_BASE + 0x13C4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_2_REG (CSR_PETX_CSR_BASE + 0x13C8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_3_REG (CSR_PETX_CSR_BASE + 0x13CC) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_4_REG (CSR_PETX_CSR_BASE + 0x13D0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_5_REG (CSR_PETX_CSR_BASE + 0x13D4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_6_REG (CSR_PETX_CSR_BASE + 0x13D8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_7_REG (CSR_PETX_CSR_BASE + 0x13DC) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_8_REG (CSR_PETX_CSR_BASE + 0x13E0) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_9_REG (CSR_PETX_CSR_BASE + 0x13E4) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_PKT_CNT_10_REG (CSR_PETX_CSR_BASE + 0x13E8) /* 报文计数器 */ +#define CSR_PETX_CSR_PETX_CPB_ERR_PKT_CNT_REG (CSR_PETX_CSR_BASE + 0x1500) /* 错误报文计数器 */ +#define CSR_PETX_CSR_PETX_MAG_ERR_PKT_CNT_REG (CSR_PETX_CSR_BASE + 0x1508) /* 错误报文计数器 */ +#define CSR_PETX_CSR_PETX_RAM_UCERR_CNT_REG (CSR_PETX_CSR_BASE + 0x1510) /* PETX RAM 不可纠错误计数器 */ +#define CSR_PETX_CSR_PETX_RAM_CERR_CNT_REG (CSR_PETX_CSR_BASE + 0x1518) /* PETX RAM 可纠错误计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_0_REG (CSR_PETX_CSR_BASE + 0x1600) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_1_REG (CSR_PETX_CSR_BASE + 0x1604) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_2_REG (CSR_PETX_CSR_BASE + 0x1608) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_3_REG (CSR_PETX_CSR_BASE + 0x160C) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_4_REG (CSR_PETX_CSR_BASE + 0x1610) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_5_REG (CSR_PETX_CSR_BASE + 0x1614) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_6_REG (CSR_PETX_CSR_BASE + 0x1618) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_7_REG (CSR_PETX_CSR_BASE + 0x161C) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_8_REG (CSR_PETX_CSR_BASE + 0x1620) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_9_REG (CSR_PETX_CSR_BASE + 0x1624) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_CPB_CYC_CNT_10_REG (CSR_PETX_CSR_BASE + 0x1628) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_0_REG (CSR_PETX_CSR_BASE + 0x1700) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_1_REG (CSR_PETX_CSR_BASE + 0x1704) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_2_REG (CSR_PETX_CSR_BASE + 0x1708) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_3_REG (CSR_PETX_CSR_BASE + 0x170C) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_4_REG (CSR_PETX_CSR_BASE + 0x1710) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_5_REG (CSR_PETX_CSR_BASE + 0x1714) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_6_REG (CSR_PETX_CSR_BASE + 0x1718) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_7_REG (CSR_PETX_CSR_BASE + 0x171C) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_8_REG (CSR_PETX_CSR_BASE + 0x1720) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_9_REG (CSR_PETX_CSR_BASE + 0x1724) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CRDT_CNT_10_REG (CSR_PETX_CSR_BASE + 0x1728) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_IFIFO_CRDT_CNT_REG (CSR_PETX_CSR_BASE + 0x1750) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RTN_CPB_CMDIDX_CRDT_CNT_REG (CSR_PETX_CSR_BASE + 0x1754) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_0_REG (CSR_PETX_CSR_BASE + 0x1800) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_1_REG (CSR_PETX_CSR_BASE + 0x1804) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_2_REG (CSR_PETX_CSR_BASE + 0x1808) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_3_REG (CSR_PETX_CSR_BASE + 0x180C) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_4_REG (CSR_PETX_CSR_BASE + 0x1810) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_5_REG (CSR_PETX_CSR_BASE + 0x1814) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_6_REG (CSR_PETX_CSR_BASE + 0x1818) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_7_REG (CSR_PETX_CSR_BASE + 0x181C) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_8_REG (CSR_PETX_CSR_BASE + 0x1820) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_9_REG (CSR_PETX_CSR_BASE + 0x1824) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_SNT_MAG_CYC_CNT_10_REG (CSR_PETX_CSR_BASE + 0x1828) /* 报文拍数计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_0_REG (CSR_PETX_CSR_BASE + 0x1900) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_1_REG (CSR_PETX_CSR_BASE + 0x1904) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_2_REG (CSR_PETX_CSR_BASE + 0x1908) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_3_REG (CSR_PETX_CSR_BASE + 0x190C) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_4_REG (CSR_PETX_CSR_BASE + 0x1910) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_5_REG (CSR_PETX_CSR_BASE + 0x1914) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_6_REG (CSR_PETX_CSR_BASE + 0x1918) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_7_REG (CSR_PETX_CSR_BASE + 0x191C) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_8_REG (CSR_PETX_CSR_BASE + 0x1920) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_9_REG (CSR_PETX_CSR_BASE + 0x1924) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CRDT_CNT_10_REG (CSR_PETX_CSR_BASE + 0x1928) /* 信用计数器 */ +#define CSR_PETX_CSR_PETX_RCV_MAG_CMDIDX_CRDT_CNT_REG (CSR_PETX_CSR_BASE + 0x1954) /* 信用计数器 */ + +/* PERX_CSR Base address of Module's Register */ +#define CSR_PERX_CSR_BASE (0x8000) + +/* **************************************************************************** */ +/* PERX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_PERX_CSR_PERX_FPGA_VER_REG (CSR_PERX_CSR_BASE + 0x0) /* FPGA版本寄存器 */ +#define CSR_PERX_CSR_PERX_EMU_VER_REG (CSR_PERX_CSR_BASE + 0x8) /* EMU版本寄存器 */ +#define CSR_PERX_CSR_PERX_INITCTAB_START_REG (CSR_PERX_CSR_BASE + 0x10) /* 配置表初始化使能寄存器 */ +#define CSR_PERX_CSR_PERX_INITCTAB_DONE_REG (CSR_PERX_CSR_BASE + 0x18) /* 配置表初始化状态寄存器 */ +#define CSR_PERX_CSR_PERX_INT_VECTOR_REG (CSR_PERX_CSR_BASE + 0x20) /* 中断向量寄存器 */ +#define CSR_PERX_CSR_PERX_INT_REG (CSR_PERX_CSR_BASE + 0x28) /* 中断数据寄存器 */ +#define CSR_PERX_CSR_PERX_INT_EN_REG (CSR_PERX_CSR_BASE + 0x30) /* 中断使能寄存器 */ +#define CSR_PERX_CSR_PERX_CMD_ERR_REG (CSR_PERX_CSR_BASE + 0x38) /* CMD错误中断错误寄存器。 */ +#define CSR_PERX_CSR_PERX_RAM_UCERR_REG (CSR_PERX_CSR_BASE + 0x40) /* RAM 不可纠错误中断错误寄存器。 */ +#define CSR_PERX_CSR_PERX_RAM_CERR_REG (CSR_PERX_CSR_BASE + 0x48) /* RAM 可纠错误中断错误寄存器。 */ +#define CSR_PERX_CSR_PERX_CRDT_ERR_REG (CSR_PERX_CSR_BASE + 0x50) /* 信用错误中断错误寄存器。 */ +#define CSR_PERX_CSR_PERX_FIFO_OVF_ERR_REG (CSR_PERX_CSR_BASE + 0x58) /* FIFO溢出中断错误寄存器。 */ +#define CSR_PERX_CSR_PERX_INDRECT_CTRL_REG (CSR_PERX_CSR_BASE + 0x320) /* 间接寻址控制寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_TIMEOUT_REG (CSR_PERX_CSR_BASE + 0x328) /* 间接寻址TIMEOUT配置寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_0_REG (CSR_PERX_CSR_BASE + 0x330) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_1_REG (CSR_PERX_CSR_BASE + 0x334) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_2_REG (CSR_PERX_CSR_BASE + 0x338) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_3_REG (CSR_PERX_CSR_BASE + 0x33C) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_4_REG (CSR_PERX_CSR_BASE + 0x340) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_5_REG (CSR_PERX_CSR_BASE + 0x344) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_6_REG (CSR_PERX_CSR_BASE + 0x348) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_7_REG (CSR_PERX_CSR_BASE + 0x34C) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_8_REG (CSR_PERX_CSR_BASE + 0x350) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_9_REG (CSR_PERX_CSR_BASE + 0x354) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_10_REG (CSR_PERX_CSR_BASE + 0x358) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_11_REG (CSR_PERX_CSR_BASE + 0x35C) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_12_REG (CSR_PERX_CSR_BASE + 0x360) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_13_REG (CSR_PERX_CSR_BASE + 0x364) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_14_REG (CSR_PERX_CSR_BASE + 0x368) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_INDRECT_DATA_15_REG (CSR_PERX_CSR_BASE + 0x36C) /* 间接寻址数据寄存器 */ +#define CSR_PERX_CSR_PERX_UCERR_CTRL_REG (CSR_PERX_CSR_BASE + 0x400) /* perx致命错误控制寄存器 */ +#define CSR_PERX_CSR_PERX_RAM_ERR_CHK_BYPASS_REG (CSR_PERX_CSR_BASE + 0x410) /* perx模块RAM错误检查BYPASS寄存器 */ +#define CSR_PERX_CSR_PERX_INJ_RAM_ERR_CFG_REG (CSR_PERX_CSR_BASE + 0x418) /* perx模块RAM错误注入寄存器 */ +#define CSR_PERX_CSR_PERX_EN_HCMD_NUM_REG (CSR_PERX_CSR_BASE + 0x420) /* HDR_CMD使能配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_0_REG (CSR_PERX_CSR_BASE + 0x428) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_1_REG (CSR_PERX_CSR_BASE + 0x42C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_2_REG (CSR_PERX_CSR_BASE + 0x430) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_3_REG (CSR_PERX_CSR_BASE + 0x434) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_4_REG (CSR_PERX_CSR_BASE + 0x438) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_5_REG (CSR_PERX_CSR_BASE + 0x43C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_6_REG (CSR_PERX_CSR_BASE + 0x440) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_7_REG (CSR_PERX_CSR_BASE + 0x444) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_8_REG (CSR_PERX_CSR_BASE + 0x448) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_9_REG (CSR_PERX_CSR_BASE + 0x44C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_10_REG (CSR_PERX_CSR_BASE + 0x450) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_11_REG (CSR_PERX_CSR_BASE + 0x454) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_12_REG (CSR_PERX_CSR_BASE + 0x458) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_13_REG (CSR_PERX_CSR_BASE + 0x45C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_14_REG (CSR_PERX_CSR_BASE + 0x460) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_15_REG (CSR_PERX_CSR_BASE + 0x464) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_16_REG (CSR_PERX_CSR_BASE + 0x468) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_17_REG (CSR_PERX_CSR_BASE + 0x46C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_18_REG (CSR_PERX_CSR_BASE + 0x470) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_19_REG (CSR_PERX_CSR_BASE + 0x474) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_20_REG (CSR_PERX_CSR_BASE + 0x478) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_21_REG (CSR_PERX_CSR_BASE + 0x47C) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_CHNL_CFG_22_REG (CSR_PERX_CSR_BASE + 0x480) /* 通道配置寄存器 */ +#define CSR_PERX_CSR_PERX_PRE_ALC_PKT_CRDT_REG (CSR_PERX_CSR_BASE + 0x500) /* PKT预扣信用寄存器 */ +#define CSR_PERX_CSR_PERX_LP_MPU_CHNL_CRDT_REG (CSR_PERX_CSR_BASE + 0x508) /* PERX环回/MPU通道信用配置寄存器 */ +#define CSR_PERX_CSR_PERX_ICRC_INI0_REG (CSR_PERX_CSR_BASE + 0x510) /* ICRC初始值寄存器 */ +#define CSR_PERX_CSR_PERX_ICRC_INI1_REG (CSR_PERX_CSR_BASE + 0x518) /* ICRC初始值寄存器 */ +#define CSR_PERX_CSR_PERX_ICRC_MGC0_REG (CSR_PERX_CSR_BASE + 0x520) /* ICRC MAGIC NUMBER寄存器 */ +#define CSR_PERX_CSR_PERX_ICRC_MGC1_REG (CSR_PERX_CSR_BASE + 0x528) /* ICRC MAGIC NUMBER寄存器 */ +#define CSR_PERX_CSR_PERX_DIFX_CFG_REG (CSR_PERX_CSR_BASE + 0x530) /* DIF/DIX校验配置寄存器 */ +#define CSR_PERX_CSR_PERX_FIFO_AF_TH_REG (CSR_PERX_CSR_BASE + 0x538) /* FIFO配置寄存器 */ +#define CSR_PERX_CSR_PERX_1588_CLK_OFS_REG (CSR_PERX_CSR_BASE + 0x540) /* EPRX1588时钟偏移配置寄存器 */ +#define CSR_PERX_CSR_PERX_PPOP_CHNL_REG (CSR_PERX_CSR_BASE + 0x548) /* PPOP channel配置寄存器 */ +#define CSR_PERX_CSR_PERX_RAM_CTRL_H_REG (CSR_PERX_CSR_BASE + 0x550) /* RAM MOD控制寄存器 */ +#define CSR_PERX_CSR_PERX_RAM_CTRL_M_REG (CSR_PERX_CSR_BASE + 0x558) /* RAM MOD控制寄存器 */ +#define CSR_PERX_CSR_PERX_RAM_CTRL_L_REG (CSR_PERX_CSR_BASE + 0x560) /* RAM MOD控制寄存器 */ +#define CSR_PERX_CSR_PERX_CLK_PERIOD_REG \ + (CSR_PERX_CSR_BASE + 0x568) /* PERX时钟周期配置寄存器。用于在CPI提供的时钟基础上维护PERX本地时钟。 */ +#define CSR_PERX_CSR_PERX_CHNL_SOP_EOP_ST_REG (CSR_PERX_CSR_BASE + 0xF98) /* 通道SOP/EOP状态 */ +#define CSR_PERX_CSR_PERX_CHNL_CRDT_ST_REG (CSR_PERX_CSR_BASE + 0xFA0) /* 通道信用状态 */ +#define CSR_PERX_CSR_PERX_FIFO_CNT_REG (CSR_PERX_CSR_BASE + 0xFA8) /* FIFO当前深度计数寄存器 */ +#define CSR_PERX_CSR_PERX_FIFO_CUR_ST_REG (CSR_PERX_CSR_BASE + 0xFB0) /* FIFO当前状态寄存器 */ +#define CSR_PERX_CSR_PERX_FIFO_HST_ST_REG (CSR_PERX_CSR_BASE + 0xFB8) /* FIFO历史状态寄存器 */ +#define CSR_PERX_CSR_PERX_SOP_EOP_ERR_HST_ST_REG (CSR_PERX_CSR_BASE + 0xFC0) /* 通道SOP/EOP错误历史寄存器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x12C0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x12C4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x12C8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x12CC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x12D0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x12D4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x12D8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x12DC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x12E0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x12E4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x12E8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x12EC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x12F0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x12F4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x12F8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_15_REG (CSR_PERX_CSR_BASE + 0x12FC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1300) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1304) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_18_REG (CSR_PERX_CSR_BASE + 0x1308) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_19_REG (CSR_PERX_CSR_BASE + 0x130C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_20_REG (CSR_PERX_CSR_BASE + 0x1310) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_21_REG (CSR_PERX_CSR_BASE + 0x1314) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_PKT_CNT_22_REG (CSR_PERX_CSR_BASE + 0x1318) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x13C0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x13C4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x13C8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x13CC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x13D0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x13D4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x13D8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x13DC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x13E0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x13E4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x13E8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x13EC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x13F0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x13F4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x13F8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_15_REG (CSR_PERX_CSR_BASE + 0x13FC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1400) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_PKT_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1404) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x1440) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x1444) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x1448) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x144C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x1450) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x1454) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x1458) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x145C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x1460) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x1464) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x1468) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x146C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x1470) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x1474) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x1478) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_15_REG (CSR_PERX_CSR_BASE + 0x147C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1480) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_PKT_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1484) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x14C0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x14C4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x14C8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x14CC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x14D0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x14D4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x14D8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x14DC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x14E0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x14E4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x14E8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x14EC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x14F0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x14F4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x14F8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_15_REG (CSR_PERX_CSR_BASE + 0x14FC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1500) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1504) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_18_REG (CSR_PERX_CSR_BASE + 0x1508) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_19_REG (CSR_PERX_CSR_BASE + 0x150C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_20_REG (CSR_PERX_CSR_BASE + 0x1510) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_21_REG (CSR_PERX_CSR_BASE + 0x1514) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CMI_PKT_CNT_22_REG (CSR_PERX_CSR_BASE + 0x1518) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_PPOP_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x151C) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x15C0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x15C4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x15C8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x15CC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x15D0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x15D4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x15D8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x15DC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x15E0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x15E4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x15E8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x15EC) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x15F0) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x15F4) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_DRP_PKT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x15F8) /* 报文计数器 */ +#define CSR_PERX_CSR_PERX_CPB_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1700) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_S_DCRY_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1708) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_R_DCRY_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1710) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_CPI_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1718) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_IPSURX_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1720) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_MPU_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x1728) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_PPOP_ERR_PKT_CNT_REG (CSR_PERX_CSR_BASE + 0x172C) /* 错误报文计数器 */ +#define CSR_PERX_CSR_PERX_RAM_UCERR_CNT_REG (CSR_PERX_CSR_BASE + 0x1730) /* PERX RAM 不可纠错误计数器 */ +#define CSR_PERX_CSR_PERX_RAM_CERR_CNT_REG (CSR_PERX_CSR_BASE + 0x1738) /* PERX RAM 可纠错误计数器 */ +#define CSR_PERX_CSR_PERX_CPI_BP_CNT_REG (CSR_PERX_CSR_BASE + 0x1740) /* CPI反压PERX计数器 */ +#define CSR_PERX_CSR_PERX_MPU_BP_CNT_REG (CSR_PERX_CSR_BASE + 0x1748) /* MPU反压PERX计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_0_REG (CSR_PERX_CSR_BASE + 0x17C0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_1_REG (CSR_PERX_CSR_BASE + 0x17C4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_2_REG (CSR_PERX_CSR_BASE + 0x17C8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_3_REG (CSR_PERX_CSR_BASE + 0x17CC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_4_REG (CSR_PERX_CSR_BASE + 0x17D0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_5_REG (CSR_PERX_CSR_BASE + 0x17D4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_6_REG (CSR_PERX_CSR_BASE + 0x17D8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_7_REG (CSR_PERX_CSR_BASE + 0x17DC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_8_REG (CSR_PERX_CSR_BASE + 0x17E0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_9_REG (CSR_PERX_CSR_BASE + 0x17E4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_10_REG (CSR_PERX_CSR_BASE + 0x17E8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_11_REG (CSR_PERX_CSR_BASE + 0x17EC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_12_REG (CSR_PERX_CSR_BASE + 0x17F0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_13_REG (CSR_PERX_CSR_BASE + 0x17F4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_14_REG (CSR_PERX_CSR_BASE + 0x17F8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_15_REG (CSR_PERX_CSR_BASE + 0x17FC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1800) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1804) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_18_REG (CSR_PERX_CSR_BASE + 0x1808) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_19_REG (CSR_PERX_CSR_BASE + 0x180C) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_20_REG (CSR_PERX_CSR_BASE + 0x1810) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_21_REG (CSR_PERX_CSR_BASE + 0x1814) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_CPB_CYC_CNT_22_REG (CSR_PERX_CSR_BASE + 0x1818) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x18C0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x18C4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x18C8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_3_REG (CSR_PERX_CSR_BASE + 0x18CC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_4_REG (CSR_PERX_CSR_BASE + 0x18D0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_5_REG (CSR_PERX_CSR_BASE + 0x18D4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_6_REG (CSR_PERX_CSR_BASE + 0x18D8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_7_REG (CSR_PERX_CSR_BASE + 0x18DC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_8_REG (CSR_PERX_CSR_BASE + 0x18E0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_9_REG (CSR_PERX_CSR_BASE + 0x18E4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_10_REG (CSR_PERX_CSR_BASE + 0x18E8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_11_REG (CSR_PERX_CSR_BASE + 0x18EC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_12_REG (CSR_PERX_CSR_BASE + 0x18F0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_13_REG (CSR_PERX_CSR_BASE + 0x18F4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_14_REG (CSR_PERX_CSR_BASE + 0x18F8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_15_REG (CSR_PERX_CSR_BASE + 0x18FC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1900) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1904) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_18_REG (CSR_PERX_CSR_BASE + 0x1908) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_19_REG (CSR_PERX_CSR_BASE + 0x190C) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_20_REG (CSR_PERX_CSR_BASE + 0x1910) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_21_REG (CSR_PERX_CSR_BASE + 0x1914) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CRDT_CNT_22_REG (CSR_PERX_CSR_BASE + 0x1918) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_IFIFO_CRDT_CNT_REG (CSR_PERX_CSR_BASE + 0x1988) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_CPB_CMDIDX_CRDT_CNT_REG (CSR_PERX_CSR_BASE + 0x19BC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_0_REG (CSR_PERX_CSR_BASE + 0x19C0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_1_REG (CSR_PERX_CSR_BASE + 0x19C4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_2_REG (CSR_PERX_CSR_BASE + 0x19C8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_3_REG (CSR_PERX_CSR_BASE + 0x19CC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_4_REG (CSR_PERX_CSR_BASE + 0x19D0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_5_REG (CSR_PERX_CSR_BASE + 0x19D4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_6_REG (CSR_PERX_CSR_BASE + 0x19D8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_7_REG (CSR_PERX_CSR_BASE + 0x19DC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_8_REG (CSR_PERX_CSR_BASE + 0x19E0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_9_REG (CSR_PERX_CSR_BASE + 0x19E4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_10_REG (CSR_PERX_CSR_BASE + 0x19E8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_11_REG (CSR_PERX_CSR_BASE + 0x19EC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_12_REG (CSR_PERX_CSR_BASE + 0x19F0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_13_REG (CSR_PERX_CSR_BASE + 0x19F4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_14_REG (CSR_PERX_CSR_BASE + 0x19F8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_15_REG (CSR_PERX_CSR_BASE + 0x19FC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1A00) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_DCRY_CYC_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1A04) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CRDT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x1AC0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CRDT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x1AC4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CRDT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x1AC8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_0_REG (CSR_PERX_CSR_BASE + 0x1BC0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_1_REG (CSR_PERX_CSR_BASE + 0x1BC4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_2_REG (CSR_PERX_CSR_BASE + 0x1BC8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_3_REG (CSR_PERX_CSR_BASE + 0x1BCC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_4_REG (CSR_PERX_CSR_BASE + 0x1BD0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_5_REG (CSR_PERX_CSR_BASE + 0x1BD4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_6_REG (CSR_PERX_CSR_BASE + 0x1BD8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_7_REG (CSR_PERX_CSR_BASE + 0x1BDC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_8_REG (CSR_PERX_CSR_BASE + 0x1BE0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_9_REG (CSR_PERX_CSR_BASE + 0x1BE4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_10_REG (CSR_PERX_CSR_BASE + 0x1BE8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_11_REG (CSR_PERX_CSR_BASE + 0x1BEC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_12_REG (CSR_PERX_CSR_BASE + 0x1BF0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_13_REG (CSR_PERX_CSR_BASE + 0x1BF4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_14_REG (CSR_PERX_CSR_BASE + 0x1BF8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_15_REG (CSR_PERX_CSR_BASE + 0x1BFC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1C00) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_DCRY_CYC_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1C04) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RTN_DCRY_CRDT_CNT_0_REG (CSR_PERX_CSR_BASE + 0x1CC0) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_DCRY_CRDT_CNT_1_REG (CSR_PERX_CSR_BASE + 0x1CC4) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_DCRY_CRDT_CNT_2_REG (CSR_PERX_CSR_BASE + 0x1CC8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_DCRY_IFIFO_CRDT_CNT_REG (CSR_PERX_CSR_BASE + 0x1DB8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_RTN_DCRY_CMDIDX_CRDT_CNT_REG (CSR_PERX_CSR_BASE + 0x1DBC) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_0_REG (CSR_PERX_CSR_BASE + 0x1DC0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_1_REG (CSR_PERX_CSR_BASE + 0x1DC4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_2_REG (CSR_PERX_CSR_BASE + 0x1DC8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_3_REG (CSR_PERX_CSR_BASE + 0x1DCC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_4_REG (CSR_PERX_CSR_BASE + 0x1DD0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_5_REG (CSR_PERX_CSR_BASE + 0x1DD4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_6_REG (CSR_PERX_CSR_BASE + 0x1DD8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_7_REG (CSR_PERX_CSR_BASE + 0x1DDC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_8_REG (CSR_PERX_CSR_BASE + 0x1DE0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_9_REG (CSR_PERX_CSR_BASE + 0x1DE4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_10_REG (CSR_PERX_CSR_BASE + 0x1DE8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_11_REG (CSR_PERX_CSR_BASE + 0x1DEC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_12_REG (CSR_PERX_CSR_BASE + 0x1DF0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_13_REG (CSR_PERX_CSR_BASE + 0x1DF4) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_14_REG (CSR_PERX_CSR_BASE + 0x1DF8) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_15_REG (CSR_PERX_CSR_BASE + 0x1DFC) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_16_REG (CSR_PERX_CSR_BASE + 0x1E00) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_17_REG (CSR_PERX_CSR_BASE + 0x1E04) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_18_REG (CSR_PERX_CSR_BASE + 0x1E08) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_CPI_CYC_CNT_19_REG (CSR_PERX_CSR_BASE + 0x1E0C) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_SNT_IPSURX_CYC_CNT_REG (CSR_PERX_CSR_BASE + 0x1EC0) /* 报文拍数计数器 */ +#define CSR_PERX_CSR_PERX_RCV_IPSURX_CRDT_CNT_REG (CSR_PERX_CSR_BASE + 0x1EC8) /* 信用计数器 */ +#define CSR_PERX_CSR_PERX_DGST_ERR_CNT_REG (CSR_PERX_CSR_BASE + 0x1ED0) /* Digest校验错误计数器 */ +#define CSR_PERX_CSR_PERX_SECTOR_GRD_ILGL_CNT_REG (CSR_PERX_CSR_BASE + 0x1ED8) /* 扇区guard域段校验错误计数器 */ +#define CSR_PERX_CSR_PERX_SECTOR_REF_ILGL_CNT_REG (CSR_PERX_CSR_BASE + 0x1EE0) /* 扇区REF域段校验错误计数器 */ +#define CSR_PERX_CSR_PERX_SECTOR_APP_ILGL_CNT_REG (CSR_PERX_CSR_BASE + 0x1EE8) /* 扇区APP域段校验错误计数器 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_DFX_CLR_REG (CSR_PERX_CSR_BASE + 0x1EF0) /* PERX DIF/DIX错误DFX清除寄存器 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_INFO_DW0_REG (CSR_PERX_CSR_BASE + 0x1EF8) /* PERX DIF/DIX错误信息 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_INFO_DW1_REG (CSR_PERX_CSR_BASE + 0x1F00) /* PERX DIF/DIX错误信息 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_INFO_DW2_REG (CSR_PERX_CSR_BASE + 0x1F08) /* PERX DIF/DIX错误信息 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_INFO_DW3_REG (CSR_PERX_CSR_BASE + 0x1F10) /* PERX DIF/DIX错误信息 */ +#define CSR_PERX_CSR_PERX_DIFX_ERR_INFO_DW4_REG (CSR_PERX_CSR_BASE + 0x1F18) /* PERX DIF/DIX错误信息 */ + +#endif // PE_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_c_union_define.h new file mode 100644 index 000000000..34ddfecbd --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_c_union_define.h @@ -0,0 +1,2091 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : pqm_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:57:27 Create file +// ****************************************************************************** + +#ifndef PQM_C_UNION_DEFINE_H +#define PQM_C_UNION_DEFINE_H + +/* Define the union csr_pqm_edition_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_edition_u; + +/* Define the union csr_pqm_initctab_start_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_wgt_initctab_start : 1; /* [0] */ + u32 pqm_shaper_initctab_start : 1; /* [1] */ + u32 pqm_sch_initctab_start : 1; /* [2] */ + u32 pqm_cfg_initctab_start : 1; /* [3] */ + u32 rsv_0 : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_initctab_start_u; + +/* Define the union csr_pqm_initctab_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_initctab_done : 1; /* [0] */ + u32 rsv_1 : 15; /* [15:1] */ + u32 pqm_wgt_init_done : 1; /* [16] */ + u32 pqm_shaper_init_done : 1; /* [17] */ + u32 pqm_sch_init_done : 1; /* [18] */ + u32 pqm_cfg_init_done : 1; /* [19] */ + u32 rsv_2 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_initctab_done_u; + +/* Define the union csr_pqm_cfg_ok_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_cfg_ok : 1; /* [0] */ + u32 rsv_3 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_cfg_ok_u; + +/* Define the union csr_pqm_initlogic_done_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_initlogic_done : 1; /* [0] */ + u32 rsv_4 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_initlogic_done_u; + +/* Define the union csr_mem_ecc_bypass_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ecc_bypass : 1; /* [0] */ + u32 rsv_5 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ecc_bypass_en_u; + +/* Define the union csr_mem_ctrl_bus_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ctrl_bus_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg0_u; + +/* Define the union csr_mem_ctrl_bus_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ctrl_bus_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg1_u; + +/* Define the union csr_mem_ctrl_bus_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ctrl_bus_2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg2_u; + +/* Define the union csr_mem_ctrl_bus_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ctrl_bus_3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg3_u; + +/* Define the union csr_mem_ctrl_bus_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_ctrl_bus_4 : 6; /* [5:0] */ + u32 rsv_6 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_mem_ctrl_bus_cfg4_u; + +/* Define the union csr_pqm_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_cpi_int_index : 24; /* [23:0] */ + u32 rsv_7 : 3; /* [26:24] */ + u32 pqm_enable : 1; /* [27] */ + u32 pqm_int_issue : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_int_vector_u; + +/* Define the union csr_pqm_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_int_data : 12; /* [11:0] */ + u32 rsv_9 : 4; /* [15:12] */ + u32 pqm_program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_int_u; + +/* Define the union csr_pqm_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_int_en : 12; /* [11:0] */ + u32 rsv_10 : 4; /* [15:12] */ + u32 pqm_program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_int_en_u; + +/* Define the union csr_pqm_mem_err_req0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_err_req_0 : 1; /* [0] */ + u32 pqm_mem_err_req_1 : 1; /* [1] */ + u32 pqm_mem_err_req_2 : 1; /* [2] */ + u32 pqm_mem_err_req_3 : 1; /* [3] */ + u32 pqm_mem_err_req_4 : 1; /* [4] */ + u32 pqm_mem_err_req_5 : 1; /* [5] */ + u32 pqm_mem_err_req_6 : 1; /* [6] */ + u32 pqm_mem_err_req_7 : 1; /* [7] */ + u32 pqm_mem_err_req_8 : 1; /* [8] */ + u32 pqm_mem_err_req_9 : 1; /* [9] */ + u32 pqm_mem_err_req_10 : 1; /* [10] */ + u32 pqm_mem_err_req_11 : 1; /* [11] */ + u32 pqm_mem_err_req_12 : 1; /* [12] */ + u32 pqm_mem_err_req_13 : 1; /* [13] */ + u32 pqm_mem_err_req_14 : 1; /* [14] */ + u32 pqm_mem_err_req_15 : 1; /* [15] */ + u32 pqm_mem_err_req_16 : 1; /* [16] */ + u32 pqm_mem_err_req_17 : 1; /* [17] */ + u32 pqm_mem_err_req_18 : 1; /* [18] */ + u32 pqm_mem_err_req_19 : 1; /* [19] */ + u32 pqm_mem_err_req_20 : 1; /* [20] */ + u32 pqm_mem_err_req_21 : 1; /* [21] */ + u32 pqm_mem_err_req_22 : 1; /* [22] */ + u32 pqm_mem_err_req_23 : 1; /* [23] */ + u32 pqm_mem_err_req_24 : 1; /* [24] */ + u32 pqm_mem_err_req_25 : 1; /* [25] */ + u32 pqm_mem_err_req_26 : 1; /* [26] */ + u32 pqm_mem_err_req_27 : 1; /* [27] */ + u32 pqm_mem_err_req_28 : 1; /* [28] */ + u32 pqm_mem_err_req_29 : 1; /* [29] */ + u32 pqm_mem_err_req_30 : 1; /* [30] */ + u32 pqm_mem_err_req_31 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mem_err_req0_u; + +/* Define the union csr_pqm_mem_err_req1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_err_req_32 : 1; /* [0] */ + u32 pqm_mem_err_req_33 : 1; /* [1] */ + u32 pqm_mem_err_req_34 : 1; /* [2] */ + u32 pqm_mem_err_req_35 : 1; /* [3] */ + u32 pqm_mem_err_req_36 : 1; /* [4] */ + u32 pqm_mem_err_req_37 : 1; /* [5] */ + u32 pqm_mem_err_req_38 : 1; /* [6] */ + u32 pqm_mem_err_req_39 : 1; /* [7] */ + u32 pqm_mem_err_req_40 : 1; /* [8] */ + u32 pqm_mem_err_req_41 : 1; /* [9] */ + u32 pqm_mem_err_req_42 : 1; /* [10] */ + u32 pqm_mem_err_req_43 : 1; /* [11] */ + u32 pqm_mem_err_req_44 : 1; /* [12] */ + u32 pqm_mem_err_req_45 : 1; /* [13] */ + u32 pqm_mem_err_req_46 : 1; /* [14] */ + u32 pqm_mem_err_req_47 : 1; /* [15] */ + u32 pqm_mem_err_req_48 : 1; /* [16] */ + u32 pqm_mem_err_req_49 : 1; /* [17] */ + u32 pqm_mem_err_req_50 : 1; /* [18] */ + u32 pqm_mem_err_req_51 : 1; /* [19] */ + u32 pqm_mem_err_req_52 : 1; /* [20] */ + u32 pqm_mem_err_req_53 : 1; /* [21] */ + u32 pqm_mem_err_req_54 : 1; /* [22] */ + u32 pqm_mem_err_req_55 : 1; /* [23] */ + u32 pqm_mem_err_req_56 : 1; /* [24] */ + u32 pqm_mem_err_req_57 : 1; /* [25] */ + u32 pqm_mem_err_req_58 : 1; /* [26] */ + u32 pqm_mem_err_req_59 : 1; /* [27] */ + u32 rsv_11 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mem_err_req1_u; + +/* Define the union csr_pqm_mem_err_req2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_err_req_64 : 1; /* [0] */ + u32 pqm_mem_err_req_65 : 1; /* [1] */ + u32 pqm_mem_err_req_66 : 1; /* [2] */ + u32 pqm_mem_err_req_67 : 1; /* [3] */ + u32 pqm_mem_err_req_68 : 1; /* [4] */ + u32 pqm_mem_err_req_69 : 1; /* [5] */ + u32 pqm_mem_err_req_70 : 1; /* [6] */ + u32 pqm_mem_err_req_71 : 1; /* [7] */ + u32 pqm_mem_err_req_72 : 1; /* [8] */ + u32 pqm_mem_err_req_73 : 1; /* [9] */ + u32 pqm_mem_err_req_74 : 1; /* [10] */ + u32 pqm_mem_err_req_75 : 1; /* [11] */ + u32 pqm_mem_err_req_76 : 1; /* [12] */ + u32 pqm_mem_err_req_77 : 1; /* [13] */ + u32 pqm_mem_err_req_78 : 1; /* [14] */ + u32 pqm_mem_err_req_79 : 1; /* [15] */ + u32 pqm_mem_err_req_80 : 1; /* [16] */ + u32 pqm_mem_err_req_81 : 1; /* [17] */ + u32 pqm_mem_err_req_82 : 1; /* [18] */ + u32 pqm_mem_err_req_83 : 1; /* [19] */ + u32 pqm_mem_err_req_84 : 1; /* [20] */ + u32 pqm_mem_err_req_85 : 1; /* [21] */ + u32 pqm_mem_err_req_86 : 1; /* [22] */ + u32 pqm_mem_err_req_87 : 1; /* [23] */ + u32 pqm_mem_err_req_88 : 1; /* [24] */ + u32 pqm_mem_err_req_89 : 1; /* [25] */ + u32 pqm_mem_err_req_90 : 1; /* [26] */ + u32 pqm_mem_err_req_91 : 1; /* [27] */ + u32 pqm_mem_err_req_92 : 1; /* [28] */ + u32 pqm_mem_err_req_93 : 1; /* [29] */ + u32 pqm_mem_err_req_94 : 1; /* [30] */ + u32 pqm_mem_err_req_95 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mem_err_req2_u; + +/* Define the union csr_pqm_mem_err_req3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mem_err_req_96 : 1; /* [0] */ + u32 pqm_mem_err_req_97 : 1; /* [1] */ + u32 pqm_mem_err_req_98 : 1; /* [2] */ + u32 pqm_mem_err_req_99 : 1; /* [3] */ + u32 pqm_mem_err_req_100 : 1; /* [4] */ + u32 pqm_mem_err_req_101 : 1; /* [5] */ + u32 pqm_mem_err_req_102 : 1; /* [6] */ + u32 pqm_mem_err_req_103 : 1; /* [7] */ + u32 pqm_mem_err_req_104 : 1; /* [8] */ + u32 pqm_mem_err_req_105 : 1; /* [9] */ + u32 pqm_mem_err_req_106 : 1; /* [10] */ + u32 pqm_mem_err_req_107 : 1; /* [11] */ + u32 pqm_mem_err_req_108 : 1; /* [12] */ + u32 pqm_mem_err_req_109 : 1; /* [13] */ + u32 pqm_mem_err_req_110 : 1; /* [14] */ + u32 pqm_mem_err_req_111 : 1; /* [15] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mem_err_req3_u; + +/* Define the union csr_pqm_ecc_one_bit_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ecc_1bit_err : 1; /* [0] */ + u32 pqm_ecc_1bit_err_insrt : 1; /* [1] */ + u32 pqm_ecc_1bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_ecc_one_bit_int_u; + +/* Define the union csr_pqm_ecc_two_bit_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ecc_2bit_err : 1; /* [0] */ + u32 pqm_ecc_2bit_err_insrt : 1; /* [1] */ + u32 pqm_ecc_2bit_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_ecc_two_bit_int_u; + +/* Define the union csr_pqm_mq_bind_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_bind_cfg_err : 1; /* [0] */ + u32 pqm_bind_cfg_err_insrt : 1; /* [1] */ + u32 pqm_bind_cfg_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mq_bind_int_u; + +/* Define the union csr_pqm_mq_bind_mcd_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mcd_bind_cfg_err : 1; /* [0] */ + u32 pqm_mcd_bind_cfg_err_insrt : 1; /* [1] */ + u32 pqm_mcd_bind_cfg_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mq_bind_mcd_int_u; + +/* Define the union csr_pqm_fifo_int0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int0_err0 : 1; /* [0] */ + u32 pqm_fifo_int0_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int0_err1 : 1; /* [2] */ + u32 pqm_fifo_int0_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int0_err2 : 1; /* [4] */ + u32 pqm_fifo_int0_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int0_err3 : 1; /* [6] */ + u32 pqm_fifo_int0_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int0_err4 : 1; /* [8] */ + u32 pqm_fifo_int0_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int0_err5 : 1; /* [10] */ + u32 pqm_fifo_int0_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int0_err6 : 1; /* [12] */ + u32 pqm_fifo_int0_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int0_err7 : 1; /* [14] */ + u32 pqm_fifo_int0_err7_insrt : 1; /* [15] */ + u32 pqm_fifo_int0_err8 : 1; /* [16] */ + u32 pqm_fifo_int0_err8_insrt : 1; /* [17] */ + u32 pqm_fifo_int0_err9 : 1; /* [18] */ + u32 pqm_fifo_int0_err9_insrt : 1; /* [19] */ + u32 rsv_13 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int0_u; + +/* Define the union csr_pqm_fifo_int0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int0_err0_en : 1; /* [0] */ + u32 pqm_fifo_int0_err1_en : 1; /* [1] */ + u32 pqm_fifo_int0_err2_en : 1; /* [2] */ + u32 pqm_fifo_int0_err3_en : 1; /* [3] */ + u32 pqm_fifo_int0_err4_en : 1; /* [4] */ + u32 pqm_fifo_int0_err5_en : 1; /* [5] */ + u32 pqm_fifo_int0_err6_en : 1; /* [6] */ + u32 pqm_fifo_int0_err7_en : 1; /* [7] */ + u32 pqm_fifo_int0_err8_en : 1; /* [8] */ + u32 pqm_fifo_int0_err9_en : 1; /* [9] */ + u32 rsv_14 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int0_mask_u; + +/* Define the union csr_pqm_fifo_int1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int1_err0 : 1; /* [0] */ + u32 pqm_fifo_int1_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int1_err1 : 1; /* [2] */ + u32 pqm_fifo_int1_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int1_err2 : 1; /* [4] */ + u32 pqm_fifo_int1_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int1_err3 : 1; /* [6] */ + u32 pqm_fifo_int1_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int1_err4 : 1; /* [8] */ + u32 pqm_fifo_int1_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int1_err5 : 1; /* [10] */ + u32 pqm_fifo_int1_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int1_err6 : 1; /* [12] */ + u32 pqm_fifo_int1_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int1_err7 : 1; /* [14] */ + u32 pqm_fifo_int1_err7_insrt : 1; /* [15] */ + u32 pqm_fifo_int1_err8 : 1; /* [16] */ + u32 pqm_fifo_int1_err8_insrt : 1; /* [17] */ + u32 pqm_fifo_int1_err9 : 1; /* [18] */ + u32 pqm_fifo_int1_err9_insrt : 1; /* [19] */ + u32 pqm_fifo_int1_err10 : 1; /* [20] */ + u32 pqm_fifo_int1_err10_insrt : 1; /* [21] */ + u32 pqm_fifo_int1_err11 : 1; /* [22] */ + u32 pqm_fifo_int1_err11_insrt : 1; /* [23] */ + u32 pqm_fifo_int1_err12 : 1; /* [24] */ + u32 pqm_fifo_int1_err12_insrt : 1; /* [25] */ + u32 pqm_fifo_int1_err13 : 1; /* [26] */ + u32 pqm_fifo_int1_err13_insrt : 1; /* [27] */ + u32 pqm_fifo_int1_err14 : 1; /* [28] */ + u32 pqm_fifo_int1_err14_insrt : 1; /* [29] */ + u32 pqm_fifo_int1_err15 : 1; /* [30] */ + u32 pqm_fifo_int1_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int1_u; + +/* Define the union csr_pqm_fifo_int1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int1_err0_en : 1; /* [0] */ + u32 pqm_fifo_int1_err1_en : 1; /* [1] */ + u32 pqm_fifo_int1_err2_en : 1; /* [2] */ + u32 pqm_fifo_int1_err3_en : 1; /* [3] */ + u32 pqm_fifo_int1_err4_en : 1; /* [4] */ + u32 pqm_fifo_int1_err5_en : 1; /* [5] */ + u32 pqm_fifo_int1_err6_en : 1; /* [6] */ + u32 pqm_fifo_int1_err7_en : 1; /* [7] */ + u32 pqm_fifo_int1_err8_en : 1; /* [8] */ + u32 pqm_fifo_int1_err9_en : 1; /* [9] */ + u32 pqm_fifo_int1_err10_en : 1; /* [10] */ + u32 pqm_fifo_int1_err11_en : 1; /* [11] */ + u32 pqm_fifo_int1_err12_en : 1; /* [12] */ + u32 pqm_fifo_int1_err13_en : 1; /* [13] */ + u32 pqm_fifo_int1_err14_en : 1; /* [14] */ + u32 pqm_fifo_int1_err15_en : 1; /* [15] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int1_mask_u; + +/* Define the union csr_pqm_fifo_int2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int2_err0 : 1; /* [0] */ + u32 pqm_fifo_int2_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int2_err1 : 1; /* [2] */ + u32 pqm_fifo_int2_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int2_err2 : 1; /* [4] */ + u32 pqm_fifo_int2_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int2_err3 : 1; /* [6] */ + u32 pqm_fifo_int2_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int2_err4 : 1; /* [8] */ + u32 pqm_fifo_int2_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int2_err5 : 1; /* [10] */ + u32 pqm_fifo_int2_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int2_err6 : 1; /* [12] */ + u32 pqm_fifo_int2_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int2_err7 : 1; /* [14] */ + u32 pqm_fifo_int2_err7_insrt : 1; /* [15] */ + u32 pqm_fifo_int2_err8 : 1; /* [16] */ + u32 pqm_fifo_int2_err8_insrt : 1; /* [17] */ + u32 pqm_fifo_int2_err9 : 1; /* [18] */ + u32 pqm_fifo_int2_err9_insrt : 1; /* [19] */ + u32 pqm_fifo_int2_err10 : 1; /* [20] */ + u32 pqm_fifo_int2_err10_insrt : 1; /* [21] */ + u32 pqm_fifo_int2_err11 : 1; /* [22] */ + u32 pqm_fifo_int2_err11_insrt : 1; /* [23] */ + u32 pqm_fifo_int2_err12 : 1; /* [24] */ + u32 pqm_fifo_int2_err12_insrt : 1; /* [25] */ + u32 pqm_fifo_int2_err13 : 1; /* [26] */ + u32 pqm_fifo_int2_err13_insrt : 1; /* [27] */ + u32 pqm_fifo_int2_err14 : 1; /* [28] */ + u32 pqm_fifo_int2_err14_insrt : 1; /* [29] */ + u32 pqm_fifo_int2_err15 : 1; /* [30] */ + u32 pqm_fifo_int2_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int2_u; + +/* Define the union csr_pqm_fifo_int2_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int2_err0_en : 1; /* [0] */ + u32 pqm_fifo_int2_err1_en : 1; /* [1] */ + u32 pqm_fifo_int2_err2_en : 1; /* [2] */ + u32 pqm_fifo_int2_err3_en : 1; /* [3] */ + u32 pqm_fifo_int2_err4_en : 1; /* [4] */ + u32 pqm_fifo_int2_err5_en : 1; /* [5] */ + u32 pqm_fifo_int2_err6_en : 1; /* [6] */ + u32 pqm_fifo_int2_err7_en : 1; /* [7] */ + u32 pqm_fifo_int2_err8_en : 1; /* [8] */ + u32 pqm_fifo_int2_err9_en : 1; /* [9] */ + u32 pqm_fifo_int2_err10_en : 1; /* [10] */ + u32 pqm_fifo_int2_err11_en : 1; /* [11] */ + u32 pqm_fifo_int2_err12_en : 1; /* [12] */ + u32 pqm_fifo_int2_err13_en : 1; /* [13] */ + u32 pqm_fifo_int2_err14_en : 1; /* [14] */ + u32 pqm_fifo_int2_err15_en : 1; /* [15] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int2_mask_u; + +/* Define the union csr_pqm_fifo_int3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int3_err0 : 1; /* [0] */ + u32 pqm_fifo_int3_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int3_err1 : 1; /* [2] */ + u32 pqm_fifo_int3_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int3_err2 : 1; /* [4] */ + u32 pqm_fifo_int3_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int3_err3 : 1; /* [6] */ + u32 pqm_fifo_int3_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int3_err4 : 1; /* [8] */ + u32 pqm_fifo_int3_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int3_err5 : 1; /* [10] */ + u32 pqm_fifo_int3_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int3_err6 : 1; /* [12] */ + u32 pqm_fifo_int3_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int3_err7 : 1; /* [14] */ + u32 pqm_fifo_int3_err7_insrt : 1; /* [15] */ + u32 pqm_fifo_int3_err8 : 1; /* [16] */ + u32 pqm_fifo_int3_err8_insrt : 1; /* [17] */ + u32 pqm_fifo_int3_err9 : 1; /* [18] */ + u32 pqm_fifo_int3_err9_insrt : 1; /* [19] */ + u32 pqm_fifo_int3_err10 : 1; /* [20] */ + u32 pqm_fifo_int3_err10_insrt : 1; /* [21] */ + u32 pqm_fifo_int3_err11 : 1; /* [22] */ + u32 pqm_fifo_int3_err11_insrt : 1; /* [23] */ + u32 pqm_fifo_int3_err12 : 1; /* [24] */ + u32 pqm_fifo_int3_err12_insrt : 1; /* [25] */ + u32 pqm_fifo_int3_err13 : 1; /* [26] */ + u32 pqm_fifo_int3_err13_insrt : 1; /* [27] */ + u32 pqm_fifo_int3_err14 : 1; /* [28] */ + u32 pqm_fifo_int3_err14_insrt : 1; /* [29] */ + u32 pqm_fifo_int3_err15 : 1; /* [30] */ + u32 pqm_fifo_int3_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int3_u; + +/* Define the union csr_pqm_fifo_int3_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int3_err0_en : 1; /* [0] */ + u32 pqm_fifo_int3_err1_en : 1; /* [1] */ + u32 pqm_fifo_int3_err2_en : 1; /* [2] */ + u32 pqm_fifo_int3_err3_en : 1; /* [3] */ + u32 pqm_fifo_int3_err4_en : 1; /* [4] */ + u32 pqm_fifo_int3_err5_en : 1; /* [5] */ + u32 pqm_fifo_int3_err6_en : 1; /* [6] */ + u32 pqm_fifo_int3_err7_en : 1; /* [7] */ + u32 pqm_fifo_int3_err8_en : 1; /* [8] */ + u32 pqm_fifo_int3_err9_en : 1; /* [9] */ + u32 pqm_fifo_int3_err10_en : 1; /* [10] */ + u32 pqm_fifo_int3_err11_en : 1; /* [11] */ + u32 pqm_fifo_int3_err12_en : 1; /* [12] */ + u32 pqm_fifo_int3_err13_en : 1; /* [13] */ + u32 pqm_fifo_int3_err14_en : 1; /* [14] */ + u32 pqm_fifo_int3_err15_en : 1; /* [15] */ + u32 rsv_17 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int3_mask_u; + +/* Define the union csr_pqm_fifo_int4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int4_err0 : 1; /* [0] */ + u32 pqm_fifo_int4_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int4_err1 : 1; /* [2] */ + u32 pqm_fifo_int4_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int4_err2 : 1; /* [4] */ + u32 pqm_fifo_int4_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int4_err3 : 1; /* [6] */ + u32 pqm_fifo_int4_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int4_err4 : 1; /* [8] */ + u32 pqm_fifo_int4_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int4_err5 : 1; /* [10] */ + u32 pqm_fifo_int4_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int4_err6 : 1; /* [12] */ + u32 pqm_fifo_int4_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int4_err7 : 1; /* [14] */ + u32 pqm_fifo_int4_err7_insrt : 1; /* [15] */ + u32 pqm_fifo_int4_err8 : 1; /* [16] */ + u32 pqm_fifo_int4_err8_insrt : 1; /* [17] */ + u32 pqm_fifo_int4_err9 : 1; /* [18] */ + u32 pqm_fifo_int4_err9_insrt : 1; /* [19] */ + u32 pqm_fifo_int4_err10 : 1; /* [20] */ + u32 pqm_fifo_int4_err10_insrt : 1; /* [21] */ + u32 pqm_fifo_int4_err11 : 1; /* [22] */ + u32 pqm_fifo_int4_err11_insrt : 1; /* [23] */ + u32 pqm_fifo_int4_err12 : 1; /* [24] */ + u32 pqm_fifo_int4_err12_insrt : 1; /* [25] */ + u32 pqm_fifo_int4_err13 : 1; /* [26] */ + u32 pqm_fifo_int4_err13_insrt : 1; /* [27] */ + u32 pqm_fifo_int4_err14 : 1; /* [28] */ + u32 pqm_fifo_int4_err14_insrt : 1; /* [29] */ + u32 pqm_fifo_int4_err15 : 1; /* [30] */ + u32 pqm_fifo_int4_err15_insrt : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int4_u; + +/* Define the union csr_pqm_fifo_int4_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int4_err0_en : 1; /* [0] */ + u32 pqm_fifo_int4_err1_en : 1; /* [1] */ + u32 pqm_fifo_int4_err2_en : 1; /* [2] */ + u32 pqm_fifo_int4_err3_en : 1; /* [3] */ + u32 pqm_fifo_int4_err4_en : 1; /* [4] */ + u32 pqm_fifo_int4_err5_en : 1; /* [5] */ + u32 pqm_fifo_int4_err6_en : 1; /* [6] */ + u32 pqm_fifo_int4_err7_en : 1; /* [7] */ + u32 pqm_fifo_int4_err8_en : 1; /* [8] */ + u32 pqm_fifo_int4_err9_en : 1; /* [9] */ + u32 pqm_fifo_int4_err10_en : 1; /* [10] */ + u32 pqm_fifo_int4_err11_en : 1; /* [11] */ + u32 pqm_fifo_int4_err12_en : 1; /* [12] */ + u32 pqm_fifo_int4_err13_en : 1; /* [13] */ + u32 pqm_fifo_int4_err14_en : 1; /* [14] */ + u32 pqm_fifo_int4_err15_en : 1; /* [15] */ + u32 rsv_18 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int4_mask_u; + +/* Define the union csr_pqm_fifo_int5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int5_err0 : 1; /* [0] */ + u32 pqm_fifo_int5_err0_insrt : 1; /* [1] */ + u32 pqm_fifo_int5_err1 : 1; /* [2] */ + u32 pqm_fifo_int5_err1_insrt : 1; /* [3] */ + u32 pqm_fifo_int5_err2 : 1; /* [4] */ + u32 pqm_fifo_int5_err2_insrt : 1; /* [5] */ + u32 pqm_fifo_int5_err3 : 1; /* [6] */ + u32 pqm_fifo_int5_err3_insrt : 1; /* [7] */ + u32 pqm_fifo_int5_err4 : 1; /* [8] */ + u32 pqm_fifo_int5_err4_insrt : 1; /* [9] */ + u32 pqm_fifo_int5_err5 : 1; /* [10] */ + u32 pqm_fifo_int5_err5_insrt : 1; /* [11] */ + u32 pqm_fifo_int5_err6 : 1; /* [12] */ + u32 pqm_fifo_int5_err6_insrt : 1; /* [13] */ + u32 pqm_fifo_int5_err7 : 1; /* [14] */ + u32 pqm_fifo_int5_err7_insrt : 1; /* [15] */ + u32 rsv_19 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int5_u; + +/* Define the union csr_pqm_fifo_int5_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo_int5_err0_en : 1; /* [0] */ + u32 pqm_fifo_int5_err1_en : 1; /* [1] */ + u32 pqm_fifo_int5_err2_en : 1; /* [2] */ + u32 pqm_fifo_int5_err3_en : 1; /* [3] */ + u32 pqm_fifo_int5_err4_en : 1; /* [4] */ + u32 pqm_fifo_int5_err5_en : 1; /* [5] */ + u32 pqm_fifo_int5_err6_en : 1; /* [6] */ + u32 pqm_fifo_int5_err7_en : 1; /* [7] */ + u32 rsv_20 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_int5_mask_u; + +/* Define the union csr_pqm_rx_ring_e0_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ring_e0_err : 1; /* [0] */ + u32 pqm_ring_e0_err_insert : 1; /* [1] */ + u32 pqm_ring_e0_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rx_ring_e0_err_int_u; + +/* Define the union csr_pqm_rx_ring_e1_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ring_e1_err : 1; /* [0] */ + u32 pqm_ring_e1_err_insert : 1; /* [1] */ + u32 pqm_ring_e1_err_info : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rx_ring_e1_err_int_u; + +/* Define the union csr_pqm_fifo_st0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo0_st0 : 2; /* [1:0] */ + u32 pqm_fifo1_st0 : 2; /* [3:2] */ + u32 pqm_fifo2_st0 : 2; /* [5:4] */ + u32 pqm_fifo3_st0 : 2; /* [7:6] */ + u32 pqm_fifo4_st0 : 2; /* [9:8] */ + u32 pqm_fifo5_st0 : 2; /* [11:10] */ + u32 pqm_fifo6_st0 : 2; /* [13:12] */ + u32 pqm_fifo7_st0 : 2; /* [15:14] */ + u32 pqm_fifo8_st0 : 2; /* [17:16] */ + u32 pqm_fifo9_st0 : 2; /* [19:18] */ + u32 pqm_fifo10_st0 : 2; /* [21:20] */ + u32 pqm_fifo11_st0 : 2; /* [23:22] */ + u32 pqm_fifo12_st0 : 2; /* [25:24] */ + u32 rsv_21 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_st0_u; + +/* Define the union csr_pqm_fifo_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo0_st1 : 2; /* [1:0] */ + u32 pqm_fifo1_st1 : 2; /* [3:2] */ + u32 pqm_fifo2_st1 : 2; /* [5:4] */ + u32 pqm_fifo3_st1 : 2; /* [7:6] */ + u32 pqm_fifo4_st1 : 2; /* [9:8] */ + u32 pqm_fifo5_st1 : 2; /* [11:10] */ + u32 pqm_fifo6_st1 : 2; /* [13:12] */ + u32 pqm_fifo7_st1 : 2; /* [15:14] */ + u32 pqm_fifo8_st1 : 2; /* [17:16] */ + u32 pqm_fifo9_st1 : 2; /* [19:18] */ + u32 pqm_fifo10_st1 : 2; /* [21:20] */ + u32 pqm_fifo11_st1 : 2; /* [23:22] */ + u32 pqm_fifo12_st1 : 2; /* [25:24] */ + u32 pqm_fifo13_st1 : 2; /* [27:26] */ + u32 pqm_fifo14_st1 : 2; /* [29:28] */ + u32 pqm_fifo15_st1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_st1_u; + +/* Define the union csr_pqm_fifo_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_fifo0_st2 : 2; /* [1:0] */ + u32 pqm_fifo1_st2 : 2; /* [3:2] */ + u32 pqm_fifo2_st2 : 2; /* [5:4] */ + u32 pqm_fifo3_st2 : 2; /* [7:6] */ + u32 pqm_fifo4_st2 : 2; /* [9:8] */ + u32 pqm_fifo5_st2 : 2; /* [11:10] */ + u32 pqm_fifo6_st2 : 2; /* [13:12] */ + u32 pqm_fifo7_st2 : 2; /* [15:14] */ + u32 pqm_fifo8_st2 : 2; /* [17:16] */ + u32 pqm_fifo9_st2 : 2; /* [19:18] */ + u32 pqm_fifo10_st2 : 2; /* [21:20] */ + u32 pqm_fifo11_st2 : 2; /* [23:22] */ + u32 rsv_22 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_st2_u; + +/* Define the union csr_pqm_rw_rsv0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_rw_rsv0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rw_rsv0_u; + +/* Define the union csr_pqm_rw_rsv1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_rw_rsv1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rw_rsv1_u; + +/* Define the union csr_pqm_rw_rsv2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_rw_rsv2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rw_rsv2_u; + +/* Define the union csr_pqm_rw_rsv3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_rw_rsv3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_rw_rsv3_u; + +/* Define the union csr_pqm_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_indrect_addr : 20; /* [19:0] */ + u32 pqm_indrect_tab : 8; /* [27:20] */ + u32 pqm_indrect_stat : 2; /* [29:28] */ + u32 pqm_indrect_mode : 1; /* [30] */ + u32 pqm_indrect_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_indrect_ctrl_u; + +/* Define the union csr_pqm_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_indrect_timeout_u; + +/* Define the union csr_pqm_indrect_data_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_indrect_data_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_indrect_data_0_u; + +/* Define the union csr_pqm_indrect_data_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_indrect_data_1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_indrect_data_1_u; + +/* Define the union csr_pqm_pass_through_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_passthru_enable : 1; /* [0] */ + u32 rsv_23 : 7; /* [7:1] */ + u32 pqm_passthru_wgt_cfg : 3; /* [10:8] */ + u32 rsv_24 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_pass_through_cfg_u; + +/* Define the union csr_pqm_weight_offset_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_cos_weight_offset : 5; /* [4:0] */ + u32 rsv_25 : 3; /* [7:5] */ + u32 pqm_ep_weight_offset : 5; /* [12:8] */ + u32 rsv_26 : 3; /* [15:13] */ + u32 pqm_host_weight_offset : 5; /* [20:16] */ + u32 rsv_27 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_weight_offset_u; + +/* Define the union csr_pqm_pps_shaper_cfg_pktlen_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_pps_typical_pktlen_cfg : 3; /* [2:0] */ + u32 rsv_28 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_pps_shaper_cfg_pktlen_u; + +/* Define the union csr_pqm_root_sch_weight_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_root_sch_wgt_cfg : 3; /* [2:0] */ + u32 rsv_29 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_root_sch_weight_cfg_u; + +/* Define the union csr_host_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_weight_cfg : 8; /* [7:0] */ + u32 rsv_30 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_weight_u; + +/* Define the union csr_host_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_31 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_bps_cfg_u; + +/* Define the union csr_host_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 host_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_32 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_host_shap_pps_cfg_u; + +/* Define the union csr_ep_weight_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_weight_cfg : 8; /* [7:0] */ + u32 rsv_33 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_weight_u; + +/* Define the union csr_ep_shap_bps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_bps_cfg : 25; /* [24:0] */ + u32 rsv_34 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_bps_cfg_u; + +/* Define the union csr_ep_shap_pps_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ep_shap_pps_cfg : 25; /* [24:0] */ + u32 rsv_35 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_ep_shap_pps_cfg_u; + +/* Define the union csr_pqm_shap_bypass_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_nmq_shap_byp_vld : 1; /* [0] */ + u32 pqm_vnic_shap_byp_vld : 1; /* [1] */ + u32 pqm_vnicgrp_shap_byp_vld : 1; /* [2] */ + u32 pqm_ep_shap_byp_vld : 1; /* [3] */ + u32 pqm_host_shap_byp_vld : 1; /* [4] */ + u32 rsv_36 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_shap_bypass_cfg_u; + +/* Define the union csr_pqm_host_ep_xon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_hostep_xon_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_host_ep_xon_cfg_u; + +/* Define the union csr_pqm_host_xon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_xon_cfg : 4; /* [3:0] */ + u32 msc_root_xon_cfg : 1; /* [4] */ + u32 rsv_37 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_host_xon_cfg_u; + +/* Define the union csr_pqm_host_ep_bps_spf_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_hostep_bps_spf_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_host_ep_bps_spf_st_u; + +/* Define the union csr_pqm_host_ep_pps_spf_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_hostep_pps_spf_st : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_host_ep_pps_spf_st_u; + +/* Define the union csr_pqm_host_spf_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 msc_host_bps_spf_st : 4; /* [3:0] */ + u32 msc_host_pps_spf_st : 4; /* [7:4] */ + u32 rsv_38 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_host_spf_st_u; + +/* Define the union csr_pqm_sch_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_host_bp : 4; /* [3:0] */ + u32 pqm_scan_bp : 1; /* [4] */ + u32 rsv_39 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_sch_bp_sta_u; + +/* Define the union csr_pqm_sch_ep_bp_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ep_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_sch_ep_bp_sta_u; + +/* Define the union csr_pqm_fifo_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_du_fifo_gap : 5; /* [4:0] */ + u32 rsv_40 : 3; /* [7:5] */ + u32 pqm_pt_fifo_gap : 5; /* [12:8] */ + u32 rsv_41 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_fifo_th_cfg_u; + +/* Define the union csr_pqm_dpl_info_ptr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_dpl_plen : 16; /* [15:0] */ + u32 pqm_dpl_pnum : 4; /* [19:16] */ + u32 rsv_42 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_dpl_info_ptr0_u; + +/* Define the union csr_pqm_dpl_info_ptr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_dpl_pqid : 14; /* [13:0] */ + u32 rsv_43 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_dpl_info_ptr1_u; + +/* Define the union csr_pqm_mcd_du_info_ptr0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mcd_plen : 19; /* [18:0] */ + u32 rsv_44 : 5; /* [23:19] */ + u32 pqm_mcd_pnum : 5; /* [28:24] */ + u32 rsv_45 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mcd_du_info_ptr0_u; + +/* Define the union csr_pqm_mcd_du_info_ptr1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_mcd_pqid : 14; /* [13:0] */ + u32 rsv_46 : 2; /* [15:14] */ + u32 pqm_mcd_color : 3; /* [18:16] */ + u32 rsv_47 : 13; /* [31:19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_mcd_du_info_ptr1_u; + +/* Define the union csr_pqm_uncrt_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_uncrt_err_mask : 1; /* [0] */ + u32 other_uncrt_err_mask : 1; /* [1] */ + u32 rsv_48 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_uncrt_err_mask_u; + +/* Define the union csr_pqm_uncrt_err_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ram_uncrt_err_clr : 1; /* [0] */ + u32 other_uncrt_err_clr : 1; /* [1] */ + u32 rsv_49 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_uncrt_err_clr_u; + +/* Define the union csr_pq_eqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_eqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_eqs_cnt_u; + +/* Define the union csr_pq_dqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_dqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_dqs_cnt_u; + +/* Define the union csr_pq_empt_dqs_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_empt_dqs_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_empt_dqs_cnt_u; + +/* Define the union csr_pq_sch_dqr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_sch_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_sch_dqr_cnt_u; + +/* Define the union csr_pq_sch_empt_dqr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_sch_empt_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_sch_empt_dqr_cnt_u; + +/* Define the union csr_pq_pt_dqr_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_pt_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_pt_dqr_cnt_u; + +/* Define the union csr_pq_dpl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_dpl_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_dpl_cnt_u; + +/* Define the union csr_pq_du_vld_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_du_info_vld_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_du_vld_cnt_u; + +/* Define the union csr_pq_du_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_du_info_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pq_du_err_cnt_u; + +/* Define the union csr_pqm_ecc_1bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ecc_1bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_ecc_1bit_err_cnt_u; + +/* Define the union csr_pqm_ecc_2bit_err_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pqm_ecc_2bit_err_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_pqm_ecc_2bit_err_cnt_u; + +/* Define the union csr_sch_pq_dfx_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_cfg : 14; /* [13:0] */ + u32 rsv_50 : 2; /* [15:14] */ + u32 sch_pq_dfx_cfg_vld : 1; /* [16] */ + u32 rsv_51 : 15; /* [31:17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_cfg_u; + +/* Define the union csr_sch_pq_dfx_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_up_cnt_u; + +/* Define the union csr_sch_pq_dfx_empt_up_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_empt_up_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_empt_up_cnt_u; + +/* Define the union csr_sch_pq_dfx_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_sch_cnt_u; + +/* Define the union csr_sch_pq_dfx_pt_deq_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_pt_dqr_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_pt_deq_cnt_u; + +/* Define the union csr_sch_pq_dfx_empt_sch_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_empt_sch_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_empt_sch_cnt_u; + +/* Define the union csr_sch_pq_dfx_du_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sch_pq_dfx_du_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sch_pq_dfx_du_cnt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_pqm_edition_u pqm_edition; /* 0 */ + volatile csr_pqm_initctab_start_u pqm_initctab_start; /* 4 */ + volatile csr_pqm_initctab_done_u pqm_initctab_done; /* 8 */ + volatile csr_pqm_cfg_ok_u pqm_cfg_ok; /* C */ + volatile csr_pqm_initlogic_done_u pqm_initlogic_done; /* 10 */ + volatile csr_mem_ecc_bypass_en_u mem_ecc_bypass_en; /* 14 */ + volatile csr_mem_ctrl_bus_cfg0_u mem_ctrl_bus_cfg0; /* 18 */ + volatile csr_mem_ctrl_bus_cfg1_u mem_ctrl_bus_cfg1; /* 1C */ + volatile csr_mem_ctrl_bus_cfg2_u mem_ctrl_bus_cfg2; /* 20 */ + volatile csr_mem_ctrl_bus_cfg3_u mem_ctrl_bus_cfg3; /* 24 */ + volatile csr_mem_ctrl_bus_cfg4_u mem_ctrl_bus_cfg4; /* 28 */ + volatile csr_pqm_int_vector_u pqm_int_vector; /* 100 */ + volatile csr_pqm_int_u pqm_int; /* 104 */ + volatile csr_pqm_int_en_u pqm_int_en; /* 108 */ + volatile csr_pqm_mem_err_req0_u pqm_mem_err_req0; /* 10C */ + volatile csr_pqm_mem_err_req1_u pqm_mem_err_req1; /* 110 */ + volatile csr_pqm_mem_err_req2_u pqm_mem_err_req2; /* 114 */ + volatile csr_pqm_mem_err_req3_u pqm_mem_err_req3; /* 118 */ + volatile csr_pqm_ecc_one_bit_int_u pqm_ecc_one_bit_int; /* 11C */ + volatile csr_pqm_ecc_two_bit_int_u pqm_ecc_two_bit_int; /* 120 */ + volatile csr_pqm_mq_bind_int_u pqm_mq_bind_int; /* 130 */ + volatile csr_pqm_mq_bind_mcd_int_u pqm_mq_bind_mcd_int; /* 134 */ + volatile csr_pqm_fifo_int0_u pqm_fifo_int0; /* 138 */ + volatile csr_pqm_fifo_int0_mask_u pqm_fifo_int0_mask; /* 13C */ + volatile csr_pqm_fifo_int1_u pqm_fifo_int1; /* 140 */ + volatile csr_pqm_fifo_int1_mask_u pqm_fifo_int1_mask; /* 144 */ + volatile csr_pqm_fifo_int2_u pqm_fifo_int2; /* 148 */ + volatile csr_pqm_fifo_int2_mask_u pqm_fifo_int2_mask; /* 14C */ + volatile csr_pqm_fifo_int3_u pqm_fifo_int3; /* 150 */ + volatile csr_pqm_fifo_int3_mask_u pqm_fifo_int3_mask; /* 154 */ + volatile csr_pqm_fifo_int4_u pqm_fifo_int4; /* 158 */ + volatile csr_pqm_fifo_int4_mask_u pqm_fifo_int4_mask; /* 15C */ + volatile csr_pqm_fifo_int5_u pqm_fifo_int5; /* 160 */ + volatile csr_pqm_fifo_int5_mask_u pqm_fifo_int5_mask; /* 164 */ + volatile csr_pqm_rx_ring_e0_err_int_u pqm_rx_ring_e0_err_int; /* 168 */ + volatile csr_pqm_rx_ring_e1_err_int_u pqm_rx_ring_e1_err_int; /* 16C */ + volatile csr_pqm_fifo_st0_u pqm_fifo_st0; /* 180 */ + volatile csr_pqm_fifo_st1_u pqm_fifo_st1; /* 184 */ + volatile csr_pqm_fifo_st2_u pqm_fifo_st2; /* 188 */ + volatile csr_pqm_rw_rsv0_u pqm_rw_rsv0; /* 300 */ + volatile csr_pqm_rw_rsv1_u pqm_rw_rsv1; /* 304 */ + volatile csr_pqm_rw_rsv2_u pqm_rw_rsv2; /* 308 */ + volatile csr_pqm_rw_rsv3_u pqm_rw_rsv3; /* 30C */ + volatile csr_pqm_indrect_ctrl_u pqm_indrect_ctrl; /* 310 */ + volatile csr_pqm_indrect_timeout_u pqm_indrect_timeout; /* 314 */ + volatile csr_pqm_indrect_data_0_u pqm_indrect_data_0; /* 318 */ + volatile csr_pqm_indrect_data_1_u pqm_indrect_data_1; /* 31C */ + volatile csr_pqm_pass_through_cfg_u pqm_pass_through_cfg; /* 320 */ + volatile csr_pqm_weight_offset_u pqm_weight_offset; /* 324 */ + volatile csr_pqm_pps_shaper_cfg_pktlen_u pqm_pps_shaper_cfg_pktlen; /* 328 */ + volatile csr_pqm_root_sch_weight_cfg_u pqm_root_sch_weight_cfg; /* 32C */ + volatile csr_host_weight_u host_weight[4]; /* 340 */ + volatile csr_host_shap_bps_cfg_u host_shap_bps_cfg[4]; /* 350 */ + volatile csr_host_shap_pps_cfg_u host_shap_pps_cfg[4]; /* 360 */ + volatile csr_ep_weight_u ep_weight[32]; /* 370 */ + volatile csr_ep_shap_bps_cfg_u ep_shap_bps_cfg[32]; /* 3F0 */ + volatile csr_ep_shap_pps_cfg_u ep_shap_pps_cfg[32]; /* 470 */ + volatile csr_pqm_shap_bypass_cfg_u pqm_shap_bypass_cfg; /* 4F0 */ + volatile csr_pqm_host_ep_xon_cfg_u pqm_host_ep_xon_cfg; /* 1000 */ + volatile csr_pqm_host_xon_cfg_u pqm_host_xon_cfg; /* 1004 */ + volatile csr_pqm_host_ep_bps_spf_st_u pqm_host_ep_bps_spf_st; /* 1008 */ + volatile csr_pqm_host_ep_pps_spf_st_u pqm_host_ep_pps_spf_st; /* 100C */ + volatile csr_pqm_host_spf_st_u pqm_host_spf_st; /* 1010 */ + volatile csr_pqm_sch_bp_sta_u pqm_sch_bp_sta; /* 1014 */ + volatile csr_pqm_sch_ep_bp_sta_u pqm_sch_ep_bp_sta; /* 1018 */ + volatile csr_pqm_fifo_th_cfg_u pqm_fifo_th_cfg; /* 101C */ + volatile csr_pqm_dpl_info_ptr0_u pqm_dpl_info_ptr0; /* 1020 */ + volatile csr_pqm_dpl_info_ptr1_u pqm_dpl_info_ptr1; /* 1024 */ + volatile csr_pqm_mcd_du_info_ptr0_u pqm_mcd_du_info_ptr0; /* 1028 */ + volatile csr_pqm_mcd_du_info_ptr1_u pqm_mcd_du_info_ptr1; /* 102C */ + volatile csr_pqm_uncrt_err_mask_u pqm_uncrt_err_mask; /* 1400 */ + volatile csr_pqm_uncrt_err_clr_u pqm_uncrt_err_clr; /* 1404 */ + volatile csr_pq_eqs_cnt_u pq_eqs_cnt; /* 1408 */ + volatile csr_pq_dqs_cnt_u pq_dqs_cnt; /* 140C */ + volatile csr_pq_empt_dqs_cnt_u pq_empt_dqs_cnt; /* 1410 */ + volatile csr_pq_sch_dqr_cnt_u pq_sch_dqr_cnt; /* 1414 */ + volatile csr_pq_sch_empt_dqr_cnt_u pq_sch_empt_dqr_cnt; /* 1418 */ + volatile csr_pq_pt_dqr_cnt_u pq_pt_dqr_cnt; /* 141C */ + volatile csr_pq_dpl_cnt_u pq_dpl_cnt; /* 1420 */ + volatile csr_pq_du_vld_cnt_u pq_du_vld_cnt; /* 1424 */ + volatile csr_pq_du_err_cnt_u pq_du_err_cnt; /* 1428 */ + volatile csr_pqm_ecc_1bit_err_cnt_u pqm_ecc_1bit_err_cnt; /* 142C */ + volatile csr_pqm_ecc_2bit_err_cnt_u pqm_ecc_2bit_err_cnt; /* 1430 */ + volatile csr_sch_pq_dfx_cfg_u sch_pq_dfx_cfg; /* 14A0 */ + volatile csr_sch_pq_dfx_up_cnt_u sch_pq_dfx_up_cnt; /* 14A4 */ + volatile csr_sch_pq_dfx_empt_up_cnt_u sch_pq_dfx_empt_up_cnt; /* 14A8 */ + volatile csr_sch_pq_dfx_sch_cnt_u sch_pq_dfx_sch_cnt; /* 14AC */ + volatile csr_sch_pq_dfx_pt_deq_cnt_u sch_pq_dfx_pt_deq_cnt; /* 14B0 */ + volatile csr_sch_pq_dfx_empt_sch_cnt_u sch_pq_dfx_empt_sch_cnt; /* 14B4 */ + volatile csr_sch_pq_dfx_du_cnt_u sch_pq_dfx_du_cnt; /* 14B8 */ +} S_pqm_top_REGS_TYPE; + +/* Declare the struct pointor of the module pqm_top */ +extern volatile S_pqm_top_REGS_TYPE *goppqm_topAllReg; + +/* Declare the functions that set the member value */ +int iSetPQM_EDITION_pqm_version(unsigned int upqm_version); +int iSetPQM_INITCTAB_START_pqm_wgt_initctab_start(unsigned int upqm_wgt_initctab_start); +int iSetPQM_INITCTAB_START_pqm_shaper_initctab_start(unsigned int upqm_shaper_initctab_start); +int iSetPQM_INITCTAB_START_pqm_sch_initctab_start(unsigned int upqm_sch_initctab_start); +int iSetPQM_INITCTAB_START_pqm_cfg_initctab_start(unsigned int upqm_cfg_initctab_start); +int iSetPQM_INITCTAB_DONE_pqm_initctab_done(unsigned int upqm_initctab_done); +int iSetPQM_INITCTAB_DONE_pqm_wgt_init_done(unsigned int upqm_wgt_init_done); +int iSetPQM_INITCTAB_DONE_pqm_shaper_init_done(unsigned int upqm_shaper_init_done); +int iSetPQM_INITCTAB_DONE_pqm_sch_init_done(unsigned int upqm_sch_init_done); +int iSetPQM_INITCTAB_DONE_pqm_cfg_init_done(unsigned int upqm_cfg_init_done); +int iSetPQM_CFG_OK_pqm_cfg_ok(unsigned int upqm_cfg_ok); +int iSetPQM_INITLOGIC_DONE_pqm_initlogic_done(unsigned int upqm_initlogic_done); +int iSetMEM_ECC_BYPASS_EN_pqm_mem_ecc_bypass(unsigned int upqm_mem_ecc_bypass); +int iSetMEM_CTRL_BUS_CFG0_pqm_mem_ctrl_bus_0(unsigned int upqm_mem_ctrl_bus_0); +int iSetMEM_CTRL_BUS_CFG1_pqm_mem_ctrl_bus_1(unsigned int upqm_mem_ctrl_bus_1); +int iSetMEM_CTRL_BUS_CFG2_pqm_mem_ctrl_bus_2(unsigned int upqm_mem_ctrl_bus_2); +int iSetMEM_CTRL_BUS_CFG3_pqm_mem_ctrl_bus_3(unsigned int upqm_mem_ctrl_bus_3); +int iSetMEM_CTRL_BUS_CFG4_pqm_mem_ctrl_bus_4(unsigned int upqm_mem_ctrl_bus_4); +int iSetPQM_INT_VECTOR_pqm_cpi_int_index(unsigned int upqm_cpi_int_index); +int iSetPQM_INT_VECTOR_pqm_enable(unsigned int upqm_enable); +int iSetPQM_INT_VECTOR_pqm_int_issue(unsigned int upqm_int_issue); +int iSetPQM_INT_pqm_int_data(unsigned int upqm_int_data); +int iSetPQM_INT_pqm_program_csr_id_ro(unsigned int upqm_program_csr_id_ro); +int iSetPQM_INT_EN_pqm_int_en(unsigned int upqm_int_en); +int iSetPQM_INT_EN_pqm_program_csr_id(unsigned int upqm_program_csr_id); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_0(unsigned int upqm_mem_err_req_0); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_1(unsigned int upqm_mem_err_req_1); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_2(unsigned int upqm_mem_err_req_2); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_3(unsigned int upqm_mem_err_req_3); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_4(unsigned int upqm_mem_err_req_4); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_5(unsigned int upqm_mem_err_req_5); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_6(unsigned int upqm_mem_err_req_6); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_7(unsigned int upqm_mem_err_req_7); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_8(unsigned int upqm_mem_err_req_8); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_9(unsigned int upqm_mem_err_req_9); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_10(unsigned int upqm_mem_err_req_10); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_11(unsigned int upqm_mem_err_req_11); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_12(unsigned int upqm_mem_err_req_12); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_13(unsigned int upqm_mem_err_req_13); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_14(unsigned int upqm_mem_err_req_14); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_15(unsigned int upqm_mem_err_req_15); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_16(unsigned int upqm_mem_err_req_16); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_17(unsigned int upqm_mem_err_req_17); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_18(unsigned int upqm_mem_err_req_18); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_19(unsigned int upqm_mem_err_req_19); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_20(unsigned int upqm_mem_err_req_20); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_21(unsigned int upqm_mem_err_req_21); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_22(unsigned int upqm_mem_err_req_22); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_23(unsigned int upqm_mem_err_req_23); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_24(unsigned int upqm_mem_err_req_24); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_25(unsigned int upqm_mem_err_req_25); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_26(unsigned int upqm_mem_err_req_26); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_27(unsigned int upqm_mem_err_req_27); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_28(unsigned int upqm_mem_err_req_28); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_29(unsigned int upqm_mem_err_req_29); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_30(unsigned int upqm_mem_err_req_30); +int iSetPQM_MEM_ERR_REQ0_pqm_mem_err_req_31(unsigned int upqm_mem_err_req_31); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_32(unsigned int upqm_mem_err_req_32); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_33(unsigned int upqm_mem_err_req_33); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_34(unsigned int upqm_mem_err_req_34); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_35(unsigned int upqm_mem_err_req_35); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_36(unsigned int upqm_mem_err_req_36); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_37(unsigned int upqm_mem_err_req_37); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_38(unsigned int upqm_mem_err_req_38); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_39(unsigned int upqm_mem_err_req_39); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_40(unsigned int upqm_mem_err_req_40); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_41(unsigned int upqm_mem_err_req_41); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_42(unsigned int upqm_mem_err_req_42); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_43(unsigned int upqm_mem_err_req_43); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_44(unsigned int upqm_mem_err_req_44); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_45(unsigned int upqm_mem_err_req_45); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_46(unsigned int upqm_mem_err_req_46); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_47(unsigned int upqm_mem_err_req_47); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_48(unsigned int upqm_mem_err_req_48); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_49(unsigned int upqm_mem_err_req_49); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_50(unsigned int upqm_mem_err_req_50); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_51(unsigned int upqm_mem_err_req_51); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_52(unsigned int upqm_mem_err_req_52); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_53(unsigned int upqm_mem_err_req_53); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_54(unsigned int upqm_mem_err_req_54); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_55(unsigned int upqm_mem_err_req_55); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_56(unsigned int upqm_mem_err_req_56); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_57(unsigned int upqm_mem_err_req_57); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_58(unsigned int upqm_mem_err_req_58); +int iSetPQM_MEM_ERR_REQ1_pqm_mem_err_req_59(unsigned int upqm_mem_err_req_59); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_64(unsigned int upqm_mem_err_req_64); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_65(unsigned int upqm_mem_err_req_65); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_66(unsigned int upqm_mem_err_req_66); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_67(unsigned int upqm_mem_err_req_67); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_68(unsigned int upqm_mem_err_req_68); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_69(unsigned int upqm_mem_err_req_69); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_70(unsigned int upqm_mem_err_req_70); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_71(unsigned int upqm_mem_err_req_71); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_72(unsigned int upqm_mem_err_req_72); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_73(unsigned int upqm_mem_err_req_73); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_74(unsigned int upqm_mem_err_req_74); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_75(unsigned int upqm_mem_err_req_75); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_76(unsigned int upqm_mem_err_req_76); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_77(unsigned int upqm_mem_err_req_77); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_78(unsigned int upqm_mem_err_req_78); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_79(unsigned int upqm_mem_err_req_79); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_80(unsigned int upqm_mem_err_req_80); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_81(unsigned int upqm_mem_err_req_81); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_82(unsigned int upqm_mem_err_req_82); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_83(unsigned int upqm_mem_err_req_83); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_84(unsigned int upqm_mem_err_req_84); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_85(unsigned int upqm_mem_err_req_85); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_86(unsigned int upqm_mem_err_req_86); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_87(unsigned int upqm_mem_err_req_87); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_88(unsigned int upqm_mem_err_req_88); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_89(unsigned int upqm_mem_err_req_89); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_90(unsigned int upqm_mem_err_req_90); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_91(unsigned int upqm_mem_err_req_91); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_92(unsigned int upqm_mem_err_req_92); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_93(unsigned int upqm_mem_err_req_93); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_94(unsigned int upqm_mem_err_req_94); +int iSetPQM_MEM_ERR_REQ2_pqm_mem_err_req_95(unsigned int upqm_mem_err_req_95); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_96(unsigned int upqm_mem_err_req_96); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_97(unsigned int upqm_mem_err_req_97); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_98(unsigned int upqm_mem_err_req_98); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_99(unsigned int upqm_mem_err_req_99); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_100(unsigned int upqm_mem_err_req_100); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_101(unsigned int upqm_mem_err_req_101); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_102(unsigned int upqm_mem_err_req_102); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_103(unsigned int upqm_mem_err_req_103); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_104(unsigned int upqm_mem_err_req_104); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_105(unsigned int upqm_mem_err_req_105); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_106(unsigned int upqm_mem_err_req_106); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_107(unsigned int upqm_mem_err_req_107); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_108(unsigned int upqm_mem_err_req_108); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_109(unsigned int upqm_mem_err_req_109); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_110(unsigned int upqm_mem_err_req_110); +int iSetPQM_MEM_ERR_REQ3_pqm_mem_err_req_111(unsigned int upqm_mem_err_req_111); +int iSetPQM_ECC_ONE_BIT_INT_pqm_ecc_1bit_err(unsigned int upqm_ecc_1bit_err); +int iSetPQM_ECC_ONE_BIT_INT_pqm_ecc_1bit_err_insrt(unsigned int upqm_ecc_1bit_err_insrt); +int iSetPQM_ECC_ONE_BIT_INT_pqm_ecc_1bit_err_info(unsigned int upqm_ecc_1bit_err_info); +int iSetPQM_ECC_TWO_BIT_INT_pqm_ecc_2bit_err(unsigned int upqm_ecc_2bit_err); +int iSetPQM_ECC_TWO_BIT_INT_pqm_ecc_2bit_err_insrt(unsigned int upqm_ecc_2bit_err_insrt); +int iSetPQM_ECC_TWO_BIT_INT_pqm_ecc_2bit_err_info(unsigned int upqm_ecc_2bit_err_info); +int iSetPQM_MQ_BIND_INT_pqm_bind_cfg_err(unsigned int upqm_bind_cfg_err); +int iSetPQM_MQ_BIND_INT_pqm_bind_cfg_err_insrt(unsigned int upqm_bind_cfg_err_insrt); +int iSetPQM_MQ_BIND_INT_pqm_bind_cfg_err_info(unsigned int upqm_bind_cfg_err_info); +int iSetPQM_MQ_BIND_MCD_INT_pqm_mcd_bind_cfg_err(unsigned int upqm_mcd_bind_cfg_err); +int iSetPQM_MQ_BIND_MCD_INT_pqm_mcd_bind_cfg_err_insrt(unsigned int upqm_mcd_bind_cfg_err_insrt); +int iSetPQM_MQ_BIND_MCD_INT_pqm_mcd_bind_cfg_err_info(unsigned int upqm_mcd_bind_cfg_err_info); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err0(unsigned int upqm_fifo_int0_err0); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err0_insrt(unsigned int upqm_fifo_int0_err0_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err1(unsigned int upqm_fifo_int0_err1); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err1_insrt(unsigned int upqm_fifo_int0_err1_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err2(unsigned int upqm_fifo_int0_err2); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err2_insrt(unsigned int upqm_fifo_int0_err2_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err3(unsigned int upqm_fifo_int0_err3); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err3_insrt(unsigned int upqm_fifo_int0_err3_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err4(unsigned int upqm_fifo_int0_err4); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err4_insrt(unsigned int upqm_fifo_int0_err4_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err5(unsigned int upqm_fifo_int0_err5); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err5_insrt(unsigned int upqm_fifo_int0_err5_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err6(unsigned int upqm_fifo_int0_err6); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err6_insrt(unsigned int upqm_fifo_int0_err6_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err7(unsigned int upqm_fifo_int0_err7); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err7_insrt(unsigned int upqm_fifo_int0_err7_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err8(unsigned int upqm_fifo_int0_err8); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err8_insrt(unsigned int upqm_fifo_int0_err8_insrt); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err9(unsigned int upqm_fifo_int0_err9); +int iSetPQM_FIFO_INT0_pqm_fifo_int0_err9_insrt(unsigned int upqm_fifo_int0_err9_insrt); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err0_en(unsigned int upqm_fifo_int0_err0_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err1_en(unsigned int upqm_fifo_int0_err1_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err2_en(unsigned int upqm_fifo_int0_err2_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err3_en(unsigned int upqm_fifo_int0_err3_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err4_en(unsigned int upqm_fifo_int0_err4_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err5_en(unsigned int upqm_fifo_int0_err5_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err6_en(unsigned int upqm_fifo_int0_err6_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err7_en(unsigned int upqm_fifo_int0_err7_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err8_en(unsigned int upqm_fifo_int0_err8_en); +int iSetPQM_FIFO_INT0_MASK_pqm_fifo_int0_err9_en(unsigned int upqm_fifo_int0_err9_en); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err0(unsigned int upqm_fifo_int1_err0); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err0_insrt(unsigned int upqm_fifo_int1_err0_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err1(unsigned int upqm_fifo_int1_err1); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err1_insrt(unsigned int upqm_fifo_int1_err1_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err2(unsigned int upqm_fifo_int1_err2); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err2_insrt(unsigned int upqm_fifo_int1_err2_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err3(unsigned int upqm_fifo_int1_err3); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err3_insrt(unsigned int upqm_fifo_int1_err3_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err4(unsigned int upqm_fifo_int1_err4); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err4_insrt(unsigned int upqm_fifo_int1_err4_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err5(unsigned int upqm_fifo_int1_err5); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err5_insrt(unsigned int upqm_fifo_int1_err5_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err6(unsigned int upqm_fifo_int1_err6); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err6_insrt(unsigned int upqm_fifo_int1_err6_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err7(unsigned int upqm_fifo_int1_err7); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err7_insrt(unsigned int upqm_fifo_int1_err7_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err8(unsigned int upqm_fifo_int1_err8); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err8_insrt(unsigned int upqm_fifo_int1_err8_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err9(unsigned int upqm_fifo_int1_err9); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err9_insrt(unsigned int upqm_fifo_int1_err9_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err10(unsigned int upqm_fifo_int1_err10); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err10_insrt(unsigned int upqm_fifo_int1_err10_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err11(unsigned int upqm_fifo_int1_err11); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err11_insrt(unsigned int upqm_fifo_int1_err11_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err12(unsigned int upqm_fifo_int1_err12); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err12_insrt(unsigned int upqm_fifo_int1_err12_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err13(unsigned int upqm_fifo_int1_err13); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err13_insrt(unsigned int upqm_fifo_int1_err13_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err14(unsigned int upqm_fifo_int1_err14); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err14_insrt(unsigned int upqm_fifo_int1_err14_insrt); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err15(unsigned int upqm_fifo_int1_err15); +int iSetPQM_FIFO_INT1_pqm_fifo_int1_err15_insrt(unsigned int upqm_fifo_int1_err15_insrt); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err0_en(unsigned int upqm_fifo_int1_err0_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err1_en(unsigned int upqm_fifo_int1_err1_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err2_en(unsigned int upqm_fifo_int1_err2_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err3_en(unsigned int upqm_fifo_int1_err3_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err4_en(unsigned int upqm_fifo_int1_err4_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err5_en(unsigned int upqm_fifo_int1_err5_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err6_en(unsigned int upqm_fifo_int1_err6_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err7_en(unsigned int upqm_fifo_int1_err7_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err8_en(unsigned int upqm_fifo_int1_err8_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err9_en(unsigned int upqm_fifo_int1_err9_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err10_en(unsigned int upqm_fifo_int1_err10_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err11_en(unsigned int upqm_fifo_int1_err11_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err12_en(unsigned int upqm_fifo_int1_err12_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err13_en(unsigned int upqm_fifo_int1_err13_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err14_en(unsigned int upqm_fifo_int1_err14_en); +int iSetPQM_FIFO_INT1_MASK_pqm_fifo_int1_err15_en(unsigned int upqm_fifo_int1_err15_en); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err0(unsigned int upqm_fifo_int2_err0); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err0_insrt(unsigned int upqm_fifo_int2_err0_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err1(unsigned int upqm_fifo_int2_err1); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err1_insrt(unsigned int upqm_fifo_int2_err1_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err2(unsigned int upqm_fifo_int2_err2); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err2_insrt(unsigned int upqm_fifo_int2_err2_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err3(unsigned int upqm_fifo_int2_err3); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err3_insrt(unsigned int upqm_fifo_int2_err3_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err4(unsigned int upqm_fifo_int2_err4); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err4_insrt(unsigned int upqm_fifo_int2_err4_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err5(unsigned int upqm_fifo_int2_err5); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err5_insrt(unsigned int upqm_fifo_int2_err5_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err6(unsigned int upqm_fifo_int2_err6); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err6_insrt(unsigned int upqm_fifo_int2_err6_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err7(unsigned int upqm_fifo_int2_err7); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err7_insrt(unsigned int upqm_fifo_int2_err7_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err8(unsigned int upqm_fifo_int2_err8); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err8_insrt(unsigned int upqm_fifo_int2_err8_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err9(unsigned int upqm_fifo_int2_err9); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err9_insrt(unsigned int upqm_fifo_int2_err9_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err10(unsigned int upqm_fifo_int2_err10); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err10_insrt(unsigned int upqm_fifo_int2_err10_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err11(unsigned int upqm_fifo_int2_err11); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err11_insrt(unsigned int upqm_fifo_int2_err11_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err12(unsigned int upqm_fifo_int2_err12); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err12_insrt(unsigned int upqm_fifo_int2_err12_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err13(unsigned int upqm_fifo_int2_err13); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err13_insrt(unsigned int upqm_fifo_int2_err13_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err14(unsigned int upqm_fifo_int2_err14); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err14_insrt(unsigned int upqm_fifo_int2_err14_insrt); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err15(unsigned int upqm_fifo_int2_err15); +int iSetPQM_FIFO_INT2_pqm_fifo_int2_err15_insrt(unsigned int upqm_fifo_int2_err15_insrt); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err0_en(unsigned int upqm_fifo_int2_err0_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err1_en(unsigned int upqm_fifo_int2_err1_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err2_en(unsigned int upqm_fifo_int2_err2_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err3_en(unsigned int upqm_fifo_int2_err3_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err4_en(unsigned int upqm_fifo_int2_err4_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err5_en(unsigned int upqm_fifo_int2_err5_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err6_en(unsigned int upqm_fifo_int2_err6_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err7_en(unsigned int upqm_fifo_int2_err7_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err8_en(unsigned int upqm_fifo_int2_err8_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err9_en(unsigned int upqm_fifo_int2_err9_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err10_en(unsigned int upqm_fifo_int2_err10_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err11_en(unsigned int upqm_fifo_int2_err11_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err12_en(unsigned int upqm_fifo_int2_err12_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err13_en(unsigned int upqm_fifo_int2_err13_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err14_en(unsigned int upqm_fifo_int2_err14_en); +int iSetPQM_FIFO_INT2_MASK_pqm_fifo_int2_err15_en(unsigned int upqm_fifo_int2_err15_en); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err0(unsigned int upqm_fifo_int3_err0); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err0_insrt(unsigned int upqm_fifo_int3_err0_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err1(unsigned int upqm_fifo_int3_err1); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err1_insrt(unsigned int upqm_fifo_int3_err1_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err2(unsigned int upqm_fifo_int3_err2); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err2_insrt(unsigned int upqm_fifo_int3_err2_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err3(unsigned int upqm_fifo_int3_err3); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err3_insrt(unsigned int upqm_fifo_int3_err3_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err4(unsigned int upqm_fifo_int3_err4); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err4_insrt(unsigned int upqm_fifo_int3_err4_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err5(unsigned int upqm_fifo_int3_err5); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err5_insrt(unsigned int upqm_fifo_int3_err5_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err6(unsigned int upqm_fifo_int3_err6); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err6_insrt(unsigned int upqm_fifo_int3_err6_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err7(unsigned int upqm_fifo_int3_err7); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err7_insrt(unsigned int upqm_fifo_int3_err7_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err8(unsigned int upqm_fifo_int3_err8); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err8_insrt(unsigned int upqm_fifo_int3_err8_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err9(unsigned int upqm_fifo_int3_err9); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err9_insrt(unsigned int upqm_fifo_int3_err9_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err10(unsigned int upqm_fifo_int3_err10); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err10_insrt(unsigned int upqm_fifo_int3_err10_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err11(unsigned int upqm_fifo_int3_err11); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err11_insrt(unsigned int upqm_fifo_int3_err11_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err12(unsigned int upqm_fifo_int3_err12); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err12_insrt(unsigned int upqm_fifo_int3_err12_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err13(unsigned int upqm_fifo_int3_err13); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err13_insrt(unsigned int upqm_fifo_int3_err13_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err14(unsigned int upqm_fifo_int3_err14); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err14_insrt(unsigned int upqm_fifo_int3_err14_insrt); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err15(unsigned int upqm_fifo_int3_err15); +int iSetPQM_FIFO_INT3_pqm_fifo_int3_err15_insrt(unsigned int upqm_fifo_int3_err15_insrt); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err0_en(unsigned int upqm_fifo_int3_err0_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err1_en(unsigned int upqm_fifo_int3_err1_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err2_en(unsigned int upqm_fifo_int3_err2_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err3_en(unsigned int upqm_fifo_int3_err3_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err4_en(unsigned int upqm_fifo_int3_err4_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err5_en(unsigned int upqm_fifo_int3_err5_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err6_en(unsigned int upqm_fifo_int3_err6_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err7_en(unsigned int upqm_fifo_int3_err7_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err8_en(unsigned int upqm_fifo_int3_err8_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err9_en(unsigned int upqm_fifo_int3_err9_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err10_en(unsigned int upqm_fifo_int3_err10_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err11_en(unsigned int upqm_fifo_int3_err11_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err12_en(unsigned int upqm_fifo_int3_err12_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err13_en(unsigned int upqm_fifo_int3_err13_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err14_en(unsigned int upqm_fifo_int3_err14_en); +int iSetPQM_FIFO_INT3_MASK_pqm_fifo_int3_err15_en(unsigned int upqm_fifo_int3_err15_en); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err0(unsigned int upqm_fifo_int4_err0); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err0_insrt(unsigned int upqm_fifo_int4_err0_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err1(unsigned int upqm_fifo_int4_err1); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err1_insrt(unsigned int upqm_fifo_int4_err1_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err2(unsigned int upqm_fifo_int4_err2); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err2_insrt(unsigned int upqm_fifo_int4_err2_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err3(unsigned int upqm_fifo_int4_err3); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err3_insrt(unsigned int upqm_fifo_int4_err3_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err4(unsigned int upqm_fifo_int4_err4); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err4_insrt(unsigned int upqm_fifo_int4_err4_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err5(unsigned int upqm_fifo_int4_err5); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err5_insrt(unsigned int upqm_fifo_int4_err5_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err6(unsigned int upqm_fifo_int4_err6); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err6_insrt(unsigned int upqm_fifo_int4_err6_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err7(unsigned int upqm_fifo_int4_err7); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err7_insrt(unsigned int upqm_fifo_int4_err7_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err8(unsigned int upqm_fifo_int4_err8); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err8_insrt(unsigned int upqm_fifo_int4_err8_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err9(unsigned int upqm_fifo_int4_err9); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err9_insrt(unsigned int upqm_fifo_int4_err9_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err10(unsigned int upqm_fifo_int4_err10); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err10_insrt(unsigned int upqm_fifo_int4_err10_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err11(unsigned int upqm_fifo_int4_err11); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err11_insrt(unsigned int upqm_fifo_int4_err11_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err12(unsigned int upqm_fifo_int4_err12); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err12_insrt(unsigned int upqm_fifo_int4_err12_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err13(unsigned int upqm_fifo_int4_err13); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err13_insrt(unsigned int upqm_fifo_int4_err13_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err14(unsigned int upqm_fifo_int4_err14); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err14_insrt(unsigned int upqm_fifo_int4_err14_insrt); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err15(unsigned int upqm_fifo_int4_err15); +int iSetPQM_FIFO_INT4_pqm_fifo_int4_err15_insrt(unsigned int upqm_fifo_int4_err15_insrt); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err0_en(unsigned int upqm_fifo_int4_err0_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err1_en(unsigned int upqm_fifo_int4_err1_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err2_en(unsigned int upqm_fifo_int4_err2_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err3_en(unsigned int upqm_fifo_int4_err3_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err4_en(unsigned int upqm_fifo_int4_err4_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err5_en(unsigned int upqm_fifo_int4_err5_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err6_en(unsigned int upqm_fifo_int4_err6_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err7_en(unsigned int upqm_fifo_int4_err7_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err8_en(unsigned int upqm_fifo_int4_err8_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err9_en(unsigned int upqm_fifo_int4_err9_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err10_en(unsigned int upqm_fifo_int4_err10_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err11_en(unsigned int upqm_fifo_int4_err11_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err12_en(unsigned int upqm_fifo_int4_err12_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err13_en(unsigned int upqm_fifo_int4_err13_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err14_en(unsigned int upqm_fifo_int4_err14_en); +int iSetPQM_FIFO_INT4_MASK_pqm_fifo_int4_err15_en(unsigned int upqm_fifo_int4_err15_en); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err0(unsigned int upqm_fifo_int5_err0); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err0_insrt(unsigned int upqm_fifo_int5_err0_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err1(unsigned int upqm_fifo_int5_err1); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err1_insrt(unsigned int upqm_fifo_int5_err1_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err2(unsigned int upqm_fifo_int5_err2); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err2_insrt(unsigned int upqm_fifo_int5_err2_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err3(unsigned int upqm_fifo_int5_err3); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err3_insrt(unsigned int upqm_fifo_int5_err3_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err4(unsigned int upqm_fifo_int5_err4); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err4_insrt(unsigned int upqm_fifo_int5_err4_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err5(unsigned int upqm_fifo_int5_err5); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err5_insrt(unsigned int upqm_fifo_int5_err5_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err6(unsigned int upqm_fifo_int5_err6); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err6_insrt(unsigned int upqm_fifo_int5_err6_insrt); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err7(unsigned int upqm_fifo_int5_err7); +int iSetPQM_FIFO_INT5_pqm_fifo_int5_err7_insrt(unsigned int upqm_fifo_int5_err7_insrt); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err0_en(unsigned int upqm_fifo_int5_err0_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err1_en(unsigned int upqm_fifo_int5_err1_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err2_en(unsigned int upqm_fifo_int5_err2_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err3_en(unsigned int upqm_fifo_int5_err3_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err4_en(unsigned int upqm_fifo_int5_err4_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err5_en(unsigned int upqm_fifo_int5_err5_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err6_en(unsigned int upqm_fifo_int5_err6_en); +int iSetPQM_FIFO_INT5_MASK_pqm_fifo_int5_err7_en(unsigned int upqm_fifo_int5_err7_en); +int iSetPQM_RX_RING_E0_ERR_INT_pqm_ring_e0_err(unsigned int upqm_ring_e0_err); +int iSetPQM_RX_RING_E0_ERR_INT_pqm_ring_e0_err_insert(unsigned int upqm_ring_e0_err_insert); +int iSetPQM_RX_RING_E0_ERR_INT_pqm_ring_e0_err_info(unsigned int upqm_ring_e0_err_info); +int iSetPQM_RX_RING_E1_ERR_INT_pqm_ring_e1_err(unsigned int upqm_ring_e1_err); +int iSetPQM_RX_RING_E1_ERR_INT_pqm_ring_e1_err_insert(unsigned int upqm_ring_e1_err_insert); +int iSetPQM_RX_RING_E1_ERR_INT_pqm_ring_e1_err_info(unsigned int upqm_ring_e1_err_info); +int iSetPQM_FIFO_ST0_pqm_fifo0_st0(unsigned int upqm_fifo0_st0); +int iSetPQM_FIFO_ST0_pqm_fifo1_st0(unsigned int upqm_fifo1_st0); +int iSetPQM_FIFO_ST0_pqm_fifo2_st0(unsigned int upqm_fifo2_st0); +int iSetPQM_FIFO_ST0_pqm_fifo3_st0(unsigned int upqm_fifo3_st0); +int iSetPQM_FIFO_ST0_pqm_fifo4_st0(unsigned int upqm_fifo4_st0); +int iSetPQM_FIFO_ST0_pqm_fifo5_st0(unsigned int upqm_fifo5_st0); +int iSetPQM_FIFO_ST0_pqm_fifo6_st0(unsigned int upqm_fifo6_st0); +int iSetPQM_FIFO_ST0_pqm_fifo7_st0(unsigned int upqm_fifo7_st0); +int iSetPQM_FIFO_ST0_pqm_fifo8_st0(unsigned int upqm_fifo8_st0); +int iSetPQM_FIFO_ST0_pqm_fifo9_st0(unsigned int upqm_fifo9_st0); +int iSetPQM_FIFO_ST0_pqm_fifo10_st0(unsigned int upqm_fifo10_st0); +int iSetPQM_FIFO_ST0_pqm_fifo11_st0(unsigned int upqm_fifo11_st0); +int iSetPQM_FIFO_ST0_pqm_fifo12_st0(unsigned int upqm_fifo12_st0); +int iSetPQM_FIFO_ST1_pqm_fifo0_st1(unsigned int upqm_fifo0_st1); +int iSetPQM_FIFO_ST1_pqm_fifo1_st1(unsigned int upqm_fifo1_st1); +int iSetPQM_FIFO_ST1_pqm_fifo2_st1(unsigned int upqm_fifo2_st1); +int iSetPQM_FIFO_ST1_pqm_fifo3_st1(unsigned int upqm_fifo3_st1); +int iSetPQM_FIFO_ST1_pqm_fifo4_st1(unsigned int upqm_fifo4_st1); +int iSetPQM_FIFO_ST1_pqm_fifo5_st1(unsigned int upqm_fifo5_st1); +int iSetPQM_FIFO_ST1_pqm_fifo6_st1(unsigned int upqm_fifo6_st1); +int iSetPQM_FIFO_ST1_pqm_fifo7_st1(unsigned int upqm_fifo7_st1); +int iSetPQM_FIFO_ST1_pqm_fifo8_st1(unsigned int upqm_fifo8_st1); +int iSetPQM_FIFO_ST1_pqm_fifo9_st1(unsigned int upqm_fifo9_st1); +int iSetPQM_FIFO_ST1_pqm_fifo10_st1(unsigned int upqm_fifo10_st1); +int iSetPQM_FIFO_ST1_pqm_fifo11_st1(unsigned int upqm_fifo11_st1); +int iSetPQM_FIFO_ST1_pqm_fifo12_st1(unsigned int upqm_fifo12_st1); +int iSetPQM_FIFO_ST1_pqm_fifo13_st1(unsigned int upqm_fifo13_st1); +int iSetPQM_FIFO_ST1_pqm_fifo14_st1(unsigned int upqm_fifo14_st1); +int iSetPQM_FIFO_ST1_pqm_fifo15_st1(unsigned int upqm_fifo15_st1); +int iSetPQM_FIFO_ST2_pqm_fifo0_st2(unsigned int upqm_fifo0_st2); +int iSetPQM_FIFO_ST2_pqm_fifo1_st2(unsigned int upqm_fifo1_st2); +int iSetPQM_FIFO_ST2_pqm_fifo2_st2(unsigned int upqm_fifo2_st2); +int iSetPQM_FIFO_ST2_pqm_fifo3_st2(unsigned int upqm_fifo3_st2); +int iSetPQM_FIFO_ST2_pqm_fifo4_st2(unsigned int upqm_fifo4_st2); +int iSetPQM_FIFO_ST2_pqm_fifo5_st2(unsigned int upqm_fifo5_st2); +int iSetPQM_FIFO_ST2_pqm_fifo6_st2(unsigned int upqm_fifo6_st2); +int iSetPQM_FIFO_ST2_pqm_fifo7_st2(unsigned int upqm_fifo7_st2); +int iSetPQM_FIFO_ST2_pqm_fifo8_st2(unsigned int upqm_fifo8_st2); +int iSetPQM_FIFO_ST2_pqm_fifo9_st2(unsigned int upqm_fifo9_st2); +int iSetPQM_FIFO_ST2_pqm_fifo10_st2(unsigned int upqm_fifo10_st2); +int iSetPQM_FIFO_ST2_pqm_fifo11_st2(unsigned int upqm_fifo11_st2); +int iSetPQM_RW_RSV0_pqm_rw_rsv0(unsigned int upqm_rw_rsv0); +int iSetPQM_RW_RSV1_pqm_rw_rsv1(unsigned int upqm_rw_rsv1); +int iSetPQM_RW_RSV2_pqm_rw_rsv2(unsigned int upqm_rw_rsv2); +int iSetPQM_RW_RSV3_pqm_rw_rsv3(unsigned int upqm_rw_rsv3); +int iSetPQM_INDRECT_CTRL_pqm_indrect_addr(unsigned int upqm_indrect_addr); +int iSetPQM_INDRECT_CTRL_pqm_indrect_tab(unsigned int upqm_indrect_tab); +int iSetPQM_INDRECT_CTRL_pqm_indrect_stat(unsigned int upqm_indrect_stat); +int iSetPQM_INDRECT_CTRL_pqm_indrect_mode(unsigned int upqm_indrect_mode); +int iSetPQM_INDRECT_CTRL_pqm_indrect_vld(unsigned int upqm_indrect_vld); +int iSetPQM_INDRECT_TIMEOUT_pqm_indrect_timeout(unsigned int upqm_indrect_timeout); +int iSetPQM_INDRECT_DATA_0_pqm_indrect_data_0(unsigned int upqm_indrect_data_0); +int iSetPQM_INDRECT_DATA_1_pqm_indrect_data_1(unsigned int upqm_indrect_data_1); +int iSetPQM_PASS_THROUGH_CFG_pqm_passthru_enable(unsigned int upqm_passthru_enable); +int iSetPQM_PASS_THROUGH_CFG_pqm_passthru_wgt_cfg(unsigned int upqm_passthru_wgt_cfg); +int iSetPQM_WEIGHT_OFFSET_pqm_cos_weight_offset(unsigned int upqm_cos_weight_offset); +int iSetPQM_WEIGHT_OFFSET_pqm_ep_weight_offset(unsigned int upqm_ep_weight_offset); +int iSetPQM_WEIGHT_OFFSET_pqm_host_weight_offset(unsigned int upqm_host_weight_offset); +int iSetPQM_PPS_SHAPER_CFG_PKTLEN_pqm_pps_typical_pktlen_cfg(unsigned int upqm_pps_typical_pktlen_cfg); +int iSetPQM_ROOT_SCH_WEIGHT_CFG_pqm_root_sch_wgt_cfg(unsigned int upqm_root_sch_wgt_cfg); +int iSetHOST_WEIGHT_host_weight_cfg(unsigned int uhost_weight_cfg); +int iSetHOST_SHAP_BPS_CFG_host_shap_bps_cfg(unsigned int uhost_shap_bps_cfg); +int iSetHOST_SHAP_PPS_CFG_host_shap_pps_cfg(unsigned int uhost_shap_pps_cfg); +int iSetEP_WEIGHT_ep_weight_cfg(unsigned int uep_weight_cfg); +int iSetEP_SHAP_BPS_CFG_ep_shap_bps_cfg(unsigned int uep_shap_bps_cfg); +int iSetEP_SHAP_PPS_CFG_ep_shap_pps_cfg(unsigned int uep_shap_pps_cfg); +int iSetPQM_SHAP_BYPASS_CFG_pqm_nmq_shap_byp_vld(unsigned int upqm_nmq_shap_byp_vld); +int iSetPQM_SHAP_BYPASS_CFG_pqm_vnic_shap_byp_vld(unsigned int upqm_vnic_shap_byp_vld); +int iSetPQM_SHAP_BYPASS_CFG_pqm_vnicgrp_shap_byp_vld(unsigned int upqm_vnicgrp_shap_byp_vld); +int iSetPQM_SHAP_BYPASS_CFG_pqm_ep_shap_byp_vld(unsigned int upqm_ep_shap_byp_vld); +int iSetPQM_SHAP_BYPASS_CFG_pqm_host_shap_byp_vld(unsigned int upqm_host_shap_byp_vld); +int iSetPQM_HOST_EP_XON_CFG_pqm_hostep_xon_cfg(unsigned int upqm_hostep_xon_cfg); +int iSetPQM_HOST_XON_CFG_msc_host_xon_cfg(unsigned int umsc_host_xon_cfg); +int iSetPQM_HOST_XON_CFG_msc_root_xon_cfg(unsigned int umsc_root_xon_cfg); +int iSetPQM_HOST_EP_BPS_SPF_ST_pqm_hostep_bps_spf_st(unsigned int upqm_hostep_bps_spf_st); +int iSetPQM_HOST_EP_PPS_SPF_ST_pqm_hostep_pps_spf_st(unsigned int upqm_hostep_pps_spf_st); +int iSetPQM_HOST_SPF_ST_msc_host_bps_spf_st(unsigned int umsc_host_bps_spf_st); +int iSetPQM_HOST_SPF_ST_msc_host_pps_spf_st(unsigned int umsc_host_pps_spf_st); +int iSetPQM_SCH_BP_STA_pqm_host_bp(unsigned int upqm_host_bp); +int iSetPQM_SCH_BP_STA_pqm_scan_bp(unsigned int upqm_scan_bp); +int iSetPQM_SCH_EP_BP_STA_pqm_ep_bp(unsigned int upqm_ep_bp); +int iSetPQM_FIFO_TH_CFG_pqm_du_fifo_gap(unsigned int upqm_du_fifo_gap); +int iSetPQM_FIFO_TH_CFG_pqm_pt_fifo_gap(unsigned int upqm_pt_fifo_gap); +int iSetPQM_DPL_INFO_PTR0_pqm_dpl_plen(unsigned int upqm_dpl_plen); +int iSetPQM_DPL_INFO_PTR0_pqm_dpl_pnum(unsigned int upqm_dpl_pnum); +int iSetPQM_DPL_INFO_PTR1_pqm_dpl_pqid(unsigned int upqm_dpl_pqid); +int iSetPQM_MCD_DU_INFO_PTR0_pqm_mcd_plen(unsigned int upqm_mcd_plen); +int iSetPQM_MCD_DU_INFO_PTR0_pqm_mcd_pnum(unsigned int upqm_mcd_pnum); +int iSetPQM_MCD_DU_INFO_PTR1_pqm_mcd_pqid(unsigned int upqm_mcd_pqid); +int iSetPQM_MCD_DU_INFO_PTR1_pqm_mcd_color(unsigned int upqm_mcd_color); +int iSetPQM_UNCRT_ERR_MASK_ram_uncrt_err_mask(unsigned int uram_uncrt_err_mask); +int iSetPQM_UNCRT_ERR_MASK_other_uncrt_err_mask(unsigned int uother_uncrt_err_mask); +int iSetPQM_UNCRT_ERR_CLR_ram_uncrt_err_clr(unsigned int uram_uncrt_err_clr); +int iSetPQM_UNCRT_ERR_CLR_other_uncrt_err_clr(unsigned int uother_uncrt_err_clr); +int iSetPQ_EQS_CNT_pqm_eqs_cnt(unsigned int upqm_eqs_cnt); +int iSetPQ_DQS_CNT_pqm_dqs_cnt(unsigned int upqm_dqs_cnt); +int iSetPQ_EMPT_DQS_CNT_pqm_empt_dqs_cnt(unsigned int upqm_empt_dqs_cnt); +int iSetPQ_SCH_DQR_CNT_pqm_sch_dqr_cnt(unsigned int upqm_sch_dqr_cnt); +int iSetPQ_SCH_EMPT_DQR_CNT_pqm_sch_empt_dqr_cnt(unsigned int upqm_sch_empt_dqr_cnt); +int iSetPQ_PT_DQR_CNT_pqm_pt_dqr_cnt(unsigned int upqm_pt_dqr_cnt); +int iSetPQ_DPL_CNT_pqm_dpl_cnt(unsigned int upqm_dpl_cnt); +int iSetPQ_DU_VLD_CNT_pqm_du_info_vld_cnt(unsigned int upqm_du_info_vld_cnt); +int iSetPQ_DU_ERR_CNT_pqm_du_info_err_cnt(unsigned int upqm_du_info_err_cnt); +int iSetPQM_ECC_1BIT_ERR_CNT_pqm_ecc_1bit_err_cnt(unsigned int upqm_ecc_1bit_err_cnt); +int iSetPQM_ECC_2BIT_ERR_CNT_pqm_ecc_2bit_err_cnt(unsigned int upqm_ecc_2bit_err_cnt); +int iSetSCH_PQ_DFX_CFG_sch_pq_dfx_cfg(unsigned int usch_pq_dfx_cfg); +int iSetSCH_PQ_DFX_CFG_sch_pq_dfx_cfg_vld(unsigned int usch_pq_dfx_cfg_vld); +int iSetSCH_PQ_DFX_UP_CNT_sch_pq_dfx_up_cnt(unsigned int usch_pq_dfx_up_cnt); +int iSetSCH_PQ_DFX_EMPT_UP_CNT_sch_pq_dfx_empt_up_cnt(unsigned int usch_pq_dfx_empt_up_cnt); +int iSetSCH_PQ_DFX_SCH_CNT_sch_pq_dfx_sch_cnt(unsigned int usch_pq_dfx_sch_cnt); +int iSetSCH_PQ_DFX_PT_DEQ_CNT_sch_pq_dfx_pt_dqr_cnt(unsigned int usch_pq_dfx_pt_dqr_cnt); +int iSetSCH_PQ_DFX_EMPT_SCH_CNT_sch_pq_dfx_empt_sch_cnt(unsigned int usch_pq_dfx_empt_sch_cnt); +int iSetSCH_PQ_DFX_DU_CNT_sch_pq_dfx_du_cnt(unsigned int usch_pq_dfx_du_cnt); + + +#endif // PQM_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_reg_offset.h new file mode 100644 index 000000000..00682ed5b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/pqm_reg_offset.h @@ -0,0 +1,291 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : pqm_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:57:27 Create file +// ****************************************************************************** + +#ifndef PQM_REG_OFFSET_H +#define PQM_REG_OFFSET_H + +/* PQM_TOP Base address of Module's Register */ +#define CSR_PQM_TOP_BASE (0xC000) + +/* **************************************************************************** */ +/* PQM_TOP Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_PQM_TOP_PQM_EDITION_REG (CSR_PQM_TOP_BASE + 0x0) /* Version Register */ +#define CSR_PQM_TOP_PQM_INITCTAB_START_REG (CSR_PQM_TOP_BASE + 0x4) /* 配置表初始化使能寄存器 */ +#define CSR_PQM_TOP_PQM_INITCTAB_DONE_REG (CSR_PQM_TOP_BASE + 0x8) /* 配置表初始化状态寄存器 */ +#define CSR_PQM_TOP_PQM_CFG_OK_REG (CSR_PQM_TOP_BASE + 0xC) /* PQM 配置完成寄存器 */ +#define CSR_PQM_TOP_PQM_INITLOGIC_DONE_REG (CSR_PQM_TOP_BASE + 0x10) /* 芯片逻辑初始化状态寄存器 */ +#define CSR_PQM_TOP_MEM_ECC_BYPASS_EN_REG (CSR_PQM_TOP_BASE + 0x14) /* RAM ECC BYPASS控制寄存器 */ +#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG0_REG (CSR_PQM_TOP_BASE + 0x18) /* RAM CTRL_BUS寄存器0 */ +#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG1_REG (CSR_PQM_TOP_BASE + 0x1C) /* RAM CTRL_BUS寄存器1 */ +#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG2_REG (CSR_PQM_TOP_BASE + 0x20) /* RAM CTRL_BUS寄存器2 */ +#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG3_REG (CSR_PQM_TOP_BASE + 0x24) /* RAM CTRL_BUS寄存器3 */ +#define CSR_PQM_TOP_MEM_CTRL_BUS_CFG4_REG (CSR_PQM_TOP_BASE + 0x28) /* RAM CTRL_BUS寄存器4 */ +#define CSR_PQM_TOP_PQM_INT_VECTOR_REG (CSR_PQM_TOP_BASE + 0x100) /* PQM Interrupt Vector Register */ +#define CSR_PQM_TOP_PQM_INT_REG (CSR_PQM_TOP_BASE + 0x104) /* PQM Interrupt Register */ +#define CSR_PQM_TOP_PQM_INT_EN_REG (CSR_PQM_TOP_BASE + 0x108) /* PQM Interrupt Mask Register */ +#define CSR_PQM_TOP_PQM_MEM_ERR_REQ0_REG (CSR_PQM_TOP_BASE + 0x10C) /* PQM mem Error Request register0. */ +#define CSR_PQM_TOP_PQM_MEM_ERR_REQ1_REG (CSR_PQM_TOP_BASE + 0x110) /* PQM mem Error Request register1. */ +#define CSR_PQM_TOP_PQM_MEM_ERR_REQ2_REG (CSR_PQM_TOP_BASE + 0x114) /* PQM mem Error Request register2. */ +#define CSR_PQM_TOP_PQM_MEM_ERR_REQ3_REG (CSR_PQM_TOP_BASE + 0x118) /* PQM mem Error Request register3. */ +#define CSR_PQM_TOP_PQM_ECC_ONE_BIT_INT_REG (CSR_PQM_TOP_BASE + 0x11C) /* RAM ECC ONE BIT ERROR */ +#define CSR_PQM_TOP_PQM_ECC_TWO_BIT_INT_REG (CSR_PQM_TOP_BASE + 0x120) /* RAM ECC TWO BITS ERROR */ +#define CSR_PQM_TOP_PQM_MQ_BIND_INT_REG (CSR_PQM_TOP_BASE + 0x130) /* MQ MAPPING CONFIG ERROR */ +#define CSR_PQM_TOP_PQM_MQ_BIND_MCD_INT_REG (CSR_PQM_TOP_BASE + 0x134) /* MQ MAPPING CONFIG FOR MCD ERROR */ +#define CSR_PQM_TOP_PQM_FIFO_INT0_REG (CSR_PQM_TOP_BASE + 0x138) /* FIFO 0 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT0_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x13C) /* FIFO 0 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_FIFO_INT1_REG (CSR_PQM_TOP_BASE + 0x140) /* FIFO 1 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT1_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x144) /* FIFO 1 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_FIFO_INT2_REG (CSR_PQM_TOP_BASE + 0x148) /* FIFO 2 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT2_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x14C) /* FIFO 2 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_FIFO_INT3_REG (CSR_PQM_TOP_BASE + 0x150) /* FIFO 3 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT3_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x154) /* FIFO 3 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_FIFO_INT4_REG (CSR_PQM_TOP_BASE + 0x158) /* FIFO 4 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT4_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x15C) /* FIFO 4 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_FIFO_INT5_REG (CSR_PQM_TOP_BASE + 0x160) /* FIFO 5 interrupt,include write int and read int */ +#define CSR_PQM_TOP_PQM_FIFO_INT5_MASK_REG \ + (CSR_PQM_TOP_BASE + 0x164) /* FIFO 5 interrupt,include write int and read init mask */ +#define CSR_PQM_TOP_PQM_RX_RING_E0_ERR_INT_REG (CSR_PQM_TOP_BASE + 0x168) /* Receive Ring E0 error int */ +#define CSR_PQM_TOP_PQM_RX_RING_E1_ERR_INT_REG (CSR_PQM_TOP_BASE + 0x16C) /* Receive Ring E0 error int */ +#define CSR_PQM_TOP_PQM_FIFO_ST0_REG (CSR_PQM_TOP_BASE + 0x180) /* fifo full and empt state0 */ +#define CSR_PQM_TOP_PQM_FIFO_ST1_REG (CSR_PQM_TOP_BASE + 0x184) /* fifo full and empt state1 */ +#define CSR_PQM_TOP_PQM_FIFO_ST2_REG (CSR_PQM_TOP_BASE + 0x188) /* fifo full and empt state2 */ +#define CSR_PQM_TOP_PQM_RW_RSV0_REG (CSR_PQM_TOP_BASE + 0x300) /* PQM reserved rw register. */ +#define CSR_PQM_TOP_PQM_RW_RSV1_REG (CSR_PQM_TOP_BASE + 0x304) /* PQM reserved rw register. */ +#define CSR_PQM_TOP_PQM_RW_RSV2_REG (CSR_PQM_TOP_BASE + 0x308) /* PQM reserved rw register. */ +#define CSR_PQM_TOP_PQM_RW_RSV3_REG (CSR_PQM_TOP_BASE + 0x30C) /* PQM reserved rw register. */ +#define CSR_PQM_TOP_PQM_INDRECT_CTRL_REG (CSR_PQM_TOP_BASE + 0x310) /* Indirect access ctrl Register。 */ +#define CSR_PQM_TOP_PQM_INDRECT_TIMEOUT_REG (CSR_PQM_TOP_BASE + 0x314) /* Indirect Access Timeout Register。 */ +#define CSR_PQM_TOP_PQM_INDRECT_DATA_0_REG (CSR_PQM_TOP_BASE + 0x318) /* Indirect Access Data Register BIT63_32 */ +#define CSR_PQM_TOP_PQM_INDRECT_DATA_1_REG (CSR_PQM_TOP_BASE + 0x31C) /* Indirect Access Data Register BIT31_0 */ +#define CSR_PQM_TOP_PQM_PASS_THROUGH_CFG_REG (CSR_PQM_TOP_BASE + 0x320) /* Pass through function enable register. */ +#define CSR_PQM_TOP_PQM_WEIGHT_OFFSET_REG (CSR_PQM_TOP_BASE + 0x324) /* Normal queue weight offset */ +#define CSR_PQM_TOP_PQM_PPS_SHAPER_CFG_PKTLEN_REG (CSR_PQM_TOP_BASE + 0x328) /* PQM Shaper Config Pktlen */ +#define CSR_PQM_TOP_PQM_ROOT_SCH_WEIGHT_CFG_REG (CSR_PQM_TOP_BASE + 0x32C) /* PQM ROOT SCH WEIGHT Config */ +#define CSR_PQM_TOP_HOST_WEIGHT_0_REG (CSR_PQM_TOP_BASE + 0x340) /* Normal MQ host weight */ +#define CSR_PQM_TOP_HOST_WEIGHT_1_REG (CSR_PQM_TOP_BASE + 0x344) /* Normal MQ host weight */ +#define CSR_PQM_TOP_HOST_WEIGHT_2_REG (CSR_PQM_TOP_BASE + 0x348) /* Normal MQ host weight */ +#define CSR_PQM_TOP_HOST_WEIGHT_3_REG (CSR_PQM_TOP_BASE + 0x34C) /* Normal MQ host weight */ +#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x350) /* HOST Node Shaper BPS Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x354) /* HOST Node Shaper BPS Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x358) /* HOST Node Shaper BPS Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_BPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x35C) /* HOST Node Shaper BPS Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x360) /* HOST Node Shaper PPS_Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x364) /* HOST Node Shaper PPS_Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x368) /* HOST Node Shaper PPS_Configuration Table */ +#define CSR_PQM_TOP_HOST_SHAP_PPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x36C) /* HOST Node Shaper PPS_Configuration Table */ +#define CSR_PQM_TOP_EP_WEIGHT_0_REG (CSR_PQM_TOP_BASE + 0x370) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_1_REG (CSR_PQM_TOP_BASE + 0x374) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_2_REG (CSR_PQM_TOP_BASE + 0x378) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_3_REG (CSR_PQM_TOP_BASE + 0x37C) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_4_REG (CSR_PQM_TOP_BASE + 0x380) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_5_REG (CSR_PQM_TOP_BASE + 0x384) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_6_REG (CSR_PQM_TOP_BASE + 0x388) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_7_REG (CSR_PQM_TOP_BASE + 0x38C) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_8_REG (CSR_PQM_TOP_BASE + 0x390) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_9_REG (CSR_PQM_TOP_BASE + 0x394) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_10_REG (CSR_PQM_TOP_BASE + 0x398) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_11_REG (CSR_PQM_TOP_BASE + 0x39C) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_12_REG (CSR_PQM_TOP_BASE + 0x3A0) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_13_REG (CSR_PQM_TOP_BASE + 0x3A4) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_14_REG (CSR_PQM_TOP_BASE + 0x3A8) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_15_REG (CSR_PQM_TOP_BASE + 0x3AC) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_16_REG (CSR_PQM_TOP_BASE + 0x3B0) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_17_REG (CSR_PQM_TOP_BASE + 0x3B4) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_18_REG (CSR_PQM_TOP_BASE + 0x3B8) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_19_REG (CSR_PQM_TOP_BASE + 0x3BC) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_20_REG (CSR_PQM_TOP_BASE + 0x3C0) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_21_REG (CSR_PQM_TOP_BASE + 0x3C4) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_22_REG (CSR_PQM_TOP_BASE + 0x3C8) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_23_REG (CSR_PQM_TOP_BASE + 0x3CC) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_24_REG (CSR_PQM_TOP_BASE + 0x3D0) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_25_REG (CSR_PQM_TOP_BASE + 0x3D4) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_26_REG (CSR_PQM_TOP_BASE + 0x3D8) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_27_REG (CSR_PQM_TOP_BASE + 0x3DC) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_28_REG (CSR_PQM_TOP_BASE + 0x3E0) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_29_REG (CSR_PQM_TOP_BASE + 0x3E4) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_30_REG (CSR_PQM_TOP_BASE + 0x3E8) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_WEIGHT_31_REG (CSR_PQM_TOP_BASE + 0x3EC) /* Normal MQ EP Node weight */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x3F0) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x3F4) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x3F8) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x3FC) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_4_REG (CSR_PQM_TOP_BASE + 0x400) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_5_REG (CSR_PQM_TOP_BASE + 0x404) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_6_REG (CSR_PQM_TOP_BASE + 0x408) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_7_REG (CSR_PQM_TOP_BASE + 0x40C) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_8_REG (CSR_PQM_TOP_BASE + 0x410) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_9_REG (CSR_PQM_TOP_BASE + 0x414) /* EP Node Shaper BPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_10_REG \ + (CSR_PQM_TOP_BASE + 0x418) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_11_REG \ + (CSR_PQM_TOP_BASE + 0x41C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_12_REG \ + (CSR_PQM_TOP_BASE + 0x420) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_13_REG \ + (CSR_PQM_TOP_BASE + 0x424) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_14_REG \ + (CSR_PQM_TOP_BASE + 0x428) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_15_REG \ + (CSR_PQM_TOP_BASE + 0x42C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_16_REG \ + (CSR_PQM_TOP_BASE + 0x430) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_17_REG \ + (CSR_PQM_TOP_BASE + 0x434) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_18_REG \ + (CSR_PQM_TOP_BASE + 0x438) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_19_REG \ + (CSR_PQM_TOP_BASE + 0x43C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_20_REG \ + (CSR_PQM_TOP_BASE + 0x440) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_21_REG \ + (CSR_PQM_TOP_BASE + 0x444) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_22_REG \ + (CSR_PQM_TOP_BASE + 0x448) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_23_REG \ + (CSR_PQM_TOP_BASE + 0x44C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_24_REG \ + (CSR_PQM_TOP_BASE + 0x450) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_25_REG \ + (CSR_PQM_TOP_BASE + 0x454) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_26_REG \ + (CSR_PQM_TOP_BASE + 0x458) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_27_REG \ + (CSR_PQM_TOP_BASE + 0x45C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_28_REG \ + (CSR_PQM_TOP_BASE + 0x460) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_29_REG \ + (CSR_PQM_TOP_BASE + 0x464) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_30_REG \ + (CSR_PQM_TOP_BASE + 0x468) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_BPS_CFG_31_REG \ + (CSR_PQM_TOP_BASE + 0x46C) /* EP Node Shaper BPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_0_REG (CSR_PQM_TOP_BASE + 0x470) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_1_REG (CSR_PQM_TOP_BASE + 0x474) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_2_REG (CSR_PQM_TOP_BASE + 0x478) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_3_REG (CSR_PQM_TOP_BASE + 0x47C) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_4_REG (CSR_PQM_TOP_BASE + 0x480) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_5_REG (CSR_PQM_TOP_BASE + 0x484) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_6_REG (CSR_PQM_TOP_BASE + 0x488) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_7_REG (CSR_PQM_TOP_BASE + 0x48C) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_8_REG (CSR_PQM_TOP_BASE + 0x490) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_9_REG (CSR_PQM_TOP_BASE + 0x494) /* EP Node Shaper PPS Configuration Table for NS \ + */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_10_REG \ + (CSR_PQM_TOP_BASE + 0x498) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_11_REG \ + (CSR_PQM_TOP_BASE + 0x49C) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_12_REG \ + (CSR_PQM_TOP_BASE + 0x4A0) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_13_REG \ + (CSR_PQM_TOP_BASE + 0x4A4) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_14_REG \ + (CSR_PQM_TOP_BASE + 0x4A8) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_15_REG \ + (CSR_PQM_TOP_BASE + 0x4AC) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_16_REG \ + (CSR_PQM_TOP_BASE + 0x4B0) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_17_REG \ + (CSR_PQM_TOP_BASE + 0x4B4) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_18_REG \ + (CSR_PQM_TOP_BASE + 0x4B8) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_19_REG \ + (CSR_PQM_TOP_BASE + 0x4BC) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_20_REG \ + (CSR_PQM_TOP_BASE + 0x4C0) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_21_REG \ + (CSR_PQM_TOP_BASE + 0x4C4) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_22_REG \ + (CSR_PQM_TOP_BASE + 0x4C8) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_23_REG \ + (CSR_PQM_TOP_BASE + 0x4CC) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_24_REG \ + (CSR_PQM_TOP_BASE + 0x4D0) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_25_REG \ + (CSR_PQM_TOP_BASE + 0x4D4) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_26_REG \ + (CSR_PQM_TOP_BASE + 0x4D8) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_27_REG \ + (CSR_PQM_TOP_BASE + 0x4DC) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_28_REG \ + (CSR_PQM_TOP_BASE + 0x4E0) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_29_REG \ + (CSR_PQM_TOP_BASE + 0x4E4) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_30_REG \ + (CSR_PQM_TOP_BASE + 0x4E8) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_EP_SHAP_PPS_CFG_31_REG \ + (CSR_PQM_TOP_BASE + 0x4EC) /* EP Node Shaper PPS Configuration Table for NS */ +#define CSR_PQM_TOP_PQM_SHAP_BYPASS_CFG_REG (CSR_PQM_TOP_BASE + 0x4F0) /* PQM Shaper Bypass Configuration */ +#define CSR_PQM_TOP_PQM_HOST_EP_XON_CFG_REG (CSR_PQM_TOP_BASE + 0x1000) /* The XON Configuration of the HOST EP node \ + */ +#define CSR_PQM_TOP_PQM_HOST_XON_CFG_REG (CSR_PQM_TOP_BASE + 0x1004) /* The XON Configuration of the HOST node */ +#define CSR_PQM_TOP_PQM_HOST_EP_BPS_SPF_ST_REG \ + (CSR_PQM_TOP_BASE + 0x1008) /* The BPS Shap Pass Flag State of the HOST EP node */ +#define CSR_PQM_TOP_PQM_HOST_EP_PPS_SPF_ST_REG \ + (CSR_PQM_TOP_BASE + 0x100C) /* The PPS Shap Pass Flag State of the HOST EP node */ +#define CSR_PQM_TOP_PQM_HOST_SPF_ST_REG (CSR_PQM_TOP_BASE + 0x1010) /* The Shap Pass Flag State of the HOST node */ +#define CSR_PQM_TOP_PQM_SCH_BP_STA_REG (CSR_PQM_TOP_BASE + 0x1014) /* PQM ROOT Level backpress status Register */ +#define CSR_PQM_TOP_PQM_SCH_EP_BP_STA_REG (CSR_PQM_TOP_BASE + 0x1018) /* PQM HSOT_EP Level backpress status Register \ + */ +#define CSR_PQM_TOP_PQM_FIFO_TH_CFG_REG (CSR_PQM_TOP_BASE + 0x101C) /* The Threshold Config Of PQM FIFO */ +#define CSR_PQM_TOP_PQM_DPL_INFO_PTR0_REG (CSR_PQM_TOP_BASE + 0x1020) /* PQM DPL INFO 0 status Register */ +#define CSR_PQM_TOP_PQM_DPL_INFO_PTR1_REG (CSR_PQM_TOP_BASE + 0x1024) /* PQM DPL INFO 1 status Register */ +#define CSR_PQM_TOP_PQM_MCD_DU_INFO_PTR0_REG (CSR_PQM_TOP_BASE + 0x1028) /* PQM MCD DU INFO 0 status Register */ +#define CSR_PQM_TOP_PQM_MCD_DU_INFO_PTR1_REG (CSR_PQM_TOP_BASE + 0x102C) /* PQM MCD DU INFO 1 status Register */ +#define CSR_PQM_TOP_PQM_UNCRT_ERR_MASK_REG (CSR_PQM_TOP_BASE + 0x1400) /* PQM Urgency Interrupt Mask Register。 */ +#define CSR_PQM_TOP_PQM_UNCRT_ERR_CLR_REG (CSR_PQM_TOP_BASE + 0x1404) /* PQM Urgency Interrupt Clear Register。 */ +#define CSR_PQM_TOP_PQ_EQS_CNT_REG (CSR_PQM_TOP_BASE + 0x1408) /* PQM MQ ENQ EQS count */ +#define CSR_PQM_TOP_PQ_DQS_CNT_REG (CSR_PQM_TOP_BASE + 0x140C) /* PQM MQ DQS count */ +#define CSR_PQM_TOP_PQ_EMPT_DQS_CNT_REG (CSR_PQM_TOP_BASE + 0x1410) /* PQM MQ EMPT DQS count */ +#define CSR_PQM_TOP_PQ_SCH_DQR_CNT_REG (CSR_PQM_TOP_BASE + 0x1414) /* PQM MQ SCH DQR count */ +#define CSR_PQM_TOP_PQ_SCH_EMPT_DQR_CNT_REG (CSR_PQM_TOP_BASE + 0x1418) /* PQM MQ SCH EMPT DQR count */ +#define CSR_PQM_TOP_PQ_PT_DQR_CNT_REG (CSR_PQM_TOP_BASE + 0x141C) /* PQM MQ PT DQR count */ +#define CSR_PQM_TOP_PQ_DPL_CNT_REG (CSR_PQM_TOP_BASE + 0x1420) /* PQM MQ DPL count */ +#define CSR_PQM_TOP_PQ_DU_VLD_CNT_REG (CSR_PQM_TOP_BASE + 0x1424) /* PQM DU VLD count */ +#define CSR_PQM_TOP_PQ_DU_ERR_CNT_REG (CSR_PQM_TOP_BASE + 0x1428) /* PQM DU ERR count */ +#define CSR_PQM_TOP_PQM_ECC_1BIT_ERR_CNT_REG (CSR_PQM_TOP_BASE + 0x142C) /* PQM MEMORY ECC 1BIT ERR count */ +#define CSR_PQM_TOP_PQM_ECC_2BIT_ERR_CNT_REG (CSR_PQM_TOP_BASE + 0x1430) /* PQM MEMORY ECC 2BIT ERR count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_CFG_REG (CSR_PQM_TOP_BASE + 0x14A0) /* PQ DFX NUM configure */ +#define CSR_PQM_TOP_SCH_PQ_DFX_UP_CNT_REG (CSR_PQM_TOP_BASE + 0x14A4) /* PQ DFX NUM ENQ UP count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_EMPT_UP_CNT_REG (CSR_PQM_TOP_BASE + 0x14A8) /* PQ DFX NUM ENQ EMPT UP count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_SCH_CNT_REG (CSR_PQM_TOP_BASE + 0x14AC) /* PQ DFX NUM DEQ SCH count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_PT_DEQ_CNT_REG (CSR_PQM_TOP_BASE + 0x14B0) /* PQ DFX NUM PT DEQ SCH count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_EMPT_SCH_CNT_REG (CSR_PQM_TOP_BASE + 0x14B4) /* PQ DFX NUM DEQ EMPT SCH count */ +#define CSR_PQM_TOP_SCH_PQ_DFX_DU_CNT_REG (CSR_PQM_TOP_BASE + 0x14B8) /* PQ DFX NUM DU count */ + +#endif // PQM_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_c_union_define.h new file mode 100644 index 000000000..1b93261f5 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_c_union_define.h @@ -0,0 +1,2937 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : prmrx_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:59:21 Create file +// ****************************************************************************** + +#ifndef PRMRX_C_UNION_DEFINE_H +#define PRMRX_C_UNION_DEFINE_H + +/* Define the union csr_prm_top_mem_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_decode_mem_ecc_req : 2; /* [1:0] */ + u32 csr_decode_mem_ecc_bypass : 1; /* [2] */ + u32 mem_power_ctrl : 3; /* [5:3] */ + u32 mem_timing_ctrl : 8; /* [13:6] */ + u32 mem_init_start : 1; /* [14] */ + u32 mem_init_done : 1; /* [15] */ + u32 rsv_0 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mem_ctrl_u; + +/* Define the union csr_prm_top_mqm_bp_mask0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_root_bp_mask : 1; /* [0] */ + u32 mqm_prm_bp_mode : 1; /* [1] */ + u32 rsv_1 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp_mask0_u; + +/* Define the union csr_prm_top_mqm_bp_mask1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_host_dp_ep_bp_mask : 8; /* [7:0] */ + u32 mqm_host_dp_root_bp_mask : 1; /* [8] */ + u32 rsv_2 : 3; /* [11:9] */ + u32 mqm_host_cp_ep_bp_mask : 8; /* [19:12] */ + u32 mqm_host_cp_root_bp_mask : 1; /* [20] */ + u32 rsv_3 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp_mask1_u; + +/* Define the union csr_prm_top_mqm_bp_mask2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_soc_dp_ep_bp_mask : 8; /* [7:0] */ + u32 mqm_soc_dp_root_bp_mask : 1; /* [8] */ + u32 rsv_4 : 3; /* [11:9] */ + u32 mqm_soc_cp_ep_bp_mask : 8; /* [19:12] */ + u32 mqm_soc_cp_root_bp_mask : 1; /* [20] */ + u32 rsv_5 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp_mask2_u; + +/* Define the union csr_prm_top_mqm_bp_mask3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_host_dp_cos_bp_mask0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp_mask3_u; + +/* Define the union csr_prm_top_mqm_bp_mask4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_host_dp_cos_bp_mask1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp_mask4_u; + +/* Define the union csr_prm_top_bp_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stliq_fc_mask : 1; /* [0] */ + u32 stfiq_fc_mask : 1; /* [1] */ + u32 oq_fc_mask : 1; /* [2] */ + u32 mag_fc_mask : 1; /* [3] */ + u32 cpb_fc_mask : 1; /* [4] */ + u32 cpi_fc_mask : 1; /* [5] */ + u32 rsv_6 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_bp_mask_u; + +/* Define the union csr_prm_top_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_7 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_8 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int_vector_u; + +/* Define the union csr_prm_top_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_9 : 10; /* [15:6] */ + u32 program_csr_id_ro : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int_u; + +/* Define the union csr_prm_top_int_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_en : 6; /* [5:0] */ + u32 rsv_10 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int_en_u; + +/* Define the union csr_prm_top_int0_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_fifo_overflow : 1; /* [0] */ + u32 int_insrt0 : 1; /* [1] */ + u32 prm_int0_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int0_sticky_u; + +/* Define the union csr_prm_top_int1_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_fifo_underflow : 1; /* [0] */ + u32 int_insrt1 : 1; /* [1] */ + u32 prm_int1_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int1_sticky_u; + +/* Define the union csr_prm_top_int2_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_2bit : 1; /* [0] */ + u32 int_insrt2 : 1; /* [1] */ + u32 prm_int2_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int2_sticky_u; + +/* Define the union csr_prm_top_int3_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_1bit : 1; /* [0] */ + u32 int_insrt3 : 1; /* [1] */ + u32 prm_int3_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_int3_sticky_u; + +/* Define the union csr_prm_int4_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_pd_proc_cnt_underflow : 1; /* [0] */ + u32 int_insr4 : 1; /* [1] */ + u32 prm_int4_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_int4_sticky_u; + +/* Define the union csr_prm_int5_sticky_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_rx_lb_cos_drop : 1; /* [0] */ + u32 int_insr5 : 1; /* [1] */ + u32 prm_int5_sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_int5_sticky_u; + +/* Define the union csr_prm_fifo_st0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fifo_over_flag : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_st0_u; + +/* Define the union csr_prm_fifo_st1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_fifo_under_flag : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_st1_u; + +/* Define the union csr_prm_fifo_st2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_fifo_over_flag : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_st2_u; + +/* Define the union csr_prm_fifo_st3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_fifo_under_flag : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_st3_u; + +/* Define the union csr_prm_src_in_vio_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 src_in_vio : 15; /* [14:0] */ + u32 rsv_11 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_src_in_vio_u; + +/* Define the union csr_prm_top_mqm_bp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_root_bp : 1; /* [0] */ + u32 rsv_12 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp0_u; + +/* Define the union csr_prm_top_mqm_bp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_host_dp_ep_bp : 8; /* [7:0] */ + u32 mqm_host_dp_root_bp : 1; /* [8] */ + u32 rsv_13 : 3; /* [11:9] */ + u32 mqm_host_cp_ep_bp : 8; /* [19:12] */ + u32 mqm_host_cp_root_bp : 1; /* [20] */ + u32 rsv_14 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp1_u; + +/* Define the union csr_prm_top_mqm_bp2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_soc_dp_ep_bp : 8; /* [7:0] */ + u32 mqm_soc_dp_root_bp : 1; /* [8] */ + u32 rsv_15 : 3; /* [11:9] */ + u32 mqm_soc_cp_ep_bp : 8; /* [19:12] */ + u32 mqm_soc_cp_root_bp : 1; /* [20] */ + u32 rsv_16 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp2_u; + +/* Define the union csr_prm_top_mqm_bp3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mqm_host_dp_cos_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mqm_bp3_u; + +/* Define the union csr_prm_top_mag_port_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_mag_rx_port_bp : 8; /* [7:0] */ + u32 rsv_17 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mag_port_bp_u; + +/* Define the union csr_prm_top_mag_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mag_fc_cos_n_merg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_mag_cos_bp_u; + +/* Define the union csr_prm_top_oq_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_fc_cos_n_merg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_oq_cos_bp_u; + +/* Define the union csr_prm_top_cpi_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_cpi_src_bp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_cpi_cos_bp_u; + +/* Define the union csr_prm_top_cpb_cos_bp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_fc_cos_n_merg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_cpb_cos_bp_u; + +/* Define the union csr_prm_top_iq_bp_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 iq_bp_sft_sub_port : 5; /* [4:0] */ + u32 iq_bp_sft_side : 1; /* [5] */ + u32 iq_bp_sft_en : 1; /* [6] */ + u32 rsv_18 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_iq_bp_cfg_u; + +/* Define the union csr_prm_top_stl_iq_bp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_stliq_icb_stf_eventq_plb_bp : 8; /* [7:0] */ + u32 prm_stliq_icb_evntq_llb_bp : 8; /* [15:8] */ + u32 prm_stliq_icb_evntq_plb_bp : 8; /* [23:16] */ + u32 prm_stliq_icb_nrmlq_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_stl_iq_bp0_u; + +/* Define the union csr_prm_top_stl_iq_bp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 8; /* [7:0] */ + u32 rsv_20 : 8; /* [15:8] */ + u32 rsv_21 : 8; /* [23:16] */ + u32 prm_stliq_icb_stf_eventq_llb_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_stl_iq_bp1_u; + +/* Define the union csr_prm_top_stf_iq_bp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_stfiq_icb_evntq_ddr_bp : 8; /* [7:0] */ + u32 prm_stfiq_icb_evntq_llb_bp : 8; /* [15:8] */ + u32 prm_stfiq_icb_evntq_plb_bp : 8; /* [23:16] */ + u32 prm_stfiq_icb_shallowq_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_stf_iq_bp0_u; + +/* Define the union csr_prm_top_stf_iq_bp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_stfiq_icb_cmd_dbe_bp : 8; /* [7:0] */ + u32 prm_stfiq_icb_cmd_pkt_bp : 8; /* [15:8] */ + u32 prm_stfiq_icb_nret_bp : 8; /* [23:16] */ + u32 prm_stfiq_icb_nrml_dbe_bp : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_stf_iq_bp1_u; + +/* Define the union csr_prm_top_1bit_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ecc_1bit_inc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_top_1bit_ecc_err_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_prm_top_mem_ctrl_u prm_top_mem_ctrl; /* 0 */ + volatile csr_prm_top_mqm_bp_mask0_u prm_top_mqm_bp_mask0; /* 4 */ + volatile csr_prm_top_mqm_bp_mask1_u prm_top_mqm_bp_mask1; /* 8 */ + volatile csr_prm_top_mqm_bp_mask2_u prm_top_mqm_bp_mask2; /* C */ + volatile csr_prm_top_mqm_bp_mask3_u prm_top_mqm_bp_mask3; /* 10 */ + volatile csr_prm_top_mqm_bp_mask4_u prm_top_mqm_bp_mask4; /* 14 */ + volatile csr_prm_top_bp_mask_u prm_top_bp_mask; /* 18 */ + volatile csr_prm_top_int_vector_u prm_top_int_vector; /* 5C */ + volatile csr_prm_top_int_u prm_top_int; /* 60 */ + volatile csr_prm_top_int_en_u prm_top_int_en; /* 64 */ + volatile csr_prm_top_int0_sticky_u prm_top_int0_sticky; /* 68 */ + volatile csr_prm_top_int1_sticky_u prm_top_int1_sticky; /* 6C */ + volatile csr_prm_top_int2_sticky_u prm_top_int2_sticky; /* 70 */ + volatile csr_prm_top_int3_sticky_u prm_top_int3_sticky; /* 74 */ + volatile csr_prm_int4_sticky_u prm_int4_sticky; /* 78 */ + volatile csr_prm_int5_sticky_u prm_int5_sticky; /* 7C */ + volatile csr_prm_fifo_st0_u prm_fifo_st0; /* 100 */ + volatile csr_prm_fifo_st1_u prm_fifo_st1; /* 104 */ + volatile csr_prm_fifo_st2_u prm_fifo_st2; /* 108 */ + volatile csr_prm_fifo_st3_u prm_fifo_st3; /* 10C */ + volatile csr_prm_src_in_vio_u prm_src_in_vio; /* 110 */ + volatile csr_prm_top_mqm_bp0_u prm_top_mqm_bp0; /* 204 */ + volatile csr_prm_top_mqm_bp1_u prm_top_mqm_bp1; /* 208 */ + volatile csr_prm_top_mqm_bp2_u prm_top_mqm_bp2; /* 20C */ + volatile csr_prm_top_mqm_bp3_u prm_top_mqm_bp3[2]; /* 210 */ + volatile csr_prm_top_mag_port_bp_u prm_top_mag_port_bp; /* 220 */ + volatile csr_prm_top_mag_cos_bp_u prm_top_mag_cos_bp[2]; /* 240 */ + volatile csr_prm_top_oq_cos_bp_u prm_top_oq_cos_bp[4]; /* 250 */ + volatile csr_prm_top_cpi_cos_bp_u prm_top_cpi_cos_bp[3]; /* 260 */ + volatile csr_prm_top_cpb_cos_bp_u prm_top_cpb_cos_bp[3]; /* 270 */ + volatile csr_prm_top_iq_bp_cfg_u prm_top_iq_bp_cfg; /* 290 */ + volatile csr_prm_top_stl_iq_bp0_u prm_top_stl_iq_bp0; /* 294 */ + volatile csr_prm_top_stl_iq_bp1_u prm_top_stl_iq_bp1; /* 298 */ + volatile csr_prm_top_stf_iq_bp0_u prm_top_stf_iq_bp0; /* 29C */ + volatile csr_prm_top_stf_iq_bp1_u prm_top_stf_iq_bp1; /* 2A0 */ + volatile csr_prm_top_1bit_ecc_err_u prm_top_1bit_ecc_err; /* 2A4 */ +} S_qu_prm_top_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_prm_top_csr */ +extern volatile S_qu_prm_top_csr_REGS_TYPE *gopqu_prm_top_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetPRM_TOP_MEM_CTRL_csr_decode_mem_ecc_req(unsigned int ucsr_decode_mem_ecc_req); +int iSetPRM_TOP_MEM_CTRL_csr_decode_mem_ecc_bypass(unsigned int ucsr_decode_mem_ecc_bypass); +int iSetPRM_TOP_MEM_CTRL_mem_power_ctrl(unsigned int umem_power_ctrl); +int iSetPRM_TOP_MEM_CTRL_mem_timing_ctrl(unsigned int umem_timing_ctrl); +int iSetPRM_TOP_MEM_CTRL_mem_init_start(unsigned int umem_init_start); +int iSetPRM_TOP_MEM_CTRL_mem_init_done(unsigned int umem_init_done); +int iSetPRM_TOP_MQM_BP_MASK0_mqm_root_bp_mask(unsigned int umqm_root_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK0_mqm_prm_bp_mode(unsigned int umqm_prm_bp_mode); +int iSetPRM_TOP_MQM_BP_MASK1_mqm_host_dp_ep_bp_mask(unsigned int umqm_host_dp_ep_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK1_mqm_host_dp_root_bp_mask(unsigned int umqm_host_dp_root_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK1_mqm_host_cp_ep_bp_mask(unsigned int umqm_host_cp_ep_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK1_mqm_host_cp_root_bp_mask(unsigned int umqm_host_cp_root_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK2_mqm_soc_dp_ep_bp_mask(unsigned int umqm_soc_dp_ep_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK2_mqm_soc_dp_root_bp_mask(unsigned int umqm_soc_dp_root_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK2_mqm_soc_cp_ep_bp_mask(unsigned int umqm_soc_cp_ep_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK2_mqm_soc_cp_root_bp_mask(unsigned int umqm_soc_cp_root_bp_mask); +int iSetPRM_TOP_MQM_BP_MASK3_mqm_host_dp_cos_bp_mask0(unsigned int umqm_host_dp_cos_bp_mask0); +int iSetPRM_TOP_MQM_BP_MASK4_mqm_host_dp_cos_bp_mask1(unsigned int umqm_host_dp_cos_bp_mask1); +int iSetPRM_TOP_BP_MASK_stliq_fc_mask(unsigned int ustliq_fc_mask); +int iSetPRM_TOP_BP_MASK_stfiq_fc_mask(unsigned int ustfiq_fc_mask); +int iSetPRM_TOP_BP_MASK_oq_fc_mask(unsigned int uoq_fc_mask); +int iSetPRM_TOP_BP_MASK_mag_fc_mask(unsigned int umag_fc_mask); +int iSetPRM_TOP_BP_MASK_cpb_fc_mask(unsigned int ucpb_fc_mask); +int iSetPRM_TOP_BP_MASK_cpi_fc_mask(unsigned int ucpi_fc_mask); +int iSetPRM_TOP_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetPRM_TOP_INT_VECTOR_enable(unsigned int uenable); +int iSetPRM_TOP_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetPRM_TOP_INT_int_data(unsigned int uint_data); +int iSetPRM_TOP_INT_program_csr_id_ro(unsigned int uprogram_csr_id_ro); +int iSetPRM_TOP_INT_EN_int_en(unsigned int uint_en); +int iSetPRM_TOP_INT_EN_program_csr_id(unsigned int uprogram_csr_id); +int iSetPRM_TOP_INT0_STICKY_prm_fifo_overflow(unsigned int uprm_fifo_overflow); +int iSetPRM_TOP_INT0_STICKY_int_insrt0(unsigned int uint_insrt0); +int iSetPRM_TOP_INT0_STICKY_prm_int0_sticky(unsigned int uprm_int0_sticky); +int iSetPRM_TOP_INT1_STICKY_prm_fifo_underflow(unsigned int uprm_fifo_underflow); +int iSetPRM_TOP_INT1_STICKY_int_insrt1(unsigned int uint_insrt1); +int iSetPRM_TOP_INT1_STICKY_prm_int1_sticky(unsigned int uprm_int1_sticky); +int iSetPRM_TOP_INT2_STICKY_mem_ecc_2bit(unsigned int umem_ecc_2bit); +int iSetPRM_TOP_INT2_STICKY_int_insrt2(unsigned int uint_insrt2); +int iSetPRM_TOP_INT2_STICKY_prm_int2_sticky(unsigned int uprm_int2_sticky); +int iSetPRM_TOP_INT3_STICKY_mem_ecc_1bit(unsigned int umem_ecc_1bit); +int iSetPRM_TOP_INT3_STICKY_int_insrt3(unsigned int uint_insrt3); +int iSetPRM_TOP_INT3_STICKY_prm_int3_sticky(unsigned int uprm_int3_sticky); +int iSetPRM_INT4_STICKY_prm_pd_proc_cnt_underflow(unsigned int uprm_pd_proc_cnt_underflow); +int iSetPRM_INT4_STICKY_int_insr4(unsigned int uint_insr4); +int iSetPRM_INT4_STICKY_prm_int4_sticky(unsigned int uprm_int4_sticky); +int iSetPRM_INT5_STICKY_prm_rx_lb_cos_drop(unsigned int uprm_rx_lb_cos_drop); +int iSetPRM_INT5_STICKY_int_insr5(unsigned int uint_insr5); +int iSetPRM_INT5_STICKY_prm_int5_sticky(unsigned int uprm_int5_sticky); +int iSetPRM_FIFO_ST0_tx_fifo_over_flag(unsigned int utx_fifo_over_flag); +int iSetPRM_FIFO_ST1_tx_fifo_under_flag(unsigned int utx_fifo_under_flag); +int iSetPRM_FIFO_ST2_rx_fifo_over_flag(unsigned int urx_fifo_over_flag); +int iSetPRM_FIFO_ST3_rx_fifo_under_flag(unsigned int urx_fifo_under_flag); +int iSetPRM_SRC_IN_VIO_src_in_vio(unsigned int usrc_in_vio); +int iSetPRM_TOP_MQM_BP0_mqm_root_bp(unsigned int umqm_root_bp); +int iSetPRM_TOP_MQM_BP1_mqm_host_dp_ep_bp(unsigned int umqm_host_dp_ep_bp); +int iSetPRM_TOP_MQM_BP1_mqm_host_dp_root_bp(unsigned int umqm_host_dp_root_bp); +int iSetPRM_TOP_MQM_BP1_mqm_host_cp_ep_bp(unsigned int umqm_host_cp_ep_bp); +int iSetPRM_TOP_MQM_BP1_mqm_host_cp_root_bp(unsigned int umqm_host_cp_root_bp); +int iSetPRM_TOP_MQM_BP2_mqm_soc_dp_ep_bp(unsigned int umqm_soc_dp_ep_bp); +int iSetPRM_TOP_MQM_BP2_mqm_soc_dp_root_bp(unsigned int umqm_soc_dp_root_bp); +int iSetPRM_TOP_MQM_BP2_mqm_soc_cp_ep_bp(unsigned int umqm_soc_cp_ep_bp); +int iSetPRM_TOP_MQM_BP2_mqm_soc_cp_root_bp(unsigned int umqm_soc_cp_root_bp); +int iSetPRM_TOP_MQM_BP3_mqm_host_dp_cos_bp(unsigned int umqm_host_dp_cos_bp); +int iSetPRM_TOP_MAG_PORT_BP_prm_mag_rx_port_bp(unsigned int uprm_mag_rx_port_bp); +int iSetPRM_TOP_MAG_COS_BP_mag_fc_cos_n_merg(unsigned int umag_fc_cos_n_merg); +int iSetPRM_TOP_OQ_COS_BP_oq_fc_cos_n_merg(unsigned int uoq_fc_cos_n_merg); +int iSetPRM_TOP_CPI_COS_BP_prm_cpi_src_bp(unsigned int uprm_cpi_src_bp); +int iSetPRM_TOP_CPB_COS_BP_cpb_fc_cos_n_merg(unsigned int ucpb_fc_cos_n_merg); +int iSetPRM_TOP_IQ_BP_CFG_iq_bp_sft_sub_port(unsigned int uiq_bp_sft_sub_port); +int iSetPRM_TOP_IQ_BP_CFG_iq_bp_sft_side(unsigned int uiq_bp_sft_side); +int iSetPRM_TOP_IQ_BP_CFG_iq_bp_sft_en(unsigned int uiq_bp_sft_en); +int iSetPRM_TOP_STL_IQ_BP0_prm_stliq_icb_stf_eventq_plb_bp(unsigned int uprm_stliq_icb_stf_eventq_plb_bp); +int iSetPRM_TOP_STL_IQ_BP0_prm_stliq_icb_evntq_llb_bp(unsigned int uprm_stliq_icb_evntq_llb_bp); +int iSetPRM_TOP_STL_IQ_BP0_prm_stliq_icb_evntq_plb_bp(unsigned int uprm_stliq_icb_evntq_plb_bp); +int iSetPRM_TOP_STL_IQ_BP0_prm_stliq_icb_nrmlq_bp(unsigned int uprm_stliq_icb_nrmlq_bp); +int iSetPRM_TOP_STL_IQ_BP1_prm_stliq_icb_stf_eventq_llb_bp(unsigned int uprm_stliq_icb_stf_eventq_llb_bp); +int iSetPRM_TOP_STF_IQ_BP0_prm_stfiq_icb_evntq_ddr_bp(unsigned int uprm_stfiq_icb_evntq_ddr_bp); +int iSetPRM_TOP_STF_IQ_BP0_prm_stfiq_icb_evntq_llb_bp(unsigned int uprm_stfiq_icb_evntq_llb_bp); +int iSetPRM_TOP_STF_IQ_BP0_prm_stfiq_icb_evntq_plb_bp(unsigned int uprm_stfiq_icb_evntq_plb_bp); +int iSetPRM_TOP_STF_IQ_BP0_prm_stfiq_icb_shallowq_bp(unsigned int uprm_stfiq_icb_shallowq_bp); +int iSetPRM_TOP_STF_IQ_BP1_prm_stfiq_icb_cmd_dbe_bp(unsigned int uprm_stfiq_icb_cmd_dbe_bp); +int iSetPRM_TOP_STF_IQ_BP1_prm_stfiq_icb_cmd_pkt_bp(unsigned int uprm_stfiq_icb_cmd_pkt_bp); +int iSetPRM_TOP_STF_IQ_BP1_prm_stfiq_icb_nret_bp(unsigned int uprm_stfiq_icb_nret_bp); +int iSetPRM_TOP_STF_IQ_BP1_prm_stfiq_icb_nrml_dbe_bp(unsigned int uprm_stfiq_icb_nrml_dbe_bp); +int iSetPRM_TOP_1BIT_ECC_ERR_mem_ecc_1bit_inc(unsigned int umem_ecc_1bit_inc); + +/* Define the union csr_prm_rx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_ctrl_u; + +/* Define the union csr_prm_rx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_timeout_u; + +/* Define the union csr_prm_rx_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_dat0_u; + +/* Define the union csr_prm_rx_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_dat1_u; + +/* Define the union csr_prm_rx_indrect_dat2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_dat2_u; + +/* Define the union csr_prm_rx_indrect_dat3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_indrect_dat3_u; + +/* Define the union csr_prm_rx_csr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dyn_csr_req_src : 8; /* [7:0] */ + u32 bmr_dyn_csr_req : 1; /* [8] */ + u32 bmy_dyn_csr_req : 1; /* [9] */ + u32 bmn_dyn_csr_req : 1; /* [10] */ + u32 rsv_0 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_csr_cfg_u; + +/* Define the union csr_prm_rx_y_stf_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_fc0_th_on : 16; /* [15:0] */ + u32 stf_state_y_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_fc_th_cfg_u; + +/* Define the union csr_prm_rx_y_stl_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_fc0_th_on : 16; /* [15:0] */ + u32 stl_state_y_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_2 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_fc_th_cfg_u; + +/* Define the union csr_prm_rx_r_stf_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_fc0_th_on : 16; /* [15:0] */ + u32 stf_state_r_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_fc_th_cfg_u; + +/* Define the union csr_prm_rx_r_stl_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_fc0_th_on : 16; /* [15:0] */ + u32 stl_state_r_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_fc_th_cfg_u; + +/* Define the union csr_prm_rx_y_stf_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_rsvd : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_rsvd_cfg_u; + +/* Define the union csr_prm_rx_y_stl_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_rsvd : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_rsvd_cfg_u; + +/* Define the union csr_prm_rx_r_stf_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_rsvd : 16; /* [15:0] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_rsvd_cfg_u; + +/* Define the union csr_prm_rx_r_stl_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_rsvd : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_rsvd_cfg_u; + +/* Define the union csr_prm_rx_y_stf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_cnt : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_cnt_u; + +/* Define the union csr_prm_rx_y_stl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_cnt : 16; /* [15:0] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_cnt_u; + +/* Define the union csr_prm_rx_r_stf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_cnt : 16; /* [15:0] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_cnt_u; + +/* Define the union csr_prm_rx_r_stl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_cnt : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_cnt_u; + +/* Define the union csr_prm_rx_y_stf_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_sh_cnt : 16; /* [15:0] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_sh_cnt_u; + +/* Define the union csr_prm_rx_y_stl_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_sh_cnt : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_sh_cnt_u; + +/* Define the union csr_prm_rx_r_stf_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_sh_cnt : 16; /* [15:0] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_sh_cnt_u; + +/* Define the union csr_prm_rx_r_stl_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_sh_cnt : 16; /* [15:0] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_sh_cnt_u; + +/* Define the union csr_prm_rx_y_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_17 : 1; /* [3] */ + u32 bmy_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_18 : 3; /* [11:9] */ + u32 bmy_cfg_mon_srv : 1; /* [12] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 bmy_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_20 : 2; /* [19:18] */ + u32 bmy_cfg_cnt_en : 1; /* [20] */ + u32 rsv_21 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_mon_cfg_u; + +/* Define the union csr_prm_rx_y_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_22 : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 bmy_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_24 : 3; /* [11:9] */ + u32 bmy_cfg_his_cnt_srv : 1; /* [12] */ + u32 rsv_25 : 3; /* [15:13] */ + u32 bmy_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_26 : 3; /* [19:17] */ + u32 bmy_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_27 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_his_cfg_u; + +/* Define the union csr_prm_rx_r_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_28 : 1; /* [3] */ + u32 bmr_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_29 : 3; /* [11:9] */ + u32 bmr_cfg_mon_srv : 1; /* [12] */ + u32 rsv_30 : 3; /* [15:13] */ + u32 bmr_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_31 : 2; /* [19:18] */ + u32 bmr_cfg_cnt_en : 1; /* [20] */ + u32 rsv_32 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_mon_cfg_u; + +/* Define the union csr_prm_rx_r_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_33 : 3; /* [2:0] */ + u32 rsv_34 : 1; /* [3] */ + u32 bmr_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_35 : 3; /* [11:9] */ + u32 bmr_cfg_his_cnt_srv : 1; /* [12] */ + u32 rsv_36 : 3; /* [15:13] */ + u32 bmr_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_37 : 3; /* [19:17] */ + u32 bmr_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_38 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_his_cfg_u; + +/* Define the union csr_prm_rx_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stlfq_aloc_u; + +/* Define the union csr_prm_rx_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq0_aloc_u; + +/* Define the union csr_prm_rx_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq1_aloc_u; + +/* Define the union csr_prm_rx_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stlfq_daloc_u; + +/* Define the union csr_prm_rx_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq0_daloc_u; + +/* Define the union csr_prm_rx_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq1_daloc_u; + +/* Define the union csr_prm_rx_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_daloc_u; + +/* Define the union csr_prm_rx_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_drop_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_drop_u; + +/* Define the union csr_prm_rx_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_oq_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_oq_daloc_u; + +/* Define the union csr_prm_rx_stlfq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stlfq_aloc_cnt_u; + +/* Define the union csr_prm_rx_stffq0_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq0_aloc_cnt_u; + +/* Define the union csr_prm_rx_stffq1_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq1_aloc_cnt_u; + +/* Define the union csr_prm_rx_stlfq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stlfq_daloc_cnt_u; + +/* Define the union csr_prm_rx_stffq0_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq0_daloc_cnt_u; + +/* Define the union csr_prm_rx_stffq1_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stffq1_daloc_cnt_u; + +/* Define the union csr_prm_rx_cpb_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_daloc_cnt_u; + +/* Define the union csr_prm_rx_cpb_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_drop_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_drop_cnt_u; + +/* Define the union csr_prm_rx_oq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_oq_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_oq_daloc_cnt_u; + +/* Define the union csr_prm_rx_r_stf_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_port : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_p_his_cnt_u; + +/* Define the union csr_prm_rx_r_stl_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_port : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_p_his_cnt_u; + +/* Define the union csr_prm_rx_r_stf_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_srv_his_cnt_u; + +/* Define the union csr_prm_rx_r_stl_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_srv_his_cnt_u; + +/* Define the union csr_prm_rx_r_stf_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_srv_sh : 16; /* [15:0] */ + u32 rsv_43 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_srv_sh_his_cnt_u; + +/* Define the union csr_prm_rx_r_stl_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_srv_sh : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_srv_sh_his_cnt_u; + +/* Define the union csr_prm_rx_r_stf_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_st : 16; /* [15:0] */ + u32 rsv_45 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_st_his_cnt_u; + +/* Define the union csr_prm_rx_r_stl_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_st : 16; /* [15:0] */ + u32 rsv_46 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_st_his_cnt_u; + +/* Define the union csr_prm_rx_r_stf_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_47 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stf_st_sh_his_cnt_u; + +/* Define the union csr_prm_rx_r_stl_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_48 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_r_stl_st_sh_his_cnt_u; + +/* Define the union csr_prm_rx_stfiq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_iq_icb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stfiq_aloc_u; + +/* Define the union csr_prm_rx_stliq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_iq_icb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stliq_aloc_u; + +/* Define the union csr_prm_rx_yda_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_yda_daloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_yda_daloc_u; + +/* Define the union csr_prm_rx_stfiq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_iq_icb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stfiq_aloc_cnt_u; + +/* Define the union csr_prm_rx_stliq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_iq_icb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_stliq_aloc_cnt_u; + +/* Define the union csr_prm_rx_yda_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_yda_daloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_yda_daloc_cnt_u; + +/* Define the union csr_prm_rx_y_stf_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_port : 16; /* [15:0] */ + u32 rsv_49 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_p_his_cnt_u; + +/* Define the union csr_prm_rx_y_stl_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_port : 16; /* [15:0] */ + u32 rsv_50 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_p_his_cnt_u; + +/* Define the union csr_prm_rx_y_stf_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_st : 16; /* [15:0] */ + u32 rsv_51 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_st_his_cnt_u; + +/* Define the union csr_prm_rx_y_stl_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_st : 16; /* [15:0] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_st_his_cnt_u; + +/* Define the union csr_prm_rx_y_stf_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_53 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stf_st_sh_his_cnt_u; + +/* Define the union csr_prm_rx_y_stl_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_y_stl_st_sh_his_cnt_u; + +/* Define the union csr_prm_rx_g_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_55 : 1; /* [3] */ + u32 bmn_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_56 : 3; /* [11:9] */ + u32 bmn_cfg_mon_side : 1; /* [12] */ + u32 rsv_57 : 3; /* [15:13] */ + u32 bmn_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_58 : 2; /* [19:18] */ + u32 bmn_cfg_cnt_en : 1; /* [20] */ + u32 rsv_59 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_g_mon_cfg_u; + +/* Define the union csr_prm_rx_g_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_cfg_his_cnt_cos : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 bmn_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_61 : 3; /* [11:9] */ + u32 rsv_62 : 1; /* [12] */ + u32 rsv_63 : 3; /* [15:13] */ + u32 bmn_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_64 : 3; /* [19:17] */ + u32 bmn_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_65 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_g_his_cfg_u; + +/* Define the union csr_prm_rx_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_cpb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_aloc_u; + +/* Define the union csr_prm_rx_grq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_grq_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_grq_aloc_u; + +/* Define the union csr_prm_rx_grq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_grq_daloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_grq_daloc_u; + +/* Define the union csr_prm_rx_cpb_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_cpb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cpb_aloc_cnt_u; + +/* Define the union csr_prm_rx_grq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_grq_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_grq_aloc_cnt_u; + +/* Define the union csr_prm_rx_grq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_grq_daloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_grq_daloc_cnt_u; + +/* Define the union csr_prm_rx_n_cos_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_his_cnt_cos : 16; /* [15:0] */ + u32 rsv_66 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_n_cos_his_cnt_u; + +/* Define the union csr_prm_rx_n_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_his_cnt_port : 16; /* [15:0] */ + u32 rsv_67 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_n_p_his_cnt_u; + +/* Define the union csr_prm_rx_n_p_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_his_sh_cnt_port : 16; /* [15:0] */ + u32 rsv_68 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_n_p_sh_his_cnt_u; + +/* Define the union csr_prm_rx_n_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_69 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_n_srv_his_cnt_u; + +/* Define the union csr_prm_rx_n_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmn_his_sh_cnt_srv : 16; /* [15:0] */ + u32 rsv_70 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_n_srv_sh_his_cnt_u; + +/* Define the union csr_prm_rx_glb_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_rsvd_th : 16; /* [15:0] */ + u32 rsv_71 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_rsvd_cfg_u; + +/* Define the union csr_prm_rx_glb_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc0_th_on : 16; /* [15:0] */ + u32 glb_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_72 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_fc_th_cfg0_u; + +/* Define the union csr_prm_rx_glb_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc1_th_on : 16; /* [15:0] */ + u32 glb_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_73 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_fc_th_cfg1_u; + +/* Define the union csr_prm_rx_glb_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc2_th_on : 16; /* [15:0] */ + u32 glb_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_74 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_fc_th_cfg2_u; + +/* Define the union csr_prm_rx_glb_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_drp_th_on : 16; /* [15:0] */ + u32 glb_drp_th_dif : 8; /* [23:16] */ + u32 rsv_75 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_drp_th_cfg_u; + +/* Define the union csr_prm_rx_pg0_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_rsvd_th : 16; /* [15:0] */ + u32 rsv_76 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_rsvd_cfg_u; + +/* Define the union csr_prm_rx_pg0_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_fc0_th_on : 16; /* [15:0] */ + u32 pg0_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_77 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_fc_th_cfg0_u; + +/* Define the union csr_prm_rx_pg0_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_fc1_th_on : 16; /* [15:0] */ + u32 pg0_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_78 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_fc_th_cfg1_u; + +/* Define the union csr_prm_rx_pg0_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_fc2_th_on : 16; /* [15:0] */ + u32 pg0_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_79 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_fc_th_cfg2_u; + +/* Define the union csr_prm_rx_pg0_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_drp_th_on : 16; /* [15:0] */ + u32 pg0_drp_th_dif : 8; /* [23:16] */ + u32 rsv_80 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_drp_th_cfg_u; + +/* Define the union csr_prm_rx_pg2_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_rsvd_th : 16; /* [15:0] */ + u32 rsv_81 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_rsvd_cfg_u; + +/* Define the union csr_prm_rx_pg2_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc0_th_on : 16; /* [15:0] */ + u32 pg2_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_82 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_fc_th_cfg0_u; + +/* Define the union csr_prm_rx_pg2_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc1_th_on : 16; /* [15:0] */ + u32 pg2_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_83 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_fc_th_cfg1_u; + +/* Define the union csr_prm_rx_pg2_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc2_th_on : 16; /* [15:0] */ + u32 pg2_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_84 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_fc_th_cfg2_u; + +/* Define the union csr_prm_rx_pg2_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_drp_th_on : 16; /* [15:0] */ + u32 pg2_drp_th_dif : 8; /* [23:16] */ + u32 rsv_85 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_drp_th_cfg_u; + +/* Define the union csr_prm_rx_pg3_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_rsvd_th : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_rsvd_cfg_u; + +/* Define the union csr_prm_rx_pg3_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc0_th_on : 16; /* [15:0] */ + u32 pg3_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_87 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_fc_th_cfg0_u; + +/* Define the union csr_prm_rx_pg3_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc1_th_on : 16; /* [15:0] */ + u32 pg3_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_88 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_fc_th_cfg1_u; + +/* Define the union csr_prm_rx_pg3_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc2_th_on : 16; /* [15:0] */ + u32 pg3_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_89 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_fc_th_cfg2_u; + +/* Define the union csr_prm_rx_pg3_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_drp_th_on : 16; /* [15:0] */ + u32 pg3_drp_th_dif : 8; /* [23:16] */ + u32 rsv_90 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_drp_th_cfg_u; + +/* Define the union csr_prm_rx_pg0_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg0_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg0_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg0_cnt_u; + +/* Define the union csr_prm_rx_pg2_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg2_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg2_cnt_u; + +/* Define the union csr_prm_rx_pg3_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg3_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pg3_cnt_u; + +/* Define the union csr_prm_rx_glb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_curr_sh_cnt_st : 16; /* [15:0] */ + u32 glb_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_cnt_u; + +/* Define the union csr_prm_rx_glb_max_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_glb_max_th : 16; /* [15:0] */ + u32 cfg_glb_max_sh : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_glb_max_cnt_cfg_u; + +/* Define the union csr_prm_rx_ipsu_bp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ipsurx_bp_all_th : 16; /* [15:0] */ + u32 ipsurx_bp_rand_th : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_ipsu_bp_th_cfg_u; + +/* Define the union csr_prm_rx_bmn_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_bmn_wrr_wgt_cfg : 8; /* [7:0] */ + u32 rsv_91 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_bmn_wrr_cfg_u; + +/* Define the union csr_prm_rx_bmy_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_bmy_wrr_wgt_cfg : 12; /* [11:0] */ + u32 rsv_92 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_bmy_wrr_cfg_u; + +/* Define the union csr_prm_rx_bmr_wrr_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_bmr_wrr_wgt_cfg0 : 24; /* [23:0] */ + u32 rsv_93 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_bmr_wrr_cfg0_u; + +/* Define the union csr_prm_rx_bmr_wrr_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_bmn_wrr_wgt_cfg1 : 12; /* [11:0] */ + u32 rsv_94 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_bmr_wrr_cfg1_u; + +/* Define the union csr_prm_rx_bmg_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rx_bmg_wrr_wgt_cfg : 16; /* [15:0] */ + u32 rsv_95 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_bmg_wrr_cfg_u; + +/* Define the union csr_prm_rx_cnt_over_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_cnt_cos_n_of : 1; /* [0] */ + u32 mem_cnt_p_n_of : 1; /* [1] */ + u32 mem_cnt_srv_n_of : 1; /* [2] */ + u32 mem_sh_cnt_p_n_of : 1; /* [3] */ + u32 mem_sh_cnt_srv_n_of : 1; /* [4] */ + u32 mem_cnt_stf_p_y_of : 1; /* [5] */ + u32 mem_cnt_stf_srv_y_of : 1; /* [6] */ + u32 mem_sh_cnt_stf_srv_y_of : 1; /* [7] */ + u32 mem_cnt_stl_p_y_of : 1; /* [8] */ + u32 mem_cnt_stl_srv_y_of : 1; /* [9] */ + u32 mem_sh_cnt_stl_srv_y_of : 1; /* [10] */ + u32 mem_cnt_stf_p_r_of : 1; /* [11] */ + u32 mem_cnt_stf_srv_r_of : 1; /* [12] */ + u32 mem_sh_cnt_stf_srv_r_of : 1; /* [13] */ + u32 mem_cnt_stl_p_r_of : 1; /* [14] */ + u32 mem_cnt_stl_srv_r_of : 1; /* [15] */ + u32 mem_sh_cnt_stl_srv_r_of : 1; /* [16] */ + u32 glb_cnt_of : 1; /* [17] */ + u32 pg3_cnt_of : 1; /* [18] */ + u32 pg2_cnt_of : 1; /* [19] */ + u32 pg0_cnt_of : 1; /* [20] */ + u32 glb_sh_cnt_of : 1; /* [21] */ + u32 pg3_sh_cnt_of : 1; /* [22] */ + u32 pg2_sh_cnt_of : 1; /* [23] */ + u32 pg0_sh_cnt_of : 1; /* [24] */ + u32 rsv_96 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cnt_over_flag_u; + +/* Define the union csr_prm_rx_cnt_under_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_cnt_cos_n_uf : 1; /* [0] */ + u32 mem_cnt_p_n_uf : 1; /* [1] */ + u32 mem_cnt_srv_n_uf : 1; /* [2] */ + u32 mem_sh_cnt_p_n_uf : 1; /* [3] */ + u32 mem_sh_cnt_srv_n_uf : 1; /* [4] */ + u32 mem_cnt_stf_p_y_uf : 1; /* [5] */ + u32 mem_cnt_stf_srv_y_uf : 1; /* [6] */ + u32 mem_sh_cnt_stf_srv_y_uf : 1; /* [7] */ + u32 mem_cnt_stl_p_y_uf : 1; /* [8] */ + u32 mem_cnt_stl_srv_y_uf : 1; /* [9] */ + u32 mem_sh_cnt_stl_srv_y_uf : 1; /* [10] */ + u32 mem_cnt_stf_p_r_uf : 1; /* [11] */ + u32 mem_cnt_stf_srv_r_uf : 1; /* [12] */ + u32 mem_sh_cnt_stf_srv_r_uf : 1; /* [13] */ + u32 mem_cnt_stl_p_r_uf : 1; /* [14] */ + u32 mem_cnt_stl_srv_r_uf : 1; /* [15] */ + u32 mem_sh_cnt_stl_srv_r_uf : 1; /* [16] */ + u32 glb_cnt_uf : 1; /* [17] */ + u32 pg3_cnt_uf : 1; /* [18] */ + u32 pg2_cnt_uf : 1; /* [19] */ + u32 pg0_cnt_uf : 1; /* [20] */ + u32 glb_sh_cnt_uf : 1; /* [21] */ + u32 pg3_sh_cnt_uf : 1; /* [22] */ + u32 pg2_sh_cnt_uf : 1; /* [23] */ + u32 pg0_sh_cnt_uf : 1; /* [24] */ + u32 rsv_97 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_cnt_under_flag_u; + +/* Define the union csr_prm_rx_fifo_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stffq1_daloc_n_af_th : 5; /* [4:0] */ + u32 stffq1_aloc_n_af_th : 5; /* [9:5] */ + u32 stffq0_daloc_n_af_th : 5; /* [14:10] */ + u32 stffq0_aloc_n_af_th : 5; /* [19:15] */ + u32 stlfq_daloc_n_af_th : 5; /* [24:20] */ + u32 stlfq_aloc_n_af_th : 5; /* [29:25] */ + u32 rsv_98 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_fifo_th_cfg0_u; + +/* Define the union csr_prm_rx_fifo_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_n_af_th : 5; /* [4:0] */ + u32 stliq_n_af_th : 5; /* [9:5] */ + u32 oq_daloc_n_af_th : 5; /* [14:10] */ + u32 rsv_99 : 5; /* [19:15] */ + u32 rsv_100 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_fifo_th_cfg1_u; + +/* Define the union csr_prm_rx_fifo_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_aloc_n_af_th : 6; /* [5:0] */ + u32 rsv_101 : 2; /* [7:6] */ + u32 cpb_daloc_n_af_th : 6; /* [13:8] */ + u32 rsv_102 : 2; /* [15:14] */ + u32 rsv_103 : 7; /* [22:16] */ + u32 rsv_104 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_fifo_th_cfg2_u; + +/* Define the union csr_prm_rx_double_daloc_wgt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_stl_daloc_pg3_wgt_cfg : 8; /* [7:0] */ + u32 stf_stl_daloc_pg2_wgt_cfg : 8; /* [15:8] */ + u32 rsv_105 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_double_daloc_wgt_u; + +/* Define the union csr_prm_rx_pqm_uload_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_pqm_underloading_th : 16; /* [15:0] */ + u32 rsv_106 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_pqm_uload_cfg_u; + +/* Define the union csr_prm_rx_err_src_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_uder_src_err : 9; /* [8:0] */ + u32 cos_over_src_err : 9; /* [17:9] */ + u32 rsv_107 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_rx_err_src_u; + +/* Define the union csr_prmrx_bw_monitor_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_cpb_aloc_bdmonitor_en : 1; /* [0] */ + u32 csr_prmrx_cpb_daloc_bdmonitor_en : 1; /* [1] */ + u32 csr_prmrx_cpb_src1_daloc_bdmonitor_en : 1; /* [2] */ + u32 csr_prmrx_cpb_drop_bdmonitor_en : 1; /* [3] */ + u32 csr_prmrx_stliq_bdmonitor_en : 1; /* [4] */ + u32 csr_prmrx_stfiq_bdmonitor_en : 1; /* [5] */ + u32 csr_prmrx_stlfq_aloc_bdmonitor_en : 1; /* [6] */ + u32 csr_prmrx_stffq0_aloc_bdmonitor_en : 1; /* [7] */ + u32 csr_prmrx_stffq1_aloc_bdmonitor_en : 1; /* [8] */ + u32 csr_prmrx_stlfq_daloc_bdmonitor_en : 1; /* [9] */ + u32 csr_prmrx_stffq0_daloc_bdmonitor_en : 1; /* [10] */ + u32 csr_prmrx_stffq1_daloc_bdmonitor_en : 1; /* [11] */ + u32 csr_prmrx_oq_daloc_bdmonitor_en : 1; /* [12] */ + u32 rsv_108 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_en_u; + +/* Define the union csr_prmrx_bw_monitor_win_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_win_len : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_win_len_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_cpb_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_cpb_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_cpb_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_cpb_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_cpb_src1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_cpb_src1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_cpb_src1_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_cpb_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_cpb_drop_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stliq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stliq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stliq_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stfiq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stfiq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stfiq_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stlfq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stlfq_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stffq0_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stffq0_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stffq1_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stffq1_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stlfq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stlfq_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stffq0_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stffq0_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_stffq1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_stffq1_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_max_times_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmrx_bdmonitro_max_times_oq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_max_times_oq_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_win_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_win_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_win_cnt_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_cpb_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_cpb_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_cpb_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_cpb_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_cpb_src1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_cpb_src1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_cpb_src1_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_cpb_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_cpb_drop_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stliq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stliq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stliq_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stfiq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stfiq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stfiq_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stlfq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stffq0_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stffq1_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_aloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stlfq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stffq0_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_stffq1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_daloc_u; + +/* Define the union csr_prmrx_bw_monitor_over_max_times_cnt_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmrx_csr_bdmonitor_over_max_cnt_oq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmrx_bw_monitor_over_max_times_cnt_oq_daloc_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_prm_rx_indrect_ctrl_u prm_rx_indrect_ctrl; /* 0 */ + volatile csr_prm_rx_indrect_timeout_u prm_rx_indrect_timeout; /* 4 */ + volatile csr_prm_rx_indrect_dat0_u prm_rx_indrect_dat0; /* 8 */ + volatile csr_prm_rx_indrect_dat1_u prm_rx_indrect_dat1; /* C */ + volatile csr_prm_rx_indrect_dat2_u prm_rx_indrect_dat2; /* 10 */ + volatile csr_prm_rx_indrect_dat3_u prm_rx_indrect_dat3; /* 14 */ + volatile csr_prm_rx_csr_cfg_u prm_rx_csr_cfg; /* 30 */ + volatile csr_prm_rx_y_stf_fc_th_cfg_u prm_rx_y_stf_fc_th_cfg; /* 34 */ + volatile csr_prm_rx_y_stl_fc_th_cfg_u prm_rx_y_stl_fc_th_cfg; /* 38 */ + volatile csr_prm_rx_r_stf_fc_th_cfg_u prm_rx_r_stf_fc_th_cfg; /* 3C */ + volatile csr_prm_rx_r_stl_fc_th_cfg_u prm_rx_r_stl_fc_th_cfg; /* 40 */ + volatile csr_prm_rx_y_stf_rsvd_cfg_u prm_rx_y_stf_rsvd_cfg; /* 44 */ + volatile csr_prm_rx_y_stl_rsvd_cfg_u prm_rx_y_stl_rsvd_cfg; /* 48 */ + volatile csr_prm_rx_r_stf_rsvd_cfg_u prm_rx_r_stf_rsvd_cfg; /* 4C */ + volatile csr_prm_rx_r_stl_rsvd_cfg_u prm_rx_r_stl_rsvd_cfg; /* 50 */ + volatile csr_prm_rx_y_stf_cnt_u prm_rx_y_stf_cnt; /* 54 */ + volatile csr_prm_rx_y_stl_cnt_u prm_rx_y_stl_cnt; /* 58 */ + volatile csr_prm_rx_r_stf_cnt_u prm_rx_r_stf_cnt; /* 5C */ + volatile csr_prm_rx_r_stl_cnt_u prm_rx_r_stl_cnt; /* 60 */ + volatile csr_prm_rx_y_stf_sh_cnt_u prm_rx_y_stf_sh_cnt; /* 64 */ + volatile csr_prm_rx_y_stl_sh_cnt_u prm_rx_y_stl_sh_cnt; /* 68 */ + volatile csr_prm_rx_r_stf_sh_cnt_u prm_rx_r_stf_sh_cnt; /* 6C */ + volatile csr_prm_rx_r_stl_sh_cnt_u prm_rx_r_stl_sh_cnt; /* 70 */ + volatile csr_prm_rx_y_mon_cfg_u prm_rx_y_mon_cfg; /* 74 */ + volatile csr_prm_rx_y_his_cfg_u prm_rx_y_his_cfg; /* 78 */ + volatile csr_prm_rx_r_mon_cfg_u prm_rx_r_mon_cfg; /* 7C */ + volatile csr_prm_rx_r_his_cfg_u prm_rx_r_his_cfg; /* 80 */ + volatile csr_prm_rx_stlfq_aloc_u prm_rx_stlfq_aloc; /* 84 */ + volatile csr_prm_rx_stffq0_aloc_u prm_rx_stffq0_aloc; /* 88 */ + volatile csr_prm_rx_stffq1_aloc_u prm_rx_stffq1_aloc; /* 8C */ + volatile csr_prm_rx_stlfq_daloc_u prm_rx_stlfq_daloc; /* 90 */ + volatile csr_prm_rx_stffq0_daloc_u prm_rx_stffq0_daloc; /* 94 */ + volatile csr_prm_rx_stffq1_daloc_u prm_rx_stffq1_daloc; /* 98 */ + volatile csr_prm_rx_cpb_daloc_u prm_rx_cpb_daloc; /* 9C */ + volatile csr_prm_rx_cpb_drop_u prm_rx_cpb_drop; /* A0 */ + volatile csr_prm_rx_oq_daloc_u prm_rx_oq_daloc; /* A4 */ + volatile csr_prm_rx_stlfq_aloc_cnt_u prm_rx_stlfq_aloc_cnt; /* A8 */ + volatile csr_prm_rx_stffq0_aloc_cnt_u prm_rx_stffq0_aloc_cnt; /* AC */ + volatile csr_prm_rx_stffq1_aloc_cnt_u prm_rx_stffq1_aloc_cnt; /* B0 */ + volatile csr_prm_rx_stlfq_daloc_cnt_u prm_rx_stlfq_daloc_cnt; /* B4 */ + volatile csr_prm_rx_stffq0_daloc_cnt_u prm_rx_stffq0_daloc_cnt; /* B8 */ + volatile csr_prm_rx_stffq1_daloc_cnt_u prm_rx_stffq1_daloc_cnt; /* BC */ + volatile csr_prm_rx_cpb_daloc_cnt_u prm_rx_cpb_daloc_cnt; /* C0 */ + volatile csr_prm_rx_cpb_drop_cnt_u prm_rx_cpb_drop_cnt; /* C4 */ + volatile csr_prm_rx_oq_daloc_cnt_u prm_rx_oq_daloc_cnt; /* C8 */ + volatile csr_prm_rx_r_stf_p_his_cnt_u prm_rx_r_stf_p_his_cnt; /* CC */ + volatile csr_prm_rx_r_stl_p_his_cnt_u prm_rx_r_stl_p_his_cnt; /* D0 */ + volatile csr_prm_rx_r_stf_srv_his_cnt_u prm_rx_r_stf_srv_his_cnt; /* D4 */ + volatile csr_prm_rx_r_stl_srv_his_cnt_u prm_rx_r_stl_srv_his_cnt; /* D8 */ + volatile csr_prm_rx_r_stf_srv_sh_his_cnt_u prm_rx_r_stf_srv_sh_his_cnt; /* DC */ + volatile csr_prm_rx_r_stl_srv_sh_his_cnt_u prm_rx_r_stl_srv_sh_his_cnt; /* E0 */ + volatile csr_prm_rx_r_stf_st_his_cnt_u prm_rx_r_stf_st_his_cnt; /* E4 */ + volatile csr_prm_rx_r_stl_st_his_cnt_u prm_rx_r_stl_st_his_cnt; /* E8 */ + volatile csr_prm_rx_r_stf_st_sh_his_cnt_u prm_rx_r_stf_st_sh_his_cnt; /* EC */ + volatile csr_prm_rx_r_stl_st_sh_his_cnt_u prm_rx_r_stl_st_sh_his_cnt; /* F0 */ + volatile csr_prm_rx_stfiq_aloc_u prm_rx_stfiq_aloc; /* F4 */ + volatile csr_prm_rx_stliq_aloc_u prm_rx_stliq_aloc; /* F8 */ + volatile csr_prm_rx_yda_daloc_u prm_rx_yda_daloc; /* FC */ + volatile csr_prm_rx_stfiq_aloc_cnt_u prm_rx_stfiq_aloc_cnt; /* 100 */ + volatile csr_prm_rx_stliq_aloc_cnt_u prm_rx_stliq_aloc_cnt; /* 104 */ + volatile csr_prm_rx_yda_daloc_cnt_u prm_rx_yda_daloc_cnt; /* 108 */ + volatile csr_prm_rx_y_stf_p_his_cnt_u prm_rx_y_stf_p_his_cnt; /* 10C */ + volatile csr_prm_rx_y_stl_p_his_cnt_u prm_rx_y_stl_p_his_cnt; /* 110 */ + volatile csr_prm_rx_y_stf_st_his_cnt_u prm_rx_y_stf_st_his_cnt; /* 114 */ + volatile csr_prm_rx_y_stl_st_his_cnt_u prm_rx_y_stl_st_his_cnt; /* 118 */ + volatile csr_prm_rx_y_stf_st_sh_his_cnt_u prm_rx_y_stf_st_sh_his_cnt; /* 11C */ + volatile csr_prm_rx_y_stl_st_sh_his_cnt_u prm_rx_y_stl_st_sh_his_cnt; /* 120 */ + volatile csr_prm_rx_g_mon_cfg_u prm_rx_g_mon_cfg; /* 124 */ + volatile csr_prm_rx_g_his_cfg_u prm_rx_g_his_cfg; /* 128 */ + volatile csr_prm_rx_cpb_aloc_u prm_rx_cpb_aloc; /* 12C */ + volatile csr_prm_rx_grq_aloc_u prm_rx_grq_aloc; /* 130 */ + volatile csr_prm_rx_grq_daloc_u prm_rx_grq_daloc; /* 134 */ + volatile csr_prm_rx_cpb_aloc_cnt_u prm_rx_cpb_aloc_cnt; /* 138 */ + volatile csr_prm_rx_grq_aloc_cnt_u prm_rx_grq_aloc_cnt; /* 13C */ + volatile csr_prm_rx_grq_daloc_cnt_u prm_rx_grq_daloc_cnt; /* 140 */ + volatile csr_prm_rx_n_cos_his_cnt_u prm_rx_n_cos_his_cnt; /* 144 */ + volatile csr_prm_rx_n_p_his_cnt_u prm_rx_n_p_his_cnt; /* 148 */ + volatile csr_prm_rx_n_p_sh_his_cnt_u prm_rx_n_p_sh_his_cnt; /* 14C */ + volatile csr_prm_rx_n_srv_his_cnt_u prm_rx_n_srv_his_cnt; /* 150 */ + volatile csr_prm_rx_n_srv_sh_his_cnt_u prm_rx_n_srv_sh_his_cnt; /* 154 */ + volatile csr_prm_rx_glb_rsvd_cfg_u prm_rx_glb_rsvd_cfg; /* 158 */ + volatile csr_prm_rx_glb_fc_th_cfg0_u prm_rx_glb_fc_th_cfg0; /* 15C */ + volatile csr_prm_rx_glb_fc_th_cfg1_u prm_rx_glb_fc_th_cfg1; /* 160 */ + volatile csr_prm_rx_glb_fc_th_cfg2_u prm_rx_glb_fc_th_cfg2; /* 164 */ + volatile csr_prm_rx_glb_drp_th_cfg_u prm_rx_glb_drp_th_cfg; /* 168 */ + volatile csr_prm_rx_pg0_rsvd_cfg_u prm_rx_pg0_rsvd_cfg; /* 16C */ + volatile csr_prm_rx_pg0_fc_th_cfg0_u prm_rx_pg0_fc_th_cfg0; /* 170 */ + volatile csr_prm_rx_pg0_fc_th_cfg1_u prm_rx_pg0_fc_th_cfg1; /* 174 */ + volatile csr_prm_rx_pg0_fc_th_cfg2_u prm_rx_pg0_fc_th_cfg2; /* 178 */ + volatile csr_prm_rx_pg0_drp_th_cfg_u prm_rx_pg0_drp_th_cfg; /* 17C */ + volatile csr_prm_rx_pg2_rsvd_cfg_u prm_rx_pg2_rsvd_cfg; /* 180 */ + volatile csr_prm_rx_pg2_fc_th_cfg0_u prm_rx_pg2_fc_th_cfg0; /* 184 */ + volatile csr_prm_rx_pg2_fc_th_cfg1_u prm_rx_pg2_fc_th_cfg1; /* 188 */ + volatile csr_prm_rx_pg2_fc_th_cfg2_u prm_rx_pg2_fc_th_cfg2; /* 18C */ + volatile csr_prm_rx_pg2_drp_th_cfg_u prm_rx_pg2_drp_th_cfg; /* 190 */ + volatile csr_prm_rx_pg3_rsvd_cfg_u prm_rx_pg3_rsvd_cfg; /* 194 */ + volatile csr_prm_rx_pg3_fc_th_cfg0_u prm_rx_pg3_fc_th_cfg0; /* 198 */ + volatile csr_prm_rx_pg3_fc_th_cfg1_u prm_rx_pg3_fc_th_cfg1; /* 19C */ + volatile csr_prm_rx_pg3_fc_th_cfg2_u prm_rx_pg3_fc_th_cfg2; /* 1A0 */ + volatile csr_prm_rx_pg3_drp_th_cfg_u prm_rx_pg3_drp_th_cfg; /* 1A4 */ + volatile csr_prm_rx_pg0_cnt_u prm_rx_pg0_cnt; /* 1A8 */ + volatile csr_prm_rx_pg2_cnt_u prm_rx_pg2_cnt; /* 1AC */ + volatile csr_prm_rx_pg3_cnt_u prm_rx_pg3_cnt; /* 1B0 */ + volatile csr_prm_rx_glb_cnt_u prm_rx_glb_cnt; /* 1B4 */ + volatile csr_prm_rx_glb_max_cnt_cfg_u prm_rx_glb_max_cnt_cfg; /* 1B8 */ + volatile csr_prm_rx_ipsu_bp_th_cfg_u prm_rx_ipsu_bp_th_cfg; /* 1BC */ + volatile csr_prm_rx_bmn_wrr_cfg_u prm_rx_bmn_wrr_cfg; /* 1C0 */ + volatile csr_prm_rx_bmy_wrr_cfg_u prm_rx_bmy_wrr_cfg; /* 1C4 */ + volatile csr_prm_rx_bmr_wrr_cfg0_u prm_rx_bmr_wrr_cfg0; /* 1C8 */ + volatile csr_prm_rx_bmr_wrr_cfg1_u prm_rx_bmr_wrr_cfg1; /* 1CC */ + volatile csr_prm_rx_bmg_wrr_cfg_u prm_rx_bmg_wrr_cfg; /* 1D0 */ + volatile csr_prm_rx_cnt_over_flag_u prm_rx_cnt_over_flag; /* 1D4 */ + volatile csr_prm_rx_cnt_under_flag_u prm_rx_cnt_under_flag; /* 1D8 */ + volatile csr_prm_rx_fifo_th_cfg0_u prm_rx_fifo_th_cfg0; /* 1E0 */ + volatile csr_prm_rx_fifo_th_cfg1_u prm_rx_fifo_th_cfg1; /* 1E4 */ + volatile csr_prm_rx_fifo_th_cfg2_u prm_rx_fifo_th_cfg2; /* 1E8 */ + volatile csr_prm_rx_double_daloc_wgt_u prm_rx_double_daloc_wgt; /* 1EC */ + volatile csr_prm_rx_pqm_uload_cfg_u prm_rx_pqm_uload_cfg; /* 1F0 */ + volatile csr_prm_rx_err_src_u prm_rx_err_src; /* 1F4 */ + volatile csr_prmrx_bw_monitor_en_u prmrx_bw_monitor_en; /* 230 */ + volatile csr_prmrx_bw_monitor_win_len_u prmrx_bw_monitor_win_len; /* 234 */ + volatile csr_prmrx_bw_monitor_max_times_cpb_aloc_u prmrx_bw_monitor_max_times_cpb_aloc; /* 238 */ + volatile csr_prmrx_bw_monitor_max_times_cpb_daloc_u prmrx_bw_monitor_max_times_cpb_daloc; /* 23C */ + volatile csr_prmrx_bw_monitor_max_times_cpb_src1_daloc_u prmrx_bw_monitor_max_times_cpb_src1_daloc; /* 240 */ + volatile csr_prmrx_bw_monitor_max_times_cpb_drop_u prmrx_bw_monitor_max_times_cpb_drop; /* 244 */ + volatile csr_prmrx_bw_monitor_max_times_stliq_u prmrx_bw_monitor_max_times_stliq; /* 248 */ + volatile csr_prmrx_bw_monitor_max_times_stfiq_u prmrx_bw_monitor_max_times_stfiq; /* 24C */ + volatile csr_prmrx_bw_monitor_max_times_stlfq_aloc_u prmrx_bw_monitor_max_times_stlfq_aloc; /* 250 */ + volatile csr_prmrx_bw_monitor_max_times_stffq0_aloc_u prmrx_bw_monitor_max_times_stffq0_aloc; /* 254 */ + volatile csr_prmrx_bw_monitor_max_times_stffq1_aloc_u prmrx_bw_monitor_max_times_stffq1_aloc; /* 258 */ + volatile csr_prmrx_bw_monitor_max_times_stlfq_daloc_u prmrx_bw_monitor_max_times_stlfq_daloc; /* 25C */ + volatile csr_prmrx_bw_monitor_max_times_stffq0_daloc_u prmrx_bw_monitor_max_times_stffq0_daloc; /* 260 */ + volatile csr_prmrx_bw_monitor_max_times_stffq1_daloc_u prmrx_bw_monitor_max_times_stffq1_daloc; /* 264 */ + volatile csr_prmrx_bw_monitor_max_times_oq_daloc_u prmrx_bw_monitor_max_times_oq_daloc; /* 268 */ + volatile csr_prmrx_bw_monitor_win_cnt_u prmrx_bw_monitor_win_cnt; /* 26C */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_cpb_aloc_u prmrx_bw_monitor_over_max_times_cnt_cpb_aloc; /* 270 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_cpb_daloc_u prmrx_bw_monitor_over_max_times_cnt_cpb_daloc; /* 274 + */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_cpb_src1_daloc_u + prmrx_bw_monitor_over_max_times_cnt_cpb_src1_daloc; /* 278 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_cpb_drop_u prmrx_bw_monitor_over_max_times_cnt_cpb_drop; /* 27C */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stliq_u prmrx_bw_monitor_over_max_times_cnt_stliq; /* 280 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stfiq_u prmrx_bw_monitor_over_max_times_cnt_stfiq; /* 284 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_aloc_u prmrx_bw_monitor_over_max_times_cnt_stlfq_aloc; /* 288 + */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_aloc_u + prmrx_bw_monitor_over_max_times_cnt_stffq0_aloc; /* 28C */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_aloc_u + prmrx_bw_monitor_over_max_times_cnt_stffq1_aloc; /* 290 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stlfq_daloc_u + prmrx_bw_monitor_over_max_times_cnt_stlfq_daloc; /* 294 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stffq0_daloc_u + prmrx_bw_monitor_over_max_times_cnt_stffq0_daloc; /* 298 */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_stffq1_daloc_u + prmrx_bw_monitor_over_max_times_cnt_stffq1_daloc; /* 29C */ + volatile csr_prmrx_bw_monitor_over_max_times_cnt_oq_daloc_u prmrx_bw_monitor_over_max_times_cnt_oq_daloc; /* 2A0 */ +} S_qu_prm_rx_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_prm_rx_csr */ +extern volatile S_qu_prm_rx_csr_REGS_TYPE *gopqu_prm_rx_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetPRM_RX_INDRECT_CTRL_indirect_ctrl(unsigned int uindirect_ctrl); +int iSetPRM_RX_INDRECT_TIMEOUT_indirect_timeout(unsigned int uindirect_timeout); +int iSetPRM_RX_INDRECT_DAT0_indirect_dat0(unsigned int uindirect_dat0); +int iSetPRM_RX_INDRECT_DAT1_indirect_dat1(unsigned int uindirect_dat1); +int iSetPRM_RX_INDRECT_DAT2_indirect_dat2(unsigned int uindirect_dat2); +int iSetPRM_RX_INDRECT_DAT3_indirect_dat3(unsigned int uindirect_dat3); +int iSetPRM_RX_CSR_CFG_dyn_csr_req_src(unsigned int udyn_csr_req_src); +int iSetPRM_RX_CSR_CFG_bmr_dyn_csr_req(unsigned int ubmr_dyn_csr_req); +int iSetPRM_RX_CSR_CFG_bmy_dyn_csr_req(unsigned int ubmy_dyn_csr_req); +int iSetPRM_RX_CSR_CFG_bmn_dyn_csr_req(unsigned int ubmn_dyn_csr_req); +int iSetPRM_RX_Y_STF_FC_TH_CFG_stf_state_y_fc0_th_on(unsigned int ustf_state_y_fc0_th_on); +int iSetPRM_RX_Y_STF_FC_TH_CFG_stf_state_y_fc0_th_dif(unsigned int ustf_state_y_fc0_th_dif); +int iSetPRM_RX_Y_STL_FC_TH_CFG_stl_state_y_fc0_th_on(unsigned int ustl_state_y_fc0_th_on); +int iSetPRM_RX_Y_STL_FC_TH_CFG_stl_state_y_fc0_th_dif(unsigned int ustl_state_y_fc0_th_dif); +int iSetPRM_RX_R_STF_FC_TH_CFG_stf_state_r_fc0_th_on(unsigned int ustf_state_r_fc0_th_on); +int iSetPRM_RX_R_STF_FC_TH_CFG_stf_state_r_fc0_th_dif(unsigned int ustf_state_r_fc0_th_dif); +int iSetPRM_RX_R_STL_FC_TH_CFG_stl_state_r_fc0_th_on(unsigned int ustl_state_r_fc0_th_on); +int iSetPRM_RX_R_STL_FC_TH_CFG_stl_state_r_fc0_th_dif(unsigned int ustl_state_r_fc0_th_dif); +int iSetPRM_RX_Y_STF_RSVD_CFG_stf_state_y_rsvd(unsigned int ustf_state_y_rsvd); +int iSetPRM_RX_Y_STL_RSVD_CFG_stl_state_y_rsvd(unsigned int ustl_state_y_rsvd); +int iSetPRM_RX_R_STF_RSVD_CFG_stf_state_r_rsvd(unsigned int ustf_state_r_rsvd); +int iSetPRM_RX_R_STL_RSVD_CFG_stl_state_r_rsvd(unsigned int ustl_state_r_rsvd); +int iSetPRM_RX_Y_STF_CNT_stf_state_y_cnt(unsigned int ustf_state_y_cnt); +int iSetPRM_RX_Y_STL_CNT_stl_state_y_cnt(unsigned int ustl_state_y_cnt); +int iSetPRM_RX_R_STF_CNT_stf_state_r_cnt(unsigned int ustf_state_r_cnt); +int iSetPRM_RX_R_STL_CNT_stl_state_r_cnt(unsigned int ustl_state_r_cnt); +int iSetPRM_RX_Y_STF_SH_CNT_stf_state_y_sh_cnt(unsigned int ustf_state_y_sh_cnt); +int iSetPRM_RX_Y_STL_SH_CNT_stl_state_y_sh_cnt(unsigned int ustl_state_y_sh_cnt); +int iSetPRM_RX_R_STF_SH_CNT_stf_state_r_sh_cnt(unsigned int ustf_state_r_sh_cnt); +int iSetPRM_RX_R_STL_SH_CNT_stl_state_r_sh_cnt(unsigned int ustl_state_r_sh_cnt); +int iSetPRM_RX_Y_MON_CFG_bmy_cfg_mon_cos(unsigned int ubmy_cfg_mon_cos); +int iSetPRM_RX_Y_MON_CFG_bmy_cfg_mon_sp(unsigned int ubmy_cfg_mon_sp); +int iSetPRM_RX_Y_MON_CFG_bmy_cfg_mon_srv(unsigned int ubmy_cfg_mon_srv); +int iSetPRM_RX_Y_MON_CFG_bmy_cfg_cnt_type(unsigned int ubmy_cfg_cnt_type); +int iSetPRM_RX_Y_MON_CFG_bmy_cfg_cnt_en(unsigned int ubmy_cfg_cnt_en); +int iSetPRM_RX_Y_HIS_CFG_bmy_cfg_his_cnt_sp(unsigned int ubmy_cfg_his_cnt_sp); +int iSetPRM_RX_Y_HIS_CFG_bmy_cfg_his_cnt_srv(unsigned int ubmy_cfg_his_cnt_srv); +int iSetPRM_RX_Y_HIS_CFG_bmy_cfg_his_cnt_clr(unsigned int ubmy_cfg_his_cnt_clr); +int iSetPRM_RX_Y_HIS_CFG_bmy_cfg_his_cnt_en(unsigned int ubmy_cfg_his_cnt_en); +int iSetPRM_RX_R_MON_CFG_bmr_cfg_mon_cos(unsigned int ubmr_cfg_mon_cos); +int iSetPRM_RX_R_MON_CFG_bmr_cfg_mon_sp(unsigned int ubmr_cfg_mon_sp); +int iSetPRM_RX_R_MON_CFG_bmr_cfg_mon_srv(unsigned int ubmr_cfg_mon_srv); +int iSetPRM_RX_R_MON_CFG_bmr_cfg_cnt_type(unsigned int ubmr_cfg_cnt_type); +int iSetPRM_RX_R_MON_CFG_bmr_cfg_cnt_en(unsigned int ubmr_cfg_cnt_en); +int iSetPRM_RX_R_HIS_CFG_bmr_cfg_his_cnt_sp(unsigned int ubmr_cfg_his_cnt_sp); +int iSetPRM_RX_R_HIS_CFG_bmr_cfg_his_cnt_srv(unsigned int ubmr_cfg_his_cnt_srv); +int iSetPRM_RX_R_HIS_CFG_bmr_cfg_his_cnt_clr(unsigned int ubmr_cfg_his_cnt_clr); +int iSetPRM_RX_R_HIS_CFG_bmr_cfg_his_cnt_en(unsigned int ubmr_cfg_his_cnt_en); +int iSetPRM_RX_STLFQ_ALOC_bmr_stlfq_aloc_cnt_wr_v(unsigned int ubmr_stlfq_aloc_cnt_wr_v); +int iSetPRM_RX_STFFQ0_ALOC_bmr_stffq0_aloc_cnt_wr_v(unsigned int ubmr_stffq0_aloc_cnt_wr_v); +int iSetPRM_RX_STFFQ1_ALOC_bmr_stffq1_aloc_cnt_wr_v(unsigned int ubmr_stffq1_aloc_cnt_wr_v); +int iSetPRM_RX_STLFQ_DALOC_bmr_stlfq_daloc_cnt_wr_v(unsigned int ubmr_stlfq_daloc_cnt_wr_v); +int iSetPRM_RX_STFFQ0_DALOC_bmr_stffq0_daloc_cnt_wr_v(unsigned int ubmr_stffq0_daloc_cnt_wr_v); +int iSetPRM_RX_STFFQ1_DALOC_bmr_stffq1_daloc_cnt_wr_v(unsigned int ubmr_stffq1_daloc_cnt_wr_v); +int iSetPRM_RX_CPB_DALOC_bmr_cpb_daloc_cnt_wr_v(unsigned int ubmr_cpb_daloc_cnt_wr_v); +int iSetPRM_RX_CPB_DROP_bmr_cpb_drop_cnt_wr_v(unsigned int ubmr_cpb_drop_cnt_wr_v); +int iSetPRM_RX_OQ_DALOC_bmr_oq_daloc_cnt_wr_v(unsigned int ubmr_oq_daloc_cnt_wr_v); +int iSetPRM_RX_STLFQ_ALOC_CNT_bmr_stlfq_aloc_cnt_num_v(unsigned int ubmr_stlfq_aloc_cnt_num_v); +int iSetPRM_RX_STFFQ0_ALOC_CNT_bmr_stffq0_aloc_cnt_num_v(unsigned int ubmr_stffq0_aloc_cnt_num_v); +int iSetPRM_RX_STFFQ1_ALOC_CNT_bmr_stffq1_aloc_cnt_num_v(unsigned int ubmr_stffq1_aloc_cnt_num_v); +int iSetPRM_RX_STLFQ_DALOC_CNT_bmr_stlfq_daloc_cnt_num_v(unsigned int ubmr_stlfq_daloc_cnt_num_v); +int iSetPRM_RX_STFFQ0_DALOC_CNT_bmr_stffq0_daloc_cnt_num_v(unsigned int ubmr_stffq0_daloc_cnt_num_v); +int iSetPRM_RX_STFFQ1_DALOC_CNT_bmr_stffq1_daloc_cnt_num_v(unsigned int ubmr_stffq1_daloc_cnt_num_v); +int iSetPRM_RX_CPB_DALOC_CNT_bmr_cpb_daloc_cnt_num_v(unsigned int ubmr_cpb_daloc_cnt_num_v); +int iSetPRM_RX_CPB_DROP_CNT_bmr_cpb_drop_cnt_num_v(unsigned int ubmr_cpb_drop_cnt_num_v); +int iSetPRM_RX_OQ_DALOC_CNT_bmr_oq_daloc_cnt_num_v(unsigned int ubmr_oq_daloc_cnt_num_v); +int iSetPRM_RX_R_STF_P_HIS_CNT_bmr_stf_his_cnt_port(unsigned int ubmr_stf_his_cnt_port); +int iSetPRM_RX_R_STL_P_HIS_CNT_bmr_stl_his_cnt_port(unsigned int ubmr_stl_his_cnt_port); +int iSetPRM_RX_R_STF_SRV_HIS_CNT_bmr_stf_his_cnt_srv(unsigned int ubmr_stf_his_cnt_srv); +int iSetPRM_RX_R_STL_SRV_HIS_CNT_bmr_stl_his_cnt_srv(unsigned int ubmr_stl_his_cnt_srv); +int iSetPRM_RX_R_STF_SRV_SH_HIS_CNT_bmr_stf_his_cnt_srv_sh(unsigned int ubmr_stf_his_cnt_srv_sh); +int iSetPRM_RX_R_STL_SRV_SH_HIS_CNT_bmr_stl_his_cnt_srv_sh(unsigned int ubmr_stl_his_cnt_srv_sh); +int iSetPRM_RX_R_STF_ST_HIS_CNT_bmr_stf_his_cnt_st(unsigned int ubmr_stf_his_cnt_st); +int iSetPRM_RX_R_STL_ST_HIS_CNT_bmr_stl_his_cnt_st(unsigned int ubmr_stl_his_cnt_st); +int iSetPRM_RX_R_STF_ST_SH_HIS_CNT_bmr_stf_his_cnt_st_sh(unsigned int ubmr_stf_his_cnt_st_sh); +int iSetPRM_RX_R_STL_ST_SH_HIS_CNT_bmr_stl_his_cnt_st_sh(unsigned int ubmr_stl_his_cnt_st_sh); +int iSetPRM_RX_STFIQ_ALOC_bmy_stf_iq_icb_aloc_cnt_wr(unsigned int ubmy_stf_iq_icb_aloc_cnt_wr); +int iSetPRM_RX_STLIQ_ALOC_bmy_stl_iq_icb_aloc_cnt_wr(unsigned int ubmy_stl_iq_icb_aloc_cnt_wr); +int iSetPRM_RX_YDA_DALOC_bmy_yda_daloc_cnt_wr(unsigned int ubmy_yda_daloc_cnt_wr); +int iSetPRM_RX_STFIQ_ALOC_CNT_bmy_stf_iq_icb_aloc_cnt_num(unsigned int ubmy_stf_iq_icb_aloc_cnt_num); +int iSetPRM_RX_STLIQ_ALOC_CNT_bmy_stl_iq_icb_aloc_cnt_num(unsigned int ubmy_stl_iq_icb_aloc_cnt_num); +int iSetPRM_RX_YDA_DALOC_CNT_bmy_yda_daloc_cnt_num(unsigned int ubmy_yda_daloc_cnt_num); +int iSetPRM_RX_Y_STF_P_HIS_CNT_bmy_stf_his_cnt_port(unsigned int ubmy_stf_his_cnt_port); +int iSetPRM_RX_Y_STL_P_HIS_CNT_bmy_stl_his_cnt_port(unsigned int ubmy_stl_his_cnt_port); +int iSetPRM_RX_Y_STF_ST_HIS_CNT_bmy_stf_his_cnt_st(unsigned int ubmy_stf_his_cnt_st); +int iSetPRM_RX_Y_STL_ST_HIS_CNT_bmy_stl_his_cnt_st(unsigned int ubmy_stl_his_cnt_st); +int iSetPRM_RX_Y_STF_ST_SH_HIS_CNT_bmy_stf_his_cnt_st_sh(unsigned int ubmy_stf_his_cnt_st_sh); +int iSetPRM_RX_Y_STL_ST_SH_HIS_CNT_bmy_stl_his_cnt_st_sh(unsigned int ubmy_stl_his_cnt_st_sh); +int iSetPRM_RX_G_MON_CFG_bmn_cfg_mon_cos(unsigned int ubmn_cfg_mon_cos); +int iSetPRM_RX_G_MON_CFG_bmn_cfg_mon_sp(unsigned int ubmn_cfg_mon_sp); +int iSetPRM_RX_G_MON_CFG_bmn_cfg_mon_side(unsigned int ubmn_cfg_mon_side); +int iSetPRM_RX_G_MON_CFG_bmn_cfg_cnt_type(unsigned int ubmn_cfg_cnt_type); +int iSetPRM_RX_G_MON_CFG_bmn_cfg_cnt_en(unsigned int ubmn_cfg_cnt_en); +int iSetPRM_RX_G_HIS_CFG_bmn_cfg_his_cnt_cos(unsigned int ubmn_cfg_his_cnt_cos); +int iSetPRM_RX_G_HIS_CFG_bmn_cfg_his_cnt_sp(unsigned int ubmn_cfg_his_cnt_sp); +int iSetPRM_RX_G_HIS_CFG_bmn_cfg_his_cnt_clr(unsigned int ubmn_cfg_his_cnt_clr); +int iSetPRM_RX_G_HIS_CFG_bmn_cfg_his_cnt_en(unsigned int ubmn_cfg_his_cnt_en); +int iSetPRM_RX_CPB_ALOC_bmn_cpb_aloc_cnt_wr(unsigned int ubmn_cpb_aloc_cnt_wr); +int iSetPRM_RX_GRQ_ALOC_bmn_grq_aloc_cnt_wr(unsigned int ubmn_grq_aloc_cnt_wr); +int iSetPRM_RX_GRQ_DALOC_bmn_grq_daloc_cnt_wr(unsigned int ubmn_grq_daloc_cnt_wr); +int iSetPRM_RX_CPB_ALOC_CNT_bmn_cpb_aloc_cnt_num(unsigned int ubmn_cpb_aloc_cnt_num); +int iSetPRM_RX_GRQ_ALOC_CNT_bmn_grq_aloc_cnt_num(unsigned int ubmn_grq_aloc_cnt_num); +int iSetPRM_RX_GRQ_DALOC_CNT_bmn_grq_daloc_cnt_num(unsigned int ubmn_grq_daloc_cnt_num); +int iSetPRM_RX_N_COS_HIS_CNT_bmn_his_cnt_cos(unsigned int ubmn_his_cnt_cos); +int iSetPRM_RX_N_P_HIS_CNT_bmn_his_cnt_port(unsigned int ubmn_his_cnt_port); +int iSetPRM_RX_N_P_SH_HIS_CNT_bmn_his_sh_cnt_port(unsigned int ubmn_his_sh_cnt_port); +int iSetPRM_RX_N_SRV_HIS_CNT_bmn_his_cnt_srv(unsigned int ubmn_his_cnt_srv); +int iSetPRM_RX_N_SRV_SH_HIS_CNT_bmn_his_sh_cnt_srv(unsigned int ubmn_his_sh_cnt_srv); +int iSetPRM_RX_GLB_RSVD_CFG_glb_rsvd_th(unsigned int uglb_rsvd_th); +int iSetPRM_RX_GLB_FC_TH_CFG0_glb_fc0_th_on(unsigned int uglb_fc0_th_on); +int iSetPRM_RX_GLB_FC_TH_CFG0_glb_fc0_th_dif(unsigned int uglb_fc0_th_dif); +int iSetPRM_RX_GLB_FC_TH_CFG1_glb_fc1_th_on(unsigned int uglb_fc1_th_on); +int iSetPRM_RX_GLB_FC_TH_CFG1_glb_fc1_th_dif(unsigned int uglb_fc1_th_dif); +int iSetPRM_RX_GLB_FC_TH_CFG2_glb_fc2_th_on(unsigned int uglb_fc2_th_on); +int iSetPRM_RX_GLB_FC_TH_CFG2_glb_fc2_th_dif(unsigned int uglb_fc2_th_dif); +int iSetPRM_RX_GLB_DRP_TH_CFG_glb_drp_th_on(unsigned int uglb_drp_th_on); +int iSetPRM_RX_GLB_DRP_TH_CFG_glb_drp_th_dif(unsigned int uglb_drp_th_dif); +int iSetPRM_RX_PG0_RSVD_CFG_pg0_rsvd_th(unsigned int upg0_rsvd_th); +int iSetPRM_RX_PG0_FC_TH_CFG0_pg0_fc0_th_on(unsigned int upg0_fc0_th_on); +int iSetPRM_RX_PG0_FC_TH_CFG0_pg0_fc0_th_dif(unsigned int upg0_fc0_th_dif); +int iSetPRM_RX_PG0_FC_TH_CFG1_pg0_fc1_th_on(unsigned int upg0_fc1_th_on); +int iSetPRM_RX_PG0_FC_TH_CFG1_pg0_fc1_th_dif(unsigned int upg0_fc1_th_dif); +int iSetPRM_RX_PG0_FC_TH_CFG2_pg0_fc2_th_on(unsigned int upg0_fc2_th_on); +int iSetPRM_RX_PG0_FC_TH_CFG2_pg0_fc2_th_dif(unsigned int upg0_fc2_th_dif); +int iSetPRM_RX_PG0_DRP_TH_CFG_pg0_drp_th_on(unsigned int upg0_drp_th_on); +int iSetPRM_RX_PG0_DRP_TH_CFG_pg0_drp_th_dif(unsigned int upg0_drp_th_dif); +int iSetPRM_RX_PG2_RSVD_CFG_pg2_rsvd_th(unsigned int upg2_rsvd_th); +int iSetPRM_RX_PG2_FC_TH_CFG0_pg2_fc0_th_on(unsigned int upg2_fc0_th_on); +int iSetPRM_RX_PG2_FC_TH_CFG0_pg2_fc0_th_dif(unsigned int upg2_fc0_th_dif); +int iSetPRM_RX_PG2_FC_TH_CFG1_pg2_fc1_th_on(unsigned int upg2_fc1_th_on); +int iSetPRM_RX_PG2_FC_TH_CFG1_pg2_fc1_th_dif(unsigned int upg2_fc1_th_dif); +int iSetPRM_RX_PG2_FC_TH_CFG2_pg2_fc2_th_on(unsigned int upg2_fc2_th_on); +int iSetPRM_RX_PG2_FC_TH_CFG2_pg2_fc2_th_dif(unsigned int upg2_fc2_th_dif); +int iSetPRM_RX_PG2_DRP_TH_CFG_pg2_drp_th_on(unsigned int upg2_drp_th_on); +int iSetPRM_RX_PG2_DRP_TH_CFG_pg2_drp_th_dif(unsigned int upg2_drp_th_dif); +int iSetPRM_RX_PG3_RSVD_CFG_pg3_rsvd_th(unsigned int upg3_rsvd_th); +int iSetPRM_RX_PG3_FC_TH_CFG0_pg3_fc0_th_on(unsigned int upg3_fc0_th_on); +int iSetPRM_RX_PG3_FC_TH_CFG0_pg3_fc0_th_dif(unsigned int upg3_fc0_th_dif); +int iSetPRM_RX_PG3_FC_TH_CFG1_pg3_fc1_th_on(unsigned int upg3_fc1_th_on); +int iSetPRM_RX_PG3_FC_TH_CFG1_pg3_fc1_th_dif(unsigned int upg3_fc1_th_dif); +int iSetPRM_RX_PG3_FC_TH_CFG2_pg3_fc2_th_on(unsigned int upg3_fc2_th_on); +int iSetPRM_RX_PG3_FC_TH_CFG2_pg3_fc2_th_dif(unsigned int upg3_fc2_th_dif); +int iSetPRM_RX_PG3_DRP_TH_CFG_pg3_drp_th_on(unsigned int upg3_drp_th_on); +int iSetPRM_RX_PG3_DRP_TH_CFG_pg3_drp_th_dif(unsigned int upg3_drp_th_dif); +int iSetPRM_RX_PG0_CNT_pg0_curr_sh_cnt_st(unsigned int upg0_curr_sh_cnt_st); +int iSetPRM_RX_PG0_CNT_pg0_curr_cnt_st(unsigned int upg0_curr_cnt_st); +int iSetPRM_RX_PG2_CNT_pg2_curr_sh_cnt_st(unsigned int upg2_curr_sh_cnt_st); +int iSetPRM_RX_PG2_CNT_pg2_curr_cnt_st(unsigned int upg2_curr_cnt_st); +int iSetPRM_RX_PG3_CNT_pg3_curr_sh_cnt_st(unsigned int upg3_curr_sh_cnt_st); +int iSetPRM_RX_PG3_CNT_pg3_curr_cnt_st(unsigned int upg3_curr_cnt_st); +int iSetPRM_RX_GLB_CNT_glb_curr_sh_cnt_st(unsigned int uglb_curr_sh_cnt_st); +int iSetPRM_RX_GLB_CNT_glb_curr_cnt_st(unsigned int uglb_curr_cnt_st); +int iSetPRM_RX_GLB_MAX_CNT_CFG_cfg_glb_max_th(unsigned int ucfg_glb_max_th); +int iSetPRM_RX_GLB_MAX_CNT_CFG_cfg_glb_max_sh(unsigned int ucfg_glb_max_sh); +int iSetPRM_RX_IPSU_BP_TH_CFG_ipsurx_bp_all_th(unsigned int uipsurx_bp_all_th); +int iSetPRM_RX_IPSU_BP_TH_CFG_ipsurx_bp_rand_th(unsigned int uipsurx_bp_rand_th); +int iSetPRM_RX_BMN_WRR_CFG_rx_bmn_wrr_wgt_cfg(unsigned int urx_bmn_wrr_wgt_cfg); +int iSetPRM_RX_BMY_WRR_CFG_rx_bmy_wrr_wgt_cfg(unsigned int urx_bmy_wrr_wgt_cfg); +int iSetPRM_RX_BMR_WRR_CFG0_rx_bmr_wrr_wgt_cfg0(unsigned int urx_bmr_wrr_wgt_cfg0); +int iSetPRM_RX_BMR_WRR_CFG1_rx_bmn_wrr_wgt_cfg1(unsigned int urx_bmn_wrr_wgt_cfg1); +int iSetPRM_RX_BMG_WRR_CFG_rx_bmg_wrr_wgt_cfg(unsigned int urx_bmg_wrr_wgt_cfg); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_cos_n_of(unsigned int umem_cnt_cos_n_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_p_n_of(unsigned int umem_cnt_p_n_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_srv_n_of(unsigned int umem_cnt_srv_n_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_p_n_of(unsigned int umem_sh_cnt_p_n_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_srv_n_of(unsigned int umem_sh_cnt_srv_n_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stf_p_y_of(unsigned int umem_cnt_stf_p_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stf_srv_y_of(unsigned int umem_cnt_stf_srv_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_stf_srv_y_of(unsigned int umem_sh_cnt_stf_srv_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stl_p_y_of(unsigned int umem_cnt_stl_p_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stl_srv_y_of(unsigned int umem_cnt_stl_srv_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_stl_srv_y_of(unsigned int umem_sh_cnt_stl_srv_y_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stf_p_r_of(unsigned int umem_cnt_stf_p_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stf_srv_r_of(unsigned int umem_cnt_stf_srv_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_stf_srv_r_of(unsigned int umem_sh_cnt_stf_srv_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stl_p_r_of(unsigned int umem_cnt_stl_p_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_cnt_stl_srv_r_of(unsigned int umem_cnt_stl_srv_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_mem_sh_cnt_stl_srv_r_of(unsigned int umem_sh_cnt_stl_srv_r_of); +int iSetPRM_RX_CNT_OVER_FLAG_glb_cnt_of(unsigned int uglb_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg3_cnt_of(unsigned int upg3_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg2_cnt_of(unsigned int upg2_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg0_cnt_of(unsigned int upg0_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_glb_sh_cnt_of(unsigned int uglb_sh_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg3_sh_cnt_of(unsigned int upg3_sh_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg2_sh_cnt_of(unsigned int upg2_sh_cnt_of); +int iSetPRM_RX_CNT_OVER_FLAG_pg0_sh_cnt_of(unsigned int upg0_sh_cnt_of); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_cos_n_uf(unsigned int umem_cnt_cos_n_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_p_n_uf(unsigned int umem_cnt_p_n_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_srv_n_uf(unsigned int umem_cnt_srv_n_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_p_n_uf(unsigned int umem_sh_cnt_p_n_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_srv_n_uf(unsigned int umem_sh_cnt_srv_n_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stf_p_y_uf(unsigned int umem_cnt_stf_p_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stf_srv_y_uf(unsigned int umem_cnt_stf_srv_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_stf_srv_y_uf(unsigned int umem_sh_cnt_stf_srv_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stl_p_y_uf(unsigned int umem_cnt_stl_p_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stl_srv_y_uf(unsigned int umem_cnt_stl_srv_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_stl_srv_y_uf(unsigned int umem_sh_cnt_stl_srv_y_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stf_p_r_uf(unsigned int umem_cnt_stf_p_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stf_srv_r_uf(unsigned int umem_cnt_stf_srv_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_stf_srv_r_uf(unsigned int umem_sh_cnt_stf_srv_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stl_p_r_uf(unsigned int umem_cnt_stl_p_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_cnt_stl_srv_r_uf(unsigned int umem_cnt_stl_srv_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_mem_sh_cnt_stl_srv_r_uf(unsigned int umem_sh_cnt_stl_srv_r_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_glb_cnt_uf(unsigned int uglb_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg3_cnt_uf(unsigned int upg3_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg2_cnt_uf(unsigned int upg2_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg0_cnt_uf(unsigned int upg0_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_glb_sh_cnt_uf(unsigned int uglb_sh_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg3_sh_cnt_uf(unsigned int upg3_sh_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg2_sh_cnt_uf(unsigned int upg2_sh_cnt_uf); +int iSetPRM_RX_CNT_UNDER_FLAG_pg0_sh_cnt_uf(unsigned int upg0_sh_cnt_uf); +int iSetPRM_RX_FIFO_TH_CFG0_stffq1_daloc_n_af_th(unsigned int ustffq1_daloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG0_stffq1_aloc_n_af_th(unsigned int ustffq1_aloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG0_stffq0_daloc_n_af_th(unsigned int ustffq0_daloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG0_stffq0_aloc_n_af_th(unsigned int ustffq0_aloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG0_stlfq_daloc_n_af_th(unsigned int ustlfq_daloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG0_stlfq_aloc_n_af_th(unsigned int ustlfq_aloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG1_stfiq_n_af_th(unsigned int ustfiq_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG1_stliq_n_af_th(unsigned int ustliq_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG1_oq_daloc_n_af_th(unsigned int uoq_daloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG2_cpb_aloc_n_af_th(unsigned int ucpb_aloc_n_af_th); +int iSetPRM_RX_FIFO_TH_CFG2_cpb_daloc_n_af_th(unsigned int ucpb_daloc_n_af_th); +int iSetPRM_RX_DOUBLE_DALOC_WGT_stf_stl_daloc_pg3_wgt_cfg(unsigned int ustf_stl_daloc_pg3_wgt_cfg); +int iSetPRM_RX_DOUBLE_DALOC_WGT_stf_stl_daloc_pg2_wgt_cfg(unsigned int ustf_stl_daloc_pg2_wgt_cfg); +int iSetPRM_RX_PQM_ULOAD_CFG_qu_pqm_underloading_th(unsigned int uqu_pqm_underloading_th); +int iSetPRM_RX_ERR_SRC_cos_uder_src_err(unsigned int ucos_uder_src_err); +int iSetPRM_RX_ERR_SRC_cos_over_src_err(unsigned int ucos_over_src_err); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_cpb_aloc_bdmonitor_en(unsigned int ucsr_prmrx_cpb_aloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_cpb_daloc_bdmonitor_en(unsigned int ucsr_prmrx_cpb_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_cpb_src1_daloc_bdmonitor_en(unsigned int ucsr_prmrx_cpb_src1_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_cpb_drop_bdmonitor_en(unsigned int ucsr_prmrx_cpb_drop_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stliq_bdmonitor_en(unsigned int ucsr_prmrx_stliq_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stfiq_bdmonitor_en(unsigned int ucsr_prmrx_stfiq_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stlfq_aloc_bdmonitor_en(unsigned int ucsr_prmrx_stlfq_aloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stffq0_aloc_bdmonitor_en(unsigned int ucsr_prmrx_stffq0_aloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stffq1_aloc_bdmonitor_en(unsigned int ucsr_prmrx_stffq1_aloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stlfq_daloc_bdmonitor_en(unsigned int ucsr_prmrx_stlfq_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stffq0_daloc_bdmonitor_en(unsigned int ucsr_prmrx_stffq0_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_stffq1_daloc_bdmonitor_en(unsigned int ucsr_prmrx_stffq1_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_EN_csr_prmrx_oq_daloc_bdmonitor_en(unsigned int ucsr_prmrx_oq_daloc_bdmonitor_en); +int iSetPRMRX_BW_MONITOR_WIN_LEN_csr_prmrx_bdmonitro_win_len(unsigned int ucsr_prmrx_bdmonitro_win_len); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_CPB_ALOC_csr_prmrx_bdmonitro_max_times_cpb_aloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_cpb_aloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_CPB_DALOC_csr_prmrx_bdmonitro_max_times_cpb_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_cpb_daloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_CPB_SRC1_DALOC_csr_prmrx_bdmonitro_max_times_cpb_src1_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_cpb_src1_daloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_CPB_DROP_csr_prmrx_bdmonitro_max_times_cpb_drop( + unsigned int ucsr_prmrx_bdmonitro_max_times_cpb_drop); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STLIQ_csr_prmrx_bdmonitro_max_times_stliq( + unsigned int ucsr_prmrx_bdmonitro_max_times_stliq); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STFIQ_csr_prmrx_bdmonitro_max_times_stfiq( + unsigned int ucsr_prmrx_bdmonitro_max_times_stfiq); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STLFQ_ALOC_csr_prmrx_bdmonitro_max_times_stlfq_aloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stlfq_aloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STFFQ0_ALOC_csr_prmrx_bdmonitro_max_times_stffq0_aloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stffq0_aloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STFFQ1_ALOC_csr_prmrx_bdmonitro_max_times_stffq1_aloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stffq1_aloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STLFQ_DALOC_csr_prmrx_bdmonitro_max_times_stlfq_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stlfq_daloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STFFQ0_DALOC_csr_prmrx_bdmonitro_max_times_stffq0_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stffq0_daloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_STFFQ1_DALOC_csr_prmrx_bdmonitro_max_times_stffq1_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_stffq1_daloc); +int iSetPRMRX_BW_MONITOR_MAX_TIMES_OQ_DALOC_csr_prmrx_bdmonitro_max_times_oq_daloc( + unsigned int ucsr_prmrx_bdmonitro_max_times_oq_daloc); +int iSetPRMRX_BW_MONITOR_WIN_CNT_prmrx_csr_bdmonitor_win_cnt(unsigned int uprmrx_csr_bdmonitor_win_cnt); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_ALOC_prmrx_csr_bdmonitor_over_max_cnt_cpb_aloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_cpb_aloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DALOC_prmrx_csr_bdmonitor_over_max_cnt_cpb_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_cpb_daloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_SRC1_DALOC_prmrx_csr_bdmonitor_over_max_cnt_cpb_src1_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_cpb_src1_daloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DROP_prmrx_csr_bdmonitor_over_max_cnt_cpb_drop( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_cpb_drop); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLIQ_prmrx_csr_bdmonitor_over_max_cnt_stliq( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stliq); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFIQ_prmrx_csr_bdmonitor_over_max_cnt_stfiq( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stfiq); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_ALOC_prmrx_csr_bdmonitor_over_max_cnt_stlfq_aloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stlfq_aloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_ALOC_prmrx_csr_bdmonitor_over_max_cnt_stffq0_aloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stffq0_aloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_ALOC_prmrx_csr_bdmonitor_over_max_cnt_stffq1_aloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stffq1_aloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_DALOC_prmrx_csr_bdmonitor_over_max_cnt_stlfq_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stlfq_daloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_DALOC_prmrx_csr_bdmonitor_over_max_cnt_stffq0_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stffq0_daloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_DALOC_prmrx_csr_bdmonitor_over_max_cnt_stffq1_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_stffq1_daloc); +int iSetPRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_DALOC_prmrx_csr_bdmonitor_over_max_cnt_oq_daloc( + unsigned int uprmrx_csr_bdmonitor_over_max_cnt_oq_daloc); + + +#endif // PRMRX_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_reg_offset.h new file mode 100644 index 000000000..0c069f244 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmrx_reg_offset.h @@ -0,0 +1,258 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : prmrx_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 21:59:21 Create file +// ****************************************************************************** + +#ifndef PRMRX_REG_OFFSET_H +#define PRMRX_REG_OFFSET_H + +/* QU_PRM_TOP_CSR Base address of Module's Register */ +#define CSR_QU_PRM_TOP_CSR_BASE (0x7000) + +/* **************************************************************************** */ +/* QU_PRM_TOP_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MEM_CTRL_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x0) /* MEM控制 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP_MASK0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x4) /* MQM_BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP_MASK1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x8) /* MQM_HOST BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP_MASK2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0xC) /* MQM_SOC BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP_MASK3_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x10) /* MQM_COS0 BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP_MASK4_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x14) /* MQM_COS1 BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_BP_MASK_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x18) /* PRM BP MASK */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT_VECTOR_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x5C) /* 中断向量 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x60) /* 中断状态 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT_EN_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x64) /* 中断屏蔽 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT0_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x68) /* 中断0的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT1_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x6C) /* 中断1的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT2_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x70) /* 中断2的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_INT3_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x74) /* 中断3的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_INT4_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x78) /* 中断4的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_INT5_STICKY_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x7C) /* 中断5的sticky信息 */ +#define CSR_QU_PRM_TOP_CSR_PRM_FIFO_ST0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x100) /* TX FIFO OVER FLAG */ +#define CSR_QU_PRM_TOP_CSR_PRM_FIFO_ST1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x104) /* TX FIFO UNDER FLAG */ +#define CSR_QU_PRM_TOP_CSR_PRM_FIFO_ST2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x108) /* RX FIFO OVER FLAG */ +#define CSR_QU_PRM_TOP_CSR_PRM_FIFO_ST3_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x10C) /* RX FIFO UNDER FLAG */ +#define CSR_QU_PRM_TOP_CSR_PRM_SRC_IN_VIO_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x110) /* 申请src超过定义范围 */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x204) /* MQM_BP */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x208) /* MQM_HOST BP */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x20C) /* MQM_SOC BP */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP3_0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x210) /* MQM_COS0 BP */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MQM_BP3_1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x214) /* MQM_COS0 BP */ +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MAG_PORT_BP_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x220) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MAG_COS_BP_0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x240) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_MAG_COS_BP_1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x244) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_OQ_COS_BP_0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x250) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_OQ_COS_BP_1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x254) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_OQ_COS_BP_2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x258) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_OQ_COS_BP_3_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x25C) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPI_COS_BP_0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x260) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPI_COS_BP_1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x264) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPI_COS_BP_2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x268) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPB_COS_BP_0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x270) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPB_COS_BP_1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x274) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_CPB_COS_BP_2_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x278) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_IQ_BP_CFG_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x290) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_STL_IQ_BP0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x294) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_STL_IQ_BP1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x298) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_STF_IQ_BP0_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x29C) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_STF_IQ_BP1_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x2A0) +#define CSR_QU_PRM_TOP_CSR_PRM_TOP_1BIT_ECC_ERR_REG (CSR_QU_PRM_TOP_CSR_BASE + 0x2A4) + +/* QU_PRM_RX_CSR Base address of Module's Register */ +#define CSR_QU_PRM_RX_CSR_BASE (0x6000) + +/* **************************************************************************** */ +/* QU_PRM_RX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_CTRL_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x0) /* PRM memory indirect access ctrl register */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_TIMEOUT_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x4) /* PRM indirect access timeout configuration */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_DAT0_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x8) /* PRM indirect access write or read data. */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_DAT1_REG (CSR_QU_PRM_RX_CSR_BASE + 0xC) +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_DAT2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x10) +#define CSR_QU_PRM_RX_CSR_PRM_RX_INDRECT_DAT3_REG (CSR_QU_PRM_RX_CSR_BASE + 0x14) +#define CSR_QU_PRM_RX_CSR_PRM_RX_CSR_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x30) /* 软件申请配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_FC_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x34) /* 黄区STF阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_FC_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x38) /* 黄区STL阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_FC_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x3C) /* 红区STF阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_FC_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x40) /* 红区STL阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x44) /* 黄区STF RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x48) /* 黄区STL RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x4C) /* 红区STF RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x50) /* 红区STL RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x54) /* 黄区STF 资源CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x58) /* 黄区STL 资源CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x5C) /* 红区STF 资源CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x60) /* 红区STL 资源CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_SH_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x64) /* 黄区STF 资源SH_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_SH_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x68) /* 黄区STL 资源SH_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_SH_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x6C) /* 红区STF 资源SH_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_SH_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x70) /* 红区STL 资源SH_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_MON_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x74) /* 黄区monitor配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_HIS_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x78) /* 黄区最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_MON_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x7C) /* 红区monitor配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_HIS_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x80) /* 红区最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLFQ_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x84) /* STLFQ ALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ0_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x88) /* STFFQ0 ALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ1_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x8C) /* STFFQ1 ALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLFQ_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x90) /* STLFQ DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ0_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x94) /* STFFQ0 DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ1_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x98) /* STFFQ1 DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x9C) /* CPB DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_DROP_REG (CSR_QU_PRM_RX_CSR_BASE + 0xA0) /* CPB DROP 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_OQ_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0xA4) /* OQ DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLFQ_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xA8) /* STLFQ ALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ0_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xAC) /* STFFQ0 ALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ1_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xB0) /* STFFQ1 ALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLFQ_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xB4) /* STLFQ DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ0_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xB8) /* STFFQ0 DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFFQ1_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xBC) /* STFFQ1 DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xC0) /* CPB DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_DROP_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xC4) /* CPB DROP CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_OQ_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xC8) /* OQ DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_P_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xCC) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_P_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xD0) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_SRV_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xD4) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_SRV_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xD8) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xDC) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xE0) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_ST_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xE4) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_ST_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xE8) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STF_ST_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xEC) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_R_STL_ST_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0xF0) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFIQ_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0xF4) /* STFIQ ALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLIQ_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0xF8) /* STLIQ ALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_YDA_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0xFC) /* YDA DALOC 次数 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STFIQ_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x100) /* STFIQ ALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_STLIQ_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x104) /* STLIQ ALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_YDA_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x108) /* YDA DALOC CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_P_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x10C) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_P_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x110) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_ST_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x114) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_ST_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x118) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STF_ST_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x11C) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_Y_STL_ST_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x120) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_G_MON_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x124) /* 绿区monitor配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_G_HIS_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x128) /* 绿区最大值记录配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x12C) /* PRM_RX_CPB_ALOC */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GRQ_ALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x130) /* PRM_RX_GRQ_ALOC */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GRQ_DALOC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x134) /* PRM_RX_GRQ_DALOC */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CPB_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x138) /* PRM_RX_CPB_ALOC_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GRQ_ALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x13C) /* PRM_RX_GRQ_ALOC_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GRQ_DALOC_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x140) /* PRM_RX_GRQ_DALOC_CNT */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_N_COS_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x144) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_N_P_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x148) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_N_P_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x14C) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_N_SRV_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x150) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_N_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x154) /* 最大值记录 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x158) /* GLB RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_FC_TH_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x15C) /* GLB阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_FC_TH_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x160) /* GLB阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_FC_TH_CFG2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x164) /* GLB阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_DRP_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x168) /* GLB阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x16C) /* PG0 RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_FC_TH_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x170) /* PG0阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_FC_TH_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x174) /* PG0阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_FC_TH_CFG2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x178) /* PG0阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_DRP_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x17C) /* PG0阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x180) /* PG2 RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_FC_TH_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x184) /* PG2阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_FC_TH_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x188) /* PG2阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_FC_TH_CFG2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x18C) /* PG2阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_DRP_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x190) /* PG2阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_RSVD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x194) /* PG3 RSVD配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_FC_TH_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x198) /* PG3阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_FC_TH_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x19C) /* PG3阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_FC_TH_CFG2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1A0) /* PG3阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_DRP_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1A4) /* PG3阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG0_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1A8) /* PG0资源统计 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG2_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1AC) /* PG2黄区资源统计 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PG3_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1B0) /* PG3红区资源统计 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_CNT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1B4) /* PG0资源统计 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_GLB_MAX_CNT_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1B8) +#define CSR_QU_PRM_RX_CSR_PRM_RX_IPSU_BP_TH_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1BC) /* IPSU 反压阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_BMN_WRR_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1C0) /* RX绿区WRR权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_BMY_WRR_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1C4) /* RX黄区WRR权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_BMR_WRR_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1C8) /* RX红区WRR权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_BMR_WRR_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1CC) /* RX红区WRR权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_BMG_WRR_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1D0) /* RX GLB 区WRR权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CNT_OVER_FLAG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1D4) /* CNT上溢出标志 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_CNT_UNDER_FLAG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1D8) /* CNT下溢出标志 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_FIFO_TH_CFG0_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1E0) /* RX fifo阈值配置0 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_FIFO_TH_CFG1_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1E4) /* RX fifo阈值配置1 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_FIFO_TH_CFG2_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1E8) /* RX fifo阈值配置2 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_DOUBLE_DALOC_WGT_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1EC) /* RX双黄/红区释放权重配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_PQM_ULOAD_CFG_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1F0) /* PG0轻负载阈值配置 */ +#define CSR_QU_PRM_RX_CSR_PRM_RX_ERR_SRC_REG (CSR_QU_PRM_RX_CSR_BASE + 0x1F4) /* RX溢出DFX */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_EN_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x230) /* PRMRX侧的入口FIFO带宽监测使能配置 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_WIN_LEN_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x234) /* PRMRX侧的入口FIFO带宽监测，窗口长度配置 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_CPB_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x238) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_CPB_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x23C) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_CPB_SRC1_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x240) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_CPB_DROP_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x244) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STLIQ_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x248) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STFIQ_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x24C) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STLFQ_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x250) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STFFQ0_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x254) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STFFQ1_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x258) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STLFQ_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x25C) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STFFQ0_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x260) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_STFFQ1_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x264) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_MAX_TIMES_OQ_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x268) /* PRMRX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_WIN_CNT_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x26C) /* PRMRX侧的入口FIFO带宽监测，窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x270) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x274) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_SRC1_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x278) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DROP_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x27C) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLIQ_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x280) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFIQ_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x284) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x288) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x28C) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_ALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x290) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x294) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x298) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x29C) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_RX_CSR_PRMRX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_DALOC_REG \ + (CSR_QU_PRM_RX_CSR_BASE + 0x2A0) /* PRMRX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ + +#endif // PRMRX_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_c_union_define.h new file mode 100644 index 000000000..cc8ef9a5b --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_c_union_define.h @@ -0,0 +1,2758 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : prmtx_c_union_define.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 22:01:17 Create file +// ****************************************************************************** + +#ifndef PRMTX_C_UNION_DEFINE_H +#define PRMTX_C_UNION_DEFINE_H + +/* Define the union csr_prm_tx_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_ctrl_u; + +/* Define the union csr_prm_tx_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_timeout_u; + +/* Define the union csr_prm_tx_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat0_u; + +/* Define the union csr_prm_tx_indrect_dat1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat1_u; + +/* Define the union csr_prm_tx_indrect_dat2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat2_u; + +/* Define the union csr_prm_tx_indrect_dat3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat3_u; + +/* Define the union csr_prm_tx_indrect_dat4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat4_u; + +/* Define the union csr_prm_tx_indrect_dat5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat5_u; + +/* Define the union csr_prm_tx_indrect_dat6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 indirect_dat6 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_indrect_dat6_u; + +/* Define the union csr_prm_tx_csr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dyn_csr_req_src : 12; /* [11:0] */ + u32 bmr_dyn_csr_req : 1; /* [12] */ + u32 bmy_dyn_csr_req : 1; /* [13] */ + u32 bmh_dyn_csr_req : 1; /* [14] */ + u32 rsv_0 : 17; /* [31:15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_csr_cfg_u; + +/* Define the union csr_prm_tx_y_stf_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_fc0_th_on : 16; /* [15:0] */ + u32 stf_state_y_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_fc_th_cfg_u; + +/* Define the union csr_prm_tx_y_stl_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_fc0_th_on : 16; /* [15:0] */ + u32 stl_state_y_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_2 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_fc_th_cfg_u; + +/* Define the union csr_prm_tx_r_stf_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_fc0_th_on : 16; /* [15:0] */ + u32 stf_state_r_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_fc_th_cfg_u; + +/* Define the union csr_prm_tx_r_stl_fc_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_fc0_th_on : 16; /* [15:0] */ + u32 stl_state_r_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_4 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_fc_th_cfg_u; + +/* Define the union csr_prm_tx_y_stf_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_rsvd : 16; /* [15:0] */ + u32 rsv_5 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_rsvd_cfg_u; + +/* Define the union csr_prm_tx_y_stl_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_rsvd : 16; /* [15:0] */ + u32 rsv_6 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_rsvd_cfg_u; + +/* Define the union csr_prm_tx_r_stf_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_rsvd : 16; /* [15:0] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_rsvd_cfg_u; + +/* Define the union csr_prm_tx_r_stl_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_rsvd : 16; /* [15:0] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_rsvd_cfg_u; + +/* Define the union csr_prm_tx_y_stf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_cnt : 16; /* [15:0] */ + u32 rsv_9 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_cnt_u; + +/* Define the union csr_prm_tx_y_stl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_cnt : 16; /* [15:0] */ + u32 rsv_10 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_cnt_u; + +/* Define the union csr_prm_tx_r_stf_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_cnt : 16; /* [15:0] */ + u32 rsv_11 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_cnt_u; + +/* Define the union csr_prm_tx_r_stl_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_cnt : 16; /* [15:0] */ + u32 rsv_12 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_cnt_u; + +/* Define the union csr_prm_tx_y_stf_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_y_sh_cnt : 16; /* [15:0] */ + u32 rsv_13 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_sh_cnt_u; + +/* Define the union csr_prm_tx_y_stl_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_y_sh_cnt : 16; /* [15:0] */ + u32 rsv_14 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_sh_cnt_u; + +/* Define the union csr_prm_tx_r_stf_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_state_r_sh_cnt : 16; /* [15:0] */ + u32 rsv_15 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_sh_cnt_u; + +/* Define the union csr_prm_tx_r_stl_sh_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stl_state_r_sh_cnt : 16; /* [15:0] */ + u32 rsv_16 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_sh_cnt_u; + +/* Define the union csr_prm_tx_y_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_17 : 1; /* [3] */ + u32 bmy_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_18 : 3; /* [11:9] */ + u32 bmy_cfg_mon_srv : 1; /* [12] */ + u32 rsv_19 : 3; /* [15:13] */ + u32 bmy_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_20 : 2; /* [19:18] */ + u32 bmy_cfg_cnt_en : 1; /* [20] */ + u32 rsv_21 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_mon_cfg_u; + +/* Define the union csr_prm_tx_y_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_22 : 3; /* [2:0] */ + u32 rsv_23 : 1; /* [3] */ + u32 bmy_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_24 : 3; /* [11:9] */ + u32 bmy_cfg_his_cnt_srv : 1; /* [12] */ + u32 rsv_25 : 3; /* [15:13] */ + u32 bmy_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_26 : 3; /* [19:17] */ + u32 bmy_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_27 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_his_cfg_u; + +/* Define the union csr_prm_tx_r_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_28 : 1; /* [3] */ + u32 bmr_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_29 : 3; /* [11:9] */ + u32 bmr_cfg_mon_srv : 1; /* [12] */ + u32 rsv_30 : 3; /* [15:13] */ + u32 bmr_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_31 : 2; /* [19:18] */ + u32 bmr_cfg_cnt_en : 1; /* [20] */ + u32 rsv_32 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_mon_cfg_u; + +/* Define the union csr_prm_tx_r_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_33 : 3; /* [2:0] */ + u32 rsv_34 : 1; /* [3] */ + u32 bmr_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_35 : 3; /* [11:9] */ + u32 bmr_cfg_his_cnt_srv : 1; /* [12] */ + u32 rsv_36 : 3; /* [15:13] */ + u32 bmr_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_37 : 3; /* [19:17] */ + u32 bmr_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_38 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_his_cfg_u; + +/* Define the union csr_prm_tx_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stlfq_aloc_u; + +/* Define the union csr_prm_tx_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq0_aloc_u; + +/* Define the union csr_prm_tx_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_aloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq1_aloc_u; + +/* Define the union csr_prm_tx_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stlfq_daloc_u; + +/* Define the union csr_prm_tx_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq0_daloc_u; + +/* Define the union csr_prm_tx_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq1_daloc_u; + +/* Define the union csr_prm_tx_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_daloc_u; + +/* Define the union csr_prm_tx_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_drop_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_drop_u; + +/* Define the union csr_prm_tx_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_oq_daloc_cnt_wr_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_oq_daloc_u; + +/* Define the union csr_prm_tx_stlfq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stlfq_aloc_cnt_u; + +/* Define the union csr_prm_tx_stffq0_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq0_aloc_cnt_u; + +/* Define the union csr_prm_tx_stffq1_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_aloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq1_aloc_cnt_u; + +/* Define the union csr_prm_tx_stlfq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stlfq_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stlfq_daloc_cnt_u; + +/* Define the union csr_prm_tx_stffq0_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq0_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq0_daloc_cnt_u; + +/* Define the union csr_prm_tx_stffq1_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stffq1_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stffq1_daloc_cnt_u; + +/* Define the union csr_prm_tx_cpb_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_daloc_cnt_u; + +/* Define the union csr_prm_tx_cpb_drop_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_cpb_drop_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_drop_cnt_u; + +/* Define the union csr_prm_tx_oq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_oq_daloc_cnt_num_v : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_oq_daloc_cnt_u; + +/* Define the union csr_prm_tx_r_stf_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_port : 16; /* [15:0] */ + u32 rsv_39 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_p_his_cnt_u; + +/* Define the union csr_prm_tx_r_stl_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_port : 16; /* [15:0] */ + u32 rsv_40 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_p_his_cnt_u; + +/* Define the union csr_prm_tx_r_stf_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_41 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_srv_his_cnt_u; + +/* Define the union csr_prm_tx_r_stl_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_42 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_srv_his_cnt_u; + +/* Define the union csr_prm_tx_r_stf_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_srv_sh : 16; /* [15:0] */ + u32 rsv_43 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_srv_sh_his_cnt_u; + +/* Define the union csr_prm_tx_r_stl_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_srv_sh : 16; /* [15:0] */ + u32 rsv_44 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_srv_sh_his_cnt_u; + +/* Define the union csr_prm_tx_r_stf_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_st : 16; /* [15:0] */ + u32 rsv_45 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_st_his_cnt_u; + +/* Define the union csr_prm_tx_r_stl_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_st : 16; /* [15:0] */ + u32 rsv_46 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_st_his_cnt_u; + +/* Define the union csr_prm_tx_r_stf_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stf_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_47 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stf_st_sh_his_cnt_u; + +/* Define the union csr_prm_tx_r_stl_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmr_stl_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_48 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_r_stl_st_sh_his_cnt_u; + +/* Define the union csr_prm_tx_stfiq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_iq_icb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stfiq_aloc_u; + +/* Define the union csr_prm_tx_stliq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_iq_icb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stliq_aloc_u; + +/* Define the union csr_prm_tx_yda_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_yda_daloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_yda_daloc_u; + +/* Define the union csr_prm_tx_stfiq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_iq_icb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stfiq_aloc_cnt_u; + +/* Define the union csr_prm_tx_stliq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_iq_icb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_stliq_aloc_cnt_u; + +/* Define the union csr_prm_tx_yda_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_yda_daloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_yda_daloc_cnt_u; + +/* Define the union csr_prm_tx_y_stf_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_port : 16; /* [15:0] */ + u32 rsv_49 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_p_his_cnt_u; + +/* Define the union csr_prm_tx_y_stl_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_port : 16; /* [15:0] */ + u32 rsv_50 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_p_his_cnt_u; + +/* Define the union csr_prm_tx_y_stf_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_st : 16; /* [15:0] */ + u32 rsv_51 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_st_his_cnt_u; + +/* Define the union csr_prm_tx_y_stl_st_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_st : 16; /* [15:0] */ + u32 rsv_52 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_st_his_cnt_u; + +/* Define the union csr_prm_tx_y_stf_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stf_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_53 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stf_st_sh_his_cnt_u; + +/* Define the union csr_prm_tx_y_stl_st_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmy_stl_his_cnt_st_sh : 16; /* [15:0] */ + u32 rsv_54 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_y_stl_st_sh_his_cnt_u; + +/* Define the union csr_prm_tx_g_mon_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cfg_mon_cos : 3; /* [2:0] */ + u32 rsv_55 : 1; /* [3] */ + u32 bmh_cfg_mon_sp : 5; /* [8:4] */ + u32 rsv_56 : 3; /* [11:9] */ + u32 bmh_cfg_mon_side : 1; /* [12] */ + u32 rsv_57 : 3; /* [15:13] */ + u32 bmh_cfg_cnt_type : 2; /* [17:16] */ + u32 rsv_58 : 2; /* [19:18] */ + u32 bmh_cfg_cnt_en : 1; /* [20] */ + u32 rsv_59 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_g_mon_cfg_u; + +/* Define the union csr_prm_tx_g_his_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cfg_his_cnt_cos : 3; /* [2:0] */ + u32 rsv_60 : 1; /* [3] */ + u32 bmh_cfg_his_cnt_sp : 5; /* [8:4] */ + u32 rsv_61 : 3; /* [11:9] */ + u32 rsv_62 : 1; /* [12] */ + u32 rsv_63 : 3; /* [15:13] */ + u32 bmh_cfg_his_cnt_clr : 1; /* [16] */ + u32 rsv_64 : 3; /* [19:17] */ + u32 bmh_cfg_his_cnt_en : 1; /* [20] */ + u32 rsv_65 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_g_his_cfg_u; + +/* Define the union csr_prm_tx_cpi_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cpi_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpi_aloc_u; + +/* Define the union csr_prm_tx_grq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_grq_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_grq_aloc_u; + +/* Define the union csr_prm_tx_grq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_grq_daloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_grq_daloc_u; + +/* Define the union csr_prm_tx_cpi_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cpi_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpi_aloc_cnt_u; + +/* Define the union csr_prm_tx_grq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_grq_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_grq_aloc_cnt_u; + +/* Define the union csr_prm_tx_grq_daloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_grq_daloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_grq_daloc_cnt_u; + +/* Define the union csr_prm_tx_h_cos_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_his_cnt_cos : 16; /* [15:0] */ + u32 rsv_66 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_h_cos_his_cnt_u; + +/* Define the union csr_prm_tx_h_p_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_his_cnt_port : 16; /* [15:0] */ + u32 rsv_67 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_h_p_his_cnt_u; + +/* Define the union csr_prm_tx_h_p_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_his_sh_cnt_port : 16; /* [15:0] */ + u32 rsv_68 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_h_p_sh_his_cnt_u; + +/* Define the union csr_prm_tx_h_srv_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_his_cnt_srv : 16; /* [15:0] */ + u32 rsv_69 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_h_srv_his_cnt_u; + +/* Define the union csr_prm_tx_h_srv_sh_his_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_his_sh_cnt_srv : 16; /* [15:0] */ + u32 rsv_70 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_h_srv_sh_his_cnt_u; + +/* Define the union csr_prm_tx_glb_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_rsvd_th : 16; /* [15:0] */ + u32 rsv_71 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_rsvd_cfg_u; + +/* Define the union csr_prm_tx_glb_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc0_th_on : 16; /* [15:0] */ + u32 glb_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_72 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_fc_th_cfg0_u; + +/* Define the union csr_prm_tx_glb_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc1_th_on : 16; /* [15:0] */ + u32 glb_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_73 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_fc_th_cfg1_u; + +/* Define the union csr_prm_tx_glb_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_fc2_th_on : 16; /* [15:0] */ + u32 glb_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_74 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_fc_th_cfg2_u; + +/* Define the union csr_prm_tx_glb_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_drp_th_on : 16; /* [15:0] */ + u32 glb_drp_th_dif : 8; /* [23:16] */ + u32 rsv_75 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_drp_th_cfg_u; + +/* Define the union csr_prm_tx_pg1_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_rsvd_th : 16; /* [15:0] */ + u32 rsv_76 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_rsvd_cfg_u; + +/* Define the union csr_prm_tx_pg1_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_fc0_th_on : 16; /* [15:0] */ + u32 pg1_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_77 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_fc_th_cfg0_u; + +/* Define the union csr_prm_tx_pg1_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_fc1_th_on : 16; /* [15:0] */ + u32 pg1_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_78 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_fc_th_cfg1_u; + +/* Define the union csr_prm_tx_pg1_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_fc2_th_on : 16; /* [15:0] */ + u32 pg1_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_79 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_fc_th_cfg2_u; + +/* Define the union csr_prm_tx_pg1_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_drp_th_on : 16; /* [15:0] */ + u32 pg1_drp_th_dif : 8; /* [23:16] */ + u32 rsv_80 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_drp_th_cfg_u; + +/* Define the union csr_prm_tx_pg2_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_rsvd_th : 16; /* [15:0] */ + u32 rsv_81 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_rsvd_cfg_u; + +/* Define the union csr_prm_tx_pg2_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc0_th_on : 16; /* [15:0] */ + u32 pg2_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_82 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_fc_th_cfg0_u; + +/* Define the union csr_prm_tx_pg2_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc1_th_on : 16; /* [15:0] */ + u32 pg2_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_83 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_fc_th_cfg1_u; + +/* Define the union csr_prm_tx_pg2_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_fc2_th_on : 16; /* [15:0] */ + u32 pg2_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_84 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_fc_th_cfg2_u; + +/* Define the union csr_prm_tx_pg2_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_drp_th_on : 16; /* [15:0] */ + u32 pg2_drp_th_dif : 8; /* [23:16] */ + u32 rsv_85 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_drp_th_cfg_u; + +/* Define the union csr_prm_tx_pg3_rsvd_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_rsvd_th : 16; /* [15:0] */ + u32 rsv_86 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_rsvd_cfg_u; + +/* Define the union csr_prm_tx_pg3_fc_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc0_th_on : 16; /* [15:0] */ + u32 pg3_fc0_th_dif : 8; /* [23:16] */ + u32 rsv_87 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_fc_th_cfg0_u; + +/* Define the union csr_prm_tx_pg3_fc_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc1_th_on : 16; /* [15:0] */ + u32 pg3_fc1_th_dif : 8; /* [23:16] */ + u32 rsv_88 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_fc_th_cfg1_u; + +/* Define the union csr_prm_tx_pg3_fc_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_fc2_th_on : 16; /* [15:0] */ + u32 pg3_fc2_th_dif : 8; /* [23:16] */ + u32 rsv_89 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_fc_th_cfg2_u; + +/* Define the union csr_prm_tx_pg3_drp_th_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_drp_th_on : 16; /* [15:0] */ + u32 pg3_drp_th_dif : 8; /* [23:16] */ + u32 rsv_90 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_drp_th_cfg_u; + +/* Define the union csr_prm_tx_pg1_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg1_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg1_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg1_cnt_u; + +/* Define the union csr_prm_tx_pg2_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg2_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg2_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg2_cnt_u; + +/* Define the union csr_prm_tx_pg3_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pg3_curr_sh_cnt_st : 16; /* [15:0] */ + u32 pg3_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_pg3_cnt_u; + +/* Define the union csr_prm_tx_glb_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 glb_curr_sh_cnt_st : 16; /* [15:0] */ + u32 glb_curr_cnt_st : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_cnt_u; + +/* Define the union csr_prm_tx_glb_max_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_glb_max_th : 16; /* [15:0] */ + u32 cfg_glb_max_sh : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_glb_max_cnt_cfg_u; + +/* Define the union csr_prm_tx_cpi_req_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_cpi_wg_period : 14; /* [13:0] */ + u32 cfg_cpi_toke_unit : 10; /* [23:14] */ + u32 msk_sel_cpi_req : 1; /* [24] */ + u32 rsv_91 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpi_req_cfg_u; + +/* Define the union csr_prm_tx_mqm_uload_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_mqm_underloading_th : 16; /* [15:0] */ + u32 rsv_92 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_mqm_uload_cfg_u; + +/* Define the union csr_prm_tx_bmh_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_bmh_wrr_wgt_cfg : 16; /* [15:0] */ + u32 rsv_93 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_bmh_wrr_cfg_u; + +/* Define the union csr_prm_tx_bmy_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_bmy_wrr_wgt_cfg : 12; /* [11:0] */ + u32 rsv_94 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_bmy_wrr_cfg_u; + +/* Define the union csr_prm_tx_bmr_wrr_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_bmr_wrr_wgt_cfg0 : 24; /* [23:0] */ + u32 rsv_95 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_bmr_wrr_cfg0_u; + +/* Define the union csr_prm_tx_bmr_wrr_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_bmr_wrr_wgt_cfg1 : 12; /* [11:0] */ + u32 rsv_96 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_bmr_wrr_cfg1_u; + +/* Define the union csr_prm_tx_bmg_wrr_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tx_bmg_wrr_wgt_cfg : 16; /* [15:0] */ + u32 rsv_97 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_bmg_wrr_cfg_u; + +/* Define the union csr_prm_tx_cnt_over_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_cnt_cos_h_of : 1; /* [0] */ + u32 mem_cnt_p_h_of : 1; /* [1] */ + u32 mem_cnt_srv_h_of : 1; /* [2] */ + u32 mem_sh_cnt_p_h_of : 1; /* [3] */ + u32 mem_sh_cnt_srv_h_of : 1; /* [4] */ + u32 mem_cnt_stf_p_y_of : 1; /* [5] */ + u32 mem_cnt_stf_srv_y_of : 1; /* [6] */ + u32 mem_sh_cnt_stf_srv_y_of : 1; /* [7] */ + u32 mem_cnt_stl_p_y_of : 1; /* [8] */ + u32 mem_cnt_stl_srv_y_of : 1; /* [9] */ + u32 mem_sh_cnt_stl_srv_y_of : 1; /* [10] */ + u32 mem_cnt_stf_p_r_of : 1; /* [11] */ + u32 mem_cnt_stf_srv_r_of : 1; /* [12] */ + u32 mem_sh_cnt_stf_srv_r_of : 1; /* [13] */ + u32 mem_cnt_stl_p_r_of : 1; /* [14] */ + u32 mem_cnt_stl_srv_r_of : 1; /* [15] */ + u32 mem_sh_cnt_stl_srv_r_of : 1; /* [16] */ + u32 glb_cnt_of : 1; /* [17] */ + u32 pg3_cnt_of : 1; /* [18] */ + u32 pg2_cnt_of : 1; /* [19] */ + u32 pg1_cnt_of : 1; /* [20] */ + u32 glb_sh_cnt_of : 1; /* [21] */ + u32 pg3_sh_cnt_of : 1; /* [22] */ + u32 pg2_sh_cnt_of : 1; /* [23] */ + u32 pg1_sh_cnt_of : 1; /* [24] */ + u32 rsv_98 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cnt_over_flag_u; + +/* Define the union csr_prm_tx_cnt_under_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_cnt_cos_h_uf : 1; /* [0] */ + u32 mem_cnt_p_h_uf : 1; /* [1] */ + u32 mem_cnt_srv_h_uf : 1; /* [2] */ + u32 mem_sh_cnt_p_h_uf : 1; /* [3] */ + u32 mem_sh_cnt_srv_h_uf : 1; /* [4] */ + u32 mem_cnt_stf_p_y_uf : 1; /* [5] */ + u32 mem_cnt_stf_srv_y_uf : 1; /* [6] */ + u32 mem_sh_cnt_stf_srv_y_uf : 1; /* [7] */ + u32 mem_cnt_stl_p_y_uf : 1; /* [8] */ + u32 mem_cnt_stl_srv_y_uf : 1; /* [9] */ + u32 mem_sh_cnt_stl_srv_y_uf : 1; /* [10] */ + u32 mem_cnt_stf_p_r_uf : 1; /* [11] */ + u32 mem_cnt_stf_srv_r_uf : 1; /* [12] */ + u32 mem_sh_cnt_stf_srv_r_uf : 1; /* [13] */ + u32 mem_cnt_stl_p_r_uf : 1; /* [14] */ + u32 mem_cnt_stl_srv_r_uf : 1; /* [15] */ + u32 mem_sh_cnt_stl_srv_r_uf : 1; /* [16] */ + u32 glb_cnt_uf : 1; /* [17] */ + u32 pg3_cnt_uf : 1; /* [18] */ + u32 pg2_cnt_uf : 1; /* [19] */ + u32 pg1_cnt_uf : 1; /* [20] */ + u32 glb_sh_cnt_uf : 1; /* [21] */ + u32 pg3_sh_cnt_uf : 1; /* [22] */ + u32 pg2_sh_cnt_uf : 1; /* [23] */ + u32 pg1_sh_cnt_uf : 1; /* [24] */ + u32 rsv_99 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cnt_under_flag_u; + +/* Define the union csr_prm_tx_fifo_th_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stffq1_daloc_n_af_th : 5; /* [4:0] */ + u32 stffq1_aloc_n_af_th : 5; /* [9:5] */ + u32 stffq0_daloc_n_af_th : 5; /* [14:10] */ + u32 stffq0_aloc_n_af_th : 5; /* [19:15] */ + u32 stlfq_daloc_n_af_th : 5; /* [24:20] */ + u32 stlfq_aloc_n_af_th : 5; /* [29:25] */ + u32 rsv_100 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_fifo_th_cfg0_u; + +/* Define the union csr_prm_tx_fifo_th_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stfiq_n_af_th : 5; /* [4:0] */ + u32 stliq_n_af_th : 5; /* [9:5] */ + u32 oq_daloc_n_af_th : 5; /* [14:10] */ + u32 oq_aloc_n_af_th : 5; /* [19:15] */ + u32 rsv_101 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_fifo_th_cfg1_u; + +/* Define the union csr_prm_tx_fifo_th_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_aloc_n_af_th : 6; /* [5:0] */ + u32 rsv_102 : 2; /* [7:6] */ + u32 cpb_daloc_n_af_th : 6; /* [13:8] */ + u32 rsv_103 : 2; /* [15:14] */ + u32 cpi_aloc_n_af_th : 7; /* [22:16] */ + u32 rsv_104 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_fifo_th_cfg2_u; + +/* Define the union csr_prm_tx_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cpb_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_aloc_u; + +/* Define the union csr_prm_tx_cpb_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_cpb_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_cpb_aloc_cnt_u; + +/* Define the union csr_prm_tx_oq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_oq_aloc_cnt_wr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_oq_aloc_u; + +/* Define the union csr_prm_tx_oq_aloc_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bmh_oq_aloc_cnt_num : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_oq_aloc_cnt_u; + +/* Define the union csr_prm_tx_double_daloc_wgt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stf_stl_daloc_pg3_wgt_cfg : 8; /* [7:0] */ + u32 stf_stl_daloc_pg2_wgt_cfg : 8; /* [15:8] */ + u32 rsv_105 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_double_daloc_wgt_u; + +/* Define the union csr_prm_tx_err_src_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cos_uder_src_err : 9; /* [8:0] */ + u32 cos_over_src_err : 9; /* [17:9] */ + u32 rsv_106 : 14; /* [31:18] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_tx_err_src_u; + +/* Define the union csr_prmtx_bw_monitor_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_cpb_aloc_bdmonitor_en : 1; /* [0] */ + u32 csr_prmtx_cpi_aloc_bdmonitor_en : 1; /* [1] */ + u32 csr_prmtx_oq_aloc_bdmonitor_en : 1; /* [2] */ + u32 csr_prmtx_cpb_daloc_bdmonitor_en : 1; /* [3] */ + u32 csr_prmtx_cpb_drop_bdmonitor_en : 1; /* [4] */ + u32 csr_prmtx_stliq_bdmonitor_en : 1; /* [5] */ + u32 csr_prmtx_stfiq_bdmonitor_en : 1; /* [6] */ + u32 csr_prmtx_stlfq_aloc_bdmonitor_en : 1; /* [7] */ + u32 csr_prmtx_stffq0_aloc_bdmonitor_en : 1; /* [8] */ + u32 csr_prmtx_stffq1_aloc_bdmonitor_en : 1; /* [9] */ + u32 csr_prmtx_stlfq_daloc_bdmonitor_en : 1; /* [10] */ + u32 csr_prmtx_stffq0_daloc_bdmonitor_en : 1; /* [11] */ + u32 csr_prmtx_stffq1_daloc_bdmonitor_en : 1; /* [12] */ + u32 csr_prmtx_oq_daloc_bdmonitor_en : 1; /* [13] */ + u32 rsv_107 : 18; /* [31:14] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_en_u; + +/* Define the union csr_prmtx_bw_monitor_win_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_win_len : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_win_len_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_cpb_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_cpb_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_cpi_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_cpi_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_cpi_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_oq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_oq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_oq_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_cpb_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_cpb_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_cpb_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_cpb_drop_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stliq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stliq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stliq_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stfiq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stfiq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stfiq_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stlfq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stlfq_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stffq0_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stffq0_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stffq1_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stffq1_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stlfq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stlfq_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stffq0_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stffq0_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_stffq1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_stffq1_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_max_times_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prmtx_bdmonitro_max_times_oq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_max_times_oq_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_win_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_win_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_win_cnt_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_cpb_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_cpb_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_cpb_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_cpi_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_cpi_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_cpi_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_oq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_oq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_oq_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_cpb_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_cpb_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_cpb_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_cpb_drop_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_cpb_drop : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_cpb_drop_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stliq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stliq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stliq_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stfiq_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stfiq : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stfiq_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stlfq_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stffq0_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_aloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stffq1_aloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_aloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stlfq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stffq0_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_stffq1_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_daloc_u; + +/* Define the union csr_prmtx_bw_monitor_over_max_times_cnt_oq_daloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prmtx_csr_bdmonitor_over_max_cnt_oq_daloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prmtx_bw_monitor_over_max_times_cnt_oq_daloc_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_prm_tx_indrect_ctrl_u prm_tx_indrect_ctrl; /* 0 */ + volatile csr_prm_tx_indrect_timeout_u prm_tx_indrect_timeout; /* 4 */ + volatile csr_prm_tx_indrect_dat0_u prm_tx_indrect_dat0; /* 8 */ + volatile csr_prm_tx_indrect_dat1_u prm_tx_indrect_dat1; /* C */ + volatile csr_prm_tx_indrect_dat2_u prm_tx_indrect_dat2; /* 10 */ + volatile csr_prm_tx_indrect_dat3_u prm_tx_indrect_dat3; /* 14 */ + volatile csr_prm_tx_indrect_dat4_u prm_tx_indrect_dat4; /* 18 */ + volatile csr_prm_tx_indrect_dat5_u prm_tx_indrect_dat5; /* 1C */ + volatile csr_prm_tx_indrect_dat6_u prm_tx_indrect_dat6; /* 20 */ + volatile csr_prm_tx_csr_cfg_u prm_tx_csr_cfg; /* 30 */ + volatile csr_prm_tx_y_stf_fc_th_cfg_u prm_tx_y_stf_fc_th_cfg; /* 34 */ + volatile csr_prm_tx_y_stl_fc_th_cfg_u prm_tx_y_stl_fc_th_cfg; /* 38 */ + volatile csr_prm_tx_r_stf_fc_th_cfg_u prm_tx_r_stf_fc_th_cfg; /* 3C */ + volatile csr_prm_tx_r_stl_fc_th_cfg_u prm_tx_r_stl_fc_th_cfg; /* 40 */ + volatile csr_prm_tx_y_stf_rsvd_cfg_u prm_tx_y_stf_rsvd_cfg; /* 44 */ + volatile csr_prm_tx_y_stl_rsvd_cfg_u prm_tx_y_stl_rsvd_cfg; /* 48 */ + volatile csr_prm_tx_r_stf_rsvd_cfg_u prm_tx_r_stf_rsvd_cfg; /* 4C */ + volatile csr_prm_tx_r_stl_rsvd_cfg_u prm_tx_r_stl_rsvd_cfg; /* 50 */ + volatile csr_prm_tx_y_stf_cnt_u prm_tx_y_stf_cnt; /* 54 */ + volatile csr_prm_tx_y_stl_cnt_u prm_tx_y_stl_cnt; /* 58 */ + volatile csr_prm_tx_r_stf_cnt_u prm_tx_r_stf_cnt; /* 5C */ + volatile csr_prm_tx_r_stl_cnt_u prm_tx_r_stl_cnt; /* 60 */ + volatile csr_prm_tx_y_stf_sh_cnt_u prm_tx_y_stf_sh_cnt; /* 64 */ + volatile csr_prm_tx_y_stl_sh_cnt_u prm_tx_y_stl_sh_cnt; /* 68 */ + volatile csr_prm_tx_r_stf_sh_cnt_u prm_tx_r_stf_sh_cnt; /* 6C */ + volatile csr_prm_tx_r_stl_sh_cnt_u prm_tx_r_stl_sh_cnt; /* 70 */ + volatile csr_prm_tx_y_mon_cfg_u prm_tx_y_mon_cfg; /* 74 */ + volatile csr_prm_tx_y_his_cfg_u prm_tx_y_his_cfg; /* 78 */ + volatile csr_prm_tx_r_mon_cfg_u prm_tx_r_mon_cfg; /* 7C */ + volatile csr_prm_tx_r_his_cfg_u prm_tx_r_his_cfg; /* 80 */ + volatile csr_prm_tx_stlfq_aloc_u prm_tx_stlfq_aloc; /* 84 */ + volatile csr_prm_tx_stffq0_aloc_u prm_tx_stffq0_aloc; /* 88 */ + volatile csr_prm_tx_stffq1_aloc_u prm_tx_stffq1_aloc; /* 8C */ + volatile csr_prm_tx_stlfq_daloc_u prm_tx_stlfq_daloc; /* 90 */ + volatile csr_prm_tx_stffq0_daloc_u prm_tx_stffq0_daloc; /* 94 */ + volatile csr_prm_tx_stffq1_daloc_u prm_tx_stffq1_daloc; /* 98 */ + volatile csr_prm_tx_cpb_daloc_u prm_tx_cpb_daloc; /* 9C */ + volatile csr_prm_tx_cpb_drop_u prm_tx_cpb_drop; /* A0 */ + volatile csr_prm_tx_oq_daloc_u prm_tx_oq_daloc; /* A4 */ + volatile csr_prm_tx_stlfq_aloc_cnt_u prm_tx_stlfq_aloc_cnt; /* A8 */ + volatile csr_prm_tx_stffq0_aloc_cnt_u prm_tx_stffq0_aloc_cnt; /* AC */ + volatile csr_prm_tx_stffq1_aloc_cnt_u prm_tx_stffq1_aloc_cnt; /* B0 */ + volatile csr_prm_tx_stlfq_daloc_cnt_u prm_tx_stlfq_daloc_cnt; /* B4 */ + volatile csr_prm_tx_stffq0_daloc_cnt_u prm_tx_stffq0_daloc_cnt; /* B8 */ + volatile csr_prm_tx_stffq1_daloc_cnt_u prm_tx_stffq1_daloc_cnt; /* BC */ + volatile csr_prm_tx_cpb_daloc_cnt_u prm_tx_cpb_daloc_cnt; /* C0 */ + volatile csr_prm_tx_cpb_drop_cnt_u prm_tx_cpb_drop_cnt; /* C4 */ + volatile csr_prm_tx_oq_daloc_cnt_u prm_tx_oq_daloc_cnt; /* C8 */ + volatile csr_prm_tx_r_stf_p_his_cnt_u prm_tx_r_stf_p_his_cnt; /* CC */ + volatile csr_prm_tx_r_stl_p_his_cnt_u prm_tx_r_stl_p_his_cnt; /* D0 */ + volatile csr_prm_tx_r_stf_srv_his_cnt_u prm_tx_r_stf_srv_his_cnt; /* D4 */ + volatile csr_prm_tx_r_stl_srv_his_cnt_u prm_tx_r_stl_srv_his_cnt; /* D8 */ + volatile csr_prm_tx_r_stf_srv_sh_his_cnt_u prm_tx_r_stf_srv_sh_his_cnt; /* DC */ + volatile csr_prm_tx_r_stl_srv_sh_his_cnt_u prm_tx_r_stl_srv_sh_his_cnt; /* E0 */ + volatile csr_prm_tx_r_stf_st_his_cnt_u prm_tx_r_stf_st_his_cnt; /* E4 */ + volatile csr_prm_tx_r_stl_st_his_cnt_u prm_tx_r_stl_st_his_cnt; /* E8 */ + volatile csr_prm_tx_r_stf_st_sh_his_cnt_u prm_tx_r_stf_st_sh_his_cnt; /* EC */ + volatile csr_prm_tx_r_stl_st_sh_his_cnt_u prm_tx_r_stl_st_sh_his_cnt; /* F0 */ + volatile csr_prm_tx_stfiq_aloc_u prm_tx_stfiq_aloc; /* F4 */ + volatile csr_prm_tx_stliq_aloc_u prm_tx_stliq_aloc; /* F8 */ + volatile csr_prm_tx_yda_daloc_u prm_tx_yda_daloc; /* FC */ + volatile csr_prm_tx_stfiq_aloc_cnt_u prm_tx_stfiq_aloc_cnt; /* 100 */ + volatile csr_prm_tx_stliq_aloc_cnt_u prm_tx_stliq_aloc_cnt; /* 104 */ + volatile csr_prm_tx_yda_daloc_cnt_u prm_tx_yda_daloc_cnt; /* 108 */ + volatile csr_prm_tx_y_stf_p_his_cnt_u prm_tx_y_stf_p_his_cnt; /* 10C */ + volatile csr_prm_tx_y_stl_p_his_cnt_u prm_tx_y_stl_p_his_cnt; /* 110 */ + volatile csr_prm_tx_y_stf_st_his_cnt_u prm_tx_y_stf_st_his_cnt; /* 114 */ + volatile csr_prm_tx_y_stl_st_his_cnt_u prm_tx_y_stl_st_his_cnt; /* 118 */ + volatile csr_prm_tx_y_stf_st_sh_his_cnt_u prm_tx_y_stf_st_sh_his_cnt; /* 11C */ + volatile csr_prm_tx_y_stl_st_sh_his_cnt_u prm_tx_y_stl_st_sh_his_cnt; /* 120 */ + volatile csr_prm_tx_g_mon_cfg_u prm_tx_g_mon_cfg; /* 124 */ + volatile csr_prm_tx_g_his_cfg_u prm_tx_g_his_cfg; /* 128 */ + volatile csr_prm_tx_cpi_aloc_u prm_tx_cpi_aloc; /* 12C */ + volatile csr_prm_tx_grq_aloc_u prm_tx_grq_aloc; /* 130 */ + volatile csr_prm_tx_grq_daloc_u prm_tx_grq_daloc; /* 134 */ + volatile csr_prm_tx_cpi_aloc_cnt_u prm_tx_cpi_aloc_cnt; /* 138 */ + volatile csr_prm_tx_grq_aloc_cnt_u prm_tx_grq_aloc_cnt; /* 13C */ + volatile csr_prm_tx_grq_daloc_cnt_u prm_tx_grq_daloc_cnt; /* 140 */ + volatile csr_prm_tx_h_cos_his_cnt_u prm_tx_h_cos_his_cnt; /* 144 */ + volatile csr_prm_tx_h_p_his_cnt_u prm_tx_h_p_his_cnt; /* 148 */ + volatile csr_prm_tx_h_p_sh_his_cnt_u prm_tx_h_p_sh_his_cnt; /* 14C */ + volatile csr_prm_tx_h_srv_his_cnt_u prm_tx_h_srv_his_cnt; /* 150 */ + volatile csr_prm_tx_h_srv_sh_his_cnt_u prm_tx_h_srv_sh_his_cnt; /* 154 */ + volatile csr_prm_tx_glb_rsvd_cfg_u prm_tx_glb_rsvd_cfg; /* 158 */ + volatile csr_prm_tx_glb_fc_th_cfg0_u prm_tx_glb_fc_th_cfg0; /* 15C */ + volatile csr_prm_tx_glb_fc_th_cfg1_u prm_tx_glb_fc_th_cfg1; /* 160 */ + volatile csr_prm_tx_glb_fc_th_cfg2_u prm_tx_glb_fc_th_cfg2; /* 164 */ + volatile csr_prm_tx_glb_drp_th_cfg_u prm_tx_glb_drp_th_cfg; /* 168 */ + volatile csr_prm_tx_pg1_rsvd_cfg_u prm_tx_pg1_rsvd_cfg; /* 16C */ + volatile csr_prm_tx_pg1_fc_th_cfg0_u prm_tx_pg1_fc_th_cfg0; /* 170 */ + volatile csr_prm_tx_pg1_fc_th_cfg1_u prm_tx_pg1_fc_th_cfg1; /* 174 */ + volatile csr_prm_tx_pg1_fc_th_cfg2_u prm_tx_pg1_fc_th_cfg2; /* 178 */ + volatile csr_prm_tx_pg1_drp_th_cfg_u prm_tx_pg1_drp_th_cfg; /* 17C */ + volatile csr_prm_tx_pg2_rsvd_cfg_u prm_tx_pg2_rsvd_cfg; /* 180 */ + volatile csr_prm_tx_pg2_fc_th_cfg0_u prm_tx_pg2_fc_th_cfg0; /* 184 */ + volatile csr_prm_tx_pg2_fc_th_cfg1_u prm_tx_pg2_fc_th_cfg1; /* 188 */ + volatile csr_prm_tx_pg2_fc_th_cfg2_u prm_tx_pg2_fc_th_cfg2; /* 18C */ + volatile csr_prm_tx_pg2_drp_th_cfg_u prm_tx_pg2_drp_th_cfg; /* 190 */ + volatile csr_prm_tx_pg3_rsvd_cfg_u prm_tx_pg3_rsvd_cfg; /* 194 */ + volatile csr_prm_tx_pg3_fc_th_cfg0_u prm_tx_pg3_fc_th_cfg0; /* 198 */ + volatile csr_prm_tx_pg3_fc_th_cfg1_u prm_tx_pg3_fc_th_cfg1; /* 19C */ + volatile csr_prm_tx_pg3_fc_th_cfg2_u prm_tx_pg3_fc_th_cfg2; /* 1A0 */ + volatile csr_prm_tx_pg3_drp_th_cfg_u prm_tx_pg3_drp_th_cfg; /* 1A4 */ + volatile csr_prm_tx_pg1_cnt_u prm_tx_pg1_cnt; /* 1A8 */ + volatile csr_prm_tx_pg2_cnt_u prm_tx_pg2_cnt; /* 1AC */ + volatile csr_prm_tx_pg3_cnt_u prm_tx_pg3_cnt; /* 1B0 */ + volatile csr_prm_tx_glb_cnt_u prm_tx_glb_cnt; /* 1B4 */ + volatile csr_prm_tx_glb_max_cnt_cfg_u prm_tx_glb_max_cnt_cfg; /* 1B8 */ + volatile csr_prm_tx_cpi_req_cfg_u prm_tx_cpi_req_cfg; /* 1BC */ + volatile csr_prm_tx_mqm_uload_cfg_u prm_tx_mqm_uload_cfg; /* 1C0 */ + volatile csr_prm_tx_bmh_wrr_cfg_u prm_tx_bmh_wrr_cfg; /* 1C4 */ + volatile csr_prm_tx_bmy_wrr_cfg_u prm_tx_bmy_wrr_cfg; /* 1C8 */ + volatile csr_prm_tx_bmr_wrr_cfg0_u prm_tx_bmr_wrr_cfg0; /* 1CC */ + volatile csr_prm_tx_bmr_wrr_cfg1_u prm_tx_bmr_wrr_cfg1; /* 1D0 */ + volatile csr_prm_tx_bmg_wrr_cfg_u prm_tx_bmg_wrr_cfg; /* 1D4 */ + volatile csr_prm_tx_cnt_over_flag_u prm_tx_cnt_over_flag; /* 1D8 */ + volatile csr_prm_tx_cnt_under_flag_u prm_tx_cnt_under_flag; /* 1DC */ + volatile csr_prm_tx_fifo_th_cfg0_u prm_tx_fifo_th_cfg0; /* 1E0 */ + volatile csr_prm_tx_fifo_th_cfg1_u prm_tx_fifo_th_cfg1; /* 1E4 */ + volatile csr_prm_tx_fifo_th_cfg2_u prm_tx_fifo_th_cfg2; /* 1E8 */ + volatile csr_prm_tx_cpb_aloc_u prm_tx_cpb_aloc; /* 1EC */ + volatile csr_prm_tx_cpb_aloc_cnt_u prm_tx_cpb_aloc_cnt; /* 1F0 */ + volatile csr_prm_tx_oq_aloc_u prm_tx_oq_aloc; /* 1F4 */ + volatile csr_prm_tx_oq_aloc_cnt_u prm_tx_oq_aloc_cnt; /* 1F8 */ + volatile csr_prm_tx_double_daloc_wgt_u prm_tx_double_daloc_wgt; /* 1FC */ + volatile csr_prm_tx_err_src_u prm_tx_err_src; /* 200 */ + volatile csr_prmtx_bw_monitor_en_u prmtx_bw_monitor_en; /* 234 */ + volatile csr_prmtx_bw_monitor_win_len_u prmtx_bw_monitor_win_len; /* 238 */ + volatile csr_prmtx_bw_monitor_max_times_cpb_aloc_u prmtx_bw_monitor_max_times_cpb_aloc; /* 23C */ + volatile csr_prmtx_bw_monitor_max_times_cpi_aloc_u prmtx_bw_monitor_max_times_cpi_aloc; /* 240 */ + volatile csr_prmtx_bw_monitor_max_times_oq_aloc_u prmtx_bw_monitor_max_times_oq_aloc; /* 244 */ + volatile csr_prmtx_bw_monitor_max_times_cpb_daloc_u prmtx_bw_monitor_max_times_cpb_daloc; /* 248 */ + volatile csr_prmtx_bw_monitor_max_times_cpb_drop_u prmtx_bw_monitor_max_times_cpb_drop; /* 24C */ + volatile csr_prmtx_bw_monitor_max_times_stliq_u prmtx_bw_monitor_max_times_stliq; /* 250 */ + volatile csr_prmtx_bw_monitor_max_times_stfiq_u prmtx_bw_monitor_max_times_stfiq; /* 254 */ + volatile csr_prmtx_bw_monitor_max_times_stlfq_aloc_u prmtx_bw_monitor_max_times_stlfq_aloc; /* 258 */ + volatile csr_prmtx_bw_monitor_max_times_stffq0_aloc_u prmtx_bw_monitor_max_times_stffq0_aloc; /* 25C */ + volatile csr_prmtx_bw_monitor_max_times_stffq1_aloc_u prmtx_bw_monitor_max_times_stffq1_aloc; /* 260 */ + volatile csr_prmtx_bw_monitor_max_times_stlfq_daloc_u prmtx_bw_monitor_max_times_stlfq_daloc; /* 264 */ + volatile csr_prmtx_bw_monitor_max_times_stffq0_daloc_u prmtx_bw_monitor_max_times_stffq0_daloc; /* 268 */ + volatile csr_prmtx_bw_monitor_max_times_stffq1_daloc_u prmtx_bw_monitor_max_times_stffq1_daloc; /* 26C */ + volatile csr_prmtx_bw_monitor_max_times_oq_daloc_u prmtx_bw_monitor_max_times_oq_daloc; /* 270 */ + volatile csr_prmtx_bw_monitor_win_cnt_u prmtx_bw_monitor_win_cnt; /* 274 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_cpb_aloc_u prmtx_bw_monitor_over_max_times_cnt_cpb_aloc; /* 278 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_cpi_aloc_u prmtx_bw_monitor_over_max_times_cnt_cpi_aloc; /* 27C */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_oq_aloc_u prmtx_bw_monitor_over_max_times_cnt_oq_aloc; /* 280 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_cpb_daloc_u prmtx_bw_monitor_over_max_times_cnt_cpb_daloc; /* 284 + */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_cpb_drop_u prmtx_bw_monitor_over_max_times_cnt_cpb_drop; /* 288 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stliq_u prmtx_bw_monitor_over_max_times_cnt_stliq; /* 28C */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stfiq_u prmtx_bw_monitor_over_max_times_cnt_stfiq; /* 290 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_aloc_u prmtx_bw_monitor_over_max_times_cnt_stlfq_aloc; /* 294 + */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_aloc_u + prmtx_bw_monitor_over_max_times_cnt_stffq0_aloc; /* 298 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_aloc_u + prmtx_bw_monitor_over_max_times_cnt_stffq1_aloc; /* 29C */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stlfq_daloc_u + prmtx_bw_monitor_over_max_times_cnt_stlfq_daloc; /* 2A0 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stffq0_daloc_u + prmtx_bw_monitor_over_max_times_cnt_stffq0_daloc; /* 2A4 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_stffq1_daloc_u + prmtx_bw_monitor_over_max_times_cnt_stffq1_daloc; /* 2A8 */ + volatile csr_prmtx_bw_monitor_over_max_times_cnt_oq_daloc_u prmtx_bw_monitor_over_max_times_cnt_oq_daloc; /* 2AC */ +} S_qu_prm_tx_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_prm_tx_csr */ +extern volatile S_qu_prm_tx_csr_REGS_TYPE *gopqu_prm_tx_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetPRM_TX_INDRECT_CTRL_indirect_ctrl(unsigned int uindirect_ctrl); +int iSetPRM_TX_INDRECT_TIMEOUT_indirect_timeout(unsigned int uindirect_timeout); +int iSetPRM_TX_INDRECT_DAT0_indirect_dat0(unsigned int uindirect_dat0); +int iSetPRM_TX_INDRECT_DAT1_indirect_dat1(unsigned int uindirect_dat1); +int iSetPRM_TX_INDRECT_DAT2_indirect_dat2(unsigned int uindirect_dat2); +int iSetPRM_TX_INDRECT_DAT3_indirect_dat3(unsigned int uindirect_dat3); +int iSetPRM_TX_INDRECT_DAT4_indirect_dat4(unsigned int uindirect_dat4); +int iSetPRM_TX_INDRECT_DAT5_indirect_dat5(unsigned int uindirect_dat5); +int iSetPRM_TX_INDRECT_DAT6_indirect_dat6(unsigned int uindirect_dat6); +int iSetPRM_TX_CSR_CFG_dyn_csr_req_src(unsigned int udyn_csr_req_src); +int iSetPRM_TX_CSR_CFG_bmr_dyn_csr_req(unsigned int ubmr_dyn_csr_req); +int iSetPRM_TX_CSR_CFG_bmy_dyn_csr_req(unsigned int ubmy_dyn_csr_req); +int iSetPRM_TX_CSR_CFG_bmh_dyn_csr_req(unsigned int ubmh_dyn_csr_req); +int iSetPRM_TX_Y_STF_FC_TH_CFG_stf_state_y_fc0_th_on(unsigned int ustf_state_y_fc0_th_on); +int iSetPRM_TX_Y_STF_FC_TH_CFG_stf_state_y_fc0_th_dif(unsigned int ustf_state_y_fc0_th_dif); +int iSetPRM_TX_Y_STL_FC_TH_CFG_stl_state_y_fc0_th_on(unsigned int ustl_state_y_fc0_th_on); +int iSetPRM_TX_Y_STL_FC_TH_CFG_stl_state_y_fc0_th_dif(unsigned int ustl_state_y_fc0_th_dif); +int iSetPRM_TX_R_STF_FC_TH_CFG_stf_state_r_fc0_th_on(unsigned int ustf_state_r_fc0_th_on); +int iSetPRM_TX_R_STF_FC_TH_CFG_stf_state_r_fc0_th_dif(unsigned int ustf_state_r_fc0_th_dif); +int iSetPRM_TX_R_STL_FC_TH_CFG_stl_state_r_fc0_th_on(unsigned int ustl_state_r_fc0_th_on); +int iSetPRM_TX_R_STL_FC_TH_CFG_stl_state_r_fc0_th_dif(unsigned int ustl_state_r_fc0_th_dif); +int iSetPRM_TX_Y_STF_RSVD_CFG_stf_state_y_rsvd(unsigned int ustf_state_y_rsvd); +int iSetPRM_TX_Y_STL_RSVD_CFG_stl_state_y_rsvd(unsigned int ustl_state_y_rsvd); +int iSetPRM_TX_R_STF_RSVD_CFG_stf_state_r_rsvd(unsigned int ustf_state_r_rsvd); +int iSetPRM_TX_R_STL_RSVD_CFG_stl_state_r_rsvd(unsigned int ustl_state_r_rsvd); +int iSetPRM_TX_Y_STF_CNT_stf_state_y_cnt(unsigned int ustf_state_y_cnt); +int iSetPRM_TX_Y_STL_CNT_stl_state_y_cnt(unsigned int ustl_state_y_cnt); +int iSetPRM_TX_R_STF_CNT_stf_state_r_cnt(unsigned int ustf_state_r_cnt); +int iSetPRM_TX_R_STL_CNT_stl_state_r_cnt(unsigned int ustl_state_r_cnt); +int iSetPRM_TX_Y_STF_SH_CNT_stf_state_y_sh_cnt(unsigned int ustf_state_y_sh_cnt); +int iSetPRM_TX_Y_STL_SH_CNT_stl_state_y_sh_cnt(unsigned int ustl_state_y_sh_cnt); +int iSetPRM_TX_R_STF_SH_CNT_stf_state_r_sh_cnt(unsigned int ustf_state_r_sh_cnt); +int iSetPRM_TX_R_STL_SH_CNT_stl_state_r_sh_cnt(unsigned int ustl_state_r_sh_cnt); +int iSetPRM_TX_Y_MON_CFG_bmy_cfg_mon_cos(unsigned int ubmy_cfg_mon_cos); +int iSetPRM_TX_Y_MON_CFG_bmy_cfg_mon_sp(unsigned int ubmy_cfg_mon_sp); +int iSetPRM_TX_Y_MON_CFG_bmy_cfg_mon_srv(unsigned int ubmy_cfg_mon_srv); +int iSetPRM_TX_Y_MON_CFG_bmy_cfg_cnt_type(unsigned int ubmy_cfg_cnt_type); +int iSetPRM_TX_Y_MON_CFG_bmy_cfg_cnt_en(unsigned int ubmy_cfg_cnt_en); +int iSetPRM_TX_Y_HIS_CFG_bmy_cfg_his_cnt_sp(unsigned int ubmy_cfg_his_cnt_sp); +int iSetPRM_TX_Y_HIS_CFG_bmy_cfg_his_cnt_srv(unsigned int ubmy_cfg_his_cnt_srv); +int iSetPRM_TX_Y_HIS_CFG_bmy_cfg_his_cnt_clr(unsigned int ubmy_cfg_his_cnt_clr); +int iSetPRM_TX_Y_HIS_CFG_bmy_cfg_his_cnt_en(unsigned int ubmy_cfg_his_cnt_en); +int iSetPRM_TX_R_MON_CFG_bmr_cfg_mon_cos(unsigned int ubmr_cfg_mon_cos); +int iSetPRM_TX_R_MON_CFG_bmr_cfg_mon_sp(unsigned int ubmr_cfg_mon_sp); +int iSetPRM_TX_R_MON_CFG_bmr_cfg_mon_srv(unsigned int ubmr_cfg_mon_srv); +int iSetPRM_TX_R_MON_CFG_bmr_cfg_cnt_type(unsigned int ubmr_cfg_cnt_type); +int iSetPRM_TX_R_MON_CFG_bmr_cfg_cnt_en(unsigned int ubmr_cfg_cnt_en); +int iSetPRM_TX_R_HIS_CFG_bmr_cfg_his_cnt_sp(unsigned int ubmr_cfg_his_cnt_sp); +int iSetPRM_TX_R_HIS_CFG_bmr_cfg_his_cnt_srv(unsigned int ubmr_cfg_his_cnt_srv); +int iSetPRM_TX_R_HIS_CFG_bmr_cfg_his_cnt_clr(unsigned int ubmr_cfg_his_cnt_clr); +int iSetPRM_TX_R_HIS_CFG_bmr_cfg_his_cnt_en(unsigned int ubmr_cfg_his_cnt_en); +int iSetPRM_TX_STLFQ_ALOC_bmr_stlfq_aloc_cnt_wr_v(unsigned int ubmr_stlfq_aloc_cnt_wr_v); +int iSetPRM_TX_STFFQ0_ALOC_bmr_stffq0_aloc_cnt_wr_v(unsigned int ubmr_stffq0_aloc_cnt_wr_v); +int iSetPRM_TX_STFFQ1_ALOC_bmr_stffq1_aloc_cnt_wr_v(unsigned int ubmr_stffq1_aloc_cnt_wr_v); +int iSetPRM_TX_STLFQ_DALOC_bmr_stlfq_daloc_cnt_wr_v(unsigned int ubmr_stlfq_daloc_cnt_wr_v); +int iSetPRM_TX_STFFQ0_DALOC_bmr_stffq0_daloc_cnt_wr_v(unsigned int ubmr_stffq0_daloc_cnt_wr_v); +int iSetPRM_TX_STFFQ1_DALOC_bmr_stffq1_daloc_cnt_wr_v(unsigned int ubmr_stffq1_daloc_cnt_wr_v); +int iSetPRM_TX_CPB_DALOC_bmr_cpb_daloc_cnt_wr_v(unsigned int ubmr_cpb_daloc_cnt_wr_v); +int iSetPRM_TX_CPB_DROP_bmr_cpb_drop_cnt_wr_v(unsigned int ubmr_cpb_drop_cnt_wr_v); +int iSetPRM_TX_OQ_DALOC_bmr_oq_daloc_cnt_wr_v(unsigned int ubmr_oq_daloc_cnt_wr_v); +int iSetPRM_TX_STLFQ_ALOC_CNT_bmr_stlfq_aloc_cnt_num_v(unsigned int ubmr_stlfq_aloc_cnt_num_v); +int iSetPRM_TX_STFFQ0_ALOC_CNT_bmr_stffq0_aloc_cnt_num_v(unsigned int ubmr_stffq0_aloc_cnt_num_v); +int iSetPRM_TX_STFFQ1_ALOC_CNT_bmr_stffq1_aloc_cnt_num_v(unsigned int ubmr_stffq1_aloc_cnt_num_v); +int iSetPRM_TX_STLFQ_DALOC_CNT_bmr_stlfq_daloc_cnt_num_v(unsigned int ubmr_stlfq_daloc_cnt_num_v); +int iSetPRM_TX_STFFQ0_DALOC_CNT_bmr_stffq0_daloc_cnt_num_v(unsigned int ubmr_stffq0_daloc_cnt_num_v); +int iSetPRM_TX_STFFQ1_DALOC_CNT_bmr_stffq1_daloc_cnt_num_v(unsigned int ubmr_stffq1_daloc_cnt_num_v); +int iSetPRM_TX_CPB_DALOC_CNT_bmr_cpb_daloc_cnt_num_v(unsigned int ubmr_cpb_daloc_cnt_num_v); +int iSetPRM_TX_CPB_DROP_CNT_bmr_cpb_drop_cnt_num_v(unsigned int ubmr_cpb_drop_cnt_num_v); +int iSetPRM_TX_OQ_DALOC_CNT_bmr_oq_daloc_cnt_num_v(unsigned int ubmr_oq_daloc_cnt_num_v); +int iSetPRM_TX_R_STF_P_HIS_CNT_bmr_stf_his_cnt_port(unsigned int ubmr_stf_his_cnt_port); +int iSetPRM_TX_R_STL_P_HIS_CNT_bmr_stl_his_cnt_port(unsigned int ubmr_stl_his_cnt_port); +int iSetPRM_TX_R_STF_SRV_HIS_CNT_bmr_stf_his_cnt_srv(unsigned int ubmr_stf_his_cnt_srv); +int iSetPRM_TX_R_STL_SRV_HIS_CNT_bmr_stl_his_cnt_srv(unsigned int ubmr_stl_his_cnt_srv); +int iSetPRM_TX_R_STF_SRV_SH_HIS_CNT_bmr_stf_his_cnt_srv_sh(unsigned int ubmr_stf_his_cnt_srv_sh); +int iSetPRM_TX_R_STL_SRV_SH_HIS_CNT_bmr_stl_his_cnt_srv_sh(unsigned int ubmr_stl_his_cnt_srv_sh); +int iSetPRM_TX_R_STF_ST_HIS_CNT_bmr_stf_his_cnt_st(unsigned int ubmr_stf_his_cnt_st); +int iSetPRM_TX_R_STL_ST_HIS_CNT_bmr_stl_his_cnt_st(unsigned int ubmr_stl_his_cnt_st); +int iSetPRM_TX_R_STF_ST_SH_HIS_CNT_bmr_stf_his_cnt_st_sh(unsigned int ubmr_stf_his_cnt_st_sh); +int iSetPRM_TX_R_STL_ST_SH_HIS_CNT_bmr_stl_his_cnt_st_sh(unsigned int ubmr_stl_his_cnt_st_sh); +int iSetPRM_TX_STFIQ_ALOC_bmy_stf_iq_icb_aloc_cnt_wr(unsigned int ubmy_stf_iq_icb_aloc_cnt_wr); +int iSetPRM_TX_STLIQ_ALOC_bmy_stl_iq_icb_aloc_cnt_wr(unsigned int ubmy_stl_iq_icb_aloc_cnt_wr); +int iSetPRM_TX_YDA_DALOC_bmy_yda_daloc_cnt_wr(unsigned int ubmy_yda_daloc_cnt_wr); +int iSetPRM_TX_STFIQ_ALOC_CNT_bmy_stf_iq_icb_aloc_cnt_num(unsigned int ubmy_stf_iq_icb_aloc_cnt_num); +int iSetPRM_TX_STLIQ_ALOC_CNT_bmy_stl_iq_icb_aloc_cnt_num(unsigned int ubmy_stl_iq_icb_aloc_cnt_num); +int iSetPRM_TX_YDA_DALOC_CNT_bmy_yda_daloc_cnt_num(unsigned int ubmy_yda_daloc_cnt_num); +int iSetPRM_TX_Y_STF_P_HIS_CNT_bmy_stf_his_cnt_port(unsigned int ubmy_stf_his_cnt_port); +int iSetPRM_TX_Y_STL_P_HIS_CNT_bmy_stl_his_cnt_port(unsigned int ubmy_stl_his_cnt_port); +int iSetPRM_TX_Y_STF_ST_HIS_CNT_bmy_stf_his_cnt_st(unsigned int ubmy_stf_his_cnt_st); +int iSetPRM_TX_Y_STL_ST_HIS_CNT_bmy_stl_his_cnt_st(unsigned int ubmy_stl_his_cnt_st); +int iSetPRM_TX_Y_STF_ST_SH_HIS_CNT_bmy_stf_his_cnt_st_sh(unsigned int ubmy_stf_his_cnt_st_sh); +int iSetPRM_TX_Y_STL_ST_SH_HIS_CNT_bmy_stl_his_cnt_st_sh(unsigned int ubmy_stl_his_cnt_st_sh); +int iSetPRM_TX_G_MON_CFG_bmh_cfg_mon_cos(unsigned int ubmh_cfg_mon_cos); +int iSetPRM_TX_G_MON_CFG_bmh_cfg_mon_sp(unsigned int ubmh_cfg_mon_sp); +int iSetPRM_TX_G_MON_CFG_bmh_cfg_mon_side(unsigned int ubmh_cfg_mon_side); +int iSetPRM_TX_G_MON_CFG_bmh_cfg_cnt_type(unsigned int ubmh_cfg_cnt_type); +int iSetPRM_TX_G_MON_CFG_bmh_cfg_cnt_en(unsigned int ubmh_cfg_cnt_en); +int iSetPRM_TX_G_HIS_CFG_bmh_cfg_his_cnt_cos(unsigned int ubmh_cfg_his_cnt_cos); +int iSetPRM_TX_G_HIS_CFG_bmh_cfg_his_cnt_sp(unsigned int ubmh_cfg_his_cnt_sp); +int iSetPRM_TX_G_HIS_CFG_bmh_cfg_his_cnt_clr(unsigned int ubmh_cfg_his_cnt_clr); +int iSetPRM_TX_G_HIS_CFG_bmh_cfg_his_cnt_en(unsigned int ubmh_cfg_his_cnt_en); +int iSetPRM_TX_CPI_ALOC_bmh_cpi_aloc_cnt_wr(unsigned int ubmh_cpi_aloc_cnt_wr); +int iSetPRM_TX_GRQ_ALOC_bmh_grq_aloc_cnt_wr(unsigned int ubmh_grq_aloc_cnt_wr); +int iSetPRM_TX_GRQ_DALOC_bmh_grq_daloc_cnt_wr(unsigned int ubmh_grq_daloc_cnt_wr); +int iSetPRM_TX_CPI_ALOC_CNT_bmh_cpi_aloc_cnt_num(unsigned int ubmh_cpi_aloc_cnt_num); +int iSetPRM_TX_GRQ_ALOC_CNT_bmh_grq_aloc_cnt_num(unsigned int ubmh_grq_aloc_cnt_num); +int iSetPRM_TX_GRQ_DALOC_CNT_bmh_grq_daloc_cnt_num(unsigned int ubmh_grq_daloc_cnt_num); +int iSetPRM_TX_H_COS_HIS_CNT_bmh_his_cnt_cos(unsigned int ubmh_his_cnt_cos); +int iSetPRM_TX_H_P_HIS_CNT_bmh_his_cnt_port(unsigned int ubmh_his_cnt_port); +int iSetPRM_TX_H_P_SH_HIS_CNT_bmh_his_sh_cnt_port(unsigned int ubmh_his_sh_cnt_port); +int iSetPRM_TX_H_SRV_HIS_CNT_bmh_his_cnt_srv(unsigned int ubmh_his_cnt_srv); +int iSetPRM_TX_H_SRV_SH_HIS_CNT_bmh_his_sh_cnt_srv(unsigned int ubmh_his_sh_cnt_srv); +int iSetPRM_TX_GLB_RSVD_CFG_glb_rsvd_th(unsigned int uglb_rsvd_th); +int iSetPRM_TX_GLB_FC_TH_CFG0_glb_fc0_th_on(unsigned int uglb_fc0_th_on); +int iSetPRM_TX_GLB_FC_TH_CFG0_glb_fc0_th_dif(unsigned int uglb_fc0_th_dif); +int iSetPRM_TX_GLB_FC_TH_CFG1_glb_fc1_th_on(unsigned int uglb_fc1_th_on); +int iSetPRM_TX_GLB_FC_TH_CFG1_glb_fc1_th_dif(unsigned int uglb_fc1_th_dif); +int iSetPRM_TX_GLB_FC_TH_CFG2_glb_fc2_th_on(unsigned int uglb_fc2_th_on); +int iSetPRM_TX_GLB_FC_TH_CFG2_glb_fc2_th_dif(unsigned int uglb_fc2_th_dif); +int iSetPRM_TX_GLB_DRP_TH_CFG_glb_drp_th_on(unsigned int uglb_drp_th_on); +int iSetPRM_TX_GLB_DRP_TH_CFG_glb_drp_th_dif(unsigned int uglb_drp_th_dif); +int iSetPRM_TX_PG1_RSVD_CFG_pg1_rsvd_th(unsigned int upg1_rsvd_th); +int iSetPRM_TX_PG1_FC_TH_CFG0_pg1_fc0_th_on(unsigned int upg1_fc0_th_on); +int iSetPRM_TX_PG1_FC_TH_CFG0_pg1_fc0_th_dif(unsigned int upg1_fc0_th_dif); +int iSetPRM_TX_PG1_FC_TH_CFG1_pg1_fc1_th_on(unsigned int upg1_fc1_th_on); +int iSetPRM_TX_PG1_FC_TH_CFG1_pg1_fc1_th_dif(unsigned int upg1_fc1_th_dif); +int iSetPRM_TX_PG1_FC_TH_CFG2_pg1_fc2_th_on(unsigned int upg1_fc2_th_on); +int iSetPRM_TX_PG1_FC_TH_CFG2_pg1_fc2_th_dif(unsigned int upg1_fc2_th_dif); +int iSetPRM_TX_PG1_DRP_TH_CFG_pg1_drp_th_on(unsigned int upg1_drp_th_on); +int iSetPRM_TX_PG1_DRP_TH_CFG_pg1_drp_th_dif(unsigned int upg1_drp_th_dif); +int iSetPRM_TX_PG2_RSVD_CFG_pg2_rsvd_th(unsigned int upg2_rsvd_th); +int iSetPRM_TX_PG2_FC_TH_CFG0_pg2_fc0_th_on(unsigned int upg2_fc0_th_on); +int iSetPRM_TX_PG2_FC_TH_CFG0_pg2_fc0_th_dif(unsigned int upg2_fc0_th_dif); +int iSetPRM_TX_PG2_FC_TH_CFG1_pg2_fc1_th_on(unsigned int upg2_fc1_th_on); +int iSetPRM_TX_PG2_FC_TH_CFG1_pg2_fc1_th_dif(unsigned int upg2_fc1_th_dif); +int iSetPRM_TX_PG2_FC_TH_CFG2_pg2_fc2_th_on(unsigned int upg2_fc2_th_on); +int iSetPRM_TX_PG2_FC_TH_CFG2_pg2_fc2_th_dif(unsigned int upg2_fc2_th_dif); +int iSetPRM_TX_PG2_DRP_TH_CFG_pg2_drp_th_on(unsigned int upg2_drp_th_on); +int iSetPRM_TX_PG2_DRP_TH_CFG_pg2_drp_th_dif(unsigned int upg2_drp_th_dif); +int iSetPRM_TX_PG3_RSVD_CFG_pg3_rsvd_th(unsigned int upg3_rsvd_th); +int iSetPRM_TX_PG3_FC_TH_CFG0_pg3_fc0_th_on(unsigned int upg3_fc0_th_on); +int iSetPRM_TX_PG3_FC_TH_CFG0_pg3_fc0_th_dif(unsigned int upg3_fc0_th_dif); +int iSetPRM_TX_PG3_FC_TH_CFG1_pg3_fc1_th_on(unsigned int upg3_fc1_th_on); +int iSetPRM_TX_PG3_FC_TH_CFG1_pg3_fc1_th_dif(unsigned int upg3_fc1_th_dif); +int iSetPRM_TX_PG3_FC_TH_CFG2_pg3_fc2_th_on(unsigned int upg3_fc2_th_on); +int iSetPRM_TX_PG3_FC_TH_CFG2_pg3_fc2_th_dif(unsigned int upg3_fc2_th_dif); +int iSetPRM_TX_PG3_DRP_TH_CFG_pg3_drp_th_on(unsigned int upg3_drp_th_on); +int iSetPRM_TX_PG3_DRP_TH_CFG_pg3_drp_th_dif(unsigned int upg3_drp_th_dif); +int iSetPRM_TX_PG1_CNT_pg1_curr_sh_cnt_st(unsigned int upg1_curr_sh_cnt_st); +int iSetPRM_TX_PG1_CNT_pg1_curr_cnt_st(unsigned int upg1_curr_cnt_st); +int iSetPRM_TX_PG2_CNT_pg2_curr_sh_cnt_st(unsigned int upg2_curr_sh_cnt_st); +int iSetPRM_TX_PG2_CNT_pg2_curr_cnt_st(unsigned int upg2_curr_cnt_st); +int iSetPRM_TX_PG3_CNT_pg3_curr_sh_cnt_st(unsigned int upg3_curr_sh_cnt_st); +int iSetPRM_TX_PG3_CNT_pg3_curr_cnt_st(unsigned int upg3_curr_cnt_st); +int iSetPRM_TX_GLB_CNT_glb_curr_sh_cnt_st(unsigned int uglb_curr_sh_cnt_st); +int iSetPRM_TX_GLB_CNT_glb_curr_cnt_st(unsigned int uglb_curr_cnt_st); +int iSetPRM_TX_GLB_MAX_CNT_CFG_cfg_glb_max_th(unsigned int ucfg_glb_max_th); +int iSetPRM_TX_GLB_MAX_CNT_CFG_cfg_glb_max_sh(unsigned int ucfg_glb_max_sh); +int iSetPRM_TX_CPI_REQ_CFG_cfg_cpi_wg_period(unsigned int ucfg_cpi_wg_period); +int iSetPRM_TX_CPI_REQ_CFG_cfg_cpi_toke_unit(unsigned int ucfg_cpi_toke_unit); +int iSetPRM_TX_CPI_REQ_CFG_msk_sel_cpi_req(unsigned int umsk_sel_cpi_req); +int iSetPRM_TX_MQM_ULOAD_CFG_qu_mqm_underloading_th(unsigned int uqu_mqm_underloading_th); +int iSetPRM_TX_BMH_WRR_CFG_tx_bmh_wrr_wgt_cfg(unsigned int utx_bmh_wrr_wgt_cfg); +int iSetPRM_TX_BMY_WRR_CFG_tx_bmy_wrr_wgt_cfg(unsigned int utx_bmy_wrr_wgt_cfg); +int iSetPRM_TX_BMR_WRR_CFG0_tx_bmr_wrr_wgt_cfg0(unsigned int utx_bmr_wrr_wgt_cfg0); +int iSetPRM_TX_BMR_WRR_CFG1_tx_bmr_wrr_wgt_cfg1(unsigned int utx_bmr_wrr_wgt_cfg1); +int iSetPRM_TX_BMG_WRR_CFG_tx_bmg_wrr_wgt_cfg(unsigned int utx_bmg_wrr_wgt_cfg); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_cos_h_of(unsigned int umem_cnt_cos_h_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_p_h_of(unsigned int umem_cnt_p_h_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_srv_h_of(unsigned int umem_cnt_srv_h_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_p_h_of(unsigned int umem_sh_cnt_p_h_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_srv_h_of(unsigned int umem_sh_cnt_srv_h_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stf_p_y_of(unsigned int umem_cnt_stf_p_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stf_srv_y_of(unsigned int umem_cnt_stf_srv_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_stf_srv_y_of(unsigned int umem_sh_cnt_stf_srv_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stl_p_y_of(unsigned int umem_cnt_stl_p_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stl_srv_y_of(unsigned int umem_cnt_stl_srv_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_stl_srv_y_of(unsigned int umem_sh_cnt_stl_srv_y_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stf_p_r_of(unsigned int umem_cnt_stf_p_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stf_srv_r_of(unsigned int umem_cnt_stf_srv_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_stf_srv_r_of(unsigned int umem_sh_cnt_stf_srv_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stl_p_r_of(unsigned int umem_cnt_stl_p_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_cnt_stl_srv_r_of(unsigned int umem_cnt_stl_srv_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_mem_sh_cnt_stl_srv_r_of(unsigned int umem_sh_cnt_stl_srv_r_of); +int iSetPRM_TX_CNT_OVER_FLAG_glb_cnt_of(unsigned int uglb_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg3_cnt_of(unsigned int upg3_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg2_cnt_of(unsigned int upg2_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg1_cnt_of(unsigned int upg1_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_glb_sh_cnt_of(unsigned int uglb_sh_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg3_sh_cnt_of(unsigned int upg3_sh_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg2_sh_cnt_of(unsigned int upg2_sh_cnt_of); +int iSetPRM_TX_CNT_OVER_FLAG_pg1_sh_cnt_of(unsigned int upg1_sh_cnt_of); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_cos_h_uf(unsigned int umem_cnt_cos_h_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_p_h_uf(unsigned int umem_cnt_p_h_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_srv_h_uf(unsigned int umem_cnt_srv_h_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_p_h_uf(unsigned int umem_sh_cnt_p_h_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_srv_h_uf(unsigned int umem_sh_cnt_srv_h_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stf_p_y_uf(unsigned int umem_cnt_stf_p_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stf_srv_y_uf(unsigned int umem_cnt_stf_srv_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_stf_srv_y_uf(unsigned int umem_sh_cnt_stf_srv_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stl_p_y_uf(unsigned int umem_cnt_stl_p_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stl_srv_y_uf(unsigned int umem_cnt_stl_srv_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_stl_srv_y_uf(unsigned int umem_sh_cnt_stl_srv_y_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stf_p_r_uf(unsigned int umem_cnt_stf_p_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stf_srv_r_uf(unsigned int umem_cnt_stf_srv_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_stf_srv_r_uf(unsigned int umem_sh_cnt_stf_srv_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stl_p_r_uf(unsigned int umem_cnt_stl_p_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_cnt_stl_srv_r_uf(unsigned int umem_cnt_stl_srv_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_mem_sh_cnt_stl_srv_r_uf(unsigned int umem_sh_cnt_stl_srv_r_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_glb_cnt_uf(unsigned int uglb_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg3_cnt_uf(unsigned int upg3_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg2_cnt_uf(unsigned int upg2_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg1_cnt_uf(unsigned int upg1_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_glb_sh_cnt_uf(unsigned int uglb_sh_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg3_sh_cnt_uf(unsigned int upg3_sh_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg2_sh_cnt_uf(unsigned int upg2_sh_cnt_uf); +int iSetPRM_TX_CNT_UNDER_FLAG_pg1_sh_cnt_uf(unsigned int upg1_sh_cnt_uf); +int iSetPRM_TX_FIFO_TH_CFG0_stffq1_daloc_n_af_th(unsigned int ustffq1_daloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG0_stffq1_aloc_n_af_th(unsigned int ustffq1_aloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG0_stffq0_daloc_n_af_th(unsigned int ustffq0_daloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG0_stffq0_aloc_n_af_th(unsigned int ustffq0_aloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG0_stlfq_daloc_n_af_th(unsigned int ustlfq_daloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG0_stlfq_aloc_n_af_th(unsigned int ustlfq_aloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG1_stfiq_n_af_th(unsigned int ustfiq_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG1_stliq_n_af_th(unsigned int ustliq_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG1_oq_daloc_n_af_th(unsigned int uoq_daloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG1_oq_aloc_n_af_th(unsigned int uoq_aloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG2_cpb_aloc_n_af_th(unsigned int ucpb_aloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG2_cpb_daloc_n_af_th(unsigned int ucpb_daloc_n_af_th); +int iSetPRM_TX_FIFO_TH_CFG2_cpi_aloc_n_af_th(unsigned int ucpi_aloc_n_af_th); +int iSetPRM_TX_CPB_ALOC_bmh_cpb_aloc_cnt_wr(unsigned int ubmh_cpb_aloc_cnt_wr); +int iSetPRM_TX_CPB_ALOC_CNT_bmh_cpb_aloc_cnt_num(unsigned int ubmh_cpb_aloc_cnt_num); +int iSetPRM_TX_OQ_ALOC_bmh_oq_aloc_cnt_wr(unsigned int ubmh_oq_aloc_cnt_wr); +int iSetPRM_TX_OQ_ALOC_CNT_bmh_oq_aloc_cnt_num(unsigned int ubmh_oq_aloc_cnt_num); +int iSetPRM_TX_DOUBLE_DALOC_WGT_stf_stl_daloc_pg3_wgt_cfg(unsigned int ustf_stl_daloc_pg3_wgt_cfg); +int iSetPRM_TX_DOUBLE_DALOC_WGT_stf_stl_daloc_pg2_wgt_cfg(unsigned int ustf_stl_daloc_pg2_wgt_cfg); +int iSetPRM_TX_ERR_SRC_cos_uder_src_err(unsigned int ucos_uder_src_err); +int iSetPRM_TX_ERR_SRC_cos_over_src_err(unsigned int ucos_over_src_err); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_cpb_aloc_bdmonitor_en(unsigned int ucsr_prmtx_cpb_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_cpi_aloc_bdmonitor_en(unsigned int ucsr_prmtx_cpi_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_oq_aloc_bdmonitor_en(unsigned int ucsr_prmtx_oq_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_cpb_daloc_bdmonitor_en(unsigned int ucsr_prmtx_cpb_daloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_cpb_drop_bdmonitor_en(unsigned int ucsr_prmtx_cpb_drop_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stliq_bdmonitor_en(unsigned int ucsr_prmtx_stliq_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stfiq_bdmonitor_en(unsigned int ucsr_prmtx_stfiq_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stlfq_aloc_bdmonitor_en(unsigned int ucsr_prmtx_stlfq_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stffq0_aloc_bdmonitor_en(unsigned int ucsr_prmtx_stffq0_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stffq1_aloc_bdmonitor_en(unsigned int ucsr_prmtx_stffq1_aloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stlfq_daloc_bdmonitor_en(unsigned int ucsr_prmtx_stlfq_daloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stffq0_daloc_bdmonitor_en(unsigned int ucsr_prmtx_stffq0_daloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_stffq1_daloc_bdmonitor_en(unsigned int ucsr_prmtx_stffq1_daloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_EN_csr_prmtx_oq_daloc_bdmonitor_en(unsigned int ucsr_prmtx_oq_daloc_bdmonitor_en); +int iSetPRMTX_BW_MONITOR_WIN_LEN_csr_prmtx_bdmonitro_win_len(unsigned int ucsr_prmtx_bdmonitro_win_len); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_CPB_ALOC_csr_prmtx_bdmonitro_max_times_cpb_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_cpb_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_CPI_ALOC_csr_prmtx_bdmonitro_max_times_cpi_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_cpi_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_OQ_ALOC_csr_prmtx_bdmonitro_max_times_oq_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_oq_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_CPB_DALOC_csr_prmtx_bdmonitro_max_times_cpb_daloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_cpb_daloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_CPB_DROP_csr_prmtx_bdmonitro_max_times_cpb_drop( + unsigned int ucsr_prmtx_bdmonitro_max_times_cpb_drop); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STLIQ_csr_prmtx_bdmonitro_max_times_stliq( + unsigned int ucsr_prmtx_bdmonitro_max_times_stliq); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STFIQ_csr_prmtx_bdmonitro_max_times_stfiq( + unsigned int ucsr_prmtx_bdmonitro_max_times_stfiq); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STLFQ_ALOC_csr_prmtx_bdmonitro_max_times_stlfq_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stlfq_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STFFQ0_ALOC_csr_prmtx_bdmonitro_max_times_stffq0_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stffq0_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STFFQ1_ALOC_csr_prmtx_bdmonitro_max_times_stffq1_aloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stffq1_aloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STLFQ_DALOC_csr_prmtx_bdmonitro_max_times_stlfq_daloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stlfq_daloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STFFQ0_DALOC_csr_prmtx_bdmonitro_max_times_stffq0_daloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stffq0_daloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_STFFQ1_DALOC_csr_prmtx_bdmonitro_max_times_stffq1_daloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_stffq1_daloc); +int iSetPRMTX_BW_MONITOR_MAX_TIMES_OQ_DALOC_csr_prmtx_bdmonitro_max_times_oq_daloc( + unsigned int ucsr_prmtx_bdmonitro_max_times_oq_daloc); +int iSetPRMTX_BW_MONITOR_WIN_CNT_prmtx_csr_bdmonitor_win_cnt(unsigned int uprmtx_csr_bdmonitor_win_cnt); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_ALOC_prmtx_csr_bdmonitor_over_max_cnt_cpb_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_cpb_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPI_ALOC_prmtx_csr_bdmonitor_over_max_cnt_cpi_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_cpi_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_ALOC_prmtx_csr_bdmonitor_over_max_cnt_oq_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_oq_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DALOC_prmtx_csr_bdmonitor_over_max_cnt_cpb_daloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_cpb_daloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DROP_prmtx_csr_bdmonitor_over_max_cnt_cpb_drop( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_cpb_drop); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLIQ_prmtx_csr_bdmonitor_over_max_cnt_stliq( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stliq); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFIQ_prmtx_csr_bdmonitor_over_max_cnt_stfiq( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stfiq); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_ALOC_prmtx_csr_bdmonitor_over_max_cnt_stlfq_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stlfq_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_ALOC_prmtx_csr_bdmonitor_over_max_cnt_stffq0_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stffq0_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_ALOC_prmtx_csr_bdmonitor_over_max_cnt_stffq1_aloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stffq1_aloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_DALOC_prmtx_csr_bdmonitor_over_max_cnt_stlfq_daloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stlfq_daloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_DALOC_prmtx_csr_bdmonitor_over_max_cnt_stffq0_daloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stffq0_daloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_DALOC_prmtx_csr_bdmonitor_over_max_cnt_stffq1_daloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_stffq1_daloc); +int iSetPRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_DALOC_prmtx_csr_bdmonitor_over_max_cnt_oq_daloc( + unsigned int uprmtx_csr_bdmonitor_over_max_cnt_oq_daloc); + +/* Define the union csr_prm_fifo_af_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_sfifo_oq_orep_af_th : 6; /* [5:0] */ + u32 csr_prm_sfifo_oq_prls_af_th : 6; /* [11:6] */ + u32 csr_prm_sfifo_cpb_prls_af_th : 8; /* [19:12] */ + u32 rsv_0 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_af_cfg0_u; + +/* Define the union csr_prm_fifo_ae_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_sfifo_oq_orep_ae_th : 6; /* [5:0] */ + u32 csr_prm_sfifo_oq_prls_ae_th : 6; /* [11:6] */ + u32 csr_prm_sfifo_cpb_prls_ae_th : 8; /* [19:12] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_ae_cfg0_u; + +/* Define the union csr_prm_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_indrect_ctrl : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_indrect_ctrl_u; + +/* Define the union csr_prm_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_indrect_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_indrect_timeout_u; + +/* Define the union csr_prm_bw_monitor_en_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_oq_orep_bdmonitor_en : 1; /* [0] */ + u32 csr_prm_oq_prls_bdmonitor_en : 1; /* [1] */ + u32 csr_prm_cpb_prls_bdmonitor_en : 1; /* [2] */ + u32 rsv_2 : 29; /* [31:3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_en_u; + +/* Define the union csr_prm_bw_monitor_win_len_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_bdmonitro_win_len : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_win_len_u; + +/* Define the union csr_prm_bw_monitor_max_times_oq_orep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_bdmonitro_max_times_oq_orep : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_max_times_oq_orep_u; + +/* Define the union csr_prm_bw_monitor_max_times_oq_prls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_bdmonitro_max_times_oq_prls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_max_times_oq_prls_u; + +/* Define the union csr_prm_bw_monitor_max_times_cpb_prls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_bdmonitro_max_times_cpb_prls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_max_times_cpb_prls_u; + +/* Define the union csr_prm_indrect_dat0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 csr_prm_indrect_data0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_indrect_dat0_u; + +/* Define the union csr_prm_fifo_fill0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_orep_fifo_fill : 6; /* [5:0] */ + u32 oq_prls_fifo_fill : 6; /* [11:6] */ + u32 cpb_prls_fifo_fill : 8; /* [19:12] */ + u32 rsv_3 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_fifo_fill0_u; + +/* Define the union csr_oq_prm_orep_rep_pck_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_prm_orep_rep_pck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_prm_orep_rep_pck_u; + +/* Define the union csr_oq_prm_orep_lrep_pck_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_prm_orep_lrep_pck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_prm_orep_lrep_pck_u; + +/* Define the union csr_oq_prm_prls_pck_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 oq_prm_prls_pck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_oq_prm_prls_pck_u; + +/* Define the union csr_cpb_prm_prls_pck_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpb_prm_prls_pck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cpb_prm_prls_pck_u; + +/* Define the union csr_prm_oq_mdp_pck_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_oq_mdp_pck : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_oq_mdp_pck_u; + +/* Define the union csr_prm_bw_monitor_win_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_csr_bdmonitor_win_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_win_cnt_u; + +/* Define the union csr_prm_bw_monitor_over_max_times_cnt_oq_orep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_csr_bdmonitor_over_max_cnt_oq_orep : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_over_max_times_cnt_oq_orep_u; + +/* Define the union csr_prm_bw_monitor_over_max_times_cnt_oq_prls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_csr_bdmonitor_over_max_cnt_oq_prls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_over_max_times_cnt_oq_prls_u; + +/* Define the union csr_prm_bw_monitor_over_max_times_cnt_cpb_prls_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 prm_csr_bdmonitor_over_max_cnt_cpb_prls : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_prm_bw_monitor_over_max_times_cnt_cpb_prls_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_prm_fifo_af_cfg0_u prm_fifo_af_cfg0; /* 0 */ + volatile csr_prm_fifo_ae_cfg0_u prm_fifo_ae_cfg0; /* 4 */ + volatile csr_prm_indrect_ctrl_u prm_indrect_ctrl; /* 8 */ + volatile csr_prm_indrect_timeout_u prm_indrect_timeout; /* C */ + volatile csr_prm_bw_monitor_en_u prm_bw_monitor_en; /* 10 */ + volatile csr_prm_bw_monitor_win_len_u prm_bw_monitor_win_len; /* 14 */ + volatile csr_prm_bw_monitor_max_times_oq_orep_u prm_bw_monitor_max_times_oq_orep; /* 18 */ + volatile csr_prm_bw_monitor_max_times_oq_prls_u prm_bw_monitor_max_times_oq_prls; /* 1C */ + volatile csr_prm_bw_monitor_max_times_cpb_prls_u prm_bw_monitor_max_times_cpb_prls; /* 20 */ + volatile csr_prm_indrect_dat0_u prm_indrect_dat0; /* 24 */ + volatile csr_prm_fifo_fill0_u prm_fifo_fill0; /* 28 */ + volatile csr_oq_prm_orep_rep_pck_u oq_prm_orep_rep_pck; /* 2C */ + volatile csr_oq_prm_orep_lrep_pck_u oq_prm_orep_lrep_pck; /* 30 */ + volatile csr_oq_prm_prls_pck_u oq_prm_prls_pck; /* 34 */ + volatile csr_cpb_prm_prls_pck_u cpb_prm_prls_pck; /* 38 */ + volatile csr_prm_oq_mdp_pck_u prm_oq_mdp_pck; /* 3C */ + volatile csr_prm_bw_monitor_win_cnt_u prm_bw_monitor_win_cnt; /* 40 */ + volatile csr_prm_bw_monitor_over_max_times_cnt_oq_orep_u prm_bw_monitor_over_max_times_cnt_oq_orep; /* 44 */ + volatile csr_prm_bw_monitor_over_max_times_cnt_oq_prls_u prm_bw_monitor_over_max_times_cnt_oq_prls; /* 48 */ + volatile csr_prm_bw_monitor_over_max_times_cnt_cpb_prls_u prm_bw_monitor_over_max_times_cnt_cpb_prls; /* 4C */ +} S_qu_prm_pd_proc_csr_REGS_TYPE; + +/* Declare the struct pointor of the module qu_prm_pd_proc_csr */ +extern volatile S_qu_prm_pd_proc_csr_REGS_TYPE *gopqu_prm_pd_proc_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetPRM_FIFO_AF_CFG0_csr_prm_sfifo_oq_orep_af_th(unsigned int ucsr_prm_sfifo_oq_orep_af_th); +int iSetPRM_FIFO_AF_CFG0_csr_prm_sfifo_oq_prls_af_th(unsigned int ucsr_prm_sfifo_oq_prls_af_th); +int iSetPRM_FIFO_AF_CFG0_csr_prm_sfifo_cpb_prls_af_th(unsigned int ucsr_prm_sfifo_cpb_prls_af_th); +int iSetPRM_FIFO_AE_CFG0_csr_prm_sfifo_oq_orep_ae_th(unsigned int ucsr_prm_sfifo_oq_orep_ae_th); +int iSetPRM_FIFO_AE_CFG0_csr_prm_sfifo_oq_prls_ae_th(unsigned int ucsr_prm_sfifo_oq_prls_ae_th); +int iSetPRM_FIFO_AE_CFG0_csr_prm_sfifo_cpb_prls_ae_th(unsigned int ucsr_prm_sfifo_cpb_prls_ae_th); +int iSetPRM_INDRECT_CTRL_csr_prm_indrect_ctrl(unsigned int ucsr_prm_indrect_ctrl); +int iSetPRM_INDRECT_TIMEOUT_csr_prm_indrect_timeout(unsigned int ucsr_prm_indrect_timeout); +int iSetPRM_BW_MONITOR_EN_csr_prm_oq_orep_bdmonitor_en(unsigned int ucsr_prm_oq_orep_bdmonitor_en); +int iSetPRM_BW_MONITOR_EN_csr_prm_oq_prls_bdmonitor_en(unsigned int ucsr_prm_oq_prls_bdmonitor_en); +int iSetPRM_BW_MONITOR_EN_csr_prm_cpb_prls_bdmonitor_en(unsigned int ucsr_prm_cpb_prls_bdmonitor_en); +int iSetPRM_BW_MONITOR_WIN_LEN_csr_prm_bdmonitro_win_len(unsigned int ucsr_prm_bdmonitro_win_len); +int iSetPRM_BW_MONITOR_MAX_TIMES_OQ_OREP_csr_prm_bdmonitro_max_times_oq_orep( + unsigned int ucsr_prm_bdmonitro_max_times_oq_orep); +int iSetPRM_BW_MONITOR_MAX_TIMES_OQ_PRLS_csr_prm_bdmonitro_max_times_oq_prls( + unsigned int ucsr_prm_bdmonitro_max_times_oq_prls); +int iSetPRM_BW_MONITOR_MAX_TIMES_CPB_PRLS_csr_prm_bdmonitro_max_times_cpb_prls( + unsigned int ucsr_prm_bdmonitro_max_times_cpb_prls); +int iSetPRM_INDRECT_DAT0_csr_prm_indrect_data0(unsigned int ucsr_prm_indrect_data0); +int iSetPRM_FIFO_FILL0_oq_orep_fifo_fill(unsigned int uoq_orep_fifo_fill); +int iSetPRM_FIFO_FILL0_oq_prls_fifo_fill(unsigned int uoq_prls_fifo_fill); +int iSetPRM_FIFO_FILL0_cpb_prls_fifo_fill(unsigned int ucpb_prls_fifo_fill); +int iSetOQ_PRM_OREP_REP_PCK_oq_prm_orep_rep_pck(unsigned int uoq_prm_orep_rep_pck); +int iSetOQ_PRM_OREP_LREP_PCK_oq_prm_orep_lrep_pck(unsigned int uoq_prm_orep_lrep_pck); +int iSetOQ_PRM_PRLS_PCK_oq_prm_prls_pck(unsigned int uoq_prm_prls_pck); +int iSetCPB_PRM_PRLS_PCK_cpb_prm_prls_pck(unsigned int ucpb_prm_prls_pck); +int iSetPRM_OQ_MDP_PCK_prm_oq_mdp_pck(unsigned int uprm_oq_mdp_pck); +int iSetPRM_BW_MONITOR_WIN_CNT_prm_csr_bdmonitor_win_cnt(unsigned int uprm_csr_bdmonitor_win_cnt); +int iSetPRM_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_OREP_prm_csr_bdmonitor_over_max_cnt_oq_orep( + unsigned int uprm_csr_bdmonitor_over_max_cnt_oq_orep); +int iSetPRM_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_PRLS_prm_csr_bdmonitor_over_max_cnt_oq_prls( + unsigned int uprm_csr_bdmonitor_over_max_cnt_oq_prls); +int iSetPRM_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_PRLS_prm_csr_bdmonitor_over_max_cnt_cpb_prls( + unsigned int uprm_csr_bdmonitor_over_max_cnt_cpb_prls); + + +#endif // PRMTX_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_reg_offset.h new file mode 100644 index 000000000..e8174b730 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/prmtx_reg_offset.h @@ -0,0 +1,264 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : prmtx_reg_offset.h +// Project line : Platform And Key Technologies Development +// Department : CAD Development Department +// Author : xxx +// Version : 1.0 +// Date : 2020/3/24 +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/03/24 22:01:17 Create file +// ****************************************************************************** + +#ifndef PRMTX_REG_OFFSET_H +#define PRMTX_REG_OFFSET_H + +/* QU_PRM_TX_CSR Base address of Module's Register */ +#define CSR_QU_PRM_TX_CSR_BASE (0x6800) + +/* **************************************************************************** */ +/* QU_PRM_TX_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_CTRL_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x0) /* PRM memory indirect access ctrl register */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_TIMEOUT_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x4) /* PRM indirect access timeout configuration */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT0_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x8) /* PRM indirect access write or read data. */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT1_REG (CSR_QU_PRM_TX_CSR_BASE + 0xC) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x10) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT3_REG (CSR_QU_PRM_TX_CSR_BASE + 0x14) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT4_REG (CSR_QU_PRM_TX_CSR_BASE + 0x18) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT5_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1C) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_INDRECT_DAT6_REG (CSR_QU_PRM_TX_CSR_BASE + 0x20) /* 间接访问数据 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CSR_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x30) /* 软件申请配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_FC_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x34) /* 黄区STF阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_FC_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x38) /* 黄区STL阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_FC_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x3C) /* 红区STF阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_FC_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x40) /* 红区STL阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x44) /* 黄区STF RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x48) /* 黄区STL RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x4C) /* 红区STF RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x50) /* 红区STL RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x54) /* 黄区STF 资源CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x58) /* 黄区STL 资源CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x5C) /* 红区STF 资源CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x60) /* 红区STL 资源CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_SH_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x64) /* 黄区STF 资源SH_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_SH_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x68) /* 黄区STL 资源SH_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_SH_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x6C) /* 红区STF 资源SH_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_SH_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x70) /* 红区STL 资源SH_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_MON_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x74) /* 黄区monitor配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_HIS_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x78) /* 黄区最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_MON_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x7C) /* 红区monitor配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_HIS_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x80) /* 红区最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLFQ_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x84) /* STLFQ ALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ0_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x88) /* STFFQ0 ALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ1_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x8C) /* STFFQ1 ALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLFQ_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x90) /* STLFQ DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ0_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x94) /* STFFQ0 DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ1_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x98) /* STFFQ1 DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x9C) /* CPB DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_DROP_REG (CSR_QU_PRM_TX_CSR_BASE + 0xA0) /* CPB DROP 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_OQ_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0xA4) /* OQ DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLFQ_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xA8) /* STLFQ ALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ0_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xAC) /* STFFQ0 ALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ1_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xB0) /* STFFQ1 ALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLFQ_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xB4) /* STLFQ DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ0_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xB8) /* STFFQ0 DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFFQ1_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xBC) /* STFFQ1 DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xC0) /* CPB DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_DROP_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xC4) /* CPB DROP CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_OQ_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xC8) /* OQ DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_P_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xCC) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_P_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xD0) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_SRV_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xD4) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_SRV_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xD8) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xDC) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xE0) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_ST_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xE4) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_ST_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xE8) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STF_ST_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xEC) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_R_STL_ST_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0xF0) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFIQ_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0xF4) /* STFIQ ALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLIQ_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0xF8) /* STLIQ ALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_YDA_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0xFC) /* YDA DALOC 次数 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STFIQ_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x100) /* STFIQ ALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_STLIQ_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x104) /* STLIQ ALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_YDA_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x108) /* YDA DALOC CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_P_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x10C) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_P_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x110) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_ST_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x114) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_ST_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x118) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STF_ST_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x11C) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_Y_STL_ST_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x120) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_G_MON_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x124) /* 绿区monitor配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_G_HIS_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x128) /* 绿区最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPI_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x12C) /* PRM_TX_CPI_ALOC */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GRQ_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x130) /* PRM_TX_GRQ_ALOC */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GRQ_DALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x134) /* PRM_TX_GRQ_DALOC */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPI_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x138) /* PRM_TX_CPI_ALOC_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GRQ_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x13C) /* PRM_TX_GRQ_ALOC_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GRQ_DALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x140) /* PRM_TX_GRQ_DALOC_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_H_COS_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x144) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_H_P_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x148) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_H_P_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x14C) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_H_SRV_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x150) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_H_SRV_SH_HIS_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x154) /* 最大值记录 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x158) /* GLB RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_FC_TH_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x15C) /* GLB阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_FC_TH_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x160) /* GLB阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_FC_TH_CFG2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x164) /* GLB阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_DRP_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x168) /* GLB阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x16C) /* PG0 RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_FC_TH_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x170) /* PG1阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_FC_TH_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x174) /* PG1阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_FC_TH_CFG2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x178) /* PG1阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_DRP_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x17C) /* PG1阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x180) /* PG2 RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_FC_TH_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x184) /* PG2阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_FC_TH_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x188) /* PG2阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_FC_TH_CFG2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x18C) /* PG2阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_DRP_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x190) /* PG2阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_RSVD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x194) /* PG3 RSVD配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_FC_TH_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x198) /* PG3阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_FC_TH_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x19C) /* PG3阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_FC_TH_CFG2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1A0) /* PG3阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_DRP_TH_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1A4) /* PG3阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG1_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1A8) /* PG1资源统计 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG2_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1AC) /* PG2黄区资源统计 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_PG3_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1B0) /* PG3红区资源统计 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1B4) /* GLB资源统计 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_GLB_MAX_CNT_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1B8) /* GLB最大阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPI_REQ_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1BC) /* CPI PRE预扣配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_MQM_ULOAD_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1C0) /* PG1轻负载阈值配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_BMH_WRR_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1C4) /* TX绿区WRR权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_BMY_WRR_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1C8) /* TX黄区WRR权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_BMR_WRR_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1CC) /* TX红区WRR权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_BMR_WRR_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1D0) /* TX红区WRR权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_BMG_WRR_CFG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1D4) /* TX GLB 区WRR权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CNT_OVER_FLAG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1D8) /* CNT上溢出标志 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CNT_UNDER_FLAG_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1DC) /* CNT下溢出标志 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_FIFO_TH_CFG0_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1E0) /* TX fifo阈值配置0 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_FIFO_TH_CFG1_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1E4) /* TX fifo阈值配置1 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_FIFO_TH_CFG2_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1E8) /* TX fifo阈值配置2 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1EC) /* PRM_TX_CPB_ALOC */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_CPB_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1F0) /* PRM_TX_CPB_ALOC_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_OQ_ALOC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1F4) /* PRM_TX_OQ_ALOC */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_OQ_ALOC_CNT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1F8) /* PRM_TX_OQ_ALOC_CNT */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_DOUBLE_DALOC_WGT_REG (CSR_QU_PRM_TX_CSR_BASE + 0x1FC) /* TX双黄/红区释放权重配置 */ +#define CSR_QU_PRM_TX_CSR_PRM_TX_ERR_SRC_REG (CSR_QU_PRM_TX_CSR_BASE + 0x200) /* TX溢出DFX */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_EN_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x234) /* PRMTX侧的入口FIFO带宽监测使能配置 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_WIN_LEN_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x238) /* PRMTX侧的入口FIFO带宽监测，窗口长度配置 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_CPB_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x23C) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_CPI_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x240) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_OQ_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x244) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_CPB_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x248) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_CPB_DROP_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x24C) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STLIQ_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x250) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STFIQ_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x254) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STLFQ_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x258) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STFFQ0_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x25C) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STFFQ1_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x260) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STLFQ_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x264) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STFFQ0_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x268) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_STFFQ1_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x26C) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_MAX_TIMES_OQ_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x270) /* PRMTX侧的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_WIN_CNT_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x274) /* PRMTX侧的入口FIFO带宽监测，窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x278) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPI_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x27C) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x280) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x284) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_DROP_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x288) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLIQ_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x28C) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFIQ_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x290) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x294) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x298) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_ALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x29C) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STLFQ_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x2A0) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ0_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x2A4) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_STFFQ1_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x2A8) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_TX_CSR_PRMTX_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_DALOC_REG \ + (CSR_QU_PRM_TX_CSR_BASE + 0x2AC) /* PRMTX侧的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ + +/* QU_PRM_PD_PROC_CSR Base address of Module's Register */ +#define CSR_QU_PRM_PD_PROC_CSR_BASE (0x7800) + +/* **************************************************************************** */ +/* QU_PRM_PD_PROC_CSR Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_QU_PRM_PD_PROC_CSR_PRM_FIFO_AF_CFG0_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x0) /* 复制流程模块FIFO的almost-full水线配置 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_FIFO_AE_CFG0_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x4) /* 复制流程模块FIFO的almost-empty水线配置 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_INDRECT_CTRL_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x8) /* PRM复制流程模块间接寻址控制寄存器 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_INDRECT_TIMEOUT_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0xC) /* PRM间接寻址Timeout水线配置 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_EN_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x10) /* PRM的入口FIFO带宽监测使能配置 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_WIN_LEN_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x14) /* PRM的入口FIFO带宽监测，窗口长度配置 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_MAX_TIMES_OQ_OREP_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x18) /* PRM的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_MAX_TIMES_OQ_PRLS_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x1C) /* PRM的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_MAX_TIMES_CPB_PRLS_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x20) /* PRM的入口FIFO带宽监测，单个窗口内允许的最大写FIFO次数。 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_INDRECT_DAT0_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x24) /* PRM memory indirect access write data or read data. */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_FIFO_FILL0_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x28) /* 复制流程模块的FIFO内数据个数 */ +#define CSR_QU_PRM_PD_PROC_CSR_OQ_PRM_OREP_REP_PCK_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x2C) /* PRM通过orep接口收到OQ的复制报文指令（不包含lrep指令）计数统计 */ +#define CSR_QU_PRM_PD_PROC_CSR_OQ_PRM_OREP_LREP_PCK_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x30) /* PRM通过orep接口收到OQ的lrep指令计数统计 */ +#define CSR_QU_PRM_PD_PROC_CSR_OQ_PRM_PRLS_PCK_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x34) /* PRM收到OQ的prls指令计数统计 */ +#define CSR_QU_PRM_PD_PROC_CSR_CPB_PRM_PRLS_PCK_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x38) /* PRM收到CPB的prls指令计数统计 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_OQ_MDP_PCK_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x3C) /* PRM通过MDP接口向OQ丢弃报文个数计数统计 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_WIN_CNT_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x40) /* PRM的入口FIFO带宽监测，窗口个数计数器 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_OREP_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x44) /* PRM的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_OVER_MAX_TIMES_CNT_OQ_PRLS_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x48) /* PRM的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ +#define CSR_QU_PRM_PD_PROC_CSR_PRM_BW_MONITOR_OVER_MAX_TIMES_CNT_CPB_PRLS_REG \ + (CSR_QU_PRM_PD_PROC_CSR_BASE + 0x4C) /* PRM的入口FIFO带宽监测，超过FIFO写上限的窗口个数计数器 */ + +#endif // PRMTX_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_c_union_define.h new file mode 100644 index 000000000..32b33ef0e --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_c_union_define.h @@ -0,0 +1,314 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : ring_cnb_c_union_define.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : xxx +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/10/23 11:46:44 Create file +// ****************************************************************************** + +#ifndef RING_CNB_C_UNION_DEFINE_H +#define RING_CNB_C_UNION_DEFINE_H + +/* Define the union csr_cnb_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_version_u; + +/* Define the union csr_cnb_tmout_cnt_thd_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tmout_cnt_thd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_tmout_cnt_thd_u; + +/* Define the union csr_cnb_empty_addr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 26; /* [25:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_empty_addr_u; + +/* Define the union csr_cnb_api_err_flit_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_err_flit_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_err_flit_cnt_u; + +/* Define the union csr_cnb_api_crt_msge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_crt_msge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_crt_msge_cnt_u; + +/* Define the union csr_cnb_api_tx_msge_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_api_tx_msge_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_tx_msge_cnt_u; + +/* Define the union csr_cnb_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_0 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_1 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_vector_u; + +/* Define the union csr_cnb_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_2 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_u; + +/* Define the union csr_cnb_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 6; /* [5:0] */ + u32 rsv_3 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_int_mask_u; + +/* Define the union csr_cnb_api_op_code_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_api_op_code_err_u; + +/* Define the union csr_cnb_csr_cmd_parity_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_cmd_parity_err_u; + +/* Define the union csr_cnb_csr_wr_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_wr_err_u; + +/* Define the union csr_cnb_csr_rddat_parity_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_rddat_parity_err_u; + +/* Define the union csr_cnb_csr_rd_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_csr_rd_err_u; + +/* Define the union csr_cnb_merr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_tmout_cnt_ovf_err : 1; /* [0] */ + u32 cnb_tmout_cnt_ovf_merr : 1; /* [1] */ + u32 cnb_int_parity_err : 1; /* [2] */ + u32 cnb_int_parity_merr : 1; /* [3] */ + u32 cnb_api_e1_err : 1; /* [4] */ + u32 cnb_api_e1_merr : 1; /* [5] */ + u32 cnb_api_e0_err : 1; /* [6] */ + u32 cnb_api_e0_merr : 1; /* [7] */ + u32 cnb_api_token_err : 1; /* [8] */ + u32 cnb_api_token_merr : 1; /* [9] */ + u32 cnb_api_protocol_err : 1; /* [10] */ + u32 cnb_api_protocol_merr : 1; /* [11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_merr_u; + +/* Define the union csr_cnb_merr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnb_tmout_cnt_ovf_err_mask : 1; /* [0] */ + u32 cnb_int_parity_err_mask : 1; /* [1] */ + u32 cnb_api_e1_err_mask : 1; /* [2] */ + u32 cnb_api_e0_err_mask : 1; /* [3] */ + u32 cnb_api_token_err_mask : 1; /* [4] */ + u32 cnb_api_procotol_err_mask : 1; /* [5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cnb_merr_mask_u; + +/* Define the union csr_rs_nd_pe_crdt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sta : 10; /* [9:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rs_nd_pe_crdt_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_cnb_version_u cnb_version; /* 0 */ + volatile csr_cnb_tmout_cnt_thd_u cnb_tmout_cnt_thd; /* 4 */ + volatile csr_cnb_empty_addr_u cnb_empty_addr; /* 8 */ + volatile csr_cnb_api_err_flit_cnt_u cnb_api_err_flit_cnt; /* C */ + volatile csr_cnb_api_crt_msge_cnt_u cnb_api_crt_msge_cnt; /* 10 */ + volatile csr_cnb_api_tx_msge_cnt_u cnb_api_tx_msge_cnt; /* 14 */ + volatile csr_cnb_int_vector_u cnb_int_vector; /* 18 */ + volatile csr_cnb_int_u cnb_int; /* 1C */ + volatile csr_cnb_int_mask_u cnb_int_mask; /* 20 */ + volatile csr_cnb_api_op_code_err_u cnb_api_op_code_err; /* 24 */ + volatile csr_cnb_csr_cmd_parity_err_u cnb_csr_cmd_parity_err; /* 28 */ + volatile csr_cnb_csr_wr_err_u cnb_csr_wr_err; /* 2C */ + volatile csr_cnb_csr_rddat_parity_err_u cnb_csr_rddat_parity_err; /* 30 */ + volatile csr_cnb_csr_rd_err_u cnb_csr_rd_err; /* 34 */ + volatile csr_cnb_merr_u cnb_merr; /* 38 */ + volatile csr_cnb_merr_mask_u cnb_merr_mask; /* 3C */ + volatile csr_rs_nd_pe_crdt_u rs_nd_pe_crdt; /* 40 */ +} S_ring_cnb_csr_REGS_TYPE; + +/* Declare the struct pointor of the module ring_cnb_csr */ +extern volatile S_ring_cnb_csr_REGS_TYPE *gopring_cnb_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetCNB_VERSION_cnb_version(unsigned int ucnb_version); +int iSetCNB_TMOUT_CNT_THD_rp_tmout_cnt_thd(unsigned int urp_tmout_cnt_thd); +int iSetCNB_EMPTY_ADDR_ctp(unsigned int uctp); +int iSetCNB_API_ERR_FLIT_CNT_cnb_api_err_flit_cnt(unsigned int ucnb_api_err_flit_cnt); +int iSetCNB_API_CRT_MSGE_CNT_cnb_api_crt_msge_cnt(unsigned int ucnb_api_crt_msge_cnt); +int iSetCNB_API_TX_MSGE_CNT_cnb_api_tx_msge_cnt(unsigned int ucnb_api_tx_msge_cnt); +int iSetCNB_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetCNB_INT_VECTOR_enable(unsigned int uenable); +int iSetCNB_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetCNB_INT_int_data(unsigned int uint_data); +int iSetCNB_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetCNB_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetCNB_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetCNB_API_OP_CODE_ERR_error_bit(unsigned int uerror_bit); +int iSetCNB_API_OP_CODE_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetCNB_API_OP_CODE_ERR_sticky(unsigned int usticky); +int iSetCNB_CSR_CMD_PARITY_ERR_error_bit(unsigned int uerror_bit); +int iSetCNB_CSR_CMD_PARITY_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetCNB_CSR_CMD_PARITY_ERR_sticky(unsigned int usticky); +int iSetCNB_CSR_WR_ERR_error_bit(unsigned int uerror_bit); +int iSetCNB_CSR_WR_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetCNB_CSR_WR_ERR_sticky(unsigned int usticky); +int iSetCNB_CSR_RDDAT_PARITY_ERR_error_bit(unsigned int uerror_bit); +int iSetCNB_CSR_RDDAT_PARITY_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetCNB_CSR_RDDAT_PARITY_ERR_sticky(unsigned int usticky); +int iSetCNB_CSR_RD_ERR_error_bit(unsigned int uerror_bit); +int iSetCNB_CSR_RD_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetCNB_CSR_RD_ERR_sticky(unsigned int usticky); +int iSetCNB_MERR_cnb_tmout_cnt_ovf_err(unsigned int ucnb_tmout_cnt_ovf_err); +int iSetCNB_MERR_cnb_tmout_cnt_ovf_merr(unsigned int ucnb_tmout_cnt_ovf_merr); +int iSetCNB_MERR_cnb_int_parity_err(unsigned int ucnb_int_parity_err); +int iSetCNB_MERR_cnb_int_parity_merr(unsigned int ucnb_int_parity_merr); +int iSetCNB_MERR_cnb_api_e1_err(unsigned int ucnb_api_e1_err); +int iSetCNB_MERR_cnb_api_e1_merr(unsigned int ucnb_api_e1_merr); +int iSetCNB_MERR_cnb_api_e0_err(unsigned int ucnb_api_e0_err); +int iSetCNB_MERR_cnb_api_e0_merr(unsigned int ucnb_api_e0_merr); +int iSetCNB_MERR_cnb_api_token_err(unsigned int ucnb_api_token_err); +int iSetCNB_MERR_cnb_api_token_merr(unsigned int ucnb_api_token_merr); +int iSetCNB_MERR_cnb_api_protocol_err(unsigned int ucnb_api_protocol_err); +int iSetCNB_MERR_cnb_api_protocol_merr(unsigned int ucnb_api_protocol_merr); +int iSetCNB_MERR_MASK_cnb_tmout_cnt_ovf_err_mask(unsigned int ucnb_tmout_cnt_ovf_err_mask); +int iSetCNB_MERR_MASK_cnb_int_parity_err_mask(unsigned int ucnb_int_parity_err_mask); +int iSetCNB_MERR_MASK_cnb_api_e1_err_mask(unsigned int ucnb_api_e1_err_mask); +int iSetCNB_MERR_MASK_cnb_api_e0_err_mask(unsigned int ucnb_api_e0_err_mask); +int iSetCNB_MERR_MASK_cnb_api_token_err_mask(unsigned int ucnb_api_token_err_mask); +int iSetCNB_MERR_MASK_cnb_api_procotol_err_mask(unsigned int ucnb_api_procotol_err_mask); +int iSetRS_ND_PE_CRDT_sta(unsigned int usta); + + +#endif // RING_CNB_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_reg_offset.h new file mode 100644 index 000000000..82d954785 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/ring_cnb_reg_offset.h @@ -0,0 +1,52 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : ring_cnb_reg_offset.h +// Project line : +// Department : +// Author : xxx +// Version : 1.0 +// Date : +// Description : xxx +// Others : Generated automatically by nManager V5.1 +// History : xxx 2020/10/23 11:46:44 Create file +// ****************************************************************************** + +#ifndef RING_CNB_REG_OFFSET_H +#define RING_CNB_REG_OFFSET_H + +/* ring_cnb_csr Base address of Module's Register */ +#define CSR_RING_CNB_CSR_BASE (0x3F00) + +/* **************************************************************************** */ +/* ring_cnb_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_RING_CNB_CSR_CNB_VERSION_REG (CSR_RING_CNB_CSR_BASE + 0x0) /* Version Log register */ +#define CSR_RING_CNB_CSR_CNB_TMOUT_CNT_THD_REG \ + (CSR_RING_CNB_CSR_BASE + 0x4) /* CNB timeout counter overflow threshold */ +#define CSR_RING_CNB_CSR_CNB_EMPTY_ADDR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x8) /* record the read error or write error API address */ +#define CSR_RING_CNB_CSR_CNB_API_ERR_FLIT_CNT_REG (CSR_RING_CNB_CSR_BASE + 0xC) /* error flit counter */ +#define CSR_RING_CNB_CSR_CNB_API_CRT_MSGE_CNT_REG (CSR_RING_CNB_CSR_BASE + 0x10) /* API correct message counter */ +#define CSR_RING_CNB_CSR_CNB_API_TX_MSGE_CNT_REG \ + (CSR_RING_CNB_CSR_BASE + 0x14) /* message counter for API transmit from CNB */ +#define CSR_RING_CNB_CSR_CNB_INT_VECTOR_REG (CSR_RING_CNB_CSR_BASE + 0x18) /* interrupt vector */ +#define CSR_RING_CNB_CSR_CNB_INT_REG (CSR_RING_CNB_CSR_BASE + 0x1C) /* interrupt data */ +#define CSR_RING_CNB_CSR_CNB_INT_MASK_REG (CSR_RING_CNB_CSR_BASE + 0x20) /* interrupt mask */ +#define CSR_RING_CNB_CSR_CNB_API_OP_CODE_ERR_REG (CSR_RING_CNB_CSR_BASE + 0x24) /* illegal op_code error */ +#define CSR_RING_CNB_CSR_CNB_CSR_CMD_PARITY_ERR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x28) /* parity check error when the command is arrived at its destination CSR */ +#define CSR_RING_CNB_CSR_CNB_CSR_WR_ERR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x2C) /* csr write error: the write address is empty or the data size is mismatch */ +#define CSR_RING_CNB_CSR_CNB_CSR_RDDAT_PARITY_ERR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x30) /* read back data/op_info error: the read back data or op_info has parity error */ +#define CSR_RING_CNB_CSR_CNB_CSR_RD_ERR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x34) /* csr read error: the read address is empty or the data size is mismatch */ +#define CSR_RING_CNB_CSR_CNB_MERR_REG \ + (CSR_RING_CNB_CSR_BASE + 0x38) /* MERR register for CNB error, Please refer to the member comments */ +#define CSR_RING_CNB_CSR_CNB_MERR_MASK_REG \ + (CSR_RING_CNB_CSR_BASE + 0x3C) /* mask control for errors list in CNB_MERR register */ +#define CSR_RING_CNB_CSR_RS_ND_PE_CRDT_REG \ + (CSR_RING_CNB_CSR_BASE + 0x40) /* record the credit cnt for RIGN packet eject port */ + +#endif // RING_CNB_REG_OFFSET_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_c_union_define.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_c_union_define.h new file mode 100644 index 000000000..b6b83a94c --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_c_union_define.h @@ -0,0 +1,6441 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : sm_c_union_define.h +// Project line : IT Product Line +// Department : ICT Processor Chipset Development Department +// Version : V100 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// file +// ****************************************************************************** + +#ifndef SM_C_UNION_DEFINE_H +#define SM_C_UNION_DEFINE_H + +/* Define the union csr_smrt_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smrt_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smrt_version_u; + +/* Define the union csr_smxr_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_chk_en : 1; /* [0] */ + u32 smxr_cnt_sel : 2; /* [2:1] */ + u32 rsv_0 : 2; /* [4:3] */ + u32 tifoe_pi_copy_enb : 1; /* [5] */ + u32 roce_pi_copy_enb : 1; /* [6] */ + u32 iwarp_pi_copy_enb : 1; /* [7] */ + u32 tp_ram_tmod : 8; /* [15:8] */ + u32 mem_ret1n : 1; /* [16] */ + u32 rsv_1 : 1; /* [17] */ + u32 tifoe_pftch_ctl : 2; /* [19:18] */ + u32 tifoe_pftch_wqe_num : 2; /* [21:20] */ + u32 rp_sm_uncrt_err_clr : 1; /* [22] */ + u32 rp_sm_uncrt_err_mask : 7; /* [29:23] */ + u32 rp_crt_err_inj_req : 1; /* [30] */ + u32 rp_uncrt_err_inj_req : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cfg1_u; + +/* Define the union csr_smxr_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_inst_id_mqm : 5; /* [4:0] */ + u32 rp_lb_mqm : 2; /* [6:5] */ + u32 rp_inst_id_qu_ld_wqe : 5; /* [11:7] */ + u32 rp_lb_qu_ld_wqe : 2; /* [13:12] */ + u32 rsv_2 : 1; /* [14] */ + u32 rp_fairness_en : 1; /* [15] */ + u32 rp_fairness_num : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cfg0_u; + +/* Define the union csr_smxt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dis_tx_eg : 1; /* [0] */ + u32 dis_tx_mc : 1; /* [1] */ + u32 dis_tx_eg_tl0 : 1; /* [2] */ + u32 dis_tx_eg_tl1 : 1; /* [3] */ + u32 reg_cap_ch_sel : 2; /* [5:4] */ + u32 cap_start : 1; /* [6] */ + u32 rsv_3 : 25; /* [31:7] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cfg_u; + +/* Define the union csr_smxr_tm_grt01_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tm_grt0 : 13; /* [12:0] */ + u32 rsv_4 : 3; /* [15:13] */ + u32 rp_tm_grt1 : 13; /* [28:16] */ + u32 rsv_5 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_tm_grt01_u; + +/* Define the union csr_smxr_tm_grt23_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_tm_grt2 : 13; /* [12:0] */ + u32 rsv_6 : 3; /* [15:13] */ + u32 rp_tm_grt3 : 13; /* [28:16] */ + u32 rsv_7 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_tm_grt23_u; + +/* Define the union csr_smrt_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_8 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_9 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smrt_int_vector_u; + +/* Define the union csr_smrt_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 3; /* [2:0] */ + u32 rsv_10 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smrt_int_u; + +/* Define the union csr_smrt_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 3; /* [2:0] */ + u32 rsv_11 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smrt_int_mask_u; + +/* Define the union csr_smxr_req_mem_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_req_mem_crt_err_u; + +/* Define the union csr_smxr_req_mem_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_req_mem_uncrt_err_u; + +/* Define the union csr_smxr_miss_sop_eop_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_miss_sop_eop_err_u; + +/* Define the union csr_smxr_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_indir_addr : 24; /* [23:0] */ + u32 smxr_indir_tab : 4; /* [27:24] */ + u32 smxr_indir_stat : 2; /* [29:28] */ + u32 smxr_indir_mode : 1; /* [30] */ + u32 smxr_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_indrect_ctrl_u; + +/* Define the union csr_smxr_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_indrect_timeout_u; + +/* Define the union csr_smxr_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_indrect_data_u; + +/* Define the union csr_smxt_cap_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cap_tag_l_en : 1; /* [0] */ + u32 cap_tag_h_en : 1; /* [1] */ + u32 cap_thd_id_en : 1; /* [2] */ + u32 cap_dnid_en : 1; /* [3] */ + u32 flit0_127_123 : 5; /* [8:4] */ + u32 flit0_127_123_msk : 5; /* [13:9] */ + u32 rsv_12 : 17; /* [30:14] */ + u32 cap_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cap_cfg_u; + +/* Define the union csr_smxt_cap_field_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dst_tag_l : 12; /* [11:0] */ + u32 dst_tag_h : 6; /* [17:12] */ + u32 dst_thd_id : 7; /* [24:18] */ + u32 dst_nd_id : 6; /* [30:25] */ + u32 rsv_13 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cap_field_cfg_u; + +/* Define the union csr_smxt_cnt_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_en_cnt_0 : 9; /* [8:0] */ + u32 rsv_14 : 7; /* [15:9] */ + u32 smxt_en_cnt_1 : 9; /* [24:16] */ + u32 rsv_15 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt_cfg0_u; + +/* Define the union csr_smxt_cnt_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_en_cnt_2 : 9; /* [8:0] */ + u32 rsv_16 : 7; /* [15:9] */ + u32 smxt_en_cnt_3 : 9; /* [24:16] */ + u32 rsv_17 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt_cfg1_u; + +/* Define the union csr_smxt_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt0_u; + +/* Define the union csr_smxt_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt1_u; + +/* Define the union csr_smxt_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt2_u; + +/* Define the union csr_smxt_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxt_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cnt3_u; + +/* Define the union csr_smxt_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tl1_ctp : 5; /* [4:0] */ + u32 tl0_ctp : 5; /* [9:5] */ + u32 ring_resp_ctp : 3; /* [12:10] */ + u32 ring_rqst_ctp : 3; /* [15:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_crdt_cnt_u; + +/* Define the union csr_smxt_fifo_depth0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 if0_tl1_ctp : 4; /* [3:0] */ + u64 if0_tl0_ctp : 4; /* [7:4] */ + u64 if0_ring_resp_ctp : 4; /* [11:8] */ + u64 if0_ring_rqst_ctp : 4; /* [15:12] */ + u64 if1_tl1_ctp : 4; /* [19:16] */ + u64 if1_tl0_ctp : 4; /* [23:20] */ + u64 if1_ring_resp_ctp : 4; /* [27:24] */ + u64 if1_ring_rqst_ctp : 4; /* [31:28] */ + u64 mc_ctp : 3; /* [34:32] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smxt_fifo_depth0_u; + +/* Define the union csr_smxt_fifo_depth1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 if2_tl1_ctp : 4; /* [3:0] */ + u32 if2_tl0_ctp : 4; /* [7:4] */ + u32 if2_ring_resp_ctp : 4; /* [11:8] */ + u32 if2_ring_rqst_ctp : 4; /* [15:12] */ + u32 if3_tl1_ctp : 4; /* [19:16] */ + u32 if3_tl0_ctp : 4; /* [23:20] */ + u32 if3_ring_resp_ctp : 4; /* [27:24] */ + u32 if3_ring_rqst_ctp : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_fifo_depth1_u; + +/* Define the union csr_tl0_q_dep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l0_ctp : 6; /* [5:0] */ + u32 rsv_18 : 2; /* [7:6] */ + u32 l1_ctp : 6; /* [13:8] */ + u32 rsv_19 : 2; /* [15:14] */ + u32 l2_ctp : 6; /* [21:16] */ + u32 rsv_20 : 2; /* [23:22] */ + u32 l3_ctp : 6; /* [29:24] */ + u32 rsv_21 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl0_q_dep_u; + +/* Define the union csr_tl1_q_dep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l0_ctp : 6; /* [5:0] */ + u32 rsv_22 : 2; /* [7:6] */ + u32 l1_ctp : 6; /* [13:8] */ + u32 rsv_23 : 2; /* [15:14] */ + u32 l2_ctp : 6; /* [21:16] */ + u32 rsv_24 : 2; /* [23:22] */ + u32 l3_ctp : 6; /* [29:24] */ + u32 rsv_25 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_tl1_q_dep_u; + +/* Define the union csr_rqst_q_dep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l0_ctp : 4; /* [3:0] */ + u32 l1_ctp : 4; /* [7:4] */ + u32 l2_ctp : 4; /* [11:8] */ + u32 l3_ctp : 4; /* [15:12] */ + u32 rsv_26 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rqst_q_dep_u; + +/* Define the union csr_rsp_q_dep_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 l0_ctp : 4; /* [3:0] */ + u32 l1_ctp : 4; /* [7:4] */ + u32 l2_ctp : 4; /* [11:8] */ + u32 l3_ctp : 4; /* [15:12] */ + u32 l4_ctp : 4; /* [19:16] */ + u32 rsv_27 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsp_q_dep_u; + +/* Define the union csr_rqst_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm0_ctp : 5; /* [4:0] */ + u32 sm1_ctp : 5; /* [9:5] */ + u32 sm2_ctp : 5; /* [14:10] */ + u32 sm3_ctp : 5; /* [19:15] */ + u32 rsv_28 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rqst_crdt_cnt_u; + +/* Define the union csr_resp_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm0_ctp : 5; /* [4:0] */ + u32 sm1_ctp : 8; /* [12:5] */ + u32 sm2_ctp : 5; /* [17:13] */ + u32 sm3_ctp : 5; /* [22:18] */ + u32 smmc_ctp : 5; /* [27:23] */ + u32 rsv_29 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_resp_crdt_cnt_u; + +/* Define the union csr_smxr_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cnt0_u; + +/* Define the union csr_smxr_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cnt1_u; + +/* Define the union csr_smxr_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cnt2_u; + +/* Define the union csr_smxr_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smxr_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cnt3_u; + +/* Define the union csr_smxt_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 api_cap_done : 1; /* [0] */ + u32 rsv_30 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_ctp_u; + +/* Define the union csr_smxr_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_virtio_core_inst_id : 6; /* [5:0] */ + u32 rsv_31 : 2; /* [7:6] */ + u32 rp_virtio_core_en : 1; /* [8] */ + u32 rsv_32 : 23; /* [31:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cfg2_u; + +/* Define the union csr_smxr_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_virtio_csr_crdt_init_val : 5; /* [4:0] */ + u32 rsv_33 : 2; /* [6:5] */ + u32 rp_virtio_csr_crdt_init_en : 1; /* [7] */ + u32 rp_virtio_rqst_crdt_init_val : 4; /* [11:8] */ + u32 rsv_34 : 3; /* [14:12] */ + u32 rp_virtio_rqst_crdt_init_en : 1; /* [15] */ + u32 rp_virtio_resp_crdt_init_val : 8; /* [23:16] */ + u32 rp_virtio_resp_crdt_init_en : 1; /* [24] */ + u32 rsv_35 : 7; /* [31:25] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxr_cfg3_u; + +/* Define the union csr_cfg_mem_ctrl_bus0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mem_ctrl_bus0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mem_ctrl_bus0_u; + +/* Define the union csr_cfg_mem_ctrl_bus1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mem_ctrl_bus1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mem_ctrl_bus1_u; + +/* Define the union csr_cfg_mem_ctrl_bus2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mem_ctrl_bus2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mem_ctrl_bus2_u; + +/* Define the union csr_cfg_mem_ctrl_bus3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mem_ctrl_bus3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mem_ctrl_bus3_u; + +/* Define the union csr_cfg_mem_ctrl_bus4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cfg_mem_ctrl_bus4 : 6; /* [5:0] */ + u32 rsv_36 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_cfg_mem_ctrl_bus4_u; + +/* Define the union csr_smxt_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_fake_vf_info_pos : 2; /* [1:0] */ + u32 rp_fake_vf_info_value : 2; /* [3:2] */ + u32 rp_fake_vf_info_en : 1; /* [4] */ + u32 rsv_37 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smxt_cfg2_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smrt_version_u smrt_version; /* 0 */ + volatile csr_smxr_cfg1_u smxr_cfg1; /* 4 */ + volatile csr_smxr_cfg0_u smxr_cfg0; /* 8 */ + volatile csr_smxt_cfg_u smxt_cfg; /* C */ + volatile csr_smxr_tm_grt01_u smxr_tm_grt01; /* 10 */ + volatile csr_smxr_tm_grt23_u smxr_tm_grt23; /* 14 */ + volatile csr_smrt_int_vector_u smrt_int_vector; /* 18 */ + volatile csr_smrt_int_u smrt_int; /* 1C */ + volatile csr_smrt_int_mask_u smrt_int_mask; /* 20 */ + volatile csr_smxr_req_mem_crt_err_u smxr_req_mem_crt_err; /* 24 */ + volatile csr_smxr_req_mem_uncrt_err_u smxr_req_mem_uncrt_err; /* 28 */ + volatile csr_smxr_miss_sop_eop_err_u smxr_miss_sop_eop_err; /* 2C */ + volatile csr_smxr_indrect_ctrl_u smxr_indrect_ctrl; /* 30 */ + volatile csr_smxr_indrect_timeout_u smxr_indrect_timeout; /* 34 */ + volatile csr_smxr_indrect_data_u smxr_indrect_data; /* 38 */ + volatile csr_smxt_cap_cfg_u smxt_cap_cfg; /* 3C */ + volatile csr_smxt_cap_field_cfg_u smxt_cap_field_cfg; /* 40 */ + volatile csr_smxt_cnt_cfg0_u smxt_cnt_cfg0; /* 44 */ + volatile csr_smxt_cnt_cfg1_u smxt_cnt_cfg1; /* 48 */ + volatile csr_smxt_cnt0_u smxt_cnt0; /* 4C */ + volatile csr_smxt_cnt1_u smxt_cnt1; /* 50 */ + volatile csr_smxt_cnt2_u smxt_cnt2; /* 54 */ + volatile csr_smxt_cnt3_u smxt_cnt3; /* 58 */ + volatile csr_smxt_crdt_cnt_u smxt_crdt_cnt; /* 5C */ + volatile csr_smxt_fifo_depth0_u smxt_fifo_depth0; /* 60 */ + volatile csr_smxt_fifo_depth1_u smxt_fifo_depth1; /* 68 */ + volatile csr_tl0_q_dep_u tl0_q_dep; /* 6C */ + volatile csr_tl1_q_dep_u tl1_q_dep; /* 70 */ + volatile csr_rqst_q_dep_u rqst_q_dep; /* 74 */ + volatile csr_rsp_q_dep_u rsp_q_dep; /* 78 */ + volatile csr_rqst_crdt_cnt_u rqst_crdt_cnt; /* 7C */ + volatile csr_resp_crdt_cnt_u resp_crdt_cnt; /* 80 */ + volatile csr_smxr_cnt0_u smxr_cnt0; /* 84 */ + volatile csr_smxr_cnt1_u smxr_cnt1; /* 88 */ + volatile csr_smxr_cnt2_u smxr_cnt2; /* 8C */ + volatile csr_smxr_cnt3_u smxr_cnt3; /* 90 */ + volatile csr_smxt_ctp_u smxt_ctp; /* 94 */ + volatile csr_smxr_cfg2_u smxr_cfg2; /* 98 */ + volatile csr_smxr_cfg3_u smxr_cfg3; /* 9C */ + volatile csr_cfg_mem_ctrl_bus0_u cfg_mem_ctrl_bus0; /* A0 */ + volatile csr_cfg_mem_ctrl_bus1_u cfg_mem_ctrl_bus1; /* A4 */ + volatile csr_cfg_mem_ctrl_bus2_u cfg_mem_ctrl_bus2; /* A8 */ + volatile csr_cfg_mem_ctrl_bus3_u cfg_mem_ctrl_bus3; /* AC */ + volatile csr_cfg_mem_ctrl_bus4_u cfg_mem_ctrl_bus4; /* B0 */ + volatile csr_smxt_cfg2_u smxt_cfg2; /* B4 */ +} S_smrt_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smrt_csr */ +extern volatile S_smrt_csr_REGS_TYPE *gopsmrt_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMRT_VERSION_smrt_version(unsigned int usmrt_version); +int iSetSMXR_CFG1_mem_chk_en(unsigned int umem_chk_en); +int iSetSMXR_CFG1_smxr_cnt_sel(unsigned int usmxr_cnt_sel); +int iSetSMXR_CFG1_tifoe_pi_copy_enb(unsigned int utifoe_pi_copy_enb); +int iSetSMXR_CFG1_roce_pi_copy_enb(unsigned int uroce_pi_copy_enb); +int iSetSMXR_CFG1_iwarp_pi_copy_enb(unsigned int uiwarp_pi_copy_enb); +int iSetSMXR_CFG1_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMXR_CFG1_mem_ret1n(unsigned int umem_ret1n); +int iSetSMXR_CFG1_tifoe_pftch_ctl(unsigned int utifoe_pftch_ctl); +int iSetSMXR_CFG1_tifoe_pftch_wqe_num(unsigned int utifoe_pftch_wqe_num); +int iSetSMXR_CFG1_rp_sm_uncrt_err_clr(unsigned int urp_sm_uncrt_err_clr); +int iSetSMXR_CFG1_rp_sm_uncrt_err_mask(unsigned int urp_sm_uncrt_err_mask); +int iSetSMXR_CFG1_rp_crt_err_inj_req(unsigned int urp_crt_err_inj_req); +int iSetSMXR_CFG1_rp_uncrt_err_inj_req(unsigned int urp_uncrt_err_inj_req); +int iSetSMXR_CFG0_rp_inst_id_mqm(unsigned int urp_inst_id_mqm); +int iSetSMXR_CFG0_rp_lb_mqm(unsigned int urp_lb_mqm); +int iSetSMXR_CFG0_rp_inst_id_qu_ld_wqe(unsigned int urp_inst_id_qu_ld_wqe); +int iSetSMXR_CFG0_rp_lb_qu_ld_wqe(unsigned int urp_lb_qu_ld_wqe); +int iSetSMXR_CFG0_rp_fairness_en(unsigned int urp_fairness_en); +int iSetSMXR_CFG0_rp_fairness_num(unsigned int urp_fairness_num); +int iSetSMXT_CFG_dis_tx_eg(unsigned int udis_tx_eg); +int iSetSMXT_CFG_dis_tx_mc(unsigned int udis_tx_mc); +int iSetSMXT_CFG_dis_tx_eg_tl0(unsigned int udis_tx_eg_tl0); +int iSetSMXT_CFG_dis_tx_eg_tl1(unsigned int udis_tx_eg_tl1); +int iSetSMXT_CFG_reg_cap_ch_sel(unsigned int ureg_cap_ch_sel); +int iSetSMXT_CFG_cap_start(unsigned int ucap_start); +int iSetSMXR_TM_GRT01_rp_tm_grt0(unsigned int urp_tm_grt0); +int iSetSMXR_TM_GRT01_rp_tm_grt1(unsigned int urp_tm_grt1); +int iSetSMXR_TM_GRT23_rp_tm_grt2(unsigned int urp_tm_grt2); +int iSetSMXR_TM_GRT23_rp_tm_grt3(unsigned int urp_tm_grt3); +int iSetSMRT_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMRT_INT_VECTOR_enable(unsigned int uenable); +int iSetSMRT_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMRT_INT_int_data(unsigned int uint_data); +int iSetSMRT_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMRT_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMRT_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMXR_REQ_MEM_CRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMXR_REQ_MEM_CRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMXR_REQ_MEM_CRT_ERR_sticky(unsigned int usticky); +int iSetSMXR_REQ_MEM_UNCRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMXR_REQ_MEM_UNCRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMXR_REQ_MEM_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMXR_MISS_SOP_EOP_ERR_error_bit(unsigned int uerror_bit); +int iSetSMXR_MISS_SOP_EOP_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMXR_MISS_SOP_EOP_ERR_sticky(unsigned int usticky); +int iSetSMXR_INDRECT_CTRL_smxr_indir_addr(unsigned int usmxr_indir_addr); +int iSetSMXR_INDRECT_CTRL_smxr_indir_tab(unsigned int usmxr_indir_tab); +int iSetSMXR_INDRECT_CTRL_smxr_indir_stat(unsigned int usmxr_indir_stat); +int iSetSMXR_INDRECT_CTRL_smxr_indir_mode(unsigned int usmxr_indir_mode); +int iSetSMXR_INDRECT_CTRL_smxr_indir_vld(unsigned int usmxr_indir_vld); +int iSetSMXR_INDRECT_TIMEOUT_smxr_indir_timeout(unsigned int usmxr_indir_timeout); +int iSetSMXR_INDRECT_DATA_smxr_indir_data(unsigned int usmxr_indir_data); +int iSetSMXT_CAP_CFG_cap_tag_l_en(unsigned int ucap_tag_l_en); +int iSetSMXT_CAP_CFG_cap_tag_h_en(unsigned int ucap_tag_h_en); +int iSetSMXT_CAP_CFG_cap_thd_id_en(unsigned int ucap_thd_id_en); +int iSetSMXT_CAP_CFG_cap_dnid_en(unsigned int ucap_dnid_en); +int iSetSMXT_CAP_CFG_flit0_127_123(unsigned int uflit0_127_123); +int iSetSMXT_CAP_CFG_flit0_127_123_msk(unsigned int uflit0_127_123_msk); +int iSetSMXT_CAP_CFG_cap_mode(unsigned int ucap_mode); +int iSetSMXT_CAP_FIELD_CFG_dst_tag_l(unsigned int udst_tag_l); +int iSetSMXT_CAP_FIELD_CFG_dst_tag_h(unsigned int udst_tag_h); +int iSetSMXT_CAP_FIELD_CFG_dst_thd_id(unsigned int udst_thd_id); +int iSetSMXT_CAP_FIELD_CFG_dst_nd_id(unsigned int udst_nd_id); +int iSetSMXT_CNT_CFG0_smxt_en_cnt_0(unsigned int usmxt_en_cnt_0); +int iSetSMXT_CNT_CFG0_smxt_en_cnt_1(unsigned int usmxt_en_cnt_1); +int iSetSMXT_CNT_CFG1_smxt_en_cnt_2(unsigned int usmxt_en_cnt_2); +int iSetSMXT_CNT_CFG1_smxt_en_cnt_3(unsigned int usmxt_en_cnt_3); +int iSetSMXT_CNT0_smxt_cnt0(unsigned int usmxt_cnt0); +int iSetSMXT_CNT1_smxt_cnt1(unsigned int usmxt_cnt1); +int iSetSMXT_CNT2_smxt_cnt2(unsigned int usmxt_cnt2); +int iSetSMXT_CNT3_smxt_cnt3(unsigned int usmxt_cnt3); +int iSetSMXT_CRDT_CNT_tl1_ctp(unsigned int utl1_ctp); +int iSetSMXT_CRDT_CNT_tl0_ctp(unsigned int utl0_ctp); +int iSetSMXT_CRDT_CNT_ring_resp_ctp(unsigned int uring_resp_ctp); +int iSetSMXT_CRDT_CNT_ring_rqst_ctp(unsigned int uring_rqst_ctp); +int iSetSMXT_FIFO_DEPTH0_if0_tl1_ctp(unsigned int uif0_tl1_ctp); +int iSetSMXT_FIFO_DEPTH0_if0_tl0_ctp(unsigned int uif0_tl0_ctp); +int iSetSMXT_FIFO_DEPTH0_if0_ring_resp_ctp(unsigned int uif0_ring_resp_ctp); +int iSetSMXT_FIFO_DEPTH0_if0_ring_rqst_ctp(unsigned int uif0_ring_rqst_ctp); +int iSetSMXT_FIFO_DEPTH0_if1_tl1_ctp(unsigned int uif1_tl1_ctp); +int iSetSMXT_FIFO_DEPTH0_if1_tl0_ctp(unsigned int uif1_tl0_ctp); +int iSetSMXT_FIFO_DEPTH0_if1_ring_resp_ctp(unsigned int uif1_ring_resp_ctp); +int iSetSMXT_FIFO_DEPTH0_if1_ring_rqst_ctp(unsigned int uif1_ring_rqst_ctp); +int iSetSMXT_FIFO_DEPTH0_mc_ctp(unsigned int umc_ctp); +int iSetSMXT_FIFO_DEPTH1_if2_tl1_ctp(unsigned int uif2_tl1_ctp); +int iSetSMXT_FIFO_DEPTH1_if2_tl0_ctp(unsigned int uif2_tl0_ctp); +int iSetSMXT_FIFO_DEPTH1_if2_ring_resp_ctp(unsigned int uif2_ring_resp_ctp); +int iSetSMXT_FIFO_DEPTH1_if2_ring_rqst_ctp(unsigned int uif2_ring_rqst_ctp); +int iSetSMXT_FIFO_DEPTH1_if3_tl1_ctp(unsigned int uif3_tl1_ctp); +int iSetSMXT_FIFO_DEPTH1_if3_tl0_ctp(unsigned int uif3_tl0_ctp); +int iSetSMXT_FIFO_DEPTH1_if3_ring_resp_ctp(unsigned int uif3_ring_resp_ctp); +int iSetSMXT_FIFO_DEPTH1_if3_ring_rqst_ctp(unsigned int uif3_ring_rqst_ctp); +int iSetTL0_Q_DEP_l0_ctp(unsigned int ul0_ctp); +int iSetTL0_Q_DEP_l1_ctp(unsigned int ul1_ctp); +int iSetTL0_Q_DEP_l2_ctp(unsigned int ul2_ctp); +int iSetTL0_Q_DEP_l3_ctp(unsigned int ul3_ctp); +int iSetTL1_Q_DEP_l0_ctp(unsigned int ul0_ctp); +int iSetTL1_Q_DEP_l1_ctp(unsigned int ul1_ctp); +int iSetTL1_Q_DEP_l2_ctp(unsigned int ul2_ctp); +int iSetTL1_Q_DEP_l3_ctp(unsigned int ul3_ctp); +int iSetRQST_Q_DEP_l0_ctp(unsigned int ul0_ctp); +int iSetRQST_Q_DEP_l1_ctp(unsigned int ul1_ctp); +int iSetRQST_Q_DEP_l2_ctp(unsigned int ul2_ctp); +int iSetRQST_Q_DEP_l3_ctp(unsigned int ul3_ctp); +int iSetRSP_Q_DEP_l0_ctp(unsigned int ul0_ctp); +int iSetRSP_Q_DEP_l1_ctp(unsigned int ul1_ctp); +int iSetRSP_Q_DEP_l2_ctp(unsigned int ul2_ctp); +int iSetRSP_Q_DEP_l3_ctp(unsigned int ul3_ctp); +int iSetRSP_Q_DEP_l4_ctp(unsigned int ul4_ctp); +int iSetRQST_CRDT_CNT_sm0_ctp(unsigned int usm0_ctp); +int iSetRQST_CRDT_CNT_sm1_ctp(unsigned int usm1_ctp); +int iSetRQST_CRDT_CNT_sm2_ctp(unsigned int usm2_ctp); +int iSetRQST_CRDT_CNT_sm3_ctp(unsigned int usm3_ctp); +int iSetRESP_CRDT_CNT_sm0_ctp(unsigned int usm0_ctp); +int iSetRESP_CRDT_CNT_sm1_ctp(unsigned int usm1_ctp); +int iSetRESP_CRDT_CNT_sm2_ctp(unsigned int usm2_ctp); +int iSetRESP_CRDT_CNT_sm3_ctp(unsigned int usm3_ctp); +int iSetRESP_CRDT_CNT_smmc_ctp(unsigned int usmmc_ctp); +int iSetSMXR_CNT0_smxr_cnt0(unsigned int usmxr_cnt0); +int iSetSMXR_CNT1_smxr_cnt1(unsigned int usmxr_cnt1); +int iSetSMXR_CNT2_smxr_cnt2(unsigned int usmxr_cnt2); +int iSetSMXR_CNT3_smxr_cnt3(unsigned int usmxr_cnt3); +int iSetSMXT_CTP_api_cap_done(unsigned int uapi_cap_done); +int iSetSMXR_CFG2_rp_virtio_core_inst_id(unsigned int urp_virtio_core_inst_id); +int iSetSMXR_CFG2_rp_virtio_core_en(unsigned int urp_virtio_core_en); +int iSetSMXR_CFG3_rp_virtio_csr_crdt_init_val(unsigned int urp_virtio_csr_crdt_init_val); +int iSetSMXR_CFG3_rp_virtio_csr_crdt_init_en(unsigned int urp_virtio_csr_crdt_init_en); +int iSetSMXR_CFG3_rp_virtio_rqst_crdt_init_val(unsigned int urp_virtio_rqst_crdt_init_val); +int iSetSMXR_CFG3_rp_virtio_rqst_crdt_init_en(unsigned int urp_virtio_rqst_crdt_init_en); +int iSetSMXR_CFG3_rp_virtio_resp_crdt_init_val(unsigned int urp_virtio_resp_crdt_init_val); +int iSetSMXR_CFG3_rp_virtio_resp_crdt_init_en(unsigned int urp_virtio_resp_crdt_init_en); +int iSetCFG_MEM_CTRL_BUS0_cfg_mem_ctrl_bus0(unsigned int ucfg_mem_ctrl_bus0); +int iSetCFG_MEM_CTRL_BUS1_cfg_mem_ctrl_bus1(unsigned int ucfg_mem_ctrl_bus1); +int iSetCFG_MEM_CTRL_BUS2_cfg_mem_ctrl_bus2(unsigned int ucfg_mem_ctrl_bus2); +int iSetCFG_MEM_CTRL_BUS3_cfg_mem_ctrl_bus3(unsigned int ucfg_mem_ctrl_bus3); +int iSetCFG_MEM_CTRL_BUS4_cfg_mem_ctrl_bus4(unsigned int ucfg_mem_ctrl_bus4); +int iSetSMXT_CFG2_rp_fake_vf_info_pos(unsigned int urp_fake_vf_info_pos); +int iSetSMXT_CFG2_rp_fake_vf_info_value(unsigned int urp_fake_vf_info_value); +int iSetSMXT_CFG2_rp_fake_vf_info_en(unsigned int urp_fake_vf_info_en); + +/* Define the union csr_smir_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_version_u; + +/* Define the union csr_smir_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dis_rx_rqst : 1; /* [0] */ + u32 dis_rx_resp : 1; /* [1] */ + u32 simple_hash : 1; /* [2] */ + u32 reg_cap_ch_sel : 1; /* [3] */ + u32 msb_thread_cfg : 1; /* [4] */ + u32 mem_chk_en : 1; /* [5] */ + u32 rp_l2nic_db_pseudo_api_en : 1; /* [6] */ + u32 rsv_0 : 9; /* [15:7] */ + u32 sp_ram_tmod : 7; /* [22:16] */ + u32 mem_ret1n : 1; /* [23] */ + u32 rp_crt_err_inj_req : 1; /* [24] */ + u32 rp_uncrt_err_inj_req : 1; /* [25] */ + u32 rsv_1 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cfg_u; + +/* Define the union csr_smir_hash_seed0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hash_seed_cfg0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_hash_seed0_u; + +/* Define the union csr_smir_hash_seed1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hash_seed_cfg1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_hash_seed1_u; + +/* Define the union csr_smir_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_int_vector_u; + +/* Define the union csr_smir_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 5; /* [4:0] */ + u32 rsv_4 : 11; /* [15:5] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_int_u; + +/* Define the union csr_smir_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 5; /* [4:0] */ + u32 rsv_5 : 11; /* [15:5] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_int_mask_u; + +/* Define the union csr_smir_err_spec_th_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_err_spec_th_u; + +/* Define the union csr_smir_req_msg_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_req_msg_err_u; + +/* Define the union csr_smir_resp_msg_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_resp_msg_err_u; + +/* Define the union csr_smir_mem_ecc_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_mem_ecc_crt_err_u; + +/* Define the union csr_smir_mem_ecc_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_mem_ecc_uncrt_err_u; + +/* Define the union csr_smir_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_indir_addr : 24; /* [23:0] */ + u32 smir_indir_tab : 4; /* [27:24] */ + u32 smir_indir_stat : 2; /* [29:28] */ + u32 smir_indir_mode : 1; /* [30] */ + u32 smir_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_indrect_ctrl_u; + +/* Define the union csr_smir_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_indrect_timeout_u; + +/* Define the union csr_smir_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_indrect_data_u; + +/* Define the union csr_smir_cap0_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stag_h : 7; /* [6:0] */ + u32 rsv_6 : 3; /* [9:7] */ + u32 src : 5; /* [14:10] */ + u32 s_inst_id : 6; /* [20:15] */ + u32 s_op_id : 6; /* [26:21] */ + u32 s_code : 2; /* [28:27] */ + u32 s_e0_bit : 1; /* [29] */ + u32 s_e1_bit : 1; /* [30] */ + u32 cap_mode : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap0_cfg_u; + +/* Define the union csr_smir_cap1_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flit0_111_96_msk : 16; /* [15:0] */ + u32 flit0_111_96 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap1_cfg_u; + +/* Define the union csr_smir_cap2_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flit0_95_64 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap2_cfg_u; + +/* Define the union csr_smir_cap3_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flit0_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap3_cfg_u; + +/* Define the union csr_smir_cap4_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flit0_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap4_cfg_u; + +/* Define the union csr_smir_cap6_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 stag_l : 12; /* [11:0] */ + u32 thread_id : 7; /* [18:12] */ + u32 cap_thread_id_en : 1; /* [19] */ + u32 flit0_95_0_msk : 6; /* [25:20] */ + u32 rsv_7 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap6_cfg_u; + +/* Define the union csr_smir_en_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_en_cnt_0 : 8; /* [7:0] */ + u32 smir_en_cnt_1 : 8; /* [15:8] */ + u32 smir_en_cnt_2 : 8; /* [23:16] */ + u32 cap_stag_h_en : 1; /* [24] */ + u32 cap_src_en : 1; /* [25] */ + u32 cap_inst_en : 1; /* [26] */ + u32 cap_op_en : 1; /* [27] */ + u32 cap_code_en : 1; /* [28] */ + u32 cap_err0_en : 1; /* [29] */ + u32 cap_err1_en : 1; /* [30] */ + u32 cap_stag_l_en : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_en_cnt_u; + +/* Define the union csr_smir_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cnt0_u; + +/* Define the union csr_smir_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cnt1_u; + +/* Define the union csr_smir_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smir_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cnt2_u; + +/* Define the union csr_smir_crdt_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 eg0_ctp : 3; /* [2:0] */ + u32 resp_ctp : 3; /* [5:3] */ + u32 rqst_ctp : 3; /* [8:6] */ + u32 smmc_ctp : 5; /* [13:9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_crdt_cnt_u; + +/* Define the union csr_smir_cap_flit0_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit0_data0_u; + +/* Define the union csr_smir_cap_flit0_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit0_data1_u; + +/* Define the union csr_smir_cap_flit1_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit1_data0_u; + +/* Define the union csr_smir_cap_flit1_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit1_data1_u; + +/* Define the union csr_smir_cap_flit2_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit2_data0_u; + +/* Define the union csr_smir_cap_flit2_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit2_data1_u; + +/* Define the union csr_smir_cap_flit3_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit3_data0_u; + +/* Define the union csr_smir_cap_flit3_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit3_data1_u; + +/* Define the union csr_smir_cap_flit4_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit4_data0_u; + +/* Define the union csr_smir_cap_flit4_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit4_data1_u; + +/* Define the union csr_smir_cap_flit5_data0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit5_data0_u; + +/* Define the union csr_smir_cap_flit5_data1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data0 : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smir_cap_flit5_data1_u; + +/* Define the union csr_smir_cap_flit0_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit0_data2_u; + +/* Define the union csr_smir_cap_flit1_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit1_data2_u; + +/* Define the union csr_smir_cap_flit2_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit2_data2_u; + +/* Define the union csr_smir_cap_flit3_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit3_data2_u; + +/* Define the union csr_smir_cap_flit4_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit4_data2_u; + +/* Define the union csr_smir_cap_flit5_data2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 capture_data0 : 2; /* [1:0] */ + u32 trigger_enable : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cap_flit5_data2_u; + +/* Define the union csr_smir_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rp_l2nic_pf_start_idx : 4; /* [3:0] */ + u32 rp_l2nic_pf_end_idx : 4; /* [7:4] */ + u32 rp_l2nic_lb_md : 2; /* [9:8] */ + u32 rp_l2nic_cmdq_md : 2; /* [11:10] */ + u32 rp_l2nic_flexible_md : 1; /* [12] */ + u32 rsv_8 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smir_cfg1_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smir_version_u smir_version; /* 0 */ + volatile csr_smir_cfg_u smir_cfg; /* 4 */ + volatile csr_smir_hash_seed0_u smir_hash_seed0; /* 8 */ + volatile csr_smir_hash_seed1_u smir_hash_seed1; /* C */ + volatile csr_smir_int_vector_u smir_int_vector; /* 10 */ + volatile csr_smir_int_u smir_int; /* 14 */ + volatile csr_smir_int_mask_u smir_int_mask; /* 18 */ + volatile csr_smir_err_spec_th_u smir_err_spec_th; /* 1C */ + volatile csr_smir_req_msg_err_u smir_req_msg_err; /* 20 */ + volatile csr_smir_resp_msg_err_u smir_resp_msg_err; /* 24 */ + volatile csr_smir_mem_ecc_crt_err_u smir_mem_ecc_crt_err; /* 28 */ + volatile csr_smir_mem_ecc_uncrt_err_u smir_mem_ecc_uncrt_err; /* 2C */ + volatile csr_smir_indrect_ctrl_u smir_indrect_ctrl; /* 30 */ + volatile csr_smir_indrect_timeout_u smir_indrect_timeout; /* 34 */ + volatile csr_smir_indrect_data_u smir_indrect_data; /* 38 */ + volatile csr_smir_cap0_cfg_u smir_cap0_cfg; /* 3C */ + volatile csr_smir_cap1_cfg_u smir_cap1_cfg; /* 40 */ + volatile csr_smir_cap2_cfg_u smir_cap2_cfg; /* 44 */ + volatile csr_smir_cap3_cfg_u smir_cap3_cfg; /* 48 */ + volatile csr_smir_cap4_cfg_u smir_cap4_cfg; /* 4C */ + volatile csr_smir_cap6_cfg_u smir_cap6_cfg; /* 50 */ + volatile csr_smir_en_cnt_u smir_en_cnt; /* 54 */ + volatile csr_smir_cnt0_u smir_cnt0; /* 58 */ + volatile csr_smir_cnt1_u smir_cnt1; /* 5C */ + volatile csr_smir_cnt2_u smir_cnt2; /* 60 */ + volatile csr_smir_crdt_cnt_u smir_crdt_cnt; /* 64 */ + volatile csr_smir_cap_flit0_data0_u smir_cap_flit0_data0; /* 68 */ + volatile csr_smir_cap_flit0_data1_u smir_cap_flit0_data1; /* 70 */ + volatile csr_smir_cap_flit1_data0_u smir_cap_flit1_data0; /* 78 */ + volatile csr_smir_cap_flit1_data1_u smir_cap_flit1_data1; /* 80 */ + volatile csr_smir_cap_flit2_data0_u smir_cap_flit2_data0; /* 88 */ + volatile csr_smir_cap_flit2_data1_u smir_cap_flit2_data1; /* 90 */ + volatile csr_smir_cap_flit3_data0_u smir_cap_flit3_data0; /* 98 */ + volatile csr_smir_cap_flit3_data1_u smir_cap_flit3_data1; /* A0 */ + volatile csr_smir_cap_flit4_data0_u smir_cap_flit4_data0; /* A8 */ + volatile csr_smir_cap_flit4_data1_u smir_cap_flit4_data1; /* B0 */ + volatile csr_smir_cap_flit5_data0_u smir_cap_flit5_data0; /* B8 */ + volatile csr_smir_cap_flit5_data1_u smir_cap_flit5_data1; /* C0 */ + volatile csr_smir_cap_flit0_data2_u smir_cap_flit0_data2; /* C8 */ + volatile csr_smir_cap_flit1_data2_u smir_cap_flit1_data2; /* CC */ + volatile csr_smir_cap_flit2_data2_u smir_cap_flit2_data2; /* D0 */ + volatile csr_smir_cap_flit3_data2_u smir_cap_flit3_data2; /* D4 */ + volatile csr_smir_cap_flit4_data2_u smir_cap_flit4_data2; /* D8 */ + volatile csr_smir_cap_flit5_data2_u smir_cap_flit5_data2; /* DC */ + volatile csr_smir_cfg1_u smir_cfg1; /* E0 */ +} S_smir_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smir_csr */ +extern volatile S_smir_csr_REGS_TYPE *gopsmir_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMIR_VERSION_smir_version(unsigned int usmir_version); +int iSetSMIR_CFG_dis_rx_rqst(unsigned int udis_rx_rqst); +int iSetSMIR_CFG_dis_rx_resp(unsigned int udis_rx_resp); +int iSetSMIR_CFG_simple_hash(unsigned int usimple_hash); +int iSetSMIR_CFG_reg_cap_ch_sel(unsigned int ureg_cap_ch_sel); +int iSetSMIR_CFG_msb_thread_cfg(unsigned int umsb_thread_cfg); +int iSetSMIR_CFG_mem_chk_en(unsigned int umem_chk_en); +int iSetSMIR_CFG_rp_l2nic_db_pseudo_api_en(unsigned int urp_l2nic_db_pseudo_api_en); +int iSetSMIR_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMIR_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMIR_CFG_rp_crt_err_inj_req(unsigned int urp_crt_err_inj_req); +int iSetSMIR_CFG_rp_uncrt_err_inj_req(unsigned int urp_uncrt_err_inj_req); +int iSetSMIR_HASH_SEED0_hash_seed_cfg0(unsigned int uhash_seed_cfg0); +int iSetSMIR_HASH_SEED1_hash_seed_cfg1(unsigned int uhash_seed_cfg1); +int iSetSMIR_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMIR_INT_VECTOR_enable(unsigned int uenable); +int iSetSMIR_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMIR_INT_int_data(unsigned int uint_data); +int iSetSMIR_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMIR_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMIR_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMIR_ERR_SPEC_TH_err(unsigned int uerr); +int iSetSMIR_ERR_SPEC_TH_multi_err(unsigned int umulti_err); +int iSetSMIR_ERR_SPEC_TH_sticky(unsigned int usticky); +int iSetSMIR_REQ_MSG_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIR_REQ_MSG_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIR_REQ_MSG_ERR_sticky(unsigned int usticky); +int iSetSMIR_RESP_MSG_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIR_RESP_MSG_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIR_RESP_MSG_ERR_sticky(unsigned int usticky); +int iSetSMIR_MEM_ECC_CRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIR_MEM_ECC_CRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIR_MEM_ECC_CRT_ERR_sticky(unsigned int usticky); +int iSetSMIR_MEM_ECC_UNCRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIR_MEM_ECC_UNCRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIR_MEM_ECC_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMIR_INDRECT_CTRL_smir_indir_addr(unsigned int usmir_indir_addr); +int iSetSMIR_INDRECT_CTRL_smir_indir_tab(unsigned int usmir_indir_tab); +int iSetSMIR_INDRECT_CTRL_smir_indir_stat(unsigned int usmir_indir_stat); +int iSetSMIR_INDRECT_CTRL_smir_indir_mode(unsigned int usmir_indir_mode); +int iSetSMIR_INDRECT_CTRL_smir_indir_vld(unsigned int usmir_indir_vld); +int iSetSMIR_INDRECT_TIMEOUT_smir_indir_timeout(unsigned int usmir_indir_timeout); +int iSetSMIR_INDRECT_DATA_smir_indir_data(unsigned int usmir_indir_data); +int iSetSMIR_CAP0_CFG_stag_h(unsigned int ustag_h); +int iSetSMIR_CAP0_CFG_src(unsigned int usrc); +int iSetSMIR_CAP0_CFG_s_inst_id(unsigned int us_inst_id); +int iSetSMIR_CAP0_CFG_s_op_id(unsigned int us_op_id); +int iSetSMIR_CAP0_CFG_s_code(unsigned int us_code); +int iSetSMIR_CAP0_CFG_s_e0_bit(unsigned int us_e0_bit); +int iSetSMIR_CAP0_CFG_s_e1_bit(unsigned int us_e1_bit); +int iSetSMIR_CAP0_CFG_cap_mode(unsigned int ucap_mode); +int iSetSMIR_CAP1_CFG_flit0_111_96_msk(unsigned int uflit0_111_96_msk); +int iSetSMIR_CAP1_CFG_flit0_111_96(unsigned int uflit0_111_96); +int iSetSMIR_CAP2_CFG_flit0_95_64(unsigned int uflit0_95_64); +int iSetSMIR_CAP3_CFG_flit0_63_32(unsigned int uflit0_63_32); +int iSetSMIR_CAP4_CFG_flit0_31_0(unsigned int uflit0_31_0); +int iSetSMIR_CAP6_CFG_stag_l(unsigned int ustag_l); +int iSetSMIR_CAP6_CFG_thread_id(unsigned int uthread_id); +int iSetSMIR_CAP6_CFG_cap_thread_id_en(unsigned int ucap_thread_id_en); +int iSetSMIR_CAP6_CFG_flit0_95_0_msk(unsigned int uflit0_95_0_msk); +int iSetSMIR_EN_CNT_smir_en_cnt_0(unsigned int usmir_en_cnt_0); +int iSetSMIR_EN_CNT_smir_en_cnt_1(unsigned int usmir_en_cnt_1); +int iSetSMIR_EN_CNT_smir_en_cnt_2(unsigned int usmir_en_cnt_2); +int iSetSMIR_EN_CNT_cap_stag_h_en(unsigned int ucap_stag_h_en); +int iSetSMIR_EN_CNT_cap_src_en(unsigned int ucap_src_en); +int iSetSMIR_EN_CNT_cap_inst_en(unsigned int ucap_inst_en); +int iSetSMIR_EN_CNT_cap_op_en(unsigned int ucap_op_en); +int iSetSMIR_EN_CNT_cap_code_en(unsigned int ucap_code_en); +int iSetSMIR_EN_CNT_cap_err0_en(unsigned int ucap_err0_en); +int iSetSMIR_EN_CNT_cap_err1_en(unsigned int ucap_err1_en); +int iSetSMIR_EN_CNT_cap_stag_l_en(unsigned int ucap_stag_l_en); +int iSetSMIR_CNT0_smir_cnt0(unsigned int usmir_cnt0); +int iSetSMIR_CNT1_smir_cnt1(unsigned int usmir_cnt1); +int iSetSMIR_CNT2_smir_cnt2(unsigned int usmir_cnt2); +int iSetSMIR_CRDT_CNT_eg0_ctp(unsigned int ueg0_ctp); +int iSetSMIR_CRDT_CNT_resp_ctp(unsigned int uresp_ctp); +int iSetSMIR_CRDT_CNT_rqst_ctp(unsigned int urqst_ctp); +int iSetSMIR_CRDT_CNT_smmc_ctp(unsigned int usmmc_ctp); +int iSetSMIR_CAP_FLIT0_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT0_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT0_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT0_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT1_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT1_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT1_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT1_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT2_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT2_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT2_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT2_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT3_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT3_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT3_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT3_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT4_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT4_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT4_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT4_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT5_DATA0_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT5_DATA0_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT5_DATA1_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT5_DATA1_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT0_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT0_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT1_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT1_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT2_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT2_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT3_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT3_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT4_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT4_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CAP_FLIT5_DATA2_capture_data0(unsigned int ucapture_data0); +int iSetSMIR_CAP_FLIT5_DATA2_trigger_enable(unsigned int utrigger_enable); +int iSetSMIR_CFG1_rp_l2nic_pf_start_idx(unsigned int urp_l2nic_pf_start_idx); +int iSetSMIR_CFG1_rp_l2nic_pf_end_idx(unsigned int urp_l2nic_pf_end_idx); +int iSetSMIR_CFG1_rp_l2nic_lb_md(unsigned int urp_l2nic_lb_md); +int iSetSMIR_CFG1_rp_l2nic_cmdq_md(unsigned int urp_l2nic_cmdq_md); +int iSetSMIR_CFG1_rp_l2nic_flexible_md(unsigned int urp_l2nic_flexible_md); + +/* Define the union csr_smeg0_abuf0_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_abuf0_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_abuf0_version_u; + +/* Define the union csr_sm_abuf_th_grw_wm_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_0 : 30; /* [29:0] */ + u32 rsv_0 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_0_u; + +/* Define the union csr_sm_abuf_th_grw_wm_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_1 : 30; /* [29:0] */ + u32 rsv_1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_1_u; + +/* Define the union csr_sm_abuf_th_grw_wm_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_2 : 30; /* [29:0] */ + u32 rsv_2 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_2_u; + +/* Define the union csr_sm_abuf_th_grw_wm_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_3 : 30; /* [29:0] */ + u32 rsv_3 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_3_u; + +/* Define the union csr_sm_abuf_th_grw_wm_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_4 : 30; /* [29:0] */ + u32 rsv_4 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_4_u; + +/* Define the union csr_sm_abuf_th_grw_wm_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_5 : 30; /* [29:0] */ + u32 rsv_5 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_5_u; + +/* Define the union csr_sm_abuf_th_grw_wm_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_grow_6 : 12; /* [11:0] */ + u32 rsv_6 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_grw_wm_6_u; + +/* Define the union csr_sm_abuf_th_shk_wm_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_0 : 30; /* [29:0] */ + u32 rsv_7 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_0_u; + +/* Define the union csr_sm_abuf_th_shk_wm_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_1 : 30; /* [29:0] */ + u32 rsv_8 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_1_u; + +/* Define the union csr_sm_abuf_th_shk_wm_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_2 : 30; /* [29:0] */ + u32 rsv_9 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_2_u; + +/* Define the union csr_sm_abuf_th_shk_wm_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_3 : 30; /* [29:0] */ + u32 rsv_10 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_3_u; + +/* Define the union csr_sm_abuf_th_shk_wm_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_4 : 30; /* [29:0] */ + u32 rsv_11 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_4_u; + +/* Define the union csr_sm_abuf_th_shk_wm_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_5 : 30; /* [29:0] */ + u32 rsv_12 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_5_u; + +/* Define the union csr_sm_abuf_th_shk_wm_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 th_shrink_6 : 12; /* [11:0] */ + u32 rsv_13 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_th_shk_wm_6_u; + +/* Define the union csr_sm_abuf_flrc_attr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flid_torc : 5; /* [4:0] */ + u32 rsv_14 : 3; /* [7:5] */ + u32 en_rclm : 1; /* [8] */ + u32 stop_rclm : 1; /* [9] */ + u32 rsv_15 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_flrc_attr_u; + +/* Define the union csr_sm_abuf_flrc_num_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_rclm : 28; /* [27:0] */ + u32 rsv_16 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_flrc_num_u; + +/* Define the union csr_sm_abuf_flrc_bound_u_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_flrc_bound_u : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_flrc_bound_u_u; + +/* Define the union csr_sm_abuf_flrc_bound_l_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_flrc_bound_l : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_flrc_bound_l_u; + +/* Define the union csr_sm_abuf_pf_lifo_clr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_pf_lifo_clr : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_pf_lifo_clr_u; + +/* Define the union csr_sm_abuf_mem_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 lifo_pberr_gen : 1; /* [0] */ + u32 info_pberr_gen : 1; /* [1] */ + u32 ibuf_pberr_gen : 1; /* [2] */ + u32 ireq_pberr_gen : 1; /* [3] */ + u32 pb_chk_en : 1; /* [4] */ + u32 rsv_17 : 3; /* [7:5] */ + u32 sp_ram_tmod : 7; /* [14:8] */ + u32 mem_ret1n : 1; /* [15] */ + u32 tp_ram_tmod : 8; /* [23:16] */ + u32 rsv_18 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_mem_cfg_u; + +/* Define the union csr_sm_abuf_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_19 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_20 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_int_vector_u; + +/* Define the union csr_sm_abuf_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_21 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_int_u; + +/* Define the union csr_sm_abuf_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 6; /* [5:0] */ + u32 rsv_22 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_int_mask_u; + +/* Define the union csr_sm_abuf_pberr_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_pberr_u; + +/* Define the union csr_sm_abuf_fl_uflow_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_fl_uflow_err_u; + +/* Define the union csr_sm_abuf_fl_oflow_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_fl_oflow_err_u; + +/* Define the union csr_sm_abuf_fl_tail_miss_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_fl_tail_miss_err_u; + +/* Define the union csr_smeg0_abuf_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_abuf_indir_addr : 24; /* [23:0] */ + u32 smeg0_abuf_indir_tab : 4; /* [27:24] */ + u32 smeg0_abuf_indir_stat : 2; /* [29:28] */ + u32 smeg0_abuf_indir_mode : 1; /* [30] */ + u32 smeg0_abuf_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_abuf_indrect_ctrl_u; + +/* Define the union csr_smeg0_abuf_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_abuf_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_abuf_indrect_timeout_u; + +/* Define the union csr_smeg0_abuf_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_abuf_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_abuf_indrect_data_u; + +/* Define the union csr_sm_abuf_dis_alloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_dis_alloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_dis_alloc_u; + +/* Define the union csr_sm_abuf_dis_de_alloc_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_dis_de_alloc : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_dis_de_alloc_u; + +/* Define the union csr_sm_abuf_flrc_st_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 done_rclm : 1; /* [0] */ + u32 rlist_cleaning : 1; /* [1] */ + u32 wlist_cleaning : 1; /* [2] */ + u32 rsv_23 : 1; /* [3] */ + u32 ctp : 28; /* [31:4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_flrc_st_u; + +/* Define the union csr_sm_abuf_empty_fl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_empty_fl_u; + +/* Define the union csr_sm_abuf_full_fl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_full_fl_u; + +/* Define the union csr_sm_abuf_st_wm_grow_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_st_wm_grow_u; + +/* Define the union csr_sm_abuf_st_wm_shrink_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_st_wm_shrink_u; + +/* Define the union csr_sm_abuf_cnt_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_src_sel : 5; /* [4:0] */ + u32 cnt0_event_sel : 3; /* [7:5] */ + u32 cnt1_src_sel : 5; /* [12:8] */ + u32 cnt1_event_sel : 3; /* [15:13] */ + u32 cnt2_src_sel : 5; /* [20:16] */ + u32 cnt2_event_sel : 3; /* [23:21] */ + u32 cnt3_src_sel : 5; /* [28:24] */ + u32 cnt3_event_sel : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_cnt_sel0_u; + +/* Define the union csr_sm_abuf_cnt_sel1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt4_src_sel : 5; /* [4:0] */ + u32 cnt4_event_sel : 3; /* [7:5] */ + u32 cnt5_src_sel : 5; /* [12:8] */ + u32 cnt5_event_sel : 3; /* [15:13] */ + u32 cnt_enable : 6; /* [21:16] */ + u32 rsv_24 : 10; /* [31:22] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_cnt_sel1_u; + +/* Define the union csr_sm_abuf_counter0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter0_u; + +/* Define the union csr_sm_abuf_counter1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter1_u; + +/* Define the union csr_sm_abuf_counter2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter2_u; + +/* Define the union csr_sm_abuf_counter3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter3_u; + +/* Define the union csr_sm_abuf_counter4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter4 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter4_u; + +/* Define the union csr_sm_abuf_counter5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sm_abuf_counter5 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_counter5_u; + +/* Define the union csr_sm_abuf_pfetch_flag_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_pfetch_flag_u; + +/* Define the union csr_sm_abuf_ireq_list_sta_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_ireq_list_sta_u; + +/* Define the union csr_sm_abuf_tail_miss0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_sm_abuf_tail_miss0_u; + +/* Define the union csr_sm_abuf_tail_miss1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 capture_data : 63; /* [62:0] */ + u64 trigger_enable : 1; /* [63] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_sm_abuf_tail_miss1_u; + +/* Define the union csr_sm_abuf_cnt_lifo_pfetch_0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 ctp : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_sm_abuf_cnt_lifo_pfetch_0_u; + +/* Define the union csr_sm_abuf_cnt_lifo_pfetch_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 ctp : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_sm_abuf_cnt_lifo_pfetch_1_u; + +/* Define the union csr_sm_abuf_cnt_lifo_pfetch_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ctp : 4; /* [3:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_cnt_lifo_pfetch_2_u; + +/* Define the union csr_sm_abuf_ecc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 list_info_1b_ecc_inj_en : 1; /* [0] */ + u32 list_info_2b_ecc_inj_en : 1; /* [1] */ + u32 list_info_ecc_en : 1; /* [2] */ + u32 rsv_25 : 1; /* [3] */ + u32 lifo_1b_ecc_inj_en : 1; /* [4] */ + u32 lifo_2b_ecc_inj_en : 1; /* [5] */ + u32 lifo_ecc_en : 1; /* [6] */ + u32 rsv_26 : 1; /* [7] */ + u32 rsv_27 : 24; /* [31:8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_ecc_cfg_u; + +/* Define the union csr_sm_abuf_ecc_1b_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_ecc_1b_err_int_u; + +/* Define the union csr_sm_abuf_ecc_2b_err_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_sm_abuf_ecc_2b_err_int_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smeg0_abuf0_version_u smeg0_abuf0_version; /* 0 */ + volatile csr_sm_abuf_th_grw_wm_0_u sm_abuf_th_grw_wm_0; /* 4 */ + volatile csr_sm_abuf_th_grw_wm_1_u sm_abuf_th_grw_wm_1; /* 8 */ + volatile csr_sm_abuf_th_grw_wm_2_u sm_abuf_th_grw_wm_2; /* C */ + volatile csr_sm_abuf_th_grw_wm_3_u sm_abuf_th_grw_wm_3; /* 10 */ + volatile csr_sm_abuf_th_grw_wm_4_u sm_abuf_th_grw_wm_4; /* 14 */ + volatile csr_sm_abuf_th_grw_wm_5_u sm_abuf_th_grw_wm_5; /* 18 */ + volatile csr_sm_abuf_th_grw_wm_6_u sm_abuf_th_grw_wm_6; /* 1C */ + volatile csr_sm_abuf_th_shk_wm_0_u sm_abuf_th_shk_wm_0; /* 20 */ + volatile csr_sm_abuf_th_shk_wm_1_u sm_abuf_th_shk_wm_1; /* 24 */ + volatile csr_sm_abuf_th_shk_wm_2_u sm_abuf_th_shk_wm_2; /* 28 */ + volatile csr_sm_abuf_th_shk_wm_3_u sm_abuf_th_shk_wm_3; /* 2C */ + volatile csr_sm_abuf_th_shk_wm_4_u sm_abuf_th_shk_wm_4; /* 30 */ + volatile csr_sm_abuf_th_shk_wm_5_u sm_abuf_th_shk_wm_5; /* 34 */ + volatile csr_sm_abuf_th_shk_wm_6_u sm_abuf_th_shk_wm_6; /* 38 */ + volatile csr_sm_abuf_flrc_attr_u sm_abuf_flrc_attr; /* 3C */ + volatile csr_sm_abuf_flrc_num_u sm_abuf_flrc_num; /* 40 */ + volatile csr_sm_abuf_flrc_bound_u_u sm_abuf_flrc_bound_u; /* 44 */ + volatile csr_sm_abuf_flrc_bound_l_u sm_abuf_flrc_bound_l; /* 48 */ + volatile csr_sm_abuf_pf_lifo_clr_u sm_abuf_pf_lifo_clr; /* 4C */ + volatile csr_sm_abuf_mem_cfg_u sm_abuf_mem_cfg; /* 50 */ + volatile csr_sm_abuf_int_vector_u sm_abuf_int_vector; /* 54 */ + volatile csr_sm_abuf_int_u sm_abuf_int; /* 58 */ + volatile csr_sm_abuf_int_mask_u sm_abuf_int_mask; /* 5C */ + volatile csr_sm_abuf_pberr_u sm_abuf_pberr; /* 60 */ + volatile csr_sm_abuf_fl_uflow_err_u sm_abuf_fl_uflow_err; /* 64 */ + volatile csr_sm_abuf_fl_oflow_err_u sm_abuf_fl_oflow_err; /* 68 */ + volatile csr_sm_abuf_fl_tail_miss_err_u sm_abuf_fl_tail_miss_err; /* 6C */ + volatile csr_smeg0_abuf_indrect_ctrl_u smeg0_abuf_indrect_ctrl; /* 70 */ + volatile csr_smeg0_abuf_indrect_timeout_u smeg0_abuf_indrect_timeout; /* 74 */ + volatile csr_smeg0_abuf_indrect_data_u smeg0_abuf_indrect_data; /* 78 */ + volatile csr_sm_abuf_dis_alloc_u sm_abuf_dis_alloc; /* 7C */ + volatile csr_sm_abuf_dis_de_alloc_u sm_abuf_dis_de_alloc; /* 80 */ + volatile csr_sm_abuf_flrc_st_u sm_abuf_flrc_st; /* 84 */ + volatile csr_sm_abuf_empty_fl_u sm_abuf_empty_fl; /* 88 */ + volatile csr_sm_abuf_full_fl_u sm_abuf_full_fl; /* 8C */ + volatile csr_sm_abuf_st_wm_grow_u sm_abuf_st_wm_grow; /* 90 */ + volatile csr_sm_abuf_st_wm_shrink_u sm_abuf_st_wm_shrink; /* 94 */ + volatile csr_sm_abuf_cnt_sel0_u sm_abuf_cnt_sel0; /* 98 */ + volatile csr_sm_abuf_cnt_sel1_u sm_abuf_cnt_sel1; /* 9C */ + volatile csr_sm_abuf_counter0_u sm_abuf_counter0; /* A0 */ + volatile csr_sm_abuf_counter1_u sm_abuf_counter1; /* A4 */ + volatile csr_sm_abuf_counter2_u sm_abuf_counter2; /* A8 */ + volatile csr_sm_abuf_counter3_u sm_abuf_counter3; /* AC */ + volatile csr_sm_abuf_counter4_u sm_abuf_counter4; /* B0 */ + volatile csr_sm_abuf_counter5_u sm_abuf_counter5; /* B4 */ + volatile csr_sm_abuf_pfetch_flag_u sm_abuf_pfetch_flag; /* B8 */ + volatile csr_sm_abuf_ireq_list_sta_u sm_abuf_ireq_list_sta; /* BC */ + volatile csr_sm_abuf_tail_miss0_u sm_abuf_tail_miss0; /* C0 */ + volatile csr_sm_abuf_tail_miss1_u sm_abuf_tail_miss1; /* C8 */ + volatile csr_sm_abuf_cnt_lifo_pfetch_0_u sm_abuf_cnt_lifo_pfetch_0; /* D0 */ + volatile csr_sm_abuf_cnt_lifo_pfetch_1_u sm_abuf_cnt_lifo_pfetch_1; /* D8 */ + volatile csr_sm_abuf_cnt_lifo_pfetch_2_u sm_abuf_cnt_lifo_pfetch_2; /* E0 */ + volatile csr_sm_abuf_ecc_cfg_u sm_abuf_ecc_cfg; /* E4 */ + volatile csr_sm_abuf_ecc_1b_err_int_u sm_abuf_ecc_1b_err_int; /* E8 */ + volatile csr_sm_abuf_ecc_2b_err_int_u sm_abuf_ecc_2b_err_int; /* EC */ +} S_smeg0_abuf0_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smeg0_abuf0_csr */ +extern volatile S_smeg0_abuf0_csr_REGS_TYPE *gopsmeg0_abuf0_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMEG0_ABUF0_VERSION_smeg0_abuf0_version(unsigned int usmeg0_abuf0_version); +int iSetSM_ABUF_TH_GRW_WM_0_th_grow_0(unsigned int uth_grow_0); +int iSetSM_ABUF_TH_GRW_WM_1_th_grow_1(unsigned int uth_grow_1); +int iSetSM_ABUF_TH_GRW_WM_2_th_grow_2(unsigned int uth_grow_2); +int iSetSM_ABUF_TH_GRW_WM_3_th_grow_3(unsigned int uth_grow_3); +int iSetSM_ABUF_TH_GRW_WM_4_th_grow_4(unsigned int uth_grow_4); +int iSetSM_ABUF_TH_GRW_WM_5_th_grow_5(unsigned int uth_grow_5); +int iSetSM_ABUF_TH_GRW_WM_6_th_grow_6(unsigned int uth_grow_6); +int iSetSM_ABUF_TH_SHK_WM_0_th_shrink_0(unsigned int uth_shrink_0); +int iSetSM_ABUF_TH_SHK_WM_1_th_shrink_1(unsigned int uth_shrink_1); +int iSetSM_ABUF_TH_SHK_WM_2_th_shrink_2(unsigned int uth_shrink_2); +int iSetSM_ABUF_TH_SHK_WM_3_th_shrink_3(unsigned int uth_shrink_3); +int iSetSM_ABUF_TH_SHK_WM_4_th_shrink_4(unsigned int uth_shrink_4); +int iSetSM_ABUF_TH_SHK_WM_5_th_shrink_5(unsigned int uth_shrink_5); +int iSetSM_ABUF_TH_SHK_WM_6_th_shrink_6(unsigned int uth_shrink_6); +int iSetSM_ABUF_FLRC_ATTR_flid_torc(unsigned int uflid_torc); +int iSetSM_ABUF_FLRC_ATTR_en_rclm(unsigned int uen_rclm); +int iSetSM_ABUF_FLRC_ATTR_stop_rclm(unsigned int ustop_rclm); +int iSetSM_ABUF_FLRC_NUM_num_rclm(unsigned int unum_rclm); +int iSetSM_ABUF_FLRC_BOUND_U_sm_abuf_flrc_bound_u(unsigned int usm_abuf_flrc_bound_u); +int iSetSM_ABUF_FLRC_BOUND_L_sm_abuf_flrc_bound_l(unsigned int usm_abuf_flrc_bound_l); +int iSetSM_ABUF_PF_LIFO_CLR_sm_abuf_pf_lifo_clr(unsigned int usm_abuf_pf_lifo_clr); +int iSetSM_ABUF_MEM_CFG_lifo_pberr_gen(unsigned int ulifo_pberr_gen); +int iSetSM_ABUF_MEM_CFG_info_pberr_gen(unsigned int uinfo_pberr_gen); +int iSetSM_ABUF_MEM_CFG_ibuf_pberr_gen(unsigned int uibuf_pberr_gen); +int iSetSM_ABUF_MEM_CFG_ireq_pberr_gen(unsigned int uireq_pberr_gen); +int iSetSM_ABUF_MEM_CFG_pb_chk_en(unsigned int upb_chk_en); +int iSetSM_ABUF_MEM_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSM_ABUF_MEM_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSM_ABUF_MEM_CFG_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSM_ABUF_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSM_ABUF_INT_VECTOR_enable(unsigned int uenable); +int iSetSM_ABUF_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSM_ABUF_INT_int_data(unsigned int uint_data); +int iSetSM_ABUF_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSM_ABUF_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSM_ABUF_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSM_ABUF_PBERR_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_PBERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_PBERR_sticky(unsigned int usticky); +int iSetSM_ABUF_FL_UFLOW_ERR_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_FL_UFLOW_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_FL_UFLOW_ERR_sticky(unsigned int usticky); +int iSetSM_ABUF_FL_OFLOW_ERR_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_FL_OFLOW_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_FL_OFLOW_ERR_sticky(unsigned int usticky); +int iSetSM_ABUF_FL_TAIL_MISS_ERR_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_FL_TAIL_MISS_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_FL_TAIL_MISS_ERR_sticky(unsigned int usticky); +int iSetSMEG0_ABUF_INDRECT_CTRL_smeg0_abuf_indir_addr(unsigned int usmeg0_abuf_indir_addr); +int iSetSMEG0_ABUF_INDRECT_CTRL_smeg0_abuf_indir_tab(unsigned int usmeg0_abuf_indir_tab); +int iSetSMEG0_ABUF_INDRECT_CTRL_smeg0_abuf_indir_stat(unsigned int usmeg0_abuf_indir_stat); +int iSetSMEG0_ABUF_INDRECT_CTRL_smeg0_abuf_indir_mode(unsigned int usmeg0_abuf_indir_mode); +int iSetSMEG0_ABUF_INDRECT_CTRL_smeg0_abuf_indir_vld(unsigned int usmeg0_abuf_indir_vld); +int iSetSMEG0_ABUF_INDRECT_TIMEOUT_smeg0_abuf_indir_timeout(unsigned int usmeg0_abuf_indir_timeout); +int iSetSMEG0_ABUF_INDRECT_DATA_smeg0_abuf_indir_data(unsigned int usmeg0_abuf_indir_data); +int iSetSM_ABUF_DIS_ALLOC_sm_abuf_dis_alloc(unsigned int usm_abuf_dis_alloc); +int iSetSM_ABUF_DIS_DE_ALLOC_sm_abuf_dis_de_alloc(unsigned int usm_abuf_dis_de_alloc); +int iSetSM_ABUF_FLRC_ST_done_rclm(unsigned int udone_rclm); +int iSetSM_ABUF_FLRC_ST_rlist_cleaning(unsigned int urlist_cleaning); +int iSetSM_ABUF_FLRC_ST_wlist_cleaning(unsigned int uwlist_cleaning); +int iSetSM_ABUF_FLRC_ST_ctp(unsigned int uctp); +int iSetSM_ABUF_EMPTY_FL_ctp(unsigned int uctp); +int iSetSM_ABUF_FULL_FL_ctp(unsigned int uctp); +int iSetSM_ABUF_ST_WM_GROW_ctp(unsigned int uctp); +int iSetSM_ABUF_ST_WM_SHRINK_ctp(unsigned int uctp); +int iSetSM_ABUF_CNT_SEL0_cnt0_src_sel(unsigned int ucnt0_src_sel); +int iSetSM_ABUF_CNT_SEL0_cnt0_event_sel(unsigned int ucnt0_event_sel); +int iSetSM_ABUF_CNT_SEL0_cnt1_src_sel(unsigned int ucnt1_src_sel); +int iSetSM_ABUF_CNT_SEL0_cnt1_event_sel(unsigned int ucnt1_event_sel); +int iSetSM_ABUF_CNT_SEL0_cnt2_src_sel(unsigned int ucnt2_src_sel); +int iSetSM_ABUF_CNT_SEL0_cnt2_event_sel(unsigned int ucnt2_event_sel); +int iSetSM_ABUF_CNT_SEL0_cnt3_src_sel(unsigned int ucnt3_src_sel); +int iSetSM_ABUF_CNT_SEL0_cnt3_event_sel(unsigned int ucnt3_event_sel); +int iSetSM_ABUF_CNT_SEL1_cnt4_src_sel(unsigned int ucnt4_src_sel); +int iSetSM_ABUF_CNT_SEL1_cnt4_event_sel(unsigned int ucnt4_event_sel); +int iSetSM_ABUF_CNT_SEL1_cnt5_src_sel(unsigned int ucnt5_src_sel); +int iSetSM_ABUF_CNT_SEL1_cnt5_event_sel(unsigned int ucnt5_event_sel); +int iSetSM_ABUF_CNT_SEL1_cnt_enable(unsigned int ucnt_enable); +int iSetSM_ABUF_COUNTER0_sm_abuf_counter0(unsigned int usm_abuf_counter0); +int iSetSM_ABUF_COUNTER1_sm_abuf_counter1(unsigned int usm_abuf_counter1); +int iSetSM_ABUF_COUNTER2_sm_abuf_counter2(unsigned int usm_abuf_counter2); +int iSetSM_ABUF_COUNTER3_sm_abuf_counter3(unsigned int usm_abuf_counter3); +int iSetSM_ABUF_COUNTER4_sm_abuf_counter4(unsigned int usm_abuf_counter4); +int iSetSM_ABUF_COUNTER5_sm_abuf_counter5(unsigned int usm_abuf_counter5); +int iSetSM_ABUF_PFETCH_FLAG_ctp(unsigned int uctp); +int iSetSM_ABUF_IREQ_LIST_STA_ctp(unsigned int uctp); +int iSetSM_ABUF_TAIL_MISS0_capture_data(unsigned int ucapture_data); +int iSetSM_ABUF_TAIL_MISS0_trigger_enable(unsigned int utrigger_enable); +int iSetSM_ABUF_TAIL_MISS1_capture_data(unsigned int ucapture_data); +int iSetSM_ABUF_TAIL_MISS1_trigger_enable(unsigned int utrigger_enable); +int iSetSM_ABUF_CNT_LIFO_PFETCH_0_ctp(unsigned int uctp); +int iSetSM_ABUF_CNT_LIFO_PFETCH_1_ctp(unsigned int uctp); +int iSetSM_ABUF_CNT_LIFO_PFETCH_2_ctp(unsigned int uctp); +int iSetSM_ABUF_ECC_CFG_list_info_1b_ecc_inj_en(unsigned int ulist_info_1b_ecc_inj_en); +int iSetSM_ABUF_ECC_CFG_list_info_2b_ecc_inj_en(unsigned int ulist_info_2b_ecc_inj_en); +int iSetSM_ABUF_ECC_CFG_list_info_ecc_en(unsigned int ulist_info_ecc_en); +int iSetSM_ABUF_ECC_CFG_lifo_1b_ecc_inj_en(unsigned int ulifo_1b_ecc_inj_en); +int iSetSM_ABUF_ECC_CFG_lifo_2b_ecc_inj_en(unsigned int ulifo_2b_ecc_inj_en); +int iSetSM_ABUF_ECC_CFG_lifo_ecc_en(unsigned int ulifo_ecc_en); +int iSetSM_ABUF_ECC_1B_ERR_INT_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_ECC_1B_ERR_INT_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_ECC_1B_ERR_INT_sticky(unsigned int usticky); +int iSetSM_ABUF_ECC_2B_ERR_INT_error_bit(unsigned int uerror_bit); +int iSetSM_ABUF_ECC_2B_ERR_INT_multi_error_bit(unsigned int umulti_error_bit); +int iSetSM_ABUF_ECC_2B_ERR_INT_sticky(unsigned int usticky); + +/* Define the union csr_smeg0_aget_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_aget_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_version_u; + +/* Define the union csr_smeg0_aget_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_chk_en : 1; /* [0] */ + u32 rsv_0 : 7; /* [7:1] */ + u32 sp_ram_tmod : 7; /* [14:8] */ + u32 mem_ret1n : 1; /* [15] */ + u32 smeg_core_mem_init_start : 1; /* [16] */ + u32 smeg0_cnt0_cfg : 2; /* [18:17] */ + u32 smeg0_cnt1_cfg : 2; /* [20:19] */ + u32 rsv_1 : 11; /* [31:21] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_cfg_u; + +/* Define the union csr_smeg0_aget_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_int_vector_u; + +/* Define the union csr_smeg0_aget_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 2; /* [1:0] */ + u32 rsv_4 : 14; /* [15:2] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_int_u; + +/* Define the union csr_smeg0_aget_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 2; /* [1:0] */ + u32 rsv_5 : 14; /* [15:2] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_int_mask_u; + +/* Define the union csr_smeg0_aget_mem_prty_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_mem_prty_err_u; + +/* Define the union csr_smeg0_aget_boundary_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_boundary_err_u; + +/* Define the union csr_smeg0_aget_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_aget_indir_addr : 24; /* [23:0] */ + u32 smeg0_aget_indir_tab : 4; /* [27:24] */ + u32 smeg0_aget_indir_stat : 2; /* [29:28] */ + u32 smeg0_aget_indir_mode : 1; /* [30] */ + u32 smeg0_aget_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_indrect_ctrl_u; + +/* Define the union csr_smeg0_aget_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_aget_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_indrect_timeout_u; + +/* Define the union csr_smeg0_aget_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_aget_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_aget_indrect_data_u; + +/* Define the union csr_smeg_core_mem_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 done : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg_core_mem_init_u; + +/* Define the union csr_smeg0_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_cnt0_u; + +/* Define the union csr_smeg0_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_cnt1_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smeg0_aget_version_u smeg0_aget_version; /* 0 */ + volatile csr_smeg0_aget_cfg_u smeg0_aget_cfg; /* 4 */ + volatile csr_smeg0_aget_int_vector_u smeg0_aget_int_vector; /* 8 */ + volatile csr_smeg0_aget_int_u smeg0_aget_int; /* C */ + volatile csr_smeg0_aget_int_mask_u smeg0_aget_int_mask; /* 10 */ + volatile csr_smeg0_aget_mem_prty_err_u smeg0_aget_mem_prty_err; /* 14 */ + volatile csr_smeg0_aget_boundary_err_u smeg0_aget_boundary_err; /* 18 */ + volatile csr_smeg0_aget_indrect_ctrl_u smeg0_aget_indrect_ctrl; /* 1C */ + volatile csr_smeg0_aget_indrect_timeout_u smeg0_aget_indrect_timeout; /* 20 */ + volatile csr_smeg0_aget_indrect_data_u smeg0_aget_indrect_data; /* 24 */ + volatile csr_smeg_core_mem_init_u smeg_core_mem_init; /* 28 */ + volatile csr_smeg0_cnt0_u smeg0_cnt0; /* 2C */ + volatile csr_smeg0_cnt1_u smeg0_cnt1; /* 30 */ +} S_smeg0_aget_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smeg0_aget_csr */ +extern volatile S_smeg0_aget_csr_REGS_TYPE *gopsmeg0_aget_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMEG0_AGET_VERSION_smeg0_aget_version(unsigned int usmeg0_aget_version); +int iSetSMEG0_AGET_CFG_mem_chk_en(unsigned int umem_chk_en); +int iSetSMEG0_AGET_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMEG0_AGET_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMEG0_AGET_CFG_smeg_core_mem_init_start(unsigned int usmeg_core_mem_init_start); +int iSetSMEG0_AGET_CFG_smeg0_cnt0_cfg(unsigned int usmeg0_cnt0_cfg); +int iSetSMEG0_AGET_CFG_smeg0_cnt1_cfg(unsigned int usmeg0_cnt1_cfg); +int iSetSMEG0_AGET_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMEG0_AGET_INT_VECTOR_enable(unsigned int uenable); +int iSetSMEG0_AGET_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMEG0_AGET_INT_int_data(unsigned int uint_data); +int iSetSMEG0_AGET_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG0_AGET_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMEG0_AGET_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG0_AGET_MEM_PRTY_ERR_err(unsigned int uerr); +int iSetSMEG0_AGET_MEM_PRTY_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_AGET_MEM_PRTY_ERR_sticky(unsigned int usticky); +int iSetSMEG0_AGET_BOUNDARY_ERR_err(unsigned int uerr); +int iSetSMEG0_AGET_BOUNDARY_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_AGET_BOUNDARY_ERR_sticky(unsigned int usticky); +int iSetSMEG0_AGET_INDRECT_CTRL_smeg0_aget_indir_addr(unsigned int usmeg0_aget_indir_addr); +int iSetSMEG0_AGET_INDRECT_CTRL_smeg0_aget_indir_tab(unsigned int usmeg0_aget_indir_tab); +int iSetSMEG0_AGET_INDRECT_CTRL_smeg0_aget_indir_stat(unsigned int usmeg0_aget_indir_stat); +int iSetSMEG0_AGET_INDRECT_CTRL_smeg0_aget_indir_mode(unsigned int usmeg0_aget_indir_mode); +int iSetSMEG0_AGET_INDRECT_CTRL_smeg0_aget_indir_vld(unsigned int usmeg0_aget_indir_vld); +int iSetSMEG0_AGET_INDRECT_TIMEOUT_smeg0_aget_indir_timeout(unsigned int usmeg0_aget_indir_timeout); +int iSetSMEG0_AGET_INDRECT_DATA_smeg0_aget_indir_data(unsigned int usmeg0_aget_indir_data); +int iSetSMEG_CORE_MEM_INIT_done(unsigned int udone); +int iSetSMEG0_CNT0_smeg0_cnt0(unsigned int usmeg0_cnt0); +int iSetSMEG0_CNT1_smeg0_cnt1(unsigned int usmeg0_cnt1); + +/* Define the union csr_smeg0_lu_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_version_u; + +/* Define the union csr_smeg0_lu_chk_enable_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_0 : 1; /* [0] */ + u32 flit_fifo_chk_enable : 1; /* [1] */ + u32 pipe1_mem_chk_enable : 1; /* [2] */ + u32 pipe0_mem_chk_enable : 1; /* [3] */ + u32 rsv_1 : 4; /* [7:4] */ + u32 tp_ram_tmod : 8; /* [15:8] */ + u32 sp_ram_tmod : 7; /* [22:16] */ + u32 mem_ret1n : 1; /* [23] */ + u32 rsv_2 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_chk_enable_cfg_u; + +/* Define the union csr_smeg0_lu_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_3 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_4 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_int_vector_u; + +/* Define the union csr_smeg0_lu_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 7; /* [6:0] */ + u32 rsv_5 : 9; /* [15:7] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_int_u; + +/* Define the union csr_smeg0_lu_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 7; /* [6:0] */ + u32 rsv_6 : 9; /* [15:7] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_int_mask_u; + +/* Define the union csr_smeg0_lu_pipe0_mem_ecc_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_pipe0_mem_ecc_crt_err_u; + +/* Define the union csr_smeg0_lu_pipe0_mem_ecc_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_pipe0_mem_ecc_uncrt_err_u; + +/* Define the union csr_smeg0_lu_pipe1_mem_ecc_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_pipe1_mem_ecc_crt_err_u; + +/* Define the union csr_smeg0_lu_pipe1_mem_ecc_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_pipe1_mem_ecc_uncrt_err_u; + +/* Define the union csr_smeg0_lu_flitfifo_mem_ecc_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_flitfifo_mem_ecc_crt_err_u; + +/* Define the union csr_smeg0_lu_flitfifo_mem_ecc_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_flitfifo_mem_ecc_uncrt_err_u; + +/* Define the union csr_smeg0_lu_sw_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err : 1; /* [0] */ + u32 multi_err : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_sw_err_u; + +/* Define the union csr_smeg0_lu_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_indir_addr : 24; /* [23:0] */ + u32 smeg0_lu_indir_tab : 4; /* [27:24] */ + u32 smeg0_lu_indir_stat : 2; /* [29:28] */ + u32 smeg0_lu_indir_mode : 1; /* [30] */ + u32 smeg0_lu_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_indrect_ctrl_u; + +/* Define the union csr_smeg0_lu_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_indrect_timeout_u; + +/* Define the union csr_smeg0_lu_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_indrect_data_u; + +/* Define the union csr_smeg0_lu_err_inj_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 pipe0_crt_err_inj_req : 1; /* [0] */ + u32 pipe0_uncrt_err_inj_req : 1; /* [1] */ + u32 pipe1_crt_err_inj_req : 1; /* [2] */ + u32 pipe1_uncrt_err_inj_req : 1; /* [3] */ + u32 flitf_crt_err_inj_req : 1; /* [4] */ + u32 flitf_uncrt_err_inj_req : 1; /* [5] */ + u32 rsv_7 : 26; /* [31:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_err_inj_cfg_u; + +/* Define the union csr_smeg0_lu_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_enable : 4; /* [3:0] */ + u32 cnt0_event_sel : 1; /* [4] */ + u32 cnt1_event_sel : 1; /* [5] */ + u32 cnt2_event_sel : 1; /* [6] */ + u32 cnt3_event_sel : 1; /* [7] */ + u32 eng_event_grp : 3; /* [10:8] */ + u32 rsv_8 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_cnt_cfg_u; + +/* Define the union csr_smeg0_lu_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_cnt0_u; + +/* Define the union csr_smeg0_lu_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_cnt1_u; + +/* Define the union csr_smeg0_lu_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_cnt2_u; + +/* Define the union csr_smeg0_lu_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg0_lu_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_cnt3_u; + +/* Define the union csr_smeg0_lu_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 num_in_result_fifo : 5; /* [4:0] */ + u32 num_in_original_fifo : 5; /* [9:5] */ + u32 rsv_9 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg0_lu_ctp_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smeg0_lu_version_u smeg0_lu_version; /* 0 */ + volatile csr_smeg0_lu_chk_enable_cfg_u smeg0_lu_chk_enable_cfg; /* 4 */ + volatile csr_smeg0_lu_int_vector_u smeg0_lu_int_vector; /* 8 */ + volatile csr_smeg0_lu_int_u smeg0_lu_int; /* C */ + volatile csr_smeg0_lu_int_mask_u smeg0_lu_int_mask; /* 10 */ + volatile csr_smeg0_lu_pipe0_mem_ecc_crt_err_u smeg0_lu_pipe0_mem_ecc_crt_err; /* 14 */ + volatile csr_smeg0_lu_pipe0_mem_ecc_uncrt_err_u smeg0_lu_pipe0_mem_ecc_uncrt_err; /* 18 */ + volatile csr_smeg0_lu_pipe1_mem_ecc_crt_err_u smeg0_lu_pipe1_mem_ecc_crt_err; /* 1C */ + volatile csr_smeg0_lu_pipe1_mem_ecc_uncrt_err_u smeg0_lu_pipe1_mem_ecc_uncrt_err; /* 20 */ + volatile csr_smeg0_lu_flitfifo_mem_ecc_crt_err_u smeg0_lu_flitfifo_mem_ecc_crt_err; /* 24 */ + volatile csr_smeg0_lu_flitfifo_mem_ecc_uncrt_err_u smeg0_lu_flitfifo_mem_ecc_uncrt_err; /* 28 */ + volatile csr_smeg0_lu_sw_err_u smeg0_lu_sw_err; /* 2C */ + volatile csr_smeg0_lu_indrect_ctrl_u smeg0_lu_indrect_ctrl; /* 30 */ + volatile csr_smeg0_lu_indrect_timeout_u smeg0_lu_indrect_timeout; /* 34 */ + volatile csr_smeg0_lu_indrect_data_u smeg0_lu_indrect_data; /* 38 */ + volatile csr_smeg0_lu_err_inj_cfg_u smeg0_lu_err_inj_cfg; /* 3C */ + volatile csr_smeg0_lu_cnt_cfg_u smeg0_lu_cnt_cfg; /* 40 */ + volatile csr_smeg0_lu_cnt0_u smeg0_lu_cnt0; /* 44 */ + volatile csr_smeg0_lu_cnt1_u smeg0_lu_cnt1; /* 48 */ + volatile csr_smeg0_lu_cnt2_u smeg0_lu_cnt2; /* 4C */ + volatile csr_smeg0_lu_cnt3_u smeg0_lu_cnt3; /* 50 */ + volatile csr_smeg0_lu_ctp_u smeg0_lu_ctp; /* 54 */ +} S_smeg0_lu_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smeg0_lu_csr */ +extern volatile S_smeg0_lu_csr_REGS_TYPE *gopsmeg0_lu_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMEG0_LU_VERSION_smeg0_lu_version(unsigned int usmeg0_lu_version); +int iSetSMEG0_LU_CHK_ENABLE_CFG_flit_fifo_chk_enable(unsigned int uflit_fifo_chk_enable); +int iSetSMEG0_LU_CHK_ENABLE_CFG_pipe1_mem_chk_enable(unsigned int upipe1_mem_chk_enable); +int iSetSMEG0_LU_CHK_ENABLE_CFG_pipe0_mem_chk_enable(unsigned int upipe0_mem_chk_enable); +int iSetSMEG0_LU_CHK_ENABLE_CFG_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMEG0_LU_CHK_ENABLE_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMEG0_LU_CHK_ENABLE_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMEG0_LU_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMEG0_LU_INT_VECTOR_enable(unsigned int uenable); +int iSetSMEG0_LU_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMEG0_LU_INT_int_data(unsigned int uint_data); +int iSetSMEG0_LU_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG0_LU_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMEG0_LU_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_PIPE0_MEM_ECC_CRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_PIPE0_MEM_ECC_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_PIPE1_MEM_ECC_CRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_PIPE1_MEM_ECC_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_CRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_FLITFIFO_MEM_ECC_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_SW_ERR_err(unsigned int uerr); +int iSetSMEG0_LU_SW_ERR_multi_err(unsigned int umulti_err); +int iSetSMEG0_LU_SW_ERR_sticky(unsigned int usticky); +int iSetSMEG0_LU_INDRECT_CTRL_smeg0_lu_indir_addr(unsigned int usmeg0_lu_indir_addr); +int iSetSMEG0_LU_INDRECT_CTRL_smeg0_lu_indir_tab(unsigned int usmeg0_lu_indir_tab); +int iSetSMEG0_LU_INDRECT_CTRL_smeg0_lu_indir_stat(unsigned int usmeg0_lu_indir_stat); +int iSetSMEG0_LU_INDRECT_CTRL_smeg0_lu_indir_mode(unsigned int usmeg0_lu_indir_mode); +int iSetSMEG0_LU_INDRECT_CTRL_smeg0_lu_indir_vld(unsigned int usmeg0_lu_indir_vld); +int iSetSMEG0_LU_INDRECT_TIMEOUT_smeg0_lu_indir_timeout(unsigned int usmeg0_lu_indir_timeout); +int iSetSMEG0_LU_INDRECT_DATA_smeg0_lu_indir_data(unsigned int usmeg0_lu_indir_data); +int iSetSMEG0_LU_ERR_INJ_CFG_pipe0_crt_err_inj_req(unsigned int upipe0_crt_err_inj_req); +int iSetSMEG0_LU_ERR_INJ_CFG_pipe0_uncrt_err_inj_req(unsigned int upipe0_uncrt_err_inj_req); +int iSetSMEG0_LU_ERR_INJ_CFG_pipe1_crt_err_inj_req(unsigned int upipe1_crt_err_inj_req); +int iSetSMEG0_LU_ERR_INJ_CFG_pipe1_uncrt_err_inj_req(unsigned int upipe1_uncrt_err_inj_req); +int iSetSMEG0_LU_ERR_INJ_CFG_flitf_crt_err_inj_req(unsigned int uflitf_crt_err_inj_req); +int iSetSMEG0_LU_ERR_INJ_CFG_flitf_uncrt_err_inj_req(unsigned int uflitf_uncrt_err_inj_req); +int iSetSMEG0_LU_CNT_CFG_cnt_enable(unsigned int ucnt_enable); +int iSetSMEG0_LU_CNT_CFG_cnt0_event_sel(unsigned int ucnt0_event_sel); +int iSetSMEG0_LU_CNT_CFG_cnt1_event_sel(unsigned int ucnt1_event_sel); +int iSetSMEG0_LU_CNT_CFG_cnt2_event_sel(unsigned int ucnt2_event_sel); +int iSetSMEG0_LU_CNT_CFG_cnt3_event_sel(unsigned int ucnt3_event_sel); +int iSetSMEG0_LU_CNT_CFG_eng_event_grp(unsigned int ueng_event_grp); +int iSetSMEG0_LU_CNT0_smeg0_lu_cnt0(unsigned int usmeg0_lu_cnt0); +int iSetSMEG0_LU_CNT1_smeg0_lu_cnt1(unsigned int usmeg0_lu_cnt1); +int iSetSMEG0_LU_CNT2_smeg0_lu_cnt2(unsigned int usmeg0_lu_cnt2); +int iSetSMEG0_LU_CNT3_smeg0_lu_cnt3(unsigned int usmeg0_lu_cnt3); +int iSetSMEG0_LU_CTP_num_in_result_fifo(unsigned int unum_in_result_fifo); +int iSetSMEG0_LU_CTP_num_in_original_fifo(unsigned int unum_in_original_fifo); + +/* Define the union csr_smeg1_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_version_u; + +/* Define the union csr_smeg1_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 detect_runaway_thread : 1; /* [0] */ + u32 preload_fairness : 1; /* [1] */ + u32 premem_count : 4; /* [5:2] */ + u32 halt_sw_err : 1; /* [6] */ + u32 halt_on_ebit : 1; /* [7] */ + u32 halt_sw_err1 : 1; /* [8] */ + u32 ctp_active_bits : 1; /* [9] */ + u32 halt_on_runaway_err : 1; /* [10] */ + u32 tcd_thd_id : 6; /* [16:11] */ + u32 msb_thread_cfg : 1; /* [17] */ + u32 mem_chk_en : 1; /* [18] */ + u32 rp_inlld_ll_ivld_en : 1; /* [19] */ + u32 bt_inst_id : 6; /* [25:20] */ + u32 rp_halt_thread_max_num : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_cfg0_u; + +/* Define the union csr_smeg1_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tp_ram_tmod : 8; /* [7:0] */ + u32 sp_ram_tmod : 7; /* [14:8] */ + u32 mem_ret1n : 1; /* [15] */ + u32 rp_crt_err_inj_req : 1; /* [16] */ + u32 rp_uncrt_err_inj_req : 1; /* [17] */ + u32 fidr_crt_err_inj_req : 1; /* [18] */ + u32 fidr_uncrt_err_inj_req : 1; /* [19] */ + u32 rsv_0 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_cfg1_u; + +/* Define the union csr_smeg1_runaway_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_runaway_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_runaway_cfg_u; + +/* Define the union csr_smeg1_thread_enable_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_thread_enable_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_thread_enable_cfg_u; + +/* Define the union csr_smeg1_tm_ts_fast2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_ts_fast2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_ts_fast2_u; + +/* Define the union csr_smeg1_tm_ts_fast3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_ts_fast3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_ts_fast3_u; + +/* Define the union csr_smeg1_tm_ts_slow0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_ts_slow0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_ts_slow0_u; + +/* Define the union csr_smeg1_tm_ts_slow1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_ts_slow1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_ts_slow1_u; + +/* Define the union csr_smeg1_tm_tmt_cfg7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt28 : 8; /* [7:0] */ + u32 smeg1_tm_tmt29 : 8; /* [15:8] */ + u32 smeg1_tm_tmt30 : 8; /* [23:16] */ + u32 smeg1_tm_tmt31 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg7_u; + +/* Define the union csr_smeg1_tm_tmt_cfg6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt24 : 8; /* [7:0] */ + u32 smeg1_tm_tmt25 : 8; /* [15:8] */ + u32 smeg1_tm_tmt26 : 8; /* [23:16] */ + u32 smeg1_tm_tmt27 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg6_u; + +/* Define the union csr_smeg1_tm_tmt_cfg5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt20 : 8; /* [7:0] */ + u32 smeg1_tm_tmt21 : 8; /* [15:8] */ + u32 smeg1_tm_tmt22 : 8; /* [23:16] */ + u32 smeg1_tm_tmt23 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg5_u; + +/* Define the union csr_smeg1_tm_tmt_cfg4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt16 : 8; /* [7:0] */ + u32 smeg1_tm_tmt17 : 8; /* [15:8] */ + u32 smeg1_tm_tmt18 : 8; /* [23:16] */ + u32 smeg1_tm_tmt19 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg4_u; + +/* Define the union csr_smeg1_tm_tmt_cfg3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt12 : 8; /* [7:0] */ + u32 smeg1_tm_tmt13 : 8; /* [15:8] */ + u32 smeg1_tm_tmt14 : 8; /* [23:16] */ + u32 smeg1_tm_tmt15 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg3_u; + +/* Define the union csr_smeg1_tm_tmt_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt8 : 8; /* [7:0] */ + u32 smeg1_tm_tmt9 : 8; /* [15:8] */ + u32 smeg1_tm_tmt10 : 8; /* [23:16] */ + u32 smeg1_tm_tmt11 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg2_u; + +/* Define the union csr_smeg1_tm_tmt_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt4 : 8; /* [7:0] */ + u32 smeg1_tm_tmt5 : 8; /* [15:8] */ + u32 smeg1_tm_tmt6 : 8; /* [23:16] */ + u32 smeg1_tm_tmt7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg1_u; + +/* Define the union csr_smeg1_tm_tmt_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tm_tmt0 : 8; /* [7:0] */ + u32 smeg1_tm_tmt1 : 8; /* [15:8] */ + u32 smeg1_tm_tmt2 : 8; /* [23:16] */ + u32 smeg1_tm_tmt3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tm_tmt_cfg0_u; + +/* Define the union csr_smeg1_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_1 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_2 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_int_vector_u; + +/* Define the union csr_smeg1_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 3; /* [2:0] */ + u32 rsv_3 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_int_u; + +/* Define the union csr_smeg1_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 3; /* [2:0] */ + u32 rsv_4 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_int_mask_u; + +/* Define the union csr_smeg1_engine_sw_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_engine_sw_err_u; + +/* Define the union csr_smeg1_err0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_crt_err0 : 1; /* [0] */ + u32 ecc_crt_merr0 : 1; /* [1] */ + u32 ecc_crt_err1 : 1; /* [2] */ + u32 ecc_crt_merr1 : 1; /* [3] */ + u32 ecc_crt_err2 : 1; /* [4] */ + u32 ecc_crt_merr2 : 1; /* [5] */ + u32 ecc_crt_err3 : 1; /* [6] */ + u32 ecc_crt_merr3 : 1; /* [7] */ + u32 ecc_crt_err4 : 1; /* [8] */ + u32 ecc_crt_merr4 : 1; /* [9] */ + u32 ecc_crt_err5 : 1; /* [10] */ + u32 ecc_crt_merr5 : 1; /* [11] */ + u32 ecc_crt_err6 : 1; /* [12] */ + u32 ecc_crt_merr6 : 1; /* [13] */ + u32 ecc_crt_err7 : 1; /* [14] */ + u32 ecc_crt_merr7 : 1; /* [15] */ + u32 runaway_err : 1; /* [16] */ + u32 runaway_merr : 1; /* [17] */ + u32 ecc_crt_err8 : 1; /* [18] */ + u32 ecc_crt_merr8 : 1; /* [19] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_err0_u; + +/* Define the union csr_smeg1_err0_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_crt_err_mask0 : 1; /* [0] */ + u32 ecc_crt_err_mask1 : 1; /* [1] */ + u32 ecc_crt_err_mask2 : 1; /* [2] */ + u32 ecc_crt_err_mask3 : 1; /* [3] */ + u32 ecc_crt_err_mask4 : 1; /* [4] */ + u32 ecc_crt_err_mask5 : 1; /* [5] */ + u32 ecc_crt_err_mask6 : 1; /* [6] */ + u32 ecc_crt_err_mask7 : 1; /* [7] */ + u32 runaway_err_mask : 1; /* [8] */ + u32 ecc_crt_err_mask8 : 1; /* [9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_err0_mask_u; + +/* Define the union csr_smeg1_err1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_uncrt_err0 : 1; /* [0] */ + u32 ecc_uncrt_merr0 : 1; /* [1] */ + u32 ecc_uncrt_err1 : 1; /* [2] */ + u32 ecc_uncrt_merr1 : 1; /* [3] */ + u32 ecc_uncrt_err2 : 1; /* [4] */ + u32 ecc_uncrt_merr2 : 1; /* [5] */ + u32 ecc_uncrt_err3 : 1; /* [6] */ + u32 ecc_uncrt_merr3 : 1; /* [7] */ + u32 ecc_uncrt_err4 : 1; /* [8] */ + u32 ecc_uncrt_merr4 : 1; /* [9] */ + u32 ecc_uncrt_err5 : 1; /* [10] */ + u32 ecc_uncrt_merr5 : 1; /* [11] */ + u32 ecc_uncrt_err6 : 1; /* [12] */ + u32 ecc_uncrt_merr6 : 1; /* [13] */ + u32 ecc_uncrt_err7 : 1; /* [14] */ + u32 ecc_uncrt_merr7 : 1; /* [15] */ + u32 ecc_uncrt_err8 : 1; /* [16] */ + u32 ecc_uncrt_merr8 : 1; /* [17] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_err1_u; + +/* Define the union csr_smeg1_err1_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_uncrt_err_mask0 : 1; /* [0] */ + u32 ecc_uncrt_err_mask1 : 1; /* [1] */ + u32 ecc_uncrt_err_mask2 : 1; /* [2] */ + u32 ecc_uncrt_err_mask3 : 1; /* [3] */ + u32 ecc_uncrt_err_mask4 : 1; /* [4] */ + u32 ecc_uncrt_err_mask5 : 1; /* [5] */ + u32 ecc_uncrt_err_mask6 : 1; /* [6] */ + u32 ecc_uncrt_err_mask7 : 1; /* [7] */ + u32 ecc_uncrt_err_mask8 : 1; /* [8] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_err1_mask_u; + +/* Define the union csr_smeg1_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_indir_addr : 24; /* [23:0] */ + u32 smeg1_indir_tab : 4; /* [27:24] */ + u32 smeg1_indir_stat : 2; /* [29:28] */ + u32 smeg1_indir_mode : 1; /* [30] */ + u32 smeg1_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_indrect_ctrl_u; + +/* Define the union csr_smeg1_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_indrect_timeout_u; + +/* Define the union csr_smeg1_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_indrect_data_u; + +/* Define the union csr_smeg1_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_enable : 1; /* [0] */ + u32 cnt1_enable : 1; /* [1] */ + u32 cnt2_enable : 1; /* [2] */ + u32 cnt3_enable : 1; /* [3] */ + u32 cnt0_match_en : 1; /* [4] */ + u32 cnt1_match_en : 1; /* [5] */ + u32 cnt2_match_en : 1; /* [6] */ + u32 cnt3_match_en : 1; /* [7] */ + u32 cnt0_sel : 1; /* [8] */ + u32 cnt1_sel : 2; /* [10:9] */ + u32 cnt2_sel : 1; /* [11] */ + u32 cnt3_sel : 1; /* [12] */ + u32 rsv_5 : 19; /* [31:13] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_cnt_cfg_u; + +/* Define the union csr_smeg1_cnt_match_id_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_match_id : 6; /* [5:0] */ + u32 cnt1_match_id : 6; /* [11:6] */ + u32 cnt2_match_id : 6; /* [17:12] */ + u32 cnt3_match_id : 6; /* [23:18] */ + u32 rsv_6 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_cnt_match_id_u; + +/* Define the union csr_smeg1_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smeg1_cnt0 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_cnt0_u; + +/* Define the union csr_smeg1_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smeg1_cnt1 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_cnt1_u; + +/* Define the union csr_smeg1_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smeg1_cnt2 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_cnt2_u; + +/* Define the union csr_smeg1_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smeg1_cnt3 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_cnt3_u; + +/* Define the union csr_rsv_1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_7 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_1_u; + +/* Define the union csr_rsv_2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_8 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_2_u; + +/* Define the union csr_smeg1_thread_enable_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_thread_enable_cfg2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_thread_enable_cfg2_u; + +/* Define the union csr_rsv_3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_9 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_3_u; + +/* Define the union csr_rsv_4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_10 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_4_u; + +/* Define the union csr_rsv_5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_11 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_5_u; + +/* Define the union csr_rsv_6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_12 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_6_u; + +/* Define the union csr_smeg1_tmt_ext_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smeg1_tmt_ext_cfg : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_tmt_ext_cfg_u; + +/* Define the union csr_smeg1_mem_ecc_err_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 flag : 9; /* [8:0] */ + u32 rsv_13 : 7; /* [15:9] */ + u32 addr : 7; /* [22:16] */ + u32 rsv_14 : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_mem_ecc_err_ctp_u; + +/* Define the union csr_smmc_cache_resource_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 sq_cnt : 14; /* [13:0] */ + u32 rsv_15 : 2; /* [15:14] */ + u32 rq_cnt : 14; /* [29:16] */ + u32 rsv_16 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_cache_resource_ctp_u; + +/* Define the union csr_smeg1_sync_api_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 snapshot_eng_id : 5; /* [4:0] */ + u32 snapshot_eng_en : 1; /* [5] */ + u32 rsv_17 : 2; /* [7:6] */ + u32 sync_cnt_threshold : 2; /* [9:8] */ + u32 rsv_18 : 22; /* [31:10] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_sync_api_cfg_u; + +/* Define the union csr_rsv_183_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_19 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_rsv_183_u; + +/* Define the union csr_smeg1_cur_timestamp_us_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 ctp : 49; /* [48:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_cur_timestamp_us_u; + +/* Define the union csr_smeg1_runaway_thd_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 ctp : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_runaway_thd_ctp_u; + +/* Define the union csr_smeg1_ctp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 active_runaway_thd : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_ctp0_u; + +/* Define the union csr_smeg1_ctp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smeg1_internal : 44; /* [43:0] */ + u64 rsv_20 : 20; /* [63:44] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_ctp1_u; + +/* Define the union csr_smeg1_ctp2_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 wt_runaway : 64; /* [63:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smeg1_ctp2_u; + +/* Define the union csr_smeg1_ctp3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tcd : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smeg1_ctp3_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smeg1_version_u smeg1_version; /* 0 */ + volatile csr_smeg1_cfg0_u smeg1_cfg0; /* 4 */ + volatile csr_smeg1_cfg1_u smeg1_cfg1; /* 8 */ + volatile csr_smeg1_runaway_cfg_u smeg1_runaway_cfg; /* C */ + volatile csr_smeg1_thread_enable_cfg_u smeg1_thread_enable_cfg; /* 10 */ + volatile csr_smeg1_tm_ts_fast2_u smeg1_tm_ts_fast2; /* 14 */ + volatile csr_smeg1_tm_ts_fast3_u smeg1_tm_ts_fast3; /* 18 */ + volatile csr_smeg1_tm_ts_slow0_u smeg1_tm_ts_slow0; /* 1C */ + volatile csr_smeg1_tm_ts_slow1_u smeg1_tm_ts_slow1; /* 20 */ + volatile csr_smeg1_tm_tmt_cfg7_u smeg1_tm_tmt_cfg7; /* 24 */ + volatile csr_smeg1_tm_tmt_cfg6_u smeg1_tm_tmt_cfg6; /* 28 */ + volatile csr_smeg1_tm_tmt_cfg5_u smeg1_tm_tmt_cfg5; /* 2C */ + volatile csr_smeg1_tm_tmt_cfg4_u smeg1_tm_tmt_cfg4; /* 30 */ + volatile csr_smeg1_tm_tmt_cfg3_u smeg1_tm_tmt_cfg3; /* 34 */ + volatile csr_smeg1_tm_tmt_cfg2_u smeg1_tm_tmt_cfg2; /* 38 */ + volatile csr_smeg1_tm_tmt_cfg1_u smeg1_tm_tmt_cfg1; /* 3C */ + volatile csr_smeg1_tm_tmt_cfg0_u smeg1_tm_tmt_cfg0; /* 40 */ + volatile csr_smeg1_int_vector_u smeg1_int_vector; /* 44 */ + volatile csr_smeg1_int_u smeg1_int; /* 48 */ + volatile csr_smeg1_int_mask_u smeg1_int_mask; /* 4C */ + volatile csr_smeg1_engine_sw_err_u smeg1_engine_sw_err; /* 50 */ + volatile csr_smeg1_err0_u smeg1_err0; /* 54 */ + volatile csr_smeg1_err0_mask_u smeg1_err0_mask; /* 58 */ + volatile csr_smeg1_err1_u smeg1_err1; /* 5C */ + volatile csr_smeg1_err1_mask_u smeg1_err1_mask; /* 60 */ + volatile csr_smeg1_indrect_ctrl_u smeg1_indrect_ctrl; /* 64 */ + volatile csr_smeg1_indrect_timeout_u smeg1_indrect_timeout; /* 68 */ + volatile csr_smeg1_indrect_data_u smeg1_indrect_data; /* 6C */ + volatile csr_smeg1_cnt_cfg_u smeg1_cnt_cfg; /* 70 */ + volatile csr_smeg1_cnt_match_id_u smeg1_cnt_match_id; /* 74 */ + volatile csr_smeg1_cnt0_u smeg1_cnt0; /* 78 */ + volatile csr_smeg1_cnt1_u smeg1_cnt1; /* 80 */ + volatile csr_smeg1_cnt2_u smeg1_cnt2; /* 88 */ + volatile csr_smeg1_cnt3_u smeg1_cnt3; /* 90 */ + volatile csr_rsv_1_u rsv_1; /* 98 */ + volatile csr_rsv_2_u rsv_2; /* 9C */ + volatile csr_smeg1_thread_enable_cfg2_u smeg1_thread_enable_cfg2; /* A0 */ + volatile csr_rsv_3_u rsv_3; /* A4 */ + volatile csr_rsv_4_u rsv_4; /* A8 */ + volatile csr_rsv_5_u rsv_5; /* AC */ + volatile csr_rsv_6_u rsv_6; /* B0 */ + volatile csr_smeg1_tmt_ext_cfg_u smeg1_tmt_ext_cfg; /* B4 */ + volatile csr_smeg1_mem_ecc_err_ctp_u smeg1_mem_ecc_err_ctp; /* B8 */ + volatile csr_smmc_cache_resource_ctp_u smmc_cache_resource_ctp; /* BC */ + volatile csr_smeg1_sync_api_cfg_u smeg1_sync_api_cfg; /* C0 */ + volatile csr_rsv_183_u rsv_183; /* C4 */ + volatile csr_smeg1_cur_timestamp_us_u smeg1_cur_timestamp_us; /* C8 */ + volatile csr_smeg1_runaway_thd_ctp_u smeg1_runaway_thd_ctp; /* D0 */ + volatile csr_smeg1_ctp0_u smeg1_ctp0; /* D8 */ + volatile csr_smeg1_ctp1_u smeg1_ctp1; /* E0 */ + volatile csr_smeg1_ctp2_u smeg1_ctp2; /* E8 */ + volatile csr_smeg1_ctp3_u smeg1_ctp3; /* F0 */ +} S_smeg1_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smeg1_csr */ +extern volatile S_smeg1_csr_REGS_TYPE *gopsmeg1_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMEG1_VERSION_smeg1_version(unsigned int usmeg1_version); +int iSetSMEG1_CFG0_detect_runaway_thread(unsigned int udetect_runaway_thread); +int iSetSMEG1_CFG0_preload_fairness(unsigned int upreload_fairness); +int iSetSMEG1_CFG0_premem_count(unsigned int upremem_count); +int iSetSMEG1_CFG0_halt_sw_err(unsigned int uhalt_sw_err); +int iSetSMEG1_CFG0_halt_on_ebit(unsigned int uhalt_on_ebit); +int iSetSMEG1_CFG0_halt_sw_err1(unsigned int uhalt_sw_err1); +int iSetSMEG1_CFG0_ctp_active_bits(unsigned int uctp_active_bits); +int iSetSMEG1_CFG0_halt_on_runaway_err(unsigned int uhalt_on_runaway_err); +int iSetSMEG1_CFG0_tcd_thd_id(unsigned int utcd_thd_id); +int iSetSMEG1_CFG0_msb_thread_cfg(unsigned int umsb_thread_cfg); +int iSetSMEG1_CFG0_mem_chk_en(unsigned int umem_chk_en); +int iSetSMEG1_CFG0_rp_inlld_ll_ivld_en(unsigned int urp_inlld_ll_ivld_en); +int iSetSMEG1_CFG0_bt_inst_id(unsigned int ubt_inst_id); +int iSetSMEG1_CFG0_rp_halt_thread_max_num(unsigned int urp_halt_thread_max_num); +int iSetSMEG1_CFG1_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMEG1_CFG1_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMEG1_CFG1_mem_ret1n(unsigned int umem_ret1n); +int iSetSMEG1_CFG1_rp_crt_err_inj_req(unsigned int urp_crt_err_inj_req); +int iSetSMEG1_CFG1_rp_uncrt_err_inj_req(unsigned int urp_uncrt_err_inj_req); +int iSetSMEG1_CFG1_fidr_crt_err_inj_req(unsigned int ufidr_crt_err_inj_req); +int iSetSMEG1_CFG1_fidr_uncrt_err_inj_req(unsigned int ufidr_uncrt_err_inj_req); +int iSetSMEG1_RUNAWAY_CFG_smeg1_runaway_cfg(unsigned int usmeg1_runaway_cfg); +int iSetSMEG1_THREAD_ENABLE_CFG_smeg1_thread_enable_cfg(unsigned int usmeg1_thread_enable_cfg); +int iSetSMEG1_TM_TS_FAST2_smeg1_tm_ts_fast2(unsigned int usmeg1_tm_ts_fast2); +int iSetSMEG1_TM_TS_FAST3_smeg1_tm_ts_fast3(unsigned int usmeg1_tm_ts_fast3); +int iSetSMEG1_TM_TS_SLOW0_smeg1_tm_ts_slow0(unsigned int usmeg1_tm_ts_slow0); +int iSetSMEG1_TM_TS_SLOW1_smeg1_tm_ts_slow1(unsigned int usmeg1_tm_ts_slow1); +int iSetSMEG1_TM_TMT_CFG7_smeg1_tm_tmt28(unsigned int usmeg1_tm_tmt28); +int iSetSMEG1_TM_TMT_CFG7_smeg1_tm_tmt29(unsigned int usmeg1_tm_tmt29); +int iSetSMEG1_TM_TMT_CFG7_smeg1_tm_tmt30(unsigned int usmeg1_tm_tmt30); +int iSetSMEG1_TM_TMT_CFG7_smeg1_tm_tmt31(unsigned int usmeg1_tm_tmt31); +int iSetSMEG1_TM_TMT_CFG6_smeg1_tm_tmt24(unsigned int usmeg1_tm_tmt24); +int iSetSMEG1_TM_TMT_CFG6_smeg1_tm_tmt25(unsigned int usmeg1_tm_tmt25); +int iSetSMEG1_TM_TMT_CFG6_smeg1_tm_tmt26(unsigned int usmeg1_tm_tmt26); +int iSetSMEG1_TM_TMT_CFG6_smeg1_tm_tmt27(unsigned int usmeg1_tm_tmt27); +int iSetSMEG1_TM_TMT_CFG5_smeg1_tm_tmt20(unsigned int usmeg1_tm_tmt20); +int iSetSMEG1_TM_TMT_CFG5_smeg1_tm_tmt21(unsigned int usmeg1_tm_tmt21); +int iSetSMEG1_TM_TMT_CFG5_smeg1_tm_tmt22(unsigned int usmeg1_tm_tmt22); +int iSetSMEG1_TM_TMT_CFG5_smeg1_tm_tmt23(unsigned int usmeg1_tm_tmt23); +int iSetSMEG1_TM_TMT_CFG4_smeg1_tm_tmt16(unsigned int usmeg1_tm_tmt16); +int iSetSMEG1_TM_TMT_CFG4_smeg1_tm_tmt17(unsigned int usmeg1_tm_tmt17); +int iSetSMEG1_TM_TMT_CFG4_smeg1_tm_tmt18(unsigned int usmeg1_tm_tmt18); +int iSetSMEG1_TM_TMT_CFG4_smeg1_tm_tmt19(unsigned int usmeg1_tm_tmt19); +int iSetSMEG1_TM_TMT_CFG3_smeg1_tm_tmt12(unsigned int usmeg1_tm_tmt12); +int iSetSMEG1_TM_TMT_CFG3_smeg1_tm_tmt13(unsigned int usmeg1_tm_tmt13); +int iSetSMEG1_TM_TMT_CFG3_smeg1_tm_tmt14(unsigned int usmeg1_tm_tmt14); +int iSetSMEG1_TM_TMT_CFG3_smeg1_tm_tmt15(unsigned int usmeg1_tm_tmt15); +int iSetSMEG1_TM_TMT_CFG2_smeg1_tm_tmt8(unsigned int usmeg1_tm_tmt8); +int iSetSMEG1_TM_TMT_CFG2_smeg1_tm_tmt9(unsigned int usmeg1_tm_tmt9); +int iSetSMEG1_TM_TMT_CFG2_smeg1_tm_tmt10(unsigned int usmeg1_tm_tmt10); +int iSetSMEG1_TM_TMT_CFG2_smeg1_tm_tmt11(unsigned int usmeg1_tm_tmt11); +int iSetSMEG1_TM_TMT_CFG1_smeg1_tm_tmt4(unsigned int usmeg1_tm_tmt4); +int iSetSMEG1_TM_TMT_CFG1_smeg1_tm_tmt5(unsigned int usmeg1_tm_tmt5); +int iSetSMEG1_TM_TMT_CFG1_smeg1_tm_tmt6(unsigned int usmeg1_tm_tmt6); +int iSetSMEG1_TM_TMT_CFG1_smeg1_tm_tmt7(unsigned int usmeg1_tm_tmt7); +int iSetSMEG1_TM_TMT_CFG0_smeg1_tm_tmt0(unsigned int usmeg1_tm_tmt0); +int iSetSMEG1_TM_TMT_CFG0_smeg1_tm_tmt1(unsigned int usmeg1_tm_tmt1); +int iSetSMEG1_TM_TMT_CFG0_smeg1_tm_tmt2(unsigned int usmeg1_tm_tmt2); +int iSetSMEG1_TM_TMT_CFG0_smeg1_tm_tmt3(unsigned int usmeg1_tm_tmt3); +int iSetSMEG1_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMEG1_INT_VECTOR_enable(unsigned int uenable); +int iSetSMEG1_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMEG1_INT_int_data(unsigned int uint_data); +int iSetSMEG1_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG1_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMEG1_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMEG1_ENGINE_SW_ERR_error_bit(unsigned int uerror_bit); +int iSetSMEG1_ENGINE_SW_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMEG1_ENGINE_SW_ERR_sticky(unsigned int usticky); +int iSetSMEG1_ERR0_ecc_crt_err0(unsigned int uecc_crt_err0); +int iSetSMEG1_ERR0_ecc_crt_merr0(unsigned int uecc_crt_merr0); +int iSetSMEG1_ERR0_ecc_crt_err1(unsigned int uecc_crt_err1); +int iSetSMEG1_ERR0_ecc_crt_merr1(unsigned int uecc_crt_merr1); +int iSetSMEG1_ERR0_ecc_crt_err2(unsigned int uecc_crt_err2); +int iSetSMEG1_ERR0_ecc_crt_merr2(unsigned int uecc_crt_merr2); +int iSetSMEG1_ERR0_ecc_crt_err3(unsigned int uecc_crt_err3); +int iSetSMEG1_ERR0_ecc_crt_merr3(unsigned int uecc_crt_merr3); +int iSetSMEG1_ERR0_ecc_crt_err4(unsigned int uecc_crt_err4); +int iSetSMEG1_ERR0_ecc_crt_merr4(unsigned int uecc_crt_merr4); +int iSetSMEG1_ERR0_ecc_crt_err5(unsigned int uecc_crt_err5); +int iSetSMEG1_ERR0_ecc_crt_merr5(unsigned int uecc_crt_merr5); +int iSetSMEG1_ERR0_ecc_crt_err6(unsigned int uecc_crt_err6); +int iSetSMEG1_ERR0_ecc_crt_merr6(unsigned int uecc_crt_merr6); +int iSetSMEG1_ERR0_ecc_crt_err7(unsigned int uecc_crt_err7); +int iSetSMEG1_ERR0_ecc_crt_merr7(unsigned int uecc_crt_merr7); +int iSetSMEG1_ERR0_runaway_err(unsigned int urunaway_err); +int iSetSMEG1_ERR0_runaway_merr(unsigned int urunaway_merr); +int iSetSMEG1_ERR0_ecc_crt_err8(unsigned int uecc_crt_err8); +int iSetSMEG1_ERR0_ecc_crt_merr8(unsigned int uecc_crt_merr8); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask0(unsigned int uecc_crt_err_mask0); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask1(unsigned int uecc_crt_err_mask1); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask2(unsigned int uecc_crt_err_mask2); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask3(unsigned int uecc_crt_err_mask3); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask4(unsigned int uecc_crt_err_mask4); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask5(unsigned int uecc_crt_err_mask5); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask6(unsigned int uecc_crt_err_mask6); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask7(unsigned int uecc_crt_err_mask7); +int iSetSMEG1_ERR0_MASK_runaway_err_mask(unsigned int urunaway_err_mask); +int iSetSMEG1_ERR0_MASK_ecc_crt_err_mask8(unsigned int uecc_crt_err_mask8); +int iSetSMEG1_ERR1_ecc_uncrt_err0(unsigned int uecc_uncrt_err0); +int iSetSMEG1_ERR1_ecc_uncrt_merr0(unsigned int uecc_uncrt_merr0); +int iSetSMEG1_ERR1_ecc_uncrt_err1(unsigned int uecc_uncrt_err1); +int iSetSMEG1_ERR1_ecc_uncrt_merr1(unsigned int uecc_uncrt_merr1); +int iSetSMEG1_ERR1_ecc_uncrt_err2(unsigned int uecc_uncrt_err2); +int iSetSMEG1_ERR1_ecc_uncrt_merr2(unsigned int uecc_uncrt_merr2); +int iSetSMEG1_ERR1_ecc_uncrt_err3(unsigned int uecc_uncrt_err3); +int iSetSMEG1_ERR1_ecc_uncrt_merr3(unsigned int uecc_uncrt_merr3); +int iSetSMEG1_ERR1_ecc_uncrt_err4(unsigned int uecc_uncrt_err4); +int iSetSMEG1_ERR1_ecc_uncrt_merr4(unsigned int uecc_uncrt_merr4); +int iSetSMEG1_ERR1_ecc_uncrt_err5(unsigned int uecc_uncrt_err5); +int iSetSMEG1_ERR1_ecc_uncrt_merr5(unsigned int uecc_uncrt_merr5); +int iSetSMEG1_ERR1_ecc_uncrt_err6(unsigned int uecc_uncrt_err6); +int iSetSMEG1_ERR1_ecc_uncrt_merr6(unsigned int uecc_uncrt_merr6); +int iSetSMEG1_ERR1_ecc_uncrt_err7(unsigned int uecc_uncrt_err7); +int iSetSMEG1_ERR1_ecc_uncrt_merr7(unsigned int uecc_uncrt_merr7); +int iSetSMEG1_ERR1_ecc_uncrt_err8(unsigned int uecc_uncrt_err8); +int iSetSMEG1_ERR1_ecc_uncrt_merr8(unsigned int uecc_uncrt_merr8); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask0(unsigned int uecc_uncrt_err_mask0); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask1(unsigned int uecc_uncrt_err_mask1); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask2(unsigned int uecc_uncrt_err_mask2); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask3(unsigned int uecc_uncrt_err_mask3); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask4(unsigned int uecc_uncrt_err_mask4); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask5(unsigned int uecc_uncrt_err_mask5); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask6(unsigned int uecc_uncrt_err_mask6); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask7(unsigned int uecc_uncrt_err_mask7); +int iSetSMEG1_ERR1_MASK_ecc_uncrt_err_mask8(unsigned int uecc_uncrt_err_mask8); +int iSetSMEG1_INDRECT_CTRL_smeg1_indir_addr(unsigned int usmeg1_indir_addr); +int iSetSMEG1_INDRECT_CTRL_smeg1_indir_tab(unsigned int usmeg1_indir_tab); +int iSetSMEG1_INDRECT_CTRL_smeg1_indir_stat(unsigned int usmeg1_indir_stat); +int iSetSMEG1_INDRECT_CTRL_smeg1_indir_mode(unsigned int usmeg1_indir_mode); +int iSetSMEG1_INDRECT_CTRL_smeg1_indir_vld(unsigned int usmeg1_indir_vld); +int iSetSMEG1_INDRECT_TIMEOUT_smeg1_indir_timeout(unsigned int usmeg1_indir_timeout); +int iSetSMEG1_INDRECT_DATA_smeg1_indir_data(unsigned int usmeg1_indir_data); +int iSetSMEG1_CNT_CFG_cnt0_enable(unsigned int ucnt0_enable); +int iSetSMEG1_CNT_CFG_cnt1_enable(unsigned int ucnt1_enable); +int iSetSMEG1_CNT_CFG_cnt2_enable(unsigned int ucnt2_enable); +int iSetSMEG1_CNT_CFG_cnt3_enable(unsigned int ucnt3_enable); +int iSetSMEG1_CNT_CFG_cnt0_match_en(unsigned int ucnt0_match_en); +int iSetSMEG1_CNT_CFG_cnt1_match_en(unsigned int ucnt1_match_en); +int iSetSMEG1_CNT_CFG_cnt2_match_en(unsigned int ucnt2_match_en); +int iSetSMEG1_CNT_CFG_cnt3_match_en(unsigned int ucnt3_match_en); +int iSetSMEG1_CNT_CFG_cnt0_sel(unsigned int ucnt0_sel); +int iSetSMEG1_CNT_CFG_cnt1_sel(unsigned int ucnt1_sel); +int iSetSMEG1_CNT_CFG_cnt2_sel(unsigned int ucnt2_sel); +int iSetSMEG1_CNT_CFG_cnt3_sel(unsigned int ucnt3_sel); +int iSetSMEG1_CNT_MATCH_ID_cnt0_match_id(unsigned int ucnt0_match_id); +int iSetSMEG1_CNT_MATCH_ID_cnt1_match_id(unsigned int ucnt1_match_id); +int iSetSMEG1_CNT_MATCH_ID_cnt2_match_id(unsigned int ucnt2_match_id); +int iSetSMEG1_CNT_MATCH_ID_cnt3_match_id(unsigned int ucnt3_match_id); +int iSetSMEG1_CNT0_smeg1_cnt0(unsigned int usmeg1_cnt0); +int iSetSMEG1_CNT1_smeg1_cnt1(unsigned int usmeg1_cnt1); +int iSetSMEG1_CNT2_smeg1_cnt2(unsigned int usmeg1_cnt2); +int iSetSMEG1_CNT3_smeg1_cnt3(unsigned int usmeg1_cnt3); + + +int iSetSMEG1_THREAD_ENABLE_CFG2_smeg1_thread_enable_cfg2(unsigned int usmeg1_thread_enable_cfg2); + + +int iSetSMEG1_TMT_EXT_CFG_smeg1_tmt_ext_cfg(unsigned int usmeg1_tmt_ext_cfg); +int iSetSMEG1_MEM_ECC_ERR_CTP_flag(unsigned int uflag); +int iSetSMEG1_MEM_ECC_ERR_CTP_addr(unsigned int uaddr); +int iSetSMMC_CACHE_RESOURCE_CTP_sq_cnt(unsigned int usq_cnt); +int iSetSMMC_CACHE_RESOURCE_CTP_rq_cnt(unsigned int urq_cnt); +int iSetSMEG1_SYNC_API_CFG_snapshot_eng_id(unsigned int usnapshot_eng_id); +int iSetSMEG1_SYNC_API_CFG_snapshot_eng_en(unsigned int usnapshot_eng_en); +int iSetSMEG1_SYNC_API_CFG_sync_cnt_threshold(unsigned int usync_cnt_threshold); + +int iSetSMEG1_CUR_TIMESTAMP_US_ctp(unsigned int uctp); +int iSetSMEG1_RUNAWAY_THD_CTP_ctp(unsigned int uctp); +int iSetSMEG1_CTP0_active_runaway_thd(unsigned int uactive_runaway_thd); +int iSetSMEG1_CTP1_smeg1_internal(unsigned int usmeg1_internal); +int iSetSMEG1_CTP2_wt_runaway(unsigned int uwt_runaway); +int iSetSMEG1_CTP3_tcd(unsigned int utcd); + +/* Define the union csr_smit_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smit_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_version_u; + +/* Define the union csr_smit_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 dis_oder : 1; /* [0] */ + u32 rsv_0 : 7; /* [7:1] */ + u32 tp_ram_tmod : 8; /* [15:8] */ + u32 mem_ret1n : 1; /* [16] */ + u32 mem_pb_chk_en : 1; /* [17] */ + u32 rp_crt_err_inj_req : 1; /* [18] */ + u32 rp_uncrt_err_inj_req : 1; /* [19] */ + u32 rsv_1 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_cfg_u; + +/* Define the union csr_smit_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_int_vector_u; + +/* Define the union csr_smit_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 3; /* [2:0] */ + u32 rsv_4 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_int_u; + +/* Define the union csr_smit_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 3; /* [2:0] */ + u32 rsv_5 : 13; /* [15:3] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_int_mask_u; + +/* Define the union csr_smit_err_prty_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_err_prty_u; + +/* Define the union csr_smit_mem_ecc_crt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_mem_ecc_crt_err_u; + +/* Define the union csr_smit_mem_ecc_uncrt_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_mem_ecc_uncrt_err_u; + +/* Define the union csr_smit_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smit_indir_addr : 24; /* [23:0] */ + u32 smit_indir_tab : 4; /* [27:24] */ + u32 smit_indir_stat : 2; /* [29:28] */ + u32 smit_indir_mode : 1; /* [30] */ + u32 smit_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_indrect_ctrl_u; + +/* Define the union csr_smit_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smit_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_indrect_timeout_u; + +/* Define the union csr_smit_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smit_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smit_indrect_data_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smit_version_u smit_version; /* 0 */ + volatile csr_smit_cfg_u smit_cfg; /* 4 */ + volatile csr_smit_int_vector_u smit_int_vector; /* 8 */ + volatile csr_smit_int_u smit_int; /* C */ + volatile csr_smit_int_mask_u smit_int_mask; /* 10 */ + volatile csr_smit_err_prty_u smit_err_prty; /* 14 */ + volatile csr_smit_mem_ecc_crt_err_u smit_mem_ecc_crt_err; /* 18 */ + volatile csr_smit_mem_ecc_uncrt_err_u smit_mem_ecc_uncrt_err; /* 1C */ + volatile csr_smit_indrect_ctrl_u smit_indrect_ctrl; /* 20 */ + volatile csr_smit_indrect_timeout_u smit_indrect_timeout; /* 24 */ + volatile csr_smit_indrect_data_u smit_indrect_data; /* 28 */ + volatile csr_cfg_mem_ctrl_bus0_u cfg_mem_ctrl_bus0; /* 2C */ + volatile csr_cfg_mem_ctrl_bus1_u cfg_mem_ctrl_bus1; /* 30 */ + volatile csr_cfg_mem_ctrl_bus2_u cfg_mem_ctrl_bus2; /* 34 */ + volatile csr_cfg_mem_ctrl_bus3_u cfg_mem_ctrl_bus3; /* 38 */ + volatile csr_cfg_mem_ctrl_bus4_u cfg_mem_ctrl_bus4; /* 3C */ +} S_smit_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smit_csr */ +extern volatile S_smit_csr_REGS_TYPE *gopsmit_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMIT_VERSION_smit_version(unsigned int usmit_version); +int iSetSMIT_CFG_dis_oder(unsigned int udis_oder); +int iSetSMIT_CFG_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMIT_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMIT_CFG_mem_pb_chk_en(unsigned int umem_pb_chk_en); +int iSetSMIT_CFG_rp_crt_err_inj_req(unsigned int urp_crt_err_inj_req); +int iSetSMIT_CFG_rp_uncrt_err_inj_req(unsigned int urp_uncrt_err_inj_req); +int iSetSMIT_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMIT_INT_VECTOR_enable(unsigned int uenable); +int iSetSMIT_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMIT_INT_int_data(unsigned int uint_data); +int iSetSMIT_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMIT_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMIT_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMIT_ERR_PRTY_error_bit(unsigned int uerror_bit); +int iSetSMIT_ERR_PRTY_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIT_ERR_PRTY_sticky(unsigned int usticky); +int iSetSMIT_MEM_ECC_CRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIT_MEM_ECC_CRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIT_MEM_ECC_CRT_ERR_sticky(unsigned int usticky); +int iSetSMIT_MEM_ECC_UNCRT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMIT_MEM_ECC_UNCRT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMIT_MEM_ECC_UNCRT_ERR_sticky(unsigned int usticky); +int iSetSMIT_INDRECT_CTRL_smit_indir_addr(unsigned int usmit_indir_addr); +int iSetSMIT_INDRECT_CTRL_smit_indir_tab(unsigned int usmit_indir_tab); +int iSetSMIT_INDRECT_CTRL_smit_indir_stat(unsigned int usmit_indir_stat); +int iSetSMIT_INDRECT_CTRL_smit_indir_mode(unsigned int usmit_indir_mode); +int iSetSMIT_INDRECT_CTRL_smit_indir_vld(unsigned int usmit_indir_vld); +int iSetSMIT_INDRECT_TIMEOUT_smit_indir_timeout(unsigned int usmit_indir_timeout); +int iSetSMIT_INDRECT_DATA_smit_indir_data(unsigned int usmit_indir_data); +int iSetCFG_MEM_CTRL_BUS0_cfg_mem_ctrl_bus0(unsigned int ucfg_mem_ctrl_bus0); +int iSetCFG_MEM_CTRL_BUS1_cfg_mem_ctrl_bus1(unsigned int ucfg_mem_ctrl_bus1); +int iSetCFG_MEM_CTRL_BUS2_cfg_mem_ctrl_bus2(unsigned int ucfg_mem_ctrl_bus2); +int iSetCFG_MEM_CTRL_BUS3_cfg_mem_ctrl_bus3(unsigned int ucfg_mem_ctrl_bus3); +int iSetCFG_MEM_CTRL_BUS4_cfg_mem_ctrl_bus4(unsigned int ucfg_mem_ctrl_bus4); + +/* Define the union csr_smlc_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smlc_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_version_u; + +/* Define the union csr_smlc_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smlc_ecc_chk_en : 1; /* [0] */ + u32 smlc_crt_err_inj : 1; /* [1] */ + u32 smlc_uncrt_err_inj : 1; /* [2] */ + u32 rsv_0 : 5; /* [7:3] */ + u32 tp_ram_tmod : 8; /* [15:8] */ + u32 sp_ram_tmod : 7; /* [22:16] */ + u32 mem_ret1n : 1; /* [23] */ + u32 rsv_1 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_cfg0_u; + +/* Define the union csr_smlc_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bypass_cd_31_0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_cfg1_u; + +/* Define the union csr_smlc_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 bypass_cd_63_32 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_cfg2_u; + +/* Define the union csr_smlc_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_int_vector_u; + +/* Define the union csr_smlc_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 2; /* [1:0] */ + u32 rsv_4 : 14; /* [15:2] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_int_u; + +/* Define the union csr_smlc_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 2; /* [1:0] */ + u32 rsv_5 : 14; /* [15:2] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_int_mask_u; + +/* Define the union csr_smlc_srf_ov_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 1; /* [2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_srf_ov_err_u; + +/* Define the union csr_smlc_rsv_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 rsv_6 : 1; /* [0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_rsv_u; + +/* Define the union csr_smlc_ecc_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fiar_1b_ecc_err : 1; /* [0] */ + u32 fiar_1b_ecc_merr : 1; /* [1] */ + u32 fiar_2b_ecc_err : 1; /* [2] */ + u32 fiar_2b_ecc_merr : 1; /* [3] */ + u32 bat_1b_ecc_err : 1; /* [4] */ + u32 bat_1b_ecc_merr : 1; /* [5] */ + u32 bat_2b_ecc_err : 1; /* [6] */ + u32 bat_2b_ecc_merr : 1; /* [7] */ + u32 stb_1b_ecc_err : 1; /* [8] */ + u32 stb_1b_ecc_merr : 1; /* [9] */ + u32 stb_2b_ecc_err : 1; /* [10] */ + u32 stb_2b_ecc_merr : 1; /* [11] */ + u32 cdb0_1b_ecc_err : 1; /* [12] */ + u32 cdb0_1b_ecc_merr : 1; /* [13] */ + u32 cdb0_2b_ecc_err : 1; /* [14] */ + u32 cdb0_2b_ecc_merr : 1; /* [15] */ + u32 cdb1_1b_ecc_err : 1; /* [16] */ + u32 cdb1_1b_ecc_merr : 1; /* [17] */ + u32 cdb1_2b_ecc_err : 1; /* [18] */ + u32 cdb1_2b_ecc_merr : 1; /* [19] */ + u32 pab_1b_ecc_err : 1; /* [20] */ + u32 pab_1b_ecc_merr : 1; /* [21] */ + u32 pab_2b_ecc_err : 1; /* [22] */ + u32 pab_2b_ecc_merr : 1; /* [23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_ecc_err_u; + +/* Define the union csr_smlc_ecc_errpr_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 fiar_1b_ecc_err_mask : 1; /* [0] */ + u32 fiar_2b_ecc_err_mask : 1; /* [1] */ + u32 bat_1b_ecc_err_mask : 1; /* [2] */ + u32 bat_2b_ecc_err_mask : 1; /* [3] */ + u32 stb_1b_ecc_err_mask : 1; /* [4] */ + u32 stb_2b_ecc_err_mask : 1; /* [5] */ + u32 cdb0_1b_ecc_err_mask : 1; /* [6] */ + u32 cdb0_2b_ecc_err_mask : 1; /* [7] */ + u32 cdb1_1b_ecc_err_mask : 1; /* [8] */ + u32 cdb1_2b_ecc_err_mask : 1; /* [9] */ + u32 pab_1b_ecc_err_mask : 1; /* [10] */ + u32 pab_2b_ecc_err_mask : 1; /* [11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_ecc_errpr_mask_u; + +/* Define the union csr_smlc_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smlc_indir_addr : 20; /* [19:0] */ + u32 smlc_indir_tab : 8; /* [27:20] */ + u32 smlc_indir_stat : 2; /* [29:28] */ + u32 smlc_indir_mode : 1; /* [30] */ + u32 smlc_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_indrect_ctrl_u; + +/* Define the union csr_smlc_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smlc_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_indrect_timeout_u; + +/* Define the union csr_smlc_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smlc_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_indrect_data_u; + +/* Define the union csr_smlc_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smlc_cnt0 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smlc_cnt0_u; + +/* Define the union csr_smlc_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smlc_cnt1 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smlc_cnt1_u; + +/* Define the union csr_smlc_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smlc_cnt2 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smlc_cnt2_u; + +/* Define the union csr_smlc_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smlc_cnt3 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smlc_cnt3_u; + +/* Define the union csr_smlc_cnt_cfg0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt_enable : 4; /* [3:0] */ + u32 cnt0_inst_match_enable : 1; /* [4] */ + u32 cnt1_inst_match_enable : 1; /* [5] */ + u32 cnt2_inst_match_enable : 1; /* [6] */ + u32 cnt3_inst_match_enable : 1; /* [7] */ + u32 cnt0_match_inst_id : 6; /* [13:8] */ + u32 cnt1_match_inst_id : 6; /* [19:14] */ + u32 cnt2_match_inst_id : 6; /* [25:20] */ + u32 cnt3_match_inst_id : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_cnt_cfg0_u; + +/* Define the union csr_smlc_cnt_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_event_sel : 4; /* [3:0] */ + u32 cnt1_event_sel : 4; /* [7:4] */ + u32 cnt2_event_sel : 4; /* [11:8] */ + u32 cnt3_event_sel : 4; /* [15:12] */ + u32 rsv_7 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_cnt_cfg1_u; + +/* Define the union csr_smlc_credit_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_credit : 5; /* [4:0] */ + u32 vc_credit : 2; /* [6:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_credit_ctp_u; + +/* Define the union csr_smlc_fifo_depth_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 srf_fifo_depth : 6; /* [5:0] */ + u32 rsv_8 : 4; /* [9:6] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_fifo_depth_ctp_u; + +/* Define the union csr_smlc_ecc_err_ctp_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 ecc_error_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smlc_ecc_err_ctp_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smlc_version_u smlc_version; /* 0 */ + volatile csr_smlc_cfg0_u smlc_cfg0; /* 4 */ + volatile csr_smlc_cfg1_u smlc_cfg1; /* 8 */ + volatile csr_smlc_cfg2_u smlc_cfg2; /* C */ + volatile csr_smlc_int_vector_u smlc_int_vector; /* 10 */ + volatile csr_smlc_int_u smlc_int; /* 14 */ + volatile csr_smlc_int_mask_u smlc_int_mask; /* 18 */ + volatile csr_smlc_srf_ov_err_u smlc_srf_ov_err; /* 1C */ + volatile csr_smlc_rsv_u smlc_rsv; /* 20 */ + volatile csr_smlc_ecc_err_u smlc_ecc_err; /* 24 */ + volatile csr_smlc_ecc_errpr_mask_u smlc_ecc_errpr_mask; /* 28 */ + volatile csr_smlc_indrect_ctrl_u smlc_indrect_ctrl; /* 2C */ + volatile csr_smlc_indrect_timeout_u smlc_indrect_timeout; /* 30 */ + volatile csr_smlc_indrect_data_u smlc_indrect_data; /* 34 */ + volatile csr_smlc_cnt0_u smlc_cnt0; /* 38 */ + volatile csr_smlc_cnt1_u smlc_cnt1; /* 40 */ + volatile csr_smlc_cnt2_u smlc_cnt2; /* 48 */ + volatile csr_smlc_cnt3_u smlc_cnt3; /* 50 */ + volatile csr_smlc_cnt_cfg0_u smlc_cnt_cfg0; /* 58 */ + volatile csr_smlc_cnt_cfg1_u smlc_cnt_cfg1; /* 5C */ + volatile csr_smlc_credit_ctp_u smlc_credit_ctp; /* 60 */ + volatile csr_smlc_fifo_depth_ctp_u smlc_fifo_depth_ctp; /* 64 */ + volatile csr_smlc_ecc_err_ctp_u smlc_ecc_err_ctp; /* 68 */ +} S_smlc_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smlc_csr */ +extern volatile S_smlc_csr_REGS_TYPE *gopsmlc_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMLC_VERSION_smlc_version(unsigned int usmlc_version); +int iSetSMLC_CFG0_smlc_ecc_chk_en(unsigned int usmlc_ecc_chk_en); +int iSetSMLC_CFG0_smlc_crt_err_inj(unsigned int usmlc_crt_err_inj); +int iSetSMLC_CFG0_smlc_uncrt_err_inj(unsigned int usmlc_uncrt_err_inj); +int iSetSMLC_CFG0_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMLC_CFG0_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMLC_CFG0_mem_ret1n(unsigned int umem_ret1n); +int iSetSMLC_CFG1_bypass_cd_31_0(unsigned int ubypass_cd_31_0); +int iSetSMLC_CFG2_bypass_cd_63_32(unsigned int ubypass_cd_63_32); +int iSetSMLC_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMLC_INT_VECTOR_enable(unsigned int uenable); +int iSetSMLC_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMLC_INT_int_data(unsigned int uint_data); +int iSetSMLC_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMLC_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMLC_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMLC_SRF_OV_ERR_error_bit(unsigned int uerror_bit); +int iSetSMLC_SRF_OV_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMLC_SRF_OV_ERR_sticky(unsigned int usticky); + +int iSetSMLC_ECC_ERR_fiar_1b_ecc_err(unsigned int ufiar_1b_ecc_err); +int iSetSMLC_ECC_ERR_fiar_1b_ecc_merr(unsigned int ufiar_1b_ecc_merr); +int iSetSMLC_ECC_ERR_fiar_2b_ecc_err(unsigned int ufiar_2b_ecc_err); +int iSetSMLC_ECC_ERR_fiar_2b_ecc_merr(unsigned int ufiar_2b_ecc_merr); +int iSetSMLC_ECC_ERR_bat_1b_ecc_err(unsigned int ubat_1b_ecc_err); +int iSetSMLC_ECC_ERR_bat_1b_ecc_merr(unsigned int ubat_1b_ecc_merr); +int iSetSMLC_ECC_ERR_bat_2b_ecc_err(unsigned int ubat_2b_ecc_err); +int iSetSMLC_ECC_ERR_bat_2b_ecc_merr(unsigned int ubat_2b_ecc_merr); +int iSetSMLC_ECC_ERR_stb_1b_ecc_err(unsigned int ustb_1b_ecc_err); +int iSetSMLC_ECC_ERR_stb_1b_ecc_merr(unsigned int ustb_1b_ecc_merr); +int iSetSMLC_ECC_ERR_stb_2b_ecc_err(unsigned int ustb_2b_ecc_err); +int iSetSMLC_ECC_ERR_stb_2b_ecc_merr(unsigned int ustb_2b_ecc_merr); +int iSetSMLC_ECC_ERR_cdb0_1b_ecc_err(unsigned int ucdb0_1b_ecc_err); +int iSetSMLC_ECC_ERR_cdb0_1b_ecc_merr(unsigned int ucdb0_1b_ecc_merr); +int iSetSMLC_ECC_ERR_cdb0_2b_ecc_err(unsigned int ucdb0_2b_ecc_err); +int iSetSMLC_ECC_ERR_cdb0_2b_ecc_merr(unsigned int ucdb0_2b_ecc_merr); +int iSetSMLC_ECC_ERR_cdb1_1b_ecc_err(unsigned int ucdb1_1b_ecc_err); +int iSetSMLC_ECC_ERR_cdb1_1b_ecc_merr(unsigned int ucdb1_1b_ecc_merr); +int iSetSMLC_ECC_ERR_cdb1_2b_ecc_err(unsigned int ucdb1_2b_ecc_err); +int iSetSMLC_ECC_ERR_cdb1_2b_ecc_merr(unsigned int ucdb1_2b_ecc_merr); +int iSetSMLC_ECC_ERR_pab_1b_ecc_err(unsigned int upab_1b_ecc_err); +int iSetSMLC_ECC_ERR_pab_1b_ecc_merr(unsigned int upab_1b_ecc_merr); +int iSetSMLC_ECC_ERR_pab_2b_ecc_err(unsigned int upab_2b_ecc_err); +int iSetSMLC_ECC_ERR_pab_2b_ecc_merr(unsigned int upab_2b_ecc_merr); +int iSetSMLC_ECC_ERRPR_MASK_fiar_1b_ecc_err_mask(unsigned int ufiar_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_fiar_2b_ecc_err_mask(unsigned int ufiar_2b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_bat_1b_ecc_err_mask(unsigned int ubat_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_bat_2b_ecc_err_mask(unsigned int ubat_2b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_stb_1b_ecc_err_mask(unsigned int ustb_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_stb_2b_ecc_err_mask(unsigned int ustb_2b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_cdb0_1b_ecc_err_mask(unsigned int ucdb0_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_cdb0_2b_ecc_err_mask(unsigned int ucdb0_2b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_cdb1_1b_ecc_err_mask(unsigned int ucdb1_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_cdb1_2b_ecc_err_mask(unsigned int ucdb1_2b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_pab_1b_ecc_err_mask(unsigned int upab_1b_ecc_err_mask); +int iSetSMLC_ECC_ERRPR_MASK_pab_2b_ecc_err_mask(unsigned int upab_2b_ecc_err_mask); +int iSetSMLC_INDRECT_CTRL_smlc_indir_addr(unsigned int usmlc_indir_addr); +int iSetSMLC_INDRECT_CTRL_smlc_indir_tab(unsigned int usmlc_indir_tab); +int iSetSMLC_INDRECT_CTRL_smlc_indir_stat(unsigned int usmlc_indir_stat); +int iSetSMLC_INDRECT_CTRL_smlc_indir_mode(unsigned int usmlc_indir_mode); +int iSetSMLC_INDRECT_CTRL_smlc_indir_vld(unsigned int usmlc_indir_vld); +int iSetSMLC_INDRECT_TIMEOUT_smlc_indir_timeout(unsigned int usmlc_indir_timeout); +int iSetSMLC_INDRECT_DATA_smlc_indir_data(unsigned int usmlc_indir_data); +int iSetSMLC_CNT0_smlc_cnt0(unsigned int usmlc_cnt0); +int iSetSMLC_CNT1_smlc_cnt1(unsigned int usmlc_cnt1); +int iSetSMLC_CNT2_smlc_cnt2(unsigned int usmlc_cnt2); +int iSetSMLC_CNT3_smlc_cnt3(unsigned int usmlc_cnt3); +int iSetSMLC_CNT_CFG0_cnt_enable(unsigned int ucnt_enable); +int iSetSMLC_CNT_CFG0_cnt0_inst_match_enable(unsigned int ucnt0_inst_match_enable); +int iSetSMLC_CNT_CFG0_cnt1_inst_match_enable(unsigned int ucnt1_inst_match_enable); +int iSetSMLC_CNT_CFG0_cnt2_inst_match_enable(unsigned int ucnt2_inst_match_enable); +int iSetSMLC_CNT_CFG0_cnt3_inst_match_enable(unsigned int ucnt3_inst_match_enable); +int iSetSMLC_CNT_CFG0_cnt0_match_inst_id(unsigned int ucnt0_match_inst_id); +int iSetSMLC_CNT_CFG0_cnt1_match_inst_id(unsigned int ucnt1_match_inst_id); +int iSetSMLC_CNT_CFG0_cnt2_match_inst_id(unsigned int ucnt2_match_inst_id); +int iSetSMLC_CNT_CFG0_cnt3_match_inst_id(unsigned int ucnt3_match_inst_id); +int iSetSMLC_CNT_CFG1_cnt0_event_sel(unsigned int ucnt0_event_sel); +int iSetSMLC_CNT_CFG1_cnt1_event_sel(unsigned int ucnt1_event_sel); +int iSetSMLC_CNT_CFG1_cnt2_event_sel(unsigned int ucnt2_event_sel); +int iSetSMLC_CNT_CFG1_cnt3_event_sel(unsigned int ucnt3_event_sel); +int iSetSMLC_CREDIT_CTP_smmc_credit(unsigned int usmmc_credit); +int iSetSMLC_CREDIT_CTP_vc_credit(unsigned int uvc_credit); +int iSetSMLC_FIFO_DEPTH_CTP_srf_fifo_depth(unsigned int usrf_fifo_depth); +int iSetSMLC_ECC_ERR_CTP_ecc_error_info(unsigned int uecc_error_info); + +/* Define the union csr_smmc_f_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_version_u; + +/* Define the union csr_smmc_f_mc_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_qu_tx_ctp_enb : 1; /* [0] */ + u32 smmc_f_qu_rx_ctp_enb : 1; /* [1] */ + u32 smmc_mc_cla_chk_enb : 1; /* [2] */ + u32 smmc_mc_ecc_parity_enable : 1; /* [3] */ + u32 smmc_qu_return_fifo_bpon_thd : 6; /* [9:4] */ + u32 smmc_qu_return_fifo_bp0ff_thd : 6; /* [15:10] */ + u32 smmc_qu_store_bp_thd : 8; /* [23:16] */ + u32 mem_bank_id_pst : 2; /* [25:24] */ + u32 write_so_ro : 2; /* [27:26] */ + u32 read_so_ro : 2; /* [29:28] */ + u32 rsv_0 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cfg_u; + +/* Define the union csr_smmc_f_mc_cfg1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cid_src : 15; /* [14:0] */ + u32 bankid_src : 15; /* [29:15] */ + u32 rsv_1 : 2; /* [31:30] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cfg1_u; + +/* Define the union csr_smmc_hash_seed0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hash_seed_cfg0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_hash_seed0_u; + +/* Define the union csr_smmc_hash_seed1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 hash_seed_cfg1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_hash_seed1_u; + +/* Define the union csr_smmc_f_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 tp_ram_tmod : 8; /* [7:0] */ + u32 sp_ram_tmod : 7; /* [14:8] */ + u32 mem_ret1n : 1; /* [15] */ + u32 smmc_f_bank_vld_num : 2; /* [17:16] */ + u32 smmc_f_bank_vld_id : 4; /* [21:18] */ + u32 rsv_2 : 2; /* [23:22] */ + u32 sp_ram_tmod_div2 : 7; /* [30:24] */ + u32 mem_ret1n_div2 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_cfg_u; + +/* Define the union csr_smmc_f_mc_init_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_mc_init : 1; /* [0] */ + u32 smmc_mc_init_start_addr : 14; /* [14:1] */ + u32 smmc_mc_init_end_addr : 14; /* [28:15] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_init_u; + +/* Define the union csr_smmc_f_mc_rf_timeout_interval_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_refill_timeout_interval : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_rf_timeout_interval_u; + +/* Define the union csr_smmc_f_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_4 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_5 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_int_vector_u; + +/* Define the union csr_smmc_f_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 6; /* [5:0] */ + u32 rsv_6 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_int_u; + +/* Define the union csr_smmc_f_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 6; /* [5:0] */ + u32 rsv_7 : 10; /* [15:6] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_int_mask_u; + +/* Define the union csr_smmc_f_mc_cache_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_tag0_1b_ecc_err : 1; /* [0] */ + u32 mc_tag0_1b_ecc_merr : 1; /* [1] */ + u32 mc_tag0_2b_ecc_err : 1; /* [2] */ + u32 mc_tag0_2b_ecc_merr : 1; /* [3] */ + u32 mc_tag1_1b_ecc_err : 1; /* [4] */ + u32 mc_tag1_1b_ecc_merr : 1; /* [5] */ + u32 mc_tag1_2b_ecc_err : 1; /* [6] */ + u32 mc_tag1_2b_ecc_merr : 1; /* [7] */ + u32 mc_tag2_1b_ecc_err : 1; /* [8] */ + u32 mc_tag2_1b_ecc_merr : 1; /* [9] */ + u32 mc_tag2_2b_ecc_err : 1; /* [10] */ + u32 mc_tag2_2b_ecc_merr : 1; /* [11] */ + u32 mc_tag3_1b_ecc_err : 1; /* [12] */ + u32 mc_tag3_1b_ecc_merr : 1; /* [13] */ + u32 mc_tag3_2b_ecc_err : 1; /* [14] */ + u32 mc_tag3_2b_ecc_merr : 1; /* [15] */ + u32 mc_data0_1b_ecc_err : 1; /* [16] */ + u32 mc_data0_1b_ecc_merr : 1; /* [17] */ + u32 mc_data0_2b_ecc_err : 1; /* [18] */ + u32 mc_data0_2b_ecc_merr : 1; /* [19] */ + u32 mc_data1_1b_ecc_err : 1; /* [20] */ + u32 mc_data1_1b_ecc_merr : 1; /* [21] */ + u32 mc_data1_2b_ecc_err : 1; /* [22] */ + u32 mc_data1_2b_ecc_merr : 1; /* [23] */ + u32 mc_data2_1b_ecc_err : 1; /* [24] */ + u32 mc_data2_1b_ecc_merr : 1; /* [25] */ + u32 mc_data2_2b_ecc_err : 1; /* [26] */ + u32 mc_data2_2b_ecc_merr : 1; /* [27] */ + u32 mc_data3_1b_ecc_err : 1; /* [28] */ + u32 mc_data3_1b_ecc_merr : 1; /* [29] */ + u32 mc_data3_2b_ecc_err : 1; /* [30] */ + u32 mc_data3_2b_ecc_merr : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cache_err_u; + +/* Define the union csr_smmc_f_mc_cache_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_tag0_1b_ecc_err_mask : 1; /* [0] */ + u32 mc_tag0_2b_ecc_err_mask : 1; /* [1] */ + u32 mc_tag1_1b_ecc_err_mask : 1; /* [2] */ + u32 mc_tag1_2b_ecc_err_mask : 1; /* [3] */ + u32 mc_tag2_1b_ecc_err_mask : 1; /* [4] */ + u32 mc_tag2_2b_ecc_err_mask : 1; /* [5] */ + u32 mc_tag3_1b_ecc_err_mask : 1; /* [6] */ + u32 mc_tag3_2b_ecc_err_mask : 1; /* [7] */ + u32 mc_data0_1b_ecc_err_mask : 1; /* [8] */ + u32 mc_data0_2b_ecc_err_mask : 1; /* [9] */ + u32 mc_data1_1b_ecc_err_mask : 1; /* [10] */ + u32 mc_data1_2b_ecc_err_mask : 1; /* [11] */ + u32 mc_data2_1b_ecc_err_mask : 1; /* [12] */ + u32 mc_data2_2b_ecc_err_mask : 1; /* [13] */ + u32 mc_data3_1b_ecc_err_mask : 1; /* [14] */ + u32 mc_data3_2b_ecc_err_mask : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cache_mask_u; + +/* Define the union csr_smmc_f_mc_cache_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cache_err_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cache_err_info_u; + +/* Define the union csr_smmc_f_buffer_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_qu_vfa_1b_ecc_err : 1; /* [0] */ + u32 mc_qu_vfa_1b_ecc_merr : 1; /* [1] */ + u32 mc_qu_vfa_2b_ecc_err : 1; /* [2] */ + u32 mc_qu_vfa_2b_ecc_merr : 1; /* [3] */ + u32 mc_eng_stbuf_1b_ecc_err : 1; /* [4] */ + u32 mc_eng_stbuf_1b_ecc_merr : 1; /* [5] */ + u32 mc_eng_stbuf_2b_ecc_err : 1; /* [6] */ + u32 mc_eng_stbuf_2b_ecc_merr : 1; /* [7] */ + u32 mc_qu_stbuf_1b_ecc_err : 1; /* [8] */ + u32 mc_qu_stbuf_1b_ecc_merr : 1; /* [9] */ + u32 mc_qu_stbuf_2b_ecc_err : 1; /* [10] */ + u32 mc_qu_stbuf_2b_ecc_merr : 1; /* [11] */ + u32 mc_qu_lrn_1b_ecc_err : 1; /* [12] */ + u32 mc_qu_lrn_1b_ecc_merr : 1; /* [13] */ + u32 mc_qu_lrn_2b_ecc_err : 1; /* [14] */ + u32 mc_qu_lrn_2b_ecc_merr : 1; /* [15] */ + u32 mc_qu_datafifo_1b_ecc_err : 1; /* [16] */ + u32 mc_qu_datafifo_1b_ecc_merr : 1; /* [17] */ + u32 mc_qu_datafifo_2b_ecc_err : 1; /* [18] */ + u32 mc_qu_datafifo_2b_ecc_merr : 1; /* [19] */ + u32 mc_rfbuf_1b_ecc_err : 1; /* [20] */ + u32 mc_rfbuf_1b_ecc_merr : 1; /* [21] */ + u32 mc_rfbuf_2b_ecc_err : 1; /* [22] */ + u32 mc_rfbuf_2b_ecc_merr : 1; /* [23] */ + u32 vc_smxtf_buf_1b_ecc_err : 1; /* [24] */ + u32 vc_smxtf_buf_1b_ecc_merr : 1; /* [25] */ + u32 vc_smxtf_buf_2b_ecc_err : 1; /* [26] */ + u32 vc_smxtf_buf_2b_ecc_merr : 1; /* [27] */ + u32 directwqe_err : 1; /* [28] */ + u32 directwqe_merr : 1; /* [29] */ + u32 fifo_ovf_err : 1; /* [30] */ + u32 fifo_ovf_merr : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_buffer_err_u; + +/* Define the union csr_smmc_f_buffer_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_qu_vfa_1b_ecc_err_mask : 1; /* [0] */ + u32 mc_qu_vfa_2b_ecc_err_mask : 1; /* [1] */ + u32 mc_eng_stbuf_1b_ecc_err_mask : 1; /* [2] */ + u32 mc_eng_stbuf_2b_ecc_err_mask : 1; /* [3] */ + u32 mc_qu_stbuf_1b_ecc_err_mask : 1; /* [4] */ + u32 mc_qu_stbuf_2b_ecc_err_mask : 1; /* [5] */ + u32 mc_qu_lrn_1b_ecc_err_mask : 1; /* [6] */ + u32 mc_qu_lrn_2b_ecc_err_mask : 1; /* [7] */ + u32 mc_qu_datafifo_1b_ecc_err_mask : 1; /* [8] */ + u32 mc_qu_datafifo_2b_ecc_err_mask : 1; /* [9] */ + u32 mc_rfbuf_1b_ecc_err_mask : 1; /* [10] */ + u32 mc_rfbuf_2b_ecc_err_mask : 1; /* [11] */ + u32 vc_smxtf_buf_1b_ecc_err_mask : 1; /* [12] */ + u32 vc_smxtf_buf_2b_ecc_err_mask : 1; /* [13] */ + u32 directwqe_err_mask : 1; /* [14] */ + u32 fifo_ovf_err_mask : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_buffer_mask_u; + +/* Define the union csr_smmc_f_buffer_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_buffer_err_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_buffer_err_info_u; + +/* Define the union csr_smmc_f_bus_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_rf_timeout_err : 1; /* [0] */ + u32 mc_rf_timeout_merr : 1; /* [1] */ + u32 mc_rf_rtn_err : 1; /* [2] */ + u32 mc_rf_rtn_merr : 1; /* [3] */ + u32 qpc_ring_e01_err : 1; /* [4] */ + u32 qpc_ring_e01_merr : 1; /* [5] */ + u32 qu_lrn_fifo_1bit_ecc_err : 1; /* [6] */ + u32 qu_lrn_fifo_1bit_ecc_merr : 1; /* [7] */ + u32 qu_lrn_fifo_2bit_ecc_err : 1; /* [8] */ + u32 qu_lrn_fifo_2bit_ecc_merr : 1; /* [9] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_bus_err_u; + +/* Define the union csr_smmc_f_bus_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_rf_timeout_err_mask : 1; /* [0] */ + u32 mc_rf_rtn_err_mask : 1; /* [1] */ + u32 qpc_ring_e01_err_mask : 1; /* [2] */ + u32 qu_lrn_fifo_1bit_ecc_err_mask : 1; /* [3] */ + u32 qu_lrn_fifo_2bit_ecc_err_mask : 1; /* [4] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_bus_mask_u; + +/* Define the union csr_smmc_f_mc_multi_hit_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_multi_hit_err_u; + +/* Define the union csr_smmc_f_vc_cache_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc_wb0_1b_ecc_err : 1; /* [0] */ + u32 vc_wb0_1b_ecc_merr : 1; /* [1] */ + u32 vc_wb0_2b_ecc_err : 1; /* [2] */ + u32 vc_wb0_2b_ecc_merr : 1; /* [3] */ + u32 vc_wb1_1b_ecc_err : 1; /* [4] */ + u32 vc_wb1_1b_ecc_merr : 1; /* [5] */ + u32 vc_wb1_2b_ecc_err : 1; /* [6] */ + u32 vc_wb1_2b_ecc_merr : 1; /* [7] */ + u32 vc_wb2_1b_ecc_err : 1; /* [8] */ + u32 vc_wb2_1b_ecc_merr : 1; /* [9] */ + u32 vc_wb2_2b_ecc_err : 1; /* [10] */ + u32 vc_wb2_2b_ecc_merr : 1; /* [11] */ + u32 vc_wb3_1b_ecc_err : 1; /* [12] */ + u32 vc_wb3_1b_ecc_merr : 1; /* [13] */ + u32 vc_wb3_2b_ecc_err : 1; /* [14] */ + u32 vc_wb3_2b_ecc_merr : 1; /* [15] */ + u32 vc_data0_1b_ecc_err : 1; /* [16] */ + u32 vc_data0_1b_ecc_merr : 1; /* [17] */ + u32 vc_data0_2b_ecc_err : 1; /* [18] */ + u32 vc_data0_2b_ecc_merr : 1; /* [19] */ + u32 vc_data1_1b_ecc_err : 1; /* [20] */ + u32 vc_data1_1b_ecc_merr : 1; /* [21] */ + u32 vc_data1_2b_ecc_err : 1; /* [22] */ + u32 vc_data1_2b_ecc_merr : 1; /* [23] */ + u32 vc_data2_1b_ecc_err : 1; /* [24] */ + u32 vc_data2_1b_ecc_merr : 1; /* [25] */ + u32 vc_data2_2b_ecc_err : 1; /* [26] */ + u32 vc_data2_2b_ecc_merr : 1; /* [27] */ + u32 vc_data3_1b_ecc_err : 1; /* [28] */ + u32 vc_data3_1b_ecc_merr : 1; /* [29] */ + u32 vc_data3_2b_ecc_err : 1; /* [30] */ + u32 vc_data3_2b_ecc_merr : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_vc_cache_err_u; + +/* Define the union csr_smmc_f_vc_cache_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc_wb0_1b_ecc_err_mask : 1; /* [0] */ + u32 vc_wb0_2b_ecc_err_mask : 1; /* [1] */ + u32 vc_wb1_1b_ecc_err_mask : 1; /* [2] */ + u32 vc_wb1_2b_ecc_err_mask : 1; /* [3] */ + u32 vc_wb2_1b_ecc_err_mask : 1; /* [4] */ + u32 vc_wb2_2b_ecc_err_mask : 1; /* [5] */ + u32 vc_wb3_1b_ecc_err_mask : 1; /* [6] */ + u32 vc_wb3_2b_ecc_err_mask : 1; /* [7] */ + u32 vc_data0_1b_ecc_err_mask : 1; /* [8] */ + u32 vc_data0_2b_ecc_err_mask : 1; /* [9] */ + u32 vc_data1_1b_ecc_err_mask : 1; /* [10] */ + u32 vc_data1_2b_ecc_err_mask : 1; /* [11] */ + u32 vc_data2_1b_ecc_err_mask : 1; /* [12] */ + u32 vc_data2_2b_ecc_err_mask : 1; /* [13] */ + u32 vc_data3_1b_ecc_err_mask : 1; /* [14] */ + u32 vc_data3_2b_ecc_err_mask : 1; /* [15] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_vc_cache_mask_u; + +/* Define the union csr_smmc_f_vc_cache_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc_cache_err_info : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_vc_cache_err_info_u; + +/* Define the union csr_smmc_f_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_indir_addr : 24; /* [23:0] */ + u32 smmc_f_indir_tab : 4; /* [27:24] */ + u32 smmc_f_indir_stat : 2; /* [29:28] */ + u32 smmc_f_indir_mode : 1; /* [30] */ + u32 smmc_f_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_indrect_ctrl_u; + +/* Define the union csr_smmc_f_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_indrect_timeout_u; + +/* Define the union csr_smmc_f_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_indrect_data_u; + +/* Define the union csr_smmc_f_mc_cnt_enb_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_mc_cnt_enb : 8; /* [7:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_enb_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel_enb_grp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_mc_cnt_event_sel_enb0 : 8; /* [7:0] */ + u32 smmc_f_mc_cnt_event_sel_enb1 : 8; /* [15:8] */ + u32 smmc_f_mc_cnt_event_sel_enb2 : 8; /* [23:16] */ + u32 smmc_f_mc_cnt_event_sel_enb3 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel_enb_grp0_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel_enb_grp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_mc_cnt_event_sel_enb4 : 8; /* [7:0] */ + u32 smmc_f_mc_cnt_event_sel_enb5 : 8; /* [15:8] */ + u32 smmc_f_mc_cnt_event_sel_enb6 : 8; /* [23:16] */ + u32 smmc_f_mc_cnt_event_sel_enb7 : 8; /* [31:24] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel_enb_grp1_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel0_vf_id : 10; /* [9:0] */ + u32 rsv_8 : 5; /* [14:10] */ + u32 mc_cnt_event_sel0_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel0_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel0_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel0_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel0_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel0_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel0_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel1_vf_id : 10; /* [9:0] */ + u32 rsv_9 : 5; /* [14:10] */ + u32 mc_cnt_event_sel1_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel1_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel1_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel1_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel1_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel1_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel1_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel2_vf_id : 10; /* [9:0] */ + u32 rsv_10 : 5; /* [14:10] */ + u32 mc_cnt_event_sel2_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel2_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel2_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel2_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel2_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel2_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel2_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel3_vf_id : 10; /* [9:0] */ + u32 rsv_11 : 5; /* [14:10] */ + u32 mc_cnt_event_sel3_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel3_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel3_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel3_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel3_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel3_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel3_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel4_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel4_vf_id : 10; /* [9:0] */ + u32 rsv_12 : 5; /* [14:10] */ + u32 mc_cnt_event_sel4_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel4_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel4_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel4_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel4_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel4_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel4_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel5_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel5_vf_id : 10; /* [9:0] */ + u32 rsv_13 : 5; /* [14:10] */ + u32 mc_cnt_event_sel5_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel5_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel5_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel5_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel5_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel5_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel5_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel6_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel6_vf_id : 10; /* [9:0] */ + u32 rsv_14 : 5; /* [14:10] */ + u32 mc_cnt_event_sel6_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel6_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel6_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel6_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel6_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel6_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel6_u; + +/* Define the union csr_smmc_f_mc_cnt_event_sel7_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_cnt_event_sel7_vf_id : 10; /* [9:0] */ + u32 rsv_15 : 5; /* [14:10] */ + u32 mc_cnt_event_sel7_tag_type : 4; /* [18:15] */ + u32 mc_cnt_event_sel7_bank_id : 2; /* [20:19] */ + u32 mc_cnt_event_sel7_req_src : 3; /* [23:21] */ + u32 mc_cnt_event_sel7_api_type : 4; /* [27:24] */ + u32 mc_cnt_event_sel7_event_type : 3; /* [30:28] */ + u32 mc_cnt_event_sel7_unit_type : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cnt_event_sel7_u; + +/* Define the union csr_smmc_f_mc_status_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mc_init_done : 1; /* [0] */ + u32 mc_free_tag_num : 7; /* [7:1] */ + u32 qu_rx_flit_ctp_done : 1; /* [8] */ + u32 qu_tx_flit_ctp_done : 1; /* [9] */ + u32 smmc_rf_timeout : 1; /* [10] */ + u32 rsv_16 : 21; /* [31:11] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_status_u; + +/* Define the union csr_smmc_f_mc_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt0 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt0_u; + +/* Define the union csr_smmc_f_mc_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt1 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt1_u; + +/* Define the union csr_smmc_f_mc_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt2 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt2_u; + +/* Define the union csr_smmc_f_mc_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt3 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt3_u; + +/* Define the union csr_smmc_f_mc_cnt4_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt4 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt4_u; + +/* Define the union csr_smmc_f_mc_cnt5_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt5 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt5_u; + +/* Define the union csr_smmc_f_mc_cnt6_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt6 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt6_u; + +/* Define the union csr_smmc_f_mc_cnt7_u */ +typedef union { + /* Define the struct bits */ + struct { + u64 smmc_f_mc_cnt7 : 48; /* [47:0] */ + } bits; + + /* Define an unsigned member */ + u64 value; +} csr_smmc_f_mc_cnt7_u; + +/* Define the union csr_smmc_f_vc_fifo_depth0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_wb_data_fifo_depth : 5; /* [4:0] */ + u32 vc1_wb_data_fifo_depth : 5; /* [9:5] */ + u32 vc2_wb_data_fifo_depth : 5; /* [14:10] */ + u32 vc3_wb_data_fifo_depth : 5; /* [19:15] */ + u32 vc0_wb_ctrl_fifo_depth : 3; /* [22:20] */ + u32 vc1_wb_ctrl_fifo_depth : 3; /* [25:23] */ + u32 vc2_wb_ctrl_fifo_depth : 3; /* [28:26] */ + u32 vc3_wb_ctrl_fifo_depth : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_vc_fifo_depth0_u; + +/* Define the union csr_smmc_f_vc_fifo_depth1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 vc0_ctrl_fifo_depth : 2; /* [1:0] */ + u32 vc1_ctrl_fifo_depth : 2; /* [3:2] */ + u32 vc2_ctrl_fifo_depth : 2; /* [5:4] */ + u32 vc3_ctrl_fifo_depth : 2; /* [7:6] */ + u32 vc0_data_fifo_depth : 2; /* [9:8] */ + u32 vc1_data_fifo_depth : 2; /* [11:10] */ + u32 vc2_data_fifo_depth : 2; /* [13:12] */ + u32 vc3_data_fifo_depth : 2; /* [15:14] */ + u32 smxtf_fifo_depth : 6; /* [21:16] */ + u32 vc_crdt_from_smit : 3; /* [24:22] */ + u32 data_credit_from_qu : 6; /* [30:25] */ + u32 rsv_17 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_vc_fifo_depth1_u; + +/* Define the union csr_smmc_f_mc_fifo1_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_cmd_fifo_depth : 4; /* [3:0] */ + u32 qu_data_fifo_depth : 6; /* [9:4] */ + u32 lrb0_fifo_depth : 6; /* [15:10] */ + u32 lrb1_fifo_depth : 6; /* [21:16] */ + u32 lrb2_fifo_depth : 6; /* [27:22] */ + u32 rsv_18 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_fifo1_depth_u; + +/* Define the union csr_smmc_f_mc_fifo2_depth_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 qu_return_fifo_depth : 6; /* [5:0] */ + u32 qu_return_fifo_bp : 1; /* [6] */ + u32 qu_store_buffer_bp : 1; /* [7] */ + u32 lrb3_fifo_depth : 6; /* [13:8] */ + u32 rfbuf_credit : 9; /* [22:14] */ + u32 qu_store_buffer_depth : 9; /* [31:23] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_fifo2_depth_u; + +/* Define the union csr_smmc_f_err_inj_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_vc0_crt_err_inj : 1; /* [0] */ + u32 smmc_vc0_uncrt_err_inj : 1; /* [1] */ + u32 smmc_vc1_crt_err_inj : 1; /* [2] */ + u32 smmc_vc1_uncrt_err_inj : 1; /* [3] */ + u32 smmc_vc2_crt_err_inj : 1; /* [4] */ + u32 smmc_vc2_uncrt_err_inj : 1; /* [5] */ + u32 smmc_vc3_crt_err_inj : 1; /* [6] */ + u32 smmc_vc3_uncrt_err_inj : 1; /* [7] */ + u32 smmc_mc0_crt_err_inj : 1; /* [8] */ + u32 smmc_mc0_uncrt_err_inj : 1; /* [9] */ + u32 smmc_mc1_crt_err_inj : 1; /* [10] */ + u32 smmc_mc1_uncrt_err_inj : 1; /* [11] */ + u32 smmc_mc2_crt_err_inj : 1; /* [12] */ + u32 smmc_mc2_uncrt_err_inj : 1; /* [13] */ + u32 smmc_mc3_crt_err_inj : 1; /* [14] */ + u32 smmc_mc3_uncrt_err_inj : 1; /* [15] */ + u32 smmc_qu_intf_crt_err_inj : 1; /* [16] */ + u32 smmc_qu_intf_uncrt_err_inj : 1; /* [17] */ + u32 smmc_rf_buf_crt_err_inj : 1; /* [18] */ + u32 smmc_rf_buf_uncrt_err_inj : 1; /* [19] */ + u32 smmc_vfa_crt_err_inj : 1; /* [20] */ + u32 smmc_vfa_uncrt_err_inj : 1; /* [21] */ + u32 smmc_stb_crt_err_inj : 1; /* [22] */ + u32 smmc_stb_uncrt_err_inj : 1; /* [23] */ + u32 smmc_smxtfb_crt_err_inj : 1; /* [24] */ + u32 smmc_smxtfb_uncrt_err_inj : 1; /* [25] */ + u32 rsv_19 : 6; /* [31:26] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_err_inj_u; + +/* Define the union csr_smmc_f_gpa_trans_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 error_bit : 1; /* [0] */ + u32 multi_error_bit : 1; /* [1] */ + u32 sticky : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_gpa_trans_err_u; + +/* Define the union csr_smmc_f_qu_intf_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_qu_intf_tx_cnt_cfg : 16; /* [15:0] */ + u32 smmc_f_qu_intf_rx_cnt_cfg : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_qu_intf_cnt_cfg_u; + +/* Define the union csr_smmc_f_qu_intf_rx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_qu_intf_rx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_qu_intf_rx_cnt_u; + +/* Define the union csr_smmc_f_qu_intf_tx_cnt_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_qu_intf_tx_cnt : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_qu_intf_tx_cnt_u; + +/* Define the union csr_smmc_f_mc_cfg2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_rsc_cnt_mix_en : 1; /* [0] */ + u32 smmc_f_rtt_cnt_type : 1; /* [1] */ + u32 smmc_f_rtt_cnt_enb : 1; /* [2] */ + u32 smmc_f_rf_err_ctp_clr : 1; /* [3] */ + u32 smf_common_mem_power_mode : 6; /* [9:4] */ + u32 mc_refill_timeout_enb : 1; /* [10] */ + u32 bypass_smvc : 1; /* [11] */ + u32 rsv_20 : 20; /* [31:12] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_f_mc_cfg2_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smmc_f_version_u smmc_f_version; /* 0 */ + volatile csr_smmc_f_mc_cfg_u smmc_f_mc_cfg; /* 4 */ + volatile csr_smmc_f_mc_cfg1_u smmc_f_mc_cfg1; /* 8 */ + volatile csr_smmc_hash_seed0_u smmc_hash_seed0; /* C */ + volatile csr_smmc_hash_seed1_u smmc_hash_seed1; /* 10 */ + volatile csr_smmc_f_cfg_u smmc_f_cfg; /* 14 */ + volatile csr_smmc_f_mc_init_u smmc_f_mc_init; /* 18 */ + volatile csr_smmc_f_mc_rf_timeout_interval_u smmc_f_mc_rf_timeout_interval; /* 1C */ + volatile csr_smmc_f_int_vector_u smmc_f_int_vector; /* 20 */ + volatile csr_smmc_f_int_u smmc_f_int; /* 24 */ + volatile csr_smmc_f_int_mask_u smmc_f_int_mask; /* 28 */ + volatile csr_smmc_f_mc_cache_err_u smmc_f_mc_cache_err; /* 2C */ + volatile csr_smmc_f_mc_cache_mask_u smmc_f_mc_cache_mask; /* 30 */ + volatile csr_smmc_f_mc_cache_err_info_u smmc_f_mc_cache_err_info; /* 34 */ + volatile csr_smmc_f_buffer_err_u smmc_f_buffer_err; /* 38 */ + volatile csr_smmc_f_buffer_mask_u smmc_f_buffer_mask; /* 3C */ + volatile csr_smmc_f_buffer_err_info_u smmc_f_buffer_err_info; /* 40 */ + volatile csr_smmc_f_bus_err_u smmc_f_bus_err; /* 44 */ + volatile csr_smmc_f_bus_mask_u smmc_f_bus_mask; /* 48 */ + volatile csr_smmc_f_mc_multi_hit_err_u smmc_f_mc_multi_hit_err; /* 4C */ + volatile csr_smmc_f_vc_cache_err_u smmc_f_vc_cache_err; /* 50 */ + volatile csr_smmc_f_vc_cache_mask_u smmc_f_vc_cache_mask; /* 54 */ + volatile csr_smmc_f_vc_cache_err_info_u smmc_f_vc_cache_err_info; /* 58 */ + volatile csr_smmc_f_indrect_ctrl_u smmc_f_indrect_ctrl; /* 5C */ + volatile csr_smmc_f_indrect_timeout_u smmc_f_indrect_timeout; /* 60 */ + volatile csr_smmc_f_indrect_data_u smmc_f_indrect_data; /* 64 */ + volatile csr_smmc_f_mc_cnt_enb_u smmc_f_mc_cnt_enb; /* 68 */ + volatile csr_smmc_f_mc_cnt_event_sel_enb_grp0_u smmc_f_mc_cnt_event_sel_enb_grp0; /* 6C */ + volatile csr_smmc_f_mc_cnt_event_sel_enb_grp1_u smmc_f_mc_cnt_event_sel_enb_grp1; /* 70 */ + volatile csr_smmc_f_mc_cnt_event_sel0_u smmc_f_mc_cnt_event_sel0; /* 74 */ + volatile csr_smmc_f_mc_cnt_event_sel1_u smmc_f_mc_cnt_event_sel1; /* 78 */ + volatile csr_smmc_f_mc_cnt_event_sel2_u smmc_f_mc_cnt_event_sel2; /* 7C */ + volatile csr_smmc_f_mc_cnt_event_sel3_u smmc_f_mc_cnt_event_sel3; /* 80 */ + volatile csr_smmc_f_mc_cnt_event_sel4_u smmc_f_mc_cnt_event_sel4; /* 84 */ + volatile csr_smmc_f_mc_cnt_event_sel5_u smmc_f_mc_cnt_event_sel5; /* 88 */ + volatile csr_smmc_f_mc_cnt_event_sel6_u smmc_f_mc_cnt_event_sel6; /* 8C */ + volatile csr_smmc_f_mc_cnt_event_sel7_u smmc_f_mc_cnt_event_sel7; /* 90 */ + volatile csr_smmc_f_mc_status_u smmc_f_mc_status; /* 94 */ + volatile csr_smmc_f_mc_cnt0_u smmc_f_mc_cnt0; /* 98 */ + volatile csr_smmc_f_mc_cnt1_u smmc_f_mc_cnt1; /* A0 */ + volatile csr_smmc_f_mc_cnt2_u smmc_f_mc_cnt2; /* A8 */ + volatile csr_smmc_f_mc_cnt3_u smmc_f_mc_cnt3; /* B0 */ + volatile csr_smmc_f_mc_cnt4_u smmc_f_mc_cnt4; /* B8 */ + volatile csr_smmc_f_mc_cnt5_u smmc_f_mc_cnt5; /* C0 */ + volatile csr_smmc_f_mc_cnt6_u smmc_f_mc_cnt6; /* C8 */ + volatile csr_smmc_f_mc_cnt7_u smmc_f_mc_cnt7; /* D0 */ + volatile csr_smmc_f_vc_fifo_depth0_u smmc_f_vc_fifo_depth0; /* D8 */ + volatile csr_smmc_f_vc_fifo_depth1_u smmc_f_vc_fifo_depth1; /* DC */ + volatile csr_smmc_f_mc_fifo1_depth_u smmc_f_mc_fifo1_depth; /* E0 */ + volatile csr_smmc_f_mc_fifo2_depth_u smmc_f_mc_fifo2_depth; /* E4 */ + volatile csr_smmc_f_err_inj_u smmc_f_err_inj; /* E8 */ + volatile csr_smmc_f_gpa_trans_err_u smmc_f_gpa_trans_err; /* EC */ + volatile csr_smmc_f_qu_intf_cnt_cfg_u smmc_f_qu_intf_cnt_cfg; /* F0 */ + volatile csr_smmc_f_qu_intf_rx_cnt_u smmc_f_qu_intf_rx_cnt; /* F4 */ + volatile csr_smmc_f_qu_intf_tx_cnt_u smmc_f_qu_intf_tx_cnt; /* F8 */ + volatile csr_smmc_f_mc_cfg2_u smmc_f_mc_cfg2; /* FC */ +} S_smmc_f_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smmc_f_csr */ +extern volatile S_smmc_f_csr_REGS_TYPE *gopsmmc_f_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMMC_F_VERSION_smmc_f_version(unsigned int usmmc_f_version); +int iSetSMMC_F_MC_CFG_smmc_f_qu_tx_ctp_enb(unsigned int usmmc_f_qu_tx_ctp_enb); +int iSetSMMC_F_MC_CFG_smmc_f_qu_rx_ctp_enb(unsigned int usmmc_f_qu_rx_ctp_enb); +int iSetSMMC_F_MC_CFG_smmc_mc_cla_chk_enb(unsigned int usmmc_mc_cla_chk_enb); +int iSetSMMC_F_MC_CFG_smmc_mc_ecc_parity_enable(unsigned int usmmc_mc_ecc_parity_enable); +int iSetSMMC_F_MC_CFG_smmc_qu_return_fifo_bpon_thd(unsigned int usmmc_qu_return_fifo_bpon_thd); +int iSetSMMC_F_MC_CFG_smmc_qu_return_fifo_bp0ff_thd(unsigned int usmmc_qu_return_fifo_bp0ff_thd); +int iSetSMMC_F_MC_CFG_smmc_qu_store_bp_thd(unsigned int usmmc_qu_store_bp_thd); +int iSetSMMC_F_MC_CFG_mem_bank_id_pst(unsigned int umem_bank_id_pst); +int iSetSMMC_F_MC_CFG_write_so_ro(unsigned int uwrite_so_ro); +int iSetSMMC_F_MC_CFG_read_so_ro(unsigned int uread_so_ro); +int iSetSMMC_F_MC_CFG1_cid_src(unsigned int ucid_src); +int iSetSMMC_F_MC_CFG1_bankid_src(unsigned int ubankid_src); +int iSetSMMC_HASH_SEED0_hash_seed_cfg0(unsigned int uhash_seed_cfg0); +int iSetSMMC_HASH_SEED1_hash_seed_cfg1(unsigned int uhash_seed_cfg1); +int iSetSMMC_F_CFG_tp_ram_tmod(unsigned int utp_ram_tmod); +int iSetSMMC_F_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMMC_F_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMMC_F_CFG_smmc_f_bank_vld_num(unsigned int usmmc_f_bank_vld_num); +int iSetSMMC_F_CFG_smmc_f_bank_vld_id(unsigned int usmmc_f_bank_vld_id); +int iSetSMMC_F_CFG_sp_ram_tmod_div2(unsigned int usp_ram_tmod_div2); +int iSetSMMC_F_CFG_mem_ret1n_div2(unsigned int umem_ret1n_div2); +int iSetSMMC_F_MC_INIT_smmc_mc_init(unsigned int usmmc_mc_init); +int iSetSMMC_F_MC_INIT_smmc_mc_init_start_addr(unsigned int usmmc_mc_init_start_addr); +int iSetSMMC_F_MC_INIT_smmc_mc_init_end_addr(unsigned int usmmc_mc_init_end_addr); +int iSetSMMC_F_MC_RF_TIMEOUT_INTERVAL_mc_refill_timeout_interval(unsigned int umc_refill_timeout_interval); +int iSetSMMC_F_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMMC_F_INT_VECTOR_enable(unsigned int uenable); +int iSetSMMC_F_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMMC_F_INT_int_data(unsigned int uint_data); +int iSetSMMC_F_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMMC_F_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMMC_F_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag0_1b_ecc_err(unsigned int umc_tag0_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag0_1b_ecc_merr(unsigned int umc_tag0_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag0_2b_ecc_err(unsigned int umc_tag0_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag0_2b_ecc_merr(unsigned int umc_tag0_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag1_1b_ecc_err(unsigned int umc_tag1_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag1_1b_ecc_merr(unsigned int umc_tag1_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag1_2b_ecc_err(unsigned int umc_tag1_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag1_2b_ecc_merr(unsigned int umc_tag1_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag2_1b_ecc_err(unsigned int umc_tag2_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag2_1b_ecc_merr(unsigned int umc_tag2_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag2_2b_ecc_err(unsigned int umc_tag2_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag2_2b_ecc_merr(unsigned int umc_tag2_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag3_1b_ecc_err(unsigned int umc_tag3_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag3_1b_ecc_merr(unsigned int umc_tag3_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag3_2b_ecc_err(unsigned int umc_tag3_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_tag3_2b_ecc_merr(unsigned int umc_tag3_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data0_1b_ecc_err(unsigned int umc_data0_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data0_1b_ecc_merr(unsigned int umc_data0_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data0_2b_ecc_err(unsigned int umc_data0_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data0_2b_ecc_merr(unsigned int umc_data0_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data1_1b_ecc_err(unsigned int umc_data1_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data1_1b_ecc_merr(unsigned int umc_data1_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data1_2b_ecc_err(unsigned int umc_data1_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data1_2b_ecc_merr(unsigned int umc_data1_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data2_1b_ecc_err(unsigned int umc_data2_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data2_1b_ecc_merr(unsigned int umc_data2_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data2_2b_ecc_err(unsigned int umc_data2_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data2_2b_ecc_merr(unsigned int umc_data2_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data3_1b_ecc_err(unsigned int umc_data3_1b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data3_1b_ecc_merr(unsigned int umc_data3_1b_ecc_merr); +int iSetSMMC_F_MC_CACHE_ERR_mc_data3_2b_ecc_err(unsigned int umc_data3_2b_ecc_err); +int iSetSMMC_F_MC_CACHE_ERR_mc_data3_2b_ecc_merr(unsigned int umc_data3_2b_ecc_merr); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag0_1b_ecc_err_mask(unsigned int umc_tag0_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag0_2b_ecc_err_mask(unsigned int umc_tag0_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag1_1b_ecc_err_mask(unsigned int umc_tag1_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag1_2b_ecc_err_mask(unsigned int umc_tag1_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag2_1b_ecc_err_mask(unsigned int umc_tag2_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag2_2b_ecc_err_mask(unsigned int umc_tag2_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag3_1b_ecc_err_mask(unsigned int umc_tag3_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_tag3_2b_ecc_err_mask(unsigned int umc_tag3_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data0_1b_ecc_err_mask(unsigned int umc_data0_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data0_2b_ecc_err_mask(unsigned int umc_data0_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data1_1b_ecc_err_mask(unsigned int umc_data1_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data1_2b_ecc_err_mask(unsigned int umc_data1_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data2_1b_ecc_err_mask(unsigned int umc_data2_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data2_2b_ecc_err_mask(unsigned int umc_data2_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data3_1b_ecc_err_mask(unsigned int umc_data3_1b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_MASK_mc_data3_2b_ecc_err_mask(unsigned int umc_data3_2b_ecc_err_mask); +int iSetSMMC_F_MC_CACHE_ERR_INFO_mc_cache_err_info(unsigned int umc_cache_err_info); +int iSetSMMC_F_BUFFER_ERR_mc_qu_vfa_1b_ecc_err(unsigned int umc_qu_vfa_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_vfa_1b_ecc_merr(unsigned int umc_qu_vfa_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_vfa_2b_ecc_err(unsigned int umc_qu_vfa_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_vfa_2b_ecc_merr(unsigned int umc_qu_vfa_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_eng_stbuf_1b_ecc_err(unsigned int umc_eng_stbuf_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_eng_stbuf_1b_ecc_merr(unsigned int umc_eng_stbuf_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_eng_stbuf_2b_ecc_err(unsigned int umc_eng_stbuf_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_eng_stbuf_2b_ecc_merr(unsigned int umc_eng_stbuf_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_stbuf_1b_ecc_err(unsigned int umc_qu_stbuf_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_stbuf_1b_ecc_merr(unsigned int umc_qu_stbuf_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_stbuf_2b_ecc_err(unsigned int umc_qu_stbuf_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_stbuf_2b_ecc_merr(unsigned int umc_qu_stbuf_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_lrn_1b_ecc_err(unsigned int umc_qu_lrn_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_lrn_1b_ecc_merr(unsigned int umc_qu_lrn_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_lrn_2b_ecc_err(unsigned int umc_qu_lrn_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_lrn_2b_ecc_merr(unsigned int umc_qu_lrn_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_datafifo_1b_ecc_err(unsigned int umc_qu_datafifo_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_datafifo_1b_ecc_merr(unsigned int umc_qu_datafifo_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_qu_datafifo_2b_ecc_err(unsigned int umc_qu_datafifo_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_qu_datafifo_2b_ecc_merr(unsigned int umc_qu_datafifo_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_rfbuf_1b_ecc_err(unsigned int umc_rfbuf_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_rfbuf_1b_ecc_merr(unsigned int umc_rfbuf_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_mc_rfbuf_2b_ecc_err(unsigned int umc_rfbuf_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_mc_rfbuf_2b_ecc_merr(unsigned int umc_rfbuf_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_vc_smxtf_buf_1b_ecc_err(unsigned int uvc_smxtf_buf_1b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_vc_smxtf_buf_1b_ecc_merr(unsigned int uvc_smxtf_buf_1b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_vc_smxtf_buf_2b_ecc_err(unsigned int uvc_smxtf_buf_2b_ecc_err); +int iSetSMMC_F_BUFFER_ERR_vc_smxtf_buf_2b_ecc_merr(unsigned int uvc_smxtf_buf_2b_ecc_merr); +int iSetSMMC_F_BUFFER_ERR_directwqe_err(unsigned int udirectwqe_err); +int iSetSMMC_F_BUFFER_ERR_directwqe_merr(unsigned int udirectwqe_merr); +int iSetSMMC_F_BUFFER_ERR_fifo_ovf_err(unsigned int ufifo_ovf_err); +int iSetSMMC_F_BUFFER_ERR_fifo_ovf_merr(unsigned int ufifo_ovf_merr); +int iSetSMMC_F_BUFFER_MASK_mc_qu_vfa_1b_ecc_err_mask(unsigned int umc_qu_vfa_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_vfa_2b_ecc_err_mask(unsigned int umc_qu_vfa_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_eng_stbuf_1b_ecc_err_mask(unsigned int umc_eng_stbuf_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_eng_stbuf_2b_ecc_err_mask(unsigned int umc_eng_stbuf_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_stbuf_1b_ecc_err_mask(unsigned int umc_qu_stbuf_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_stbuf_2b_ecc_err_mask(unsigned int umc_qu_stbuf_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_lrn_1b_ecc_err_mask(unsigned int umc_qu_lrn_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_lrn_2b_ecc_err_mask(unsigned int umc_qu_lrn_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_datafifo_1b_ecc_err_mask(unsigned int umc_qu_datafifo_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_qu_datafifo_2b_ecc_err_mask(unsigned int umc_qu_datafifo_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_rfbuf_1b_ecc_err_mask(unsigned int umc_rfbuf_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_mc_rfbuf_2b_ecc_err_mask(unsigned int umc_rfbuf_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_vc_smxtf_buf_1b_ecc_err_mask(unsigned int uvc_smxtf_buf_1b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_vc_smxtf_buf_2b_ecc_err_mask(unsigned int uvc_smxtf_buf_2b_ecc_err_mask); +int iSetSMMC_F_BUFFER_MASK_directwqe_err_mask(unsigned int udirectwqe_err_mask); +int iSetSMMC_F_BUFFER_MASK_fifo_ovf_err_mask(unsigned int ufifo_ovf_err_mask); +int iSetSMMC_F_BUFFER_ERR_INFO_mc_buffer_err_info(unsigned int umc_buffer_err_info); +int iSetSMMC_F_BUS_ERR_mc_rf_timeout_err(unsigned int umc_rf_timeout_err); +int iSetSMMC_F_BUS_ERR_mc_rf_timeout_merr(unsigned int umc_rf_timeout_merr); +int iSetSMMC_F_BUS_ERR_mc_rf_rtn_err(unsigned int umc_rf_rtn_err); +int iSetSMMC_F_BUS_ERR_mc_rf_rtn_merr(unsigned int umc_rf_rtn_merr); +int iSetSMMC_F_BUS_ERR_qpc_ring_e01_err(unsigned int uqpc_ring_e01_err); +int iSetSMMC_F_BUS_ERR_qpc_ring_e01_merr(unsigned int uqpc_ring_e01_merr); +int iSetSMMC_F_BUS_ERR_qu_lrn_fifo_1bit_ecc_err(unsigned int uqu_lrn_fifo_1bit_ecc_err); +int iSetSMMC_F_BUS_ERR_qu_lrn_fifo_1bit_ecc_merr(unsigned int uqu_lrn_fifo_1bit_ecc_merr); +int iSetSMMC_F_BUS_ERR_qu_lrn_fifo_2bit_ecc_err(unsigned int uqu_lrn_fifo_2bit_ecc_err); +int iSetSMMC_F_BUS_ERR_qu_lrn_fifo_2bit_ecc_merr(unsigned int uqu_lrn_fifo_2bit_ecc_merr); +int iSetSMMC_F_BUS_MASK_mc_rf_timeout_err_mask(unsigned int umc_rf_timeout_err_mask); +int iSetSMMC_F_BUS_MASK_mc_rf_rtn_err_mask(unsigned int umc_rf_rtn_err_mask); +int iSetSMMC_F_BUS_MASK_qpc_ring_e01_err_mask(unsigned int uqpc_ring_e01_err_mask); +int iSetSMMC_F_BUS_MASK_qu_lrn_fifo_1bit_ecc_err_mask(unsigned int uqu_lrn_fifo_1bit_ecc_err_mask); +int iSetSMMC_F_BUS_MASK_qu_lrn_fifo_2bit_ecc_err_mask(unsigned int uqu_lrn_fifo_2bit_ecc_err_mask); +int iSetSMMC_F_MC_MULTI_HIT_ERR_error_bit(unsigned int uerror_bit); +int iSetSMMC_F_MC_MULTI_HIT_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMMC_F_MC_MULTI_HIT_ERR_sticky(unsigned int usticky); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb0_1b_ecc_err(unsigned int uvc_wb0_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb0_1b_ecc_merr(unsigned int uvc_wb0_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb0_2b_ecc_err(unsigned int uvc_wb0_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb0_2b_ecc_merr(unsigned int uvc_wb0_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb1_1b_ecc_err(unsigned int uvc_wb1_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb1_1b_ecc_merr(unsigned int uvc_wb1_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb1_2b_ecc_err(unsigned int uvc_wb1_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb1_2b_ecc_merr(unsigned int uvc_wb1_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb2_1b_ecc_err(unsigned int uvc_wb2_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb2_1b_ecc_merr(unsigned int uvc_wb2_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb2_2b_ecc_err(unsigned int uvc_wb2_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb2_2b_ecc_merr(unsigned int uvc_wb2_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb3_1b_ecc_err(unsigned int uvc_wb3_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb3_1b_ecc_merr(unsigned int uvc_wb3_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb3_2b_ecc_err(unsigned int uvc_wb3_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_wb3_2b_ecc_merr(unsigned int uvc_wb3_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data0_1b_ecc_err(unsigned int uvc_data0_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data0_1b_ecc_merr(unsigned int uvc_data0_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data0_2b_ecc_err(unsigned int uvc_data0_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data0_2b_ecc_merr(unsigned int uvc_data0_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data1_1b_ecc_err(unsigned int uvc_data1_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data1_1b_ecc_merr(unsigned int uvc_data1_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data1_2b_ecc_err(unsigned int uvc_data1_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data1_2b_ecc_merr(unsigned int uvc_data1_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data2_1b_ecc_err(unsigned int uvc_data2_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data2_1b_ecc_merr(unsigned int uvc_data2_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data2_2b_ecc_err(unsigned int uvc_data2_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data2_2b_ecc_merr(unsigned int uvc_data2_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data3_1b_ecc_err(unsigned int uvc_data3_1b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data3_1b_ecc_merr(unsigned int uvc_data3_1b_ecc_merr); +int iSetSMMC_F_VC_CACHE_ERR_vc_data3_2b_ecc_err(unsigned int uvc_data3_2b_ecc_err); +int iSetSMMC_F_VC_CACHE_ERR_vc_data3_2b_ecc_merr(unsigned int uvc_data3_2b_ecc_merr); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb0_1b_ecc_err_mask(unsigned int uvc_wb0_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb0_2b_ecc_err_mask(unsigned int uvc_wb0_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb1_1b_ecc_err_mask(unsigned int uvc_wb1_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb1_2b_ecc_err_mask(unsigned int uvc_wb1_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb2_1b_ecc_err_mask(unsigned int uvc_wb2_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb2_2b_ecc_err_mask(unsigned int uvc_wb2_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb3_1b_ecc_err_mask(unsigned int uvc_wb3_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_wb3_2b_ecc_err_mask(unsigned int uvc_wb3_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data0_1b_ecc_err_mask(unsigned int uvc_data0_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data0_2b_ecc_err_mask(unsigned int uvc_data0_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data1_1b_ecc_err_mask(unsigned int uvc_data1_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data1_2b_ecc_err_mask(unsigned int uvc_data1_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data2_1b_ecc_err_mask(unsigned int uvc_data2_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data2_2b_ecc_err_mask(unsigned int uvc_data2_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data3_1b_ecc_err_mask(unsigned int uvc_data3_1b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_MASK_vc_data3_2b_ecc_err_mask(unsigned int uvc_data3_2b_ecc_err_mask); +int iSetSMMC_F_VC_CACHE_ERR_INFO_vc_cache_err_info(unsigned int uvc_cache_err_info); +int iSetSMMC_F_INDRECT_CTRL_smmc_f_indir_addr(unsigned int usmmc_f_indir_addr); +int iSetSMMC_F_INDRECT_CTRL_smmc_f_indir_tab(unsigned int usmmc_f_indir_tab); +int iSetSMMC_F_INDRECT_CTRL_smmc_f_indir_stat(unsigned int usmmc_f_indir_stat); +int iSetSMMC_F_INDRECT_CTRL_smmc_f_indir_mode(unsigned int usmmc_f_indir_mode); +int iSetSMMC_F_INDRECT_CTRL_smmc_f_indir_vld(unsigned int usmmc_f_indir_vld); +int iSetSMMC_F_INDRECT_TIMEOUT_smmc_f_indir_timeout(unsigned int usmmc_f_indir_timeout); +int iSetSMMC_F_INDRECT_DATA_smmc_f_indir_data(unsigned int usmmc_f_indir_data); +int iSetSMMC_F_MC_CNT_ENB_smmc_f_mc_cnt_enb(unsigned int usmmc_f_mc_cnt_enb); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_smmc_f_mc_cnt_event_sel_enb0(unsigned int usmmc_f_mc_cnt_event_sel_enb0); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_smmc_f_mc_cnt_event_sel_enb1(unsigned int usmmc_f_mc_cnt_event_sel_enb1); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_smmc_f_mc_cnt_event_sel_enb2(unsigned int usmmc_f_mc_cnt_event_sel_enb2); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP0_smmc_f_mc_cnt_event_sel_enb3(unsigned int usmmc_f_mc_cnt_event_sel_enb3); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_smmc_f_mc_cnt_event_sel_enb4(unsigned int usmmc_f_mc_cnt_event_sel_enb4); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_smmc_f_mc_cnt_event_sel_enb5(unsigned int usmmc_f_mc_cnt_event_sel_enb5); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_smmc_f_mc_cnt_event_sel_enb6(unsigned int usmmc_f_mc_cnt_event_sel_enb6); +int iSetSMMC_F_MC_CNT_EVENT_SEL_ENB_GRP1_smmc_f_mc_cnt_event_sel_enb7(unsigned int usmmc_f_mc_cnt_event_sel_enb7); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_vf_id(unsigned int umc_cnt_event_sel0_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_tag_type(unsigned int umc_cnt_event_sel0_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_bank_id(unsigned int umc_cnt_event_sel0_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_req_src(unsigned int umc_cnt_event_sel0_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_api_type(unsigned int umc_cnt_event_sel0_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_event_type(unsigned int umc_cnt_event_sel0_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL0_mc_cnt_event_sel0_unit_type(unsigned int umc_cnt_event_sel0_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_vf_id(unsigned int umc_cnt_event_sel1_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_tag_type(unsigned int umc_cnt_event_sel1_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_bank_id(unsigned int umc_cnt_event_sel1_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_req_src(unsigned int umc_cnt_event_sel1_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_api_type(unsigned int umc_cnt_event_sel1_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_event_type(unsigned int umc_cnt_event_sel1_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL1_mc_cnt_event_sel1_unit_type(unsigned int umc_cnt_event_sel1_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_vf_id(unsigned int umc_cnt_event_sel2_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_tag_type(unsigned int umc_cnt_event_sel2_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_bank_id(unsigned int umc_cnt_event_sel2_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_req_src(unsigned int umc_cnt_event_sel2_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_api_type(unsigned int umc_cnt_event_sel2_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_event_type(unsigned int umc_cnt_event_sel2_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL2_mc_cnt_event_sel2_unit_type(unsigned int umc_cnt_event_sel2_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_vf_id(unsigned int umc_cnt_event_sel3_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_tag_type(unsigned int umc_cnt_event_sel3_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_bank_id(unsigned int umc_cnt_event_sel3_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_req_src(unsigned int umc_cnt_event_sel3_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_api_type(unsigned int umc_cnt_event_sel3_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_event_type(unsigned int umc_cnt_event_sel3_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL3_mc_cnt_event_sel3_unit_type(unsigned int umc_cnt_event_sel3_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_vf_id(unsigned int umc_cnt_event_sel4_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_tag_type(unsigned int umc_cnt_event_sel4_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_bank_id(unsigned int umc_cnt_event_sel4_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_req_src(unsigned int umc_cnt_event_sel4_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_api_type(unsigned int umc_cnt_event_sel4_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_event_type(unsigned int umc_cnt_event_sel4_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL4_mc_cnt_event_sel4_unit_type(unsigned int umc_cnt_event_sel4_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_vf_id(unsigned int umc_cnt_event_sel5_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_tag_type(unsigned int umc_cnt_event_sel5_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_bank_id(unsigned int umc_cnt_event_sel5_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_req_src(unsigned int umc_cnt_event_sel5_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_api_type(unsigned int umc_cnt_event_sel5_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_event_type(unsigned int umc_cnt_event_sel5_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL5_mc_cnt_event_sel5_unit_type(unsigned int umc_cnt_event_sel5_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_vf_id(unsigned int umc_cnt_event_sel6_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_tag_type(unsigned int umc_cnt_event_sel6_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_bank_id(unsigned int umc_cnt_event_sel6_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_req_src(unsigned int umc_cnt_event_sel6_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_api_type(unsigned int umc_cnt_event_sel6_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_event_type(unsigned int umc_cnt_event_sel6_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL6_mc_cnt_event_sel6_unit_type(unsigned int umc_cnt_event_sel6_unit_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_vf_id(unsigned int umc_cnt_event_sel7_vf_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_tag_type(unsigned int umc_cnt_event_sel7_tag_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_bank_id(unsigned int umc_cnt_event_sel7_bank_id); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_req_src(unsigned int umc_cnt_event_sel7_req_src); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_api_type(unsigned int umc_cnt_event_sel7_api_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_event_type(unsigned int umc_cnt_event_sel7_event_type); +int iSetSMMC_F_MC_CNT_EVENT_SEL7_mc_cnt_event_sel7_unit_type(unsigned int umc_cnt_event_sel7_unit_type); +int iSetSMMC_F_MC_STATUS_mc_init_done(unsigned int umc_init_done); +int iSetSMMC_F_MC_STATUS_mc_free_tag_num(unsigned int umc_free_tag_num); +int iSetSMMC_F_MC_STATUS_qu_rx_flit_ctp_done(unsigned int uqu_rx_flit_ctp_done); +int iSetSMMC_F_MC_STATUS_qu_tx_flit_ctp_done(unsigned int uqu_tx_flit_ctp_done); +int iSetSMMC_F_MC_STATUS_smmc_rf_timeout(unsigned int usmmc_rf_timeout); +int iSetSMMC_F_MC_CNT0_smmc_f_mc_cnt0(unsigned int usmmc_f_mc_cnt0); +int iSetSMMC_F_MC_CNT1_smmc_f_mc_cnt1(unsigned int usmmc_f_mc_cnt1); +int iSetSMMC_F_MC_CNT2_smmc_f_mc_cnt2(unsigned int usmmc_f_mc_cnt2); +int iSetSMMC_F_MC_CNT3_smmc_f_mc_cnt3(unsigned int usmmc_f_mc_cnt3); +int iSetSMMC_F_MC_CNT4_smmc_f_mc_cnt4(unsigned int usmmc_f_mc_cnt4); +int iSetSMMC_F_MC_CNT5_smmc_f_mc_cnt5(unsigned int usmmc_f_mc_cnt5); +int iSetSMMC_F_MC_CNT6_smmc_f_mc_cnt6(unsigned int usmmc_f_mc_cnt6); +int iSetSMMC_F_MC_CNT7_smmc_f_mc_cnt7(unsigned int usmmc_f_mc_cnt7); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc0_wb_data_fifo_depth(unsigned int uvc0_wb_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc1_wb_data_fifo_depth(unsigned int uvc1_wb_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc2_wb_data_fifo_depth(unsigned int uvc2_wb_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc3_wb_data_fifo_depth(unsigned int uvc3_wb_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc0_wb_ctrl_fifo_depth(unsigned int uvc0_wb_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc1_wb_ctrl_fifo_depth(unsigned int uvc1_wb_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc2_wb_ctrl_fifo_depth(unsigned int uvc2_wb_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH0_vc3_wb_ctrl_fifo_depth(unsigned int uvc3_wb_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc0_ctrl_fifo_depth(unsigned int uvc0_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc1_ctrl_fifo_depth(unsigned int uvc1_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc2_ctrl_fifo_depth(unsigned int uvc2_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc3_ctrl_fifo_depth(unsigned int uvc3_ctrl_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc0_data_fifo_depth(unsigned int uvc0_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc1_data_fifo_depth(unsigned int uvc1_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc2_data_fifo_depth(unsigned int uvc2_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc3_data_fifo_depth(unsigned int uvc3_data_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_smxtf_fifo_depth(unsigned int usmxtf_fifo_depth); +int iSetSMMC_F_VC_FIFO_DEPTH1_vc_crdt_from_smit(unsigned int uvc_crdt_from_smit); +int iSetSMMC_F_VC_FIFO_DEPTH1_data_credit_from_qu(unsigned int udata_credit_from_qu); +int iSetSMMC_F_MC_FIFO1_DEPTH_qu_cmd_fifo_depth(unsigned int uqu_cmd_fifo_depth); +int iSetSMMC_F_MC_FIFO1_DEPTH_qu_data_fifo_depth(unsigned int uqu_data_fifo_depth); +int iSetSMMC_F_MC_FIFO1_DEPTH_lrb0_fifo_depth(unsigned int ulrb0_fifo_depth); +int iSetSMMC_F_MC_FIFO1_DEPTH_lrb1_fifo_depth(unsigned int ulrb1_fifo_depth); +int iSetSMMC_F_MC_FIFO1_DEPTH_lrb2_fifo_depth(unsigned int ulrb2_fifo_depth); +int iSetSMMC_F_MC_FIFO2_DEPTH_qu_return_fifo_depth(unsigned int uqu_return_fifo_depth); +int iSetSMMC_F_MC_FIFO2_DEPTH_qu_return_fifo_bp(unsigned int uqu_return_fifo_bp); +int iSetSMMC_F_MC_FIFO2_DEPTH_qu_store_buffer_bp(unsigned int uqu_store_buffer_bp); +int iSetSMMC_F_MC_FIFO2_DEPTH_lrb3_fifo_depth(unsigned int ulrb3_fifo_depth); +int iSetSMMC_F_MC_FIFO2_DEPTH_rfbuf_credit(unsigned int urfbuf_credit); +int iSetSMMC_F_MC_FIFO2_DEPTH_qu_store_buffer_depth(unsigned int uqu_store_buffer_depth); +int iSetSMMC_F_ERR_INJ_smmc_vc0_crt_err_inj(unsigned int usmmc_vc0_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc0_uncrt_err_inj(unsigned int usmmc_vc0_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc1_crt_err_inj(unsigned int usmmc_vc1_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc1_uncrt_err_inj(unsigned int usmmc_vc1_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc2_crt_err_inj(unsigned int usmmc_vc2_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc2_uncrt_err_inj(unsigned int usmmc_vc2_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc3_crt_err_inj(unsigned int usmmc_vc3_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vc3_uncrt_err_inj(unsigned int usmmc_vc3_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc0_crt_err_inj(unsigned int usmmc_mc0_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc0_uncrt_err_inj(unsigned int usmmc_mc0_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc1_crt_err_inj(unsigned int usmmc_mc1_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc1_uncrt_err_inj(unsigned int usmmc_mc1_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc2_crt_err_inj(unsigned int usmmc_mc2_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc2_uncrt_err_inj(unsigned int usmmc_mc2_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc3_crt_err_inj(unsigned int usmmc_mc3_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_mc3_uncrt_err_inj(unsigned int usmmc_mc3_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_qu_intf_crt_err_inj(unsigned int usmmc_qu_intf_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_qu_intf_uncrt_err_inj(unsigned int usmmc_qu_intf_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_rf_buf_crt_err_inj(unsigned int usmmc_rf_buf_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_rf_buf_uncrt_err_inj(unsigned int usmmc_rf_buf_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vfa_crt_err_inj(unsigned int usmmc_vfa_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_vfa_uncrt_err_inj(unsigned int usmmc_vfa_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_stb_crt_err_inj(unsigned int usmmc_stb_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_stb_uncrt_err_inj(unsigned int usmmc_stb_uncrt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_smxtfb_crt_err_inj(unsigned int usmmc_smxtfb_crt_err_inj); +int iSetSMMC_F_ERR_INJ_smmc_smxtfb_uncrt_err_inj(unsigned int usmmc_smxtfb_uncrt_err_inj); +int iSetSMMC_F_GPA_TRANS_ERR_error_bit(unsigned int uerror_bit); +int iSetSMMC_F_GPA_TRANS_ERR_multi_error_bit(unsigned int umulti_error_bit); +int iSetSMMC_F_GPA_TRANS_ERR_sticky(unsigned int usticky); +int iSetSMMC_F_QU_INTF_CNT_CFG_smmc_f_qu_intf_tx_cnt_cfg(unsigned int usmmc_f_qu_intf_tx_cnt_cfg); +int iSetSMMC_F_QU_INTF_CNT_CFG_smmc_f_qu_intf_rx_cnt_cfg(unsigned int usmmc_f_qu_intf_rx_cnt_cfg); +int iSetSMMC_F_QU_INTF_RX_CNT_smmc_f_qu_intf_rx_cnt(unsigned int usmmc_f_qu_intf_rx_cnt); +int iSetSMMC_F_QU_INTF_TX_CNT_smmc_f_qu_intf_tx_cnt(unsigned int usmmc_f_qu_intf_tx_cnt); +int iSetSMMC_F_MC_CFG2_smmc_f_rsc_cnt_mix_en(unsigned int usmmc_f_rsc_cnt_mix_en); +int iSetSMMC_F_MC_CFG2_smmc_f_rtt_cnt_type(unsigned int usmmc_f_rtt_cnt_type); +int iSetSMMC_F_MC_CFG2_smmc_f_rtt_cnt_enb(unsigned int usmmc_f_rtt_cnt_enb); +int iSetSMMC_F_MC_CFG2_smmc_f_rf_err_ctp_clr(unsigned int usmmc_f_rf_err_ctp_clr); +int iSetSMMC_F_MC_CFG2_smf_common_mem_power_mode(unsigned int usmf_common_mem_power_mode); +int iSetSMMC_F_MC_CFG2_mc_refill_timeout_enb(unsigned int umc_refill_timeout_enb); +int iSetSMMC_F_MC_CFG2_bypass_smvc(unsigned int ubypass_smvc); + +/* Define the union csr_smmc_l_version_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_version : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_version_u; + +/* Define the union csr_smmc_l_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_parity_chk : 1; /* [0] */ + u32 smmc_l_ecc_chk : 1; /* [1] */ + u32 mem_ini_en : 1; /* [2] */ + u32 rsv_0 : 13; /* [15:3] */ + u32 sp_ram_tmod : 7; /* [22:16] */ + u32 mem_ret1n : 1; /* [23] */ + u32 sp_ram_tmod_div2 : 7; /* [30:24] */ + u32 mem_ret1n_div2 : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cfg_u; + +/* Define the union csr_smmc_l_stat_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_ini_done : 1; /* [0] */ + u32 rsv_1 : 31; /* [31:1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_stat_u; + +/* Define the union csr_smmc_l_int_vector_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cpi_int_index : 24; /* [23:0] */ + u32 rsv_2 : 3; /* [26:24] */ + u32 enable : 1; /* [27] */ + u32 int_issue : 1; /* [28] */ + u32 rsv_3 : 3; /* [31:29] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_int_vector_u; + +/* Define the union csr_smmc_l_int_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 int_data : 1; /* [0] */ + u32 rsv_4 : 15; /* [15:1] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_int_u; + +/* Define the union csr_smmc_l_int_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 err_mask : 1; /* [0] */ + u32 rsv_5 : 15; /* [15:1] */ + u32 program_csr_id : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_int_mask_u; + +/* Define the union csr_smmc_l_mem_err_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 main_mem_2b_ecc_err : 1; /* [0] */ + u32 main_mem_2b_ecc_merr : 1; /* [1] */ + u32 main_mem_1b_ecc_err : 1; /* [2] */ + u32 main_mem_1b_ecc_merr : 1; /* [3] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_mem_err_u; + +/* Define the union csr_smmc_l_mem_err_mask_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 main_mem_2b_ecc_err_mask : 1; /* [0] */ + u32 main_mem_1b_ecc_err_mask : 1; /* [1] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_mem_err_mask_u; + +/* Define the union csr_smmc_l_mem_err_info_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 mem_err_index : 15; /* [14:0] */ + u32 rsv_6 : 1; /* [15] */ + u32 mem_err_info_type : 2; /* [17:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_mem_err_info_u; + +/* Define the union csr_smmc_l_indrect_ctrl_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_indir_addr : 24; /* [23:0] */ + u32 smmc_l_indir_tab : 4; /* [27:24] */ + u32 smmc_l_indir_stat : 2; /* [29:28] */ + u32 smmc_l_indir_mode : 1; /* [30] */ + u32 smmc_l_indir_vld : 1; /* [31] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_indrect_ctrl_u; + +/* Define the union csr_smmc_l_indrect_timeout_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_indir_timeout : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_indrect_timeout_u; + +/* Define the union csr_smmc_l_indrect_data_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_f_indir_data : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_indrect_data_u; + +/* Define the union csr_smmc_l_cnt_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_enable : 1; /* [0] */ + u32 cnt1_enable : 1; /* [1] */ + u32 cnt2_enable : 1; /* [2] */ + u32 cnt3_enable : 1; /* [3] */ + u32 cnt0_match_en : 2; /* [5:4] */ + u32 cnt1_match_en : 2; /* [7:6] */ + u32 cnt2_match_en : 2; /* [9:8] */ + u32 cnt3_match_en : 2; /* [11:10] */ + u32 cnt0_sel : 2; /* [13:12] */ + u32 cnt1_sel : 2; /* [15:14] */ + u32 cnt2_sel : 2; /* [17:16] */ + u32 cnt3_sel : 2; /* [19:18] */ + u32 rsv_7 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt_cfg_u; + +/* Define the union csr_smmc_l_cnt_match_bank_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_match_bank : 4; /* [3:0] */ + u32 cnt1_match_bank : 4; /* [7:4] */ + u32 cnt2_match_bank : 4; /* [11:8] */ + u32 cnt3_match_bank : 4; /* [15:12] */ + u32 rsv_8 : 16; /* [31:16] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt_match_bank_u; + +/* Define the union csr_smmc_l_cnt_match_instance_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cnt0_match_inst : 5; /* [4:0] */ + u32 cnt1_match_inst : 5; /* [9:5] */ + u32 cnt2_match_inst : 5; /* [14:10] */ + u32 cnt3_match_inst : 5; /* [19:15] */ + u32 rsv_9 : 12; /* [31:20] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt_match_instance_u; + +/* Define the union csr_smmc_l_cnt0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_cnt0 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt0_u; + +/* Define the union csr_smmc_l_cnt1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_cnt1 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt1_u; + +/* Define the union csr_smmc_l_cnt2_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_cnt2 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt2_u; + +/* Define the union csr_smmc_l_cnt3_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_cnt3 : 32; /* [31:0] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_cnt3_u; + +/* Define the union csr_smmc_l_bank_queue_depth_ctp0_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_depth_bank0 : 4; /* [3:0] */ + u32 cur_depth_bank1 : 4; /* [7:4] */ + u32 cur_depth_bank2 : 4; /* [11:8] */ + u32 cur_depth_bank3 : 4; /* [15:12] */ + u32 cur_depth_bank4 : 4; /* [19:16] */ + u32 cur_depth_bank5 : 4; /* [23:20] */ + u32 cur_depth_bank6 : 4; /* [27:24] */ + u32 cur_depth_bank7 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_bank_queue_depth_ctp0_u; + +/* Define the union csr_smmc_l_bank_queue_depth_ctp1_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 cur_depth_bank8 : 4; /* [3:0] */ + u32 cur_depth_bank9 : 4; /* [7:4] */ + u32 cur_depth_bank10 : 4; /* [11:8] */ + u32 cur_depth_bank11 : 4; /* [15:12] */ + u32 cur_depth_bank12 : 4; /* [19:16] */ + u32 cur_depth_bank13 : 4; /* [23:20] */ + u32 cur_depth_bank14 : 4; /* [27:24] */ + u32 cur_depth_bank15 : 4; /* [31:28] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_bank_queue_depth_ctp1_u; + +/* Define the union csr_smmc_l_ecc_inj_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_1b_ecc_inj_en : 1; /* [0] */ + u32 smmc_l_2b_ecc_inj_en : 1; /* [1] */ + u32 rsv_10 : 30; /* [31:2] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_ecc_inj_cfg_u; + +/* Define the union csr_smmc_l_pg_cfg_u */ +typedef union { + /* Define the struct bits */ + struct { + u32 smmc_l_pg_grp1_id : 2; /* [1:0] */ + u32 smmc_l_pg_grp0_id : 2; /* [3:2] */ + u32 smmc_l_pg_grp_num : 1; /* [4] */ + u32 rsv_11 : 27; /* [31:5] */ + } bits; + + /* Define an unsigned member */ + u32 value; +} csr_smmc_l_pg_cfg_u; + + +// ============================================================================== +/* Define the global struct */ +typedef struct { + volatile csr_smmc_l_version_u smmc_l_version; /* 0 */ + volatile csr_smmc_l_cfg_u smmc_l_cfg; /* 4 */ + volatile csr_smmc_l_stat_u smmc_l_stat; /* 8 */ + volatile csr_smmc_l_int_vector_u smmc_l_int_vector; /* C */ + volatile csr_smmc_l_int_u smmc_l_int; /* 10 */ + volatile csr_smmc_l_int_mask_u smmc_l_int_mask; /* 14 */ + volatile csr_smmc_l_mem_err_u smmc_l_mem_err; /* 18 */ + volatile csr_smmc_l_mem_err_mask_u smmc_l_mem_err_mask; /* 1C */ + volatile csr_smmc_l_mem_err_info_u smmc_l_mem_err_info; /* 20 */ + volatile csr_smmc_l_indrect_ctrl_u smmc_l_indrect_ctrl; /* 24 */ + volatile csr_smmc_l_indrect_timeout_u smmc_l_indrect_timeout; /* 28 */ + volatile csr_smmc_l_indrect_data_u smmc_l_indrect_data; /* 2C */ + volatile csr_smmc_l_cnt_cfg_u smmc_l_cnt_cfg; /* 30 */ + volatile csr_smmc_l_cnt_match_bank_u smmc_l_cnt_match_bank; /* 34 */ + volatile csr_smmc_l_cnt_match_instance_u smmc_l_cnt_match_instance; /* 38 */ + volatile csr_smmc_l_cnt0_u smmc_l_cnt0; /* 3C */ + volatile csr_smmc_l_cnt1_u smmc_l_cnt1; /* 40 */ + volatile csr_smmc_l_cnt2_u smmc_l_cnt2; /* 44 */ + volatile csr_smmc_l_cnt3_u smmc_l_cnt3; /* 48 */ + volatile csr_smmc_l_bank_queue_depth_ctp0_u smmc_l_bank_queue_depth_ctp0; /* 4C */ + volatile csr_smmc_l_bank_queue_depth_ctp1_u smmc_l_bank_queue_depth_ctp1; /* 50 */ + volatile csr_smmc_l_ecc_inj_cfg_u smmc_l_ecc_inj_cfg; /* 54 */ + volatile csr_smmc_l_pg_cfg_u smmc_l_pg_cfg; /* 58 */ +} S_smmc_l_csr_REGS_TYPE; + +/* Declare the struct pointor of the module smmc_l_csr */ +extern volatile S_smmc_l_csr_REGS_TYPE *gopsmmc_l_csrAllReg; + +/* Declare the functions that set the member value */ +int iSetSMMC_L_VERSION_smmc_l_version(unsigned int usmmc_l_version); +int iSetSMMC_L_CFG_smmc_l_parity_chk(unsigned int usmmc_l_parity_chk); +int iSetSMMC_L_CFG_smmc_l_ecc_chk(unsigned int usmmc_l_ecc_chk); +int iSetSMMC_L_CFG_mem_ini_en(unsigned int umem_ini_en); +int iSetSMMC_L_CFG_sp_ram_tmod(unsigned int usp_ram_tmod); +int iSetSMMC_L_CFG_mem_ret1n(unsigned int umem_ret1n); +int iSetSMMC_L_CFG_sp_ram_tmod_div2(unsigned int usp_ram_tmod_div2); +int iSetSMMC_L_CFG_mem_ret1n_div2(unsigned int umem_ret1n_div2); +int iSetSMMC_L_STAT_mem_ini_done(unsigned int umem_ini_done); +int iSetSMMC_L_INT_VECTOR_cpi_int_index(unsigned int ucpi_int_index); +int iSetSMMC_L_INT_VECTOR_enable(unsigned int uenable); +int iSetSMMC_L_INT_VECTOR_int_issue(unsigned int uint_issue); +int iSetSMMC_L_INT_int_data(unsigned int uint_data); +int iSetSMMC_L_INT_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMMC_L_INT_MASK_err_mask(unsigned int uerr_mask); +int iSetSMMC_L_INT_MASK_program_csr_id(unsigned int uprogram_csr_id); +int iSetSMMC_L_MEM_ERR_main_mem_2b_ecc_err(unsigned int umain_mem_2b_ecc_err); +int iSetSMMC_L_MEM_ERR_main_mem_2b_ecc_merr(unsigned int umain_mem_2b_ecc_merr); +int iSetSMMC_L_MEM_ERR_main_mem_1b_ecc_err(unsigned int umain_mem_1b_ecc_err); +int iSetSMMC_L_MEM_ERR_main_mem_1b_ecc_merr(unsigned int umain_mem_1b_ecc_merr); +int iSetSMMC_L_MEM_ERR_MASK_main_mem_2b_ecc_err_mask(unsigned int umain_mem_2b_ecc_err_mask); +int iSetSMMC_L_MEM_ERR_MASK_main_mem_1b_ecc_err_mask(unsigned int umain_mem_1b_ecc_err_mask); +int iSetSMMC_L_MEM_ERR_INFO_mem_err_index(unsigned int umem_err_index); +int iSetSMMC_L_MEM_ERR_INFO_mem_err_info_type(unsigned int umem_err_info_type); +int iSetSMMC_L_INDRECT_CTRL_smmc_l_indir_addr(unsigned int usmmc_l_indir_addr); +int iSetSMMC_L_INDRECT_CTRL_smmc_l_indir_tab(unsigned int usmmc_l_indir_tab); +int iSetSMMC_L_INDRECT_CTRL_smmc_l_indir_stat(unsigned int usmmc_l_indir_stat); +int iSetSMMC_L_INDRECT_CTRL_smmc_l_indir_mode(unsigned int usmmc_l_indir_mode); +int iSetSMMC_L_INDRECT_CTRL_smmc_l_indir_vld(unsigned int usmmc_l_indir_vld); +int iSetSMMC_L_INDRECT_TIMEOUT_smmc_l_indir_timeout(unsigned int usmmc_l_indir_timeout); +int iSetSMMC_L_INDRECT_DATA_smmc_f_indir_data(unsigned int usmmc_f_indir_data); +int iSetSMMC_L_CNT_CFG_cnt0_enable(unsigned int ucnt0_enable); +int iSetSMMC_L_CNT_CFG_cnt1_enable(unsigned int ucnt1_enable); +int iSetSMMC_L_CNT_CFG_cnt2_enable(unsigned int ucnt2_enable); +int iSetSMMC_L_CNT_CFG_cnt3_enable(unsigned int ucnt3_enable); +int iSetSMMC_L_CNT_CFG_cnt0_match_en(unsigned int ucnt0_match_en); +int iSetSMMC_L_CNT_CFG_cnt1_match_en(unsigned int ucnt1_match_en); +int iSetSMMC_L_CNT_CFG_cnt2_match_en(unsigned int ucnt2_match_en); +int iSetSMMC_L_CNT_CFG_cnt3_match_en(unsigned int ucnt3_match_en); +int iSetSMMC_L_CNT_CFG_cnt0_sel(unsigned int ucnt0_sel); +int iSetSMMC_L_CNT_CFG_cnt1_sel(unsigned int ucnt1_sel); +int iSetSMMC_L_CNT_CFG_cnt2_sel(unsigned int ucnt2_sel); +int iSetSMMC_L_CNT_CFG_cnt3_sel(unsigned int ucnt3_sel); +int iSetSMMC_L_CNT_MATCH_BANK_cnt0_match_bank(unsigned int ucnt0_match_bank); +int iSetSMMC_L_CNT_MATCH_BANK_cnt1_match_bank(unsigned int ucnt1_match_bank); +int iSetSMMC_L_CNT_MATCH_BANK_cnt2_match_bank(unsigned int ucnt2_match_bank); +int iSetSMMC_L_CNT_MATCH_BANK_cnt3_match_bank(unsigned int ucnt3_match_bank); +int iSetSMMC_L_CNT_MATCH_INSTANCE_cnt0_match_inst(unsigned int ucnt0_match_inst); +int iSetSMMC_L_CNT_MATCH_INSTANCE_cnt1_match_inst(unsigned int ucnt1_match_inst); +int iSetSMMC_L_CNT_MATCH_INSTANCE_cnt2_match_inst(unsigned int ucnt2_match_inst); +int iSetSMMC_L_CNT_MATCH_INSTANCE_cnt3_match_inst(unsigned int ucnt3_match_inst); +int iSetSMMC_L_CNT0_smmc_l_cnt0(unsigned int usmmc_l_cnt0); +int iSetSMMC_L_CNT1_smmc_l_cnt1(unsigned int usmmc_l_cnt1); +int iSetSMMC_L_CNT2_smmc_l_cnt2(unsigned int usmmc_l_cnt2); +int iSetSMMC_L_CNT3_smmc_l_cnt3(unsigned int usmmc_l_cnt3); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank0(unsigned int ucur_depth_bank0); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank1(unsigned int ucur_depth_bank1); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank2(unsigned int ucur_depth_bank2); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank3(unsigned int ucur_depth_bank3); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank4(unsigned int ucur_depth_bank4); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank5(unsigned int ucur_depth_bank5); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank6(unsigned int ucur_depth_bank6); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP0_cur_depth_bank7(unsigned int ucur_depth_bank7); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank8(unsigned int ucur_depth_bank8); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank9(unsigned int ucur_depth_bank9); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank10(unsigned int ucur_depth_bank10); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank11(unsigned int ucur_depth_bank11); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank12(unsigned int ucur_depth_bank12); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank13(unsigned int ucur_depth_bank13); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank14(unsigned int ucur_depth_bank14); +int iSetSMMC_L_BANK_QUEUE_DEPTH_CTP1_cur_depth_bank15(unsigned int ucur_depth_bank15); +int iSetSMMC_L_ECC_INJ_CFG_smmc_l_1b_ecc_inj_en(unsigned int usmmc_l_1b_ecc_inj_en); +int iSetSMMC_L_ECC_INJ_CFG_smmc_l_2b_ecc_inj_en(unsigned int usmmc_l_2b_ecc_inj_en); +int iSetSMMC_L_PG_CFG_smmc_l_pg_grp1_id(unsigned int usmmc_l_pg_grp1_id); +int iSetSMMC_L_PG_CFG_smmc_l_pg_grp0_id(unsigned int usmmc_l_pg_grp0_id); +int iSetSMMC_L_PG_CFG_smmc_l_pg_grp_num(unsigned int usmmc_l_pg_grp_num); + + +#endif // SM_C_UNION_DEFINE_H diff --git a/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_reg_offset.h b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_reg_offset.h new file mode 100644 index 000000000..66ebe8c62 --- /dev/null +++ b/drivers/infiniband/hw/hiroce3/include/hw/register/infra/sm_reg_offset.h @@ -0,0 +1,860 @@ +// ****************************************************************************** +// Copyright : Copyright (C) 2020, Hisilicon Technologies Co. Ltd. +// File name : hi1822_reg_offset.h +// Project line : IT Product Line +// Department : ICT Processor Chipset Development Department +// Version : V100 +// Date : +// Description : The description of xxx project +// Others : Generated automatically by nManager V5.1 +// file +// ****************************************************************************** + +#ifndef SM_REG_OFFSET_H +#define SM_REG_OFFSET_H + +/* smrt_csr Base address of Module's Register */ +#define CSR_SMRT_CSR_BASE (0xA00) + +/* **************************************************************************** */ +/* smrt_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMRT_CSR_SMRT_VERSION_REG (CSR_SMRT_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMRT_CSR_SMXR_CFG1_REG (CSR_SMRT_CSR_BASE + 0x4) /* SMXR cofigure registers */ +#define CSR_SMRT_CSR_SMXR_CFG0_REG (CSR_SMRT_CSR_BASE + 0x8) /* SMXR cofigure registers */ +#define CSR_SMRT_CSR_SMXT_CFG_REG \ + (CSR_SMRT_CSR_BASE + 0xC) /* This is the Smart Memory Infra Cross Transmission (SMXT) module configuration \ + register. The software use this register for debug. */ +#define CSR_SMRT_CSR_SMXR_TM_GRT01_REG (CSR_SMRT_CSR_BASE + 0x10) /* Timer Group Routing table element 0 and 1 */ +#define CSR_SMRT_CSR_SMXR_TM_GRT23_REG (CSR_SMRT_CSR_BASE + 0x14) /* Timer Group Routing table element 2 and 3 */ +#define CSR_SMRT_CSR_SMRT_INT_VECTOR_REG (CSR_SMRT_CSR_BASE + 0x18) +#define CSR_SMRT_CSR_SMRT_INT_REG (CSR_SMRT_CSR_BASE + 0x1C) /* SMRT interrupt data */ +#define CSR_SMRT_CSR_SMRT_INT_MASK_REG (CSR_SMRT_CSR_BASE + 0x20) /* SMIR interrupt mask configuration */ +#define CSR_SMRT_CSR_SMXR_REQ_MEM_CRT_ERR_REG \ + (CSR_SMRT_CSR_BASE + 0x24) /* ECC correctable memory detected on SMXR request memory */ +#define CSR_SMRT_CSR_SMXR_REQ_MEM_UNCRT_ERR_REG \ + (CSR_SMRT_CSR_BASE + 0x28) /* ECC un-correctable memory detected on SMXR request memory */ +#define CSR_SMRT_CSR_SMXR_MISS_SOP_EOP_ERR_REG (CSR_SMRT_CSR_BASE + 0x2C) /* SMXR received miss EOP API */ +#define CSR_SMRT_CSR_SMXR_INDRECT_CTRL_REG (CSR_SMRT_CSR_BASE + 0x30) /* indirect access address registers */ +#define CSR_SMRT_CSR_SMXR_INDRECT_TIMEOUT_REG (CSR_SMRT_CSR_BASE + 0x34) /* memory access timeout configure */ +#define CSR_SMRT_CSR_SMXR_INDRECT_DATA_REG (CSR_SMRT_CSR_BASE + 0x38) /* indirect access data registers */ +#define CSR_SMRT_CSR_SMXT_CAP_CFG_REG \ + (CSR_SMRT_CSR_BASE + \ + 0x3C) /* smxt capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per \ + field via <cap_sel_en> in <smxr_en_cnt> ) */ +#define CSR_SMRT_CSR_SMXT_CAP_FIELD_CFG_REG \ + (CSR_SMRT_CSR_BASE + \ + 0x40) /* SMXT capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per \ + field via <cap_sel_en> in <smxr_en_cnt> ) */ +#define CSR_SMRT_CSR_SMXT_CNT_CFG0_REG \ + (CSR_SMRT_CSR_BASE + 0x44) /* SMXT mappable event counter controal . The software use this control to configure \ + expected counter mapping . */ +#define CSR_SMRT_CSR_SMXT_CNT_CFG1_REG \ + (CSR_SMRT_CSR_BASE + 0x48) /* SMXT mappable event counter controal . The software use this control to configure \ + expected counter mapping . */ +#define CSR_SMRT_CSR_SMXT_CNT0_REG \ + (CSR_SMRT_CSR_BASE + 0x4C) /* SMXT physical counter 0.software can enable which events to be counted into it via \ + field <SMXT_en_cnt_0> in register <SMXT_CNT_CFG0> . */ +#define CSR_SMRT_CSR_SMXT_CNT1_REG \ + (CSR_SMRT_CSR_BASE + 0x50) /* SMXT physical counter 1.software can enable which events to be counted into it via \ + field <SMXT_en_cnt_1> in register <SMXT_CNT_CFG0> . */ +#define CSR_SMRT_CSR_SMXT_CNT2_REG \ + (CSR_SMRT_CSR_BASE + 0x54) /* SMXT physical counter 2.software can enable which events to be counted into it via \ + field <SMXT_en_cnt_2> in register <SMXT_CNT_CFG1> . */ +#define CSR_SMRT_CSR_SMXT_CNT3_REG \ + (CSR_SMRT_CSR_BASE + 0x58) /* SMXT physical counter 3.software can enable which events to be counted into it via \ + field <SMXT_en_cnt_3> in register <SMXT_CNT_CFG1> . */ +#define CSR_SMRT_CSR_SMXT_CRDT_CNT_REG (CSR_SMRT_CSR_BASE + 0x5C) /* smxt credit counter CTP registers */ +#define CSR_SMRT_CSR_SMXT_FIFO_DEPTH0_REG \ + (CSR_SMRT_CSR_BASE + 0x60) /* FIFO depth CTP registers for SMXT FIFOs for SMF infra1 and infra0 */ +#define CSR_SMRT_CSR_SMXT_FIFO_DEPTH1_REG \ + (CSR_SMRT_CSR_BASE + 0x68) /* FIFO depth CTP registers for SMXT FIFOs for SMF infra3 and Infra2 */ +#define CSR_SMRT_CSR_TL0_Q_DEP_REG (CSR_SMRT_CSR_BASE + 0x6C) /* queue depth for API from TILE0 in SMXR */ +#define CSR_SMRT_CSR_TL1_Q_DEP_REG (CSR_SMRT_CSR_BASE + 0x70) /* queue depth for API from TILE1 in SMXR */ +#define CSR_SMRT_CSR_RQST_Q_DEP_REG \ + (CSR_SMRT_CSR_BASE + 0x74) /* queue depth for API from RING request channel in SMXR */ +#define CSR_SMRT_CSR_RSP_Q_DEP_REG \ + (CSR_SMRT_CSR_BASE + 0x78) /* queue depth for API from RING request channel in SMXR */ +#define CSR_SMRT_CSR_RQST_CRDT_CNT_REG (CSR_SMRT_CSR_BASE + 0x7C) /* rqst channel credit counter in SMXR */ +#define CSR_SMRT_CSR_RESP_CRDT_CNT_REG (CSR_SMRT_CSR_BASE + 0x80) /* rsponse channel credit counter in SMXR */ +#define CSR_SMRT_CSR_SMXR_CNT0_REG (CSR_SMRT_CSR_BASE + 0x84) /* Cnt for tile0 direct channel */ +#define CSR_SMRT_CSR_SMXR_CNT1_REG (CSR_SMRT_CSR_BASE + 0x88) /* Cnt for tile1 direct channel */ +#define CSR_SMRT_CSR_SMXR_CNT2_REG (CSR_SMRT_CSR_BASE + 0x8C) /* Cnt for ring request channel */ +#define CSR_SMRT_CSR_SMXR_CNT3_REG (CSR_SMRT_CSR_BASE + 0x90) /* Cnt for ring rsponse channel */ +#define CSR_SMRT_CSR_SMXT_CTP_REG (CSR_SMRT_CSR_BASE + 0x94) /* SMXT CTP registers */ +#define CSR_SMRT_CSR_SMXR_CFG2_REG (CSR_SMRT_CSR_BASE + 0x98) /* SMXR cofigure registers */ +#define CSR_SMRT_CSR_SMXR_CFG3_REG (CSR_SMRT_CSR_BASE + 0x9C) /* SMXR cofigure registers */ +#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS0_REG (CSR_SMRT_CSR_BASE + 0xA0) /* RAM CTRL_BUS寄存器0 */ +#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS1_REG (CSR_SMRT_CSR_BASE + 0xA4) /* RAM CTRL_BUS寄存器1 */ +#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS2_REG (CSR_SMRT_CSR_BASE + 0xA8) /* RAM CTRL_BUS寄存器2 */ +#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS3_REG (CSR_SMRT_CSR_BASE + 0xAC) /* RAM CTRL_BUS寄存器3 */ +#define CSR_SMRT_CSR_CFG_MEM_CTRL_BUS4_REG (CSR_SMRT_CSR_BASE + 0xB0) /* RAM CTRL_BUS寄存器4 */ +#define CSR_SMRT_CSR_SMXT_CFG2_REG (CSR_SMRT_CSR_BASE + 0xB4) /* SMXT cofigure registers */ + +/* smir_csr Base address of Module's Register */ +#define CSR_SMIR_CSR_BASE (0x100) + +/* **************************************************************************** */ +/* smir_csr Registers' Definitions */ +/* **************************************************************************** */ + +#define CSR_SMIR_CSR_SMIR_VERSION_REG (CSR_SMIR_CSR_BASE + 0x0) /* reserved for ECO */ +#define CSR_SMIR_CSR_SMIR_CFG_REG \ + (CSR_SMIR_CSR_BASE + 0x4) /* This is the Smart Memory Infra Receive (SMIR) module configuration register. Use this \ + register for debug. */ +#define CSR_SMIR_CSR_SMIR_HASH_SEED0_REG \ + (CSR_SMIR_CSR_BASE + 0x8) /* Hash function seed conifg register. This register used to change the original seed of \ + hash function. */ +#define CSR_SMIR_CSR_SMIR_HASH_SEED1_REG \ + (CSR_SMIR_CSR_BASE + 0xC) /* Hash function seed conifg register. This register used to change the original seed of \ + hash function. */ +#define CSR_SMIR_CSR_SMIR_INT_VECTOR_REG (CSR_SMIR_CSR_BASE + 0x10) +#define CSR_SMIR_CSR_SMIR_INT_REG (CSR_SMIR_CSR_BASE + 0x14) /* SMIR interrupt data */ +#define CSR_SMIR_CSR_SMIR_INT_MASK_REG (CSR_SMIR_CSR_BASE + 0x18) /* SMIR interrupt mask configuration */ +#define CSR_SMIR_CSR_SMIR_ERR_SPEC_TH_REG (CSR_SMIR_CSR_BASE + 0x1C) /* Int[0] :specital thread drop for busy. */ +#define CSR_SMIR_CSR_SMIR_REQ_MSG_ERR_REG (CSR_SMIR_CSR_BASE + 0x20) /* SMIR request channel message error register. \ + */ +#define CSR_SMIR_CSR_SMIR_RESP_MSG_ERR_REG \ + (CSR_SMIR_CSR_BASE + 0x24) /* SMIR response channel message error register. */ +#define CSR_SMIR_CSR_SMIR_MEM_ECC_CRT_ERR_REG (CSR_SMIR_CSR_BASE + 0x28) /* smir memory ecc correctable error */ +#define CSR_SMIR_CSR_SMIR_MEM_ECC_UNCRT_ERR_REG (CSR_SMIR_CSR_BASE + 0x2C) /* smir memory ecc uncorrectable error */ +#define CSR_SMIR_CSR_SMIR_INDRECT_CTRL_REG (CSR_SMIR_CSR_BASE + 0x30) /* indirect access address registers */ +#define CSR_SMIR_CSR_SMIR_INDRECT_TIMEOUT_REG (CSR_SMIR_CSR_BASE + 0x34) /* memory access timeout configure */ +#define CSR_SMIR_CSR_SMIR_INDRECT_DATA_REG (CSR_SMIR_CSR_BASE + 0x38) /* indirect access data registers */ +#define CSR_SMIR_CSR_SMIR_CAP0_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x3C) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here.(need to enable per \ + field via <cap_sel_en> in <smir_en_cnt> ) */ +#define CSR_SMIR_CSR_SMIR_CAP1_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x40) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here. */ +#define CSR_SMIR_CSR_SMIR_CAP2_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x44) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here. */ +#define CSR_SMIR_CSR_SMIR_CAP3_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x48) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here. */ +#define CSR_SMIR_CSR_SMIR_CAP4_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x4C) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here. */ +#define CSR_SMIR_CSR_SMIR_CAP6_CFG_REG \ + (CSR_SMIR_CSR_BASE + \ + 0x50) /* SMIR capture fields configuration register .This is used for debug . The software can configure \ + capture conditions here .For example ,the software want to capture message and count matched message \ + .The software can enable <cap_mode> field and cofigure compare fields data here. */ +#define CSR_SMIR_CSR_SMIR_EN_CNT_REG \ + (CSR_SMIR_CSR_BASE + 0x54) /* SMIR mappable event counter controal . The software use this control to configure \ + expected counter mapping . */ +#define CSR_SMIR_CSR_SMIR_CNT0_REG \ + (CSR_SMIR_CSR_BASE + 0x58) /* SMIR physical counter 0.software can enable which events to be counted into it via \ + field <smir_en_cnt_0> in register <SMIR_EN_CNT> . */ +#define CSR_SMIR_CSR_SMIR_CNT1_REG \ + (CSR_SMIR_CSR_BASE + 0x5C) /* SMIR physical counter 1.software can enable which events to be counted into it via \ + field <smir_en_cnt_1> in register <SMIR_EN_CNT> . */ +#define CSR_SMIR_CSR_SMIR_CNT2_REG \ + (CSR_SMIR_CSR_BASE + 0x60) /* SMIR physical counter 2.software can enable which events to be counted into it via \ + field <smir_en_cnt_2> in register <SMIR_EN_CNT> . */ +#define CSR_SMIR_CSR_SMIR_CRDT_CNT_REG (CSR_SMIR_CSR_BASE + 0x64) /* SMIR credit counter CTP register */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT0_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0x68) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT0_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0x70) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT1_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0x78) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT1_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0x80) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT2_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0x88) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT2_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0x90) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT3_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0x98) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT3_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0xA0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT4_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0xA8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT4_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0xB0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT5_DATA0_REG \ + (CSR_SMIR_CSR_BASE + 0xB8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT5_DATA1_REG \ + (CSR_SMIR_CSR_BASE + 0xC0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT0_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xC8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT1_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xCC) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT2_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xD0) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT3_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xD4) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT4_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xD8) /* SMIR capture data according to <SMIR_CAP_CFG> configuration.1) capture mode:first \ + flit's lower 127bits of matched message;2) sample mode:first flit's lower 127bits of \ + latest message.This is used for debug . Software can configure capture condition \ + in SMIR_CAP_CFG. And Read capture data here. */ +#define CSR_SMIR_CSR_SMIR_CAP_FLIT5_DATA2_REG \ + (CSR_SMIR_CSR_BASE + 0xDC) /* SMIR capture data according to <