virt inclusion category:bugfix bugzilla:https://atomgit.com/openeuler/kernel/issues/8756 CVE:NA ----------------------------------------------------------- For compatibility reasons, add MIDR definitions MIDR_HISI_HIP08, MIDR_HISI_HIP10, MIDR_HISI_HIP10C and use MIDR instead of cpu type to determine whether NCSNP, IPIv and DVMBM are supported. Signed-off-by:Li Qiqi <liqiqi23@huawei.com> --- arch/arm64/include/asm/cache.h | 2 +- arch/arm64/include/asm/cputype.h | 8 ++++++-- arch/arm64/kernel/cpu_errata.c | 4 ++-- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/proton-pack.c | 4 ++-- arch/arm64/kvm/hisilicon/hisi_virt.c | 18 ++++++++++-------- drivers/perf/hisilicon/hisi_uncore_pmu.c | 2 +- tools/arch/arm64/include/asm/cputype.h | 4 ++-- 8 files changed, 25 insertions(+), 19 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 62fac127d889..43b9710b1233 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -120,7 +120,7 @@ static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void) u32 ctr = read_cpuid_cachetype(); #ifdef CONFIG_HISILICON_ERRATUM_1980005 static const struct midr_range idc_support_list[] = { - MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + MIDR_ALL_VERSIONS(MIDR_HISI_HIP08), MIDR_REV(MIDR_HISI_LINXICORE9100, 1, 0), { /* sentinel */ } }; diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 490c2ac36ac0..c7f851b4ba07 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -140,8 +140,10 @@ #define FUJITSU_CPU_PART_A64FX 0x001 -#define HISI_CPU_PART_TSV110 0xD01 +#define HISI_CPU_PART_HIP08 0xD01 #define HISI_CPU_PART_LINXICORE9100 0xD02 +#define HISI_CPU_PART_HIP10 0xD03 +#define HISI_CPU_PART_HIP10C 0xD45 #define HISI_CPU_PART_HIP12 0xD06 #define APPLE_CPU_PART_M1_ICESTORM 0x022 @@ -228,8 +230,10 @@ #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) -#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) +#define MIDR_HISI_HIP08 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP08) #define MIDR_HISI_LINXICORE9100 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_LINXICORE9100) +#define MIDR_HISI_HIP10 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP10) +#define MIDR_HISI_HIP10C MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP10C) #define MIDR_HISI_HIP12 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP12) #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 9be2d36133f5..52e721822013 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -129,7 +129,7 @@ hisilicon_1980005_match(const struct arm64_cpu_capabilities *entry, int scope) { static const struct midr_range idc_support_list[] = { - MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + MIDR_ALL_VERSIONS(MIDR_HISI_HIP08), MIDR_REV(MIDR_HISI_LINXICORE9100, 1, 0), { /* sentinel */ } }; @@ -988,7 +988,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { { .desc = "HiSilicon HIP08 Cache Readunique Prefetch Disable", .capability = ARM64_WORKAROUND_HISI_HIP08_RU_PREFETCH, - ERRATA_MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + ERRATA_MIDR_ALL_VERSIONS(MIDR_HISI_HIP08), .matches = should_disable_hisi_hip08_ru_prefetch, .cpu_enable = hisi_hip08_ru_prefetch_disable, }, diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 4492eaa4f4b8..cdd702772bd9 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1713,7 +1713,7 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), - MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + MIDR_ALL_VERSIONS(MIDR_HISI_HIP08), MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c index c8e13f196899..836eee1d959a 100644 --- a/arch/arm64/kernel/proton-pack.c +++ b/arch/arm64/kernel/proton-pack.c @@ -159,7 +159,7 @@ static enum mitigation_state spectre_v2_get_cpu_hw_mitigation_state(void) MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), - MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + MIDR_ALL_VERSIONS(MIDR_HISI_HIP08), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), @@ -896,7 +896,7 @@ static u8 spectre_bhb_loop_affected(void) MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), - MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + MIDR_ALL_VERSIONS(MIDR_HISI_HIP08), {}, }; static const struct midr_range spectre_bhb_k24_list[] = { diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c index d82c7691836e..8519dc5cc1ce 100644 --- a/arch/arm64/kvm/hisilicon/hisi_virt.c +++ b/arch/arm64/kvm/hisilicon/hisi_virt.c @@ -121,7 +121,7 @@ bool hisi_ncsnp_supported(void) unsigned int high; bool supported = false; - if (cpu_type != HI_1620) + if (read_cpuid_id() != MIDR_HISI_HIP08) return supported; base = ioremap(NCSNP_MMIO_BASE, 4); @@ -171,7 +171,7 @@ early_param("kvm-arm.ipiv_enabled", early_ipiv_enable); bool hisi_ipiv_supported(void) { - if (cpu_type != HI_IP12) + if (read_cpuid_implementor() != ARM_CPU_IMP_HISI) return false; /* Determine whether IPIV is supported by the hardware */ @@ -232,8 +232,7 @@ void ipiv_gicd_init(void) bool hisi_dvmbm_supported(void) { - if (cpu_type != HI_IP10 && cpu_type != HI_IP10C && - cpu_type != HI_IP12) + if (read_cpuid_implementor() != ARM_CPU_IMP_HISI) return false; if (!is_kernel_in_hyp_mode()) { @@ -542,6 +541,7 @@ void kvm_tlbi_dvmbm_vcpu_load(struct kvm_vcpu *vcpu) struct kvm_vcpu *tmp; cpumask_t mask; unsigned long i; + u32 midr; /* Don't bother on old hardware */ if (!kvm_dvmbm_support) @@ -581,10 +581,11 @@ void kvm_tlbi_dvmbm_vcpu_load(struct kvm_vcpu *vcpu) * Re-calculate LSUDVMBM_EL2 for this VM and kick all vcpus * out to reload the LSUDVMBM configuration. */ - if (cpu_type == HI_IP12) - kvm_update_vm_lsudvmbm_hip12(kvm); - else + midr = read_cpuid_id(); + if (midr == MIDR_HISI_HIP10 || midr == MIDR_HISI_HIP10C) kvm_update_vm_lsudvmbm(kvm); + else + kvm_update_vm_lsudvmbm_hip12(kvm); kvm_make_all_cpus_request(kvm, KVM_REQ_RELOAD_TLBI_DVMBM); out_unlock: @@ -608,8 +609,9 @@ void kvm_get_pg_cfg(void) u32 pg_cfgs[MAX_PG_CFG_SOCKETS * MAX_DIES_PER_SOCKET]; u64 mn_phy_base; u32 val; + u32 midr = read_cpuid_id(); - if (cpu_type == HI_IP12) + if (midr != MIDR_HISI_HIP10 && midr != MIDR_HISI_HIP10C) return; socket_num = kvm_get_socket_num(); diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c index 6d5a10d903b3..1f544f7278b7 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c @@ -473,7 +473,7 @@ static void hisi_read_sccl_and_ccl_id(int *scclp, int *cclp) bool mt = mpidr & MPIDR_MT_BITMASK; int sccl, ccl; - if (mt && read_cpuid_part_number() == HISI_CPU_PART_TSV110) { + if (mt && read_cpuid_part_number() == HISI_CPU_PART_HIP08) { sccl = aff2 >> 3; ccl = aff2 & 0x7; } else if (mt) { diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h index 62f01cd23180..0233aaada369 100644 --- a/tools/arch/arm64/include/asm/cputype.h +++ b/tools/arch/arm64/include/asm/cputype.h @@ -126,7 +126,7 @@ #define FUJITSU_CPU_PART_A64FX 0x001 -#define HISI_CPU_PART_TSV110 0xD01 +#define HISI_CPU_PART_HIP08 0xD01 #define HISI_CPU_PART_HIP12 0xD06 #define APPLE_CPU_PART_M1_ICESTORM 0x022 @@ -199,7 +199,7 @@ #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) -#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) +#define MIDR_HISI_HIP08 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP08) #define MIDR_HISI_HIP12 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP12) #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) -- 2.43.0