26 Mar
2021
26 Mar
'21
9:48 a.m.
On 2021/3/25 18:07, LeoLiu-oc wrote:
All Zhaoxin CPUs that support C3 share cache. And caches should not be flushed by software while entering C3 type state. And On all recent Zhaoxin platforms, ARB_DISABLE is a nop. So, set bm_control to zero to indicate that ARB_DISABLE is not required while entering C3 type state.
LeoLiu-oc (2): x86/power: Optimize C3 entry on Centaur CPUs x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3
arch/x86/kernel/acpi/cstate.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>