From: wanghaibin <wanghaibin.wang@huawei.com> The ARM rVIC is the simplest PV interrupt controller on this side of the universe. I mean it! Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-rvic.c | 554 +++++++++++++++++++++++++++++++ include/linux/cpuhotplug.h | 1 + include/linux/irqchip/irq-rvic.h | 77 +++++ 5 files changed, 639 insertions(+) create mode 100644 drivers/irqchip/irq-rvic.c create mode 100644 include/linux/irqchip/irq-rvic.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index a15fbf9fa85f..95897923b0c7 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -123,6 +123,12 @@ config ARM_NVIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_CHIP +config ARM_RVIC + bool + default ARM64 + select IRQ_DOMAIN_HIERARCHY + select GENERIC_IRQ_EFFECTIVE_AFF_MASK + config ARM_VIC bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index d8778ff3f260..906923c83903 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_ARM_GIC_PHYTIUM_2500) += irq-gic-phytium-2500.o irq-gic-phytium-250 obj-$(CONFIG_PARTITION_PERCPU) += irq-partition-percpu.o obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o obj-$(CONFIG_ARM_NVIC) += irq-nvic.o +obj-$(CONFIG_ARM_RVIC) += irq-rvic.o obj-$(CONFIG_ARM_VIC) += irq-vic.o obj-$(CONFIG_ARMADA_370_XP_IRQ) += irq-armada-370-xp.o obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o diff --git a/drivers/irqchip/irq-rvic.c b/drivers/irqchip/irq-rvic.c new file mode 100644 index 000000000000..1c65ccabbf5a --- /dev/null +++ b/drivers/irqchip/irq-rvic.c @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * A Reduced Virtual Interrupt Controler driver + * + * Initial draft from Alex Shirshikov <alexander.shirshikov@arm.com> + * + * Copyright 2020 Google LLC. + * Author: Marc Zyngier <maz@kernel.org> + */ + + +#define pr_fmt(fmt) "rVIC: " fmt + +#include <linux/arm-smccc.h> +#include <linux/cpuhotplug.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/irqchip.h> +#include <linux/irqdomain.h> + +#include <linux/irqchip/irq-rvic.h> + +#include <asm/exception.h> + +#define RVIC_WARN_INTID_TARGET(r, s, intid, mpid) \ + WARN((r), "Error " s " INTID%ld target %llx (%ld, %ld)\n", \ + (intid), (mpid), \ + RVIC_STATUS_REASON((r)), RVIC_STATUS_INDEX((r))); + +#define RVIC_WARN_INTID(r, s, intid) \ + WARN((r), "Error " s " INTID%ld (%ld, %ld)\n", \ + (intid), \ + RVIC_STATUS_REASON((r)), RVIC_STATUS_INDEX((r))); + +static DEFINE_PER_CPU(unsigned long *, trusted_masked); + +struct rvic_data { + struct fwnode_handle *fwnode; + struct irq_domain *domain; + unsigned int nr_trusted; + unsigned int nr_untrusted; +}; + +static struct rvic_data rvic; + +static inline int rvic_version(unsigned long *version) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVIC_VERSION, &res); + if (res.a0 == RVIC_STATUS_SUCCESS) + *version = res.a1; + return res.a0; +} + +static inline unsigned long rvic_info(unsigned long key, + unsigned long *value) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVIC_INFO, key, &res); + if (res.a0 == RVIC_STATUS_SUCCESS) + *value = res.a1; + return res.a0; +} + +static inline unsigned long rvic_enable(void) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVIC_ENABLE, &res); + return res.a0; +} + +static inline unsigned long rvic_disable(void) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVIC_DISABLE, &res); + return res.a0; +} + +static inline unsigned long rvic_set_masked(unsigned long target, + unsigned long intid) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVIC_SET_MASKED, target, intid, &res); + return res.a0; +} + +static inline unsigned long rvic_clear_masked(unsigned long target, + unsigned long intid) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVIC_CLEAR_MASKED, target, intid, &res); + return res.a0; +} + +static inline unsigned long rvic_is_pending(unsigned long target, + unsigned long intid, + bool *is_pending) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVIC_IS_PENDING, target, intid, &res); + if (res.a0 == RVIC_STATUS_SUCCESS) + *is_pending = res.a1; + return res.a0; +} + +static inline unsigned long rvic_signal(unsigned long target, + unsigned long intid) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVIC_SIGNAL, target, intid, &res); + return res.a0; +} + +static inline unsigned long rvic_clear_pending(unsigned long target, + unsigned long intid) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVIC_CLEAR_PENDING, target, intid, &res); + return res.a0; +} + +static inline unsigned long rvic_acknowledge(unsigned long *intid) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVIC_ACKNOWLEDGE, &res); + if (res.a0 == RVIC_STATUS_SUCCESS) + *intid = res.a1; + return res.a0; +} + +static inline unsigned long rvic_resample(unsigned long intid) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVIC_RESAMPLE, intid, &res); + return res.a0; +} + +static u64 rvic_irq_to_mpidr(struct irq_data *data, int *cpup) +{ + int cpu; + + if (data->hwirq < rvic.nr_trusted) { + *cpup = smp_processor_id(); + return read_cpuid_mpidr() & MPIDR_HWID_BITMASK; + } + + cpu = cpumask_first(data->common->effective_affinity); + *cpup = cpu; + return cpu_logical_map(cpu) & MPIDR_HWID_BITMASK; +} + +static void rvic_irq_mask(struct irq_data *data) +{ + unsigned long ret; + u64 mpidr; + int cpu; + + mpidr = rvic_irq_to_mpidr(data, &cpu); + pr_debug("%llu irq %d hwirq %ld masked\n", + mpidr, data->irq, data->hwirq); + ret = rvic_set_masked(mpidr, data->hwirq); + RVIC_WARN_INTID_TARGET(ret, "masking", data->hwirq, mpidr); + + if (data->hwirq < rvic.nr_trusted) + set_bit(data->hwirq, per_cpu(trusted_masked, cpu)); +} + +static void rvic_irq_unmask(struct irq_data *data) +{ + unsigned long ret; + u64 mpidr; + int cpu; + + mpidr = rvic_irq_to_mpidr(data, &cpu); + pr_debug("%llu irq %d hwirq %ld unmasked\n", + mpidr, data->irq, data->hwirq); + ret = rvic_clear_masked(mpidr, data->hwirq); + RVIC_WARN_INTID_TARGET(ret, "unmasking", data->hwirq, mpidr); + + if (data->hwirq < rvic.nr_trusted) + clear_bit(data->hwirq, per_cpu(trusted_masked, cpu)); +} + +static void rvic_irq_eoi(struct irq_data *data) +{ + bool masked; + + /* Resampling is only available on trusted interrupts for now */ + if (data->hwirq < rvic.nr_trusted && + (irqd_get_trigger_type(data) & IRQ_TYPE_LEVEL_MASK)) { + unsigned long ret; + + ret = rvic_resample(data->hwirq); + RVIC_WARN_INTID(ret, "resampling", data->hwirq); + } + + /* irqd_irq_masked doesn't work on percpu-devid interrupts. */ + if (data->hwirq < rvic.nr_trusted) + masked = test_bit(data->hwirq, *this_cpu_ptr(&trusted_masked)); + else + masked = irqd_irq_masked(data); + + if (!masked) + rvic_irq_unmask(data); +} + +static void rvic_ipi_send_mask(struct irq_data *data, + const struct cpumask *mask) +{ + int cpu; + + for_each_cpu(cpu, mask) { + u64 mpidr = cpu_logical_map(cpu) & MPIDR_HWID_BITMASK; + unsigned long ret; + + ret = rvic_signal(mpidr, data->hwirq); + RVIC_WARN_INTID_TARGET(ret, "signaling", data->hwirq, mpidr); + } +} + +static int rvic_irq_get_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, bool *val) +{ + unsigned long ret; + u64 mpidr; + int cpu; + + mpidr = rvic_irq_to_mpidr(data, &cpu); + + switch (which) { + case IRQCHIP_STATE_PENDING: + ret = rvic_is_pending(mpidr, data->hwirq, val); + RVIC_WARN_INTID_TARGET(ret, "getting pending state", + data->hwirq, mpidr); + return ret ? -EINVAL : 0; + + default: + return -EINVAL; + }; +} + +static int rvic_irq_set_irqchip_state(struct irq_data *data, + enum irqchip_irq_state which, bool val) +{ + unsigned long ret; + u64 mpidr; + int cpu; + + mpidr = rvic_irq_to_mpidr(data, &cpu); + + switch (which) { + case IRQCHIP_STATE_PENDING: + if (val) + ret = rvic_signal(mpidr, data->hwirq); + else + ret = rvic_clear_pending(mpidr, data->hwirq); + RVIC_WARN_INTID_TARGET(ret, "setting pending state", + data->hwirq, mpidr); + return ret ? -EINVAL : 0; + + case IRQCHIP_STATE_MASKED: + if (val) + ret = rvic_set_masked(mpidr, data->hwirq); + else + ret = rvic_clear_masked(mpidr, data->hwirq); + RVIC_WARN_INTID_TARGET(ret, "setting masked state", + data->hwirq, mpidr); + return ret ? -EINVAL : 0; + + default: + return -EINVAL; + } + +} + +static int rvic_irq_retrigger(struct irq_data *data) +{ + return !!rvic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true); +} + +static int rvic_set_type(struct irq_data *data, unsigned int type) +{ + /* + * Nothing to do here, we're always edge under the hood. Just + * weed out untrusted interrupts, as they cannot be level yet. + */ + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + if (data->hwirq >= rvic.nr_trusted) + return -EINVAL; + + fallthrough; + case IRQ_TYPE_EDGE_RISING: + return 0; + default: + return -EINVAL; + } +} + +static struct irq_chip rvic_chip = { + .name = "rvic", + .irq_mask = rvic_irq_mask, + .irq_unmask = rvic_irq_unmask, + .irq_eoi = rvic_irq_eoi, + .ipi_send_mask = rvic_ipi_send_mask, + .irq_get_irqchip_state = rvic_irq_get_irqchip_state, + .irq_set_irqchip_state = rvic_irq_set_irqchip_state, + .irq_retrigger = rvic_irq_retrigger, + .irq_set_type = rvic_set_type, +}; + +static asmlinkage void __exception_irq_entry rvic_handle_irq(struct pt_regs *regs) +{ + unsigned long ret, intid; + int err; + + ret = rvic_acknowledge(&intid); + if (unlikely(ret == RVIC_STATUS_NO_INTERRUPTS)) { + pr_debug("CPU%d: Spurious interrupt\n", smp_processor_id()); + return; + } + + if ((unlikely(ret))) { + WARN(1, "rVIC: Error acknowledging interrupt (%ld, %ld)\n", + RVIC_STATUS_REASON(ret), + RVIC_STATUS_INDEX(ret)); + return; + } + + if (unlikely(intid >= (rvic.nr_trusted + rvic.nr_untrusted))) { + WARN(1, "Unexpected intid out of range (%lu)\n", intid); + return; + } + + pr_debug("CPU%d: IRQ%ld\n", smp_processor_id(), intid); + err = generic_handle_domain_irq(rvic.domain, intid); + WARN_ONCE(err, "Unexpected interrupt received %d\n", err); +} + +static int rvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + struct irq_fwspec *fwspec = arg; + unsigned int type = IRQ_TYPE_NONE; + irq_hw_number_t hwirq; + int i, ret; + + ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) { + unsigned int intid = hwirq + i; + unsigned int irq = virq + i; + + if (intid < 16) { + irq_set_percpu_devid(irq); + irq_domain_set_info(domain, irq, intid, &rvic_chip, + domain->host_data, + handle_percpu_devid_irq, + NULL, NULL); + } else if (intid < rvic.nr_trusted) { + irq_set_percpu_devid(irq); + irq_domain_set_info(domain, irq, intid, &rvic_chip, + domain->host_data, + handle_percpu_devid_irq, + NULL, NULL); + } else { + return -EINVAL; + } + } + + return 0; +} + +static void rvic_irq_domain_free(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs) +{ + int i; + + for (i = 0; i < nr_irqs; i++) { + struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); + irq_set_handler(virq + i, NULL); + irq_domain_reset_irq_data(d); + } +} + +static const struct irq_domain_ops rvic_irq_domain_ops = { + .translate = irq_domain_translate_twocell, + .alloc = rvic_irq_domain_alloc, + .free = rvic_irq_domain_free, +}; + +static int rvic_cpu_starting(unsigned int cpu) +{ + u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; + unsigned long ret; + int i; + + rvic_disable(); + + for (i = 0; i < (rvic.nr_trusted + rvic.nr_untrusted); i++) { + rvic_set_masked(mpidr, i); + rvic_clear_pending(mpidr, i); + } + + ret = rvic_enable(); + if (ret != RVIC_STATUS_SUCCESS) { + pr_err("rVIC: error enabling instance (%ld, %ld)\n", + RVIC_STATUS_REASON(ret), + RVIC_STATUS_INDEX(ret)); + return -ENXIO; + } + + return 0; +} + +static int rvic_cpu_dying(unsigned int cpu) +{ + unsigned long ret; + + ret = rvic_disable(); + if (ret != RVIC_STATUS_SUCCESS) { + pr_err("rVIC: error disabling instance (%ld, %ld)\n", + RVIC_STATUS_REASON(ret), + RVIC_STATUS_INDEX(ret)); + return -ENXIO; + } + + return 0; +} + +static void __init rvic_smp_init(struct fwnode_handle *fwnode) +{ + struct irq_fwspec ipi_fwspec = { + .fwnode = fwnode, + .param_count = 2, + .param[0] = 0, + .param[1] = IRQ_TYPE_EDGE_RISING, + }; + int base_ipi; + + cpuhp_setup_state(CPUHP_AP_IRQ_RVIC_STARTING, "irqchip/rvic:starting", + rvic_cpu_starting, rvic_cpu_dying); + + base_ipi = __irq_domain_alloc_irqs(rvic.domain, -1, 16, + NUMA_NO_NODE, &ipi_fwspec, + false, NULL); + if (WARN_ON(base_ipi < 0)) + return; + + set_smp_ipi_range(base_ipi, 16); +} + +static int __init rvic_init(struct device_node *node, + struct device_node *parent) +{ + unsigned long ret, version, val; + int cpu; + + if (arm_smccc_get_version() < ARM_SMCCC_VERSION_1_1) { + pr_err("SMCCC 1.1 required, abording\n"); + return -EINVAL; + } + + rvic.fwnode = of_node_to_fwnode(node); + + ret = rvic_version(&version); + if (ret != RVIC_STATUS_SUCCESS) { + pr_err("error retrieving version (%ld, %ld)\n", + RVIC_STATUS_REASON(ret), + RVIC_STATUS_INDEX(ret)); + return -ENXIO; + } + + if (version < RVIC_VERSION(0, 3)) { + pr_err("version (%ld, %ld) too old, expected min. (%d, %d)\n", + RVIC_VERSION_MAJOR(version), + RVIC_VERSION_MINOR(version), + 0, 3); + return -ENXIO; + } + + ret = rvic_info(RVIC_INFO_KEY_NR_TRUSTED_INTERRUPTS, &val); + if (ret != RVIC_STATUS_SUCCESS) { + pr_err("error retrieving nr of trusted interrupts (%ld, %ld)\n", + RVIC_STATUS_REASON(ret), + RVIC_STATUS_INDEX(ret)); + return -ENXIO; + } + + rvic.nr_trusted = val; + + ret = rvic_info(RVIC_INFO_KEY_NR_UNTRUSTED_INTERRUPTS, &val); + if (ret != RVIC_STATUS_SUCCESS) { + pr_err("error retrieving nr of untrusted interrupts (%ld, %ld)\n", + RVIC_STATUS_REASON(ret), + RVIC_STATUS_INDEX(ret)); + return -ENXIO; + } + + rvic.nr_untrusted = val; + + pr_info("probed %u trusted interrupts, %u untrusted interrupts\n", + rvic.nr_trusted, rvic.nr_untrusted); + + rvic.domain = irq_domain_create_linear(rvic.fwnode, + rvic.nr_trusted + rvic.nr_untrusted, + &rvic_irq_domain_ops, &rvic); + if (!rvic.domain) { + pr_warn("Failed to allocate irq domain\n"); + return -ENOMEM; + } + + for_each_possible_cpu(cpu) { + unsigned long *map = bitmap_alloc(rvic.nr_trusted, GFP_KERNEL); + + if (!map) { + pr_warn("Failed to allocate trusted bitmap (CPU %d)\n", + cpu); + goto free_percpu; + } + + /* Default to masked */ + bitmap_fill(map, rvic.nr_trusted); + per_cpu(trusted_masked, cpu) = map; + } + + rvic_smp_init(rvic.fwnode); + set_handle_irq(rvic_handle_irq); + + return 0; + +free_percpu: + for_each_possible_cpu(cpu) + kfree(per_cpu(trusted_masked, cpu)); + + irq_domain_remove(rvic.domain); + + return -ENOMEM; +} + +IRQCHIP_DECLARE(rvic, "arm,rvic", rvic_init); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 89fd528e8ef4..069e60fad2f1 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -150,6 +150,7 @@ enum cpuhp_state { CPUHP_AP_IRQ_APPLE_AIC_STARTING, CPUHP_AP_IRQ_ARMADA_XP_STARTING, CPUHP_AP_IRQ_BCM2836_STARTING, + CPUHP_AP_IRQ_RVIC_STARTING, CPUHP_AP_IRQ_MIPS_GIC_STARTING, CPUHP_AP_IRQ_RISCV_STARTING, CPUHP_AP_IRQ_LOONGARCH_STARTING, diff --git a/include/linux/irqchip/irq-rvic.h b/include/linux/irqchip/irq-rvic.h new file mode 100644 index 000000000000..0176ca7d3c30 --- /dev/null +++ b/include/linux/irqchip/irq-rvic.h @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Definitions for rVIC/rVID PV interrupt controller architecture. + * + * Copyright 2020 Google LLC. + * Author: Marc Zyngier <maz@kernel.org> + * + * WARNING: All these constants are subject to change until the spec is final. + */ + +#ifndef __IRQCHIP_IRQ_RVIC_H__ +#define __IRQCHIP_IRQ_RVIC_H__ + +#include <linux/bitfield.h> + +/* Versioning */ +#define RVIx_VERSION_MAJOR_MASK GENMASK(31, 16) +#define RVIx_VERSION_MINOR_MASK GENMASK(15, 0) + +#define RVIx_VERSION(M, m) \ + (FIELD_PREP(RVIx_VERSION_MAJOR_MASK, (M)) | \ + FIELD_PREP(RVIx_VERSION_MINOR_MASK, (m))) + +#define RVIx_VERSION_MAJOR(v) FIELD_GET(RVIx_VERSION_MAJOR_MASK, (v)) +#define RVIx_VERSION_MINOR(v) FIELD_GET(RVIx_VERSION_MINOR_MASK, (v)) + +/* Error reporting */ +#define RVIx_STATUS_REASON_MASK GENMASK(7, 0) +#define RVIx_STATUS_INDEX_MASK GENMASK(15, 8) + +#define RVIx_STATUS_PACK(r,i) \ + (FIELD_PREP(RVIx_STATUS_REASON_MASK, (r)) | \ + FIELD_PREP(RVIx_STATUS_INDEX_MASK, (i))) + +#define RVIx_STATUS_REASON(c) FIELD_GET(RVIx_STATUS_REASON_MASK, (c)) +#define RVIx_STATUS_INDEX(c) FIELD_GET(RVIx_STATUS_INDEX_MASK, (c)) + +#define RVIx_STATUS_SUCCESS 0 +#define RVIx_STATUS_ERROR_PARAMETER 1 +#define RVIx_STATUS_INVALID_CPU 2 +#define RVIx_STATUS_DISABLED 3 +#define RVIx_STATUS_NO_INTERRUPTS 4 + +/* rVIC functions */ +#define SMC64_RVIC_BASE 0xc5000200 +#define SMC64_RVIC_FN(n) (SMC64_RVIC_BASE + (n)) + +#define SMC64_RVIC_VERSION SMC64_RVIC_FN(0) +#define SMC64_RVIC_INFO SMC64_RVIC_FN(1) +#define SMC64_RVIC_ENABLE SMC64_RVIC_FN(2) +#define SMC64_RVIC_DISABLE SMC64_RVIC_FN(3) +#define SMC64_RVIC_SET_MASKED SMC64_RVIC_FN(4) +#define SMC64_RVIC_CLEAR_MASKED SMC64_RVIC_FN(5) +#define SMC64_RVIC_IS_PENDING SMC64_RVIC_FN(6) +#define SMC64_RVIC_SIGNAL SMC64_RVIC_FN(7) +#define SMC64_RVIC_CLEAR_PENDING SMC64_RVIC_FN(8) +#define SMC64_RVIC_ACKNOWLEDGE SMC64_RVIC_FN(9) +#define SMC64_RVIC_RESAMPLE SMC64_RVIC_FN(10) + +#define RVIC_INFO_KEY_NR_TRUSTED_INTERRUPTS 0 +#define RVIC_INFO_KEY_NR_UNTRUSTED_INTERRUPTS 1 + +#define RVIC_VERSION(M, m) RVIx_VERSION((M), (m)) + +#define RVIC_VERSION_MAJOR(v) RVIx_VERSION_MAJOR((v)) +#define RVIC_VERSION_MINOR(v) RVIx_VERSION_MINOR((v)) + +#define RVIC_STATUS_REASON(c) RVIx_STATUS_REASON((c)) +#define RVIC_STATUS_INDEX(c) RVIx_STATUS_INDEX((c)) + +#define RVIC_STATUS_SUCCESS RVIx_STATUS_SUCCESS +#define RVIC_STATUS_ERROR_PARAMETER RVIx_STATUS_ERROR_PARAMETER +#define RVIC_STATUS_INVALID_CPU RVIx_STATUS_INVALID_CPU +#define RVIC_STATUS_DISABLED RVIx_STATUS_DISABLED +#define RVIC_STATUS_NO_INTERRUPTS RVIx_STATUS_NO_INTERRUPTS + +#endif /* __IRQCHIP_IRQ_RVIC_H__ */ -- 2.33.0

From: Marc Zyngier <maz@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-rvid.c | 259 +++++++++++++++++++++++++++++++ include/linux/irqchip/irq-rvic.h | 19 +++ 4 files changed, 285 insertions(+) create mode 100644 drivers/irqchip/irq-rvid.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 95897923b0c7..ace9f1c55fe4 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -129,6 +129,12 @@ config ARM_RVIC select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_EFFECTIVE_AFF_MASK +config ARM_RVID + bool + default ARM64 + select IRQ_DOMAIN_HIERARCHY + select GENERIC_IRQ_EFFECTIVE_AFF_MASK + config ARM_VIC bool select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 906923c83903..3669628d298d 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_PARTITION_PERCPU) += irq-partition-percpu.o obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o obj-$(CONFIG_ARM_NVIC) += irq-nvic.o obj-$(CONFIG_ARM_RVIC) += irq-rvic.o +obj-$(CONFIG_ARM_RVID) += irq-rvid.o obj-$(CONFIG_ARM_VIC) += irq-vic.o obj-$(CONFIG_ARMADA_370_XP_IRQ) += irq-armada-370-xp.o obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o diff --git a/drivers/irqchip/irq-rvid.c b/drivers/irqchip/irq-rvid.c new file mode 100644 index 000000000000..953f654e58d4 --- /dev/null +++ b/drivers/irqchip/irq-rvid.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Google LLC. + * Author: Marc Zyngier <maz@kernel.org> + */ + +#define pr_fmt(fmt) "rVID: " fmt + +#include <linux/arm-smccc.h> +#include <linux/cpuhotplug.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/irqchip.h> +#include <linux/irqdomain.h> + +#include <linux/irqchip/irq-rvic.h> + +struct rvid_data { + struct fwnode_handle *fwnode; + struct irq_domain *domain; +}; + +static struct rvid_data rvid; + +static inline int rvid_version(unsigned long *version) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVID_VERSION, &res); + if (res.a0 == RVID_STATUS_SUCCESS) + *version = res.a1; + return res.a0; +} + +static inline int rvid_map(unsigned long input, + unsigned long target, unsigned long intid) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVID_MAP, input, target, intid, &res); + return res.a0; +} + +static inline int rvid_unmap(unsigned long input) +{ + struct arm_smccc_res res; + + arm_smccc_1_1_invoke(SMC64_RVID_UNMAP, input, &res); + return res.a0; +} + +static int rvid_irq_set_affinity(struct irq_data *data, + const struct cpumask *mask_val, + bool force) +{ + unsigned int old_cpu, cpu; + bool masked, pending; + int err = 0, ret; + u64 mpidr; + + if (force) + cpu = cpumask_first(mask_val); + else + cpu = cpumask_any_and(mask_val, cpu_online_mask); + + if (cpu >= nr_cpu_ids) + return -EINVAL; + + mpidr = cpu_logical_map(cpu) & MPIDR_HWID_BITMASK; + old_cpu = cpumask_first(data->common->effective_affinity); + if (cpu == old_cpu) + return 0; + + /* Mask on source */ + masked = irqd_irq_masked(data); + if (!masked) + irq_chip_mask_parent(data); + + /* Switch to target */ + irq_data_update_effective_affinity(data, cpumask_of(cpu)); + + /* Mask on target */ + irq_chip_mask_parent(data); + + /* Map the input signal to the new target */ + ret = rvid_map(data->hwirq, mpidr, data->parent_data->hwirq); + if (ret != RVID_STATUS_SUCCESS) { + err = -ENXIO; + goto unmask; + } + + /* Back to the source */ + irq_data_update_effective_affinity(data, cpumask_of(old_cpu)); + + /* Sample pending state and clear it if necessary */ + err = irq_chip_get_parent_state(data, IRQCHIP_STATE_PENDING, &pending); + if (err) + goto unmask; + if (pending) + irq_chip_set_parent_state(data, IRQCHIP_STATE_PENDING, false); + + /* + * To the target again (for good this time), propagating the + * pending bit if required. + */ + irq_data_update_effective_affinity(data, cpumask_of(cpu)); + if (pending) + irq_chip_set_parent_state(data, IRQCHIP_STATE_PENDING, true); +unmask: + /* Propagate the masking state */ + if (!masked) + irq_chip_unmask_parent(data); + + return err; +} + +static struct irq_chip rvid_chip = { + .name = "rvid", + .irq_mask = irq_chip_mask_parent, + .irq_unmask = irq_chip_unmask_parent, + .irq_eoi = irq_chip_eoi_parent, + .irq_get_irqchip_state = irq_chip_get_parent_state, + .irq_set_irqchip_state = irq_chip_set_parent_state, + .irq_retrigger = irq_chip_retrigger_hierarchy, + .irq_set_type = irq_chip_set_type_parent, + .irq_set_affinity = rvid_irq_set_affinity, +}; + +static int rvid_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + struct irq_fwspec *fwspec = arg; + unsigned int type = IRQ_TYPE_NONE; + irq_hw_number_t hwirq; + int i, ret; + + ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) { + unsigned int intid = hwirq + i; + unsigned int irq = virq + i; + + /* Get the rVIC to allocate any untrusted intid */ + ret = irq_domain_alloc_irqs_parent(domain, irq, 1, NULL); + if (WARN_ON(ret)) + return ret; + + irq_domain_set_hwirq_and_chip(domain, irq, intid, + &rvid_chip, &rvid); + irqd_set_affinity_on_activate(irq_get_irq_data(irq)); + } + + return 0; +} + +static void rvid_irq_domain_free(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs) +{ + int i; + + irq_domain_free_irqs_parent(domain, virq, nr_irqs); + + for (i = 0; i < nr_irqs; i++) { + struct irq_data *d; + + d = irq_domain_get_irq_data(domain, virq + i); + irq_set_handler(virq + i, NULL); + irq_domain_reset_irq_data(d); + } +} + +static int rvid_irq_domain_activate(struct irq_domain *domain, + struct irq_data *data, bool reserve) +{ + unsigned long ret; + int cpu, err = 0; + u64 mpidr; + + cpu = get_cpu(); + mpidr = cpu_logical_map(cpu) & MPIDR_HWID_BITMASK; + + /* Map the input signal */ + ret = rvid_map(data->hwirq, mpidr, data->parent_data->hwirq); + if (ret != RVID_STATUS_SUCCESS) { + err = -ENXIO; + goto out; + } + + irq_data_update_effective_affinity(data, cpumask_of(cpu)); + +out: + put_cpu(); + return err; +} + +static void rvid_irq_domain_deactivate(struct irq_domain *domain, + struct irq_data *data) +{ + rvid_unmap(data->hwirq); +} + +static const struct irq_domain_ops rvid_irq_domain_ops = { + .translate = irq_domain_translate_onecell, + .alloc = rvid_irq_domain_alloc, + .free = rvid_irq_domain_free, + .activate = rvid_irq_domain_activate, + .deactivate = rvid_irq_domain_deactivate, +}; + +static int __init rvid_init(struct device_node *node, + struct device_node *parent) +{ + struct irq_domain *parent_domain; + unsigned long ret, version; + + if (arm_smccc_get_version() < ARM_SMCCC_VERSION_1_1) { + pr_err("SMCCC 1.1 required, aborting\n"); + return -EINVAL; + } + + if (!parent) + return -ENXIO; + + parent_domain = irq_find_host(parent); + if (!parent_domain) + return -ENXIO; + + rvid.fwnode = of_node_to_fwnode(node); + + ret = rvid_version(&version); + if (ret != RVID_STATUS_SUCCESS) { + pr_err("error retrieving version (%ld, %ld)\n", + RVID_STATUS_REASON(ret), RVID_STATUS_INDEX(ret)); + return -ENXIO; + } + + if (version < RVID_VERSION(0, 3)) { + pr_err("version (%ld, %ld) too old, expected min. (%d, %d)\n", + RVID_VERSION_MAJOR(version), RVID_VERSION_MINOR(version), + 0, 3); + return -ENXIO; + } + + pr_info("distributing interrupts to %pOF\n", parent); + + rvid.domain = irq_domain_create_hierarchy(parent_domain, 0, 0, + rvid.fwnode, + &rvid_irq_domain_ops, &rvid); + if (!rvid.domain) { + pr_warn("Failed to allocate irq domain\n"); + return -ENOMEM; + } + + return 0; +} + +IRQCHIP_DECLARE(rvic, "arm,rvid", rvid_init); diff --git a/include/linux/irqchip/irq-rvic.h b/include/linux/irqchip/irq-rvic.h index 0176ca7d3c30..4545c1e89741 100644 --- a/include/linux/irqchip/irq-rvic.h +++ b/include/linux/irqchip/irq-rvic.h @@ -74,4 +74,23 @@ #define RVIC_STATUS_DISABLED RVIx_STATUS_DISABLED #define RVIC_STATUS_NO_INTERRUPTS RVIx_STATUS_NO_INTERRUPTS +/* rVID functions */ +#define SMC64_RVID_BASE 0xc5000100 +#define SMC64_RVID_FN(n) (SMC64_RVID_BASE + (n)) + +#define SMC64_RVID_VERSION SMC64_RVID_FN(0) +#define SMC64_RVID_MAP SMC64_RVID_FN(1) +#define SMC64_RVID_UNMAP SMC64_RVID_FN(2) + +#define RVID_VERSION(M, m) RVIx_VERSION((M), (m)) + +#define RVID_VERSION_MAJOR(v) RVIx_VERSION_MAJOR((v)) +#define RVID_VERSION_MINOR(v) RVIx_VERSION_MINOR((v)) + +#define RVID_STATUS_REASON(c) RVIx_STATUS_REASON((c)) +#define RVID_STATUS_INDEX(c) RVIx_STATUS_INDEX((c)) + +#define RVID_STATUS_SUCCESS RVIx_STATUS_SUCCESS +#define RVID_STATUS_ERROR_PARAMETER RVIx_STATUS_ERROR_PARAMETER + #endif /* __IRQCHIP_IRQ_RVIC_H__ */ -- 2.33.0

From: wanghaibin <wanghaibin.wang@huawei.com> In order to allow more than just GIC implementations in the future, let's move the GIC model outside of the distributor. This also allows us to back irqchip_in_kernel() with its own irqchip type (IRQCHIP_USER), removing another field from the distributor. New helpers are provided as a convenience. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/include/asm/kvm_irq.h | 20 ++++++++++++++++++++ arch/arm64/kvm/vgic/vgic-debug.c | 5 +++-- arch/arm64/kvm/vgic/vgic-init.c | 27 +++++++++++++-------------- arch/arm64/kvm/vgic/vgic-kvm-device.c | 16 ++++++++++++---- arch/arm64/kvm/vgic/vgic-mmio-v3.c | 2 +- arch/arm64/kvm/vgic/vgic-mmio.c | 14 ++++++-------- arch/arm64/kvm/vgic/vgic-v3.c | 20 ++++++++------------ arch/arm64/kvm/vgic/vgic.h | 2 +- include/kvm/arm_vgic.h | 5 ----- 10 files changed, 67 insertions(+), 47 deletions(-) create mode 100644 arch/arm64/include/asm/kvm_irq.h diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 69a08a4f3d85..badc60577f91 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -31,6 +31,8 @@ #include <asm/kvm_rme.h> #include <asm/kvm_tmm.h> +#include <asm/kvm_irq.h> + #define __KVM_HAVE_ARCH_INTC_INITIALIZED #define KVM_HALT_POLL_NS_DEFAULT 500000 @@ -216,6 +218,7 @@ struct kvm_arch { u8 pfr1_nmi; /* Interrupt controller */ + enum kvm_irqchip_type irqchip_type; struct vgic_dist vgic; /* Timers */ diff --git a/arch/arm64/include/asm/kvm_irq.h b/arch/arm64/include/asm/kvm_irq.h new file mode 100644 index 000000000000..46bffb6026f8 --- /dev/null +++ b/arch/arm64/include/asm/kvm_irq.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 - Google LLC + * Author: Marc Zyngier <maz@kernel.org> + */ + +#ifndef __ARM64_KVM_IRQ_H__ +#define __ARM64_KVM_IRQ_H__ + +enum kvm_irqchip_type { + IRQCHIP_USER, /* Implemented in userspace */ + IRQCHIP_GICv2, /* v2 on v2, or v2 on v3 */ + IRQCHIP_GICv3, /* v3 on v3 */ +}; + +#define irqchip_in_kernel(k) ((k)->arch.irqchip_type != IRQCHIP_USER) +#define irqchip_is_gic_v2(k) ((k)->arch.irqchip_type == IRQCHIP_GICv2) +#define irqchip_is_gic_v3(k) ((k)->arch.irqchip_type == IRQCHIP_GICv3) + +#endif diff --git a/arch/arm64/kvm/vgic/vgic-debug.c b/arch/arm64/kvm/vgic/vgic-debug.c index 340f960a1154..660499e5c797 100644 --- a/arch/arm64/kvm/vgic/vgic-debug.c +++ b/arch/arm64/kvm/vgic/vgic-debug.c @@ -61,7 +61,7 @@ static void iter_init(struct kvm *kvm, struct vgic_state_iter *iter, iter->nr_cpus = nr_cpus; iter->nr_spis = kvm->arch.vgic.nr_spis; - if (kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { + if (irqchip_is_gic_v3(kvm)) { iter->nr_lpis = vgic_copy_lpi_list(kvm, NULL, &iter->lpi_array); if (iter->nr_lpis < 0) iter->nr_lpis = 0; @@ -142,7 +142,8 @@ static void vgic_debug_stop(struct seq_file *s, void *v) static void print_dist_state(struct seq_file *s, struct vgic_dist *dist) { - bool v3 = dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3; + struct kvm *kvm = container_of(dist, struct kvm, arch.vgic); + bool v3 = irqchip_is_gic_v3(kvm); seq_printf(s, "Distributor\n"); seq_printf(s, "===========\n"); diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index 14c4ce075232..3e4be3c80290 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -136,8 +136,8 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) goto out_unlock; } - kvm->arch.vgic.in_kernel = true; - kvm->arch.vgic.vgic_model = type; + kvm->arch.irqchip_type = (type == KVM_DEV_TYPE_ARM_VGIC_V2 ? + IRQCHIP_GICv2 : IRQCHIP_GICv3); kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; @@ -186,12 +186,12 @@ static int kvm_vgic_dist_init(struct kvm *kvm, unsigned int nr_spis) irq->vcpu = NULL; irq->target_vcpu = vcpu0; kref_init(&irq->refcount); - switch (dist->vgic_model) { - case KVM_DEV_TYPE_ARM_VGIC_V2: + switch (kvm->arch.irqchip_type) { + case IRQCHIP_GICv2: irq->targets = 0; irq->group = 0; break; - case KVM_DEV_TYPE_ARM_VGIC_V3: + case IRQCHIP_GICv3: irq->mpidr = 0; irq->group = 1; break; @@ -216,7 +216,6 @@ static int kvm_vgic_dist_init(struct kvm *kvm, unsigned int nr_spis) int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) { struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; - struct vgic_dist *dist = &vcpu->kvm->arch.vgic; int ret = 0; int i; @@ -261,7 +260,7 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) * If we are creating a VCPU with a GICv3 we must also register the * KVM io device for the redistributor that belongs to this VCPU. */ - if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { + if (irqchip_is_gic_v3(vcpu->kvm)) { mutex_lock(&vcpu->kvm->slots_lock); ret = vgic_register_redist_iodev(vcpu); mutex_unlock(&vcpu->kvm->slots_lock); @@ -316,12 +315,12 @@ int vgic_init(struct kvm *kvm) for (i = 0; i < VGIC_NR_PRIVATE_IRQS; i++) { struct vgic_irq *irq = &vgic_cpu->private_irqs[i]; - switch (dist->vgic_model) { - case KVM_DEV_TYPE_ARM_VGIC_V3: + switch (kvm->arch.irqchip_type) { + case IRQCHIP_GICv3: irq->group = 1; irq->mpidr = kvm_vcpu_get_mpidr_aff(vcpu); break; - case KVM_DEV_TYPE_ARM_VGIC_V2: + case IRQCHIP_GICv2: irq->group = 0; irq->targets = 1U << idx; break; @@ -388,7 +387,7 @@ static void kvm_vgic_dist_destroy(struct kvm *kvm) dist->nr_spis = 0; dist->vgic_dist_base = VGIC_ADDR_UNDEF; - if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { + if (irqchip_is_gic_v3(kvm)) { list_for_each_entry_safe(rdreg, next, &dist->rd_regions, list) vgic_v3_free_redist_region(kvm, rdreg); INIT_LIST_HEAD(&dist->rd_regions); @@ -414,7 +413,7 @@ static void __kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu) vgic_flush_pending_lpis(vcpu); INIT_LIST_HEAD(&vgic_cpu->ap_list_head); - if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { + if (irqchip_is_gic_v3(vcpu->kvm)) { vgic_unregister_redist_iodev(vcpu); vgic_cpu->rd_iodev.base_addr = VGIC_ADDR_UNDEF; } @@ -466,7 +465,7 @@ int vgic_lazy_init(struct kvm *kvm) * be explicitly initialized once setup with the respective * KVM device call. */ - if (kvm->arch.vgic.vgic_model != KVM_DEV_TYPE_ARM_VGIC_V2) + if (!irqchip_is_gic_v2(kvm)) return -EBUSY; mutex_lock(&kvm->arch.config_lock); @@ -506,7 +505,7 @@ int kvm_vgic_map_resources(struct kvm *kvm) if (!irqchip_in_kernel(kvm)) goto out; - if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2) { + if (irqchip_is_gic_v2(kvm)) { ret = vgic_v2_map_resources(kvm); type = VGIC_V2; } else { diff --git a/arch/arm64/kvm/vgic/vgic-kvm-device.c b/arch/arm64/kvm/vgic/vgic-kvm-device.c index 2f9e8c611f64..d035d9eedb6d 100644 --- a/arch/arm64/kvm/vgic/vgic-kvm-device.c +++ b/arch/arm64/kvm/vgic/vgic-kvm-device.c @@ -35,10 +35,18 @@ int vgic_check_iorange(struct kvm *kvm, phys_addr_t ioaddr, static int vgic_check_type(struct kvm *kvm, int type_needed) { - if (kvm->arch.vgic.vgic_model != type_needed) - return -ENODEV; - else - return 0; + switch (type_needed) { + case KVM_DEV_TYPE_ARM_VGIC_V2: + if (irqchip_is_gic_v2(kvm)) + return 0; + break; + case KVM_DEV_TYPE_ARM_VGIC_V3: + if (irqchip_is_gic_v3(kvm)) + return 0; + break; + } + + return -ENODEV; } int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr) diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c index 623160d51e54..ea14c0c9d33d 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -42,7 +42,7 @@ bool vgic_has_its(struct kvm *kvm) { struct vgic_dist *dist = &kvm->arch.vgic; - if (dist->vgic_model != KVM_DEV_TYPE_ARM_VGIC_V3) + if (!irqchip_is_gic_v3(kvm)) return false; return dist->has_its; diff --git a/arch/arm64/kvm/vgic/vgic-mmio.c b/arch/arm64/kvm/vgic/vgic-mmio.c index 1b4a959601af..44a1a77ddd58 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio.c +++ b/arch/arm64/kvm/vgic/vgic-mmio.c @@ -279,8 +279,8 @@ static unsigned long __read_pending(struct kvm_vcpu *vcpu, } else if (!is_user && vgic_irq_is_mapped_level(irq)) { val = vgic_get_phys_line_level(irq); } else { - switch (vcpu->kvm->arch.vgic.vgic_model) { - case KVM_DEV_TYPE_ARM_VGIC_V3: + switch (vcpu->kvm->arch.irqchip_type) { + case IRQCHIP_GICv3: if (is_user) { val = irq->pending_latch; break; @@ -315,8 +315,7 @@ unsigned long vgic_uaccess_read_pending(struct kvm_vcpu *vcpu, static bool is_vgic_v2_sgi(struct kvm_vcpu *vcpu, struct vgic_irq *irq) { - return (vgic_irq_is_sgi(irq->intid) && - vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V2); + return (vgic_irq_is_sgi(irq->intid) && irqchip_is_gic_v2(vcpu->kvm)); } void vgic_mmio_write_spending(struct kvm_vcpu *vcpu, @@ -503,7 +502,7 @@ int vgic_uaccess_write_cpending(struct kvm_vcpu *vcpu, */ static void vgic_access_active_prepare(struct kvm_vcpu *vcpu, u32 intid) { - if ((vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 && + if ((irqchip_is_gic_v3(vcpu->kvm) && vcpu != kvm_get_running_vcpu()) || intid >= VGIC_NR_PRIVATE_IRQS) kvm_arm_halt_guest(vcpu->kvm); @@ -512,7 +511,7 @@ static void vgic_access_active_prepare(struct kvm_vcpu *vcpu, u32 intid) /* See vgic_access_active_prepare */ static void vgic_access_active_finish(struct kvm_vcpu *vcpu, u32 intid) { - if ((vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 && + if ((irqchip_is_gic_v3(vcpu->kvm) && vcpu != kvm_get_running_vcpu()) || intid >= VGIC_NR_PRIVATE_IRQS) kvm_arm_resume_guest(vcpu->kvm); @@ -610,7 +609,6 @@ static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq, irq->vtimer_info->set_active_stat(vcpu, irq->intid, active); #endif } else { - u32 model = vcpu->kvm->arch.vgic.vgic_model; u8 active_source; irq->active = active; @@ -628,7 +626,7 @@ static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq, */ active_source = (requester_vcpu) ? requester_vcpu->vcpu_id : 0; - if (model == KVM_DEV_TYPE_ARM_VGIC_V2 && + if (irqchip_is_gic_v2(vcpu->kvm) && active && vgic_irq_is_sgi(irq->intid)) irq->active_source = active_source; } diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c index 378cb6d370b1..f0fe7737a8ed 100644 --- a/arch/arm64/kvm/vgic/vgic-v3.c +++ b/arch/arm64/kvm/vgic/vgic-v3.c @@ -39,7 +39,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) { struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; - u32 model = vcpu->kvm->arch.vgic.vgic_model; + bool is_v3 = irqchip_is_gic_v3(vcpu->kvm); int lr; DEBUG_SPINLOCK_BUG_ON(!irqs_disabled()); @@ -56,7 +56,7 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) cpuid = val & GICH_LR_PHYSID_CPUID; cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT; - if (model == KVM_DEV_TYPE_ARM_VGIC_V3) { + if (is_v3) { intid = val & ICH_LR_VIRTUAL_ID_MASK; } else { intid = val & GICH_LR_VIRTUALID; @@ -109,12 +109,11 @@ void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu) /* Requires the irq to be locked already */ void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) { - u32 model = vcpu->kvm->arch.vgic.vgic_model; + bool is_v2 = irqchip_is_gic_v2(vcpu->kvm); u64 val = irq->intid; bool allow_pending = true, is_v2_sgi; - is_v2_sgi = (vgic_irq_is_sgi(irq->intid) && - model == KVM_DEV_TYPE_ARM_VGIC_V2); + is_v2_sgi = (vgic_irq_is_sgi(irq->intid) && is_v2); if (irq->active) { val |= ICH_LR_ACTIVE_BIT; @@ -155,8 +154,7 @@ void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr) if (irq->config == VGIC_CONFIG_EDGE) irq->pending_latch = false; - if (vgic_irq_is_sgi(irq->intid) && - model == KVM_DEV_TYPE_ARM_VGIC_V2) { + if (vgic_irq_is_sgi(irq->intid) && is_v2) { u32 src = ffs(irq->source); if (WARN_RATELIMIT(!src, "No SGI source for INTID %d\n", @@ -201,10 +199,9 @@ void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr) void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) { struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; - u32 model = vcpu->kvm->arch.vgic.vgic_model; u32 vmcr; - if (model == KVM_DEV_TYPE_ARM_VGIC_V2) { + if (irqchip_is_gic_v2(vcpu->kvm)) { vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) & ICH_VMCR_ACK_CTL_MASK; vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) & @@ -231,12 +228,11 @@ void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp) { struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; - u32 model = vcpu->kvm->arch.vgic.vgic_model; u32 vmcr; vmcr = cpu_if->vgic_vmcr; - if (model == KVM_DEV_TYPE_ARM_VGIC_V2) { + if (irqchip_is_gic_v2(vcpu->kvm)) { vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >> ICH_VMCR_ACK_CTL_SHIFT; vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >> @@ -281,7 +277,7 @@ void vgic_v3_enable(struct kvm_vcpu *vcpu) * Also, we don't support any form of IRQ/FIQ bypass. * This goes with the spec allowing the value to be RAO/WI. */ - if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { + if (irqchip_is_gic_v3(vcpu->kvm)) { vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB | ICC_SRE_EL1_DFB | ICC_SRE_EL1_SRE); diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h index f78c026c20f0..b7405cf95624 100644 --- a/arch/arm64/kvm/vgic/vgic.h +++ b/arch/arm64/kvm/vgic/vgic.h @@ -363,7 +363,7 @@ static inline bool kvm_has_gicv3(struct kvm *kvm) { return (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && irqchip_in_kernel(kvm) && - kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3); + irqchip_is_gic_v3(kvm)); } #endif diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 0b734d6f3d21..640507053c69 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -281,13 +281,9 @@ struct vgic_redist_region { }; struct vgic_dist { - bool in_kernel; bool ready; bool initialized; - /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ - u32 vgic_model; - /* Implementation revision as reported in the GICD_IIDR */ u32 implementation_rev; #define KVM_VGIC_IMP_REV_2 2 /* GICv2 restorable groups */ @@ -469,7 +465,6 @@ void kvm_vgic_load(struct kvm_vcpu *vcpu); void kvm_vgic_put(struct kvm_vcpu *vcpu); void kvm_vgic_vmcr_sync(struct kvm_vcpu *vcpu); -#define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel)) #define vgic_initialized(k) ((k)->arch.vgic.initialized) #define vgic_ready(k) ((k)->arch.vgic.ready) #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ -- 2.33.0

From: wanghaibin <wanghaibin.wang@huawei.com> As we are about to abstract part of the vgic implementation in order to make it more modular, let's start by adding a data structure that will eventually contain interrupt controller specific callbacks, as well as helpers to call them (or gracefully skip them if they aren't implemented. It is empty so far, so no functional changes are anticipated. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/include/asm/kvm_irq.h | 29 +++++++++++++++++++++++++++++ arch/arm64/kvm/vgic/vgic-init.c | 5 +++++ 3 files changed, 35 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index badc60577f91..3526c2256e94 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -219,6 +219,7 @@ struct kvm_arch { /* Interrupt controller */ enum kvm_irqchip_type irqchip_type; + struct kvm_irqchip_flow irqchip_flow; struct vgic_dist vgic; /* Timers */ diff --git a/arch/arm64/include/asm/kvm_irq.h b/arch/arm64/include/asm/kvm_irq.h index 46bffb6026f8..7a70bb803560 100644 --- a/arch/arm64/include/asm/kvm_irq.h +++ b/arch/arm64/include/asm/kvm_irq.h @@ -17,4 +17,33 @@ enum kvm_irqchip_type { #define irqchip_is_gic_v2(k) ((k)->arch.irqchip_type == IRQCHIP_GICv2) #define irqchip_is_gic_v3(k) ((k)->arch.irqchip_type == IRQCHIP_GICv3) +struct kvm_irqchip_flow { +}; + +/* + * Macro galore. At the point this is included, the various types are + * not defined yet. Yes, this is terminally ugly. + */ +#define __kvm_irqchip_action(k, x, ...) \ + do { \ + if (likely((k)->arch.irqchip_flow.irqchip_##x)) \ + (k)->arch.irqchip_flow.irqchip_##x(__VA_ARGS__); \ + } while (0) + +#define __kvm_irqchip_action_ret(k, x, ...) \ + ({ \ + typeof ((k)->arch.irqchip_flow.irqchip_##x(__VA_ARGS__)) ret; \ + ret = (likely((k)->arch.irqchip_flow.irqchip_##x) ? \ + (k)->arch.irqchip_flow.irqchip_##x(__VA_ARGS__) : \ + 0); \ + \ + ret; \ + }) + +#define __vcpu_irqchip_action(v, ...) \ + __kvm_irqchip_action((v)->kvm, __VA_ARGS__) + +#define __vcpu_irqchip_action_ret(v, ...) \ + __kvm_irqchip_action_ret((v)->kvm, __VA_ARGS__) + #endif diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index 52eac2530d54..be105bb97cb8 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -18,6 +18,9 @@ #include "hisilicon/hisi_virt.h" #endif +static struct kvm_irqchip_flow vgic_irqchip_flow = { +}; + /* * Initialization rules: there are multiple stages to the vgic * initialization, both for the distributor and the CPU interfaces. The basic @@ -63,6 +66,8 @@ static void kvm_vgic_early_init(struct kvm *kvm) int i; #endif + kvm->arch.irqchip_flow = vgic_irqchip_flow; + INIT_LIST_HEAD(&dist->lpi_list_head); #ifdef CONFIG_KVM_ARM_MULTI_LPI_TRANSLATE_CACHE for (i = 0; i < LPI_TRANS_CACHES_NUM; i++) { -- 2.33.0

From: wanghaibin <wanghaibin.wang@huawei.com> Abstract kvm_vgic_vcpu_init() by moving it to the irqchip_flow structure. This results in a minor change of the way we initialize vcpus: VCPUs created prior to the creation of the vgic device don't have their local view of the vgic initialized. This means that on vgic instantiation, we must "catch up" and initialise the CPU interfaces for these vcpus. VCPUs created after the vgic device will follow the unusual flow. Special care must be taken to accomodate the different locking contexts though. The function can then be made static and the irqchip_in_kernel() test dropped, as we only get here if a vgic has been created. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- arch/arm64/include/asm/kvm_irq.h | 4 ++++ arch/arm64/kvm/arm.c | 2 +- arch/arm64/kvm/vgic/vgic-init.c | 39 ++++++++++++++++++++++++++------ include/kvm/arm_vgic.h | 1 - 4 files changed, 37 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/kvm_irq.h b/arch/arm64/include/asm/kvm_irq.h index 42d110155627..8fa29ede1835 100644 --- a/arch/arm64/include/asm/kvm_irq.h +++ b/arch/arm64/include/asm/kvm_irq.h @@ -20,6 +20,7 @@ enum kvm_irqchip_type { struct kvm_irqchip_flow { void (*irqchip_destroy)(struct kvm *); void (*irqchip_vcpu_destroy)(struct kvm_vcpu *vcpu); + int (*irqchip_vcpu_init)(struct kvm_vcpu *); }; /* @@ -55,4 +56,7 @@ struct kvm_irqchip_flow { #define kvm_irqchip_vcpu_destroy(v) \ __vcpu_irqchip_action((v), vcpu_destroy, (v)) +#define kvm_irqchip_vcpu_init(v) \ + __vcpu_irqchip_action_ret((v), vcpu_init, (v)) + #endif diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 9a21a064afb3..3fc15c48ec0c 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -636,7 +636,7 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) vcpu->arch.hw_mmu = &vcpu->kvm->arch.mmu; - err = kvm_vgic_vcpu_init(vcpu); + err = kvm_irqchip_vcpu_init(vcpu); if (err) return err; diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index 0c8972404b79..45a5dc95a910 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -18,12 +18,14 @@ #include "hisilicon/hisi_virt.h" #endif +static int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); static void kvm_vgic_destroy(struct kvm *kvm); static void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); static struct kvm_irqchip_flow vgic_irqchip_flow = { .irqchip_destroy = kvm_vgic_destroy, .irqchip_vcpu_destroy = kvm_vgic_vcpu_destroy, + .irqchip_vcpu_init = kvm_vgic_vcpu_init, }; /* @@ -90,6 +92,8 @@ static void kvm_vgic_early_init(struct kvm *kvm) #endif } +static int __kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); + /* CREATION */ /** @@ -158,8 +162,22 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) kvm_vgic_early_init(kvm); + out_unlock: mutex_unlock(&kvm->arch.config_lock); + + /* + * vcpus may have been created before the GIC. Initialize + * them. Careful that kvm->lock is held already on the + * KVM_CREATE_DEVICE path, so use the non-locking version. + * fix: need slot lock, use the lock vcpu init + */ + kvm_for_each_vcpu(i, vcpu, kvm) { + ret = kvm_vgic_vcpu_init(vcpu); + if (ret) + break; + } + unlock_all_vcpus(kvm); return ret; } @@ -225,7 +243,7 @@ static int kvm_vgic_dist_init(struct kvm *kvm, unsigned int nr_spis) * Only do initialization, but do not actually enable the * VGIC CPU interface */ -int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) +static int __kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) { struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; int ret = 0; @@ -265,18 +283,25 @@ int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) #endif } - if (!irqchip_in_kernel(vcpu->kvm)) - return 0; /* * If we are creating a VCPU with a GICv3 we must also register the * KVM io device for the redistributor that belongs to this VCPU. */ - if (irqchip_is_gic_v3(vcpu->kvm)) { - mutex_lock(&vcpu->kvm->slots_lock); + if (irqchip_is_gic_v3(vcpu->kvm)) ret = vgic_register_redist_iodev(vcpu); - mutex_unlock(&vcpu->kvm->slots_lock); - } + + return ret; +} + +static int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu) +{ + int ret; + + mutex_lock(&vcpu->kvm->slots_lock); + ret = __kvm_vgic_vcpu_init(vcpu); + mutex_unlock(&vcpu->kvm->slots_lock); + return ret; } diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 6b650434e499..b6132c062725 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -442,7 +442,6 @@ extern struct static_key_false vgic_v2_cpuif_trap; extern struct static_key_false vgic_v3_cpuif_trap; int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr); -int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); int kvm_vgic_create(struct kvm *kvm, u32 type); int kvm_vgic_map_resources(struct kvm *kvm); int kvm_vgic_hyp_init(void); -- 2.33.0

From: wanghaibin <wanghaibin.wang@huawei.com> Abstract the calls to kvm_vgic_vcpu_load/put() via the irqchip_flow structure. No functional change. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- arch/arm64/include/asm/kvm_irq.h | 8 ++++++++ arch/arm64/kvm/arm.c | 4 ++-- arch/arm64/kvm/vgic/vgic-init.c | 2 ++ arch/arm64/kvm/vgic/vgic.h | 3 +++ arch/arm64/kvm/virtcca_cvm.c | 2 +- include/kvm/arm_vgic.h | 3 --- 6 files changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/kvm_irq.h b/arch/arm64/include/asm/kvm_irq.h index efb12693db13..08c93bab3036 100644 --- a/arch/arm64/include/asm/kvm_irq.h +++ b/arch/arm64/include/asm/kvm_irq.h @@ -23,6 +23,8 @@ struct kvm_irqchip_flow { int (*irqchip_vcpu_init)(struct kvm_vcpu *); void (*irqchip_vcpu_blocking)(struct kvm_vcpu *); void (*irqchip_vcpu_unblocking)(struct kvm_vcpu *); + void (*irqchip_vcpu_load)(struct kvm_vcpu *); + void (*irqchip_vcpu_put)(struct kvm_vcpu *); }; /* @@ -67,4 +69,10 @@ struct kvm_irqchip_flow { #define kvm_irqchip_vcpu_unblocking(v) \ __vcpu_irqchip_action((v), vcpu_unblocking, (v)) +#define kvm_irqchip_vcpu_load(v) \ + __vcpu_irqchip_action((v), vcpu_load, (v)) + +#define kvm_irqchip_vcpu_put(v) \ + __vcpu_irqchip_action((v), vcpu_put, (v)) + #endif diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 11a1bbc4a3b7..8e8526bf8b3a 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -731,7 +731,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) vcpu->cpu = cpu; - kvm_vgic_load(vcpu); + kvm_irqchip_vcpu_load(vcpu); kvm_timer_vcpu_load(vcpu); if (kvm_arm_is_pvtime_enabled(&vcpu->arch)) kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); @@ -769,7 +769,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) { kvm_timer_vcpu_put(vcpu); - kvm_vgic_put(vcpu); + kvm_irqchip_vcpu_put(vcpu); vcpu->cpu = -1; diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index 7367bb5bff1e..62e352e5aeed 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -28,6 +28,8 @@ static struct kvm_irqchip_flow vgic_irqchip_flow = { .irqchip_vcpu_init = kvm_vgic_vcpu_init, .irqchip_vcpu_blocking = kvm_vgic_vcpu_blocking, .irqchip_vcpu_unblocking = kvm_vgic_vcpu_unblocking, + .irqchip_vcpu_load = kvm_vgic_load, + .irqchip_vcpu_put = kvm_vgic_put, }; /* diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h index 3cf986eeec93..c18604139cd5 100644 --- a/arch/arm64/kvm/vgic/vgic.h +++ b/arch/arm64/kvm/vgic/vgic.h @@ -369,4 +369,7 @@ static inline bool kvm_has_gicv3(struct kvm *kvm) irqchip_is_gic_v3(kvm)); } +void kvm_vgic_load(struct kvm_vcpu *vcpu); +void kvm_vgic_put(struct kvm_vcpu *vcpu); + #endif diff --git a/arch/arm64/kvm/virtcca_cvm.c b/arch/arm64/kvm/virtcca_cvm.c index c270f33ce933..4558afa969bd 100644 --- a/arch/arm64/kvm/virtcca_cvm.c +++ b/arch/arm64/kvm/virtcca_cvm.c @@ -964,7 +964,7 @@ int kvm_load_user_data(struct kvm *kvm, unsigned long arg) void kvm_cvm_vcpu_put(struct kvm_vcpu *vcpu) { kvm_timer_vcpu_put(vcpu); - kvm_vgic_put(vcpu); + kvm_irqchip_vcpu_put(vcpu); vcpu->cpu = -1; } diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 54e222fb0aa8..598fde9c578b 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -457,9 +457,6 @@ bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid); int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); -void kvm_vgic_load(struct kvm_vcpu *vcpu); -void kvm_vgic_put(struct kvm_vcpu *vcpu); - #define vgic_initialized(k) ((k)->arch.vgic.initialized) #define vgic_ready(k) ((k)->arch.vgic.ready) #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ -- 2.33.0

From: wanghaibin <wanghaibin.wang@huawei.com> The "first run" part of the vgic init is pretty cumbersome, as it leaks all over the place. Reduce its footprint by moving it to an actual per-vcpu "first run" callback, and let it deal with the resource mapping. This allows the vgic_ready() macro to be made vgic-private, and placed in the common vgic code instead of the architecture backends. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- arch/arm64/include/asm/kvm_irq.h | 4 ++++ arch/arm64/kvm/arm.c | 6 +----- arch/arm64/kvm/vgic/vgic-init.c | 12 ++++++------ arch/arm64/kvm/vgic/vgic.h | 2 ++ include/kvm/arm_vgic.h | 2 -- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm64/include/asm/kvm_irq.h b/arch/arm64/include/asm/kvm_irq.h index 00debef7c2ed..460e32d89d0f 100644 --- a/arch/arm64/include/asm/kvm_irq.h +++ b/arch/arm64/include/asm/kvm_irq.h @@ -26,6 +26,7 @@ struct kvm_irqchip_flow { void (*irqchip_vcpu_load)(struct kvm_vcpu *); void (*irqchip_vcpu_put)(struct kvm_vcpu *); int (*irqchip_vcpu_pending_irq)(struct kvm_vcpu *); + int (*irqchip_vcpu_first_run)(struct kvm_vcpu *); }; /* @@ -79,4 +80,7 @@ struct kvm_irqchip_flow { #define kvm_irqchip_vcpu_pending_irq(v) \ __vcpu_irqchip_action_ret((v), vcpu_pending_irq, (v)) +#define kvm_irqchip_vcpu_first_run(v) \ + __vcpu_irqchip_action_ret((v), vcpu_first_run, (v)) + #endif diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 89c5c3b9403c..cfd0c5034c04 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -916,11 +916,7 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) #endif if (likely(irqchip_in_kernel(kvm))) { - /* - * Map the VGIC hardware resources before running a vcpu the - * first time on this VM. - */ - ret = kvm_vgic_map_resources(kvm); + ret = kvm_irqchip_vcpu_first_run(vcpu); if (ret) return ret; } diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index d63989cca594..a58855f485ae 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -18,6 +18,7 @@ #include "hisilicon/hisi_virt.h" #endif +static int kvm_vgic_vcpu_first_run(struct kvm_vcpu *vcpu); static int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu); static void kvm_vgic_destroy(struct kvm *kvm); static void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu); @@ -31,6 +32,7 @@ static struct kvm_irqchip_flow vgic_irqchip_flow = { .irqchip_vcpu_load = kvm_vgic_load, .irqchip_vcpu_put = kvm_vgic_put, .irqchip_vcpu_pending_irq = kvm_vgic_vcpu_pending_irq, + .irqchip_vcpu_first_run = kvm_vgic_vcpu_first_run, }; /* @@ -527,10 +529,11 @@ int vgic_lazy_init(struct kvm *kvm) * v2 calls vgic_init() if not already done. * v3 and derivatives return an error if the VGIC is not initialized. * vgic_ready() returns true if this function has succeeded. - * @kvm: kvm struct pointer - */ -int kvm_vgic_map_resources(struct kvm *kvm) + * @vcpu: vcpu struct pointer +*/ +static int kvm_vgic_vcpu_first_run(struct kvm_vcpu *vcpu) { + struct kvm *kvm = vcpu->kvm; struct vgic_dist *dist = &kvm->arch.vgic; enum vgic_type type; gpa_t dist_base; @@ -544,9 +547,6 @@ int kvm_vgic_map_resources(struct kvm *kvm) if (vgic_ready(kvm)) goto out; - if (!irqchip_in_kernel(kvm)) - goto out; - if (irqchip_is_gic_v2(kvm)) { ret = vgic_v2_map_resources(kvm); type = VGIC_V2; diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h index 6858d233c05c..3f2b8236ebcd 100644 --- a/arch/arm64/kvm/vgic/vgic.h +++ b/arch/arm64/kvm/vgic/vgic.h @@ -104,6 +104,8 @@ static inline u32 vgic_get_implementation_rev(struct kvm_vcpu *vcpu) return vcpu->kvm->arch.vgic.implementation_rev; } +#define vgic_ready(k) ((k)->arch.vgic.ready) + /* Requires the irq_lock to be held by the caller. */ static inline bool irq_is_pending(struct vgic_irq *irq) { diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 9c2573e3d35f..b260f4064aab 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -443,7 +443,6 @@ extern struct static_key_false vgic_v3_cpuif_trap; int kvm_set_legacy_vgic_v2_addr(struct kvm *kvm, struct kvm_arm_device_addr *dev_addr); int kvm_vgic_create(struct kvm *kvm, u32 type); -int kvm_vgic_map_resources(struct kvm *kvm); int kvm_vgic_hyp_init(void); void kvm_vgic_init_cpu_hardware(void); @@ -456,7 +455,6 @@ int kvm_vgic_get_map(struct kvm_vcpu *vcpu, unsigned int vintid); bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid); #define vgic_initialized(k) ((k)->arch.vgic.initialized) -#define vgic_ready(k) ((k)->arch.vgic.ready) #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) -- 2.33.0

From: wanghaibin <wanghaibin.wang@huawei.com> If we aren't modeling a GIC, there is no need to save/restore the GICv3 state at all. Note that this only matters for nVHE, as VHE already has this code outside of the world switch. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- arch/arm64/kvm/hyp/nvhe/switch.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c index ff502b5e1480..68f2f7bf5fc1 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -115,7 +115,10 @@ static void __deactivate_traps(struct kvm_vcpu *vcpu) /* Save VGICv3 state on non-VHE systems */ static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu) { - if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { + struct kvm *kvm = kern_hyp_va(vcpu->kvm); + + if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && + (irqchip_is_gic_v2(kvm) || irqchip_is_gic_v3(kvm))) { __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3); __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3); } @@ -124,7 +127,10 @@ static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu) /* Restore VGICv3 state on non-VHE systems */ static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu) { - if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { + struct kvm *kvm = kern_hyp_va(vcpu->kvm); + + if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) && + (irqchip_is_gic_v2(kvm) || irqchip_is_gic_v3(kvm))) { __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3); __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3); } -- 2.33.0

From: wanghaibin <wanghaibin.wang@huawei.com> As we continue cutting a VGIC-shaped hole in KVM, let's indirect all of the handling of mapped interrupts into the bit irqchip_flow bucket. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- arch/arm64/include/asm/kvm_irq.h | 18 +++++++++++++ arch/arm64/kvm/arch_timer.c | 44 ++++++++++++++++---------------- arch/arm64/kvm/vgic/vgic-init.c | 4 +++ arch/arm64/kvm/vgic/vgic.h | 8 ++++++ include/kvm/arm_vgic.h | 6 ----- 5 files changed, 52 insertions(+), 28 deletions(-) diff --git a/arch/arm64/include/asm/kvm_irq.h b/arch/arm64/include/asm/kvm_irq.h index 4b5e4a280395..40fe9e826ee4 100644 --- a/arch/arm64/include/asm/kvm_irq.h +++ b/arch/arm64/include/asm/kvm_irq.h @@ -6,6 +6,7 @@ #ifndef __ARM64_KVM_IRQ_H__ #define __ARM64_KVM_IRQ_H__ +#include <kvm/arm_vgic.h> /* fix */ enum kvm_irqchip_type { IRQCHIP_USER, /* Implemented in userspace */ @@ -34,6 +35,11 @@ struct kvm_irqchip_flow { int (*irqchip_inject_userspace_irq)(struct kvm *, unsigned int type, unsigned int cpu, unsigned int intid, bool); + bool (*irqchip_map_is_active)(struct kvm_vcpu *, unsigned in); + void (*irqchip_reset_mapped_irq)(struct kvm_vcpu *, u32); + int (*irqchip_map_phys_irq)(struct kvm_vcpu *, unsigned int, + u32, struct irq_ops *); + int (*irqchip_unmap_phys_irq)(struct kvm_vcpu *, unsigned int); }; /* @@ -102,4 +108,16 @@ struct kvm_irqchip_flow { #define kvm_irqchip_inject_userspace_irq(k, ...) \ __kvm_irqchip_action_ret((k), inject_userspace_irq, (k), __VA_ARGS__) +#define kvm_irqchip_map_is_active(v, ...) \ + __vcpu_irqchip_action_ret((v), map_is_active, (v), __VA_ARGS__) + +#define kvm_irqchip_reset_mapped_irq(v, ...) \ + __vcpu_irqchip_action((v), reset_mapped_irq, (v), __VA_ARGS__) + +#define kvm_irqchip_map_phys_irq(v, ...) \ + __vcpu_irqchip_action_ret((v), map_phys_irq, (v), __VA_ARGS__) + +#define kvm_irqchip_unmap_phys_irq(v, ...) \ + __vcpu_irqchip_action_ret((v), unmap_phys_irq, (v), __VA_ARGS__) + #endif diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index d02c7414c4da..cb652edb04a7 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -811,7 +811,7 @@ static void kvm_timer_vcpu_load_gic(struct arch_timer_context *ctx) kvm_timer_update_irq(ctx->vcpu, kvm_timer_should_fire(ctx), ctx); if (irqchip_in_kernel(vcpu->kvm)) - phys_active = kvm_vgic_map_is_active(vcpu, timer_irq(ctx)); + phys_active = kvm_irqchip_map_is_active(vcpu, timer_irq(ctx)); phys_active |= ctx->irq.level; @@ -875,18 +875,18 @@ static void kvm_timer_vcpu_load_nested_switch(struct kvm_vcpu *vcpu, */ hw = kvm_vgic_get_map(vcpu, timer_irq(map->direct_vtimer)); if (hw < 0) { - kvm_vgic_unmap_phys_irq(vcpu, timer_irq(map->emul_vtimer)); - kvm_vgic_unmap_phys_irq(vcpu, timer_irq(map->emul_ptimer)); + kvm_irqchip_unmap_phys_irq(vcpu, timer_irq(map->emul_vtimer)); + kvm_irqchip_unmap_phys_irq(vcpu, timer_irq(map->emul_ptimer)); - ret = kvm_vgic_map_phys_irq(vcpu, - map->direct_vtimer->host_timer_irq, - timer_irq(map->direct_vtimer), - &arch_timer_irq_ops); + ret = kvm_irqchip_map_phys_irq(vcpu, + map->direct_vtimer->host_timer_irq, + timer_irq(map->direct_vtimer), + &arch_timer_irq_ops); WARN_ON_ONCE(ret); - ret = kvm_vgic_map_phys_irq(vcpu, - map->direct_ptimer->host_timer_irq, - timer_irq(map->direct_ptimer), - &arch_timer_irq_ops); + ret = kvm_irqchip_map_phys_irq(vcpu, + map->direct_ptimer->host_timer_irq, + timer_irq(map->direct_ptimer), + &arch_timer_irq_ops); WARN_ON_ONCE(ret); /* @@ -1190,7 +1190,7 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu) kvm_timer_update_irq(vcpu, false, vcpu_ptimer(vcpu)); if (irqchip_in_kernel(vcpu->kvm) && map.direct_ptimer) - kvm_vgic_reset_mapped_irq(vcpu, timer_irq(map.direct_ptimer)); + kvm_irqchip_reset_mapped_irq(vcpu, timer_irq(map.direct_ptimer)); goto skip_reset_vtimer; } @@ -1200,9 +1200,9 @@ int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu) vcpu_get_timer(vcpu, i)); if (irqchip_in_kernel(vcpu->kvm)) { - kvm_vgic_reset_mapped_irq(vcpu, timer_irq(map.direct_vtimer)); + kvm_irqchip_reset_mapped_irq(vcpu, timer_irq(map.direct_vtimer)); if (map.direct_ptimer) - kvm_vgic_reset_mapped_irq(vcpu, timer_irq(map.direct_ptimer)); + kvm_irqchip_reset_mapped_irq(vcpu, timer_irq(map.direct_ptimer)); } } @@ -1901,10 +1901,10 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) if (vtimer_is_irqbypass()) goto skip_map_vtimer; #endif - ret = kvm_vgic_map_phys_irq(vcpu, - map.direct_vtimer->host_timer_irq, - timer_irq(map.direct_vtimer), - &arch_timer_irq_ops); + ret = kvm_irqchip_map_phys_irq(vcpu, + map.direct_vtimer->host_timer_irq, + timer_irq(map.direct_vtimer), + &arch_timer_irq_ops); if (ret) return ret; @@ -1912,10 +1912,10 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) skip_map_vtimer: #endif if (map.direct_ptimer) { - ret = kvm_vgic_map_phys_irq(vcpu, - map.direct_ptimer->host_timer_irq, - timer_irq(map.direct_ptimer), - &arch_timer_irq_ops); + ret = kvm_irqchip_map_phys_irq(vcpu, + map.direct_ptimer->host_timer_irq, + timer_irq(map.direct_ptimer), + &arch_timer_irq_ops); } if (ret) diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index 71fb7b6b1a1b..e2667f8c5002 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -37,6 +37,10 @@ static struct kvm_irqchip_flow vgic_irqchip_flow = { .irqchip_vcpu_sync_hwstate = kvm_vgic_sync_hwstate, .irqchip_inject_irq = kvm_vgic_inject_irq, .irqchip_inject_userspace_irq = kvm_vgic_inject_userspace_irq, + .irqchip_map_is_active = kvm_vgic_map_is_active, + .irqchip_reset_mapped_irq = kvm_vgic_reset_mapped_irq, + .irqchip_map_phys_irq = kvm_vgic_map_phys_irq, + .irqchip_unmap_phys_irq = kvm_vgic_unmap_phys_irq, }; /* diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h index ec149e8dd59b..612d161dc409 100644 --- a/arch/arm64/kvm/vgic/vgic.h +++ b/arch/arm64/kvm/vgic/vgic.h @@ -377,6 +377,14 @@ static inline bool kvm_has_gicv3(struct kvm *kvm) irqchip_is_gic_v3(kvm)); } +bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid); +void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid); + +int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq, + u32 vintid, struct irq_ops *ops); +int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid); + + int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu); void kvm_vgic_load(struct kvm_vcpu *vcpu); diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 53a0c3d20fc6..9bd83bc8e1aa 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -446,18 +446,12 @@ int kvm_vgic_create(struct kvm *kvm, u32 type); int kvm_vgic_hyp_init(void); void kvm_vgic_init_cpu_hardware(void); -int kvm_vgic_map_phys_irq(struct kvm_vcpu *vcpu, unsigned int host_irq, - u32 vintid, struct irq_ops *ops); -int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid); int kvm_vgic_get_map(struct kvm_vcpu *vcpu, unsigned int vintid); -bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid); #define vgic_initialized(k) ((k)->arch.vgic.initialized) #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) -void kvm_vgic_reset_mapped_irq(struct kvm_vcpu *vcpu, u32 vintid); - void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1); #ifdef CONFIG_VIRT_VTIMER_IRQ_BYPASS -- 2.33.0

From: wanghaibin <wanghaibin.wang@huawei.com> As we aim to make the core KVM/arm64 code GIC-agnostic, let's turn vgic_initialized into something more generic, and move the corresponding flag outside of the vgic data structure. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/include/asm/kvm_irq.h | 2 ++ arch/arm64/kvm/arm.c | 4 ++-- arch/arm64/kvm/pmu-emul.c | 2 +- arch/arm64/kvm/vgic/vgic-debug.c | 2 +- arch/arm64/kvm/vgic/vgic-init.c | 11 +++++------ arch/arm64/kvm/vgic/vgic-irqfd.c | 2 +- arch/arm64/kvm/vgic/vgic-its.c | 2 +- arch/arm64/kvm/vgic/vgic-kvm-device.c | 2 +- arch/arm64/kvm/vgic/vgic-v3.c | 4 ++-- arch/arm64/kvm/vgic/vgic.c | 10 +++++----- include/kvm/arm_vgic.h | 2 -- 12 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 3526c2256e94..9329163ffc93 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -219,6 +219,7 @@ struct kvm_arch { /* Interrupt controller */ enum kvm_irqchip_type irqchip_type; + bool irqchip_finalized; struct kvm_irqchip_flow irqchip_flow; struct vgic_dist vgic; diff --git a/arch/arm64/include/asm/kvm_irq.h b/arch/arm64/include/asm/kvm_irq.h index 5665bb668c19..5696dd949ad1 100644 --- a/arch/arm64/include/asm/kvm_irq.h +++ b/arch/arm64/include/asm/kvm_irq.h @@ -18,6 +18,8 @@ enum kvm_irqchip_type { #define irqchip_is_gic_v2(k) ((k)->arch.irqchip_type == IRQCHIP_GICv2) #define irqchip_is_gic_v3(k) ((k)->arch.irqchip_type == IRQCHIP_GICv3) +#define irqchip_finalized(k) ((k)->arch.irqchip_finalized) + struct kvm_irqchip_flow { void (*irqchip_destroy)(struct kvm *); void (*irqchip_vcpu_destroy)(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index a0c048944ec2..328afbfb9c96 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -582,7 +582,7 @@ struct kvm *kvm_arch_alloc_vm(void) int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) { - if (irqchip_in_kernel(kvm) && vgic_initialized(kvm)) + if (irqchip_in_kernel(kvm) && irqchip_finalized(kvm)) return -EBUSY; if (id >= kvm->max_vcpus) @@ -971,7 +971,7 @@ void kvm_arch_pinned_vmid_put(struct kvm *kvm) bool kvm_arch_intc_initialized(struct kvm *kvm) { - return vgic_initialized(kvm); + return (irqchip_in_kernel(kvm) && irqchip_finalized(kvm)); } void kvm_arm_halt_guest(struct kvm *kvm) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index fdc27f16e157..9776e4259021 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -853,7 +853,7 @@ static int kvm_arm_pmu_v3_init(struct kvm_vcpu *vcpu) * implementation, we require the GIC to be already * initialized when initializing the PMU. */ - if (!vgic_initialized(vcpu->kvm)) + if (!irqchip_finalized(vcpu->kvm)) return -ENODEV; if (!kvm_arm_pmu_irq_initialized(vcpu)) diff --git a/arch/arm64/kvm/vgic/vgic-debug.c b/arch/arm64/kvm/vgic/vgic-debug.c index 660499e5c797..9600fd891376 100644 --- a/arch/arm64/kvm/vgic/vgic-debug.c +++ b/arch/arm64/kvm/vgic/vgic-debug.c @@ -242,7 +242,7 @@ static int vgic_debug_show(struct seq_file *s, void *v) return 0; } - if (!kvm->arch.vgic.initialized) + if (!irqchip_finalized(kvm)) return 0; if (iter->vcpu_id < iter->nr_cpus) diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index 8e584fefe768..5f37d2362453 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -336,7 +336,7 @@ static void kvm_vgic_vcpu_enable(struct kvm_vcpu *vcpu) * - the number of vcpus * The function is generally called when nr_spis has been explicitly set * by the guest through the KVM DEVICE API. If not nr_spis is set to 256. - * vgic_initialized() returns true when this function has succeeded. + * irqchip_finalized() returns true when this function has succeeded. */ int vgic_init(struct kvm *kvm) { @@ -347,7 +347,7 @@ int vgic_init(struct kvm *kvm) lockdep_assert_held(&kvm->arch.config_lock); - if (vgic_initialized(kvm)) + if (irqchip_finalized(kvm)) return 0; /* Are we also in the middle of creating a VCPU? */ @@ -421,8 +421,7 @@ int vgic_init(struct kvm *kvm) dist->has_nmi = kvm_vgic_global_state.has_nmi; } - dist->initialized = true; - + kvm->arch.irqchip_finalized = true; out: return ret; } @@ -432,8 +431,8 @@ static void kvm_vgic_dist_destroy(struct kvm *kvm) struct vgic_dist *dist = &kvm->arch.vgic; struct vgic_redist_region *rdreg, *next; + kvm->arch.irqchip_finalized = false; dist->ready = false; - dist->initialized = false; kfree(dist->spis); dist->spis = NULL; @@ -511,7 +510,7 @@ int vgic_lazy_init(struct kvm *kvm) { int ret = 0; - if (unlikely(!vgic_initialized(kvm))) { + if (unlikely(!irqchip_finalized(kvm))) { /* * We only provide the automatic initialization of the VGIC * for the legacy case of a GICv2. Any other type must diff --git a/arch/arm64/kvm/vgic/vgic-irqfd.c b/arch/arm64/kvm/vgic/vgic-irqfd.c index f7de55ae55be..e3c1197332b5 100644 --- a/arch/arm64/kvm/vgic/vgic-irqfd.c +++ b/arch/arm64/kvm/vgic/vgic-irqfd.c @@ -168,7 +168,7 @@ int kvm_arch_set_irq_inatomic(struct kvm_kernel_irq_routing_entry *e, * Injecting SPIs is always possible in atomic context * as long as the damn vgic is initialized. */ - if (unlikely(!vgic_initialized(kvm))) + if (unlikely(!irqchip_finalized(kvm))) break; return vgic_irqfd_set_irq(e, kvm, irq_source_id, 1, line_status); } diff --git a/arch/arm64/kvm/vgic/vgic-its.c b/arch/arm64/kvm/vgic/vgic-its.c index fdeb22083196..f1e88e08564b 100644 --- a/arch/arm64/kvm/vgic/vgic-its.c +++ b/arch/arm64/kvm/vgic/vgic-its.c @@ -2209,7 +2209,7 @@ static int vgic_its_create(struct kvm_device *dev, u32 type) mutex_lock(&dev->kvm->arch.config_lock); - if (vgic_initialized(dev->kvm)) { + if (irqchip_finalized(dev->kvm)) { ret = vgic_v4_init(dev->kvm); if (ret < 0) { mutex_unlock(&dev->kvm->arch.config_lock); diff --git a/arch/arm64/kvm/vgic/vgic-kvm-device.c b/arch/arm64/kvm/vgic/vgic-kvm-device.c index d035d9eedb6d..4cfb873ebaf8 100644 --- a/arch/arm64/kvm/vgic/vgic-kvm-device.c +++ b/arch/arm64/kvm/vgic/vgic-kvm-device.c @@ -554,7 +554,7 @@ static int vgic_v3_attr_regs_access(struct kvm_device *dev, mutex_lock(&dev->kvm->arch.config_lock); - if (unlikely(!vgic_initialized(dev->kvm))) { + if (unlikely(!irqchip_finalized(dev->kvm))) { ret = -EBUSY; goto out; } diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c index f0fe7737a8ed..9c4b397b9cba 100644 --- a/arch/arm64/kvm/vgic/vgic-v3.c +++ b/arch/arm64/kvm/vgic/vgic-v3.c @@ -386,7 +386,7 @@ int vgic_v3_save_pending_tables(struct kvm *kvm) int ret = 0; u8 val; - if (unlikely(!vgic_initialized(kvm))) + if (unlikely(!irqchip_finalized(kvm))) return -ENXIO; /* @@ -567,7 +567,7 @@ int vgic_v3_map_resources(struct kvm *kvm) * For a VGICv3 we require the userland to explicitly initialize * the VGIC before we need to use it. */ - if (!vgic_initialized(kvm)) { + if (!irqchip_finalized(kvm)) { return -EBUSY; } diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c index 934ef4918655..8ce7666972d3 100644 --- a/arch/arm64/kvm/vgic/vgic.c +++ b/arch/arm64/kvm/vgic/vgic.c @@ -595,7 +595,7 @@ int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid) struct vgic_irq *irq; unsigned long flags; - if (!vgic_initialized(vcpu->kvm)) + if (!irqchip_finalized(vcpu->kvm)) return -EAGAIN; irq = vgic_get_irq(vcpu->kvm, vcpu, vintid); @@ -666,7 +666,7 @@ int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner) unsigned long flags; int ret = 0; - if (!vgic_initialized(vcpu->kvm)) + if (!irqchip_finalized(vcpu->kvm)) return -EAGAIN; /* SGIs and LPIs cannot be wired up to any device */ @@ -1071,7 +1071,7 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) void kvm_vgic_load(struct kvm_vcpu *vcpu) { if (unlikely(!irqchip_in_kernel(vcpu->kvm) || - !vgic_initialized(vcpu->kvm) || + !irqchip_finalized(vcpu->kvm) || vcpu_is_rec(vcpu))) { if (has_vhe() && static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3); @@ -1087,7 +1087,7 @@ void kvm_vgic_load(struct kvm_vcpu *vcpu) void kvm_vgic_put(struct kvm_vcpu *vcpu) { if (unlikely(!irqchip_in_kernel(vcpu->kvm) || - !vgic_initialized(vcpu->kvm) || + !irqchip_finalized(vcpu->kvm) || vcpu_is_rec(vcpu))) { if (has_vhe() && static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3); @@ -1187,7 +1187,7 @@ bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid) bool map_is_active; unsigned long flags; - if (!vgic_initialized(vcpu->kvm)) + if (!irqchip_finalized(vcpu->kvm)) return false; irq = vgic_get_irq(vcpu->kvm, vcpu, vintid); diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 45a4d786b75a..1c11a13716e0 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -282,7 +282,6 @@ struct vgic_redist_region { struct vgic_dist { bool ready; - bool initialized; /* Implementation revision as reported in the GICD_IIDR */ u32 implementation_rev; @@ -448,7 +447,6 @@ void kvm_vgic_init_cpu_hardware(void); int kvm_vgic_get_map(struct kvm_vcpu *vcpu, unsigned int vintid); -#define vgic_initialized(k) ((k)->arch.vgic.initialized) #define vgic_valid_spi(k, i) (((i) >= VGIC_NR_PRIVATE_IRQS) && \ ((i) < (k)->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS)) -- 2.33.0

From: Marc Zyngier <maz@kernel.org> Although it is safe for now, do condition the returning of a msis_require_devid capability on the irqchip being a GICv3. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- arch/arm64/kvm/arm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 2e67b6353c06..5b207573fbfb 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -478,7 +478,8 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) if (!kvm) r = -EINVAL; else - r = kvm->arch.vgic.msis_require_devid; + r = (irqchip_is_gic_v3(kvm) && + kvm->arch.vgic.msis_require_devid); break; case KVM_CAP_ARM_USER_IRQ: /* -- 2.33.0

From: Marc Zyngier <maz@kernel.org> It turns out that having these debugfs information is really useful when trying to understand what is going wrong in a guest, or even in the host kernel... Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: wanghaibin <wanghaibin.wang@huawei.com> --- arch/arm64/kvm/rvic-cpu.c | 140 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/kvm/rvic-cpu.c b/arch/arm64/kvm/rvic-cpu.c index f951ab381fbd..6386dd3a4bbb 100644 --- a/arch/arm64/kvm/rvic-cpu.c +++ b/arch/arm64/kvm/rvic-cpu.c @@ -6,6 +6,7 @@ * Author: Marc Zyngier <maz@kernel.org> */ +#include <linux/debugfs.h> #include <linux/kernel.h> #include <linux/kvm_host.h> #include <linux/list.h> @@ -709,6 +710,8 @@ static int rvic_inject_userspace_irq(struct kvm *kvm, unsigned int type, } } +static void rvic_create_debugfs(struct kvm_vcpu *vcpu); + static int rvic_vcpu_init(struct kvm_vcpu *vcpu) { struct rvic_vm_data *data = vcpu->kvm->arch.irqchip_data; @@ -745,6 +748,8 @@ static int rvic_vcpu_init(struct kvm_vcpu *vcpu) irq->line_level = false; } + rvic_create_debugfs(vcpu); + return 0; } @@ -916,6 +921,8 @@ static void rvic_device_destroy(struct kvm_device *dev) kfree(dev); } +static void rvid_create_debugfs(struct kvm *kvm); + static int rvic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) { struct rvic_vm_data *data; @@ -973,6 +980,7 @@ static int rvic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr) } dev->kvm->arch.irqchip_data = data; + rvid_create_debugfs(dev->kvm); ret = 0; break; @@ -1075,3 +1083,135 @@ int kvm_register_rvic_device(void) { return kvm_register_device_ops(&rvic_dev_ops, KVM_DEV_TYPE_ARM_RVIC); } + +static void rvic_irq_debug_show_one(struct seq_file *s, struct rvic_irq *irq) +{ + unsigned long flags; + + spin_lock_irqsave(&irq->lock, flags); + + seq_printf(s, "%d: [%d] %c %c %ps %c %c\n", + irq->intid, irq->host_irq, + irq->pending ? 'P' : 'p', + irq->masked ? 'M' : 'm', + irq->get_line_level, + irq->get_line_level ? 'x' : (irq->line_level ? 'H' : 'L'), + rvic_irq_queued(irq) ? 'Q' : 'i'); + + spin_unlock_irqrestore(&irq->lock, flags); +} + +static int rvic_irq_debug_show(struct seq_file *s, void *p) +{ + rvic_irq_debug_show_one(s, s->private); + return 0; +} + +static int rvic_irq_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, rvic_irq_debug_show, inode->i_private); +} + +static const struct file_operations rvic_irq_debug_fops = { + .open = rvic_irq_debug_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int rvic_debug_show(struct seq_file *s, void *p) +{ + struct kvm_vcpu *vcpu = s->private; + struct rvic *rvic = kvm_vcpu_to_rvic(vcpu); + struct rvic_irq *irq; + unsigned long flags; + + spin_lock_irqsave(&rvic->lock, flags); + + seq_printf(s, "%s\n", rvic->enabled ? "Enabled" : "Disabled"); + seq_printf(s, "%d Trusted\n", rvic->nr_trusted); + seq_printf(s, "%d Total\n", rvic->nr_total); + list_for_each_entry(irq, &rvic->delivery, delivery_entry) + rvic_irq_debug_show_one(s, irq); + + spin_unlock_irqrestore(&rvic->lock, flags); + + return 0; +} + +static int rvic_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, rvic_debug_show, inode->i_private); +} + +static const struct file_operations rvic_debug_fops = { + .open = rvic_debug_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void rvic_create_debugfs(struct kvm_vcpu *vcpu) +{ + struct rvic *rvic = kvm_vcpu_to_rvic(vcpu); + struct dentry *rvic_root; + char dname[128]; + int i; + + snprintf(dname, sizeof(dname), "rvic-%d", vcpu->vcpu_id); + rvic_root = debugfs_create_dir(dname, vcpu->kvm->debugfs_dentry); + if (!rvic_root) + return; + + debugfs_create_file("state", 0444, rvic_root, vcpu, &rvic_debug_fops); + for (i = 0; i < rvic->nr_total; i++) { + snprintf(dname, sizeof(dname), "%d", i); + debugfs_create_file(dname, 0444, rvic_root, + rvic_get_irq(rvic, i), + &rvic_irq_debug_fops); + } +} + +static int rvid_debug_show(struct seq_file *s, void *p) +{ + struct kvm *kvm = s->private; + struct rvic_vm_data *data = kvm->arch.irqchip_data; + unsigned long flags; + int i; + + spin_lock_irqsave(&data->lock, flags); + + seq_printf(s, "%d Trusted\n", data->nr_trusted); + seq_printf(s, "%d Total\n", data->nr_total); + + for (i = 0; i < rvic_nr_untrusted(data); i++) { + if (data->rvid_map[i].intid < data->nr_trusted) + continue; + + seq_printf(s, "%4u: vcpu-%u %u\n", + i, data->rvid_map[i].target_vcpu, + data->rvid_map[i].intid); + } + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int rvid_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, rvid_debug_show, inode->i_private); +} + +static const struct file_operations rvid_debug_fops = { + .open = rvid_debug_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static void rvid_create_debugfs(struct kvm *kvm) +{ + debugfs_create_file("rvid", 0444, kvm->debugfs_dentry, + kvm, &rvid_debug_fops); +} -- 2.33.0