driver inclusion category: feature -------------------------------- Implement the .ndo_open function to Calculate the Rx buffer size， allocate the channels and rings. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> --- .../ethernet/motorcomm/yt6801/yt6801_desc.c | 273 ++++++++++++++++++ .../ethernet/motorcomm/yt6801/yt6801_net.c | 99 +++++++ 2 files changed, 372 insertions(+) diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.c index 476cf6633..2edf53d9b 100644 --- a/drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.c +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.c @@ -47,3 +47,276 @@ void fxgmac_desc_data_unmap(struct fxgmac_pdata *pdata, desc_data->mapped_as_page = 0; } + +static void fxgmac_ring_free(struct fxgmac_pdata *pdata, + struct fxgmac_ring *ring) +{ + if (!ring) + return; + + if (ring->desc_data_head) { + for (u32 i = 0; i < ring->dma_desc_count; i++) + fxgmac_desc_data_unmap(pdata, + FXGMAC_GET_DESC_DATA(ring, i)); + + kfree(ring->desc_data_head); + ring->desc_data_head = NULL; + } + + if (ring->rx_hdr_pa.pages) { + dma_unmap_page(pdata->dev, ring->rx_hdr_pa.pages_dma, + ring->rx_hdr_pa.pages_len, DMA_FROM_DEVICE); + put_page(ring->rx_hdr_pa.pages); + + ring->rx_hdr_pa.pages = NULL; + ring->rx_hdr_pa.pages_len = 0; + ring->rx_hdr_pa.pages_offset = 0; + ring->rx_hdr_pa.pages_dma = 0; + } + + if (ring->rx_buf_pa.pages) { + dma_unmap_page(pdata->dev, ring->rx_buf_pa.pages_dma, + ring->rx_buf_pa.pages_len, DMA_FROM_DEVICE); + put_page(ring->rx_buf_pa.pages); + + ring->rx_buf_pa.pages = NULL; + ring->rx_buf_pa.pages_len = 0; + ring->rx_buf_pa.pages_offset = 0; + ring->rx_buf_pa.pages_dma = 0; + } + if (ring->dma_desc_head) { + dma_free_coherent(pdata->dev, (sizeof(struct fxgmac_dma_desc) * + ring->dma_desc_count), ring->dma_desc_head, + ring->dma_desc_head_addr); + ring->dma_desc_head = NULL; + } +} + +static int fxgmac_ring_init(struct fxgmac_pdata *pdata, + struct fxgmac_ring *ring, + unsigned int dma_desc_count) +{ + /* Descriptors */ + ring->dma_desc_count = dma_desc_count; + ring->dma_desc_head = + dma_alloc_coherent(pdata->dev, (sizeof(struct fxgmac_dma_desc) * + dma_desc_count), + &ring->dma_desc_head_addr, GFP_KERNEL); + if (!ring->dma_desc_head) + return -ENOMEM; + + /* Array of descriptor data */ + ring->desc_data_head = kcalloc(dma_desc_count, + sizeof(struct fxgmac_desc_data), + GFP_KERNEL); + if (!ring->desc_data_head) + return -ENOMEM; + + yt_dbg(pdata, + "dma_desc_head=%p, dma_desc_head_addr=%pad, desc_data_head=%p\n", + ring->dma_desc_head, &ring->dma_desc_head_addr, + ring->desc_data_head); + return 0; +} + +static void fxgmac_rings_free(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + + fxgmac_ring_free(pdata, channel->tx_ring); + + for (u32 i = 0; i < pdata->channel_count; i++, channel++) + fxgmac_ring_free(pdata, channel->rx_ring); +} + +static int fxgmac_rings_alloc(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + int ret; + + yt_dbg(pdata, "%s - Tx ring:\n", channel->name); + ret = fxgmac_ring_init(pdata, channel->tx_ring, + pdata->tx_desc_count); + if (ret < 0) { + yt_err(pdata, "error initializing Tx ring"); + goto err_init_ring; + } + if (netif_msg_drv(pdata)) + yt_dbg(pdata, + "%s, ch=%u,tx_desc_cnt=%u\n", + __func__, 0, pdata->tx_desc_count); + + for (u32 i = 0; i < pdata->channel_count; i++, channel++) { + yt_dbg(pdata, "%s - Rx ring:\n", channel->name); + ret = fxgmac_ring_init(pdata, channel->rx_ring, + pdata->rx_desc_count); + if (ret < 0) { + yt_err(pdata, "error initializing Rx ring\n"); + goto err_init_ring; + } + if (netif_msg_drv(pdata)) + yt_dbg(pdata, + "%s, ch=%u,rx_desc_cnt=%u\n", + __func__, i, + pdata->rx_desc_count); + } + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "%s ok\n", __func__); + + return 0; + +err_init_ring: + fxgmac_rings_free(pdata); + return ret; +} + +static void fxgmac_channels_free(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "free_channels,tx_ring=%p\n", channel->tx_ring); + + kfree(channel->tx_ring); + channel->tx_ring = NULL; + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "free_channels,rx_ring=%p\n", channel->rx_ring); + + kfree(channel->rx_ring); + channel->rx_ring = NULL; + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "free_channels,channel=%p\n", channel); + + kfree(channel); + pdata->channel_head = NULL; +} + +#ifdef CONFIG_PCI_MSI +static void fxgmac_set_msix_tx_irq(struct fxgmac_pdata *pdata, + struct fxgmac_channel *channel, u32 i) +{ + if (!FXGMAC_IS_CHANNEL_WITH_TX_IRQ(i)) + return; + + pdata->channel_irq[FXGMAC_MAX_DMA_RX_CHANNELS] = + pdata->msix_entries[FXGMAC_MAX_DMA_RX_CHANNELS].vector; + channel->dma_irq_tx = pdata->channel_irq[FXGMAC_MAX_DMA_RX_CHANNELS]; + + yt_dbg(pdata, "%s, for MSIx, channel %d dma_irq_tx=%u\n", __func__, i, + channel->dma_irq_tx); +} +#endif + +static int fxgmac_channels_alloc(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel_head, *channel; + struct fxgmac_ring *tx_ring, *rx_ring; + int ret = -ENOMEM; + + channel_head = kcalloc(pdata->channel_count, + sizeof(struct fxgmac_channel), GFP_KERNEL); + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "alloc_channels,channel_head=%p,size=%d*%ld\n", + channel_head, pdata->channel_count, + sizeof(struct fxgmac_channel)); + + if (!channel_head) + return ret; + + tx_ring = kcalloc(FXGMAC_TX_1_RING, sizeof(struct fxgmac_ring), + GFP_KERNEL); + if (!tx_ring) + goto err_tx_ring; + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "alloc_channels,tx_ring=%p,size=%d*%ld\n", + tx_ring, FXGMAC_TX_1_RING, + sizeof(struct fxgmac_ring)); + + rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct fxgmac_ring), + GFP_KERNEL); + if (!rx_ring) + goto err_rx_ring; + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "alloc_channels,rx_ring=%p,size=%d*%ld\n", + rx_ring, pdata->rx_ring_count, + sizeof(struct fxgmac_ring)); + + channel = channel_head; + for (u32 i = 0; i < pdata->channel_count; i++, channel++) { + snprintf(channel->name, sizeof(channel->name), "channel-%u", i); + channel->pdata = pdata; + channel->queue_index = i; + channel->dma_reg_offset = DMA_CH_BASE + (DMA_CH_INC * i); + + if (pdata->per_channel_irq) { + pdata->channel_irq[i] = pdata->msix_entries[i].vector; +#ifdef CONFIG_PCI_MSI + fxgmac_set_msix_tx_irq(pdata, channel, i); +#endif + + /* Get the per DMA rx interrupt */ + ret = pdata->channel_irq[i]; + if (ret < 0) { + yt_err(pdata, "get_irq %u err\n", i + 1); + goto err_irq; + } + + channel->dma_irq_rx = ret; + yt_dbg(pdata, + "%s, for MSIx, channel %d dma_irq_rx=%u\n", + __func__, i, channel->dma_irq_rx); + } + + if (i < FXGMAC_TX_1_RING) + channel->tx_ring = tx_ring++; + + if (i < pdata->rx_ring_count) + channel->rx_ring = rx_ring++; + } + + pdata->channel_head = channel_head; + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "%s ok\n", __func__); + return 0; + +err_irq: + kfree(rx_ring); + +err_rx_ring: + kfree(tx_ring); + +err_tx_ring: + kfree(channel_head); + + yt_err(pdata, "%s err:%d\n", __func__, ret); + return ret; +} + +void fxgmac_channels_rings_free(struct fxgmac_pdata *pdata) +{ + fxgmac_rings_free(pdata); + fxgmac_channels_free(pdata); +} + +int fxgmac_channels_rings_alloc(struct fxgmac_pdata *pdata) +{ + int ret; + + ret = fxgmac_channels_alloc(pdata); + if (ret < 0) + goto err_alloc; + + ret = fxgmac_rings_alloc(pdata); + if (ret < 0) + goto err_alloc; + + return 0; + +err_alloc: + fxgmac_channels_rings_free(pdata); + return ret; +} diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c index 0cb2808b7..39b91cc26 100644 --- a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c @@ -11,6 +11,26 @@ #include "yt6801_desc.h" #include "yt6801_net.h" +static int fxgmac_calc_rx_buf_size(struct fxgmac_pdata *pdata, unsigned int mtu) +{ + u32 rx_buf_size, max_mtu; + + max_mtu = FXGMAC_JUMBO_PACKET_MTU - ETH_HLEN; + if (mtu > max_mtu) { + yt_err(pdata, "MTU exceeds maximum supported value\n"); + return -EINVAL; + } + + rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; + rx_buf_size = + clamp_val(rx_buf_size, FXGMAC_RX_MIN_BUF_SIZE, PAGE_SIZE * 4); + + rx_buf_size = (rx_buf_size + FXGMAC_RX_BUF_ALIGN - 1) & + ~(FXGMAC_RX_BUF_ALIGN - 1); + + return rx_buf_size; +} + #define FXGMAC_NAPI_ENABLE 0x1 #define FXGMAC_NAPI_DISABLE 0x0 static void fxgmac_napi_disable(struct fxgmac_pdata *pdata) @@ -197,6 +217,36 @@ void fxgmac_stop(struct fxgmac_pdata *pdata) netdev_tx_reset_queue(txq); } +void fxgmac_restart(struct fxgmac_pdata *pdata) +{ + int ret; + + /* If not running, "restart" will happen on open */ + if (!netif_running(pdata->netdev) && + pdata->dev_state != FXGMAC_DEV_START) + return; + + mutex_lock(&pdata->mutex); + fxgmac_stop(pdata); + fxgmac_free_tx_data(pdata); + fxgmac_free_rx_data(pdata); + ret = fxgmac_start(pdata); + if (ret < 0) + yt_err(pdata, "%s err.\n", __func__); + + mutex_unlock(&pdata->mutex); +} + +static void fxgmac_restart_work(struct work_struct *work) +{ + struct fxgmac_pdata *pdata = + container_of(work, struct fxgmac_pdata, restart_work); + + rtnl_lock(); + fxgmac_restart(pdata); + rtnl_unlock(); +} + int fxgmac_net_powerdown(struct fxgmac_pdata *pdata, bool wake_en) { struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; @@ -250,6 +300,46 @@ int fxgmac_net_powerdown(struct fxgmac_pdata *pdata, bool wake_en) return 0; } +static int fxgmac_open(struct net_device *netdev) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + int ret; + + mutex_lock(&pdata->mutex); + pdata->dev_state = FXGMAC_DEV_OPEN; + + /* Calculate the Rx buffer size before allocating rings */ + ret = fxgmac_calc_rx_buf_size(pdata, netdev->mtu); + if (ret < 0) + goto unlock; + pdata->rx_buf_size = ret; + + /* Allocate the channels and rings */ + ret = fxgmac_channels_rings_alloc(pdata); + if (ret < 0) + goto unlock; + + INIT_WORK(&pdata->restart_work, fxgmac_restart_work); + + ret = fxgmac_start(pdata); + if (ret < 0) + goto err_channels_and_rings; + + mutex_unlock(&pdata->mutex); + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "%s ok\n", __func__); + + return 0; + +err_channels_and_rings: + fxgmac_channels_rings_free(pdata); + yt_dbg(pdata, "%s, channel alloc err\n", __func__); +unlock: + mutex_unlock(&pdata->mutex); + return ret; +} + #ifdef CONFIG_PCI_MSI static void fxgmac_init_interrupt_scheme(struct fxgmac_pdata *pdata) { @@ -442,3 +532,12 @@ int fxgmac_drv_probe(struct device *dev, struct fxgmac_resources *res) free_netdev(netdev); return ret; } + +static const struct net_device_ops fxgmac_netdev_ops = { + .ndo_open = fxgmac_open, +}; + +const struct net_device_ops *fxgmac_get_netdev_ops(void) +{ + return &fxgmac_netdev_ops; +} -- 2.34.1

driver inclusion category: feature -------------------------------- Implement the fxgmac_read_mac_addr function to read mac address form efuse. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> --- .../ethernet/motorcomm/yt6801/yt6801_net.c | 147 ++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c index aa51ecdd7..c3baa06b0 100644 --- a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c @@ -796,6 +796,153 @@ static int fxgmac_open(struct net_device *netdev) return ret; } +#define EFUSE_FISRT_UPDATE_ADDR 255 +#define EFUSE_SECOND_UPDATE_ADDR 209 +#define EFUSE_MAX_ENTRY 39 +#define EFUSE_PATCH_ADDR_START 0 +#define EFUSE_PATCH_DATA_START 2 +#define EFUSE_PATCH_SIZE 6 +#define EFUSE_REGION_A_B_LENGTH 18 + +static bool fxgmac_efuse_read_data(struct fxgmac_pdata *pdata, u32 offset, + u8 *value) +{ + bool ret = false; + u32 wait = 1000; + u32 val = 0; + + fxgmac_set_bits(&val, EFUSE_OP_ADDR_POS, EFUSE_OP_ADDR_LEN, offset); + fxgmac_set_bits(&val, EFUSE_OP_START_POS, EFUSE_OP_START_LEN, 1); + fxgmac_set_bits(&val, EFUSE_OP_MODE_POS, EFUSE_OP_MODE_LEN, + EFUSE_OP_MODE_ROW_READ); + wr32_mem(pdata, val, EFUSE_OP_CTRL_0); + + while (wait--) { + fsleep(20); + val = rd32_mem(pdata, EFUSE_OP_CTRL_1); + if (FXGMAC_GET_BITS(val, EFUSE_OP_DONE_POS, + EFUSE_OP_DONE_LEN)) { + ret = true; + break; + } + } + + if (!ret) { + yt_err(pdata, "Fail to reading efuse Byte%d\n", offset); + return ret; + } + + if (value) + *value = FXGMAC_GET_BITS(val, EFUSE_OP_RD_DATA_POS, + EFUSE_OP_RD_DATA_LEN) & 0xff; + + return ret; +} + +static bool fxgmac_efuse_read_index_patch(struct fxgmac_pdata *pdata, u8 index, + u32 *offset, u32 *value) +{ + u8 tmp[EFUSE_PATCH_SIZE - EFUSE_PATCH_DATA_START]; + u32 addr, i; + bool ret; + + if (index >= EFUSE_MAX_ENTRY) { + yt_err(pdata, "Reading efuse out of range, index %d\n", index); + return false; + } + + for (i = EFUSE_PATCH_ADDR_START; i < EFUSE_PATCH_DATA_START; i++) { + addr = EFUSE_REGION_A_B_LENGTH + index * EFUSE_PATCH_SIZE + i; + ret = fxgmac_efuse_read_data(pdata, addr, + tmp + i - EFUSE_PATCH_ADDR_START); + if (!ret) { + yt_err(pdata, "Fail to reading efuse Byte%d\n", addr); + return ret; + } + } + if (offset) { + /* tmp[0] is low 8bit date, tmp[1] is high 8bit date */ + *offset = tmp[0] | (tmp[1] << 8); + } + + for (i = EFUSE_PATCH_DATA_START; i < EFUSE_PATCH_SIZE; i++) { + addr = EFUSE_REGION_A_B_LENGTH + index * EFUSE_PATCH_SIZE + i; + ret = fxgmac_efuse_read_data(pdata, addr, + tmp + i - EFUSE_PATCH_DATA_START); + if (!ret) { + yt_err(pdata, "Fail to reading efuse Byte%d\n", addr); + return ret; + } + } + if (value) { + /* tmp[0] is low 8bit date, tmp[1] is low 8bit date + * ... tmp[3] is highest 8bit date + */ + *value = tmp[0] | (tmp[1] << 8) | (tmp[2] << 16) | + (tmp[3] << 24); + } + + return ret; +} + +static bool fxgmac_efuse_read_mac_subsys(struct fxgmac_pdata *pdata, + u8 *mac_addr, u32 *subsys, u32 *revid) +{ + u32 machr = 0, maclr = 0; + u32 offset = 0, val = 0; + bool ret = true; + u8 index; + + for (index = 0;; index++) { + if (!fxgmac_efuse_read_index_patch(pdata, index, &offset, &val)) + return false; + + if (offset == 0x00) + break; /* Reach the blank. */ + + if (offset == MACA0LR_FROM_EFUSE) + maclr = val; + + if (offset == MACA0HR_FROM_EFUSE) + machr = val; + + if (offset == PCI_REVISION_ID && revid) + *revid = val; + + if (offset == PCI_SUBSYSTEM_VENDOR_ID && subsys) + *subsys = val; + } + + if (mac_addr) { + mac_addr[5] = (u8)(maclr & 0xFF); + mac_addr[4] = (u8)((maclr >> 8) & 0xFF); + mac_addr[3] = (u8)((maclr >> 16) & 0xFF); + mac_addr[2] = (u8)((maclr >> 24) & 0xFF); + mac_addr[1] = (u8)(machr & 0xFF); + mac_addr[0] = (u8)((machr >> 8) & 0xFF); + } + + return ret; +} + +static int fxgmac_read_mac_addr(struct fxgmac_pdata *pdata) +{ + u8 default_addr[ETH_ALEN] = { 0, 0x55, 0x7b, 0xb5, 0x7d, 0xf7 }; + struct net_device *netdev = pdata->netdev; + int ret; + + /* If efuse have mac addr, use it. if not, use static mac address. */ + ret = fxgmac_efuse_read_mac_subsys(pdata, pdata->mac_addr, NULL, NULL); + if (!ret) + return -1; + + if (is_zero_ether_addr(pdata->mac_addr)) + /* Use a static mac address for test */ + memcpy(pdata->mac_addr, default_addr, netdev->addr_len); + + return 0; +} + #define FXGMAC_SYSCLOCK 125000000 /* System clock is 125 MHz */ static void fxgmac_default_config(struct fxgmac_pdata *pdata) -- 2.34.1

driver inclusion category: feature -------------------------------- Implement following callback function .get_drvinfo .get_link .get_msglevel .set_msglevel .get_channels .get_coalesce .set_coalesce .supported_coalesce_params .get_strings .get_sset_count .get_ethtool_stats .get_regs_len .get_regs .get_ringparam .set_ringparam .get_rxfh_indir_size .get_rxfh_key_size .get_rxfh .set_rxfh .nway_reset .reset .get_link_ksettings .set_link_ksettings .get_pauseparam .set_pauseparam Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> --- .../motorcomm/yt6801/yt6801_ethtool.c | 669 ++++++++++++++++++ 1 file changed, 669 insertions(+) create mode 100644 drivers/net/ethernet/motorcomm/yt6801/yt6801_ethtool.c diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_ethtool.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_ethtool.c new file mode 100644 index 000000000..12150584f --- /dev/null +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_ethtool.c @@ -0,0 +1,669 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2022 - 2024 Motorcomm Electronic Technology Co.,Ltd. */ + +#include <linux/netdevice.h> +#include <linux/ethtool.h> +#include <linux/kernel.h> + +#include "yt6801_desc.h" +#include "yt6801_net.h" + +struct fxgmac_stats_desc { + char stat_string[ETH_GSTRING_LEN]; + int stat_offset; +}; + +#define FXGMAC_STAT(str, var) \ + { \ + str, offsetof(struct fxgmac_pdata, stats.var), \ + } + +static const struct fxgmac_stats_desc fxgmac_gstring_stats[] = { + /* MMC TX counters */ + FXGMAC_STAT("tx_bytes", txoctetcount_gb), + FXGMAC_STAT("tx_bytes_good", txoctetcount_g), + FXGMAC_STAT("tx_packets", txframecount_gb), + FXGMAC_STAT("tx_packets_good", txframecount_g), + FXGMAC_STAT("tx_unicast_packets", txunicastframes_gb), + FXGMAC_STAT("tx_broadcast_packets", txbroadcastframes_gb), + FXGMAC_STAT("tx_broadcast_packets_good", txbroadcastframes_g), + FXGMAC_STAT("tx_multicast_packets", txmulticastframes_gb), + FXGMAC_STAT("tx_multicast_packets_good", txmulticastframes_g), + FXGMAC_STAT("tx_vlan_packets_good", txvlanframes_g), + FXGMAC_STAT("tx_64_byte_packets", tx64octets_gb), + FXGMAC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), + FXGMAC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb), + FXGMAC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb), + FXGMAC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb), + FXGMAC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb), + FXGMAC_STAT("tx_underflow_errors", txunderflowerror), + FXGMAC_STAT("tx_pause_frames", txpauseframes), + FXGMAC_STAT("tx_single_collision", txsinglecollision_g), + FXGMAC_STAT("tx_multiple_collision", txmultiplecollision_g), + FXGMAC_STAT("tx_deferred_frames", txdeferredframes), + FXGMAC_STAT("tx_late_collision_frames", txlatecollisionframes), + FXGMAC_STAT("tx_excessive_collision_frames", + txexcessivecollisionframes), + FXGMAC_STAT("tx_carrier_error_frames", txcarriererrorframes), + FXGMAC_STAT("tx_excessive_deferral_error", txexcessivedeferralerror), + FXGMAC_STAT("tx_oversize_frames_good", txoversize_g), + + /* MMC RX counters */ + FXGMAC_STAT("rx_bytes", rxoctetcount_gb), + FXGMAC_STAT("rx_bytes_good", rxoctetcount_g), + FXGMAC_STAT("rx_packets", rxframecount_gb), + FXGMAC_STAT("rx_unicast_packets_good", rxunicastframes_g), + FXGMAC_STAT("rx_broadcast_packets_good", rxbroadcastframes_g), + FXGMAC_STAT("rx_multicast_packets_good", rxmulticastframes_g), + FXGMAC_STAT("rx_vlan_packets_mac", rxvlanframes_gb), + FXGMAC_STAT("rx_64_byte_packets", rx64octets_gb), + FXGMAC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), + FXGMAC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb), + FXGMAC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb), + FXGMAC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb), + FXGMAC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb), + FXGMAC_STAT("rx_undersize_packets_good", rxundersize_g), + FXGMAC_STAT("rx_oversize_packets_good", rxoversize_g), + FXGMAC_STAT("rx_crc_errors", rxcrcerror), + FXGMAC_STAT("rx_align_error", rxalignerror), + FXGMAC_STAT("rx_crc_errors_small_packets", rxrunterror), + FXGMAC_STAT("rx_crc_errors_giant_packets", rxjabbererror), + FXGMAC_STAT("rx_length_errors", rxlengtherror), + FXGMAC_STAT("rx_out_of_range_errors", rxoutofrangetype), + FXGMAC_STAT("rx_fifo_overflow_errors", rxfifooverflow), + FXGMAC_STAT("rx_watchdog_errors", rxwatchdogerror), + FXGMAC_STAT("rx_pause_frames", rxpauseframes), + FXGMAC_STAT("rx_receive_error_frames", rxreceiveerrorframe), + FXGMAC_STAT("rx_control_frames_good", rxcontrolframe_g), + + /* Extra counters */ + FXGMAC_STAT("tx_tso_packets", tx_tso_packets), + FXGMAC_STAT("rx_split_header_packets", rx_split_header_packets), + FXGMAC_STAT("tx_process_stopped", tx_process_stopped), + FXGMAC_STAT("rx_process_stopped", rx_process_stopped), + FXGMAC_STAT("tx_buffer_unavailable", tx_buffer_unavailable), + FXGMAC_STAT("rx_buffer_unavailable", rx_buffer_unavailable), + FXGMAC_STAT("fatal_bus_error", fatal_bus_error), + FXGMAC_STAT("tx_vlan_packets_net", tx_vlan_packets), + FXGMAC_STAT("rx_vlan_packets_net", rx_vlan_packets), + FXGMAC_STAT("napi_poll_isr", napi_poll_isr), + FXGMAC_STAT("napi_poll_txtimer", napi_poll_txtimer), + FXGMAC_STAT("alive_cnt_txtimer", cnt_alive_txtimer), + FXGMAC_STAT("ephy_poll_timer", ephy_poll_timer_cnt), + FXGMAC_STAT("mgmt_int_isr", mgmt_int_isr), +}; + +#define FXGMAC_STATS_COUNT ARRAY_SIZE(fxgmac_gstring_stats) + +static void fxgmac_ethtool_get_drvinfo(struct net_device *netdev, + struct ethtool_drvinfo *drvinfo) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + u32 ver = pdata->hw_feat.version; + u32 sver, devid, userver; + + strscpy(drvinfo->version, pdata->drv_ver, sizeof(drvinfo->version)); + + /* S|SVER: MAC Version + * D|DEVID: Indicates the Device family + * U|USERVER: User-defined Version + */ + sver = FXGMAC_GET_BITS(ver, MAC_VR_SVER_POS, MAC_VR_SVER_LEN); + devid = FXGMAC_GET_BITS(ver, MAC_VR_DEVID_POS, MAC_VR_DEVID_LEN); + userver = FXGMAC_GET_BITS(ver, MAC_VR_USERVER_POS, MAC_VR_USERVER_LEN); + + snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), + "S.D.U: %x.%x.%x", sver, devid, userver); +} + +static u32 fxgmac_ethtool_get_msglevel(struct net_device *netdev) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + + return pdata->msg_enable; +} + +static void fxgmac_ethtool_set_msglevel(struct net_device *netdev, u32 msglevel) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + + yt_dbg(pdata, "set msglvl from %08x to %08x\n", pdata->msg_enable, + msglevel); + pdata->msg_enable = msglevel; +} + +static void fxgmac_ethtool_get_channels(struct net_device *netdev, + struct ethtool_channels *channel) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + + /* report maximum channels */ + channel->max_rx = FXGMAC_MAX_DMA_RX_CHANNELS; + channel->max_tx = FXGMAC_MAX_DMA_TX_CHANNELS; + channel->max_other = 0; + channel->max_combined = + channel->max_rx + channel->max_tx + channel->max_other; + + yt_dbg(pdata, "channels max rx:%d, tx:%d, other:%d, combined:%d\n", + channel->max_rx, channel->max_tx, channel->max_other, + channel->max_combined); + + channel->rx_count = pdata->rx_q_count; + channel->tx_count = FXGMAC_TX_1_Q; + channel->other_count = 0; + /* record RSS queues */ + channel->combined_count = + channel->rx_count + channel->tx_count + channel->other_count; + + yt_dbg(pdata, "channels count rx:%d, tx:%d, other:%d, combined:%d\n", + channel->rx_count, channel->tx_count, channel->other_count, + channel->combined_count); +} + +static int +fxgmac_ethtool_get_coalesce(struct net_device *netdev, + struct ethtool_coalesce *ec, + struct kernel_ethtool_coalesce *kernel_coal, + struct netlink_ext_ack *extack) + +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + + memset(ec, 0, sizeof(struct ethtool_coalesce)); + ec->rx_coalesce_usecs = pdata->rx_usecs; + ec->tx_coalesce_usecs = pdata->tx_usecs; + + return 0; +} + +#define FXGMAC_MAX_DMA_RIWT 0xff +#define FXGMAC_MIN_DMA_RIWT 0x01 + +static int +fxgmac_ethtool_set_coalesce(struct net_device *netdev, + struct ethtool_coalesce *ec, + struct kernel_ethtool_coalesce *kernel_coal, + struct netlink_ext_ack *extack) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + unsigned int rx_frames, rx_riwt, rx_usecs; + unsigned int tx_frames; + + /* Check for not supported parameters */ + if (ec->rx_coalesce_usecs_irq || ec->rx_max_coalesced_frames_irq || + ec->tx_coalesce_usecs_high || ec->tx_max_coalesced_frames_irq || + ec->tx_coalesce_usecs_irq || ec->stats_block_coalesce_usecs || + ec->pkt_rate_low || ec->use_adaptive_rx_coalesce || + ec->use_adaptive_tx_coalesce || ec->rx_max_coalesced_frames_low || + ec->rx_coalesce_usecs_low || ec->tx_coalesce_usecs_low || + ec->tx_max_coalesced_frames_low || ec->pkt_rate_high || + ec->rx_coalesce_usecs_high || ec->rx_max_coalesced_frames_high || + ec->tx_max_coalesced_frames_high || ec->rate_sample_interval) + return -EOPNOTSUPP; + + rx_usecs = ec->rx_coalesce_usecs; + rx_riwt = hw_ops->usec_to_riwt(pdata, rx_usecs); + rx_frames = ec->rx_max_coalesced_frames; + tx_frames = ec->tx_max_coalesced_frames; + + if (rx_riwt > FXGMAC_MAX_DMA_RIWT || rx_riwt < FXGMAC_MIN_DMA_RIWT || + rx_frames > pdata->rx_desc_count) + return -EINVAL; + + if (tx_frames > pdata->tx_desc_count) + return -EINVAL; + + pdata->rx_usecs = rx_usecs; + pdata->rx_frames = rx_frames; + pdata->rx_riwt = rx_riwt; + hw_ops->config_rx_coalesce(pdata); + + pdata->tx_frames = tx_frames; + pdata->tx_usecs = ec->tx_coalesce_usecs; + hw_ops->set_interrupt_moderation(pdata); + + return 0; +} + +static u32 fxgmac_get_rxfh_key_size(struct net_device *netdev) +{ + return FXGMAC_RSS_HASH_KEY_SIZE; +} + +static u32 fxgmac_rss_indir_size(struct net_device *netdev) +{ + return FXGMAC_RSS_MAX_TABLE_SIZE; +} + +static int fxgmac_get_rss_hash_opts(struct fxgmac_pdata *pdata, + struct ethtool_rxnfc *cmd) +{ + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + u32 reg_opt; + + cmd->data = 0; + reg_opt = hw_ops->get_rss_options(pdata); + yt_dbg(pdata, "%s, hw=%02x, %02x\n", __func__, reg_opt, + pdata->rss_options); + + if (reg_opt != pdata->rss_options) + yt_dbg(pdata, "warning, options are not consistent\n"); + + /* Report default options for RSS */ + switch (cmd->flow_type) { + case TCP_V4_FLOW: + case UDP_V4_FLOW: + if ((cmd->flow_type == TCP_V4_FLOW && + (pdata->rss_options & FXGMAC_RSS_TCP4TE)) || + (cmd->flow_type == UDP_V4_FLOW && + (pdata->rss_options & FXGMAC_RSS_UDP4TE))) { + cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; + } + fallthrough; + case SCTP_V4_FLOW: + case AH_ESP_V4_FLOW: + case AH_V4_FLOW: + case ESP_V4_FLOW: + case IPV4_FLOW: + if ((cmd->flow_type == TCP_V4_FLOW && + (pdata->rss_options & FXGMAC_RSS_TCP4TE)) || + (cmd->flow_type == UDP_V4_FLOW && + (pdata->rss_options & FXGMAC_RSS_UDP4TE)) || + (pdata->rss_options & BIT(FXGMAC_RSS_IP4TE))) { + cmd->data |= RXH_IP_SRC | RXH_IP_DST; + } + break; + case TCP_V6_FLOW: + case UDP_V6_FLOW: + if ((cmd->flow_type == TCP_V6_FLOW && + (pdata->rss_options & FXGMAC_RSS_TCP6TE)) || + (cmd->flow_type == UDP_V6_FLOW && + (pdata->rss_options & FXGMAC_RSS_UDP6TE))) { + cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; + } + fallthrough; + case SCTP_V6_FLOW: + case AH_ESP_V6_FLOW: + case AH_V6_FLOW: + case ESP_V6_FLOW: + case IPV6_FLOW: + if ((cmd->flow_type == TCP_V6_FLOW && + (pdata->rss_options & FXGMAC_RSS_TCP6TE)) || + (cmd->flow_type == UDP_V6_FLOW && + (pdata->rss_options & FXGMAC_RSS_UDP6TE)) || + (pdata->rss_options & FXGMAC_RSS_IP6TE)) { + cmd->data |= RXH_IP_SRC | RXH_IP_DST; + } + break; + default: + return -EINVAL; + } + + return 0; +} + +static int fxgmac_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, + u32 *rule_locs) +{ + struct fxgmac_pdata *pdata = netdev_priv(dev); + int ret = 0; + + switch (cmd->cmd) { + case ETHTOOL_GRXRINGS: + cmd->data = pdata->rx_q_count; + yt_dbg(pdata, "%s, rx ring cnt\n", __func__); + break; + case ETHTOOL_GRXCLSRLCNT: + cmd->rule_cnt = 0; + yt_dbg(pdata, "%s, classify rule cnt\n", __func__); + break; + case ETHTOOL_GRXCLSRULE: + yt_dbg(pdata, "%s, classify rules\n", __func__); + break; + case ETHTOOL_GRXCLSRLALL: + cmd->rule_cnt = 0; + yt_dbg(pdata, "%s, classify both cnt and rules\n", __func__); + break; + case ETHTOOL_GRXFH: + ret = fxgmac_get_rss_hash_opts(pdata, cmd); + yt_dbg(pdata, "%s, hash options\n", __func__); + break; + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} + +#define UDP_RSS_FLAGS (FXGMAC_RSS_UDP4TE | FXGMAC_RSS_UDP6TE) + +static int fxgmac_set_rss_hash_opt(struct fxgmac_pdata *pdata, + struct ethtool_rxnfc *nfc) +{ + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + __u64 data = nfc->data; + u32 rssopt = 0; + + yt_dbg(pdata, "%s nfc_data=%llx,cur opt=%x\n", __func__, data, + pdata->rss_options); + + /* For RSS, it does not support anything other than hashing + * to queues on src,dst IPs and L4 ports + */ + if (data & ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3)) + return -EINVAL; + + switch (nfc->flow_type) { + case TCP_V4_FLOW: + case TCP_V6_FLOW: + /* default to TCP flow and do nothting */ + if (!(data & + (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))) + return -EINVAL; + if (nfc->flow_type == TCP_V4_FLOW) + rssopt |= BIT(FXGMAC_RSS_IP4TE) | FXGMAC_RSS_TCP4TE; + if (nfc->flow_type == TCP_V6_FLOW) + rssopt |= FXGMAC_RSS_IP6TE | FXGMAC_RSS_TCP6TE; + break; + case UDP_V4_FLOW: + if (!(data & (RXH_IP_SRC | RXH_IP_DST))) + return -EINVAL; + rssopt |= BIT(FXGMAC_RSS_IP4TE); + switch (data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { + case 0: + break; + case (RXH_L4_B_0_1 | RXH_L4_B_2_3): + rssopt |= FXGMAC_RSS_UDP4TE; + break; + default: + return -EINVAL; + } + break; + case UDP_V6_FLOW: + if (!(data & (RXH_IP_SRC | RXH_IP_DST))) + return -EINVAL; + rssopt |= FXGMAC_RSS_IP6TE; + + switch (data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { + case 0: + break; + case (RXH_L4_B_0_1 | RXH_L4_B_2_3): + rssopt |= FXGMAC_RSS_UDP6TE; + break; + default: + return -EINVAL; + } + break; + case AH_ESP_V4_FLOW: + case AH_V4_FLOW: + case ESP_V4_FLOW: + case SCTP_V4_FLOW: + case AH_ESP_V6_FLOW: + case AH_V6_FLOW: + case ESP_V6_FLOW: + case SCTP_V6_FLOW: + if (!(data & + (RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))) + return -EINVAL; + break; + default: + return -EINVAL; + } + + /* if options are changed, then update to hw */ + if (rssopt != pdata->rss_options) { + if ((rssopt & UDP_RSS_FLAGS) && + !(pdata->rss_options & UDP_RSS_FLAGS)) + yt_dbg(pdata, + "enabling UDP RSS: fragmented packets may arrive out of order to the stack above."); + + yt_dbg(pdata, "rss option changed from %x to %x\n", + pdata->rss_options, rssopt); + pdata->rss_options = rssopt; + hw_ops->set_rss_options(pdata); + } + + return 0; +} + +static int fxgmac_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) +{ + struct fxgmac_pdata *pdata = netdev_priv(dev); + int ret = -EOPNOTSUPP; + + switch (cmd->cmd) { + case ETHTOOL_SRXCLSRLINS: + yt_dbg(pdata, "%s, rx cls rule insert-n\\a\n", __func__); + break; + case ETHTOOL_SRXCLSRLDEL: + yt_dbg(pdata, "%s, rx cls rule del-n\\a\n", __func__); + break; + case ETHTOOL_SRXFH: + yt_dbg(pdata, "%s, rx rss option\n", __func__); + ret = fxgmac_set_rss_hash_opt(pdata, cmd); + break; + default: + break; + } + + return ret; +} + +static void fxgmac_get_ringparam(struct net_device *netdev, + struct ethtool_ringparam *ring, + struct kernel_ethtool_ringparam *kernel_ring, + struct netlink_ext_ack *exact) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + + ring->rx_max_pending = FXGMAC_RX_DESC_CNT; + ring->tx_max_pending = FXGMAC_TX_DESC_CNT; + ring->rx_mini_max_pending = 0; + ring->rx_jumbo_max_pending = 0; + ring->rx_pending = pdata->rx_desc_count; + ring->tx_pending = pdata->tx_desc_count; + ring->rx_mini_pending = 0; + ring->rx_jumbo_pending = 0; +} + +static int fxgmac_set_ringparam(struct net_device *netdev, + struct ethtool_ringparam *ring, + struct kernel_ethtool_ringparam *kernel_ring, + struct netlink_ext_ack *exact) + +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + int ret; + + if (pdata->dev_state != FXGMAC_DEV_START) + return 0; + + mutex_lock(&pdata->mutex); + pdata->tx_desc_count = ring->tx_pending; + pdata->rx_desc_count = ring->rx_pending; + + fxgmac_stop(pdata); + fxgmac_free_tx_data(pdata); + fxgmac_free_rx_data(pdata); + ret = fxgmac_channels_rings_alloc(pdata); + if (ret < 0) + goto unlock; + + ret = fxgmac_start(pdata); + +unlock: + mutex_unlock(&pdata->mutex); + return ret; +} + +static int fxgmac_get_regs_len(struct net_device __always_unused *netdev) +{ + return FXGMAC_PHY_REG_CNT * sizeof(u32); +} + +static void fxgmac_get_regs(struct net_device *netdev, + struct ethtool_regs *regs, void *p) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + u32 *regs_buff = p; + + memset(p, 0, FXGMAC_PHY_REG_CNT * sizeof(u32)); + for (u32 i = MII_BMCR; i < FXGMAC_PHY_REG_CNT; i++) + regs_buff[i] = phy_read(pdata->phydev, i); + + regs->version = regs_buff[MII_PHYSID1] << 16 | regs_buff[MII_PHYSID2]; +} + +static void fxgmac_get_pauseparam(struct net_device *dev, + struct ethtool_pauseparam *data) +{ + struct fxgmac_pdata *yt = netdev_priv(dev); + bool tx_pause, rx_pause; + + phy_get_pause(yt->phydev, &tx_pause, &rx_pause); + + data->autoneg = yt->phydev->autoneg; + data->tx_pause = tx_pause ? 1 : 0; + data->rx_pause = rx_pause ? 1 : 0; + + yt_dbg(yt, "%s, rx=%d, tx=%d\n", __func__, data->rx_pause, + data->tx_pause); +} + +static int fxgmac_set_pauseparam(struct net_device *dev, + struct ethtool_pauseparam *data) +{ + struct fxgmac_pdata *yt = netdev_priv(dev); + + if (dev->mtu > ETH_DATA_LEN) + return -EOPNOTSUPP; + + phy_set_asym_pause(yt->phydev, data->rx_pause, data->tx_pause); + + yt_dbg(yt, "%s, autoneg=%d, rx=%d, tx=%d\n", __func__, + data->autoneg, data->rx_pause, data->tx_pause); + + return 0; +} + +static void fxgmac_ethtool_get_strings(struct net_device *netdev, u32 stringset, + u8 *data) +{ + switch (stringset) { + case ETH_SS_STATS: + for (u32 i = 0; i < FXGMAC_STATS_COUNT; i++) { + memcpy(data, fxgmac_gstring_stats[i].stat_string, + strlen(fxgmac_gstring_stats[i].stat_string)); + data += ETH_GSTRING_LEN; + } + break; + default: + WARN_ON(1); + break; + } +} + +static int fxgmac_ethtool_get_sset_count(struct net_device *netdev, + int stringset) +{ + int ret; + + switch (stringset) { + case ETH_SS_STATS: + ret = FXGMAC_STATS_COUNT; + break; + + default: + ret = -EOPNOTSUPP; + } + + return ret; +} + +static void fxgmac_ethtool_get_ethtool_stats(struct net_device *netdev, + struct ethtool_stats *stats, + u64 *data) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + + if (!test_bit(FXGMAC_POWER_STATE_DOWN, &pdata->powerstate)) + pdata->hw_ops.read_mmc_stats(pdata); + + for (u32 i = 0; i < FXGMAC_STATS_COUNT; i++) + *data++ = *(u64 *)((u8 *)pdata + + fxgmac_gstring_stats[i].stat_offset); +} + +static int fxgmac_ethtool_reset(struct net_device *netdev, u32 *flag) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + int ret = 0; + u32 val; + + val = *flag & (ETH_RESET_ALL | ETH_RESET_PHY); + if (!val) { + yt_err(pdata, "Operation not support.\n"); + return -EOPNOTSUPP; + } + + switch (*flag) { + case ETH_RESET_ALL: + fxgmac_restart(pdata); + *flag = 0; + break; + case ETH_RESET_PHY: + /* Power off and on the phy in order to properly + * configure the MAC timing + */ + ret = phy_modify(pdata->phydev, MII_BMCR, BMCR_PDOWN, + BMCR_PDOWN); + if (ret < 0) + return ret; + fsleep(9000); + + ret = phy_modify(pdata->phydev, MII_BMCR, BMCR_PDOWN, 0); + if (ret < 0) + return ret; + *flag = 0; + break; + default: + break; + } + + return 0; +} + +static const struct ethtool_ops fxgmac_ethtool_ops = { + .get_drvinfo = fxgmac_ethtool_get_drvinfo, + .get_link = ethtool_op_get_link, + .get_msglevel = fxgmac_ethtool_get_msglevel, + .set_msglevel = fxgmac_ethtool_set_msglevel, + .get_channels = fxgmac_ethtool_get_channels, + .get_coalesce = fxgmac_ethtool_get_coalesce, + .set_coalesce = fxgmac_ethtool_set_coalesce, + .reset = fxgmac_ethtool_reset, + .supported_coalesce_params = ETHTOOL_COALESCE_USECS, + .get_strings = fxgmac_ethtool_get_strings, + .get_sset_count = fxgmac_ethtool_get_sset_count, + .get_ethtool_stats = fxgmac_ethtool_get_ethtool_stats, + .get_regs_len = fxgmac_get_regs_len, + .get_regs = fxgmac_get_regs, + .get_ringparam = fxgmac_get_ringparam, + .set_ringparam = fxgmac_set_ringparam, + .get_rxnfc = fxgmac_get_rxnfc, + .set_rxnfc = fxgmac_set_rxnfc, + .get_rxfh_indir_size = fxgmac_rss_indir_size, + .get_rxfh_key_size = fxgmac_get_rxfh_key_size, + .nway_reset = phy_ethtool_nway_reset, + .get_link_ksettings = phy_ethtool_get_link_ksettings, + .set_link_ksettings = phy_ethtool_set_link_ksettings, + .get_pauseparam = fxgmac_get_pauseparam, + .set_pauseparam = fxgmac_set_pauseparam, +}; + +const struct ethtool_ops *fxgmac_get_ethtool_ops(void) +{ + return &fxgmac_ethtool_ops; +} -- 2.34.1

driver inclusion category: feature -------------------------------- Implement the pci_driver suspend function to enable the device to sleep, and implement the resume function to enable the device to resume operation. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> --- .../net/ethernet/motorcomm/yt6801/yt6801_hw.c | 118 ++++++++++++++++++ .../ethernet/motorcomm/yt6801/yt6801_net.c | 28 +++++ .../ethernet/motorcomm/yt6801/yt6801_pci.c | 61 +++++++++ 3 files changed, 207 insertions(+) diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_hw.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_hw.c index bd3036625..25411f2dd 100644 --- a/drivers/net/ethernet/motorcomm/yt6801/yt6801_hw.c +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_hw.c @@ -2424,6 +2424,56 @@ static void fxgmac_config_dma_bus(struct fxgmac_pdata *pdata) wr32_mac(pdata, val, DMA_SBMR); } +static int fxgmac_pre_powerdown(struct fxgmac_pdata *pdata) +{ + u32 val = 0; + int ret; + + fxgmac_disable_rx(pdata); + + yt_dbg(pdata, "%s, phy and mac status update\n", __func__); + + if (device_may_wakeup(pdata->dev)) { + val = rd32_mem(pdata, EPHY_CTRL); + if (val & EPHY_CTRL_STA_LINKUP) { + ret = phy_speed_down(pdata->phydev, true); + if (ret < 0) { + yt_err(pdata, "%s, phy_speed_down err:%d\n", __func__, ret); + return ret; + } + + ret = phy_read_status(pdata->phydev); + if (ret < 0) { + yt_err(pdata, "%s, phy_read_status err:%d\n", + __func__, ret); + return ret; + } + + pdata->phy_speed = pdata->phydev->speed; + pdata->phy_duplex = pdata->phydev->duplex; + yt_dbg(pdata, "%s, speed :%d, duplex :%d\n", __func__, + pdata->phy_speed, pdata->phy_duplex); + + fxgmac_config_mac_speed(pdata); + } else { + yt_dbg(pdata, "%s link down, do nothing\n", __func__); + } + } + + /* After enable OOB_WOL from efuse, mac will loopcheck phy status, + * and lead to panic sometimes. So we should disable it from powerup, + * enable it from power down. + */ + val = rd32_mem(pdata, OOB_WOL_CTRL); + fxgmac_set_bits(&val, OOB_WOL_CTRL_DIS_POS, OOB_WOL_CTRL_DIS_LEN, 0); + wr32_mem(pdata, val, OOB_WOL_CTRL); + fsleep(2000); + + fxgmac_set_mac_address(pdata, pdata->mac_addr); + + return 0; +} + static int fxgmac_phy_clear_interrupt(struct fxgmac_pdata *pdata) { u32 stats_pre, stats; @@ -2458,6 +2508,70 @@ static int fxgmac_phy_clear_interrupt(struct fxgmac_pdata *pdata) return -ETIMEDOUT; } +static void fxgmac_config_powerdown(struct fxgmac_pdata *pdata, + bool wol) +{ + u32 val = 0; + + /* Use default arp offloading feature */ + fxgmac_update_aoe_ipv4addr(pdata, (u8 *)NULL); + fxgmac_enable_arp_offload(pdata); + fxgmac_update_ns_offload_ipv6addr(pdata, FXGMAC_NS_IFA_GLOBAL_UNICAST); + fxgmac_update_ns_offload_ipv6addr(pdata, FXGMAC_NS_IFA_LOCAL_LINK); + fxgmac_enable_ns_offload(pdata); + fxgmac_enable_wake_packet_indication(pdata, 1); + + /* Enable MAC Rx TX */ + val = rd32_mac(pdata, MAC_CR); + fxgmac_set_bits(&val, MAC_CR_RE_POS, MAC_CR_RE_LEN, 1); + fxgmac_set_bits(&val, MAC_CR_TE_POS, MAC_CR_TE_LEN, 1); + wr32_mac(pdata, val, MAC_CR); + + val = rd32_mem(pdata, LPW_CTRL); + fxgmac_set_bits(&val, LPW_CTRL_ASPM_LPW_EN_POS, + LPW_CTRL_ASPM_LPW_EN_LEN, 1); + wr32_mem(pdata, val, LPW_CTRL); + + /* Set gmac power down */ + val = rd32_mac(pdata, MAC_PMT_STA); + fxgmac_set_bits(&val, MAC_PMT_STA_PWRDWN_POS, MAC_PMT_STA_PWRDWN_LEN, + 1); + wr32_mac(pdata, val, MAC_PMT_STA); + + val = rd32_mem(pdata, MGMT_SIGDET); + fxgmac_set_bits(&val, MGMT_SIGDET_POS, MGMT_SIGDET_LEN, + MGMT_SIGDET_55MV); + wr32_mem(pdata, val, MGMT_SIGDET); + fxgmac_phy_clear_interrupt(pdata); +} + +static void fxgmac_config_powerup(struct fxgmac_pdata *pdata) +{ + u32 val = 0; + + /* After enable OOB_WOL from efuse, mac will loopcheck phy status, + * and lead to panic sometimes. + * So we should disable it from powerup, enable it from power down. + */ + val = rd32_mem(pdata, OOB_WOL_CTRL); + fxgmac_set_bits(&val, OOB_WOL_CTRL_DIS_POS, OOB_WOL_CTRL_DIS_LEN, 1); + wr32_mem(pdata, val, OOB_WOL_CTRL); + + /* Clear wpi mode whether or not waked by WOL, write reset value */ + val = rd32_mem(pdata, MGMT_WPI_CTRL0); + fxgmac_set_bits(&val, MGMT_WPI_CTRL0_WPI_MODE_POS, + MGMT_WPI_CTRL0_WPI_MODE_LEN, 0); + wr32_mem(pdata, val, MGMT_WPI_CTRL0); + + /* Read pmt_status register to De-assert the pmt_intr_o */ + val = rd32_mac(pdata, MAC_PMT_STA); + /* whether or not waked up by WOL, write reset value */ + fxgmac_set_bits(&val, MAC_PMT_STA_PWRDWN_POS, MAC_PMT_STA_PWRDWN_LEN, + 0); + /* Write register to synchronized always-on block */ + wr32_mac(pdata, val, MAC_PMT_STA); +} + #define FXGMAC_WOL_WAIT_2_MS 2 static void fxgmac_config_wol_wait_time(struct fxgmac_pdata *pdata) @@ -3262,4 +3376,8 @@ void fxgmac_hw_ops_init(struct fxgmac_hw_ops *hw_ops) hw_ops->enable_wake_pattern = fxgmac_enable_wake_pattern; hw_ops->disable_wake_pattern = fxgmac_disable_wake_pattern; + /* Power Management */ + hw_ops->pre_power_down = fxgmac_pre_powerdown; + hw_ops->config_power_down = fxgmac_config_powerdown; + hw_ops->config_power_up = fxgmac_config_powerup; } diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c index 6a3d1073c..10c103e95 100644 --- a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c @@ -986,6 +986,34 @@ static void fxgmac_restart_work(struct work_struct *work) rtnl_unlock(); } +int fxgmac_net_powerup(struct fxgmac_pdata *pdata) +{ + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + int ret; + + /* Signal that we are up now */ + pdata->powerstate = 0; + if (__test_and_set_bit(FXGMAC_POWER_STATE_UP, &pdata->powerstate)) + return 0; /* do nothing if already up */ + + ret = fxgmac_start(pdata); + if (ret < 0) { + yt_err(pdata, "%s: fxgmac_start err: %d\n", __func__, ret); + return ret; + } + + /* Must call it after fxgmac_start,because it will be + * enable in fxgmac_start + */ + hw_ops->disable_arp_offload(pdata); + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "%s, powerstate :%ld.\n", __func__, + pdata->powerstate); + + return 0; +} + int fxgmac_config_wol(struct fxgmac_pdata *pdata, bool en) { struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_pci.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_pci.c index b2cd75b5c..860b79d13 100644 --- a/drivers/net/ethernet/motorcomm/yt6801/yt6801_pci.c +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_pci.c @@ -104,6 +104,62 @@ static void fxgmac_shutdown(struct pci_dev *pcidev) (system_state == SYSTEM_POWER_OFF) ? 1 : 0); } +static int fxgmac_suspend(struct device *device) +{ + struct fxgmac_pdata *pdata = dev_get_drvdata(device); + struct net_device *netdev = pdata->netdev; + int ret = 0; + + mutex_lock(&pdata->mutex); + if (pdata->dev_state != FXGMAC_DEV_START) + goto unlock; + + if (netif_running(netdev)) { + ret = __fxgmac_shutdown(to_pci_dev(device), NULL); + if (ret < 0) + goto unlock; + } + + pdata->dev_state = FXGMAC_DEV_SUSPEND; +unlock: + mutex_unlock(&pdata->mutex); + + return ret; +} + +static int fxgmac_resume(struct device *device) +{ + struct fxgmac_pdata *pdata = dev_get_drvdata(device); + struct net_device *netdev = pdata->netdev; + int ret = 0; + + mutex_lock(&pdata->mutex); + if (pdata->dev_state != FXGMAC_DEV_SUSPEND) + goto unlock; + + pdata->dev_state = FXGMAC_DEV_RESUME; + __clear_bit(FXGMAC_POWER_STATE_DOWN, &pdata->powerstate); + + rtnl_lock(); + if (netif_running(netdev)) { + ret = fxgmac_net_powerup(pdata); + if (ret < 0) { + dev_err(device, "%s, fxgmac_net_powerup err:%d\n", + __func__, ret); + goto unlock; + } + } + + netif_device_attach(netdev); + rtnl_unlock(); + + dev_dbg(device, "%s ok\n", __func__); +unlock: + mutex_unlock(&pdata->mutex); + + return ret; +} + #define MOTORCOMM_PCI_ID 0x1f0a #define YT6801_PCI_DEVICE_ID 0x6801 @@ -114,11 +170,16 @@ static const struct pci_device_id fxgmac_pci_tbl[] = { MODULE_DEVICE_TABLE(pci, fxgmac_pci_tbl); +static const struct dev_pm_ops fxgmac_pm_ops = { + SYSTEM_SLEEP_PM_OPS(fxgmac_suspend, fxgmac_resume) +}; + static struct pci_driver fxgmac_pci_driver = { .name = FXGMAC_DRV_NAME, .id_table = fxgmac_pci_tbl, .probe = fxgmac_probe, .remove = fxgmac_remove, + .driver.pm = pm_ptr(&fxgmac_pm_ops), .shutdown = fxgmac_shutdown, }; -- 2.34.1

driver inclusion category: feature -------------------------------- Implement following callback function .ndo_stop .ndo_start_xmit .ndo_get_stats64 .ndo_set_mac_address .ndo_validate_addr .ndo_vlan_rx_add_vid .ndo_vlan_rx_kill_vid .ndo_poll_controller .ndo_set_features .ndo_fix_features .ndo_set_rx_mode Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> --- .../ethernet/motorcomm/yt6801/yt6801_net.c | 196 ++++++++++++++++++ 1 file changed, 196 insertions(+) diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c index fa1587e69..ed65c9cc9 100644 --- a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c @@ -996,6 +996,25 @@ static int fxgmac_open(struct net_device *netdev) return ret; } +static int fxgmac_close(struct net_device *netdev) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + + mutex_lock(&pdata->mutex); + fxgmac_stop(pdata); /* Stop the device */ + pdata->dev_state = FXGMAC_DEV_CLOSE; + fxgmac_channels_rings_free(pdata); /* Free the channels and rings */ + hw_ops->reset_phy(pdata); + phy_disconnect(pdata->phydev); + mutex_unlock(&pdata->mutex); + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "%s ok\n", __func__); + + return 0; +} + #define EFUSE_FISRT_UPDATE_ADDR 255 #define EFUSE_SECOND_UPDATE_ADDR 209 #define EFUSE_MAX_ENTRY 39 @@ -1981,9 +2000,186 @@ static netdev_tx_t fxgmac_xmit(struct sk_buff *skb, struct net_device *netdev) return NETDEV_TX_OK; } + +static void fxgmac_get_stats64(struct net_device *netdev, + struct rtnl_link_stats64 *s) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + struct fxgmac_stats *pstats = &pdata->stats; + + if (test_bit(FXGMAC_POWER_STATE_DOWN, &pdata->powerstate)) + return; + + pdata->hw_ops.read_mmc_stats(pdata); + + s->rx_packets = pstats->rxframecount_gb; + s->rx_bytes = pstats->rxoctetcount_gb; + s->rx_errors = pstats->rxframecount_gb - pstats->rxbroadcastframes_g - + pstats->rxmulticastframes_g - pstats->rxunicastframes_g; + + s->rx_length_errors = pstats->rxlengtherror; + s->rx_crc_errors = pstats->rxcrcerror; + s->rx_fifo_errors = pstats->rxfifooverflow; + + s->tx_packets = pstats->txframecount_gb; + s->tx_bytes = pstats->txoctetcount_gb; + s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g; + s->tx_dropped = netdev->stats.tx_dropped; +} + +static int fxgmac_set_mac_address(struct net_device *netdev, void *addr) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + struct sockaddr *saddr = addr; + + if (!is_valid_ether_addr(saddr->sa_data)) + return -EADDRNOTAVAIL; + + eth_hw_addr_set(netdev, saddr->sa_data); + memcpy(pdata->mac_addr, saddr->sa_data, netdev->addr_len); + hw_ops->set_mac_address(pdata, saddr->sa_data); + hw_ops->set_mac_hash(pdata); + + yt_dbg(pdata, "fxgmac,set mac addr to %pM\n", netdev->dev_addr); + + return 0; +} + +static int fxgmac_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, + u16 vid) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + + set_bit(vid, pdata->active_vlans); + hw_ops->update_vlan_hash_table(pdata); + + yt_dbg(pdata, "fxgmac,add rx vlan %d\n", vid); + + return 0; +} + +static int fxgmac_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, + u16 vid) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + + clear_bit(vid, pdata->active_vlans); + hw_ops->update_vlan_hash_table(pdata); + + yt_dbg(pdata, "fxgmac,del rx vlan %d\n", vid); + + return 0; +} + +#ifdef CONFIG_NET_POLL_CONTROLLER +static void fxgmac_poll_controller(struct net_device *netdev) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + struct fxgmac_channel *channel; + + if (pdata->per_channel_irq) { + channel = pdata->channel_head; + for (u32 i = 0; i < pdata->channel_count; i++, channel++) + fxgmac_dma_isr(channel->dma_irq_rx, channel); + } else { + disable_irq(pdata->dev_irq); + fxgmac_isr(pdata->dev_irq, pdata); + enable_irq(pdata->dev_irq); + } +} +#endif /* CONFIG_NET_POLL_CONTROLLER */ + +static netdev_features_t fxgmac_fix_features(struct net_device *netdev, + netdev_features_t features) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + u32 fifo_size; + + fifo_size = pdata->hw_ops.calculate_max_checksum_size(pdata); + if (netdev->mtu > fifo_size) { + features &= ~NETIF_F_IP_CSUM; + features &= ~NETIF_F_IPV6_CSUM; + } + + return features; +} + +static int fxgmac_set_features(struct net_device *netdev, + netdev_features_t features) +{ + netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter, tso; + struct fxgmac_pdata *pdata = netdev_priv(netdev); + struct fxgmac_hw_ops *hw_ops; + + hw_ops = &pdata->hw_ops; + rxhash = pdata->netdev_features & NETIF_F_RXHASH; + rxcsum = pdata->netdev_features & NETIF_F_RXCSUM; + rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX; + rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER; + tso = pdata->netdev_features & (NETIF_F_TSO | NETIF_F_TSO6); + + if ((features & (NETIF_F_TSO | NETIF_F_TSO6)) && !tso) { + yt_dbg(pdata, "enable tso.\n"); + pdata->hw_feat.tso = 1; + hw_ops->config_tso(pdata); + } else if (!(features & (NETIF_F_TSO | NETIF_F_TSO6)) && tso) { + yt_dbg(pdata, "disable tso.\n"); + pdata->hw_feat.tso = 0; + hw_ops->config_tso(pdata); + } + + if ((features & NETIF_F_RXHASH) && !rxhash) + hw_ops->enable_rss(pdata); + else if (!(features & NETIF_F_RXHASH) && rxhash) + hw_ops->disable_rss(pdata); + + if ((features & NETIF_F_RXCSUM) && !rxcsum) + hw_ops->enable_rx_csum(pdata); + else if (!(features & NETIF_F_RXCSUM) && rxcsum) + hw_ops->disable_rx_csum(pdata); + + if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan) + hw_ops->enable_rx_vlan_stripping(pdata); + else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan) + hw_ops->disable_rx_vlan_stripping(pdata); + + if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter) + hw_ops->enable_rx_vlan_filtering(pdata); + else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter) + hw_ops->disable_rx_vlan_filtering(pdata); + + pdata->netdev_features = features; + + yt_dbg(pdata, "fxgmac,set features done,%llx\n", (u64)features); + return 0; +} + +static void fxgmac_set_rx_mode(struct net_device *netdev) +{ + struct fxgmac_pdata *pdata = netdev_priv(netdev); + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + + hw_ops->config_rx_mode(pdata); +} + static const struct net_device_ops fxgmac_netdev_ops = { .ndo_open = fxgmac_open, + .ndo_stop = fxgmac_close, .ndo_start_xmit = fxgmac_xmit, + .ndo_get_stats64 = fxgmac_get_stats64, + .ndo_set_mac_address = fxgmac_set_mac_address, + .ndo_validate_addr = eth_validate_addr, + .ndo_vlan_rx_add_vid = fxgmac_vlan_rx_add_vid, + .ndo_vlan_rx_kill_vid = fxgmac_vlan_rx_kill_vid, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = fxgmac_poll_controller, +#endif + .ndo_set_features = fxgmac_set_features, + .ndo_fix_features = fxgmac_fix_features, + .ndo_set_rx_mode = fxgmac_set_rx_mode, }; const struct net_device_ops *fxgmac_get_netdev_ops(void) -- 2.34.1

driver inclusion category: feature -------------------------------- Implement some hw_ops function to set default hardware settings, including PHY control, Vlan related config, RX coalescing, Receive Side Scaling and other basic function control. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> --- .../net/ethernet/motorcomm/yt6801/yt6801_hw.c | 2216 +++++++++++++++++ 1 file changed, 2216 insertions(+) create mode 100644 drivers/net/ethernet/motorcomm/yt6801/yt6801_hw.c diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_hw.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_hw.c new file mode 100644 index 000000000..1af26b0b4 --- /dev/null +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_hw.c @@ -0,0 +1,2216 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2022 - 2024 Motorcomm Electronic Technology Co.,Ltd. */ + +#include "yt6801_desc.h" +#include "yt6801_net.h" + +static void fxgmac_disable_rx_csum(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, MAC_CR); + fxgmac_set_bits(&val, MAC_CR_IPC_POS, MAC_CR_IPC_LEN, 0); + wr32_mac(pdata, val, MAC_CR); +} + +static void fxgmac_enable_rx_csum(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, MAC_CR); + fxgmac_set_bits(&val, MAC_CR_IPC_POS, MAC_CR_IPC_LEN, 1); + wr32_mac(pdata, val, MAC_CR); +} + +static void fxgmac_disable_tx_vlan(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, MAC_VLANIR); + /* Set VLAN Tag input enable */ + fxgmac_set_bits(&val, MAC_VLANIR_CSVL_POS, MAC_VLANIR_CSVL_LEN, 0); + fxgmac_set_bits(&val, MAC_VLANIR_VLTI_POS, MAC_VLANIR_VLTI_LEN, 1); + /* Set VLAN priority control disable */ + fxgmac_set_bits(&val, MAC_VLANIR_VLP_POS, MAC_VLANIR_VLP_LEN, 0); + fxgmac_set_bits(&val, MAC_VLANIR_VLC_POS, MAC_VLANIR_VLC_LEN, 0); + wr32_mac(pdata, val, MAC_VLANIR); +} + +static void fxgmac_enable_rx_vlan_stripping(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, MAC_VLANTR); + /* Put the VLAN tag in the Rx descriptor */ + fxgmac_set_bits(&val, MAC_VLANTR_EVLRXS_POS, MAC_VLANTR_EVLRXS_LEN, 1); + /* Don't check the VLAN type */ + fxgmac_set_bits(&val, MAC_VLANTR_DOVLTC_POS, MAC_VLANTR_DOVLTC_LEN, 1); + /* Check only C-TAG (0x8100) packets */ + fxgmac_set_bits(&val, MAC_VLANTR_ERSVLM_POS, MAC_VLANTR_ERSVLM_LEN, 0); + /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */ + fxgmac_set_bits(&val, MAC_VLANTR_ESVL_POS, MAC_VLANTR_ESVL_LEN, 0); + /* Enable VLAN tag stripping */ + fxgmac_set_bits(&val, MAC_VLANTR_EVLS_POS, MAC_VLANTR_EVLS_LEN, 3); + wr32_mac(pdata, val, MAC_VLANTR); +} + +static void fxgmac_disable_rx_vlan_stripping(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, MAC_VLANTR); + fxgmac_set_bits(&val, MAC_VLANTR_EVLS_POS, MAC_VLANTR_EVLS_LEN, 0); + wr32_mac(pdata, val, MAC_VLANTR); +} + +static void fxgmac_enable_rx_vlan_filtering(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, MAC_PFR); + /* Enable VLAN filtering */ + fxgmac_set_bits(&val, MAC_PFR_VTFE_POS, MAC_PFR_VTFE_LEN, 1); + wr32_mac(pdata, val, MAC_PFR); + + val = rd32_mac(pdata, MAC_VLANTR); + /* Enable VLAN Hash Table filtering */ + fxgmac_set_bits(&val, MAC_VLANTR_VTHM_POS, MAC_VLANTR_VTHM_LEN, 1); + /* Disable VLAN tag inverse matching */ + fxgmac_set_bits(&val, MAC_VLANTR_VTIM_POS, MAC_VLANTR_VTIM_LEN, 0); + /* Only filter on the lower 12-bits of the VLAN tag */ + fxgmac_set_bits(&val, MAC_VLANTR_ETV_POS, MAC_VLANTR_ETV_LEN, 1); +} + +static void fxgmac_disable_rx_vlan_filtering(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, MAC_PFR); + fxgmac_set_bits(&val, MAC_PFR_VTFE_POS, MAC_PFR_VTFE_LEN, 0); + wr32_mac(pdata, val, MAC_PFR); +} + +static u32 fxgmac_vid_crc32_le(__le16 vid_le) +{ + unsigned char *data = (unsigned char *)&vid_le; + unsigned char data_byte = 0; + u32 crc = ~0; + u32 temp = 0; + int i, bits; + + bits = get_bitmask_order(VLAN_VID_MASK); + for (i = 0; i < bits; i++) { + if ((i % 8) == 0) + data_byte = data[i / 8]; + + temp = ((crc & 1) ^ data_byte) & 1; + crc >>= 1; + data_byte >>= 1; + + if (temp) + crc ^= CRC32_POLY_LE; + } + + return crc; +} + +static void fxgmac_update_vlan_hash_table(struct fxgmac_pdata *pdata) +{ + u16 vid, vlan_hash_table = 0; + __le16 vid_le; + u32 val, crc; + + /* Generate the VLAN Hash Table value */ + for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { + /* Get the CRC32 value of the VLAN ID */ + vid_le = cpu_to_le16(vid); + crc = bitrev32(~fxgmac_vid_crc32_le(vid_le)) >> 28; + + vlan_hash_table |= (1 << crc); + } + + /* Set the VLAN Hash Table filtering register */ + val = rd32_mac(pdata, MAC_VLANHTR); + fxgmac_set_bits(&val, MAC_VLANHTR_VLHT_POS, MAC_VLANHTR_VLHT_LEN, + vlan_hash_table); + wr32_mac(pdata, val, MAC_VLANHTR); + + yt_dbg(pdata, "fxgmac_update_vlan_hash_tabl done,hash tbl=%08x.\n", + vlan_hash_table); +} + +static void fxgmac_set_promiscuous_mode(struct fxgmac_pdata *pdata, + unsigned int enable) +{ + u32 val, en = enable ? 1 : 0; + + val = rd32_mac(pdata, MAC_PFR); + if (FXGMAC_GET_BITS(val, MAC_PFR_PR_POS, MAC_PFR_PR_LEN) == en) + return; + + fxgmac_set_bits(&val, MAC_PFR_PR_POS, MAC_PFR_PR_LEN, en); + wr32_mac(pdata, val, MAC_PFR); + + /* Hardware will still perform VLAN filtering in promiscuous mode */ + if (enable) { + fxgmac_disable_rx_vlan_filtering(pdata); + return; + } + + if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) + fxgmac_enable_rx_vlan_filtering(pdata); +} + +static void fxgmac_enable_rx_broadcast(struct fxgmac_pdata *pdata, + unsigned int enable) +{ + u32 val, en = enable ? 0 : 1; + + val = rd32_mac(pdata, MAC_PFR); + if (FXGMAC_GET_BITS(val, MAC_PFR_DBF_POS, MAC_PFR_DBF_LEN) == en) + return; + + fxgmac_set_bits(&val, MAC_PFR_DBF_POS, MAC_PFR_DBF_LEN, en); + wr32_mac(pdata, val, MAC_PFR); +} + +static void fxgmac_set_all_multicast_mode(struct fxgmac_pdata *pdata, + unsigned int enable) +{ + u32 val, en = enable ? 1 : 0; + + val = rd32_mac(pdata, MAC_PFR); + if (FXGMAC_GET_BITS(val, MAC_PFR_PM_POS, MAC_PFR_PM_LEN) == en) + return; + + fxgmac_set_bits(&val, MAC_PFR_PM_POS, MAC_PFR_PM_LEN, en); + wr32_mac(pdata, val, MAC_PFR); +} + +static void fxgmac_set_mac_reg(struct fxgmac_pdata *pdata, + struct netdev_hw_addr *ha, unsigned int *mac_reg) +{ + unsigned int mac_hi, mac_lo; + u8 *mac_addr; + + mac_lo = 0; + mac_hi = 0; + + if (ha) { + mac_addr = (u8 *)&mac_lo; + mac_addr[0] = ha->addr[0]; + mac_addr[1] = ha->addr[1]; + mac_addr[2] = ha->addr[2]; + mac_addr[3] = ha->addr[3]; + + mac_addr = (u8 *)&mac_hi; + mac_addr[0] = ha->addr[4]; + mac_addr[1] = ha->addr[5]; + + fxgmac_set_bits(&mac_hi, MAC_MACA1HR_AE_POS, + MAC_MACA1HR_AE_LEN, 1); + + yt_dbg(pdata, "adding mac address %pM at %#x\n", ha->addr, + *mac_reg); + } + + /* If "ha" is NULL, clear the additional MAC address entries */ + wr32_mac(pdata, mac_hi, *mac_reg); + *mac_reg += MAC_MACA_INC; + wr32_mac(pdata, mac_lo, *mac_reg); + *mac_reg += MAC_MACA_INC; +} + +static void fxgmac_set_mac_addn_addrs(struct fxgmac_pdata *pdata) +{ + struct net_device *netdev = pdata->netdev; + unsigned int addn_macs, mac_reg; + struct netdev_hw_addr *ha; + + mac_reg = MAC_MACA1HR; + addn_macs = pdata->hw_feat.addn_mac; + + if (netdev_uc_count(netdev) > addn_macs) { + fxgmac_set_promiscuous_mode(pdata, 1); + } else { + netdev_for_each_uc_addr(ha, netdev) { + fxgmac_set_mac_reg(pdata, ha, &mac_reg); + addn_macs--; + } + + if (netdev_mc_count(netdev) > addn_macs) { + fxgmac_set_all_multicast_mode(pdata, 1); + } else { + netdev_for_each_mc_addr(ha, netdev) { + fxgmac_set_mac_reg(pdata, ha, &mac_reg); + addn_macs--; + } + } + } + + /* Clear remaining additional MAC address entries */ + while (addn_macs--) + fxgmac_set_mac_reg(pdata, NULL, &mac_reg); +} + +#define GET_REG_AND_BIT_POS(reversalval, regout, bitout) \ + do { \ + typeof(reversalval)(_reversalval) = (reversalval); \ + regout = (((_reversalval) >> 5) & 0x7); \ + bitout = ((_reversalval) & 0x1f); \ + } while (0) + +static u32 fxgmac_crc32(unsigned char *data, int length) +{ + u32 crc = ~0; + + while (--length >= 0) { + unsigned char byte = *data++; + int bit; + + for (bit = 8; --bit >= 0; byte >>= 1) { + if ((crc ^ byte) & 1) { + crc >>= 1; + crc ^= CRC32_POLY_LE; + } else { + crc >>= 1; + } + } + } + + return ~crc; +} + +/* Maximum MAC address hash table size (256 bits = 8 bytes) */ +#define FXGMAC_MAC_HASH_TABLE_SIZE 8 + +static void fxgmac_config_multicast_mac_hash_table(struct fxgmac_pdata *pdata, + unsigned char *pmc_mac, + int b_add) +{ + unsigned int j, hash_reg, reg_bit; + u32 val, crc, reversal_crc; + + if (!pmc_mac) { + for (j = 0; j < FXGMAC_MAC_HASH_TABLE_SIZE; j++) { + hash_reg = j; + hash_reg = (MAC_HTR0 + hash_reg * MAC_HTR_INC); + wr32_mac(pdata, 0, hash_reg); + } + return; + } + + crc = fxgmac_crc32(pmc_mac, ETH_ALEN); + + /* Reverse the crc */ + for (j = 0, reversal_crc = 0; j < 32; j++) { + if (crc & ((u32)1 << j)) + reversal_crc |= 1 << (31 - j); + } + + GET_REG_AND_BIT_POS((reversal_crc >> 24), hash_reg, reg_bit); + /* Set the MAC Hash Table registers */ + hash_reg = (MAC_HTR0 + hash_reg * MAC_HTR_INC); + + val = rd32_mac(pdata, hash_reg); + fxgmac_set_bits(&val, reg_bit, 1, (b_add ? 1 : 0)); + wr32_mac(pdata, val, hash_reg); +} + +static void fxgmac_set_mac_hash_table(struct fxgmac_pdata *pdata) +{ + struct net_device *netdev = pdata->netdev; + struct netdev_hw_addr *ha; + + fxgmac_config_multicast_mac_hash_table(pdata, NULL, 1); + netdev_for_each_mc_addr(ha, netdev) { + fxgmac_config_multicast_mac_hash_table(pdata, ha->addr, 1); + } +} + +static void fxgmac_set_mc_addresses(struct fxgmac_pdata *pdata) +{ + if (pdata->hw_feat.hash_table_size) + fxgmac_set_mac_hash_table(pdata); + else + fxgmac_set_mac_addn_addrs(pdata); +} + +static void fxgmac_set_multicast_mode(struct fxgmac_pdata *pdata, + unsigned int enable) +{ + if (enable) + fxgmac_set_mc_addresses(pdata); + else + fxgmac_config_multicast_mac_hash_table(pdata, NULL, 1); +} + +static void fxgmac_set_mac_address(struct fxgmac_pdata *pdata, u8 *addr) +{ + u32 mac_hi, mac_lo; + + mac_lo = (u32)addr[0] | ((u32)addr[1] << 8) | + ((u32)addr[2] << 16) | ((u32)addr[3] << 24); + + mac_hi = (u32)addr[4] | ((u32)addr[5] << 8); + + wr32_mac(pdata, mac_lo, MAC_MACA0LR); + wr32_mac(pdata, mac_hi, MAC_MACA0HR); +} + +static void fxgmac_config_mac_address(struct fxgmac_pdata *pdata) +{ + u32 val; + + fxgmac_set_mac_address(pdata, pdata->mac_addr); + + val = rd32_mac(pdata, MAC_PFR); + fxgmac_set_bits(&val, MAC_PFR_HPF_POS, MAC_PFR_HPF_LEN, 1); + fxgmac_set_bits(&val, MAC_PFR_HUC_POS, MAC_PFR_HUC_LEN, 1); + fxgmac_set_bits(&val, MAC_PFR_HMC_POS, MAC_PFR_HMC_LEN, 1); + wr32_mac(pdata, val, MAC_PFR); +} + +static void fxgmac_config_crc_check(struct fxgmac_pdata *pdata) +{ + u32 val, en = pdata->crc_check ? 0 : 1; + + val = rd32_mac(pdata, MAC_ECR); + fxgmac_set_bits(&val, MAC_ECR_DCRCC_POS, MAC_ECR_DCRCC_LEN, en); + wr32_mac(pdata, val, MAC_ECR); +} + +static void fxgmac_config_jumbo(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, MAC_CR); + fxgmac_set_bits(&val, MAC_CR_JE_POS, MAC_CR_JE_LEN, pdata->jumbo); + wr32_mac(pdata, val, MAC_CR); +} + +static void fxgmac_config_checksum_offload(struct fxgmac_pdata *pdata) +{ + if (pdata->netdev->features & NETIF_F_RXCSUM) + fxgmac_enable_rx_csum(pdata); + else + fxgmac_disable_rx_csum(pdata); +} + +static void fxgmac_config_vlan_support(struct fxgmac_pdata *pdata) +{ + /* Configure dynamical vlanID from TX Context. */ + fxgmac_disable_tx_vlan(pdata); + + /* Set the current VLAN Hash Table register value */ + fxgmac_update_vlan_hash_table(pdata); + + if (pdata->vlan_filter) + fxgmac_enable_rx_vlan_filtering(pdata); + else + fxgmac_disable_rx_vlan_filtering(pdata); + + if (pdata->vlan_strip) + fxgmac_enable_rx_vlan_stripping(pdata); + else + fxgmac_disable_rx_vlan_stripping(pdata); +} + +static void fxgmac_config_rx_mode(struct fxgmac_pdata *pdata) +{ + u32 pr_mode, am_mode, mu_mode, bd_mode; + + pr_mode = ((pdata->netdev->flags & IFF_PROMISC) != 0); + am_mode = ((pdata->netdev->flags & IFF_ALLMULTI) != 0); + mu_mode = ((pdata->netdev->flags & IFF_MULTICAST) != 0); + bd_mode = ((pdata->netdev->flags & IFF_BROADCAST) != 0); + + fxgmac_enable_rx_broadcast(pdata, bd_mode); + fxgmac_set_promiscuous_mode(pdata, pr_mode); + fxgmac_set_all_multicast_mode(pdata, am_mode); + fxgmac_set_multicast_mode(pdata, mu_mode); +} + +static void fxgmac_prepare_tx_stop(struct fxgmac_pdata *pdata, + struct fxgmac_channel *channel) +{ + unsigned int tx_q_idx, tx_status; + unsigned int tx_dsr, tx_pos; + unsigned long tx_timeout; + + /* Calculate the status register to read and the position within */ + if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) { + tx_dsr = DMA_DSR0; + tx_pos = (channel->queue_index * DMA_DSR_Q_LEN) + + DMA_DSR0_TPS_START; + } else { + tx_q_idx = channel->queue_index - DMA_DSRX_FIRST_QUEUE; + + tx_dsr = DMA_DSR1 + ((tx_q_idx / DMA_DSRX_QPR) * DMA_DSRX_INC); + tx_pos = ((tx_q_idx % DMA_DSRX_QPR) * DMA_DSR_Q_LEN) + + DMA_DSRX_TPS_START; + } + + /* The Tx engine cannot be stopped if it is actively processing + * descriptors. Wait for the Tx engine to enter the stopped or + * suspended state. + */ + tx_timeout = jiffies + (FXGMAC_DMA_STOP_TIMEOUT * HZ); + + while (time_before(jiffies, tx_timeout)) { + tx_status = rd32_mac(pdata, tx_dsr); + tx_status = FXGMAC_GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_LEN); + if (tx_status == DMA_TPS_STOPPED || + tx_status == DMA_TPS_SUSPENDED) + break; + + fsleep(500); + } + + if (!time_before(jiffies, tx_timeout)) + yt_dbg(pdata, + "timed out waiting for Tx DMA channel %u to stop\n", + channel->queue_index); +} + +static void fxgmac_enable_tx(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val; + + /* Enable Tx DMA channel */ + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_TCR)); + fxgmac_set_bits(&val, DMA_CH_TCR_ST_POS, DMA_CH_TCR_ST_LEN, 1); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_TCR)); + + /* Enable Tx queue */ + val = rd32_mac(pdata, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); + fxgmac_set_bits(&val, MTL_Q_TQOMR_TXQEN_POS, + MTL_Q_TQOMR_TXQEN_LEN, MTL_Q_ENABLED); + wr32_mac(pdata, val, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); + + /* Enable MAC Tx */ + val = rd32_mac(pdata, MAC_CR); + fxgmac_set_bits(&val, MAC_CR_TE_POS, MAC_CR_TE_LEN, 1); + wr32_mac(pdata, val, MAC_CR); +} + +static void fxgmac_disable_tx(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val; + + /* Prepare for Tx DMA channel stop */ + fxgmac_prepare_tx_stop(pdata, channel); + + /* Disable MAC Tx */ + val = rd32_mac(pdata, MAC_CR); + fxgmac_set_bits(&val, MAC_CR_TE_POS, MAC_CR_TE_LEN, 0); + wr32_mac(pdata, val, MAC_CR); + + /* Disable Tx queue */ + val = rd32_mac(pdata, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); + fxgmac_set_bits(&val, MTL_Q_TQOMR_TXQEN_POS, + MTL_Q_TQOMR_TXQEN_LEN, 0); + wr32_mac(pdata, val, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); + + /* Disable Tx DMA channel */ + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_TCR)); + fxgmac_set_bits(&val, DMA_CH_TCR_ST_POS, + DMA_CH_TCR_ST_LEN, 0); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_TCR)); +} + +static void fxgmac_prepare_rx_stop(struct fxgmac_pdata *pdata, + unsigned int queue) +{ + unsigned int rx_status, rx_q, rx_q_sts; + unsigned long rx_timeout; + + /* The Rx engine cannot be stopped if it is actively processing + * packets. Wait for the Rx queue to empty the Rx fifo. + */ + rx_timeout = jiffies + (FXGMAC_DMA_STOP_TIMEOUT * HZ); + + while (time_before(jiffies, rx_timeout)) { + rx_status = rd32_mac(pdata, FXGMAC_MTL_REG(queue, MTL_Q_RQDR)); + rx_q = FXGMAC_GET_BITS(rx_status, MTL_Q_RQDR_PRXQ_POS, + MTL_Q_RQDR_PRXQ_LEN); + rx_q_sts = FXGMAC_GET_BITS(rx_status, MTL_Q_RQDR_RXQSTS_POS, + MTL_Q_RQDR_RXQSTS_LEN); + if (rx_q == 0 && rx_q_sts == 0) + break; + + fsleep(500); + } + + if (!time_before(jiffies, rx_timeout)) + yt_dbg(pdata, "timed out waiting for Rx queue %u to empty\n", + queue); +} + +static void fxgmac_enable_rx(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val, i; + + /* Enable each Rx DMA channel */ + for (i = 0; i < pdata->channel_count; i++, channel++) { + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_RCR)); + fxgmac_set_bits(&val, DMA_CH_RCR_SR_POS, DMA_CH_RCR_SR_LEN, 1); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_RCR)); + } + + /* Enable each Rx queue */ + val = 0; + for (i = 0; i < pdata->rx_q_count; i++) + val |= (0x02 << (i << 1)); + + wr32_mac(pdata, val, MAC_RQC0R); + + /* Enable MAC Rx */ + val = rd32_mac(pdata, MAC_CR); + fxgmac_set_bits(&val, MAC_CR_CST_POS, MAC_CR_CST_LEN, 1); + fxgmac_set_bits(&val, MAC_CR_ACS_POS, MAC_CR_ACS_LEN, 1); + fxgmac_set_bits(&val, MAC_CR_RE_POS, MAC_CR_RE_LEN, 1); + wr32_mac(pdata, val, MAC_CR); +} + +static void fxgmac_disable_rx(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val, i; + + /* Disable MAC Rx */ + val = rd32_mac(pdata, MAC_CR); + fxgmac_set_bits(&val, MAC_CR_CST_POS, MAC_CR_CST_LEN, 0); + fxgmac_set_bits(&val, MAC_CR_ACS_POS, MAC_CR_ACS_LEN, 0); + fxgmac_set_bits(&val, MAC_CR_RE_POS, MAC_CR_RE_LEN, 0); + wr32_mac(pdata, val, MAC_CR); + + /* Prepare for Rx DMA channel stop */ + for (i = 0; i < pdata->rx_q_count; i++) + fxgmac_prepare_rx_stop(pdata, i); + + wr32_mac(pdata, 0, MAC_RQC0R); /* Disable each Rx queue */ + + /* Disable each Rx DMA channel */ + for (i = 0; i < pdata->channel_count; i++, channel++) { + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_RCR)); + fxgmac_set_bits(&val, DMA_CH_RCR_SR_POS, DMA_CH_RCR_SR_LEN, 0); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_RCR)); + } +} + +static void fxgmac_config_tx_flow_control(struct fxgmac_pdata *pdata) +{ + u32 val, i; + + /* Set MTL flow control */ + for (i = 0; i < pdata->rx_q_count; i++) { + val = rd32_mac(pdata, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + fxgmac_set_bits(&val, MTL_Q_RQOMR_EHFC_POS, + MTL_Q_RQOMR_EHFC_LEN, pdata->tx_pause); + wr32_mac(pdata, val, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + } + + /* Set MAC flow control */ + val = rd32_mac(pdata, MAC_Q0TFCR); + fxgmac_set_bits(&val, MAC_Q0TFCR_TFE_POS, MAC_Q0TFCR_TFE_LEN, + pdata->tx_pause); + if (pdata->tx_pause == 1) + /* Set pause time */ + fxgmac_set_bits(&val, MAC_Q0TFCR_PT_POS, + MAC_Q0TFCR_PT_LEN, 0xffff); + wr32_mac(pdata, val, MAC_Q0TFCR); +} + +static void fxgmac_config_rx_flow_control(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, MAC_RFCR); + fxgmac_set_bits(&val, MAC_RFCR_RFE_POS, MAC_RFCR_RFE_LEN, + pdata->rx_pause); + wr32_mac(pdata, val, MAC_RFCR); +} + +static void fxgmac_config_rx_coalesce(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val; + + for (u32 i = 0; i < pdata->channel_count; i++, channel++) { + if (!channel->rx_ring) + break; + + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_RIWT)); + fxgmac_set_bits(&val, DMA_CH_RIWT_RWT_POS, DMA_CH_RIWT_RWT_LEN, + pdata->rx_riwt); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_RIWT)); + } +} + +static void fxgmac_config_rx_fep_disable(struct fxgmac_pdata *pdata) +{ + u32 val; + + for (u32 i = 0; i < pdata->rx_q_count; i++) { + val = rd32_mac(pdata, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + /* Enable the rx queue forward packet with error status + * (crc error,gmii_er, watch dog timeout.or overflow) + */ + fxgmac_set_bits(&val, MTL_Q_RQOMR_FEP_POS, MTL_Q_RQOMR_FEP_LEN, + MTL_FEP_ENABLE); + wr32_mac(pdata, val, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + } +} + +static void fxgmac_config_rx_fup_enable(struct fxgmac_pdata *pdata) +{ + u32 val; + + for (u32 i = 0; i < pdata->rx_q_count; i++) { + val = rd32_mac(pdata, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + fxgmac_set_bits(&val, MTL_Q_RQOMR_FUP_POS, MTL_Q_RQOMR_FUP_LEN, + 1); + wr32_mac(pdata, val, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + } +} + +static void fxgmac_config_rx_buffer_size(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val; + + for (u32 i = 0; i < pdata->channel_count; i++, channel++) { + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_RCR)); + fxgmac_set_bits(&val, DMA_CH_RCR_RBSZ_POS, DMA_CH_RCR_RBSZ_LEN, + pdata->rx_buf_size); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_RCR)); + } +} + +static void fxgmac_config_tso_mode(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val; + + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_TCR)); + fxgmac_set_bits(&val, DMA_CH_TCR_TSE_POS, DMA_CH_TCR_TSE_LEN, + pdata->hw_feat.tso); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_TCR)); +} + +static void fxgmac_config_sph_mode(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val; + + for (u32 i = 0; i < pdata->channel_count; i++, channel++) { + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_CR)); + fxgmac_set_bits(&val, DMA_CH_CR_SPH_POS, DMA_CH_CR_SPH_LEN, 0); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_CR)); + } + + val = rd32_mac(pdata, MAC_ECR); + fxgmac_set_bits(&val, MAC_ECR_HDSMS_POS, MAC_ECR_HDSMS_LEN, + FXGMAC_SPH_HDSMS_SIZE_512B); + wr32_mac(pdata, val, MAC_ECR); +} + +static unsigned int fxgmac_usec_to_riwt(struct fxgmac_pdata *pdata, + unsigned int usec) +{ + /* Convert the input usec value to the watchdog timer value. Each + * watchdog timer value is equivalent to 256 clock cycles. + * Calculate the required value as: + * ( usec * ( system_clock_mhz / 10^6) / 256 + */ + return (usec * (pdata->sysclk_rate / 1000000)) / 256; +} + +static void fxgmac_config_rx_threshold(struct fxgmac_pdata *pdata, + unsigned int set_val) +{ + u32 val; + + for (u32 i = 0; i < pdata->rx_q_count; i++) { + val = rd32_mac(pdata, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + fxgmac_set_bits(&val, MTL_Q_RQOMR_RTC_POS, MTL_Q_RQOMR_RTC_LEN, + set_val); + wr32_mac(pdata, val, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + } +} + +static void fxgmac_config_mtl_mode(struct fxgmac_pdata *pdata) +{ + u32 val; + + /* Set Tx to weighted round robin scheduling algorithm */ + val = rd32_mac(pdata, MTL_OMR); + fxgmac_set_bits(&val, MTL_OMR_ETSALG_POS, MTL_OMR_ETSALG_LEN, + MTL_ETSALG_WRR); + wr32_mac(pdata, val, MTL_OMR); + + /* Set Tx traffic classes to use WRR algorithm with equal weights */ + val = rd32_mac(pdata, FXGMAC_MTL_REG(0, MTL_TC_QWR)); + fxgmac_set_bits(&val, MTL_TC_QWR_QW_POS, MTL_TC_QWR_QW_LEN, 1); + wr32_mac(pdata, val, FXGMAC_MTL_REG(0, MTL_TC_QWR)); + + /* Set Rx to strict priority algorithm */ + val = rd32_mac(pdata, MTL_OMR); + fxgmac_set_bits(&val, MTL_OMR_RAA_POS, MTL_OMR_RAA_LEN, MTL_RAA_SP); + wr32_mac(pdata, val, MTL_OMR); +} + +static void fxgmac_config_queue_mapping(struct fxgmac_pdata *pdata) +{ + unsigned int ppq, ppq_extra, prio_queues; + unsigned int __maybe_unused prio; + unsigned int reg, val, mask; + + /* Map the 8 VLAN priority values to available MTL Rx queues */ + prio_queues = + min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, pdata->rx_q_count); + ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; + ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; + + reg = MAC_RQC2R; + val = 0; + for (u32 i = 0, prio = 0; i < prio_queues;) { + mask = 0; + for (u32 j = 0; j < ppq; j++) { + yt_dbg(pdata, "PRIO%u mapped to RXq%u\n", prio, i); + mask |= (1 << prio); + prio++; + } + + if (i < ppq_extra) { + yt_dbg(pdata, "PRIO%u mapped to RXq%u\n", prio, i); + mask |= (1 << prio); + prio++; + } + + val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); + + if ((i % MAC_RQC2_Q_PER_REG) && i != prio_queues) + continue; + + wr32_mac(pdata, val, reg); + reg += MAC_RQC2_INC; + val = 0; + } + + /* Configure one to one, MTL Rx queue to DMA Rx channel mapping + * ie Q0 <--> CH0, Q1 <--> CH1 ... Q11 <--> CH11 + */ + val = rd32_mac(pdata, MTL_RQDCM0R); + val |= (MTL_RQDCM0R_Q0MDMACH | MTL_RQDCM0R_Q1MDMACH | + MTL_RQDCM0R_Q2MDMACH | MTL_RQDCM0R_Q3MDMACH); + + /* Selection to let RSS work, * ie, bit4,12,20,28 for + * Q0,1,2,3 individual + */ + if (pdata->rss) + val |= (MTL_RQDCM0R_Q0DDMACH | MTL_RQDCM0R_Q1DDMACH | + MTL_RQDCM0R_Q2DDMACH | MTL_RQDCM0R_Q3DDMACH); + + wr32_mac(pdata, val, MTL_RQDCM0R); + + val = rd32_mac(pdata, MTL_RQDCM0R + MTL_RQDCM_INC); + val |= (MTL_RQDCM1R_Q4MDMACH | MTL_RQDCM1R_Q5MDMACH | + MTL_RQDCM1R_Q6MDMACH | MTL_RQDCM1R_Q7MDMACH); + wr32_mac(pdata, val, MTL_RQDCM0R + MTL_RQDCM_INC); +} + +#define FXGMAC_MAX_FIFO 81920 + +static unsigned int fxgmac_calculate_per_queue_fifo(unsigned int fifo_size, + unsigned int queue_count) +{ + u32 q_fifo_size, p_fifo; + + /* Calculate the configured fifo size */ + q_fifo_size = 1 << (fifo_size + 7); + + /* The configured value may not be the actual amount of fifo RAM */ + q_fifo_size = min_t(unsigned int, FXGMAC_MAX_FIFO, q_fifo_size); + q_fifo_size = q_fifo_size / queue_count; + + /* Each increment in the queue fifo size represents 256 bytes of + * fifo, with 0 representing 256 bytes. Distribute the fifo equally + * between the queues. + */ + p_fifo = q_fifo_size / 256; + if (p_fifo) + p_fifo--; + + return p_fifo; +} + +static u32 fxgmac_calculate_max_checksum_size(struct fxgmac_pdata *pdata) +{ + u32 fifo_size; + + fifo_size = fxgmac_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size, + FXGMAC_TX_1_Q); + + /* Each increment in the queue fifo size represents 256 bytes of + * fifo, with 0 representing 256 bytes. Distribute the fifo equally + * between the queues. + */ + fifo_size = (fifo_size + 1) * 256; + + /* Packet size < TxQSize - (PBL + N)*(DATAWIDTH/8), + * Datawidth = 128 + * If Datawidth = 32, N = 7, elseif Datawidth != 32, N = 5. + * TxQSize is indicated by TQS field of MTL_TxQ#_Operation_Mode register + * PBL = TxPBL field in the DMA_CH#_TX_Control register in all + * DMA configurations. + */ + fifo_size -= (pdata->tx_pbl * (pdata->pblx8 ? 8 : 1) + 5) * + (FXGMAC_DATA_WIDTH / 8); + fifo_size -= 256; + + return fifo_size; +} + +static void fxgmac_config_tx_fifo_size(struct fxgmac_pdata *pdata) +{ + u32 val, fifo_size; + + fifo_size = fxgmac_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size, + FXGMAC_TX_1_Q); + + val = rd32_mac(pdata, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); + fxgmac_set_bits(&val, MTL_Q_TQOMR_TQS_POS, MTL_Q_TQOMR_TQS_LEN, + fifo_size); + wr32_mac(pdata, val, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); + + yt_dbg(pdata, "%d Tx hardware queues, %d byte fifo per queue\n", + FXGMAC_TX_1_Q, ((fifo_size + 1) * 256)); +} + +static void fxgmac_config_rx_fifo_size(struct fxgmac_pdata *pdata) +{ + u32 val, fifo_size; + + fifo_size = fxgmac_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size, + pdata->rx_q_count); + + for (u32 i = 0; i < pdata->rx_q_count; i++) { + val = rd32_mac(pdata, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + fxgmac_set_bits(&val, MTL_Q_RQOMR_RQS_POS, MTL_Q_RQOMR_RQS_LEN, + fifo_size); + wr32_mac(pdata, val, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + } + + yt_dbg(pdata, "%d Rx hardware queues, %d byte fifo per queue\n", + pdata->rx_q_count, ((fifo_size + 1) * 256)); +} + +static void fxgmac_config_flow_control_threshold(struct fxgmac_pdata *pdata) +{ + u32 val; + + for (u32 i = 0; i < pdata->rx_q_count; i++) { + val = rd32_mac(pdata, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + /* Activate flow control when less than 4k left in fifo */ + fxgmac_set_bits(&val, MTL_Q_RQOMR_RFA_POS, MTL_Q_RQOMR_RFA_LEN, + 6); + /* De-activate flow control when more than 6k left in fifo */ + fxgmac_set_bits(&val, MTL_Q_RQOMR_RFD_POS, MTL_Q_RQOMR_RFD_LEN, + 10); + wr32_mac(pdata, val, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + } +} + +static void fxgmac_config_tx_threshold(struct fxgmac_pdata *pdata, + unsigned int set_val) +{ + u32 val; + + val = rd32_mac(pdata, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); + fxgmac_set_bits(&val, MTL_Q_TQOMR_TTC_POS, MTL_Q_TQOMR_TTC_LEN, + set_val); + wr32_mac(pdata, val, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); +} + +static void fxgmac_config_rsf_mode(struct fxgmac_pdata *pdata, + unsigned int set_val) +{ + u32 val; + + for (u32 i = 0; i < pdata->rx_q_count; i++) { + val = rd32_mac(pdata, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + fxgmac_set_bits(&val, MTL_Q_RQOMR_RSF_POS, MTL_Q_RQOMR_RSF_LEN, + set_val); + wr32_mac(pdata, val, FXGMAC_MTL_REG(i, MTL_Q_RQOMR)); + } +} + +static void fxgmac_config_tsf_mode(struct fxgmac_pdata *pdata, + unsigned int set_val) +{ + u32 val; + + val = rd32_mac(pdata, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); + fxgmac_set_bits(&val, MTL_Q_TQOMR_TSF_POS, MTL_Q_TQOMR_TSF_LEN, + set_val); + wr32_mac(pdata, val, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); +} + +static void fxgmac_config_osp_mode(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val; + + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_TCR)); + fxgmac_set_bits(&val, DMA_CH_TCR_OSP_POS, DMA_CH_TCR_OSP_LEN, + pdata->tx_osp_mode); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_TCR)); +} + +static void fxgmac_config_pblx8(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val; + + for (u32 i = 0; i < pdata->channel_count; i++, channel++) { + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_CR)); + fxgmac_set_bits(&val, DMA_CH_CR_PBLX8_POS, DMA_CH_CR_PBLX8_LEN, + pdata->pblx8); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_CR)); + } +} + +static void fxgmac_config_tx_pbl_val(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val; + + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_TCR)); + fxgmac_set_bits(&val, DMA_CH_TCR_PBL_POS, DMA_CH_TCR_PBL_LEN, + pdata->tx_pbl); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_TCR)); +} + +static void fxgmac_config_rx_pbl_val(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val; + + for (u32 i = 0; i < pdata->channel_count; i++, channel++) { + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_RCR)); + fxgmac_set_bits(&val, DMA_CH_RCR_PBL_POS, DMA_CH_RCR_PBL_LEN, + pdata->rx_pbl); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_RCR)); + } +} + +static void fxgmac_tx_mmc_int(struct fxgmac_pdata *yt) +{ + unsigned int mmc_isr = rd32_mac(yt, MMC_TISR); + struct fxgmac_stats *stats = &yt->stats; + + if (mmc_isr & BIT(MMC_TISR_TXOCTETCOUNT_GB_POS)) + stats->txoctetcount_gb += rd32_mac(yt, MMC_TXOCTETCOUNT_GB_LO); + + if (mmc_isr & BIT(MMC_TISR_TXFRAMECOUNT_GB_POS)) + stats->txframecount_gb += rd32_mac(yt, MMC_TXFRAMECOUNT_GB_LO); + + if (mmc_isr & BIT(MMC_TISR_TXBROADCASTFRAMES_G_POS)) + stats->txbroadcastframes_g += + rd32_mac(yt, MMC_TXBROADCASTFRAMES_G_LO); + + if (mmc_isr & BIT(MMC_TISR_TXMULTICASTFRAMES_G_POS)) + stats->txmulticastframes_g += + rd32_mac(yt, MMC_TXMULTICASTFRAMES_G_LO); + + if (mmc_isr & BIT(MMC_TISR_TX64OCTETS_GB_POS)) + stats->tx64octets_gb += rd32_mac(yt, MMC_TX64OCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_TISR_TX65TO127OCTETS_GB_POS)) + stats->tx65to127octets_gb += + rd32_mac(yt, MMC_TX65TO127OCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_TISR_TX128TO255OCTETS_GB_POS)) + stats->tx128to255octets_gb += + rd32_mac(yt, MMC_TX128TO255OCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_TISR_TX256TO511OCTETS_GB_POS)) + stats->tx256to511octets_gb += + rd32_mac(yt, MMC_TX256TO511OCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_TISR_TX512TO1023OCTETS_GB_POS)) + stats->tx512to1023octets_gb += + rd32_mac(yt, MMC_TX512TO1023OCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_TISR_TX1024TOMAXOCTETS_GB_POS)) + stats->tx1024tomaxoctets_gb += + rd32_mac(yt, MMC_TX1024TOMAXOCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_TISR_TXUNICASTFRAMES_GB_POS)) + stats->txunicastframes_gb += + rd32_mac(yt, MMC_TXUNICASTFRAMES_GB_LO); + + if (mmc_isr & BIT(MMC_TISR_TXMULTICASTFRAMES_GB_POS)) + stats->txmulticastframes_gb += + rd32_mac(yt, MMC_TXMULTICASTFRAMES_GB_LO); + + if (mmc_isr & BIT(MMC_TISR_TXBROADCASTFRAMES_GB_POS)) + stats->txbroadcastframes_g += + rd32_mac(yt, MMC_TXBROADCASTFRAMES_GB_LO); + + if (mmc_isr & BIT(MMC_TISR_TXUNDERFLOWERROR_POS)) + stats->txunderflowerror += + rd32_mac(yt, MMC_TXUNDERFLOWERROR_LO); + + if (mmc_isr & BIT(MMC_TISR_TXSINGLECOLLISION_G_POS)) + stats->txsinglecollision_g += + rd32_mac(yt, MMC_TXSINGLECOLLISION_G); + + if (mmc_isr & BIT(MMC_TISR_TXMULTIPLECOLLISION_G_POS)) + stats->txmultiplecollision_g += + rd32_mac(yt, MMC_TXMULTIPLECOLLISION_G); + + if (mmc_isr & BIT(MMC_TISR_TXDEFERREDFRAMES_POS)) + stats->txdeferredframes += rd32_mac(yt, MMC_TXDEFERREDFRAMES); + + if (mmc_isr & BIT(MMC_TISR_TXLATECOLLISIONFRAMES_POS)) + stats->txlatecollisionframes += + rd32_mac(yt, MMC_TXLATECOLLISIONFRAMES); + + if (mmc_isr & BIT(MMC_TISR_TXEXCESSIVECOLLISIONFRAMES_POS)) + stats->txexcessivecollisionframes += + rd32_mac(yt, MMC_TXEXCESSIVECOLLSIONFRAMES); + + if (mmc_isr & BIT(MMC_TISR_TXCARRIERERRORFRAMES_POS)) + stats->txcarriererrorframes += + rd32_mac(yt, MMC_TXCARRIERERRORFRAMES); + + if (mmc_isr & BIT(MMC_TISR_TXOCTETCOUNT_G_POS)) + stats->txoctetcount_g += rd32_mac(yt, MMC_TXOCTETCOUNT_G_LO); + + if (mmc_isr & BIT(MMC_TISR_TXFRAMECOUNT_G_POS)) + stats->txframecount_g += rd32_mac(yt, MMC_TXFRAMECOUNT_G_LO); + + if (mmc_isr & BIT(MMC_TISR_TXEXCESSIVEDEFERRALFRAMES_POS)) + stats->txexcessivedeferralerror += + rd32_mac(yt, MMC_TXEXCESSIVEDEFERRALERROR); + + if (mmc_isr & BIT(MMC_TISR_TXPAUSEFRAMES_POS)) + stats->txpauseframes += rd32_mac(yt, MMC_TXPAUSEFRAMES_LO); + + if (mmc_isr & BIT(MMC_TISR_TXVLANFRAMES_G_POS)) + stats->txvlanframes_g += rd32_mac(yt, MMC_TXVLANFRAMES_G_LO); + + if (mmc_isr & BIT(MMC_TISR_TXOVERSIZE_G_POS)) + stats->txoversize_g += rd32_mac(yt, MMC_TXOVERSIZEFRAMES); +} + +static void fxgmac_rx_mmc_int(struct fxgmac_pdata *yt) +{ + unsigned int mmc_isr = rd32_mac(yt, MMC_RISR); + struct fxgmac_stats *stats = &yt->stats; + + if (mmc_isr & BIT(MMC_RISR_RXFRAMECOUNT_GB_POS)) + stats->rxframecount_gb += rd32_mac(yt, MMC_RXFRAMECOUNT_GB_LO); + + if (mmc_isr & BIT(MMC_RISR_RXOCTETCOUNT_GB_POS)) + stats->rxoctetcount_gb += rd32_mac(yt, MMC_RXOCTETCOUNT_GB_LO); + + if (mmc_isr & BIT(MMC_RISR_RXOCTETCOUNT_G_POS)) + stats->rxoctetcount_g += rd32_mac(yt, MMC_RXOCTETCOUNT_G_LO); + + if (mmc_isr & BIT(MMC_RISR_RXBROADCASTFRAMES_G_POS)) + stats->rxbroadcastframes_g += + rd32_mac(yt, MMC_RXBROADCASTFRAMES_G_LO); + + if (mmc_isr & BIT(MMC_RISR_RXMULTICASTFRAMES_G_POS)) + stats->rxmulticastframes_g += + rd32_mac(yt, MMC_RXMULTICASTFRAMES_G_LO); + + if (mmc_isr & BIT(MMC_RISR_RXCRCERROR_POS)) + stats->rxcrcerror += rd32_mac(yt, MMC_RXCRCERROR_LO); + + if (mmc_isr & BIT(MMC_RISR_RXALIGNERROR_POS)) + stats->rxalignerror += rd32_mac(yt, MMC_RXALIGNERROR); + + if (mmc_isr & BIT(MMC_RISR_RXRUNTERROR_POS)) + stats->rxrunterror += rd32_mac(yt, MMC_RXRUNTERROR); + + if (mmc_isr & BIT(MMC_RISR_RXJABBERERROR_POS)) + stats->rxjabbererror += rd32_mac(yt, MMC_RXJABBERERROR); + + if (mmc_isr & BIT(MMC_RISR_RXUNDERSIZE_G_POS)) + stats->rxundersize_g += rd32_mac(yt, MMC_RXUNDERSIZE_G); + + if (mmc_isr & BIT(MMC_RISR_RXOVERSIZE_G_POS)) + stats->rxoversize_g += rd32_mac(yt, MMC_RXOVERSIZE_G); + + if (mmc_isr & BIT(MMC_RISR_RX64OCTETS_GB_POS)) + stats->rx64octets_gb += rd32_mac(yt, MMC_RX64OCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_RISR_RX65TO127OCTETS_GB_POS)) + stats->rx65to127octets_gb += + rd32_mac(yt, MMC_RX65TO127OCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_RISR_RX128TO255OCTETS_GB_POS)) + stats->rx128to255octets_gb += + rd32_mac(yt, MMC_RX128TO255OCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_RISR_RX256TO511OCTETS_GB_POS)) + stats->rx256to511octets_gb += + rd32_mac(yt, MMC_RX256TO511OCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_RISR_RX512TO1023OCTETS_GB_POS)) + stats->rx512to1023octets_gb += + rd32_mac(yt, MMC_RX512TO1023OCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_RISR_RX1024TOMAXOCTETS_GB_POS)) + stats->rx1024tomaxoctets_gb += + rd32_mac(yt, MMC_RX1024TOMAXOCTETS_GB_LO); + + if (mmc_isr & BIT(MMC_RISR_RXUNICASTFRAMES_G_POS)) + stats->rxunicastframes_g += + rd32_mac(yt, MMC_RXUNICASTFRAMES_G_LO); + + if (mmc_isr & BIT(MMC_RISR_RXLENGTHERROR_POS)) + stats->rxlengtherror += rd32_mac(yt, MMC_RXLENGTHERROR_LO); + + if (mmc_isr & BIT(MMC_RISR_RXOUTOFRANGETYPE_POS)) + stats->rxoutofrangetype += + rd32_mac(yt, MMC_RXOUTOFRANGETYPE_LO); + + if (mmc_isr & BIT(MMC_RISR_RXPAUSEFRAMES_POS)) + stats->rxpauseframes += rd32_mac(yt, MMC_RXPAUSEFRAMES_LO); + + if (mmc_isr & BIT(MMC_RISR_RXFIFOOVERFLOW_POS)) + stats->rxfifooverflow += rd32_mac(yt, MMC_RXFIFOOVERFLOW_LO); + + if (mmc_isr & BIT(MMC_RISR_RXVLANFRAMES_GB_POS)) + stats->rxvlanframes_gb += rd32_mac(yt, MMC_RXVLANFRAMES_GB_LO); + + if (mmc_isr & BIT(MMC_RISR_RXWATCHDOGERROR_POS)) + stats->rxwatchdogerror += rd32_mac(yt, MMC_RXWATCHDOGERROR); + + if (mmc_isr & BIT(MMC_RISR_RXERRORFRAMES_POS)) + stats->rxreceiveerrorframe += + rd32_mac(yt, MMC_RXRECEIVEERRORFRAME); + + if (mmc_isr & BIT(MMC_RISR_RXERRORCONTROLFRAMES_POS)) + stats->rxcontrolframe_g += rd32_mac(yt, MMC_RXCONTROLFRAME_G); +} + +static void fxgmac_config_mmc(struct fxgmac_pdata *pdata) +{ + u32 val; + + /* Set counters to reset on read, Reset the counters */ + val = rd32_mac(pdata, MMC_CR); + fxgmac_set_bits(&val, MMC_CR_ROR_POS, MMC_CR_ROR_LEN, 1); + fxgmac_set_bits(&val, MMC_CR_CR_POS, MMC_CR_CR_LEN, 1); + wr32_mac(pdata, val, MMC_CR); + + wr32_mac(pdata, 0xffffffff, MMC_IPCRXINTMASK); +} + +static u32 fxgmac_read_rss_options(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mem(pdata, MGMT_RSS_CTRL); + val = FXGMAC_GET_BITS(val, MGMT_RSS_CTRL_OPT_POS, + MGMT_RSS_CTRL_OPT_LEN); + + return val; +} + +static void fxgmac_write_rss_options(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mem(pdata, MGMT_RSS_CTRL); + fxgmac_set_bits(&val, MGMT_RSS_CTRL_OPT_POS, MGMT_RSS_CTRL_OPT_LEN, + pdata->rss_options); + wr32_mem(pdata, val, MGMT_RSS_CTRL); +} + +static void fxgmac_write_rss_hash_key(struct fxgmac_pdata *pdata) +{ + unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); + u32 *key = (u32 *)&pdata->rss_key; + + while (key_regs--) { + wr32_mem(pdata, cpu_to_be32(*key), + MGMT_RSS_KEY0 + key_regs * MGMT_RSS_KEY_INC); + key++; + } +} + +static void fxgmac_write_rss_lookup_table(struct fxgmac_pdata *pdata) +{ + u32 i, j, val = 0; + + for (i = 0, j = 0; i < ARRAY_SIZE(pdata->rss_table); i++, j++) { + if (j < MGMT_RSS_IDT_ENTRY_SIZE) { + val |= ((pdata->rss_table[i] & MGMT_RSS_IDT_ENTRY_MASK) + << (j * 2)); + continue; + } + + wr32_mem(pdata, val, + MGMT_RSS_IDT + (i / MGMT_RSS_IDT_ENTRY_SIZE - 1) * + MGMT_RSS_IDT_INC); + val = pdata->rss_table[i]; + j = 0; + } + + if (j != MGMT_RSS_IDT_ENTRY_SIZE) + return; + + /* Last IDT */ + wr32_mem(pdata, val, + MGMT_RSS_IDT + + (i / MGMT_RSS_IDT_ENTRY_SIZE - 1) * MGMT_RSS_IDT_INC); +} + +static void fxgmac_set_rss_hash_key(struct fxgmac_pdata *pdata, const u8 *key) +{ + memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); + fxgmac_write_rss_hash_key(pdata); +} + +static u32 log2ex(u32 value) +{ + u32 i = 31; + + while (i > 0) { + if (value & 0x80000000) + break; + + value <<= 1; + i--; + } + return i; +} + +static void fxgmac_enable_rss(struct fxgmac_pdata *pdata) +{ + u32 val, size = 0; + + fxgmac_write_rss_hash_key(pdata); + fxgmac_write_rss_lookup_table(pdata); + + /* Set RSS IDT table size, Enable RSS, Set the RSS options */ + val = rd32_mem(pdata, MGMT_RSS_CTRL); + size = log2ex(FXGMAC_RSS_MAX_TABLE_SIZE) - 1; + fxgmac_set_bits(&val, MGMT_RSS_CTRL_TBL_SIZE_POS, + MGMT_RSS_CTRL_TBL_SIZE_LEN, size); + fxgmac_set_bits(&val, MGMT_RSS_CTRL_RSSE_POS, MGMT_RSS_CTRL_RSSE_LEN, + 1); + fxgmac_set_bits(&val, MGMT_RSS_CTRL_OPT_POS, MGMT_RSS_CTRL_OPT_LEN, + pdata->rss_options); + wr32_mem(pdata, val, MGMT_RSS_CTRL); +} + +static void fxgmac_disable_rss(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mem(pdata, MGMT_RSS_CTRL); + fxgmac_set_bits(&val, MGMT_RSS_CTRL_RSSE_POS, MGMT_RSS_CTRL_RSSE_LEN, + 0); + wr32_mem(pdata, val, MGMT_RSS_CTRL); +} + +static void fxgmac_config_rss(struct fxgmac_pdata *pdata) +{ + if (pdata->rss) + fxgmac_enable_rss(pdata); + else + fxgmac_disable_rss(pdata); +} + +static int fxgmac_check_wake_pattern_fifo_pointer(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, MAC_PMT_STA); + fxgmac_set_bits(&val, MAC_PMT_STA_RWKFILTERST_POS, + MAC_PMT_STA_RWKFILTERST_LEN, 1); + wr32_mac(pdata, val, MAC_PMT_STA); + + val = rd32_mac(pdata, MAC_PMT_STA); + val = FXGMAC_GET_BITS(val, MAC_PMT_STA_RWKPTR_POS, + MAC_PMT_STA_RWKPTR_LEN); + if (val != 0) { + yt_err(pdata, "Remote fifo pointer is not 0\n"); + return -EINVAL; + } + + return 0; +} + +static void fxgmac_enable_dma_interrupts(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 dma_ch; + + for (u32 i = 0; i < pdata->channel_count; i++, channel++) { + /* Clear all the interrupts which are set */ + dma_ch = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_SR)); + wr32_mac(pdata, dma_ch, FXGMAC_DMA_REG(channel, DMA_CH_SR)); + + dma_ch = 0; /* Clear all interrupt enable bits */ + + /* Enable following interrupts + * NIE - Normal Interrupt Summary Enable + * FBEE - Fatal Bus Error Enable + */ + fxgmac_set_bits(&dma_ch, DMA_CH_IER_NIE_POS, DMA_CH_IER_NIE_LEN, + 1); + fxgmac_set_bits(&dma_ch, DMA_CH_IER_FBEE_POS, + DMA_CH_IER_FBEE_LEN, 1); + + if (FXGMAC_IS_CHANNEL_WITH_TX_IRQ(i) && channel->tx_ring) { + /* Enable the following Tx interrupts + * TIE - Transmit Interrupt Enable (unless using + * per channel interrupts) + */ + fxgmac_set_bits(&dma_ch, DMA_CH_IER_TIE_POS, + DMA_CH_IER_TIE_LEN, 1); + } + if (channel->rx_ring) { + /* Enable following Rx interrupts + * RBUE - Receive Buffer Unavailable Enable + * RIE - Receive Interrupt Enable (unless using + * per channel interrupts) + */ + fxgmac_set_bits(&dma_ch, DMA_CH_IER_RBUE_POS, + DMA_CH_IER_RBUE_LEN, 1); + fxgmac_set_bits(&dma_ch, DMA_CH_IER_RIE_POS, + DMA_CH_IER_RIE_LEN, 1); + } + + wr32_mac(pdata, dma_ch, FXGMAC_DMA_REG(channel, DMA_CH_IER)); + } +} + +static void fxgmac_enable_mtl_interrupts(struct fxgmac_pdata *pdata) +{ + unsigned int mtl_q_isr; + + for (u32 i = 0; i < pdata->hw_feat.rx_q_cnt; i++) { + /* Clear all the interrupts which are set */ + mtl_q_isr = rd32_mac(pdata, FXGMAC_MTL_REG(i, MTL_Q_ISR)); + wr32_mac(pdata, mtl_q_isr, FXGMAC_MTL_REG(i, MTL_Q_ISR)); + + /* No MTL interrupts to be enabled */ + wr32_mac(pdata, 0, FXGMAC_MTL_REG(i, MTL_Q_IER)); + } +} + +#define FXGMAC_MMC_IER_ALL_DEFAULT 0 +static void fxgmac_enable_mac_interrupts(struct fxgmac_pdata *pdata) +{ + u32 val, ier = 0; + + /* Enable Timestamp interrupt */ + fxgmac_set_bits(&ier, MAC_IER_TSIE_POS, MAC_IER_TSIE_LEN, 1); + wr32_mac(pdata, ier, MAC_IER); + + val = rd32_mac(pdata, MMC_RIER); + fxgmac_set_bits(&val, MMC_RIER_ALL_INTERRUPTS_POS, + MMC_RIER_ALL_INTERRUPTS_LEN, + FXGMAC_MMC_IER_ALL_DEFAULT); + wr32_mac(pdata, val, MMC_RIER); + + val = rd32_mac(pdata, MMC_TIER); + fxgmac_set_bits(&val, MMC_TIER_ALL_INTERRUPTS_POS, + MMC_TIER_ALL_INTERRUPTS_LEN, + FXGMAC_MMC_IER_ALL_DEFAULT); + wr32_mac(pdata, val, MMC_TIER); +} + +static void fxgmac_config_mac_speed(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, MAC_CR); + if (pdata->phy_duplex != DUPLEX_UNKNOWN) + fxgmac_set_bits(&val, MAC_CR_DM_POS, MAC_CR_DM_LEN, pdata->phy_duplex); + + switch (pdata->phy_speed) { + case SPEED_1000: + fxgmac_set_bits(&val, MAC_CR_PS_POS, MAC_CR_PS_LEN, 0); + fxgmac_set_bits(&val, MAC_CR_FES_POS, MAC_CR_FES_LEN, 0); + break; + case SPEED_100: + fxgmac_set_bits(&val, MAC_CR_PS_POS, MAC_CR_PS_LEN, 1); + fxgmac_set_bits(&val, MAC_CR_FES_POS, MAC_CR_FES_LEN, 1); + break; + case SPEED_10: + fxgmac_set_bits(&val, MAC_CR_PS_POS, MAC_CR_PS_LEN, 1); + fxgmac_set_bits(&val, MAC_CR_FES_POS, MAC_CR_FES_LEN, 0); + break; + default: + WARN_ON(1); + break; + } + + wr32_mac(pdata, val, MAC_CR); +} + +static int mdio_loop_wait(struct fxgmac_pdata *pdata, u32 max_cnt) +{ + u32 val, i; + + for (i = 0; i < max_cnt; i++) { + val = rd32_mac(pdata, MAC_MDIO_ADDRESS); + if ((val & MAC_MDIO_ADDR_BUSY) == 0) + break; + + fsleep(10); + } + + if (i >= max_cnt) { + WARN_ON(1); + yt_err(pdata, "%s timeout. used cnt:%d, reg_val=%x.\n", + __func__, i + 1, val); + + return -ETIMEDOUT; + } + + return 0; +} + +#define PHY_MDIO_MAX_TRY 50 +#define PHY_WR_CONFIG(reg_offset) (0x8000205 + ((reg_offset) * 0x10000)) +static int fxgmac_phy_write_reg(struct fxgmac_pdata *pdata, u32 reg_id, u32 data) +{ + int ret; + + wr32_mac(pdata, data, MAC_MDIO_DATA); + wr32_mac(pdata, PHY_WR_CONFIG(reg_id), MAC_MDIO_ADDRESS); + ret = mdio_loop_wait(pdata, PHY_MDIO_MAX_TRY); + if (ret < 0) + return ret; + + yt_dbg(pdata, "%s, id:%x %s, ctrl:0x%08x, data:0x%08x\n", __func__, + reg_id, (ret == 0) ? "ok" : "err", PHY_WR_CONFIG(reg_id), data); + + return ret; +} + +#define PHY_RD_CONFIG(reg_offset) (0x800020d + ((reg_offset) * 0x10000)) +static int fxgmac_phy_read_reg(struct fxgmac_pdata *pdata, u32 reg_id) +{ + u32 val; + int ret; + + wr32_mac(pdata, PHY_RD_CONFIG(reg_id), MAC_MDIO_ADDRESS); + ret = mdio_loop_wait(pdata, PHY_MDIO_MAX_TRY); + if (ret < 0) + return ret; + + val = rd32_mac(pdata, MAC_MDIO_DATA); /* Read data */ + yt_dbg(pdata, "%s, id:%x ok, ctrl:0x%08x, val:0x%08x.\n", __func__, + reg_id, PHY_RD_CONFIG(reg_id), val); + + return val; +} + +static int fxgmac_config_flow_control(struct fxgmac_pdata *pdata) +{ + u32 val = 0; + int ret; + + fxgmac_config_tx_flow_control(pdata); + fxgmac_config_rx_flow_control(pdata); + + /* Set auto negotiation advertisement pause ability */ + if (pdata->tx_pause || pdata->rx_pause) + val |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; + + ret = phy_modify(pdata->phydev, MII_ADVERTISE, + ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, val); + if (ret < 0) + return ret; + + return phy_modify(pdata->phydev, MII_BMCR, BMCR_RESET, BMCR_RESET); +} + +static void fxgmac_phy_reset(struct fxgmac_pdata *pdata) +{ + u32 val = 0; + + fxgmac_set_bits(&val, EPHY_CTRL_RESET_POS, EPHY_CTRL_RESET_LEN, + EPHY_CTRL_STA_RESET); + wr32_mem(pdata, val, EPHY_CTRL); + fsleep(1500); +} + +static void fxgmac_phy_release(struct fxgmac_pdata *pdata) +{ + u32 val = 0; + + fxgmac_set_bits(&val, EPHY_CTRL_RESET_POS, EPHY_CTRL_RESET_LEN, + EPHY_CTRL_STA_RELEASE); + wr32_mem(pdata, val, EPHY_CTRL); + fsleep(100); +} + +static void fxgmac_enable_channel_irq(struct fxgmac_channel *channel, + enum fxgmac_int int_id) +{ + struct fxgmac_pdata *pdata = channel->pdata; + unsigned int dma_ch_ier; + + dma_ch_ier = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_IER)); + + switch (int_id) { + case FXGMAC_INT_DMA_CH_SR_TI: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_TIE_POS, + DMA_CH_IER_TIE_LEN, 1); + break; + case FXGMAC_INT_DMA_CH_SR_TPS: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_TXSE_POS, + DMA_CH_IER_TXSE_LEN, 1); + break; + case FXGMAC_INT_DMA_CH_SR_TBU: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_TBUE_POS, + DMA_CH_IER_TBUE_LEN, 1); + break; + case FXGMAC_INT_DMA_CH_SR_RI: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_RIE_POS, + DMA_CH_IER_RIE_LEN, 1); + break; + case FXGMAC_INT_DMA_CH_SR_RBU: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_RBUE_POS, + DMA_CH_IER_RBUE_LEN, 1); + break; + case FXGMAC_INT_DMA_CH_SR_RPS: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_RSE_POS, + DMA_CH_IER_RSE_LEN, 1); + break; + case FXGMAC_INT_DMA_CH_SR_TI_RI: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_TIE_POS, + DMA_CH_IER_TIE_LEN, 1); + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_RIE_POS, + DMA_CH_IER_RIE_LEN, 1); + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_NIE_POS, + DMA_CH_IER_NIE_LEN, 1); + break; + case FXGMAC_INT_DMA_CH_SR_FBE: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_FBEE_POS, + DMA_CH_IER_FBEE_LEN, 1); + break; + case FXGMAC_INT_DMA_ALL: + dma_ch_ier |= channel->saved_ier; + break; + default: + WARN_ON(1); + return; + } + + wr32_mac(pdata, dma_ch_ier, FXGMAC_DMA_REG(channel, DMA_CH_IER)); +} + +static void fxgmac_disable_channel_irq(struct fxgmac_channel *channel, + enum fxgmac_int int_id) +{ + struct fxgmac_pdata *pdata = channel->pdata; + u32 dma_ch_ier; + + dma_ch_ier = rd32_mac(channel->pdata, + FXGMAC_DMA_REG(channel, DMA_CH_IER)); + + switch (int_id) { + case FXGMAC_INT_DMA_CH_SR_TI: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_TIE_POS, + DMA_CH_IER_TIE_LEN, 0); + break; + case FXGMAC_INT_DMA_CH_SR_TPS: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_TXSE_POS, + DMA_CH_IER_TXSE_LEN, 0); + break; + case FXGMAC_INT_DMA_CH_SR_TBU: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_TBUE_POS, + DMA_CH_IER_TBUE_LEN, 0); + break; + case FXGMAC_INT_DMA_CH_SR_RI: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_RIE_POS, + DMA_CH_IER_RIE_LEN, 0); + break; + case FXGMAC_INT_DMA_CH_SR_RBU: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_RBUE_POS, + DMA_CH_IER_RBUE_LEN, 0); + break; + case FXGMAC_INT_DMA_CH_SR_RPS: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_RSE_POS, + DMA_CH_IER_RSE_LEN, 0); + break; + case FXGMAC_INT_DMA_CH_SR_TI_RI: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_TIE_POS, + DMA_CH_IER_TIE_LEN, 0); + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_RIE_POS, + DMA_CH_IER_RIE_LEN, 0); + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_NIE_POS, + DMA_CH_IER_NIE_LEN, 0); + break; + case FXGMAC_INT_DMA_CH_SR_FBE: + fxgmac_set_bits(&dma_ch_ier, DMA_CH_IER_FBEE_POS, + DMA_CH_IER_FBEE_LEN, 0); + break; + case FXGMAC_INT_DMA_ALL: +#define FXGMAC_DMA_INTERRUPT_MASK 0x31c7 + channel->saved_ier = dma_ch_ier & FXGMAC_DMA_INTERRUPT_MASK; + dma_ch_ier &= ~FXGMAC_DMA_INTERRUPT_MASK; + break; + default: + WARN_ON(1); + return; + } + + wr32_mac(pdata, dma_ch_ier, FXGMAC_DMA_REG(channel, DMA_CH_IER)); +} + +static void fxgmac_dismiss_all_int(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + u32 val, i; + + for (i = 0; i < pdata->channel_count; i++, channel++) { + /* Clear all the interrupts which are set */ + val = rd32_mac(pdata, FXGMAC_DMA_REG(channel, DMA_CH_SR)); + wr32_mac(pdata, val, FXGMAC_DMA_REG(channel, DMA_CH_SR)); + } + + for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++) { + /* Clear all the interrupts which are set */ + val = rd32_mac(pdata, FXGMAC_MTL_REG(i, MTL_Q_ISR)); + wr32_mac(pdata, val, FXGMAC_MTL_REG(i, MTL_Q_ISR)); + } + + rd32_mac(pdata, MAC_ISR); /* Clear all MAC interrupts */ + /* Clear MAC tx/rx error interrupts */ + rd32_mac(pdata, MAC_TX_RX_STA); + rd32_mac(pdata, MAC_PMT_STA); + rd32_mac(pdata, MAC_LPI_STA); + + val = rd32_mac(pdata, MAC_DBG_STA); + wr32_mac(pdata, val, MAC_DBG_STA); /* Write clear */ +} + +static void fxgmac_set_interrupt_moderation(struct fxgmac_pdata *pdata) +{ + u32 val = 0, time; + + time = (pdata->intr_mod) ? pdata->tx_usecs : 0; + fxgmac_set_bits(&val, INT_MOD_TX_POS, INT_MOD_TX_LEN, time); + + time = (pdata->intr_mod) ? pdata->rx_usecs : 0; + fxgmac_set_bits(&val, INT_MOD_RX_POS, INT_MOD_RX_LEN, time); + wr32_mem(pdata, val, INT_MOD); +} + +static void fxgmac_enable_msix_one_irq(struct fxgmac_pdata *pdata, u32 intid) +{ + wr32_mem(pdata, 0, MSIX_TBL_MASK + intid * 16); +} + +static void fxgmac_disable_msix_one_irq(struct fxgmac_pdata *pdata, u32 intid) +{ + wr32_mem(pdata, 1, MSIX_TBL_MASK + intid * 16); +} + +static void fxgmac_enable_mgm_irq(struct fxgmac_pdata *pdata) +{ + u32 val = 0; + + fxgmac_set_bits(&val, MGMT_INT_CTRL0_INT_MASK_POS, + MGMT_INT_CTRL0_INT_MASK_LEN, + MGMT_INT_CTRL0_INT_MASK_DISABLE); + wr32_mem(pdata, val, MGMT_INT_CTRL0); +} + +static void fxgmac_disable_mgm_irq(struct fxgmac_pdata *pdata) +{ + u32 val = 0; + + fxgmac_set_bits(&val, MGMT_INT_CTRL0_INT_MASK_POS, + MGMT_INT_CTRL0_INT_MASK_LEN, + MGMT_INT_CTRL0_INT_MASK_MASK); + wr32_mem(pdata, val, MGMT_INT_CTRL0); +} + +static int fxgmac_flush_tx_queues(struct fxgmac_pdata *pdata) +{ + u32 val, count; + + val = rd32_mac(pdata, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); + fxgmac_set_bits(&val, MTL_Q_TQOMR_FTQ_POS, MTL_Q_TQOMR_FTQ_LEN, + 1); + wr32_mac(pdata, val, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); + + count = 2000; + do { + fsleep(20); + val = rd32_mac(pdata, FXGMAC_MTL_REG(0, MTL_Q_TQOMR)); + val = FXGMAC_GET_BITS(val, MTL_Q_TQOMR_FTQ_POS, + MTL_Q_TQOMR_FTQ_LEN); + + } while (--count && val); + + if (val) + return -EBUSY; + + return 0; +} + +static void fxgmac_config_dma_bus(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mac(pdata, DMA_SBMR); + /* Set enhanced addressing mode */ + fxgmac_set_bits(&val, DMA_SBMR_EAME_POS, DMA_SBMR_EAME_LEN, 1); + + /* Out standing read/write requests */ + fxgmac_set_bits(&val, DMA_SBMR_RD_OSR_LMT_POS, DMA_SBMR_RD_OSR_LMT_LEN, + 0x7); + fxgmac_set_bits(&val, DMA_SBMR_WR_OSR_LMT_POS, DMA_SBMR_WR_OSR_LMT_LEN, + 0x7); + + /* Set the System Bus mode */ + fxgmac_set_bits(&val, DMA_SBMR_FB_POS, DMA_SBMR_FB_LEN, 0); + fxgmac_set_bits(&val, DMA_SBMR_BLEN_4_POS, DMA_SBMR_BLEN_4_LEN, 1); + fxgmac_set_bits(&val, DMA_SBMR_BLEN_8_POS, DMA_SBMR_BLEN_8_LEN, 1); + fxgmac_set_bits(&val, DMA_SBMR_BLEN_16_POS, DMA_SBMR_BLEN_16_LEN, 1); + fxgmac_set_bits(&val, DMA_SBMR_BLEN_32_POS, DMA_SBMR_BLEN_32_LEN, 1); + wr32_mac(pdata, val, DMA_SBMR); +} + +static int fxgmac_phy_clear_interrupt(struct fxgmac_pdata *pdata) +{ + u32 stats_pre, stats; + + if (mutex_trylock(&pdata->phydev->mdio.bus->mdio_lock) == 0) { + yt_dbg(pdata, "lock not ready!\n"); + return 0; + } + + stats_pre = fxgmac_phy_read_reg(pdata, PHY_INT_STATUS); + if (stats_pre < 0) + goto unlock; + + stats = fxgmac_phy_read_reg(pdata, PHY_INT_STATUS); + if (stats < 0) + goto unlock; + + phy_unlock_mdio_bus(pdata->phydev); + +#define LINK_DOWN 0x800 +#define LINK_UP 0x400 +#define LINK_CHANGE (LINK_DOWN | LINK_UP) + if ((stats_pre & LINK_CHANGE) != (stats & LINK_CHANGE)) { + yt_dbg(pdata, "phy link change\n"); + return 1; + } + + return 0; +unlock: + phy_unlock_mdio_bus(pdata->phydev); + yt_err(pdata, "fxgmac_phy_read_reg err!\n"); + return -ETIMEDOUT; +} + +#define FXGMAC_WOL_WAIT_2_MS 2 + +static void fxgmac_config_wol_wait_time(struct fxgmac_pdata *pdata) +{ + u32 val; + + val = rd32_mem(pdata, WOL_CTRL); + fxgmac_set_bits(&val, WOL_WAIT_TIME_POS, WOL_WAIT_TIME_LEN, + FXGMAC_WOL_WAIT_2_MS); + wr32_mem(pdata, val, WOL_CTRL); +} + +static void fxgmac_desc_rx_channel_init(struct fxgmac_channel *channel) +{ + struct fxgmac_pdata *pdata = channel->pdata; + struct fxgmac_ring *ring = channel->rx_ring; + unsigned int start_index = ring->cur; + struct fxgmac_desc_data *desc_data; + + /* Initialize all descriptors */ + for (u32 i = 0; i < ring->dma_desc_count; i++) { + desc_data = FXGMAC_GET_DESC_DATA(ring, i); + + /* Initialize Rx descriptor */ + fxgmac_desc_rx_reset(desc_data); + } + + /* Update the total number of Rx descriptors */ + wr32_mac(pdata, ring->dma_desc_count - 1, FXGMAC_DMA_REG(channel, DMA_CH_RDRLR)); + + /* Update the starting address of descriptor ring */ + desc_data = FXGMAC_GET_DESC_DATA(ring, start_index); + wr32_mac(pdata, upper_32_bits(desc_data->dma_desc_addr), + FXGMAC_DMA_REG(channel, DMA_CH_RDLR_HI)); + wr32_mac(pdata, lower_32_bits(desc_data->dma_desc_addr), + FXGMAC_DMA_REG(channel, DMA_CH_RDLR_LO)); + + /* Update the Rx Descriptor Tail Pointer */ + desc_data = FXGMAC_GET_DESC_DATA(ring, start_index + + ring->dma_desc_count - 1); + wr32_mac(pdata, lower_32_bits(desc_data->dma_desc_addr), + FXGMAC_DMA_REG(channel, DMA_CH_RDTR_LO)); +} + +static void fxgmac_desc_rx_init(struct fxgmac_pdata *pdata) +{ + struct fxgmac_desc_data *desc_data; + struct fxgmac_dma_desc *dma_desc; + struct fxgmac_channel *channel; + dma_addr_t dma_desc_addr; + struct fxgmac_ring *ring; + + channel = pdata->channel_head; + for (u32 i = 0; i < pdata->channel_count; i++, channel++) { + ring = channel->rx_ring; + dma_desc = ring->dma_desc_head; + dma_desc_addr = ring->dma_desc_head_addr; + + for (u32 j = 0; j < ring->dma_desc_count; j++) { + desc_data = FXGMAC_GET_DESC_DATA(ring, j); + desc_data->dma_desc = dma_desc; + desc_data->dma_desc_addr = dma_desc_addr; + + if (fxgmac_rx_buffe_map(pdata, ring, desc_data)) + break; + + dma_desc++; + dma_desc_addr += sizeof(struct fxgmac_dma_desc); + } + + ring->cur = 0; + ring->dirty = 0; + + fxgmac_desc_rx_channel_init(channel); + } +} + +static void fxgmac_desc_tx_channel_init(struct fxgmac_channel *channel) +{ + struct fxgmac_pdata *pdata = channel->pdata; + struct fxgmac_ring *ring = channel->tx_ring; + struct fxgmac_desc_data *desc_data; + int start_index = ring->cur; + + /* Initialize all descriptors */ + for (u32 i = 0; i < ring->dma_desc_count; i++) { + desc_data = FXGMAC_GET_DESC_DATA(ring, i); + fxgmac_desc_tx_reset(desc_data); /* Initialize Tx descriptor */ + } + + /* Update the total number of Tx descriptors */ + wr32_mac(pdata, channel->pdata->tx_desc_count - 1, + FXGMAC_DMA_REG(channel, DMA_CH_TDRLR)); + + /* Update the starting address of descriptor ring */ + desc_data = FXGMAC_GET_DESC_DATA(ring, start_index); + wr32_mac(pdata, upper_32_bits(desc_data->dma_desc_addr), + FXGMAC_DMA_REG(channel, DMA_CH_TDLR_HI)); + wr32_mac(pdata, lower_32_bits(desc_data->dma_desc_addr), + FXGMAC_DMA_REG(channel, DMA_CH_TDLR_LO)); +} + +static void fxgmac_desc_tx_init(struct fxgmac_pdata *pdata) +{ + struct fxgmac_desc_data *desc_data; + struct fxgmac_dma_desc *dma_desc; + struct fxgmac_channel *channel; + dma_addr_t dma_desc_addr; + struct fxgmac_ring *ring; + + channel = pdata->channel_head; + channel->tx_timer_active = 0; /* reset the tx timer status. */ + ring = channel->tx_ring; + dma_desc = ring->dma_desc_head; + dma_desc_addr = ring->dma_desc_head_addr; + + for (u32 j = 0; j < ring->dma_desc_count; j++) { + desc_data = FXGMAC_GET_DESC_DATA(ring, j); + desc_data->dma_desc = dma_desc; + desc_data->dma_desc_addr = dma_desc_addr; + + dma_desc++; + dma_desc_addr += sizeof(struct fxgmac_dma_desc); + } + + ring->cur = 0; + ring->dirty = 0; + memset(&ring->tx, 0, sizeof(ring->tx)); + fxgmac_desc_tx_channel_init(pdata->channel_head); +} + +static int fxgmac_hw_init(struct fxgmac_pdata *pdata) +{ + int ret; + + /* Flush Tx queues */ + ret = fxgmac_flush_tx_queues(pdata); + if (ret < 0) { + yt_err(pdata, "%s, flush tx queue err:%d\n", __func__, ret); + return ret; + } + + /* Initialize DMA related features */ + fxgmac_config_dma_bus(pdata); + fxgmac_config_osp_mode(pdata); + fxgmac_config_pblx8(pdata); + fxgmac_config_tx_pbl_val(pdata); + fxgmac_config_rx_pbl_val(pdata); + fxgmac_config_rx_coalesce(pdata); + fxgmac_config_rx_buffer_size(pdata); + fxgmac_config_tso_mode(pdata); + fxgmac_config_sph_mode(pdata); + fxgmac_config_rss(pdata); + + fxgmac_desc_tx_init(pdata); + fxgmac_desc_rx_init(pdata); + fxgmac_enable_dma_interrupts(pdata); + + /* Initialize MTL related features */ + fxgmac_config_mtl_mode(pdata); + fxgmac_config_queue_mapping(pdata); + fxgmac_config_tsf_mode(pdata, pdata->tx_sf_mode); + fxgmac_config_rsf_mode(pdata, pdata->rx_sf_mode); + fxgmac_config_tx_threshold(pdata, pdata->tx_threshold); + fxgmac_config_rx_threshold(pdata, pdata->rx_threshold); + fxgmac_config_tx_fifo_size(pdata); + fxgmac_config_rx_fifo_size(pdata); + fxgmac_config_flow_control_threshold(pdata); + fxgmac_config_rx_fep_disable(pdata); + fxgmac_config_rx_fup_enable(pdata); + fxgmac_enable_mtl_interrupts(pdata); + + /* Initialize MAC related features */ + fxgmac_config_mac_address(pdata); + fxgmac_config_crc_check(pdata); + fxgmac_config_rx_mode(pdata); + fxgmac_config_jumbo(pdata); + ret = fxgmac_config_flow_control(pdata); + if (ret < 0) { + yt_err(pdata, "%s, fxgmac_config_flow_control err:%d\n", + __func__, ret); + return ret; + } + + fxgmac_config_mac_speed(pdata); + fxgmac_config_checksum_offload(pdata); + fxgmac_config_vlan_support(pdata); + fxgmac_config_mmc(pdata); + fxgmac_enable_mac_interrupts(pdata); + fxgmac_config_wol_wait_time(pdata); + + ret = fxgmac_phy_irq_enable(pdata, true); + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "%s ok\n", __func__); + + return ret; +} + +static void fxgmac_save_nonstick_reg(struct fxgmac_pdata *pdata) +{ + for (u32 i = GLOBAL_CTRL0; i < MSI_PBA; i += 4) { + pdata->reg_nonstick[(i - GLOBAL_CTRL0) >> 2] = + rd32_mem(pdata, i); + } +} + +static void fxgmac_restore_nonstick_reg(struct fxgmac_pdata *pdata) +{ + for (u32 i = GLOBAL_CTRL0; i < MSI_PBA; i += 4) + wr32_mem(pdata, pdata->reg_nonstick[(i - GLOBAL_CTRL0) >> 2], + i); +} + +static void fxgmac_hw_exit(struct fxgmac_pdata *pdata) +{ + u32 val = 0; + + /* Issue a CHIP reset, + * it will reset trigger circuit and reload efuse patch + */ + val = rd32_mem(pdata, SYS_RESET); + yt_dbg(pdata, "CHIP_RESET 0x%x\n", val); + fxgmac_set_bits(&val, SYS_RESET_POS, SYS_RESET_LEN, 1); + wr32_mem(pdata, val, SYS_RESET); + fsleep(9000); + + fxgmac_phy_release(pdata); + + /* Reset will clear nonstick registers. */ + fxgmac_restore_nonstick_reg(pdata); +} + +static void fxgmac_pcie_init(struct fxgmac_pdata *pdata) +{ + u32 val = 0; + + fxgmac_set_bits(&val, LTR_IDLE_ENTER_REQUIRE_POS, + LTR_IDLE_ENTER_REQUIRE_LEN, LTR_IDLE_ENTER_REQUIRE); + fxgmac_set_bits(&val, LTR_IDLE_ENTER_SCALE_POS, + LTR_IDLE_ENTER_SCALE_LEN, LTR_IDLE_ENTER_SCALE_1024_NS); + fxgmac_set_bits(&val, LTR_IDLE_ENTER_POS, LTR_IDLE_ENTER_LEN, + LTR_IDLE_ENTER_900_US); + val = (val << 16) + val; /* snoopy + non-snoopy */ + wr32_mem(pdata, val, LTR_IDLE_ENTER); + + val = 0; + fxgmac_set_bits(&val, LTR_IDLE_EXIT_REQUIRE_POS, + LTR_IDLE_EXIT_REQUIRE_LEN, LTR_IDLE_EXIT_REQUIRE); + fxgmac_set_bits(&val, LTR_IDLE_EXIT_SCALE_POS, LTR_IDLE_EXIT_SCALE_LEN, + LTR_IDLE_EXIT_SCALE); + fxgmac_set_bits(&val, LTR_IDLE_EXIT_POS, LTR_IDLE_EXIT_LEN, + LTR_IDLE_EXIT_171_US); + val = (val << 16) + val; /* snoopy + non-snoopy */ + wr32_mem(pdata, val, LTR_IDLE_EXIT); + + val = 0; + fxgmac_set_bits(&val, PCIE_SERDES_PLL_AUTOOFF_POS, + PCIE_SERDES_PLL_AUTOOFF_LEN, 1); + wr32_mem(pdata, val, PCIE_SERDES_PLL); +} + +static void fxgmac_clear_misc_int_status(struct fxgmac_pdata *pdata) +{ + u32 val, i; + + if (fxgmac_phy_clear_interrupt(pdata) == 1) /* Link change */ + phy_mac_interrupt(pdata->phydev); + + /* Clear other interrupt status */ + val = rd32_mac(pdata, MAC_ISR); + if (val) { + if (val & BIT(MAC_ISR_PHYIF_STA_POS)) + rd32_mac(pdata, MAC_PHYIF_STA); + + if (val & (BIT(MAC_ISR_AN_SR0_POS) | BIT(MAC_ISR_AN_SR1_POS) | + BIT(MAC_ISR_AN_SR2_POS))) + rd32_mac(pdata, MAC_AN_SR); + + if (val & BIT(MAC_ISR_PMT_STA_POS)) + rd32_mac(pdata, MAC_PMT_STA); + + if (val & BIT(MAC_ISR_LPI_STA_POS)) + rd32_mac(pdata, MAC_LPI_STA); + + if (val & BIT(MAC_ISR_MMC_STA_POS)) { + if (val & BIT(MAC_ISR_RX_MMC_STA_POS)) + fxgmac_rx_mmc_int(pdata); + + if (val & BIT(MAC_ISR_TX_MMC_STA_POS)) + fxgmac_tx_mmc_int(pdata); + + if (val & BIT(MAC_ISR_IPCRXINT_POS)) + rd32_mac(pdata, MMC_IPCRXINT); + } + + if (val & + (BIT(MAC_ISR_TX_RX_STA0_POS) | BIT(MAC_ISR_TX_RX_STA1_POS))) + rd32_mac(pdata, MAC_TX_RX_STA); + + if (val & BIT(MAC_ISR_GPIO_SR_POS)) + rd32_mac(pdata, MAC_GPIO_SR); + } + + /* MTL_Interrupt_Status, write 1 clear */ + val = rd32_mac(pdata, MTL_INT_SR); + if (val) + wr32_mac(pdata, val, MTL_INT_SR); + + /* MTL_Q(#i)_Interrupt_Control_Status, write 1 clear */ + for (i = 0; i < pdata->hw_feat.rx_q_cnt; i++) { + /* Clear all the interrupts which are set */ + val = rd32_mac(pdata, MTL_Q_INT_CTL_SR + i * MTL_Q_INC); + if (val) + wr32_mac(pdata, val, MTL_Q_INT_CTL_SR + i * MTL_Q_INC); + } + + /* MTL_ECC_Interrupt_Status, write 1 clear */ + val = rd32_mac(pdata, MTL_ECC_INT_SR); + if (val) + wr32_mac(pdata, val, MTL_ECC_INT_SR); + + /* DMA_ECC_Interrupt_Status, write 1 clear */ + val = rd32_mac(pdata, DMA_ECC_INT_SR); + if (val) + wr32_mac(pdata, val, DMA_ECC_INT_SR); +} + +void fxgmac_hw_ops_init(struct fxgmac_hw_ops *hw_ops) +{ + hw_ops->pcie_init = fxgmac_pcie_init; + hw_ops->init = fxgmac_hw_init; + hw_ops->exit = fxgmac_hw_exit; + hw_ops->save_nonstick_reg = fxgmac_save_nonstick_reg; + hw_ops->restore_nonstick_reg = fxgmac_restore_nonstick_reg; + + hw_ops->enable_tx = fxgmac_enable_tx; + hw_ops->disable_tx = fxgmac_disable_tx; + hw_ops->enable_rx = fxgmac_enable_rx; + hw_ops->disable_rx = fxgmac_disable_rx; + + hw_ops->enable_channel_irq = fxgmac_enable_channel_irq; + hw_ops->disable_channel_irq = fxgmac_disable_channel_irq; + hw_ops->set_interrupt_moderation = fxgmac_set_interrupt_moderation; + hw_ops->enable_msix_one_irq = fxgmac_enable_msix_one_irq; + hw_ops->disable_msix_one_irq = fxgmac_disable_msix_one_irq; + hw_ops->enable_mgm_irq = fxgmac_enable_mgm_irq; + hw_ops->disable_mgm_irq = fxgmac_disable_mgm_irq; + + hw_ops->dismiss_all_int = fxgmac_dismiss_all_int; + hw_ops->clear_misc_int_status = fxgmac_clear_misc_int_status; + + hw_ops->set_mac_address = fxgmac_set_mac_address; + hw_ops->set_mac_hash = fxgmac_set_mc_addresses; + hw_ops->config_rx_mode = fxgmac_config_rx_mode; + hw_ops->enable_rx_csum = fxgmac_enable_rx_csum; + hw_ops->disable_rx_csum = fxgmac_disable_rx_csum; + hw_ops->config_tso = fxgmac_config_tso_mode; + hw_ops->calculate_max_checksum_size = + fxgmac_calculate_max_checksum_size; + hw_ops->config_mac_speed = fxgmac_config_mac_speed; + + /* PHY Control */ + hw_ops->reset_phy = fxgmac_phy_reset; + hw_ops->release_phy = fxgmac_phy_release; + hw_ops->write_phy_reg = fxgmac_phy_write_reg; + hw_ops->read_phy_reg = fxgmac_phy_read_reg; + + /* Vlan related config */ + hw_ops->enable_rx_vlan_stripping = fxgmac_enable_rx_vlan_stripping; + hw_ops->disable_rx_vlan_stripping = fxgmac_disable_rx_vlan_stripping; + hw_ops->enable_rx_vlan_filtering = fxgmac_enable_rx_vlan_filtering; + hw_ops->disable_rx_vlan_filtering = fxgmac_disable_rx_vlan_filtering; + hw_ops->update_vlan_hash_table = fxgmac_update_vlan_hash_table; + + /* RX coalescing */ + hw_ops->config_rx_coalesce = fxgmac_config_rx_coalesce; + hw_ops->usec_to_riwt = fxgmac_usec_to_riwt; + /* Receive Side Scaling */ + hw_ops->enable_rss = fxgmac_enable_rss; + hw_ops->disable_rss = fxgmac_disable_rss; + hw_ops->get_rss_options = fxgmac_read_rss_options; + hw_ops->set_rss_options = fxgmac_write_rss_options; + hw_ops->set_rss_hash_key = fxgmac_set_rss_hash_key; + hw_ops->write_rss_lookup_table = fxgmac_write_rss_lookup_table; +} -- 2.34.1

driver inclusion category: feature -------------------------------- Implement the fxgmac_init to init hardware settings, including setting function pointers, default configuration data, irq, base_addr, MAC address, DMA mask,device operations and device features. It alseo populates the hardware features, initialize RSS hash key and lookup table and other configure. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> --- .../ethernet/motorcomm/yt6801/yt6801_net.c | 555 ++++++++++++++++++ 1 file changed, 555 insertions(+) diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c index 2033267d9..aa51ecdd7 100644 --- a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c @@ -11,6 +11,7 @@ #include "yt6801_desc.h" #include "yt6801_net.h" +const struct net_device_ops *fxgmac_get_netdev_ops(void); static void fxgmac_napi_enable(struct fxgmac_pdata *pdata); static unsigned int fxgmac_desc_tx_avail(struct fxgmac_ring *ring) @@ -795,6 +796,560 @@ static int fxgmac_open(struct net_device *netdev) return ret; } +#define FXGMAC_SYSCLOCK 125000000 /* System clock is 125 MHz */ + +static void fxgmac_default_config(struct fxgmac_pdata *pdata) +{ + pdata->tx_threshold = MTL_TX_THRESHOLD_128; + pdata->rx_threshold = MTL_RX_THRESHOLD_128; + pdata->tx_osp_mode = DMA_OSP_ENABLE; + pdata->tx_sf_mode = MTL_TSF_ENABLE; + pdata->rx_sf_mode = MTL_RSF_ENABLE; + pdata->pblx8 = DMA_PBL_X8_ENABLE; + pdata->tx_pbl = DMA_PBL_16; + pdata->rx_pbl = DMA_PBL_4; + pdata->crc_check = 1; + pdata->tx_pause = 1; /* Enable tx pause */ + pdata->rx_pause = 1; /* Enable rx pause */ + pdata->intr_mod = 1; + pdata->intr_mod_timer = INT_MOD_200_US; + pdata->vlan_strip = 1; + pdata->rss = 1; + + pdata->phy_autoeng = AUTONEG_ENABLE; + pdata->phy_duplex = DUPLEX_FULL; + pdata->phy_speed = SPEED_1000; + pdata->phy_link = false; + + pdata->sysclk_rate = FXGMAC_SYSCLOCK; + pdata->wol = WAKE_MAGIC; + + strscpy(pdata->drv_name, FXGMAC_DRV_NAME, sizeof(pdata->drv_name)); + strscpy(pdata->drv_ver, FXGMAC_DRV_VERSION, sizeof(pdata->drv_ver)); + yt_dbg(pdata, "drv_name:%s, drv_ver:%s\n", FXGMAC_DRV_NAME, + FXGMAC_DRV_VERSION); +} + +static void fxgmac_get_all_hw_features(struct fxgmac_pdata *pdata) +{ + struct fxgmac_hw_features *hw_feat = &pdata->hw_feat; + unsigned int mac_hfr0, mac_hfr1, mac_hfr2, mac_hfr3; + + mac_hfr0 = rd32_mac(pdata, MAC_HWF0R); + mac_hfr1 = rd32_mac(pdata, MAC_HWF1R); + mac_hfr2 = rd32_mac(pdata, MAC_HWF2R); + mac_hfr3 = rd32_mac(pdata, MAC_HWF3R); + memset(hw_feat, 0, sizeof(*hw_feat)); + hw_feat->version = rd32_mac(pdata, MAC_VR); + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "Mac ver=%#x\n", hw_feat->version); + + /* Hardware feature register 0 */ + hw_feat->phyifsel = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_ACTPHYIFSEL_POS, + MAC_HWF0R_ACTPHYIFSEL_LEN); + hw_feat->vlhash = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_VLHASH_POS, + MAC_HWF0R_VLHASH_LEN); + hw_feat->sma = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_SMASEL_POS, + MAC_HWF0R_SMASEL_LEN); + hw_feat->rwk = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_RWKSEL_POS, + MAC_HWF0R_RWKSEL_LEN); + hw_feat->mgk = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_MGKSEL_POS, + MAC_HWF0R_MGKSEL_LEN); + hw_feat->mmc = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_MMCSEL_POS, + MAC_HWF0R_MMCSEL_LEN); + hw_feat->aoe = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_ARPOFFSEL_POS, + MAC_HWF0R_ARPOFFSEL_LEN); + hw_feat->ts = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_TSSEL_POS, + MAC_HWF0R_TSSEL_LEN); + hw_feat->eee = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_EEESEL_POS, + MAC_HWF0R_EEESEL_LEN); + hw_feat->tx_coe = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_TXCOESEL_POS, + MAC_HWF0R_TXCOESEL_LEN); + hw_feat->rx_coe = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_RXCOESEL_POS, + MAC_HWF0R_RXCOESEL_LEN); + hw_feat->addn_mac = FXGMAC_GET_BITS(mac_hfr0, + MAC_HWF0R_ADDMACADRSEL_POS, + MAC_HWF0R_ADDMACADRSEL_LEN); + hw_feat->ts_src = FXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R_TSSTSSEL_POS, + MAC_HWF0R_TSSTSSEL_LEN); + hw_feat->sa_vlan_ins = FXGMAC_GET_BITS(mac_hfr0, + MAC_HWF0R_SAVLANINS_POS, + MAC_HWF0R_SAVLANINS_LEN); + + /* Hardware feature register 1 */ + hw_feat->rx_fifo_size = FXGMAC_GET_BITS(mac_hfr1, + MAC_HWF1R_RXFIFOSIZE_POS, + MAC_HWF1R_RXFIFOSIZE_LEN); + hw_feat->tx_fifo_size = FXGMAC_GET_BITS(mac_hfr1, + MAC_HWF1R_TXFIFOSIZE_POS, + MAC_HWF1R_TXFIFOSIZE_LEN); + hw_feat->adv_ts_hi = FXGMAC_GET_BITS(mac_hfr1, + MAC_HWF1R_ADVTHWORD_POS, + MAC_HWF1R_ADVTHWORD_LEN); + hw_feat->dma_width = FXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R_ADDR64_POS, + MAC_HWF1R_ADDR64_LEN); + hw_feat->dcb = FXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R_DCBEN_POS, + MAC_HWF1R_DCBEN_LEN); + hw_feat->sph = FXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R_SPHEN_POS, + MAC_HWF1R_SPHEN_LEN); + hw_feat->tso = FXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R_TSOEN_POS, + MAC_HWF1R_TSOEN_LEN); + hw_feat->dma_debug = FXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R_DBGMEMA_POS, + MAC_HWF1R_DBGMEMA_LEN); + hw_feat->avsel = FXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R_RAVSEL_POS, + MAC_HWF1R_RAVSEL_LEN); + hw_feat->ravsel = FXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R_RAVSEL_POS, + MAC_HWF1R_RAVSEL_LEN); + hw_feat->hash_table_size = FXGMAC_GET_BITS(mac_hfr1, + MAC_HWF1R_HASHTBLSZ_POS, + MAC_HWF1R_HASHTBLSZ_LEN); + hw_feat->l3l4_filter_num = FXGMAC_GET_BITS(mac_hfr1, + MAC_HWF1R_L3L4FNUM_POS, + MAC_HWF1R_L3L4FNUM_LEN); + hw_feat->tx_q_cnt = FXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R_TXQCNT_POS, + MAC_HWF2R_TXQCNT_LEN); + hw_feat->rx_ch_cnt = FXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R_RXCHCNT_POS, + MAC_HWF2R_RXCHCNT_LEN); + hw_feat->tx_ch_cnt = FXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R_TXCHCNT_POS, + MAC_HWF2R_TXCHCNT_LEN); + hw_feat->pps_out_num = FXGMAC_GET_BITS(mac_hfr2, + MAC_HWF2R_PPSOUTNUM_POS, + MAC_HWF2R_PPSOUTNUM_LEN); + hw_feat->aux_snap_num = FXGMAC_GET_BITS(mac_hfr2, + MAC_HWF2R_AUXSNAPNUM_POS, + MAC_HWF2R_AUXSNAPNUM_LEN); + + /* Translate the Hash Table size into actual number */ + switch (hw_feat->hash_table_size) { + case 0: + break; + case 1: + hw_feat->hash_table_size = 64; + break; + case 2: + hw_feat->hash_table_size = 128; + break; + case 3: + hw_feat->hash_table_size = 256; + break; + } + + /* Translate the address width setting into actual number */ + switch (hw_feat->dma_width) { + case 0: + hw_feat->dma_width = 32; + break; + case 1: + hw_feat->dma_width = 40; + break; + case 2: + hw_feat->dma_width = 48; + break; + default: + hw_feat->dma_width = 32; + } + + /* The Queue, Channel are zero based so increment them + * to get the actual number + */ + hw_feat->tx_q_cnt++; + hw_feat->rx_ch_cnt++; + hw_feat->tx_ch_cnt++; + + /* HW implement 1 rx fifo, 4 dma channel. but from software + * we see 4 logical queues. hardcode to 4 queues. + */ + hw_feat->rx_q_cnt = 4; + + hw_feat->hwfr3 = mac_hfr3; +} + +static void fxgmac_print_all_hw_features(struct fxgmac_pdata *pdata) +{ + char *str; + + yt_dbg(pdata, "\n"); + yt_dbg(pdata, "====================================================\n"); + yt_dbg(pdata, "\n"); + yt_dbg(pdata, "HW support following feature\n"); + yt_dbg(pdata, "\n"); + + /* HW Feature Register0 */ + yt_dbg(pdata, "VLAN Hash Filter Selected : %s\n", + pdata->hw_feat.vlhash ? "YES" : "NO"); + yt_dbg(pdata, "SMA (MDIO) Interface : %s\n", + pdata->hw_feat.sma ? "YES" : "NO"); + yt_dbg(pdata, "PMT Remote Wake-up Packet Enable : %s\n", + pdata->hw_feat.rwk ? "YES" : "NO"); + yt_dbg(pdata, "PMT Magic Packet Enable : %s\n", + pdata->hw_feat.mgk ? "YES" : "NO"); + yt_dbg(pdata, "RMON/MMC Module Enable : %s\n", + pdata->hw_feat.mmc ? "YES" : "NO"); + yt_dbg(pdata, "ARP Offload Enabled : %s\n", + pdata->hw_feat.aoe ? "YES" : "NO"); + yt_dbg(pdata, "IEEE 1588-2008 Timestamp Enabled : %s\n", + pdata->hw_feat.ts ? "YES" : "NO"); + yt_dbg(pdata, "Energy Efficient Ethernet Enabled : %s\n", + pdata->hw_feat.eee ? "YES" : "NO"); + yt_dbg(pdata, "Transmit Checksum Offload Enabled : %s\n", + pdata->hw_feat.tx_coe ? "YES" : "NO"); + yt_dbg(pdata, "Receive Checksum Offload Enabled : %s\n", + pdata->hw_feat.rx_coe ? "YES" : "NO"); + yt_dbg(pdata, "Additional MAC Addresses 1-31 Selected : %s\n", + pdata->hw_feat.addn_mac ? "YES" : "NO"); + + switch (pdata->hw_feat.ts_src) { + case 0: + str = "RESERVED"; + break; + case 1: + str = "INTERNAL"; + break; + case 2: + str = "EXTERNAL"; + break; + case 3: + str = "BOTH"; + break; + } + yt_dbg(pdata, "Timestamp System Time Source : %s\n", + str); + yt_dbg(pdata, "Source Address or VLAN Insertion Enable : %s\n", + pdata->hw_feat.sa_vlan_ins ? "YES" : "NO"); + + /* HW Feature Register1 */ + switch (pdata->hw_feat.rx_fifo_size) { + case 0: + str = "128 bytes"; + break; + case 1: + str = "256 bytes"; + break; + case 2: + str = "512 bytes"; + break; + case 3: + str = "1 KBytes"; + break; + case 4: + str = "2 KBytes"; + break; + case 5: + str = "4 KBytes"; + break; + case 6: + str = "8 KBytes"; + break; + case 7: + str = "16 KBytes"; + break; + case 8: + str = "32 kBytes"; + break; + case 9: + str = "64 KBytes"; + break; + case 10: + str = "128 KBytes"; + break; + case 11: + str = "256 KBytes"; + break; + default: + str = "RESERVED"; + } + yt_dbg(pdata, "MTL Receive FIFO Size : %s\n", + str); + + switch (pdata->hw_feat.tx_fifo_size) { + case 0: + str = "128 bytes"; + break; + case 1: + str = "256 bytes"; + break; + case 2: + str = "512 bytes"; + break; + case 3: + str = "1 KBytes"; + break; + case 4: + str = "2 KBytes"; + break; + case 5: + str = "4 KBytes"; + break; + case 6: + str = "8 KBytes"; + break; + case 7: + str = "16 KBytes"; + break; + case 8: + str = "32 kBytes"; + break; + case 9: + str = "64 KBytes"; + break; + case 10: + str = "128 KBytes"; + break; + case 11: + str = "256 KBytes"; + break; + default: + str = "RESERVED"; + } + yt_dbg(pdata, "MTL Transmit FIFO Size : %s\n", + str); + yt_dbg(pdata, "IEEE 1588 High Word Register Enable : %s\n", + pdata->hw_feat.adv_ts_hi ? "YES" : "NO"); + yt_dbg(pdata, "Address width : %u\n", + pdata->hw_feat.dma_width); + yt_dbg(pdata, "DCB Feature Enable : %s\n", + pdata->hw_feat.dcb ? "YES" : "NO"); + yt_dbg(pdata, "Split Header Feature Enable : %s\n", + pdata->hw_feat.sph ? "YES" : "NO"); + yt_dbg(pdata, "TCP Segmentation Offload Enable : %s\n", + pdata->hw_feat.tso ? "YES" : "NO"); + yt_dbg(pdata, "DMA Debug Registers Enabled : %s\n", + pdata->hw_feat.dma_debug ? "YES" : "NO"); + yt_dbg(pdata, "RSS Feature Enabled : %s\n", + "YES"); + yt_dbg(pdata, "AV Feature Enabled : %s\n", + pdata->hw_feat.avsel ? "YES" : "NO"); + yt_dbg(pdata, "Rx Side Only AV Feature Enabled : %s\n", + (pdata->hw_feat.ravsel ? "YES" : "NO")); + yt_dbg(pdata, "Hash Table Size : %u\n", + pdata->hw_feat.hash_table_size); + yt_dbg(pdata, "Total number of L3 or L4 Filters : %u\n", + pdata->hw_feat.l3l4_filter_num); + + /* HW Feature Register2 */ + yt_dbg(pdata, "Number of MTL Receive Queues : %u\n", + pdata->hw_feat.rx_q_cnt); + yt_dbg(pdata, "Number of MTL Transmit Queues : %u\n", + pdata->hw_feat.tx_q_cnt); + yt_dbg(pdata, "Number of DMA Receive Channels : %u\n", + pdata->hw_feat.rx_ch_cnt); + yt_dbg(pdata, "Number of DMA Transmit Channels : %u\n", + pdata->hw_feat.tx_ch_cnt); + + switch (pdata->hw_feat.pps_out_num) { + case 0: + str = "No PPS output"; + break; + case 1: + str = "1 PPS output"; + break; + case 2: + str = "2 PPS output"; + break; + case 3: + str = "3 PPS output"; + break; + case 4: + str = "4 PPS output"; + break; + default: + str = "RESERVED"; + } + yt_dbg(pdata, "Number of PPS Outputs : %s\n", + str); + + switch (pdata->hw_feat.aux_snap_num) { + case 0: + str = "No auxiliary input"; + break; + case 1: + str = "1 auxiliary input"; + break; + case 2: + str = "2 auxiliary input"; + break; + case 3: + str = "3 auxiliary input"; + break; + case 4: + str = "4 auxiliary input"; + break; + default: + str = "RESERVED"; + } + yt_dbg(pdata, "Number of Auxiliary Snapshot Inputs : %s\n", + str); + + yt_dbg(pdata, "\n"); + yt_dbg(pdata, "====================================================\n"); + yt_dbg(pdata, "\n"); +} + +static int fxgmac_init(struct fxgmac_pdata *pdata, bool save_private_reg) +{ + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + struct net_device *netdev = pdata->netdev; + int ret; + + fxgmac_hw_ops_init(hw_ops); /* Set hw the function pointers */ + fxgmac_default_config(pdata); /* Set default configuration data */ + + /* Set irq, base_addr, MAC address */ + netdev->irq = pdata->dev_irq; + netdev->base_addr = (unsigned long)pdata->hw_addr; + + ret = fxgmac_read_mac_addr(pdata); + if (ret) { + yt_err(pdata, "fxgmac_read_mac_addr err:%d\n", ret); + return ret; + } + eth_hw_addr_set(netdev, pdata->mac_addr); + + if (save_private_reg) + hw_ops->save_nonstick_reg(pdata); + + hw_ops->exit(pdata); /* Reset here to get hw features correctly */ + + /* Populate the hardware features */ + fxgmac_get_all_hw_features(pdata); + fxgmac_print_all_hw_features(pdata); + + /* Set the DMA mask */ + ret = dma_set_mask_and_coherent(pdata->dev, + DMA_BIT_MASK(pdata->hw_feat.dma_width)); + if (ret) { + yt_err(pdata, "dma_set_mask_and_coherent err:%d\n", ret); + return ret; + } + if (pdata->int_flags & FXGMAC_FLAG_LEGACY_ENABLED) { + /* We should disable msi and msix here when we use legacy + * interrupt,for two reasons: + * 1. Exit will restore msi and msix config regisiter, + * that may enable them. + * 2. When the driver that uses the msix interrupt by default + * is compiled into the OS, uninstall the driver through rmmod, + * and then install the driver that uses the legacy interrupt, + * at which time the msix enable will be turned on again by + * default after waking up from S4 on some + * platform. such as UOS platform. + */ + pci_disable_msi(to_pci_dev(pdata->dev)); + pci_disable_msix(to_pci_dev(pdata->dev)); + } + + BUILD_BUG_ON_NOT_POWER_OF_2(FXGMAC_TX_DESC_CNT); + pdata->tx_desc_count = FXGMAC_TX_DESC_CNT; + BUILD_BUG_ON_NOT_POWER_OF_2(FXGMAC_RX_DESC_CNT); + pdata->rx_desc_count = FXGMAC_RX_DESC_CNT; + + ret = netif_set_real_num_tx_queues(netdev, FXGMAC_TX_1_Q); + yt_dbg(pdata, + "num_online_cpus:%u, tx:ch_cnt:%u, q_cnt:%u, ring_count:%u\n", + num_online_cpus(), pdata->hw_feat.tx_ch_cnt, + pdata->hw_feat.tx_q_cnt, FXGMAC_TX_1_RING); + if (ret) { + yt_err(pdata, "error setting real tx queue count\n"); + return ret; + } + + pdata->rx_ring_count = min_t(unsigned int, + netif_get_num_default_rss_queues(), + pdata->hw_feat.rx_ch_cnt); + pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count, + pdata->hw_feat.rx_q_cnt); + pdata->rx_q_count = pdata->rx_ring_count; + ret = netif_set_real_num_rx_queues(netdev, pdata->rx_q_count); + if (ret) { + yt_err(pdata, "error setting real rx queue count\n"); + return ret; + } + + pdata->channel_count = + max_t(unsigned int, FXGMAC_TX_1_RING, pdata->rx_ring_count); + + yt_dbg(pdata, + "default rss queues:%u, rx:ch_cnt:%u, q_cnt:%u, ring_count:%u, channel_count:%u, netdev tx channel_num=%u\n", + netif_get_num_default_rss_queues(), pdata->hw_feat.rx_ch_cnt, + pdata->hw_feat.rx_q_cnt, pdata->rx_ring_count, + pdata->channel_count, netdev->real_num_tx_queues); + + /* Initialize RSS hash key and lookup table */ + netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key)); + + for (u32 i = 0; i < FXGMAC_RSS_MAX_TABLE_SIZE; i++) { + fxgmac_set_bits(&pdata->rss_table[i], MAC_RSSDR_DMCH_POS, + MAC_RSSDR_DMCH_LEN, i % pdata->rx_ring_count); + } + + pdata->rss_options |= FXGMAC_RSS_IP4TE | FXGMAC_RSS_TCP4TE | + FXGMAC_RSS_UDP4TE; + + netdev->min_mtu = ETH_MIN_MTU; + netdev->max_mtu = + FXGMAC_JUMBO_PACKET_MTU + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); + + yt_dbg(pdata, "rss_options:0x%x\n", pdata->rss_options); + + /* Set device operations */ + netdev->netdev_ops = fxgmac_get_netdev_ops(); + netdev->ethtool_ops = fxgmac_get_ethtool_ops(); + + /* Set device features */ + if (pdata->hw_feat.tso) { + netdev->hw_features = NETIF_F_TSO; + netdev->hw_features |= NETIF_F_TSO6; + netdev->hw_features |= NETIF_F_SG; + netdev->hw_features |= NETIF_F_IP_CSUM; + netdev->hw_features |= NETIF_F_IPV6_CSUM; + } else if (pdata->hw_feat.tx_coe) { + netdev->hw_features = NETIF_F_IP_CSUM; + netdev->hw_features |= NETIF_F_IPV6_CSUM; + } + + if (pdata->hw_feat.rx_coe) { + netdev->hw_features |= NETIF_F_RXCSUM; + netdev->hw_features |= NETIF_F_GRO; + } + + netdev->hw_features |= NETIF_F_RXHASH; + netdev->vlan_features |= netdev->hw_features; + + netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; + + if (pdata->hw_feat.sa_vlan_ins) + netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; + + netdev->features |= netdev->hw_features; + pdata->netdev_features = netdev->features; + + netdev->priv_flags |= IFF_UNICAST_FLT; + netdev->watchdog_timeo = msecs_to_jiffies(5000); + +#define NIC_MAX_TCP_OFFLOAD_SIZE 7300 + + netif_set_tso_max_size(netdev, NIC_MAX_TCP_OFFLOAD_SIZE); + +/* Default coalescing parameters */ +#define FXGMAC_INIT_DMA_TX_USECS INT_MOD_200_US +#define FXGMAC_INIT_DMA_TX_FRAMES 25 +#define FXGMAC_INIT_DMA_RX_USECS INT_MOD_200_US +#define FXGMAC_INIT_DMA_RX_FRAMES 25 + + /* Tx coalesce parameters initialization */ + pdata->tx_usecs = FXGMAC_INIT_DMA_TX_USECS; + pdata->tx_frames = FXGMAC_INIT_DMA_TX_FRAMES; + + /* Rx coalesce parameters initialization */ + pdata->rx_riwt = hw_ops->usec_to_riwt(pdata, FXGMAC_INIT_DMA_RX_USECS); + pdata->rx_usecs = FXGMAC_INIT_DMA_RX_USECS; + pdata->rx_frames = FXGMAC_INIT_DMA_RX_FRAMES; + + mutex_init(&pdata->mutex); + yt_dbg(pdata, "%s ok.\n", __func__); + + return 0; +} + #ifdef CONFIG_PCI_MSI static void fxgmac_init_interrupt_scheme(struct fxgmac_pdata *pdata) { -- 2.34.1

driver inclusion category: feature -------------------------------- Implement the pci_driver shutdown function to shutdown this driver. Signed-off-by: Frank Sae <Frank.Sae@motor-comm.com> --- .../net/ethernet/motorcomm/yt6801/yt6801.h | 617 ++++++++++++++++++ .../ethernet/motorcomm/yt6801/yt6801_desc.c | 49 ++ .../ethernet/motorcomm/yt6801/yt6801_desc.h | 39 ++ .../ethernet/motorcomm/yt6801/yt6801_net.c | 251 +++++++ .../ethernet/motorcomm/yt6801/yt6801_net.h | 32 + .../ethernet/motorcomm/yt6801/yt6801_pci.c | 26 + 6 files changed, 1014 insertions(+) create mode 100644 drivers/net/ethernet/motorcomm/yt6801/yt6801.h create mode 100644 drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.c create mode 100644 drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.h create mode 100644 drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c create mode 100644 drivers/net/ethernet/motorcomm/yt6801/yt6801_net.h diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801.h b/drivers/net/ethernet/motorcomm/yt6801/yt6801.h new file mode 100644 index 000000000..d06457f57 --- /dev/null +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801.h @@ -0,0 +1,617 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2022 - 2024 Motorcomm Electronic Technology Co.,Ltd. */ + +#ifndef YT6801_H +#define YT6801_H + +#include <linux/dma-mapping.h> +#include <linux/timecounter.h> +#include <linux/pm_wakeup.h> +#include <linux/workqueue.h> +#include <linux/crc32poly.h> +#include <linux/if_vlan.h> +#include <linux/bitrev.h> +#include <linux/bitops.h> +#include <linux/mdio.h> +#include <linux/phy.h> + +#ifdef CONFIG_PCI_MSI +#include <linux/pci.h> +#endif + +#include "yt6801_type.h" + +#define FXGMAC_DRV_VERSION "1.0.29" +#define FXGMAC_DRV_NAME "yt6801" +#define FXGMAC_DRV_DESC "Motorcomm Gigabit Ethernet Driver" + +#define FXGMAC_RX_BUF_ALIGN 64 +#define FXGMAC_TX_MAX_BUF_SIZE (0x3fff & ~(FXGMAC_RX_BUF_ALIGN - 1)) +#define FXGMAC_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN) + +/* Descriptors required for maximum contiguous TSO/GSO packet */ +#define FXGMAC_TX_MAX_SPLIT ((GSO_MAX_SIZE / FXGMAC_TX_MAX_BUF_SIZE) + 1) + +/* Maximum possible descriptors needed for a SKB */ +#define FXGMAC_TX_MAX_DESC_NR (MAX_SKB_FRAGS + FXGMAC_TX_MAX_SPLIT + 2) + +#define FXGMAC_DMA_STOP_TIMEOUT 5 + +/* Receive Side Scaling */ +#define FXGMAC_RSS_HASH_KEY_SIZE 40 +#define FXGMAC_RSS_MAX_TABLE_SIZE 128 +#define FXGMAC_RSS_LOOKUP_TABLE_TYPE 0 +#define FXGMAC_RSS_HASH_KEY_TYPE 1 + +#define FXGMAC_JUMBO_PACKET_MTU 9014 +#define FXGMAC_DATA_WIDTH 128 + +#define FXGMAC_MAX_DMA_RX_CHANNELS 4 +#define FXGMAC_MAX_DMA_TX_CHANNELS 1 +#define FXGMAC_MAX_DMA_CHANNELS \ + (FXGMAC_MAX_DMA_RX_CHANNELS + FXGMAC_MAX_DMA_TX_CHANNELS) + +#define FXGMAC_PHY_INT_NUM 1 +#define FXGMAC_MSIX_INT_NUMS (FXGMAC_MAX_DMA_CHANNELS + FXGMAC_PHY_INT_NUM) + +/* WOL pattern settings */ +#define MAX_PATTERN_SIZE 128 /* pattern length */ +#define MAX_PATTERN_COUNT 16 /* pattern count */ + +struct wol_bitmap_pattern { + u32 flags; + u32 pattern_size; + u32 mask_size; + u8 mask_info[MAX_PATTERN_SIZE / 8]; + u8 pattern_info[MAX_PATTERN_SIZE]; + u8 pattern_offset; + u16 pattern_crc; +}; + +enum _wake_reason { + WAKE_REASON_NONE = 0, + WAKE_REASON_MAGIC, + WAKE_REASON_PATTERNMATCH, + WAKE_REASON_LINK, + WAKE_REASON_TCPSYNV4, + WAKE_REASON_TCPSYNV6, + /* For wake up method like Link-change, GMAC cannot + * identify and need more checking. + */ + WAKE_REASON_TBD, + WAKE_REASON_HW_ERR, +}; + +enum fxgmac_int { + FXGMAC_INT_DMA_CH_SR_TI, + FXGMAC_INT_DMA_CH_SR_TPS, + FXGMAC_INT_DMA_CH_SR_TBU, + FXGMAC_INT_DMA_CH_SR_RI, + FXGMAC_INT_DMA_CH_SR_RBU, + FXGMAC_INT_DMA_CH_SR_RPS, + FXGMAC_INT_DMA_CH_SR_TI_RI, + FXGMAC_INT_DMA_CH_SR_FBE, + FXGMAC_INT_DMA_ALL, +}; + +struct fxgmac_stats { + /* MMC TX counters */ + u64 txoctetcount_gb; + u64 txframecount_gb; + u64 txbroadcastframes_g; + u64 txmulticastframes_g; + u64 tx64octets_gb; + u64 tx65to127octets_gb; + u64 tx128to255octets_gb; + u64 tx256to511octets_gb; + u64 tx512to1023octets_gb; + u64 tx1024tomaxoctets_gb; + u64 txunicastframes_gb; + u64 txmulticastframes_gb; + u64 txbroadcastframes_gb; + u64 txunderflowerror; + u64 txsinglecollision_g; + u64 txmultiplecollision_g; + u64 txdeferredframes; + u64 txlatecollisionframes; + u64 txexcessivecollisionframes; + u64 txcarriererrorframes; + u64 txoctetcount_g; + u64 txframecount_g; + u64 txexcessivedeferralerror; + u64 txpauseframes; + u64 txvlanframes_g; + u64 txoversize_g; + + /* MMC RX counters */ + u64 rxframecount_gb; + u64 rxoctetcount_gb; + u64 rxoctetcount_g; + u64 rxbroadcastframes_g; + u64 rxmulticastframes_g; + u64 rxcrcerror; + u64 rxalignerror; + u64 rxrunterror; + u64 rxjabbererror; + u64 rxundersize_g; + u64 rxoversize_g; + u64 rx64octets_gb; + u64 rx65to127octets_gb; + u64 rx128to255octets_gb; + u64 rx256to511octets_gb; + u64 rx512to1023octets_gb; + u64 rx1024tomaxoctets_gb; + u64 rxunicastframes_g; + u64 rxlengtherror; + u64 rxoutofrangetype; + u64 rxpauseframes; + u64 rxfifooverflow; + u64 rxvlanframes_gb; + u64 rxwatchdogerror; + u64 rxreceiveerrorframe; + u64 rxcontrolframe_g; + + /* Extra counters */ + u64 tx_tso_packets; + u64 rx_split_header_packets; + u64 tx_process_stopped; + u64 rx_process_stopped; + u64 tx_buffer_unavailable; + u64 rx_buffer_unavailable; + u64 fatal_bus_error; + u64 tx_vlan_packets; + u64 rx_vlan_packets; + u64 napi_poll_isr; + u64 napi_poll_txtimer; + u64 cnt_alive_txtimer; + u64 ephy_poll_timer_cnt; + u64 mgmt_int_isr; +}; + +struct fxgmac_ring_buf { + struct sk_buff *skb; + dma_addr_t skb_dma; + unsigned int skb_len; +}; + +/* Common Tx and Rx DMA hardware descriptor */ +struct fxgmac_dma_desc { + __le32 desc0; + __le32 desc1; + __le32 desc2; + __le32 desc3; +}; + +/* Page allocation related values */ +struct fxgmac_page_alloc { + struct page *pages; + unsigned int pages_len; + unsigned int pages_offset; + dma_addr_t pages_dma; +}; + +/* Ring entry buffer data */ +struct fxgmac_buffer_data { + struct fxgmac_page_alloc pa; + struct fxgmac_page_alloc pa_unmap; + + dma_addr_t dma_base; + unsigned long dma_off; + unsigned int dma_len; +}; + +/* Tx-related desc data */ +struct fxgmac_tx_desc_data { + unsigned int packets; /* BQL packet count */ + unsigned int bytes; /* BQL byte count */ +}; + +/* Rx-related desc data */ +struct fxgmac_rx_desc_data { + struct fxgmac_buffer_data hdr; /* Header locations */ + struct fxgmac_buffer_data buf; /* Payload locations */ + unsigned short hdr_len; /* Length of received header */ + unsigned short len; /* Length of received packet */ +}; + +struct fxgmac_pkt_info { + struct sk_buff *skb; + unsigned int attributes; + unsigned int errors; + + /* descriptors needed for this packet */ + unsigned int desc_count; + unsigned int length; + unsigned int tx_packets; + unsigned int tx_bytes; + + unsigned int header_len; + unsigned int tcp_header_len; + unsigned int tcp_payload_len; + unsigned short mss; + unsigned short vlan_ctag; + + u64 rx_tstamp; + u32 rss_hash; + enum pkt_hash_types rss_hash_type; +}; + +struct fxgmac_desc_data { + struct fxgmac_dma_desc *dma_desc; /* Virtual address of descriptor */ + dma_addr_t dma_desc_addr; /* DMA address of descriptor */ + struct sk_buff *skb; /* Virtual address of SKB */ + dma_addr_t skb_dma; /* DMA address of SKB data */ + unsigned int skb_dma_len; /* Length of SKB DMA area */ + + /* Tx/Rx -related data */ + struct fxgmac_tx_desc_data tx; + struct fxgmac_rx_desc_data rx; + + unsigned int mapped_as_page; +}; + +struct fxgmac_ring { + struct fxgmac_pkt_info pkt_info; /* Per packet related information */ + + /* Virtual/DMA addresses of DMA descriptor list and the total count */ + struct fxgmac_dma_desc *dma_desc_head; + dma_addr_t dma_desc_head_addr; + unsigned int dma_desc_count; + + /* Array of descriptor data corresponding the DMA descriptor + * (always use the FXGMAC_GET_DESC_DATA macro to access this data) + */ + struct fxgmac_desc_data *desc_data_head; + + /* Page allocation for RX buffers */ + struct fxgmac_page_alloc rx_hdr_pa; + struct fxgmac_page_alloc rx_buf_pa; + + /* Ring index values + * cur - Tx: index of descriptor to be used for current transfer + * Rx: index of descriptor to check for packet availability + * dirty - Tx: index of descriptor to check for transfer complete + * Rx: index of descriptor to check for buffer reallocation + */ + unsigned int cur; + unsigned int dirty; + + struct { + unsigned int xmit_more; + unsigned int queue_stopped; + unsigned short cur_mss; + unsigned short cur_vlan_ctag; + } tx; +} ____cacheline_aligned; + +struct fxgmac_channel { + char name[16]; + + /* Address of private data area for device */ + struct fxgmac_pdata *pdata; + + /* Queue index and base address of queue's DMA registers */ + unsigned int queue_index; + + /* Per channel interrupt irq number */ + u32 dma_irq_rx; + char dma_irq_rx_name[IFNAMSIZ + 32]; + u32 dma_irq_tx; + char dma_irq_tx_name[IFNAMSIZ + 32]; + + /* Netdev related settings */ + struct napi_struct napi_tx; + struct napi_struct napi_rx; + + unsigned int saved_ier; + unsigned int tx_timer_active; + struct timer_list tx_timer; + + u32 dma_reg_offset; + struct fxgmac_ring *tx_ring; + struct fxgmac_ring *rx_ring; +} ____cacheline_aligned; + +struct fxgmac_hw_ops { + void (*pcie_init)(struct fxgmac_pdata *pdata); + int (*init)(struct fxgmac_pdata *pdata); + void (*exit)(struct fxgmac_pdata *pdata); + void (*save_nonstick_reg)(struct fxgmac_pdata *pdata); + void (*restore_nonstick_reg)(struct fxgmac_pdata *pdata); + + void (*enable_tx)(struct fxgmac_pdata *pdata); + void (*disable_tx)(struct fxgmac_pdata *pdata); + void (*enable_rx)(struct fxgmac_pdata *pdata); + void (*disable_rx)(struct fxgmac_pdata *pdata); + int (*dev_read)(struct fxgmac_channel *channel); + void (*dev_xmit)(struct fxgmac_channel *channel); + + void (*enable_channel_irq)(struct fxgmac_channel *channel, + enum fxgmac_int int_id); + void (*disable_channel_irq)(struct fxgmac_channel *channel, + enum fxgmac_int int_id); + void (*set_interrupt_moderation)(struct fxgmac_pdata *pdata); + void (*enable_msix_one_irq)(struct fxgmac_pdata *pdata, u32 intid); + void (*disable_msix_one_irq)(struct fxgmac_pdata *pdata, u32 intid); + void (*enable_mgm_irq)(struct fxgmac_pdata *pdata); + void (*disable_mgm_irq)(struct fxgmac_pdata *pdata); + + void (*dismiss_all_int)(struct fxgmac_pdata *pdata); + void (*clear_misc_int_status)(struct fxgmac_pdata *pdata); + + void (*set_mac_address)(struct fxgmac_pdata *pdata, u8 *addr); + void (*set_mac_hash)(struct fxgmac_pdata *pdata); + void (*config_rx_mode)(struct fxgmac_pdata *pdata); + void (*enable_rx_csum)(struct fxgmac_pdata *pdata); + void (*disable_rx_csum)(struct fxgmac_pdata *pdata); + void (*config_tso)(struct fxgmac_pdata *pdata); + u32 (*calculate_max_checksum_size)(struct fxgmac_pdata *pdata); + void (*config_mac_speed)(struct fxgmac_pdata *pdata); + + /* PHY Control */ + void (*reset_phy)(struct fxgmac_pdata *pdata); + void (*release_phy)(struct fxgmac_pdata *pdata); + int (*write_phy_reg)(struct fxgmac_pdata *pdata, u32 val, u32 data); + int (*read_phy_reg)(struct fxgmac_pdata *pdata, u32 val); + + /* Vlan related config */ + void (*enable_rx_vlan_stripping)(struct fxgmac_pdata *pdata); + void (*disable_rx_vlan_stripping)(struct fxgmac_pdata *pdata); + void (*enable_rx_vlan_filtering)(struct fxgmac_pdata *pdata); + void (*disable_rx_vlan_filtering)(struct fxgmac_pdata *pdata); + void (*update_vlan_hash_table)(struct fxgmac_pdata *pdata); + + /* RX coalescing */ + void (*config_rx_coalesce)(struct fxgmac_pdata *pdata); + unsigned int (*usec_to_riwt)(struct fxgmac_pdata *pdata, + unsigned int usec); + + /* MMC statistics */ + void (*read_mmc_stats)(struct fxgmac_pdata *pdata); + + /* Receive Side Scaling */ + void (*enable_rss)(struct fxgmac_pdata *pdata); + void (*disable_rss)(struct fxgmac_pdata *pdata); + u32 (*get_rss_options)(struct fxgmac_pdata *pdata); + void (*set_rss_options)(struct fxgmac_pdata *pdata); + void (*set_rss_hash_key)(struct fxgmac_pdata *pdata, const u8 *key); + void (*write_rss_lookup_table)(struct fxgmac_pdata *pdata); + + /* Wake */ + void (*enable_wake_pattern)(struct fxgmac_pdata *pdata); + void (*disable_wake_pattern)(struct fxgmac_pdata *pdata); + void (*disable_arp_offload)(struct fxgmac_pdata *pdata); + void (*disable_wake_magic_pattern)(struct fxgmac_pdata *pdata); + int (*set_wake_pattern)(struct fxgmac_pdata *pdata, + struct wol_bitmap_pattern *wol_pattern, + u32 pattern_cnt); + void (*enable_wake_magic_pattern)(struct fxgmac_pdata *pdata); + void (*enable_wake_link_change)(struct fxgmac_pdata *pdata); + void (*disable_wake_link_change)(struct fxgmac_pdata *pdata); + + /* Power management */ + int (*pre_power_down)(struct fxgmac_pdata *pdata); + void (*config_power_down)(struct fxgmac_pdata *pdata, bool wake_en); + void (*config_power_up)(struct fxgmac_pdata *pdata); +}; + +/* This structure contains flags that indicate what hardware features + * or configurations are present in the device. + */ +struct fxgmac_hw_features { + unsigned int version; /* HW Version */ + + /* HW Feature Register0 */ + unsigned int phyifsel; /* PHY interface support */ + unsigned int vlhash; /* VLAN Hash Filter */ + unsigned int sma; /* SMA(MDIO) Interface */ + unsigned int rwk; /* PMT remote wake-up packet */ + unsigned int mgk; /* PMT magic packet */ + unsigned int mmc; /* RMON module */ + unsigned int aoe; /* ARP Offload */ + unsigned int ts; /* IEEE 1588-2008 Advanced Timestamp */ + unsigned int eee; /* Energy Efficient Ethernet */ + unsigned int tx_coe; /* Tx Checksum Offload */ + unsigned int rx_coe; /* Rx Checksum Offload */ + unsigned int addn_mac; /* Additional MAC Addresses */ + unsigned int ts_src; /* Timestamp Source */ + unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */ + + /* HW Feature Register1 */ + unsigned int rx_fifo_size; /* MTL Receive FIFO Size */ + unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */ + unsigned int adv_ts_hi; /* Advance Timestamping High Word */ + unsigned int dma_width; /* DMA width */ + unsigned int dcb; /* DCB Feature */ + unsigned int sph; /* Split Header Feature */ + unsigned int tso; /* TCP Segmentation Offload */ + unsigned int dma_debug; /* DMA Debug Registers */ + unsigned int rss; /* Receive Side Scaling */ + unsigned int tc_cnt; /* Number of Traffic Classes */ + unsigned int avsel; /* AV Feature Enable */ + unsigned int ravsel; /* Rx Side Only AV Feature Enable */ + unsigned int hash_table_size; /* Hash Table Size */ + unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */ + + /* HW Feature Register2 */ + unsigned int rx_q_cnt; /* Number of MTL Receive Queues */ + unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */ + unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */ + unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */ + unsigned int pps_out_num; /* Number of PPS outputs */ + unsigned int aux_snap_num; /* Number of Aux snapshot inputs */ + + u32 hwfr3; /* HW Feature Register3 */ +}; + +struct fxgmac_resources { + void __iomem *addr; + int irq; +}; + +enum fxgmac_dev_state { + FXGMAC_DEV_OPEN = 0x0, + FXGMAC_DEV_CLOSE = 0x1, + FXGMAC_DEV_STOP = 0x2, + FXGMAC_DEV_START = 0x3, + FXGMAC_DEV_SUSPEND = 0x4, + FXGMAC_DEV_RESUME = 0x5, + FXGMAC_DEV_PROBE = 0xFF, +}; + +enum fxgmac_task_flag { + FXGMAC_TASK_FLAG_DOWN = 0, + FXGMAC_TASK_FLAG_RESET, + FXGMAC_TASK_FLAG_LINK_CHG, + FXGMAC_TASK_FLAG_MAX +}; + +struct fxgmac_pdata { + struct net_device *netdev; + struct device *dev; + struct phy_device *phydev; + + struct fxgmac_hw_features hw_feat; /* Hardware features */ + struct fxgmac_hw_ops hw_ops; + void __iomem *hw_addr; /* Registers base */ + struct fxgmac_stats stats; /* Device statistics */ + + /* Rings for Tx/Rx on a DMA channel */ + struct fxgmac_channel *channel_head; + unsigned int channel_count; + unsigned int rx_ring_count; + unsigned int rx_desc_count; + unsigned int rx_q_count; +#define FXGMAC_TX_1_RING 1 +#define FXGMAC_TX_1_Q 1 + unsigned int tx_desc_count; + + unsigned long sysclk_rate; /* Device clocks */ + unsigned int pblx8; /* Tx/Rx common settings */ + unsigned int crc_check; + + /* Tx settings */ + unsigned int tx_sf_mode; + unsigned int tx_threshold; + unsigned int tx_pbl; + unsigned int tx_osp_mode; + unsigned int tx_hang_restart_queuing; + + /* Rx settings */ + unsigned int rx_sf_mode; + unsigned int rx_threshold; + unsigned int rx_pbl; + + /* Tx coalescing settings */ + unsigned int tx_usecs; + unsigned int tx_frames; + + /* Rx coalescing settings */ + unsigned int rx_riwt; + unsigned int rx_usecs; + unsigned int rx_frames; + + unsigned int rx_buf_size; /* Current Rx buffer size */ + + /* Flow control settings */ + unsigned int tx_pause; + unsigned int rx_pause; + + /* Jumbo frames */ + unsigned int mtu; + unsigned int jumbo; + + /* vlan */ + unsigned int vlan; + unsigned int vlan_exist; + unsigned int vlan_filter; + unsigned int vlan_strip; + + /* Device interrupt */ + int dev_irq; + unsigned int per_channel_irq; + u32 channel_irq[FXGMAC_MAX_DMA_CHANNELS]; + int misc_irq; + char misc_irq_name[IFNAMSIZ + 32]; + struct msix_entry *msix_entries; +#define FXGMAC_FLAG_INTERRUPT_POS 0 +#define FXGMAC_FLAG_INTERRUPT_LEN 5 +#define FXGMAC_FLAG_MSI_CAPABLE BIT(0) +#define FXGMAC_FLAG_MSI_ENABLED BIT(1) +#define FXGMAC_FLAG_MSIX_CAPABLE BIT(2) +#define FXGMAC_FLAG_MSIX_ENABLED BIT(3) +#define FXGMAC_FLAG_LEGACY_ENABLED BIT(4) +#define FXGMAC_FLAG_RX_NAPI_POS 18 +#define FXGMAC_FLAG_RX_NAPI_LEN 4 +#define FXGMAC_FLAG_PER_RX_NAPI_LEN 1 +#define FXGMAC_FLAG_RX_IRQ_POS 22 +#define FXGMAC_FLAG_RX_IRQ_LEN 4 +#define FXGMAC_FLAG_PER_RX_IRQ_LEN 1 +#define FXGMAC_FLAG_TX_NAPI_POS 26 +#define FXGMAC_FLAG_TX_NAPI_LEN 1 +#define FXGMAC_FLAG_TX_IRQ_POS 27 +#define FXGMAC_FLAG_TX_IRQ_LEN 1 +#define FXGMAC_FLAG_MISC_NAPI_POS 28 +#define FXGMAC_FLAG_MISC_NAPI_LEN 1 +#define FXGMAC_FLAG_MISC_IRQ_POS 29 +#define FXGMAC_FLAG_MISC_IRQ_LEN 1 +#define FXGMAC_FLAG_LEGACY_NAPI_POS 30 +#define FXGMAC_FLAG_LEGACY_NAPI_LEN 1 +#define FXGMAC_FLAG_LEGACY_IRQ_POS 31 +#define FXGMAC_FLAG_LEGACY_IRQ_LEN 1 + u32 int_flags; + + /* Interrupt Moderation */ + unsigned int intr_mod; + unsigned int intr_mod_timer; + + /* Netdev related settings */ + unsigned char mac_addr[ETH_ALEN]; + netdev_features_t netdev_features; + struct napi_struct napi; + struct napi_struct napi_misc; + + /* Filtering support */ + unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; + + /* Receive Side Scaling settings */ + unsigned int rss; + u8 rss_key[FXGMAC_RSS_HASH_KEY_SIZE]; + u32 rss_table[FXGMAC_RSS_MAX_TABLE_SIZE]; +#define FXGMAC_RSS_IP4TE BIT(0) +#define FXGMAC_RSS_TCP4TE BIT(1) +#define FXGMAC_RSS_UDP4TE BIT(2) +#define FXGMAC_RSS_IP6TE BIT(3) +#define FXGMAC_RSS_TCP6TE BIT(4) +#define FXGMAC_RSS_UDP6TE BIT(5) + u32 rss_options; + + int phy_speed; + int phy_duplex; + int phy_autoeng; + bool phy_link; + + u32 msg_enable; + u32 reg_nonstick[(MSI_PBA - GLOBAL_CTRL0) >> 2]; + + u32 wol; + struct wol_bitmap_pattern pattern[MAX_PATTERN_COUNT]; + + struct work_struct restart_work; + DECLARE_BITMAP(task_flags, FXGMAC_TASK_FLAG_MAX); + + enum fxgmac_dev_state dev_state; +#define FXGMAC_POWER_STATE_DOWN 0 +#define FXGMAC_POWER_STATE_UP 1 + unsigned long powerstate; + struct mutex mutex; /* Driver lock */ + + char drv_name[32]; + char drv_ver[32]; +}; + +void fxgmac_hw_ops_init(struct fxgmac_hw_ops *hw_ops); +int fxgmac_phy_irq_enable(struct fxgmac_pdata *pdata, bool clear_phy_interrupt); +const struct ethtool_ops *fxgmac_get_ethtool_ops(void); + +#endif /* YT6801_H */ diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.c new file mode 100644 index 000000000..476cf6633 --- /dev/null +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2022 - 2024 Motorcomm Electronic Technology Co.,Ltd. */ + +#include "yt6801_desc.h" + +void fxgmac_desc_data_unmap(struct fxgmac_pdata *pdata, + struct fxgmac_desc_data *desc_data) +{ + if (desc_data->skb_dma) { + if (desc_data->mapped_as_page) { + dma_unmap_page(pdata->dev, desc_data->skb_dma, + desc_data->skb_dma_len, DMA_TO_DEVICE); + } else { + dma_unmap_single(pdata->dev, desc_data->skb_dma, + desc_data->skb_dma_len, DMA_TO_DEVICE); + } + desc_data->skb_dma = 0; + desc_data->skb_dma_len = 0; + } + + if (desc_data->skb) { + dev_kfree_skb_any(desc_data->skb); + desc_data->skb = NULL; + } + + if (desc_data->rx.hdr.pa.pages) + put_page(desc_data->rx.hdr.pa.pages); + + if (desc_data->rx.hdr.pa_unmap.pages) { + dma_unmap_page(pdata->dev, desc_data->rx.hdr.pa_unmap.pages_dma, + desc_data->rx.hdr.pa_unmap.pages_len, + DMA_FROM_DEVICE); + put_page(desc_data->rx.hdr.pa_unmap.pages); + } + + if (desc_data->rx.buf.pa.pages) + put_page(desc_data->rx.buf.pa.pages); + + if (desc_data->rx.buf.pa_unmap.pages) { + dma_unmap_page(pdata->dev, desc_data->rx.buf.pa_unmap.pages_dma, + desc_data->rx.buf.pa_unmap.pages_len, + DMA_FROM_DEVICE); + put_page(desc_data->rx.buf.pa_unmap.pages); + } + memset(&desc_data->tx, 0, sizeof(desc_data->tx)); + memset(&desc_data->rx, 0, sizeof(desc_data->rx)); + + desc_data->mapped_as_page = 0; +} diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.h b/drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.h new file mode 100644 index 000000000..24e3d9b85 --- /dev/null +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_desc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2022 - 2024 Motorcomm Electronic Technology Co.,Ltd. */ + +#ifndef YT6801_DESC_H +#define YT6801_DESC_H + +#include "yt6801.h" + +#define FXGMAC_TX_DESC_CNT 256 +#define FXGMAC_TX_DESC_MIN_FREE (FXGMAC_TX_DESC_CNT >> 3) +#define FXGMAC_TX_DESC_MAX_PROC (FXGMAC_TX_DESC_CNT >> 1) +#define FXGMAC_RX_DESC_CNT 1024 +#define FXGMAC_RX_DESC_MAX_DIRTY (FXGMAC_RX_DESC_CNT >> 3) + +#define FXGMAC_GET_DESC_DATA(ring, idx) ((ring)->desc_data_head + (idx)) +#define FXGMAC_GET_ENTRY(x, size) (((x) + 1) & ((size) - 1)) + +#define FXGMAC_IS_CHANNEL_WITH_TX_IRQ(chid) (0 == (chid) ? 1 : 0) + +void fxgmac_desc_tx_reset(struct fxgmac_desc_data *desc_data); +void fxgmac_desc_rx_reset(struct fxgmac_desc_data *desc_data); +void fxgmac_desc_data_unmap(struct fxgmac_pdata *pdata, + struct fxgmac_desc_data *desc_data); + +int fxgmac_channels_rings_alloc(struct fxgmac_pdata *pdata); +void fxgmac_channels_rings_free(struct fxgmac_pdata *pdata); +int fxgmac_tx_skb_map(struct fxgmac_channel *channel, struct sk_buff *skb); +int fxgmac_rx_buffe_map(struct fxgmac_pdata *pdata, struct fxgmac_ring *ring, + struct fxgmac_desc_data *desc_data); +void fxgmac_dump_tx_desc(struct fxgmac_pdata *pdata, struct fxgmac_ring *ring, + unsigned int idx, unsigned int count, + unsigned int flag); +void fxgmac_dump_rx_desc(struct fxgmac_pdata *pdata, struct fxgmac_ring *ring, + unsigned int idx); + +int fxgmac_is_tx_complete(struct fxgmac_dma_desc *dma_desc); +int fxgmac_is_last_desc(struct fxgmac_dma_desc *dma_desc); + +#endif /* YT6801_DESC_H */ diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c new file mode 100644 index 000000000..925bc1e7d --- /dev/null +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2022 - 2024 Motorcomm Electronic Technology Co.,Ltd. */ + +#include <linux/inetdevice.h> +#include <linux/netdevice.h> +#include <linux/interrupt.h> +#include <net/addrconf.h> +#include <linux/inet.h> +#include <linux/tcp.h> + +#include "yt6801_desc.h" +#include "yt6801_net.h" + +#define FXGMAC_NAPI_ENABLE 0x1 +#define FXGMAC_NAPI_DISABLE 0x0 +static void fxgmac_napi_disable(struct fxgmac_pdata *pdata) +{ + u32 i, *flags = &pdata->int_flags; + struct fxgmac_channel *channel; + u32 misc_napi, tx, rx, val; + + misc_napi = FIELD_GET(BIT(FXGMAC_FLAG_MISC_NAPI_POS), *flags); + tx = FXGMAC_GET_BITS(*flags, FXGMAC_FLAG_TX_NAPI_POS, + FXGMAC_FLAG_TX_NAPI_LEN); + rx = FXGMAC_GET_BITS(*flags, FXGMAC_FLAG_RX_NAPI_POS, + FXGMAC_FLAG_RX_NAPI_LEN); + + if (!pdata->per_channel_irq) { + val = FIELD_GET(BIT(FXGMAC_FLAG_LEGACY_NAPI_POS), *flags); + if (val == 0) + return; + + napi_disable(&pdata->napi); + netif_napi_del(&pdata->napi); + fxgmac_set_bits(flags, FXGMAC_FLAG_LEGACY_NAPI_POS, + FXGMAC_FLAG_LEGACY_NAPI_LEN, + FXGMAC_NAPI_DISABLE); + return; + } + + channel = pdata->channel_head; + for (i = 0; i < pdata->channel_count; i++, channel++) { + if (FXGMAC_GET_BITS(rx, i, FXGMAC_FLAG_PER_RX_NAPI_LEN)) { + napi_disable(&channel->napi_rx); + netif_napi_del(&channel->napi_rx); + fxgmac_set_bits(flags, FXGMAC_FLAG_RX_NAPI_POS + i, + FXGMAC_FLAG_PER_RX_NAPI_LEN, + FXGMAC_NAPI_DISABLE); + } + + if (FXGMAC_IS_CHANNEL_WITH_TX_IRQ(i) && tx) { + napi_disable(&channel->napi_tx); + netif_napi_del(&channel->napi_tx); + fxgmac_set_bits(flags, FXGMAC_FLAG_TX_NAPI_POS, + FXGMAC_FLAG_TX_NAPI_LEN, + FXGMAC_NAPI_DISABLE); + } + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, + "napi_disable, msix ch%d, napi disabled done. ", + i); + } + + if (misc_napi) { + napi_disable(&pdata->napi_misc); + netif_napi_del(&pdata->napi_misc); + fxgmac_set_bits(flags, FXGMAC_FLAG_MISC_NAPI_POS, + FXGMAC_FLAG_MISC_NAPI_LEN, FXGMAC_NAPI_DISABLE); + } +} + +static void fxgmac_free_irqs(struct fxgmac_pdata *pdata) +{ + u32 i, need_free, misc, tx, rx, msix; + u32 *flags = &pdata->int_flags; + struct fxgmac_channel *channel; + + msix = FIELD_GET(FXGMAC_FLAG_MSIX_ENABLED, *flags); + need_free = FIELD_GET(BIT(FXGMAC_FLAG_LEGACY_IRQ_POS), *flags); + if (!msix && need_free) { + devm_free_irq(pdata->dev, pdata->dev_irq, pdata); + fxgmac_set_bits(flags, FXGMAC_FLAG_LEGACY_IRQ_POS, + FXGMAC_FLAG_LEGACY_IRQ_LEN, FXGMAC_IRQ_DISABLE); + } + + if (!pdata->per_channel_irq) + return; + + channel = pdata->channel_head; + + misc = FIELD_GET(BIT(FXGMAC_FLAG_MISC_IRQ_POS), *flags); + tx = FXGMAC_GET_BITS(*flags, FXGMAC_FLAG_TX_IRQ_POS, + FXGMAC_FLAG_TX_IRQ_LEN); + rx = FXGMAC_GET_BITS(*flags, FXGMAC_FLAG_RX_IRQ_POS, + FXGMAC_FLAG_RX_IRQ_LEN); + for (i = 0; i < pdata->channel_count; i++, channel++) { + if (FXGMAC_IS_CHANNEL_WITH_TX_IRQ(i) && tx) { + fxgmac_set_bits(flags, FXGMAC_FLAG_TX_IRQ_POS, + FXGMAC_FLAG_TX_IRQ_LEN, + FXGMAC_IRQ_DISABLE); + devm_free_irq(pdata->dev, channel->dma_irq_tx, channel); + if (netif_msg_drv(pdata)) + yt_dbg(pdata, + "%s, MSIx irq_tx clear done ch=%d\n", + __func__, i); + } + + if (FXGMAC_GET_BITS(rx, i, FXGMAC_FLAG_PER_RX_IRQ_LEN)) { + fxgmac_set_bits(flags, FXGMAC_FLAG_RX_IRQ_POS + i, + FXGMAC_FLAG_PER_RX_IRQ_LEN, + FXGMAC_IRQ_DISABLE); + devm_free_irq(pdata->dev, channel->dma_irq_rx, channel); + } + } + + if (misc) { + fxgmac_set_bits(flags, FXGMAC_FLAG_MISC_IRQ_POS, + FXGMAC_FLAG_MISC_IRQ_LEN, FXGMAC_IRQ_DISABLE); + devm_free_irq(pdata->dev, pdata->misc_irq, pdata); + } + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "%s, MSIx rx irq clear done, total=%d\n", + __func__, i); +} + +void fxgmac_free_tx_data(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + struct fxgmac_desc_data *desc_data; + struct fxgmac_ring *ring; + + for (u32 i = 0; i < pdata->channel_count; i++, channel++) { + ring = channel->tx_ring; + if (!ring) + break; + + for (u32 j = 0; j < ring->dma_desc_count; j++) { + desc_data = FXGMAC_GET_DESC_DATA(ring, j); + fxgmac_desc_data_unmap(pdata, desc_data); + } + } +} + +void fxgmac_free_rx_data(struct fxgmac_pdata *pdata) +{ + struct fxgmac_channel *channel = pdata->channel_head; + struct fxgmac_desc_data *desc_data; + struct fxgmac_ring *ring; + + for (u32 i = 0; i < pdata->channel_count; i++, channel++) { + ring = channel->rx_ring; + if (!ring) + break; + + for (u32 j = 0; j < ring->dma_desc_count; j++) { + desc_data = FXGMAC_GET_DESC_DATA(ring, j); + fxgmac_desc_data_unmap(pdata, desc_data); + } + } +} + +static void fxgmac_disable_msix_irqs(struct fxgmac_pdata *pdata) +{ + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + + for (u32 intid = 0; intid < MSIX_TBL_MAX_NUM; intid++) + hw_ops->disable_msix_one_irq(pdata, intid); +} + +void fxgmac_stop(struct fxgmac_pdata *pdata) +{ + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + struct net_device *netdev = pdata->netdev; + struct netdev_queue *txq; + + if (pdata->dev_state != FXGMAC_DEV_START) + return; + + pdata->dev_state = FXGMAC_DEV_STOP; + + if (pdata->per_channel_irq) + fxgmac_disable_msix_irqs(pdata); + else + hw_ops->disable_mgm_irq(pdata); + + pdata->phy_link = false; + netif_carrier_off(netdev); + netif_tx_stop_all_queues(netdev); + hw_ops->disable_tx(pdata); + hw_ops->disable_rx(pdata); + fxgmac_free_irqs(pdata); + fxgmac_napi_disable(pdata); + phy_stop(pdata->phydev); + + txq = netdev_get_tx_queue(netdev, pdata->channel_head->queue_index); + netdev_tx_reset_queue(txq); +} + +int fxgmac_net_powerdown(struct fxgmac_pdata *pdata, bool wake_en) +{ + struct fxgmac_hw_ops *hw_ops = &pdata->hw_ops; + struct net_device *netdev = pdata->netdev; + int ret; + + /* Signal that we are down to the interrupt handler */ + if (__test_and_set_bit(FXGMAC_POWER_STATE_DOWN, &pdata->powerstate)) + return 0; /* do nothing if already down */ + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "%s, continue with down process.\n", __func__); + + __clear_bit(FXGMAC_POWER_STATE_UP, &pdata->powerstate); + netif_tx_stop_all_queues(netdev); /* Shut off incoming Tx traffic */ + + /* Call carrier off first to avoid false dev_watchdog timeouts */ + netif_carrier_off(netdev); + netif_tx_disable(netdev); + hw_ops->disable_rx(pdata); /* Disable Rx */ + + /* Synchronize_rcu() needed for pending XDP buffers to drain */ + synchronize_rcu(); + + fxgmac_stop(pdata); + ret = hw_ops->pre_power_down(pdata); + if (ret < 0) { + yt_err(pdata, "pre_power_down err.\n"); + return ret; + } + + if (!test_bit(FXGMAC_POWER_STATE_DOWN, &pdata->powerstate)) { + yt_err(pdata, + "fxgmac powerstate is %lu when config powe down.\n", + pdata->powerstate); + } + + /* Set mac to lowpower mode and enable wol accordingly */ + hw_ops->disable_tx(pdata); + hw_ops->disable_rx(pdata); + fxgmac_config_wol(pdata, wake_en); + hw_ops->config_power_down(pdata, wake_en); + + fxgmac_free_tx_data(pdata); + fxgmac_free_rx_data(pdata); + + if (netif_msg_drv(pdata)) + yt_dbg(pdata, "%s, powerstate :%ld.\n", __func__, + pdata->powerstate); + + return 0; +} diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.h b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.h new file mode 100644 index 000000000..adcad045b --- /dev/null +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_net.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2022 - 2024 Motorcomm Electronic Technology Co.,Ltd. */ + +#ifndef YT6801_NET_H +#define YT6801_NET_H + +#include "yt6801.h" + +/* flags for ipv6 NS offload address, local link or Global unicast */ +#define FXGMAC_NS_IFA_LOCAL_LINK 1 +#define FXGMAC_NS_IFA_GLOBAL_UNICAST 2 + +unsigned int fxgmac_get_netdev_ip4addr(struct fxgmac_pdata *pdata); +unsigned char *fxgmac_get_netdev_ip6addr(struct fxgmac_pdata *pdata, + unsigned char *ipval, + unsigned char *ip6addr_solicited, + unsigned int ifa_flag); +int fxgmac_start(struct fxgmac_pdata *pdata); +void fxgmac_stop(struct fxgmac_pdata *pdata); +void fxgmac_restart(struct fxgmac_pdata *pdata); +void fxgmac_dbg_pkt(struct fxgmac_pdata *pdata, struct sk_buff *skb, + bool tx_rx); +void fxgmac_tx_start_xmit(struct fxgmac_channel *channel, + struct fxgmac_ring *ring); +void fxgmac_free_tx_data(struct fxgmac_pdata *pdata); +void fxgmac_free_rx_data(struct fxgmac_pdata *pdata); +int fxgmac_config_wol(struct fxgmac_pdata *pdata, bool en); +int fxgmac_net_powerup(struct fxgmac_pdata *pdata); +int fxgmac_net_powerdown(struct fxgmac_pdata *pdata, bool wake_en); +int fxgmac_drv_probe(struct device *dev, struct fxgmac_resources *res); + +#endif /* YT6801_NET_H */ diff --git a/drivers/net/ethernet/motorcomm/yt6801/yt6801_pci.c b/drivers/net/ethernet/motorcomm/yt6801/yt6801_pci.c index c93698586..b2cd75b5c 100644 --- a/drivers/net/ethernet/motorcomm/yt6801/yt6801_pci.c +++ b/drivers/net/ethernet/motorcomm/yt6801/yt6801_pci.c @@ -8,6 +8,8 @@ #include <linux/pci.h> #endif +#include "yt6801_net.h" + static int fxgmac_probe(struct pci_dev *pcidev, const struct pci_device_id *id) { struct device *dev = &pcidev->dev; @@ -79,6 +81,29 @@ static int __fxgmac_shutdown(struct pci_dev *pcidev, bool *wake_en) return 0; } +static void fxgmac_shutdown(struct pci_dev *pcidev) +{ + struct fxgmac_pdata *pdata = dev_get_drvdata(&pcidev->dev); + struct device *dev = &pcidev->dev; + bool wake; + int ret; + + mutex_lock(&pdata->mutex); + ret = __fxgmac_shutdown(pcidev, &wake); + if (ret < 0) + goto unlock; + + if (system_state == SYSTEM_POWER_OFF) { + pci_wake_from_d3(pcidev, wake); + pci_set_power_state(pcidev, PCI_D3hot); + } +unlock: + mutex_unlock(&pdata->mutex); + + dev_dbg(dev, "%s, system power off=%d\n", __func__, + (system_state == SYSTEM_POWER_OFF) ? 1 : 0); +} + #define MOTORCOMM_PCI_ID 0x1f0a #define YT6801_PCI_DEVICE_ID 0x6801 @@ -94,6 +119,7 @@ static struct pci_driver fxgmac_pci_driver = { .id_table = fxgmac_pci_tbl, .probe = fxgmac_probe, .remove = fxgmac_remove, + .shutdown = fxgmac_shutdown, }; module_pci_driver(fxgmac_pci_driver); -- 2.34.1