From: Qi Liu <liuqi115@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- Add support for HiSilicon L3C PMU aliasing on Hip09 platform. Signed-off-by: Qi Liu <liuqi115@huawei.com> Signed-off-by: Junhao He <hejunhao3@huawei.com> Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- .../arm64/hisilicon/hip09/sys/uncore-l3c.json | 125 ++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json new file mode 100644 index 000000000000..46167a2eec51 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json @@ -0,0 +1,125 @@ +[ + { + "EventCode": "0x00", + "EventName": "rd_cpipe", + "BriefDescription": "Total read accesses", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x02", + "EventName": "rd_hit_cpipe", + "BriefDescription": "Total read hits", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x20", + "EventName": "rd_spipe", + "BriefDescription": "Count of the number of read lines that come from this cluster of CPU core in spipe", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x22", + "EventName": "rd_hit_spipe", + "BriefDescription": "Count of the number of read lines that hits in spipe of this L3C", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x29", + "EventName": "back_invalid", + "BriefDescription": "Count of the number of L3C back invalid operations", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x40", + "EventName": "retry_cpu", + "BriefDescription": "Count of the number of retry that L3C suppresses the CPU operations", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x41", + "EventName": "retry_ring", + "BriefDescription": "Count of the number of retry that L3C suppresses the ring operations", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x48", + "EventName": "l3c_hit", + "BriefDescription": "Count of the total number of L3C hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x80", + "EventName": "read_sum", + "Filter": "tt_core=0xff", + "BriefDescription": "total time taken by CPU to read L3C", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xb8", + "EventName": "l3c_ref", + "BriefDescription": "Count of the total number of CPU accessed L3C", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xb9", + "EventName": "dat_access", + "BriefDescription": "Count of the total number of CPU accessed L3C", + "Filter": "tt_core=0xff", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc0", + "EventName": "read_alloc", + "Filter": "tt_core=0xff", + "BriefDescription": "Count of the requests issued by CPU received by L3C", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xce", + "EventName": "retry_alloc", + "Filter": "tt_core=0xff", + "BriefDescription": "Count of the L3C retry CPU", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x7f", + "EventName": "l3c_cycles", + "BriefDescription": "Count of L3C cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventName": "cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricExpr": "l3c_hit / l3c_ref", + "BriefDescription": "hit rate of L3C", + "Compat": "0x00000030", + "MetricGroup": "L3Cache", + "MetricName": "l3c_hit_rate", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricExpr": "read_sum / (l3c_ref - retry_alloc)", + "BriefDescription": "Average latency of CPU reading L3", + "Compat": "0x00000030", + "MetricGroup": "L3Cache", + "MetricName": "l3c_latency", + "Unit": "hisi_sccl,l3c" + } +] \ No newline at end of file -- 2.43.0

From: Qi Liu <liuqi115@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- Add support for HiSilicon HHA PMU aliasing on Hip09 platform. Signed-off-by: Qi Liu <liuqi115@huawei.com> Signed-off-by: Junhao He <hejunhao3@huawei.com> Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- .../arm64/hisilicon/hip09/sys/uncore-hha.json | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json new file mode 100644 index 000000000000..e49dceeaa263 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json @@ -0,0 +1,102 @@ +[ + { + "EventCode": "0x00", + "EventName": "rx_ops_num", + "BriefDescription": "The number of all operations received by the HHA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x01", + "EventName": "rx_outer", + "BriefDescription": "The number of all operations received by the HHA from another socket", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x02", + "EventName": "rx_sccl", + "BriefDescription": "The number of all operations received by the HHA from another SCCL in this socket", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1c", + "EventName": "rd_ddr_64b", + "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1d", + "EventName": "wr_ddr_64b", + "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1e", + "EventName": "rd_ddr_128b", + "BriefDescription": "The number of read operations sent by HHA to DDRC which size is 128 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1f", + "EventName": "wr_ddr_128b", + "BriefDescription": "The number of write operations sent by HHA to DDRC which size is 128 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x2e", + "EventName": "hha_retry", + "BriefDescription": "Count of the HHA retry", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x55", + "EventName": "hha_cycles", + "BriefDescription": "Count of the HHA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventName": "cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricExpr": "(rd_ddr_64b * 64 + rd_ddr_128b *128) / duration_time", + "BriefDescription": "Average bandwidth of reading DDRC(Byte/s)", + "Compat": "0x00000030", + "MetricGroup": "HHA", + "MetricName": "hha_read_ddrc_bw", + "Unit": "hisi_sccl,hha" + }, + { + "MetricExpr": "(wr_ddr_64b * 64 + wr_ddr_128b *128) / duration_time", + "BriefDescription": "Average bandwidth of writing DDRC(Byte/s)", + "Compat": "0x00000030", + "MetricGroup": "HHA", + "MetricName": "hha_write_ddrc_bw", + "Unit": "hisi_sccl,hha" + }, + { + "MetricExpr": "rx_outer / rx_ops_num", + "BriefDescription": "Rate of cross-chip operations received by HHA", + "Compat": "0x00000030", + "MetricGroup": "HHA", + "MetricName": "cross_chip_ops_rate", + "Unit": "hisi_sccl,hha" + }, + { + "MetricExpr": "rx_sccl / rx_ops_num", + "BriefDescription": "Rate of cross-die operations received by HHA", + "Compat": "0x00000030", + "MetricGroup": "HHA", + "MetricName": "cross_die_ops_rate", + "Unit": "hisi_sccl,hha" + } +] \ No newline at end of file -- 2.43.0

From: Qi Liu <liuqi115@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- Add support for HiSilicon PA PMU aliasing on Hip09 platform. Signed-off-by: Qi Liu <liuqi115@huawei.com> Signed-off-by: Junhao He <hejunhao3@huawei.com> Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- .../arm64/hisilicon/hip09/sys/uncore-pa.json | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-pa.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-pa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-pa.json new file mode 100644 index 000000000000..6ddc9b4ffa16 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-pa.json @@ -0,0 +1,86 @@ +[ + { + "EventCode": "0x78", + "EventName": "pa_cycles", + "BriefDescription": "Count of PA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventName": "cycle", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x40", + "EventName": "rx_req", + "BriefDescription": "Count of the requests received by PA link0", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x41", + "EventName": "rx_req_link1", + "BriefDescription": "Count of the requests received by PA link1", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x42", + "EventName": "rx_req_link2", + "BriefDescription": "Count of the requests received by PA link2", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x43", + "EventName": "rx_req_link3", + "BriefDescription": "Count of the requests received by PA link3", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x5c", + "EventName": "tx_req", + "BriefDescription": "Count of the requests transmitted by PA link0", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x5d", + "EventName": "tx_req_link1", + "BriefDescription": "Count of the requests transmitted by PA link1", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x5e", + "EventName": "tx_req_link2", + "BriefDescription": "Count of the requests transmitted by PA link2", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x5f", + "EventName": "tx_req_link3", + "BriefDescription": "Count of the requests transmitted by PA link3", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricExpr": "(rx_req + rx_req_link1 + rx_req_link2 + rx_req_link3) / duration_time", + "BriefDescription": "Average bandwidth of PA receive requests", + "Compat": "0x00000030", + "MetricGroup": "PA", + "MetricName": "pa_rx_req_bw", + "Unit": "hisi_sicl,pa" + }, + { + "MetricExpr": "(tx_req + tx_req_link1 + tx_req_link2 + tx_req_link3) / duration_time", + "BriefDescription": "Average bandwidth of PA transmitted requests", + "Compat": "0x00000030", + "MetricGroup": "PA", + "MetricName": "pa_tx_req_bw", + "Unit": "hisi_sicl,pa" + } +] \ No newline at end of file -- 2.43.0

From: Junhao He <hejunhao3@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- Add support to parse sys metrics. Signed-off-by: Junhao He <hejunhao3@huawei.com> Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- .../arm64/hisilicon/hip09/sys/uncore-cpa.json | 83 ++++++ .../hisilicon/hip09/sys/uncore-ddrc.json | 154 ++++++++++ .../arm64/hisilicon/hip09/sys/uncore-hha.json | 191 ++++++++++++ .../arm64/hisilicon/hip09/sys/uncore-l3c.json | 142 +++++++++ .../arm64/hisilicon/hip09/sys/uncore-mn.json | 163 +++++++++++ .../arm64/hisilicon/hip09/sys/uncore-noc.json | 158 ++++++++++ .../arm64/hisilicon/hip09/sys/uncore-pa.json | 274 ++++++++++++++++++ .../hisilicon/hip09/sys/uncore-sllc.json | 204 +++++++++++++ 8 files changed, 1369 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-mn.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-noc.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-pa.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-sllc.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json new file mode 100644 index 000000000000..705efb48f99b --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json @@ -0,0 +1,83 @@ +[ + { + "ConfigCode": "0x00", + "EventName": "cpa_cycles", + "BriefDescription": "count of CPA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x61", + "EventName": "cpa_p1_wr_dat", + "BriefDescription": "Number of write ops transmitted by the P1 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x62", + "EventName": "cpa_p1_rd_dat", + "BriefDescription": "Number of read ops transmitted by the P1 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x3", + "EventName": "cpa_p1_rd_dat_64b", + "BriefDescription": "Number of read ops transmitted by the P1 port which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x4", + "EventName": "cpa_p1_rd_dat_32b", + "BriefDescription": "Number of read ops transmitted by the P1 port which size is 32 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0xE1", + "EventName": "cpa_p0_wr_dat", + "BriefDescription": "Number of write ops transmitted by the P0 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0xE2", + "EventName": "cpa_p0_rd_dat", + "BriefDescription": "Number of read ops transmitted by the P0 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x83", + "EventName": "cpa_p0_rd_dat_64b", + "BriefDescription": "Number of read ops transmitted by the P0 port which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x84", + "EventName": "cpa_p0_rd_dat_32b", + "BriefDescription": "Number of read ops transmitted by the P0 port which size is 32 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "MetricName": "cpa_p1_avg_bw", + "MetricExpr": "(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / duration_time / 1e6", + "BriefDescription": "Average bandwidth of CPA Port 1", + "MetricGroup": "CPA_bw", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "MetricName": "cpa_p0_avg_bw", + "MetricExpr": "(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / duration_time / 1e6", + "BriefDescription": "Average bandwidth of CPA Port 0", + "MetricGroup": "CPA_bw", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json new file mode 100644 index 000000000000..331a44d2eb59 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json @@ -0,0 +1,154 @@ +[ + { + "EventCode": "0x00", + "EventName": "ddrc_cycles", + "BriefDescription": "Count of DDRC cycles", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x00", + "EventName": "cycles", + "BriefDescription": "Count of DDRC cycles", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x01", + "EventName": "ddrc_active_cmd", + "BriefDescription": "Count of DDRC active commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x02", + "EventName": "ddrc_precharge_cmd", + "BriefDescription": "Count of DDRC precharge commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x03", + "EventName": "ddrc_cas_cmd", + "BriefDescription": "Count of DDRC read and write commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x30", + "EventName": "ddrc_rdwr_changes", + "BriefDescription": "Count the DDRC read and write changes", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x31", + "EventName": "ddrc_rank_changes", + "BriefDescription": "Count the DDRC rank changes", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x32", + "EventName": "ddrc_bg_changes", + "BriefDescription": "Count the DDRC BG changes", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x41", + "EventName": "ddrc_read_cmd", + "BriefDescription": "Count of DDRC read commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x44", + "EventName": "ddrc_write_cmd", + "BriefDescription": "Count of DDRC write commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x80", + "EventName": "ddrc_read_cmd_occupancy", + "BriefDescription": "Count of cycles occupied by the read command in the queue", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x81", + "EventName": "ddrc_write_cmd_occupancy", + "BriefDescription": "Count of cycles occupied by the write command in the queue", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x83", + "EventName": "flux_wr", + "BriefDescription": "Count of DDRC write commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "EventCode": "0x84", + "EventName": "flux_rd", + "BriefDescription": "Count of DDRC read commands", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_write_bw", + "MetricExpr": "flux_wr * 4 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of write DDRC memory", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_read_bw", + "MetricExpr": "flux_rd * 4 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of read DDRC memory", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_rdwr_bw", + "MetricExpr": "(flux_wr + flux_rd) * 4 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of DDRC (including memory read and write)", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_read_lat", + "MetricExpr": "ddrc_read_cmd_occupancy / ddrc_read_cmd * (duration_time * 1e9 / ddrc_cycles)", + "MetricGroup": "DDRC_lat", + "BriefDescription": "Average scheduling latency of DDRC read command", + "ScaleUnit": "1ns", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_write_lat", + "MetricExpr": "ddrc_write_cmd_occupancy / ddrc_write_cmd * (duration_time * 1e9 / ddrc_cycles)", + "MetricGroup": "DDRC_lat", + "BriefDescription": "Average scheduling of DDRC write command", + "ScaleUnit": "1ns", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_rowhit_rate", + "MetricExpr": "1 - ddrc_active_cmd / ddrc_cas_cmd", + "MetricGroup": "DDRC", + "BriefDescription": "Row hit rate of DDRC", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json new file mode 100644 index 000000000000..6e3eac3ba80c --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json @@ -0,0 +1,191 @@ +[ + { + "EventCode": "0x00", + "EventName": "rx_ops_num", + "BriefDescription": "Number of all operations received by the HHA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x01", + "EventName": "rx_outer", + "BriefDescription": "Number of all operations received by the HHA from another socket", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x02", + "EventName": "rx_sccl", + "BriefDescription": "Number of all operations received by the HHA from another SCCL in this socket", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x03", + "EventName": "hha_rx_cxl", + "BriefDescription": "Number of operations that HHA has received from CXL", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x13", + "EventName": "hha_rx_cmo", + "BriefDescription": "Count number of CMO operations received by the HHA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x16", + "EventName": "hha_rx_prefetch_drop", + "BriefDescription": "Count number of prefetch operations dropped by the HHA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1a", + "EventName": "hha_rx_ch0", + "BriefDescription": "Count number of all operations received by the HHA from channel 0", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1b", + "EventName": "hha_rx_ch1", + "BriefDescription": "Count number of all operations received by the HHA from channel 1", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1c", + "EventName": "hha_rd_ddr_64b", + "BriefDescription": "Count number of read operations sent by HHA to DDRC which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1d", + "EventName": "hha_wr_ddr_64b", + "BriefDescription": "Count number of write operations sent by HHA to DDRC which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1e", + "EventName": "hha_rd_ddr_128b", + "BriefDescription": "Count number of read operations sent by HHA to DDRC which size is 128 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x1f", + "EventName": "hha_wr_ddr_128b", + "BriefDescription": "Count number of write operations sent by HHA to DDRC which size is 128 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x23", + "EventName": "hha_retry", + "BriefDescription": "Count of the HHA retry", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x2e", + "EventName": "hha_backinvalid", + "BriefDescription": "Count number of HHA back invalid operations", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x55", + "EventName": "hha_cycles", + "BriefDescription": "Count of the HHA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0x55", + "EventName": "cycles", + "BriefDescription": "Count of the HHA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0xc5", + "EventName": "hha_req_lat", + "BriefDescription": "Count the total latency that HHA completes all requests", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "EventCode": "0xcd", + "EventName": "hha_req_cnt", + "BriefDescription": "Count the total operations that HHA receives", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_read_ddrc_bw", + "MetricExpr": "(hha_rd_ddr_64b * 8 + hha_rd_ddr_128b * 16) / duration_time / 1e6", + "MetricGroup": "HHA_bw", + "BriefDescription": "Average bandwidth of reading DDRC", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_write_ddrc_bw", + "MetricExpr": "(hha_wr_ddr_64b * 8 + hha_wr_ddr_128b * 16) / duration_time / 1e6", + "MetricGroup": "HHA_bw", + "BriefDescription": "Average bandwidth of writing DDRC", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_cross_chip_ops_rate", + "MetricExpr": "rx_outer / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of cross-chip operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_cross_die_ops_rate", + "MetricExpr": "rx_sccl / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of cross-die operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_channel0_ops_rate", + "MetricExpr": "hha_rx_ch0 / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of channel 0 operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_channel1_ops_rate", + "MetricExpr": "hha_rx_ch1 / rx_ops_num", + "MetricGroup": "HHA_lat", + "BriefDescription": "Rate of channel 1 operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_req_average_lat", + "MetricExpr": "hha_req_lat / hha_req_cnt * (duration_time * 1e9 / hha_cycles)", + "MetricGroup": "HHA_lat", + "BriefDescription": "Average latency that HHA completes all requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json new file mode 100644 index 000000000000..1d905beec448 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json @@ -0,0 +1,142 @@ +[ + { + "EventCode": "0x29", + "EventName": "l3c_back_invalid", + "BriefDescription": "Count number of L3C back invalid operations", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x3c", + "EventName": "l3c_cpu_evict", + "BriefDescription": "Count number of evict from CPU core", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x40", + "EventName": "l3c_retry_cpu", + "BriefDescription": "Count number of retry that L3C suppresses the CPU operations", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x41", + "EventName": "l3c_retry_ring", + "BriefDescription": "Count number of retry that L3C suppresses the ring operations", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x48", + "EventName": "l3c_hit", + "BriefDescription": "Count number of hit data from L3C to CPU core", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x7f", + "EventName": "l3c_cycles", + "BriefDescription": "Count of L3C cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x7f", + "EventName": "cycles", + "BriefDescription": "Count of L3C cycles", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x80", + "EventName": "cpu_read_l3c_lat", + "Filter": "tt_core=0xff", + "BriefDescription": "Count the total latency that L3C completes the cluster CPU read requests", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x83", + "EventName": "l3c_read_hha_lat", + "Filter": "tt_core=0xff,tt_req=0x4", + "BriefDescription": "Count the total latency that HHA completes the L3C read requests", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xb8", + "EventName": "l3c_ref", + "BriefDescription": "Count number of all CPU accessed L3C", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xb9", + "EventName": "dat_access", + "BriefDescription": "Count number of the cluster CPU accessed L3C", + "Filter": "tt_core=0xff", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc0", + "EventName": "cpu_read_l3c_sum", + "Filter": "tt_core=0xff", + "BriefDescription": "Count of the requests issued by the cluster CPU read L3C", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc3", + "EventName": "l3c_read_hha_sum", + "Filter": "tt_core=0xff,tt_req=0x4", + "BriefDescription": "Count number of L3C read access to HHA", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xce", + "EventName": "l3c_retry_alloc", + "Filter": "tt_core=0xff", + "BriefDescription": "Count of the L3C retry CPU", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "l3c_hit_rate", + "MetricExpr": "l3c_hit / l3c_ref", + "MetricGroup": "L3C", + "BriefDescription": "hit rate of L3C", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "l3c_access_bw", + "MetricExpr": "l3c_ref * 64 / duration_time / 1e6", + "MetricGroup": "L3C_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "cpu_read_l3c_average_lat", + "MetricExpr": "cpu_read_l3c_lat / cpu_read_l3c_sum * (duration_time * 1e9 / l3c_cycles)", + "MetricGroup": "L3C_lat", + "BriefDescription": "Average latency of CPU reading L3C", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "l3c_read_hha_average_lat", + "MetricExpr": "l3c_read_hha_lat / l3c_read_hha_sum * (duration_time * 1e9 / l3c_cycles)", + "MetricGroup": "L3C_lat", + "BriefDescription": "Average latency of L3C reading HHA", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-mn.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-mn.json new file mode 100644 index 000000000000..fac1a3300ef8 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-mn.json @@ -0,0 +1,163 @@ +[ + { + "EventCode": "0x82", + "EventName": "l3t_req_dvm_latency", + "BriefDescription": "Count of total DVM Non-Sync requests latency from L3T", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x09", + "EventName": "l3t_req_dvm_num", + "BriefDescription": "Count the number of DVM Non-Sync requests from L3T", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x83", + "EventName": "l3t_req_dvmsync_latency", + "BriefDescription": "Count of total DVM -Sync requests latency from L3T", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x0A", + "EventName": "l3t_req_dvmsync_num", + "BriefDescription": "Count the number of DVM Sync requests from L3T", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x84", + "EventName": "mn_req_dvm_latency", + "BriefDescription": "Count of total DVM Non-Sync requests latency from others MN", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x0B", + "EventName": "mn_req_dvm_num", + "BriefDescription": "Count the number of DVM Non-Sync requests from others MN", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x85", + "EventName": "mn_req_dvmsync_latency", + "BriefDescription": "Count of total DVM -Sync requests latency from others MN", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x0C", + "EventName": "mn_req_dvmsync_num", + "BriefDescription": "Count the number of DVM Sync requests from others MN", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x86", + "EventName": "pa_req_dvm_latency", + "BriefDescription": "Count of total DVM Non-Sync requests latency from PA", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x0D", + "EventName": "pa_req_dvm_num", + "BriefDescription": "Count the number of DVM Non-Sync requests from PA", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x87", + "EventName": "pa_req_dvmsync_latency", + "BriefDescription": "Count of total DVM -Sync requests latency from PA", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x0E", + "EventName": "pa_req_dvmsync_num", + "BriefDescription": "Count the number of DVM Sync requests from PA", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x00", + "EventName": "req_eobarrier_num", + "BriefDescription": "Count the number of eobarrier requests from CPU", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x01", + "EventName": "req_ecbarrier_num", + "BriefDescription": "Count the number of ecbarrier requests from CPU", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x02", + "EventName": "req_dvmop_num", + "BriefDescription": "Count the number of DVM (DVM Sync + DVM Non-Sync) opention requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x03", + "EventName": "req_dvmsync_num", + "BriefDescription": "Count the number of DVM Sync requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x04", + "EventName": "req_retry_num", + "BriefDescription": "Count the number of DVM retry requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x05", + "EventName": "req_writenosnp_num", + "BriefDescription": "Count the number of writenosnp requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x06", + "EventName": "req_readnosnp_num", + "BriefDescription": "Count the number of readnosnp requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x80", + "EventName": "snp_dvm_latency", + "BriefDescription": "Count of total DVM Non-Sync snoop requests latency", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x07", + "EventName": "snp_dvm_num", + "BriefDescription": "Count the number of DVM Non-Sync snoop requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x81", + "EventName": "snp_dvmsync_latency", + "BriefDescription": "Count of total DVM Sync snoop requests latency", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + }, + { + "EventCode": "0x08", + "EventName": "snp_dvmsync_num", + "BriefDescription": "Count the number of DVM Sync snoop requests", + "Compat": "0x00000000", + "Unit": "hisi_scl,mn" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-noc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-noc.json new file mode 100644 index 000000000000..c45edcb8ebf9 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-noc.json @@ -0,0 +1,158 @@ +[ + { + "EventCode": "0x0e", + "EventName": "noc_cycles", + "BriefDescription": "Count of noc cycles", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "EventCode": "0x0e", + "EventName": "cycles", + "BriefDescription": "Count of noc cycles", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "EventCode": "0x01", + "EventName": "cw_ingress_fail", + "BriefDescription": "Count the number of retry data flits clockwise from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "EventCode": "0x03", + "EventName": "cw_egress_fail", + "BriefDescription": "Count the number of retry data flits clockwise from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "EventCode": "0x09", + "EventName": "cc_ingress_fail", + "BriefDescription": "Count the number of retry data flits counterclockwise from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "EventCode": "0x0b", + "EventName": "cc_egress_fail", + "BriefDescription": "Count the number of retry data flits counterclockwise from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "EventCode": "0x05", + "EventName": "cw_main_flow_sum", + "BriefDescription": "Count the number of clockwise main Ring data flits", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "EventCode": "0x0d", + "EventName": "cc_main_flow_sum", + "BriefDescription": "Count the number of counterclockwise main Ring data flits", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "EventCode": "0x12", + "EventName": "egress_buf_full", + "BriefDescription": "Count the number of data buffer full from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "EventCode": "0x17", + "EventName": "egress_flow_sum", + "BriefDescription": "Count the number of data flits from Ring to subsys", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "EventCode": "0x19", + "EventName": "ingress_buf_full", + "BriefDescription": "Count the number of data buffer full from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "EventCode": "0x1a", + "EventName": "ingress_flow_sum", + "BriefDescription": "Count the number of data flits from subsys to Ring", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "ingress_flow_bw", + "MetricExpr": "ingress_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NOC_bw", + "BriefDescription": "Average data bandwidth from subsys to Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "ingress_flow_bw_occupancy", + "MetricExpr": "ingress_flow_sum / noc_cycles", + "MetricGroup": "NOC_bw", + "BriefDescription": "Average data bandwidth occupancy from subsys to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "egress_flow_bw", + "MetricExpr": "egress_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NOC_bw", + "BriefDescription": "Average data bandwidth from Ring to subsys", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "egress_flow_bw_occupancy", + "MetricExpr": "egress_flow_sum / noc_cycles", + "MetricGroup": "NOC_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to subsys", + "ScaleUnit": "100%", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "cw_main_flow_bw", + "MetricExpr": "cw_main_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NOC_bw", + "BriefDescription": "Average data bandwidth of clockwise main Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "cw_main_flow_bw_occupancy", + "MetricExpr": "cw_main_flow_sum / noc_cycles", + "MetricGroup": "NOC_bw", + "BriefDescription": "Average data bandwidth occupancy of clockwise main Ring", + "ScaleUnit": "100%", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "cw_main_flow_bw", + "MetricExpr": "cc_main_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NOC_bw", + "BriefDescription": "Average data bandwidth of counterclockwise main Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "cw_main_flow_bw_occupancy", + "MetricExpr": "cc_main_flow_sum / noc_cycles", + "MetricGroup": "NOC_bw", + "BriefDescription": "Average data bandwidth occupancy of counterclockwise main Ring", + "ScaleUnit": "100%", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-pa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-pa.json new file mode 100644 index 000000000000..0126043edb77 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-pa.json @@ -0,0 +1,274 @@ +[ + { + "EventCode": "0x00", + "EventName": "tx_req", + "BriefDescription": "Count of the requests transmitted by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x01", + "EventName": "tx_dat", + "BriefDescription": "Count of the data transmitted by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x02", + "EventName": "tx_snp", + "BriefDescription": "Count of the snoopy transmitted by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x07", + "EventName": "rx_req", + "BriefDescription": "Count of the requests received by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x08", + "EventName": "rx_dat", + "BriefDescription": "Count of the data received by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x09", + "EventName": "rx_snp", + "BriefDescription": "Count of the snoopy received by PA", + "Compat": "0x00000040", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x78", + "EventName": "pa_cycles", + "BriefDescription": "Count of PA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x78", + "EventName": "cycle", + "BriefDescription": "Count of PA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x40", + "EventName": "rx_req", + "BriefDescription": "Count of the requests flit from Ring to PA link0", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x40", + "EventName": "pa_rx_req_link0", + "BriefDescription": "Count of the requests flit from Ring to PA link0", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x41", + "EventName": "pa_rx_req_link1", + "BriefDescription": "Count of the requests flit from Ring to PA link1", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x42", + "EventName": "pa_rx_req_link2", + "BriefDescription": "Count of the requests flit from Ring to PA link2", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x43", + "EventName": "pa_rx_req_link3", + "BriefDescription": "Count of the requests flit from Ring to PA link3", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x44", + "EventName": "pa_rx_data_link0", + "BriefDescription": "Count of the data flit from Ring to PA link0", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x45", + "EventName": "pa_rx_data_link1", + "BriefDescription": "Count of the data flit from Ring to PA link1", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x46", + "EventName": "pa_rx_data_link2", + "BriefDescription": "Count of the data flit from Ring to PA link2", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x47", + "EventName": "pa_rx_data_link3", + "BriefDescription": "Count of the data flit from Ring to PA link3", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x5c", + "EventName": "tx_req", + "BriefDescription": "Count of the total flit transmitted by PA link0", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x60", + "EventName": "pa_tx_req_link0", + "BriefDescription": "Count of the requests flit from PA link0 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x61", + "EventName": "pa_tx_req_link1", + "BriefDescription": "Count of the requests flit from PA link1 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x62", + "EventName": "pa_tx_req_link2", + "BriefDescription": "Count of the requests flit from PA link2 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x63", + "EventName": "pa_tx_req_link3", + "BriefDescription": "Count of the requests flit from PA link3 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x64", + "EventName": "pa_tx_data_link0", + "BriefDescription": "Count of the data flit from PA link0 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x65", + "EventName": "pa_tx_data_link1", + "BriefDescription": "Count of the data flit from PA link1 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x66", + "EventName": "pa_tx_data_link2", + "BriefDescription": "Count of the data flit from PA link2 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "EventCode": "0x67", + "EventName": "pa_tx_data_link3", + "BriefDescription": "Count of the data flit from PA link3 to Ring", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_bw", + "MetricExpr": "(pa_rx_data_link0 + pa_rx_data_link1 + pa_rx_data_link2 + pa_rx_data_link3) * 20 / duration_time / 1e6", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth from Ring to PA", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_bw", + "MetricExpr": "(pa_tx_data_link0 + pa_tx_data_link1 + pa_tx_data_link2 + pa_tx_data_link3) * 20 / duration_time / 1e6", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth from PA to Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link0_bw_occupancy", + "MetricExpr": "pa_rx_data_link0 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link0", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link1_bw_occupancy", + "MetricExpr": "pa_rx_data_link1 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link1", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link2_bw_occupancy", + "MetricExpr": "pa_rx_data_link2 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link2", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link3_bw_occupancy", + "MetricExpr": "pa_rx_data_link3 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link3", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link0_bw_occupancy", + "MetricExpr": "pa_tx_data_link0 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link0 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link1_bw_occupancy", + "MetricExpr": "pa_tx_data_link1 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link1 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link2_bw_occupancy", + "MetricExpr": "pa_tx_data_link2 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link2 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link3_bw_occupancy", + "MetricExpr": "pa_tx_data_link3 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link3 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-sllc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-sllc.json new file mode 100644 index 000000000000..18b18e46c4ec --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-sllc.json @@ -0,0 +1,204 @@ +[ + { + "EventCode": "0x09", + "EventName": "sllc_cycles", + "BriefDescription": "Count of SLLC cycles", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x09", + "EventName": "cycles", + "BriefDescription": "Count of SLLC cycles", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x20", + "EventName": "sllc_rx_req_lat", + "BriefDescription": "Total latency SLLC taken to receive requests", + "Filter": "tracetag_en", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x21", + "EventName": "sllc_rx_data_lat", + "BriefDescription": "Total latency SLLC taken to receive data", + "Filter": "tracetag_en", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x24", + "EventName": "sllc_tx_req_lat", + "BriefDescription": "Total latency SLLC taken to transmit requests", + "Filter": "tracetag_en", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x25", + "EventName": "sllc_tx_data_lat", + "BriefDescription": "Total latency SLLC taken to transmit data", + "Filter": "tracetag_en", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x30", + "EventName": "rx_req", + "BriefDescription": "Count of the requests received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x30", + "EventName": "sllc_rx_req", + "BriefDescription": "Count of the requests received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x31", + "EventName": "rx_data", + "BriefDescription": "Count of the data received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x31", + "EventName": "sllc_rx_data", + "BriefDescription": "Count of the data received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x32", + "EventName": "sllc_rx_snp", + "BriefDescription": "Count of the snoop received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x33", + "EventName": "sllc_rx_rsp", + "BriefDescription": "Count of the response received by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x34", + "EventName": "tx_req", + "BriefDescription": "Count of the requests transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x34", + "EventName": "sllc_tx_req", + "BriefDescription": "Count of the requests transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x35", + "EventName": "tx_data", + "BriefDescription": "Count of the data transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x35", + "EventName": "sllc_tx_data", + "BriefDescription": "Count of the data transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x36", + "EventName": "sllc_tx_snp", + "BriefDescription": "Count of the snoop transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "EventCode": "0x37", + "EventName": "sllc_tx_rsp", + "BriefDescription": "Count of the response transmitted by SLLC", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_req_average_lat", + "MetricExpr": "sllc_rx_req_lat / sllc_rx_req * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC receive requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_data_average_lat", + "MetricExpr": "sllc_rx_data_lat / sllc_rx_data * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC receive data", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_req_average_lat", + "MetricExpr": "sllc_tx_req_lat / sllc_tx_req * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC transmit requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_data_average_lat", + "MetricExpr": "sllc_tx_data_lat / sllc_tx_data * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC transmit data", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_bw", + "MetricExpr": "sllc_rx_data * 64 / duration_time / 1e6", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth of SLLC receive data", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_bw_occupancy", + "MetricExpr": "sllc_rx_data / sllc_cycles", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth occupancy of SLLC receive data", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_bw", + "MetricExpr": "sllc_tx_data * 64 / duration_time / 1e6", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth of SLLC transmit data", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_bw_occupancy", + "MetricExpr": "sllc_tx_data / sllc_cycles", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth occupancy of SLLC transmit data", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + } +] -- 2.43.0

From: Yicong Yang <yangyicong@hisilicon.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- .../arm64/hisilicon/hip09/sys/uncore-uc.json | 238 +++++++++++++++++- 1 file changed, 234 insertions(+), 4 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-uc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-uc.json index 42e64ecbc4b3..27c7625e2638 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-uc.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-uc.json @@ -67,6 +67,13 @@ "Compat": "0x00000030", "Unit": "hisi_sccl,uc" }, + { + "EventCode": "0x18", + "EventName": "cpu_rd128", + "BriefDescription": "Count of the number of the cpu_rd128 request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, { "EventCode": "0x19", "EventName": "cpu_rs64", @@ -74,6 +81,13 @@ "Compat": "0x00000030", "Unit": "hisi_sccl,uc" }, + { + "EventCode": "0x1a", + "EventName": "cpu_rs128", + "BriefDescription": "Count of the number of the cpu_rs128 request that come from cpu", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, { "EventCode": "0x1C", "EventName": "cpu_mru", @@ -102,6 +116,34 @@ "Compat": "0x00000030", "Unit": "hisi_sccl,uc" }, + { + "EventCode": "0x33", + "EventName": "ext2uc_ru64", + "BriefDescription": "Count of the number of the 64B ReadUnique request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x34", + "EventName": "ext2uc_ru128", + "BriefDescription": "Count of the number of the 128B ReadUnique request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x35", + "EventName": "ext2uc_rs64", + "BriefDescription": "Count of the number of the 64B ReadShared request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0x36", + "EventName": "ext2uc_rs128", + "BriefDescription": "Count of the number of the 128B ReadShared request that come from ext", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, { "EventCode": "0x47", "EventName": "uc2ext_read_uring", @@ -263,20 +305,118 @@ "Compat": "0x00000030", "Unit": "hisi_sccl,uc" }, + { + "EventCode": "0xB1", + "EventName": "hpipe_lookup", + "BriefDescription": "Count of SPIPE lookup", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, { "EventCode": "0xB3", - "EventName": "spipe_hit", + "EventName": "hpipe_hit", "BriefDescription": "Count of the number of spipe hit", "Compat": "0x00000030", "Unit": "hisi_sccl,uc" }, + { + "EventCode": "0xB4", + "EventName": "hpipe_rd_hit", + "BriefDescription": "Count of SPIPE read hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xB5", + "EventName": "hpipe_wr_hit", + "BriefDescription": "Count of SPIPE write hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xBA", + "EventName": "hc_pipe_lookup", + "BriefDescription": "Count of HC_PIPE lookup", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xBB", + "EventName": "hc_pipe_hit_1k", + "BriefDescription": "Count of HC_PIPE hit 1k", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xBD", + "EventName": "hc_pipe_rd_hit", + "BriefDescription": "Count of HC_PIPE read hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xBE", + "EventName": "hc_pipe_wr_hit", + "BriefDescription": "Count of HC_PIPE write hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xCE", + "EventName": "sc_pipe_lookup", + "BriefDescription": "Count of SC_PIPE lookup", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xCF", + "EventName": "sc_pipe_hit_sector", + "BriefDescription": "Count of SC_PIPE hit sector", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xD1", + "EventName": "sc_pipe_rd_hit", + "BriefDescription": "Count of SC_PIPE read hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xD2", + "EventName": "sc_pipe_wr_hit", + "BriefDescription": "Count of SC_PIPE write hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xD9", + "EventName": "spipe_lookup", + "BriefDescription": "Count of HPIPE lookup", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, { "EventCode": "0xDB", - "EventName": "hpipe_hit", + "EventName": "spipe_hit", "BriefDescription": "Count of the number of hpipe hit", "Compat": "0x00000030", "Unit": "hisi_sccl,uc" }, + { + "EventCode": "0xDC", + "EventName": "spipe_rd_hit", + "BriefDescription": "Count of HPIPE read hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "EventCode": "0xDD", + "EventName": "spipe_wr_hit", + "BriefDescription": "Count of HPIPE write hit", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, { "EventCode": "0xFA", "EventName": "cring_rxdat_cnt", @@ -355,11 +495,29 @@ "Compat": "0x00000030", "Unit": "hisi_sccl,uc" }, + { + "MetricName": "uc2uring_rx_merge_dat_bw", + "MetricExpr": "uring_rxreqdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC received merged data bandwidth", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2uring_tx_merge_dat_bw", + "MetricExpr": "uring_txreqdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC transmit merged data bandwidth", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, { "MetricName": "uc2hbm_rd_bw", "MetricExpr": "(uc2hbm_bank0_rd64 * 64 + uc2hbm_bank0_rd128 * 128 + uc2hbm_bank1_rd64 * 64 + uc2hbm_bank1_rd128 * 128) / duration_time / 1e6", "MetricGroup": "UC_bw", - "BriefDescription": "Average latency of UC reading HBM", + "BriefDescription": "Average bandwidth of UC reading HBM", "ScaleUnit": "1MB/s", "Compat": "0x00000030", "Unit": "hisi_sccl,uc" @@ -368,9 +526,81 @@ "MetricName": "uc2hbm_wr_bw", "MetricExpr": "(uc2hbm_bank0_wr64 * 64 + uc2hbm_bank0_wr128 * 128 + uc2hbm_bank1_wr64 * 64 + uc2hbm_bank1_wr128 * 128) / duration_time / 1e6", "MetricGroup": "UC_bw", - "BriefDescription": "Average latency of UC writing HBM", + "BriefDescription": "Average bandwidth of UC writing HBM", "ScaleUnit": "1MB/s", "Compat": "0x00000030", "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "spipe_hit_ratio", + "MetricExpr": "spipe_hit / spipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of SPIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "hpipe_hit_ratio", + "MetricExpr": "hpipe_hit / hpipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of HPIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "hc_pipe_hit_ratio", + "MetricExpr": "hc_pipe_hit_1k / hc_pipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of HC_PIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "sc_pipe_hit_ratio", + "MetricExpr": "sc_pipe_hit_sector / sc_pipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of SC_PIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "cring_rd_concurrency_numa", + "MetricExpr": "(cpu_rd64 + cpu_rd128 + cpu_rs64 + cpu_rs128 + cpu_mru) / duration_time", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC cring on NUMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "cring_rd_concurrency_uma", + "MetricExpr": "(cpu_rd64 + cpu_rd128 + cpu_rs64 + cpu_rs128 + cpu_mru) * cring_txdat_cnt / duration_time / (cring_txdat_cnt + uring_txdat_cnt)", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC cring on UMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uring_rd_concurrency_numa", + "MetricExpr": "(ext2uc_ru64 + ext2uc_ru128 + ext2uc_rs64 + ext2uc_rs128) / duration_time", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC uring on UMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "hbm_read_concurrency", + "MetricExpr": "(2 * (uc2hbm_bank0_rd128 + uc2hbm_bank1_rd128) + uc2hbm_bank0_rd64 + uc2hbm_bank1_rd64) / duration_time", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC uring on UMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" } ] -- 2.43.0

driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- The pmu-event architecture is adjusted. The sys field is used to match events and the cpuid field is used to match metrics. Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- .../hisilicon/hip09/uncore-cpa-metric.json | 20 +++ .../hisilicon/hip09/uncore-ddrc-metric.json | 56 +++++++ .../hisilicon/hip09/uncore-hha-metric.json | 65 ++++++++ .../hisilicon/hip09/uncore-l3c-metric.json | 38 +++++ .../hisilicon/hip09/uncore-pa-metric.json | 92 +++++++++++ .../hisilicon/hip09/uncore-sllc-metric.json | 74 +++++++++ .../hisilicon/hip09/uncore-uc-metric.json | 146 ++++++++++++++++++ .../hisilicon/hip12/uncore-noc-metric.json | 38 +++++ .../sys/uncore-cpa-event.json} | 18 --- .../sys/uncore-ddrc-event.json} | 54 ------- .../sys/uncore-hha-event.json} | 63 -------- .../sys/uncore-l3c-event.json} | 36 ----- .../sys/uncore-mn-event.json} | 0 .../sys/uncore-noc-event.json} | 36 ----- .../sys/uncore-pa-event.json} | 90 ----------- .../sys/uncore-sllc-event.json} | 72 --------- .../sys/uncore-uc-event.json} | 146 +----------------- 17 files changed, 530 insertions(+), 514 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-cpa-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-ddrc-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-hha-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-l3c-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-pa-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-sllc-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-uc-metric.json create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-noc-metric.json rename tools/perf/pmu-events/arch/arm64/hisilicon/{hip09/sys/uncore-cpa.json => hipxx/sys/uncore-cpa-event.json} (73%) rename tools/perf/pmu-events/arch/arm64/hisilicon/{hip09/sys/uncore-ddrc.json => hipxx/sys/uncore-ddrc-event.json} (59%) rename tools/perf/pmu-events/arch/arm64/hisilicon/{hip09/sys/uncore-hha.json => hipxx/sys/uncore-hha-event.json} (64%) rename tools/perf/pmu-events/arch/arm64/hisilicon/{hip09/sys/uncore-l3c.json => hipxx/sys/uncore-l3c-event.json} (71%) rename tools/perf/pmu-events/arch/arm64/hisilicon/{hip09/sys/uncore-mn.json => hipxx/sys/uncore-mn-event.json} (100%) rename tools/perf/pmu-events/arch/arm64/hisilicon/{hip12/sys/uncore-noc.json => hipxx/sys/uncore-noc-event.json} (89%) rename tools/perf/pmu-events/arch/arm64/hisilicon/{hip09/sys/uncore-pa.json => hipxx/sys/uncore-pa-event.json} (62%) rename tools/perf/pmu-events/arch/arm64/hisilicon/{hip09/sys/uncore-sllc.json => hipxx/sys/uncore-sllc-event.json} (59%) rename tools/perf/pmu-events/arch/arm64/hisilicon/{hip09/sys/uncore-uc.json => hipxx/sys/uncore-uc-event.json} (73%) diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-cpa-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-cpa-metric.json new file mode 100644 index 000000000000..1ead2819abe0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-cpa-metric.json @@ -0,0 +1,20 @@ +[ + { + "MetricName": "cpa_p1_avg_bw", + "MetricExpr": "(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / duration_time / 1e6", + "BriefDescription": "Average bandwidth of CPA Port 1", + "MetricGroup": "CPA_bw", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "MetricName": "cpa_p0_avg_bw", + "MetricExpr": "(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / duration_time / 1e6", + "BriefDescription": "Average bandwidth of CPA Port 0", + "MetricGroup": "CPA_bw", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-ddrc-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-ddrc-metric.json new file mode 100644 index 000000000000..b4a95fd53b76 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-ddrc-metric.json @@ -0,0 +1,56 @@ +[ + { + "MetricName": "ddrc_write_bw", + "MetricExpr": "flux_wr * 32 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of write DDRC memory", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_read_bw", + "MetricExpr": "flux_rd * 32 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of read DDRC memory", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_rdwr_bw", + "MetricExpr": "(flux_wr + flux_rd) * 32 / duration_time / 1e6", + "MetricGroup": "DDRC_bw", + "BriefDescription": "Average bandwidth of DDRC (including memory read and write)", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_read_lat", + "MetricExpr": "ddrc_read_cmd_occupancy / ddrc_read_cmd * (duration_time * 1e9 / ddrc_cycles)", + "MetricGroup": "DDRC_lat", + "BriefDescription": "Average scheduling latency of DDRC read command", + "ScaleUnit": "1ns", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_write_lat", + "MetricExpr": "ddrc_write_cmd_occupancy / ddrc_write_cmd * (duration_time * 1e9 / ddrc_cycles)", + "MetricGroup": "DDRC_lat", + "BriefDescription": "Average scheduling of DDRC write command", + "ScaleUnit": "1ns", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + }, + { + "MetricName": "ddrc_rowhit_rate", + "MetricExpr": "1 - ddrc_active_cmd / ddrc_cas_cmd", + "MetricGroup": "DDRC", + "BriefDescription": "Row hit rate of DDRC", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,ddrc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-hha-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-hha-metric.json new file mode 100644 index 000000000000..1232f30f5b0a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-hha-metric.json @@ -0,0 +1,65 @@ +[ + { + "MetricName": "hha_read_ddrc_bw", + "MetricExpr": "(hha_rd_ddr_64b * 64 + hha_rd_ddr_128b * 128) / duration_time / 1e6", + "MetricGroup": "HHA_bw", + "BriefDescription": "Average bandwidth of reading DDRC", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_write_ddrc_bw", + "MetricExpr": "(hha_wr_ddr_64b * 64 + hha_wr_ddr_128b * 128) / duration_time / 1e6", + "MetricGroup": "HHA_bw", + "BriefDescription": "Average bandwidth of writing DDRC", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_cross_chip_ops_rate", + "MetricExpr": "rx_outer / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of cross-chip operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_cross_die_ops_rate", + "MetricExpr": "rx_sccl / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of cross-die operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_channel0_ops_rate", + "MetricExpr": "hha_rx_ch0 / rx_ops_num", + "MetricGroup": "HHA", + "BriefDescription": "Rate of channel 0 operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_channel1_ops_rate", + "MetricExpr": "hha_rx_ch1 / rx_ops_num", + "MetricGroup": "HHA_lat", + "BriefDescription": "Rate of channel 1 operations received by HHA", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + }, + { + "MetricName": "hha_req_average_lat", + "MetricExpr": "hha_req_lat / hha_req_cnt * (duration_time * 1e9 / hha_cycles)", + "MetricGroup": "HHA_lat", + "BriefDescription": "Average latency that HHA completes all requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,hha" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-l3c-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-l3c-metric.json new file mode 100644 index 000000000000..86cdb39501a1 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-l3c-metric.json @@ -0,0 +1,38 @@ +[ + { + "MetricName": "l3c_hit_rate", + "MetricExpr": "l3c_hit / l3c_ref", + "MetricGroup": "L3C", + "BriefDescription": "hit rate of L3C", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "l3c_access_bw", + "MetricExpr": "l3c_ref * 64 / duration_time / 1e6", + "MetricGroup": "L3C_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "cpu_read_l3c_average_lat", + "MetricExpr": "cpu_read_l3c_lat / cpu_read_l3c_sum * (duration_time * 1e9 / l3c_cycles)", + "MetricGroup": "L3C_lat", + "BriefDescription": "Average latency of CPU reading L3C", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + }, + { + "MetricName": "l3c_read_hha_average_lat", + "MetricExpr": "l3c_read_hha_lat / l3c_read_hha_sum * (duration_time * 1e9 / l3c_cycles)", + "MetricGroup": "L3C_lat", + "BriefDescription": "Average latency of L3C reading HHA", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,l3c" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-pa-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-pa-metric.json new file mode 100644 index 000000000000..94846f1812c0 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-pa-metric.json @@ -0,0 +1,92 @@ +[ + { + "MetricName": "pa_rx_bw", + "MetricExpr": "(pa_rx_data_link0 + pa_rx_data_link1 + pa_rx_data_link2 + pa_rx_data_link3) * 20 / duration_time / 1e6", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth from Ring to PA", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_bw", + "MetricExpr": "(pa_tx_data_link0 + pa_tx_data_link1 + pa_tx_data_link2 + pa_tx_data_link3) * 20 / duration_time / 1e6", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth from PA to Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link0_bw_occupancy", + "MetricExpr": "pa_rx_data_link0 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link0", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link1_bw_occupancy", + "MetricExpr": "pa_rx_data_link1 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link1", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link2_bw_occupancy", + "MetricExpr": "pa_rx_data_link2 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link2", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_rx_link3_bw_occupancy", + "MetricExpr": "pa_rx_data_link3 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from Ring to PA link3", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link0_bw_occupancy", + "MetricExpr": "pa_tx_data_link0 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link0 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link1_bw_occupancy", + "MetricExpr": "pa_tx_data_link1 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link1 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link2_bw_occupancy", + "MetricExpr": "pa_tx_data_link2 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link2 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + }, + { + "MetricName": "pa_tx_link3_bw_occupancy", + "MetricExpr": "pa_tx_data_link3 / pa_cycles", + "MetricGroup": "PA_bw", + "BriefDescription": "Average data bandwidth occupancy from PA link3 to Ring", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sicl,pa" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-sllc-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-sllc-metric.json new file mode 100644 index 000000000000..62f9abc078d2 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-sllc-metric.json @@ -0,0 +1,74 @@ +[ + { + "MetricName": "sllc_rx_req_average_lat", + "MetricExpr": "sllc_rx_req_lat / sllc_rx_req * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC receive requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_data_average_lat", + "MetricExpr": "sllc_rx_data_lat / sllc_rx_data * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC receive data", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_req_average_lat", + "MetricExpr": "sllc_tx_req_lat / sllc_tx_req * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC transmit requests", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_data_average_lat", + "MetricExpr": "sllc_tx_data_lat / sllc_tx_data * (duration_time * 1e9 / sllc_cycles)", + "MetricGroup": "sllc_lat", + "BriefDescription": "Average latency of SLLC transmit data", + "ScaleUnit": "1ns", + "Compat": "0x00000030", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_bw", + "MetricExpr": "sllc_rx_data * 64 / duration_time / 1e6", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth of SLLC receive data", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_rx_bw_occupancy", + "MetricExpr": "sllc_rx_data / sllc_cycles", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth occupancy of SLLC receive data", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_bw", + "MetricExpr": "sllc_tx_data * 64 / duration_time / 1e6", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth of SLLC transmit data", + "ScaleUnit": "1MB/s", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + }, + { + "MetricName": "sllc_tx_bw_occupancy", + "MetricExpr": "sllc_tx_data / sllc_cycles", + "MetricGroup": "sllc_bw", + "BriefDescription": "Average bandwidth occupancy of SLLC transmit data", + "ScaleUnit": "100%", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,sllc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-uc-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-uc-metric.json new file mode 100644 index 000000000000..5e1be1623c2b --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/uncore-uc-metric.json @@ -0,0 +1,146 @@ +[ + { + "MetricName": "uc2cring_rxdat_bw", + "MetricExpr": "cring_rxdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC access CRing", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2cring_txdat_bw", + "MetricExpr": "cring_txdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2uring_rxdat_bw", + "MetricExpr": "uring_rxdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2uring_txdat_bw", + "MetricExpr": "uring_txdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of CPU access L3C", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2uring_rx_merge_dat_bw", + "MetricExpr": "uring_rxreqdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC received merged data bandwidth", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2uring_tx_merge_dat_bw", + "MetricExpr": "uring_txreqdat_cnt * 64 / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC transmit merged data bandwidth", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2hbm_rd_bw", + "MetricExpr": "(uc2hbm_bank0_rd64 * 64 + uc2hbm_bank0_rd128 * 128 + uc2hbm_bank1_rd64 * 64 + uc2hbm_bank1_rd128 * 128) / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC reading HBM", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uc2hbm_wr_bw", + "MetricExpr": "(uc2hbm_bank0_wr64 * 64 + uc2hbm_bank0_wr128 * 128 + uc2hbm_bank1_wr64 * 64 + uc2hbm_bank1_wr128 * 128) / duration_time / 1e6", + "MetricGroup": "UC_bw", + "BriefDescription": "Average bandwidth of UC writing HBM", + "ScaleUnit": "1MB/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "spipe_hit_ratio", + "MetricExpr": "spipe_hit / spipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of SPIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "hpipe_hit_ratio", + "MetricExpr": "hpipe_hit / hpipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of HPIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "hc_pipe_hit_ratio", + "MetricExpr": "hc_pipe_hit_1k / hc_pipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of HC_PIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "sc_pipe_hit_ratio", + "MetricExpr": "sc_pipe_hit_sector / sc_pipe_lookup", + "MetricGroup": "UC_hit_ratio", + "BriefDescription": "Hit ratio of SC_PIPE", + "ScaleUnit": "100%", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "cring_rd_concurrency_numa", + "MetricExpr": "(cpu_rd64 + cpu_rd128 + cpu_rs64 + cpu_rs128 + cpu_mru) / duration_time", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC cring on NUMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "cring_rd_concurrency_uma", + "MetricExpr": "(cpu_rd64 + cpu_rd128 + cpu_rs64 + cpu_rs128 + cpu_mru) * cring_txdat_cnt / duration_time / (cring_txdat_cnt + uring_txdat_cnt)", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC cring on UMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "uring_rd_concurrency_numa", + "MetricExpr": "(ext2uc_ru64 + ext2uc_ru128 + ext2uc_rs64 + ext2uc_rs128) / duration_time", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC uring on UMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + }, + { + "MetricName": "hbm_read_concurrency", + "MetricExpr": "(2 * (uc2hbm_bank0_rd128 + uc2hbm_bank1_rd128) + uc2hbm_bank0_rd64 + uc2hbm_bank1_rd64) / duration_time", + "MetricGroup": "UC_concurrency", + "BriefDescription": "Concurrency of read requests from UC uring on UMA mode", + "ScaleUnit": "1req/s", + "Compat": "0x00000030", + "Unit": "hisi_sccl,uc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-noc-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-noc-metric.json new file mode 100644 index 000000000000..4cee78c5880c --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-noc-metric.json @@ -0,0 +1,38 @@ +[ + { + "MetricName": "ingress_flow_bw", + "MetricExpr": "ingress_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NoC_bw", + "BriefDescription": "Average data bandwidth from subsys to Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "egress_flow_bw", + "MetricExpr": "egress_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NoC_bw", + "BriefDescription": "Average data bandwidth from Ring to subsys", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "cw_main_flow_bw", + "MetricExpr": "cw_main_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NoC_bw", + "BriefDescription": "Average data bandwidth of clockwise main Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + }, + { + "MetricName": "cc_main_flow_bw", + "MetricExpr": "cc_main_flow_sum * 64 / duration_time / 1e6", + "MetricGroup": "NoC_bw", + "BriefDescription": "Average data bandwidth of counterclockwise main Ring", + "ScaleUnit": "1MB/s", + "Compat": "0x00000000", + "Unit": "hisi_scl,noc" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-cpa-event.json similarity index 73% rename from tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json rename to tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-cpa-event.json index 705efb48f99b..1103741b921b 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-cpa-event.json @@ -61,23 +61,5 @@ "BriefDescription": "Number of read ops transmitted by the P0 port which size is 32 bytes", "Compat": "0x00000030", "Unit": "hisi_sicl,cpa" - }, - { - "MetricName": "cpa_p1_avg_bw", - "MetricExpr": "(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / duration_time / 1e6", - "BriefDescription": "Average bandwidth of CPA Port 1", - "MetricGroup": "CPA_bw", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sicl,cpa" - }, - { - "MetricName": "cpa_p0_avg_bw", - "MetricExpr": "(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / duration_time / 1e6", - "BriefDescription": "Average bandwidth of CPA Port 0", - "MetricGroup": "CPA_bw", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sicl,cpa" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-ddrc-event.json similarity index 59% rename from tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json rename to tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-ddrc-event.json index 8facfb35ea89..d172125518f1 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-ddrc.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-ddrc-event.json @@ -96,59 +96,5 @@ "BriefDescription": "Count of DDRC read commands", "Compat": "0x000000(30|40)", "Unit": "hisi_sccl,ddrc" - }, - { - "MetricName": "ddrc_write_bw", - "MetricExpr": "flux_wr * 32 / duration_time / 1e6", - "MetricGroup": "DDRC_bw", - "BriefDescription": "Average bandwidth of write DDRC memory", - "ScaleUnit": "1MB/s", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,ddrc" - }, - { - "MetricName": "ddrc_read_bw", - "MetricExpr": "flux_rd * 32 / duration_time / 1e6", - "MetricGroup": "DDRC_bw", - "BriefDescription": "Average bandwidth of read DDRC memory", - "ScaleUnit": "1MB/s", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,ddrc" - }, - { - "MetricName": "ddrc_rdwr_bw", - "MetricExpr": "(flux_wr + flux_rd) * 32 / duration_time / 1e6", - "MetricGroup": "DDRC_bw", - "BriefDescription": "Average bandwidth of DDRC (including memory read and write)", - "ScaleUnit": "1MB/s", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,ddrc" - }, - { - "MetricName": "ddrc_read_lat", - "MetricExpr": "ddrc_read_cmd_occupancy / ddrc_read_cmd * (duration_time * 1e9 / ddrc_cycles)", - "MetricGroup": "DDRC_lat", - "BriefDescription": "Average scheduling latency of DDRC read command", - "ScaleUnit": "1ns", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,ddrc" - }, - { - "MetricName": "ddrc_write_lat", - "MetricExpr": "ddrc_write_cmd_occupancy / ddrc_write_cmd * (duration_time * 1e9 / ddrc_cycles)", - "MetricGroup": "DDRC_lat", - "BriefDescription": "Average scheduling of DDRC write command", - "ScaleUnit": "1ns", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,ddrc" - }, - { - "MetricName": "ddrc_rowhit_rate", - "MetricExpr": "1 - ddrc_active_cmd / ddrc_cas_cmd", - "MetricGroup": "DDRC", - "BriefDescription": "Row hit rate of DDRC", - "ScaleUnit": "100%", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,ddrc" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-hha-event.json similarity index 64% rename from tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json rename to tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-hha-event.json index c294aeecd2ca..78aed4f2641d 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-hha.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-hha-event.json @@ -124,68 +124,5 @@ "BriefDescription": "Count the total operations that HHA receives", "Compat": "0x00000030", "Unit": "hisi_sccl,hha" - }, - { - "MetricName": "hha_read_ddrc_bw", - "MetricExpr": "(hha_rd_ddr_64b * 64 + hha_rd_ddr_128b * 128) / duration_time / 1e6", - "MetricGroup": "HHA_bw", - "BriefDescription": "Average bandwidth of reading DDRC", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,hha" - }, - { - "MetricName": "hha_write_ddrc_bw", - "MetricExpr": "(hha_wr_ddr_64b * 64 + hha_wr_ddr_128b * 128) / duration_time / 1e6", - "MetricGroup": "HHA_bw", - "BriefDescription": "Average bandwidth of writing DDRC", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,hha" - }, - { - "MetricName": "hha_cross_chip_ops_rate", - "MetricExpr": "rx_outer / rx_ops_num", - "MetricGroup": "HHA", - "BriefDescription": "Rate of cross-chip operations received by HHA", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sccl,hha" - }, - { - "MetricName": "hha_cross_die_ops_rate", - "MetricExpr": "rx_sccl / rx_ops_num", - "MetricGroup": "HHA", - "BriefDescription": "Rate of cross-die operations received by HHA", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sccl,hha" - }, - { - "MetricName": "hha_channel0_ops_rate", - "MetricExpr": "hha_rx_ch0 / rx_ops_num", - "MetricGroup": "HHA", - "BriefDescription": "Rate of channel 0 operations received by HHA", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sccl,hha" - }, - { - "MetricName": "hha_channel1_ops_rate", - "MetricExpr": "hha_rx_ch1 / rx_ops_num", - "MetricGroup": "HHA_lat", - "BriefDescription": "Rate of channel 1 operations received by HHA", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sccl,hha" - }, - { - "MetricName": "hha_req_average_lat", - "MetricExpr": "hha_req_lat / hha_req_cnt * (duration_time * 1e9 / hha_cycles)", - "MetricGroup": "HHA_lat", - "BriefDescription": "Average latency that HHA completes all requests", - "ScaleUnit": "1ns", - "Compat": "0x00000030", - "Unit": "hisi_sccl,hha" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c-event.json similarity index 71% rename from tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json rename to tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c-event.json index 1d905beec448..5cdc5a5db533 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-l3c.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c-event.json @@ -102,41 +102,5 @@ "BriefDescription": "Count of the L3C retry CPU", "Compat": "0x00000030", "Unit": "hisi_sccl,l3c" - }, - { - "MetricName": "l3c_hit_rate", - "MetricExpr": "l3c_hit / l3c_ref", - "MetricGroup": "L3C", - "BriefDescription": "hit rate of L3C", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sccl,l3c" - }, - { - "MetricName": "l3c_access_bw", - "MetricExpr": "l3c_ref * 64 / duration_time / 1e6", - "MetricGroup": "L3C_bw", - "BriefDescription": "Average bandwidth of CPU access L3C", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,l3c" - }, - { - "MetricName": "cpu_read_l3c_average_lat", - "MetricExpr": "cpu_read_l3c_lat / cpu_read_l3c_sum * (duration_time * 1e9 / l3c_cycles)", - "MetricGroup": "L3C_lat", - "BriefDescription": "Average latency of CPU reading L3C", - "ScaleUnit": "1ns", - "Compat": "0x00000030", - "Unit": "hisi_sccl,l3c" - }, - { - "MetricName": "l3c_read_hha_average_lat", - "MetricExpr": "l3c_read_hha_lat / l3c_read_hha_sum * (duration_time * 1e9 / l3c_cycles)", - "MetricGroup": "L3C_lat", - "BriefDescription": "Average latency of L3C reading HHA", - "ScaleUnit": "1ns", - "Compat": "0x00000030", - "Unit": "hisi_sccl,l3c" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-mn.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-mn-event.json similarity index 100% rename from tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-mn.json rename to tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-mn-event.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/sys/uncore-noc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-noc-event.json similarity index 89% rename from tools/perf/pmu-events/arch/arm64/hisilicon/hip12/sys/uncore-noc.json rename to tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-noc-event.json index bcdcac9e25ab..5d998dbe963b 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/sys/uncore-noc.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-noc-event.json @@ -325,41 +325,5 @@ "BriefDescription": "Count the number of data channel retry data flits counterclockwise from Ring to subsys", "Compat": "0x00000000", "Unit": "hisi_scl,noc" - }, - { - "MetricName": "ingress_flow_bw", - "MetricExpr": "ingress_flow_sum * 64 / duration_time / 1e6", - "MetricGroup": "NoC_bw", - "BriefDescription": "Average data bandwidth from subsys to Ring", - "ScaleUnit": "1MB/s", - "Compat": "0x00000000", - "Unit": "hisi_scl,noc" - }, - { - "MetricName": "egress_flow_bw", - "MetricExpr": "egress_flow_sum * 64 / duration_time / 1e6", - "MetricGroup": "NoC_bw", - "BriefDescription": "Average data bandwidth from Ring to subsys", - "ScaleUnit": "1MB/s", - "Compat": "0x00000000", - "Unit": "hisi_scl,noc" - }, - { - "MetricName": "cw_main_flow_bw", - "MetricExpr": "cw_main_flow_sum * 64 / duration_time / 1e6", - "MetricGroup": "NoC_bw", - "BriefDescription": "Average data bandwidth of clockwise main Ring", - "ScaleUnit": "1MB/s", - "Compat": "0x00000000", - "Unit": "hisi_scl,noc" - }, - { - "MetricName": "cc_main_flow_bw", - "MetricExpr": "cc_main_flow_sum * 64 / duration_time / 1e6", - "MetricGroup": "NoC_bw", - "BriefDescription": "Average data bandwidth of counterclockwise main Ring", - "ScaleUnit": "1MB/s", - "Compat": "0x00000000", - "Unit": "hisi_scl,noc" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-pa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-pa-event.json similarity index 62% rename from tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-pa.json rename to tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-pa-event.json index 0126043edb77..b74dc7801142 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-pa.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-pa-event.json @@ -180,95 +180,5 @@ "BriefDescription": "Count of the data flit from PA link3 to Ring", "Compat": "0x00000030", "Unit": "hisi_sicl,pa" - }, - { - "MetricName": "pa_rx_bw", - "MetricExpr": "(pa_rx_data_link0 + pa_rx_data_link1 + pa_rx_data_link2 + pa_rx_data_link3) * 20 / duration_time / 1e6", - "MetricGroup": "PA_bw", - "BriefDescription": "Average data bandwidth from Ring to PA", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sicl,pa" - }, - { - "MetricName": "pa_tx_bw", - "MetricExpr": "(pa_tx_data_link0 + pa_tx_data_link1 + pa_tx_data_link2 + pa_tx_data_link3) * 20 / duration_time / 1e6", - "MetricGroup": "PA_bw", - "BriefDescription": "Average data bandwidth from PA to Ring", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sicl,pa" - }, - { - "MetricName": "pa_rx_link0_bw_occupancy", - "MetricExpr": "pa_rx_data_link0 / pa_cycles", - "MetricGroup": "PA_bw", - "BriefDescription": "Average data bandwidth occupancy from Ring to PA link0", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sicl,pa" - }, - { - "MetricName": "pa_rx_link1_bw_occupancy", - "MetricExpr": "pa_rx_data_link1 / pa_cycles", - "MetricGroup": "PA_bw", - "BriefDescription": "Average data bandwidth occupancy from Ring to PA link1", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sicl,pa" - }, - { - "MetricName": "pa_rx_link2_bw_occupancy", - "MetricExpr": "pa_rx_data_link2 / pa_cycles", - "MetricGroup": "PA_bw", - "BriefDescription": "Average data bandwidth occupancy from Ring to PA link2", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sicl,pa" - }, - { - "MetricName": "pa_rx_link3_bw_occupancy", - "MetricExpr": "pa_rx_data_link3 / pa_cycles", - "MetricGroup": "PA_bw", - "BriefDescription": "Average data bandwidth occupancy from Ring to PA link3", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sicl,pa" - }, - { - "MetricName": "pa_tx_link0_bw_occupancy", - "MetricExpr": "pa_tx_data_link0 / pa_cycles", - "MetricGroup": "PA_bw", - "BriefDescription": "Average data bandwidth occupancy from PA link0 to Ring", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sicl,pa" - }, - { - "MetricName": "pa_tx_link1_bw_occupancy", - "MetricExpr": "pa_tx_data_link1 / pa_cycles", - "MetricGroup": "PA_bw", - "BriefDescription": "Average data bandwidth occupancy from PA link1 to Ring", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sicl,pa" - }, - { - "MetricName": "pa_tx_link2_bw_occupancy", - "MetricExpr": "pa_tx_data_link2 / pa_cycles", - "MetricGroup": "PA_bw", - "BriefDescription": "Average data bandwidth occupancy from PA link2 to Ring", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sicl,pa" - }, - { - "MetricName": "pa_tx_link3_bw_occupancy", - "MetricExpr": "pa_tx_data_link3 / pa_cycles", - "MetricGroup": "PA_bw", - "BriefDescription": "Average data bandwidth occupancy from PA link3 to Ring", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sicl,pa" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-sllc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-sllc-event.json similarity index 59% rename from tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-sllc.json rename to tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-sllc-event.json index 18b18e46c4ec..745d649501fc 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-sllc.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-sllc-event.json @@ -128,77 +128,5 @@ "BriefDescription": "Count of the response transmitted by SLLC", "Compat": "0x000000(30|40)", "Unit": "hisi_sccl,sllc" - }, - { - "MetricName": "sllc_rx_req_average_lat", - "MetricExpr": "sllc_rx_req_lat / sllc_rx_req * (duration_time * 1e9 / sllc_cycles)", - "MetricGroup": "sllc_lat", - "BriefDescription": "Average latency of SLLC receive requests", - "ScaleUnit": "1ns", - "Compat": "0x00000030", - "Unit": "hisi_sccl,sllc" - }, - { - "MetricName": "sllc_rx_data_average_lat", - "MetricExpr": "sllc_rx_data_lat / sllc_rx_data * (duration_time * 1e9 / sllc_cycles)", - "MetricGroup": "sllc_lat", - "BriefDescription": "Average latency of SLLC receive data", - "ScaleUnit": "1ns", - "Compat": "0x00000030", - "Unit": "hisi_sccl,sllc" - }, - { - "MetricName": "sllc_tx_req_average_lat", - "MetricExpr": "sllc_tx_req_lat / sllc_tx_req * (duration_time * 1e9 / sllc_cycles)", - "MetricGroup": "sllc_lat", - "BriefDescription": "Average latency of SLLC transmit requests", - "ScaleUnit": "1ns", - "Compat": "0x00000030", - "Unit": "hisi_sccl,sllc" - }, - { - "MetricName": "sllc_tx_data_average_lat", - "MetricExpr": "sllc_tx_data_lat / sllc_tx_data * (duration_time * 1e9 / sllc_cycles)", - "MetricGroup": "sllc_lat", - "BriefDescription": "Average latency of SLLC transmit data", - "ScaleUnit": "1ns", - "Compat": "0x00000030", - "Unit": "hisi_sccl,sllc" - }, - { - "MetricName": "sllc_rx_bw", - "MetricExpr": "sllc_rx_data * 64 / duration_time / 1e6", - "MetricGroup": "sllc_bw", - "BriefDescription": "Average bandwidth of SLLC receive data", - "ScaleUnit": "1MB/s", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,sllc" - }, - { - "MetricName": "sllc_rx_bw_occupancy", - "MetricExpr": "sllc_rx_data / sllc_cycles", - "MetricGroup": "sllc_bw", - "BriefDescription": "Average bandwidth occupancy of SLLC receive data", - "ScaleUnit": "100%", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,sllc" - }, - { - "MetricName": "sllc_tx_bw", - "MetricExpr": "sllc_tx_data * 64 / duration_time / 1e6", - "MetricGroup": "sllc_bw", - "BriefDescription": "Average bandwidth of SLLC transmit data", - "ScaleUnit": "1MB/s", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,sllc" - }, - { - "MetricName": "sllc_tx_bw_occupancy", - "MetricExpr": "sllc_tx_data / sllc_cycles", - "MetricGroup": "sllc_bw", - "BriefDescription": "Average bandwidth occupancy of SLLC transmit data", - "ScaleUnit": "100%", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,sllc" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-uc.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-uc-event.json similarity index 73% rename from tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-uc.json rename to tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-uc-event.json index 27c7625e2638..076b81ca7a21 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-uc.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-uc-event.json @@ -458,149 +458,5 @@ "BriefDescription": "Count of the number of data combination requests sent by the UC to the uring module", "Compat": "0x00000030", "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "uc2cring_rxdat_bw", - "MetricExpr": "cring_rxdat_cnt * 64 / duration_time / 1e6", - "MetricGroup": "UC_bw", - "BriefDescription": "Average bandwidth of UC access CRing", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "uc2cring_txdat_bw", - "MetricExpr": "cring_txdat_cnt * 64 / duration_time / 1e6", - "MetricGroup": "UC_bw", - "BriefDescription": "Average bandwidth of CPU access L3C", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "uc2uring_rxdat_bw", - "MetricExpr": "uring_rxdat_cnt * 64 / duration_time / 1e6", - "MetricGroup": "UC_bw", - "BriefDescription": "Average bandwidth of CPU access L3C", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "uc2uring_txdat_bw", - "MetricExpr": "uring_txdat_cnt * 64 / duration_time / 1e6", - "MetricGroup": "UC_bw", - "BriefDescription": "Average bandwidth of CPU access L3C", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "uc2uring_rx_merge_dat_bw", - "MetricExpr": "uring_rxreqdat_cnt * 64 / duration_time / 1e6", - "MetricGroup": "UC_bw", - "BriefDescription": "Average bandwidth of UC received merged data bandwidth", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "uc2uring_tx_merge_dat_bw", - "MetricExpr": "uring_txreqdat_cnt * 64 / duration_time / 1e6", - "MetricGroup": "UC_bw", - "BriefDescription": "Average bandwidth of UC transmit merged data bandwidth", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "uc2hbm_rd_bw", - "MetricExpr": "(uc2hbm_bank0_rd64 * 64 + uc2hbm_bank0_rd128 * 128 + uc2hbm_bank1_rd64 * 64 + uc2hbm_bank1_rd128 * 128) / duration_time / 1e6", - "MetricGroup": "UC_bw", - "BriefDescription": "Average bandwidth of UC reading HBM", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "uc2hbm_wr_bw", - "MetricExpr": "(uc2hbm_bank0_wr64 * 64 + uc2hbm_bank0_wr128 * 128 + uc2hbm_bank1_wr64 * 64 + uc2hbm_bank1_wr128 * 128) / duration_time / 1e6", - "MetricGroup": "UC_bw", - "BriefDescription": "Average bandwidth of UC writing HBM", - "ScaleUnit": "1MB/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "spipe_hit_ratio", - "MetricExpr": "spipe_hit / spipe_lookup", - "MetricGroup": "UC_hit_ratio", - "BriefDescription": "Hit ratio of SPIPE", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "hpipe_hit_ratio", - "MetricExpr": "hpipe_hit / hpipe_lookup", - "MetricGroup": "UC_hit_ratio", - "BriefDescription": "Hit ratio of HPIPE", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "hc_pipe_hit_ratio", - "MetricExpr": "hc_pipe_hit_1k / hc_pipe_lookup", - "MetricGroup": "UC_hit_ratio", - "BriefDescription": "Hit ratio of HC_PIPE", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "sc_pipe_hit_ratio", - "MetricExpr": "sc_pipe_hit_sector / sc_pipe_lookup", - "MetricGroup": "UC_hit_ratio", - "BriefDescription": "Hit ratio of SC_PIPE", - "ScaleUnit": "100%", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "cring_rd_concurrency_numa", - "MetricExpr": "(cpu_rd64 + cpu_rd128 + cpu_rs64 + cpu_rs128 + cpu_mru) / duration_time", - "MetricGroup": "UC_concurrency", - "BriefDescription": "Concurrency of read requests from UC cring on NUMA mode", - "ScaleUnit": "1req/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "cring_rd_concurrency_uma", - "MetricExpr": "(cpu_rd64 + cpu_rd128 + cpu_rs64 + cpu_rs128 + cpu_mru) * cring_txdat_cnt / duration_time / (cring_txdat_cnt + uring_txdat_cnt)", - "MetricGroup": "UC_concurrency", - "BriefDescription": "Concurrency of read requests from UC cring on UMA mode", - "ScaleUnit": "1req/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "uring_rd_concurrency_numa", - "MetricExpr": "(ext2uc_ru64 + ext2uc_ru128 + ext2uc_rs64 + ext2uc_rs128) / duration_time", - "MetricGroup": "UC_concurrency", - "BriefDescription": "Concurrency of read requests from UC uring on UMA mode", - "ScaleUnit": "1req/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - }, - { - "MetricName": "hbm_read_concurrency", - "MetricExpr": "(2 * (uc2hbm_bank0_rd128 + uc2hbm_bank1_rd128) + uc2hbm_bank0_rd64 + uc2hbm_bank1_rd64) / duration_time", - "MetricGroup": "UC_concurrency", - "BriefDescription": "Concurrency of read requests from UC uring on UMA mode", - "ScaleUnit": "1req/s", - "Compat": "0x00000030", - "Unit": "hisi_sccl,uc" - } + } ] -- 2.43.0

driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- a) Add support for Hisilicon MN PMU perf metric: · Average latency of dvmsync/no-sync snoop request; · Average latency of dvmsync/no-sync request. Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- .../hisilicon/hip12/uncore-mn-metric.json | 58 +++++++++++++++++++ tools/perf/pmu-events/jevents.py | 1 + 2 files changed, 59 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-mn-metric.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-mn-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-mn-metric.json new file mode 100644 index 000000000000..8d68ce7ffb31 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-mn-metric.json @@ -0,0 +1,58 @@ +[ + { + "MetricName": "snp_dvm_average_latency", + "MetricExpr": "snp_dvm_latency / snp_dvm_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Non-Sync snoop request average latency", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "pa_req_dvm_average_latency", + "MetricExpr": "pa_req_dvm_latency / pa_req_dvm_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Non-Sync request average latency from PA", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "mn_req_dvm_average_latency", + "MetricExpr": "mn_req_dvm_latency / mn_req_dvm_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Non-Sync request average latency from MN", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "l3t_req_dvm_average_latency", + "MetricExpr": "l3t_req_dvm_latency / l3t_req_dvm_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Non-Sync request average latency from L3T", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "snp_dvmsync_average_latency", + "MetricExpr": "snp_dvmsync_latency / snp_dvmsync_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Sync snoop request average latency", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "pa_req_dvmsync_average_latency", + "MetricExpr": "pa_req_dvmsync_latency / pa_req_dvmsync_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Sync request average latency from PA", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "mn_req_dvmsync_average_latency", + "MetricExpr": "mn_req_dvmsync_latency / mn_req_dvmsync_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Sync request average latency from MN", + "ScaleUnit": "1cycle" + }, + { + "MetricName": "l3t_req_dvmsync_average_latency", + "MetricExpr": "l3t_req_dvmsync_latency / l3t_req_dvmsync_num", + "MetricGroup": "MN_AVG_LAT", + "BriefDescription": "Count of one DVM Sync request average latency from L3T", + "ScaleUnit": "1cycle" + } +] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 0612dcef48c4..63c33aac6ab4 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -284,6 +284,7 @@ class JsonEvent: 'hisi_sccl,hha': 'hisi_sccl,hha', 'hisi_sccl,l3c': 'hisi_sccl,l3c', 'hisi_scl,noc': 'hisi_scl,noc', + 'hisi_scl,mn': 'hisi_scl,mn', 'imx8_ddr': 'imx8_ddr', 'L3PMC': 'amd_l3', 'DFPMC': 'amd_df', -- 2.43.0

driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- a) Add support for hisilicon L3C PMU perf event: · Add hip12 l3c event in l3c pmu; b) Add support for Hisilicon L3C PMU perf metric: · Average outstanding of l3t event; · Average latency of l3t event; · Average throughput of l3t evnt; Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- .../hisilicon/hip12/uncore-l3c-metric.json | 205 ++++++++++ .../arm64/hisilicon/hipxx/sys/uncore-l3c.json | 359 +++++++++++++++++- 2 files changed, 556 insertions(+), 8 deletions(-) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json new file mode 100644 index 000000000000..9b1846bd6fea --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json @@ -0,0 +1,205 @@ +[ + { + "MetricName": "l3t_dvmop_ost", + "MetricExpr": "l3t_dvmop_sum / l3c_cycles", + "MetricGroup": "L3C_OST", + "BriefDescription": "Average number of outstanding DVMOp requests in L3T per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_dvmop_thp", + "MetricExpr": "l3t_dvmop_alloc / l3c_cycles", + "MetricGroup": "L3C_THP", + "BriefDescription": "Average throughput of DVMOp requests processed by L3T per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_dvmop_lat", + "MetricExpr": "l3t_dvmop_sum / l3t_dvmop_alloc", + "MetricGroup": "L3C_LAT", + "BriefDescription": "Average latency of DVMOp requests processed by L3T", + "ScaleUnit": "cycles" + }, + { + "MetricName": "l3t_aq_time_ost", + "MetricExpr": "l3t_aq_time_sum / l3c_cycles", + "MetricGroup": "L3C_OST", + "BriefDescription": "Average number of outstanding AQ buffer time per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_aq_time_thp", + "MetricExpr": "l3t_aq_time_alloc / l3c_cycles", + "MetricGroup": "L3C_THP", + "BriefDescription": "Average throughput of AQ buffer time per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_aq_time_lat", + "MetricExpr": "l3t_aq_time_sum / l3t_aq_time_alloc", + "MetricGroup": "L3C_LAT", + "BriefDescription": "Average latency of AQ buffer time", + "ScaleUnit": "cycles" + }, + { + "MetricName": "l3t_pq_time_ost", + "MetricExpr": "l3t_pq_time_sum / l3c_cycles", + "MetricGroup": "L3C_OST", + "BriefDescription": "Average number of outstanding PQ buffer time per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_pq_time_thp", + "MetricExpr": "l3t_pq_time_alloc / l3c_cycles", + "MetricGroup": "L3C_THP", + "BriefDescription": "Average throughput of PQ buffer time per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_pq_time_lat", + "MetricExpr": "l3t_pq_time_sum / l3t_pq_time_alloc", + "MetricGroup": "L3C_LAT", + "BriefDescription": "Average latency of PQ buffer time", + "ScaleUnit": "cycles" + }, + { + "MetricName": "l3t_snp_cpu_ost", + "MetricExpr": "l3t_snp_cpu_sum / l3c_cycles", + "MetricGroup": "L3C_OST", + "BriefDescription": "Average number of outstanding SNPs sent to CPU per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_snp_cpu_thp", + "MetricExpr": "l3t_snp_cpu_alloc / l3c_cycles", + "MetricGroup": "L3C_THP", + "BriefDescription": "Average throughput of SNPs sent to CPU per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_snp_cpu_lat", + "MetricExpr": "l3t_snp_cpu_sum / l3t_snp_cpu_alloc", + "MetricGroup": "L3C_LAT", + "BriefDescription": "Average latency of SNPs sent to CPU", + "ScaleUnit": "cycles" + }, + { + "MetricName": "l3t_rxsnp_l3t_ost", + "MetricExpr": "l3t_rxsnp_l3t_sum / l3c_cycles", + "MetricGroup": "L3C_OST", + "BriefDescription": "Average number of outstanding SNPs received by L3T per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_rxsnp_l3t_thp", + "MetricExpr": "l3t_rxsnp_l3t_alloc / l3c_cycles", + "MetricGroup": "L3C_THP", + "BriefDescription": "Average throughput of SNPs received by L3T per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_rxsnp_l3t_lat", + "MetricExpr": "l3t_rxsnp_l3t_sum / l3t_rxsnp_l3t_alloc", + "MetricGroup": "L3C_LAT", + "BriefDescription": "Average latency of SNPs received by L3T", + "ScaleUnit": "cycles" + }, + { + "MetricName": "l3t_rxhydrasnp_l3t_ost", + "MetricExpr": "l3t_rxhydrasnp_l3t_sum / l3c_cycles", + "MetricGroup": "L3C_OST", + "BriefDescription": "Average number of outstanding HYDRASNPs received by L3T per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_rxhydrasnp_l3t_thp", + "MetricExpr": "l3t_rxhydrasnp_l3t_alloc / l3c_cycles", + "MetricGroup": "L3C_THP", + "BriefDescription": "Average throughput of HYDRASNPs received by L3T per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_rxhydrasnp_l3t_lat", + "MetricExpr": "l3t_rxhydrasnp_l3t_sum / l3t_rxhydrasnp_l3t_alloc", + "MetricGroup": "L3C_LAT", + "BriefDescription": "Average latency of HYDRASNPs received by L3T", + "ScaleUnit": "cycles" + }, + { + "MetricName": "l3t_dbid_l3t_ost", + "MetricExpr": "l3t_dbid_l3t_sum / l3c_cycles", + "MetricGroup": "L3C_OST", + "BriefDescription": "Average number of outstanding DBIDs returned to CPU per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_dbid_l3t_thp", + "MetricExpr": "l3t_dbid_l3t_alloc / l3c_cycles", + "MetricGroup": "L3C_THP", + "BriefDescription": "Average throughput of DBIDs returned to CPU per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_dbid_l3t_lat", + "MetricExpr": "l3t_dbid_l3t_sum / l3t_dbid_l3t_alloc", + "MetricGroup": "L3C_LAT", + "BriefDescription": "Average latency of DBIDs returned to CPU", + "ScaleUnit": "cycles" + }, + { + "MetricName": "l3t_wrnotram_ost", + "MetricExpr": "l3t_wrnotram_sum / l3c_cycles", + "MetricGroup": "L3C_OST", + "BriefDescription": "Average number of outstanding write requests to MATA per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_wrnotram_thp", + "MetricExpr": "l3t_wrnotram_alloc / l3c_cycles", + "MetricGroup": "L3C_THP", + "BriefDescription": "Average throughput of write requests to MATA per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_wrnotram_lat", + "MetricExpr": "l3t_wrnotram_sum / l3t_wrnotram_alloc", + "MetricGroup": "L3C_LAT", + "BriefDescription": "Average latency of write requests to MATA", + "ScaleUnit": "cycles" + }, + { + "MetricName": "l3t_retry_ost", + "MetricExpr": "l3t_retry_sum / l3c_cycles", + "MetricGroup": "L3C_OST", + "BriefDescription": "Average number of outstanding retry requests per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_retry_thp", + "MetricExpr": "l3t_retry_alloc / l3c_cycles", + "MetricGroup": "L3C_THP", + "BriefDescription": "Average throughput of retry requests per cycle", + "ScaleUnit": "per cycle" + }, + { + "MetricName": "l3t_retry_lat", + "MetricExpr": "l3t_retry_sum / l3t_retry_alloc", + "MetricGroup": "L3C_LAT", + "BriefDescription": "Average latency of retry requests", + "ScaleUnit": "cycles" + }, + { + "MetricName": "l3t_ret_cpu_bw", + "MetricExpr": "l3t_ret_cpu_sum * 64 / l3c_cycles", + "MetricGroup": "L3C_BW", + "BriefDescription": "Bandwidth of data returned to CPU from L3T (64B)", + "ScaleUnit": "B/s" + }, + { + "MetricName": "l3t_ret_ring_bw", + "MetricExpr": "l3t_ret_ring_sum * 64 / l3c_cycles", + "MetricGroup": "L3C_BW", + "BriefDescription": "Bandwidth of data returned to RING from L3T (64B)", + "ScaleUnit": "B/s" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json index 5cdc5a5db533..8c3632b85ee5 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json @@ -27,6 +27,48 @@ "Compat": "0x00000030", "Unit": "hisi_sccl,l3c" }, + { + "EventCode": "0x42", + "EventName": "atomic_tablehsnp_rejecten", + "BriefDescription": "Number of times the hydrasnp in the atomic table is rejected.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x43", + "EventName": "atomic_tablerejecten", + "BriefDescription": "Number of times internal requests in the atomic table are rejected.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x44", + "EventName": "atomic_tablealloc", + "BriefDescription": "Number of times the atomic table is allocated.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x45", + "EventName": "atomic_tablevic", + "BriefDescription": "Number of times the atomic table is replaced.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x46", + "EventName": "atomic_tabletimeout", + "BriefDescription": "Number of times the atomic table times out.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x47", + "EventName": "atomic_tablehmerge", + "BriefDescription": "Number of times the atomic table performs hydrasnp merge protocol.", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, { "EventCode": "0x48", "EventName": "l3c_hit", @@ -38,14 +80,14 @@ "EventCode": "0x7f", "EventName": "l3c_cycles", "BriefDescription": "Count of L3C cycles", - "Compat": "0x00000030", + "Compat": "0x000000(30|40)", "Unit": "hisi_sccl,l3c" }, { "EventCode": "0x7f", "EventName": "cycles", "BriefDescription": "Count of L3C cycles", - "Compat": "0x00000030", + "Compat": "0x000000(30|40)", "Unit": "hisi_sccl,l3c" }, { @@ -53,7 +95,7 @@ "EventName": "cpu_read_l3c_lat", "Filter": "tt_core=0xff", "BriefDescription": "Count the total latency that L3C completes the cluster CPU read requests", - "Compat": "0x00000030", + "Compat": "0x000000(30|40)", "Unit": "hisi_sccl,l3c" }, { @@ -61,7 +103,7 @@ "EventName": "l3c_read_hha_lat", "Filter": "tt_core=0xff,tt_req=0x4", "BriefDescription": "Count the total latency that HHA completes the L3C read requests", - "Compat": "0x00000030", + "Compat": "0x000000(30|40)", "Unit": "hisi_sccl,l3c" }, { @@ -79,12 +121,30 @@ "Compat": "0x00000030", "Unit": "hisi_sccl,l3c" }, + { + "EventCode": "0xbc", + "EventName": "l3t_ret_cpu_sum", + "BriefDescription": "Count number of the L3T return data to CPU(64B)", + "Filter": "tt_core=0xff", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + + }, + { + "EventCode": "0xbd", + "EventName": "l3t_ret_ring_sum", + "BriefDescription": "Count number of the L3T return data to RING(64B)", + "Filter": "tt_core=0xff", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + + }, { "EventCode": "0xc0", "EventName": "cpu_read_l3c_sum", "Filter": "tt_core=0xff", "BriefDescription": "Count of the requests issued by the cluster CPU read L3C", - "Compat": "0x00000030", + "Compat": "0x000000(30|40)", "Unit": "hisi_sccl,l3c" }, { @@ -92,15 +152,298 @@ "EventName": "l3c_read_hha_sum", "Filter": "tt_core=0xff,tt_req=0x4", "BriefDescription": "Count number of L3C read access to HHA", - "Compat": "0x00000030", + "Compat": "0x000000(30|40)", "Unit": "hisi_sccl,l3c" }, { "EventCode": "0xce", - "EventName": "l3c_retry_alloc", + "EventName": "l3t_retry_alloc", "Filter": "tt_core=0xff", "BriefDescription": "Count of the L3C retry CPU", - "Compat": "0x00000030", + "Compat": "0x000000(30|40)", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x81", + "EventName": "l3t_dvmop_sum", + "Filter": "tt_req=0x3", + "BriefDescription": "Total time spent by L3T on DVMOp requests", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x84", + "EventName": "l3t_aq_time_sum", + "BriefDescription": "Total time spent by marked requests in AQ buffer", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x85", + "EventName": "l3t_pq_time_sum", + "BriefDescription": "Total time spent by marked requests in PQ buffer", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x86", + "EventName": "l3t_snp_cpu_sum", + "BriefDescription": "Total time spent by L3T on sending SNPs to CPU", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x88", + "EventName": "l3t_rxsnp_l3t_sum", + "BriefDescription": "Total time spent by L3T receiving SNPs from RING", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x8a", + "EventName": "l3t_rxhydrasnp_l3t_sum", + "BriefDescription": "Total time spent by L3T receiving HYDRASNPs from RING", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x8b", + "EventName": "l3t_dbid_l3t_sum", + "BriefDescription": "Total time spent by L3T returning DBIDs to CPU", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x8d", + "EventName": "l3t_wrnotram_sum", + "BriefDescription": "Total time spent by L3T on sending writes to MATA", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x8e", + "EventName": "l3t_retry_sum", + "BriefDescription": "Total time spent by L3T on sending retries to CPU", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc1", + "EventName": "l3t_dvmop_alloc", + "Filter": "tt_req=0x3", + "BriefDescription": "Number of DVMOp requests received by L3T", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc4", + "EventName": "l3t_aq_time_alloc", + "BriefDescription": "Total time spent by AQ buffer for marked requests", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc5", + "EventName": "l3t_pq_time_alloc", + "BriefDescription": "Total time spent by PQ buffer for marked requests", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc6", + "EventName": "l3t_snp_cpu_alloc", + "BriefDescription": "Number of SNPs sent by L3T to CPU", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xc8", + "EventName": "l3t_rxsnp_l3t_alloc", + "BriefDescription": "Number of SNPs received by L3T from RING", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xca", + "EventName": "l3t_rxhydrasnp_l3t_alloc", + "BriefDescription": "Number of HYDRASNPs received by L3T from RING", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xcb", + "EventName": "l3t_dbid_l3t_alloc", + "BriefDescription": "Number of CPU requests received by L3T", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0xcd", + "EventName": "l3t_wrnotram_alloc", + "BriefDescription": "Number of write requests received by L3T for MATA", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x00", + "EventName": "rd_cpipe", + "BriefDescription": "the number of CPIPEs from CPU send read request", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x01", + "EventName": "rd_hit_cpipe", + "BriefDescription": "the number of CPIPEs from CPU read request hit", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x02", + "EventName": "wr_cpipe", + "BriefDescription": "the number of CPIPEs from CPU send stream write request", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x03", + "EventName": "wr_hit_cpipe", + "BriefDescription": "the number of CPIPEs from CPU stream write request hit", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x04", + "EventName": "io_rd_cpipe", + "Filter": "tt_req=0x4", + "BriefDescription": "the number of IO send read request to CPIPE", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x05", + "EventName": "io_rd_hit_cpipe", + "Filter": "tt_req=0x4", + "BriefDescription": "the number of IO read request hit CPIPE", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x06", + "EventName": "io_wr_cpipe", + "Filter": "tt_req=0x5", + "BriefDescription": "the number of IO send stream write request to CPIPE", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x07", + "EventName": "io_wr_hit_cpipe", + "Filter": "tt_req=0x5", + "BriefDescription": "the number of IO stream write request hit CPIPE", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x0c", + "EventName": "l3_victim", + "BriefDescription": "the number of victim entries in L3", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x0d", + "EventName": "l3d_compress_alloc_solo", + "BriefDescription": "the number of times that data is not compressed when alloc L3D data is compressed", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x0e", + "EventName": "l3d_compress_alloc_twins", + "BriefDescription": "the number of times that data is compressed when alloc L3D data is compressed", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x0f", + "EventName": "l3d_compress_vic_solo", + "BriefDescription": "the number of times that only 64-byte data is compressed during data replacement", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x10", + "EventName": "l3d_compress_vic_twins", + "BriefDescription": "the number of times that only 128-byte data is compressed during data replacement", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x12", + "EventName": "l3d_alloc", + "BriefDescription": "the number of l3d allocs", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x18", + "EventName": "rd_spipe", + "BriefDescription": "the number of SPipe from CPU send read request", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x19", + "EventName": "rd_hit_spipe", + "BriefDescription": "the number of SPipe from CPU read request hit", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1a", + "EventName": "wr_hit", + "BriefDescription": "the number of SPipe from CPU send stream write request", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1b", + "EventName": "wr_hit_spipe", + "BriefDescription": "the number of SPipe from CPU stream write request hit", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1c", + "EventName": "io_rd_spipe", + "Filter": "tt_req=0x4", + "BriefDescription": "the number of IO send read request to SPipe", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1d", + "EventName": "io_rd_hit_spipe", + "Filter": "tt_req=0x4", + "BriefDescription": "the number of IO read request hit SPipe", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1e", + "EventName": "io_wr_spipe", + "Filter": "tt_req=0x5", + "BriefDescription": "the number of IO send stream write request to SPipe", + "Compat": "0x00000040", + "Unit": "hisi_sccl,l3c" + }, + { + "EventCode": "0x1f", + "EventName": "io_wr_hit_spipe", + "Filter": "tt_req=0x5", + "BriefDescription": "the number of IO send stream write request hit to SPipe", + "Compat": "0x00000040", "Unit": "hisi_sccl,l3c" } ] -- 2.43.0

driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- After the 0x80-8f event enabled, dfx_en is pulled down. If the same counter is used to collect statistics on the 0x80 to 0x8F events, the statistics may be inaccurate and a counter overflow interrupt is reported. The hardware frequently reports overflow interrupts. As a result, the kernel does not even reset the watchdog. calltrace occured. Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- .../hisilicon/hip12/uncore-l3c-metric.json | 158 +----------------- .../arm64/hisilicon/hipxx/sys/uncore-l3c.json | 80 --------- 2 files changed, 9 insertions(+), 229 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json index 9b1846bd6fea..3feb20e8a08a 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip12/uncore-l3c-metric.json @@ -1,205 +1,65 @@ [ - { - "MetricName": "l3t_dvmop_ost", - "MetricExpr": "l3t_dvmop_sum / l3c_cycles", - "MetricGroup": "L3C_OST", - "BriefDescription": "Average number of outstanding DVMOp requests in L3T per cycle", - "ScaleUnit": "per cycle" - }, { "MetricName": "l3t_dvmop_thp", "MetricExpr": "l3t_dvmop_alloc / l3c_cycles", "MetricGroup": "L3C_THP", "BriefDescription": "Average throughput of DVMOp requests processed by L3T per cycle", - "ScaleUnit": "per cycle" - }, - { - "MetricName": "l3t_dvmop_lat", - "MetricExpr": "l3t_dvmop_sum / l3t_dvmop_alloc", - "MetricGroup": "L3C_LAT", - "BriefDescription": "Average latency of DVMOp requests processed by L3T", - "ScaleUnit": "cycles" - }, - { - "MetricName": "l3t_aq_time_ost", - "MetricExpr": "l3t_aq_time_sum / l3c_cycles", - "MetricGroup": "L3C_OST", - "BriefDescription": "Average number of outstanding AQ buffer time per cycle", - "ScaleUnit": "per cycle" + "ScaleUnit": "ops/cycle" }, { "MetricName": "l3t_aq_time_thp", "MetricExpr": "l3t_aq_time_alloc / l3c_cycles", "MetricGroup": "L3C_THP", "BriefDescription": "Average throughput of AQ buffer time per cycle", - "ScaleUnit": "per cycle" - }, - { - "MetricName": "l3t_aq_time_lat", - "MetricExpr": "l3t_aq_time_sum / l3t_aq_time_alloc", - "MetricGroup": "L3C_LAT", - "BriefDescription": "Average latency of AQ buffer time", - "ScaleUnit": "cycles" - }, - { - "MetricName": "l3t_pq_time_ost", - "MetricExpr": "l3t_pq_time_sum / l3c_cycles", - "MetricGroup": "L3C_OST", - "BriefDescription": "Average number of outstanding PQ buffer time per cycle", - "ScaleUnit": "per cycle" + "ScaleUnit": "ops/cycle" }, { "MetricName": "l3t_pq_time_thp", "MetricExpr": "l3t_pq_time_alloc / l3c_cycles", "MetricGroup": "L3C_THP", "BriefDescription": "Average throughput of PQ buffer time per cycle", - "ScaleUnit": "per cycle" - }, - { - "MetricName": "l3t_pq_time_lat", - "MetricExpr": "l3t_pq_time_sum / l3t_pq_time_alloc", - "MetricGroup": "L3C_LAT", - "BriefDescription": "Average latency of PQ buffer time", - "ScaleUnit": "cycles" - }, - { - "MetricName": "l3t_snp_cpu_ost", - "MetricExpr": "l3t_snp_cpu_sum / l3c_cycles", - "MetricGroup": "L3C_OST", - "BriefDescription": "Average number of outstanding SNPs sent to CPU per cycle", - "ScaleUnit": "per cycle" + "ScaleUnit": "ops/cycle" }, { "MetricName": "l3t_snp_cpu_thp", "MetricExpr": "l3t_snp_cpu_alloc / l3c_cycles", "MetricGroup": "L3C_THP", "BriefDescription": "Average throughput of SNPs sent to CPU per cycle", - "ScaleUnit": "per cycle" - }, - { - "MetricName": "l3t_snp_cpu_lat", - "MetricExpr": "l3t_snp_cpu_sum / l3t_snp_cpu_alloc", - "MetricGroup": "L3C_LAT", - "BriefDescription": "Average latency of SNPs sent to CPU", - "ScaleUnit": "cycles" - }, - { - "MetricName": "l3t_rxsnp_l3t_ost", - "MetricExpr": "l3t_rxsnp_l3t_sum / l3c_cycles", - "MetricGroup": "L3C_OST", - "BriefDescription": "Average number of outstanding SNPs received by L3T per cycle", - "ScaleUnit": "per cycle" + "ScaleUnit": "ops/cycle" }, { "MetricName": "l3t_rxsnp_l3t_thp", "MetricExpr": "l3t_rxsnp_l3t_alloc / l3c_cycles", "MetricGroup": "L3C_THP", "BriefDescription": "Average throughput of SNPs received by L3T per cycle", - "ScaleUnit": "per cycle" - }, - { - "MetricName": "l3t_rxsnp_l3t_lat", - "MetricExpr": "l3t_rxsnp_l3t_sum / l3t_rxsnp_l3t_alloc", - "MetricGroup": "L3C_LAT", - "BriefDescription": "Average latency of SNPs received by L3T", - "ScaleUnit": "cycles" - }, - { - "MetricName": "l3t_rxhydrasnp_l3t_ost", - "MetricExpr": "l3t_rxhydrasnp_l3t_sum / l3c_cycles", - "MetricGroup": "L3C_OST", - "BriefDescription": "Average number of outstanding HYDRASNPs received by L3T per cycle", - "ScaleUnit": "per cycle" + "ScaleUnit": "ops/cycle" }, { "MetricName": "l3t_rxhydrasnp_l3t_thp", "MetricExpr": "l3t_rxhydrasnp_l3t_alloc / l3c_cycles", "MetricGroup": "L3C_THP", "BriefDescription": "Average throughput of HYDRASNPs received by L3T per cycle", - "ScaleUnit": "per cycle" - }, - { - "MetricName": "l3t_rxhydrasnp_l3t_lat", - "MetricExpr": "l3t_rxhydrasnp_l3t_sum / l3t_rxhydrasnp_l3t_alloc", - "MetricGroup": "L3C_LAT", - "BriefDescription": "Average latency of HYDRASNPs received by L3T", - "ScaleUnit": "cycles" - }, - { - "MetricName": "l3t_dbid_l3t_ost", - "MetricExpr": "l3t_dbid_l3t_sum / l3c_cycles", - "MetricGroup": "L3C_OST", - "BriefDescription": "Average number of outstanding DBIDs returned to CPU per cycle", - "ScaleUnit": "per cycle" + "ScaleUnit": "ops/cycle" }, { "MetricName": "l3t_dbid_l3t_thp", "MetricExpr": "l3t_dbid_l3t_alloc / l3c_cycles", "MetricGroup": "L3C_THP", "BriefDescription": "Average throughput of DBIDs returned to CPU per cycle", - "ScaleUnit": "per cycle" - }, - { - "MetricName": "l3t_dbid_l3t_lat", - "MetricExpr": "l3t_dbid_l3t_sum / l3t_dbid_l3t_alloc", - "MetricGroup": "L3C_LAT", - "BriefDescription": "Average latency of DBIDs returned to CPU", - "ScaleUnit": "cycles" - }, - { - "MetricName": "l3t_wrnotram_ost", - "MetricExpr": "l3t_wrnotram_sum / l3c_cycles", - "MetricGroup": "L3C_OST", - "BriefDescription": "Average number of outstanding write requests to MATA per cycle", - "ScaleUnit": "per cycle" + "ScaleUnit": "ops/cycle" }, { "MetricName": "l3t_wrnotram_thp", "MetricExpr": "l3t_wrnotram_alloc / l3c_cycles", "MetricGroup": "L3C_THP", "BriefDescription": "Average throughput of write requests to MATA per cycle", - "ScaleUnit": "per cycle" - }, - { - "MetricName": "l3t_wrnotram_lat", - "MetricExpr": "l3t_wrnotram_sum / l3t_wrnotram_alloc", - "MetricGroup": "L3C_LAT", - "BriefDescription": "Average latency of write requests to MATA", - "ScaleUnit": "cycles" - }, - { - "MetricName": "l3t_retry_ost", - "MetricExpr": "l3t_retry_sum / l3c_cycles", - "MetricGroup": "L3C_OST", - "BriefDescription": "Average number of outstanding retry requests per cycle", - "ScaleUnit": "per cycle" + "ScaleUnit": "ops/cycle" }, { "MetricName": "l3t_retry_thp", "MetricExpr": "l3t_retry_alloc / l3c_cycles", "MetricGroup": "L3C_THP", "BriefDescription": "Average throughput of retry requests per cycle", - "ScaleUnit": "per cycle" - }, - { - "MetricName": "l3t_retry_lat", - "MetricExpr": "l3t_retry_sum / l3t_retry_alloc", - "MetricGroup": "L3C_LAT", - "BriefDescription": "Average latency of retry requests", - "ScaleUnit": "cycles" - }, - { - "MetricName": "l3t_ret_cpu_bw", - "MetricExpr": "l3t_ret_cpu_sum * 64 / l3c_cycles", - "MetricGroup": "L3C_BW", - "BriefDescription": "Bandwidth of data returned to CPU from L3T (64B)", - "ScaleUnit": "B/s" - }, - { - "MetricName": "l3t_ret_ring_bw", - "MetricExpr": "l3t_ret_ring_sum * 64 / l3c_cycles", - "MetricGroup": "L3C_BW", - "BriefDescription": "Bandwidth of data returned to RING from L3T (64B)", - "ScaleUnit": "B/s" + "ScaleUnit": "ops/cycle" } ] diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json index 889b49527571..99e434cf915a 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-l3c.json @@ -90,22 +90,6 @@ "Compat": "0x000000(30|40)", "Unit": "hisi_sccl,l3c" }, - { - "EventCode": "0x80", - "EventName": "cpu_read_l3c_lat", - "Filter": "tt_core=0xff", - "BriefDescription": "Count the total latency that L3C completes the cluster CPU read requests", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,l3c" - }, - { - "EventCode": "0x83", - "EventName": "l3c_read_hha_lat", - "Filter": "tt_core=0xff,tt_req=0x4", - "BriefDescription": "Count the total latency that HHA completes the L3C read requests", - "Compat": "0x000000(30|40)", - "Unit": "hisi_sccl,l3c" - }, { "EventCode": "0xb8", "EventName": "l3c_ref", @@ -170,70 +154,6 @@ "Compat": "0x000000(30|40)", "Unit": "hisi_sccl,l3c" }, - { - "EventCode": "0x81", - "EventName": "l3t_dvmop_sum", - "Filter": "tt_req=0x3", - "BriefDescription": "Total time spent by L3T on DVMOp requests", - "Compat": "0x00000040", - "Unit": "hisi_sccl,l3c" - }, - { - "EventCode": "0x84", - "EventName": "l3t_aq_time_sum", - "BriefDescription": "Total time spent by marked requests in AQ buffer", - "Compat": "0x00000040", - "Unit": "hisi_sccl,l3c" - }, - { - "EventCode": "0x85", - "EventName": "l3t_pq_time_sum", - "BriefDescription": "Total time spent by marked requests in PQ buffer", - "Compat": "0x00000040", - "Unit": "hisi_sccl,l3c" - }, - { - "EventCode": "0x86", - "EventName": "l3t_snp_cpu_sum", - "BriefDescription": "Total time spent by L3T on sending SNPs to CPU", - "Compat": "0x00000040", - "Unit": "hisi_sccl,l3c" - }, - { - "EventCode": "0x88", - "EventName": "l3t_rxsnp_l3t_sum", - "BriefDescription": "Total time spent by L3T receiving SNPs from RING", - "Compat": "0x00000040", - "Unit": "hisi_sccl,l3c" - }, - { - "EventCode": "0x8a", - "EventName": "l3t_rxhydrasnp_l3t_sum", - "BriefDescription": "Total time spent by L3T receiving HYDRASNPs from RING", - "Compat": "0x00000040", - "Unit": "hisi_sccl,l3c" - }, - { - "EventCode": "0x8b", - "EventName": "l3t_dbid_l3t_sum", - "BriefDescription": "Total time spent by L3T returning DBIDs to CPU", - "Compat": "0x00000040", - "Unit": "hisi_sccl,l3c" - }, - { - "EventCode": "0x8d", - "EventName": "l3t_wrnotram_sum", - "BriefDescription": "Total time spent by L3T on sending writes to MATA", - "Compat": "0x00000040", - "Unit": "hisi_sccl,l3c" - }, - { - "EventCode": "0x8e", - "EventName": "l3t_retry_sum", - "BriefDescription": "Total time spent by L3T on sending retries to CPU", - "Compat": "0x00000040", - "Unit": "hisi_sccl,l3c" - }, { "EventCode": "0xc1", "EventName": "l3t_dvmop_alloc", -- 2.43.0

From: Yushan Wang <wangyushan12@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- The metric alias for hha_retry and hha_backinvalid is exchanged by mistake, correct them. Signed-off-by: Yushan Wang <wangyushan12@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- .../arch/arm64/hisilicon/hipxx/sys/uncore-hha.json | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-hha.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-hha.json index 78aed4f2641d..9c5f0a633be0 100644 --- a/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-hha.json +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hipxx/sys/uncore-hha.json @@ -85,15 +85,15 @@ }, { "EventCode": "0x23", - "EventName": "hha_retry", - "BriefDescription": "Count of the HHA retry", + "EventName": "hha_backinvalid", + "BriefDescription": "Count number of HHA back invalid operations", "Compat": "0x00000030", "Unit": "hisi_sccl,hha" }, { "EventCode": "0x2e", - "EventName": "hha_backinvalid", - "BriefDescription": "Count number of HHA back invalid operations", + "EventName": "hha_retry", + "BriefDescription": "Count of the HHA retry", "Compat": "0x00000030", "Unit": "hisi_sccl,hha" }, -- 2.43.0

From: Qi Liu <liuqi115@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICRSOQ ---------------------------------------------------------------------- pmu_name of DDRC PMU on Hip09 platform is set as "hisi_sllcX_ddrcY_Z", current match method of pmu_name cannot fit DDRC pmu, so modify the method. Signed-off-by: Qi Liu <liuqi115@huawei.com> Signed-off-by: Junhao He <hejunhao3@huawei.com> Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Qizhi Zhang <zhangqizhi3@h-partners.com> Signed-off-by: JiangShui Yang <yangjiangshui@h-partners.com> --- tools/perf/util/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index bc10a22f5dac..676b42b5bfee 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -827,7 +827,7 @@ static bool perf_pmu__match_ignoring_suffix(const char *pmu_name, const char *to /* Ensure we end in a number */ while (1) { - if (!isdigit(*p)) + if (!isdigit(*p) && (*p != '_')) return false; if (*(++p) == 0) break; -- 2.43.0