tree: https://gitee.com/openeuler/kernel.git OLK-6.6 head: 3b421b6002e287e38790cbdad4a3e08baf7e1bc4 commit: 86b90dc581ce2fcc6b724b4ffaea6103122a4b68 [3269/10596] iommu/arm-smmu-v3: Add support for ECMDQ register mode config: arm64-randconfig-r131-20240707 (https://download.01.org/0day-ci/archive/20240708/202407080437.gW9dgdMn-lkp@i...) compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project a0c6b8aef853eedaa0980f07c0a502a5a8a9740e) reproduce: (https://download.01.org/0day-ci/archive/20240708/202407080437.gW9dgdMn-lkp@i...) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202407080437.gW9dgdMn-lkp@intel.com/ sparse warnings: (new ones prefixed by >>)

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drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3942:23: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct arm_smmu_ecmdq *ecmdq @@ got struct arm_smmu_ecmdq [noderef] __percpu * @@ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3942:23: sparse: expected struct arm_smmu_ecmdq *ecmdq drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3942:23: sparse: got struct arm_smmu_ecmdq [noderef] __percpu * drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3947:58: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected void const [noderef] __percpu *__vpp_verify @@ got struct arm_smmu_ecmdq * @@ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3947:58: sparse: expected void const [noderef] __percpu *__vpp_verify drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3947:58: sparse: got struct arm_smmu_ecmdq * drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3973:45: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const *addr @@ got void [noderef] __iomem *base @@ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3973:45: sparse: expected void const *addr drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:3973:45: sparse: got void [noderef] __iomem *base drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c: note: in included file (through arch/arm64/include/asm/atomic.h, include/linux/atomic.h, include/asm-generic/bitops/atomic.h, ...): arch/arm64/include/asm/cmpxchg.h:168:1: sparse: sparse: cast truncates bits from constant value (ffffffff80000000 becomes 0) arch/arm64/include/asm/cmpxchg.h:168:1: sparse: sparse: cast truncates bits from constant value (ffffffff80000000 becomes 0)

vim +3942 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c 3934 3935 #ifdef CONFIG_ARM_SMMU_V3_ECMDQ 3936 static int arm_smmu_ecmdq_layout(struct arm_smmu_device *smmu) 3937 { 3938 int cpu; 3939 struct arm_smmu_ecmdq *ecmdq; 3940 3941 if (num_possible_cpus() <= smmu->nr_ecmdq) {

3942 ecmdq = devm_alloc_percpu(smmu->dev, *ecmdq); 3943 if (!ecmdq) 3944 return -ENOMEM; 3945 3946 for_each_possible_cpu(cpu) 3947 *per_cpu_ptr(smmu->ecmdq, cpu) = per_cpu_ptr(ecmdq, cpu); 3948 3949 /* A core requires at most one ECMDQ */ 3950 smmu->nr_ecmdq = num_possible_cpus(); 3951 3952 return 0; 3953 } 3954 3955 return -ENOSPC; 3956 } 3957 3958 static int arm_smmu_ecmdq_probe(struct arm_smmu_device *smmu) 3959 { 3960 int ret, cpu; 3961 u32 i, nump, numq, gap; 3962 u32 reg, shift_increment; 3963 u64 addr, smmu_dma_base; 3964 void __iomem *cp_regs, *cp_base; 3965 3966 /* IDR6 */ 3967 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR6); 3968 nump = 1 << FIELD_GET(IDR6_LOG2NUMP, reg); 3969 numq = 1 << FIELD_GET(IDR6_LOG2NUMQ, reg); 3970 smmu->nr_ecmdq = nump * numq; 3971 gap = ECMDQ_CP_RRESET_SIZE >> FIELD_GET(IDR6_LOG2NUMQ, reg); 3972 3973 smmu_dma_base = (vmalloc_to_pfn(smmu->base) << PAGE_SHIFT); 3974 cp_regs = ioremap(smmu_dma_base + ARM_SMMU_ECMDQ_CP_BASE, PAGE_SIZE); 3975 if (!cp_regs) 3976 return -ENOMEM; 3977 3978 for (i = 0; i < nump; i++) { 3979 u64 val, pre_addr; 3980 3981 val = readq_relaxed(cp_regs + 32 * i); 3982 if (!(val & ECMDQ_CP_PRESET)) { 3983 iounmap(cp_regs); 3984 dev_err(smmu->dev, "ecmdq control page %u is memory mode\n", i); 3985 return -EFAULT; 3986 } 3987 3988 if (i && ((val & ECMDQ_CP_ADDR) != (pre_addr + ECMDQ_CP_RRESET_SIZE))) { 3989 iounmap(cp_regs); 3990 dev_err(smmu->dev, "ecmdq_cp memory region is not contiguous\n"); 3991 return -EFAULT; 3992 } 3993 3994 pre_addr = val & ECMDQ_CP_ADDR; 3995 } 3996 3997 addr = readl_relaxed(cp_regs) & ECMDQ_CP_ADDR; 3998 iounmap(cp_regs); 3999 4000 cp_base = devm_ioremap(smmu->dev, smmu_dma_base + addr, ECMDQ_CP_RRESET_SIZE * nump); 4001 if (!cp_base) 4002 return -ENOMEM; 4003 4004 smmu->ecmdq = devm_alloc_percpu(smmu->dev, struct arm_smmu_ecmdq *); 4005 if (!smmu->ecmdq) 4006 return -ENOMEM; 4007 4008 ret = arm_smmu_ecmdq_layout(smmu); 4009 if (ret) 4010 return ret; 4011 4012 shift_increment = order_base_2(num_possible_cpus() / smmu->nr_ecmdq); 4013 4014 addr = 0; 4015 for_each_possible_cpu(cpu) { 4016 struct arm_smmu_ecmdq *ecmdq; 4017 struct arm_smmu_queue *q; 4018 4019 ecmdq = *per_cpu_ptr(smmu->ecmdq, cpu); 4020 ecmdq->base = cp_base + addr; 4021 4022 q = &ecmdq->cmdq.q; 4023 4024 q->llq.max_n_shift = ECMDQ_MAX_SZ_SHIFT + shift_increment; 4025 ret = arm_smmu_init_one_queue(smmu, q, ecmdq->base, ARM_SMMU_ECMDQ_PROD, 4026 ARM_SMMU_ECMDQ_CONS, CMDQ_ENT_DWORDS, "ecmdq"); 4027 if (ret) 4028 return ret; 4029 4030 q->ecmdq_prod = ECMDQ_PROD_EN; 4031 rwlock_init(&q->ecmdq_lock); 4032 4033 ret = arm_smmu_ecmdq_init(&ecmdq->cmdq); 4034 if (ret) { 4035 dev_err(smmu->dev, "ecmdq[%d] init failed\n", i); 4036 return ret; 4037 } 4038 4039 addr += gap; 4040 } 4041 4042 return 0; 4043 } 4044 #endif 4045

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