hulk inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/IBH1XN -------------------------------- Commit 010deecfc1b0 ("arch/x86: fix kabi broken in struct cpuinfo_x86") move struct cpuinfo_x86's member 'x86_mode' 'x86' 'x86_vendor' to another place. This actually broke the kabi because a module may access it with origin offset and find it is zero. This commit fix it. Fixes: 010deecfc1b0 ("[Huawei] arch/x86: fix kabi broken in struct cpuinfo_x86")' Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> --- arch/x86/include/asm/cpu_device_id.h | 2 ++ arch/x86/include/asm/processor.h | 26 ++++---------------------- arch/x86/kernel/cpu/intel.c | 22 +++++++++++----------- 3 files changed, 17 insertions(+), 33 deletions(-) diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cpu_device_id.h index e8e3dbe7f173..8a85ec0cc76a 100644 --- a/arch/x86/include/asm/cpu_device_id.h +++ b/arch/x86/include/asm/cpu_device_id.h @@ -35,6 +35,8 @@ ((_vendor) << VFM_VENDOR_BIT) \ ) +#define CPUINFO_VFM(cpuinfo) VFM_MAKE(cpuinfo->x86_vendor, cpuinfo->x86, cpuinfo->x86_model) + /* * Declare drivers belonging to specific x86 CPUs * Similar in spirit to pci_device_id and related PCI functions diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 44e0112f2e58..1e75538019fc 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -86,9 +86,9 @@ struct cpuinfo_x86_resvd { */ struct cpuinfo_x86 { - KABI_DEPRECATE(__u8, x86) - KABI_DEPRECATE(__u8, x86_vendor) - KABI_DEPRECATE(__u8, x86_model) + __u8 x86; + __u8 x86_vendor; + __u8 x86_model; __u8 x86_stepping; #ifdef CONFIG_X86_64 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ @@ -151,25 +151,7 @@ struct cpuinfo_x86 { /* Address space bits used by the cache internally */ u8 x86_cache_bits; unsigned initialized : 1; - KABI_USE(1, - union { - /* - * The particular ordering (low-to-high) of (vendor, - * family, model) is done in case range of models, like - * it is usually done on AMD, need to be compared. - */ - struct { - __u8 x86_model; - /* CPU family */ - __u8 x86; - /* CPU vendor */ - __u8 x86_vendor; - __u8 x86_reserved; - }; - /* combined vendor, family, model */ - __u32 x86_vfm; - } - ) + KABI_RESERVE(1) KABI_RESERVE(2) KABI_RESERVE(3) KABI_RESERVE(4) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index a84e137fcc3c..e1097b62b3da 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -72,7 +72,7 @@ static bool cpu_model_supports_sld __ro_after_init; */ static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) { - switch (c->x86_vfm) { + switch (CPUINFO_VFM(c)) { case INTEL_CORE_YONAH: case INTEL_CORE2_MEROM: case INTEL_CORE2_MEROM_L: @@ -106,7 +106,7 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) */ if (c->x86 != 6) return; - switch (c->x86_vfm) { + switch (CPUINFO_VFM(c)) { case INTEL_XEON_PHI_KNL: case INTEL_XEON_PHI_KNM: break; @@ -174,7 +174,7 @@ static bool bad_spectre_microcode(struct cpuinfo_x86 *c) return false; for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) { - if (c->x86_vfm == spectre_bad_microcodes[i].vfm && + if (CPUINFO_VFM(c) == spectre_bad_microcodes[i].vfm && c->x86_stepping == spectre_bad_microcodes[i].stepping) return (c->microcode <= spectre_bad_microcodes[i].microcode); } @@ -309,7 +309,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) * need the microcode to have already been loaded... so if it is * not, recommend a BIOS update and disable large pages. */ - if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 && + if (CPUINFO_VFM(c) == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 && c->microcode < 0x20e) { pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n"); clear_cpu_cap(c, X86_FEATURE_PSE); @@ -341,7 +341,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) } /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */ - switch (c->x86_vfm) { + switch (CPUINFO_VFM(c)) { case INTEL_ATOM_SALTWELL_MID: case INTEL_ATOM_SALTWELL_TABLET: case INTEL_ATOM_SILVERMONT_MID: @@ -386,7 +386,7 @@ static void early_init_intel(struct cpuinfo_x86 *c) * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE * to be modified. */ - if (c->x86_vfm == INTEL_QUARK_X1000) { + if (CPUINFO_VFM(c) == INTEL_QUARK_X1000) { pr_info("Disabling PGE capability bit\n"); setup_clear_cpu_cap(X86_FEATURE_PGE); } @@ -644,14 +644,14 @@ static void init_intel(struct cpuinfo_x86 *c) } if (boot_cpu_has(X86_FEATURE_CLFLUSH) && - (c->x86_vfm == INTEL_CORE2_DUNNINGTON || - c->x86_vfm == INTEL_NEHALEM_EX || - c->x86_vfm == INTEL_WESTMERE_EX)) + (CPUINFO_VFM(c) == INTEL_CORE2_DUNNINGTON || + CPUINFO_VFM(c) == INTEL_NEHALEM_EX || + CPUINFO_VFM(c) == INTEL_WESTMERE_EX)) set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); if (boot_cpu_has(X86_FEATURE_MWAIT) && - (c->x86_vfm == INTEL_ATOM_GOLDMONT || - c->x86_vfm == INTEL_LUNARLAKE_M)) + (CPUINFO_VFM(c) == INTEL_ATOM_GOLDMONT || + CPUINFO_VFM(c) == INTEL_LUNARLAKE_M)) set_cpu_bug(c, X86_BUG_MONITOR); #ifdef CONFIG_X86_64 -- 2.20.1