From: Zhou Wang <wangzhou1@hisilicon.com> driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/ICURZK --------------------------------------------------------------------- On HIP12, mpidr indicates the die ID and socket ID, which are bit[2:0] and bit[4:3] of aff3 respectively. The socket ID and die ID obtained from the mpidr do not correspond to the socket ID and die ID fields indicated by the bitmap register. Perform necessary conversion when writing the bitmap register based on the die ID and socket ID obtained from the mpidr. Fixes: 2671ba221968 ("kvm: hisi_virt: Update TLBI broadcast feature for hip12") Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- arch/arm64/kvm/hisilicon/hisi_virt.c | 12 +++++++++--- arch/arm64/kvm/hisilicon/hisi_virt.h | 5 +++++ 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c index d108b0ba3146..647fa62f2a4e 100644 --- a/arch/arm64/kvm/hisilicon/hisi_virt.c +++ b/arch/arm64/kvm/hisilicon/hisi_virt.c @@ -486,7 +486,9 @@ static void kvm_update_vm_lsudvmbm_hip12(struct kvm *kvm) if (nr_dies == 1) { val = DVMBM_RANGE_ONE_DIE << DVMBM_RANGE_SHIFT | - vm_aff3s[0] << DVMBM_DIE1_VDIE_SHIFT_HIP12; + (vm_aff3s[0] & MPIDR_AFF3_DIE_ID_MASK) << DVMBM_DIE1_VDIE_SHIFT_HIP12 | + ((vm_aff3s[0] & MPIDR_AFF3_SOCKET_ID_MASK) >> MPIDR_AFF3_SOCKET_ID_SHIFT) + << DVMBM_DIE1_SOCKET_SHIFT_HIP12; /* fulfill bits [11:6] */ for_each_cpu(cpu, kvm->arch.sched_cpus) { @@ -502,8 +504,12 @@ static void kvm_update_vm_lsudvmbm_hip12(struct kvm *kvm) /* nr_dies == 2 */ val = DVMBM_RANGE_TWO_DIES << DVMBM_RANGE_SHIFT | DVMBM_GRAN_CLUSTER << DVMBM_GRAN_SHIFT | - vm_aff3s[0] << DVMBM_DIE1_VDIE_SHIFT_HIP12 | - vm_aff3s[1] << DVMBM_DIE2_VDIE_SHIFT_HIP12; + (vm_aff3s[0] & MPIDR_AFF3_DIE_ID_MASK) << DVMBM_DIE1_VDIE_SHIFT_HIP12 | + ((vm_aff3s[0] & MPIDR_AFF3_SOCKET_ID_MASK) >> MPIDR_AFF3_SOCKET_ID_SHIFT) + << DVMBM_DIE1_SOCKET_SHIFT_HIP12 | + (vm_aff3s[1] & MPIDR_AFF3_DIE_ID_MASK) << DVMBM_DIE2_VDIE_SHIFT_HIP12 | + ((vm_aff3s[1] & MPIDR_AFF3_SOCKET_ID_MASK) >> MPIDR_AFF3_SOCKET_ID_SHIFT) + << DVMBM_DIE2_SOCKET_SHIFT_HIP12; /* and fulfill bits [11:0] */ for_each_cpu(cpu, kvm->arch.sched_cpus) { diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.h b/arch/arm64/kvm/hisilicon/hisi_virt.h index 85dccafde8a6..3ae2cb9e7890 100644 --- a/arch/arm64/kvm/hisilicon/hisi_virt.h +++ b/arch/arm64/kvm/hisilicon/hisi_virt.h @@ -70,11 +70,16 @@ enum hisi_cpu_type { #define DVMBM_MAX_DIES 32 /* HIP12 */ +#define DVMBM_DIE1_SOCKET_SHIFT_HIP12 59 +#define DVMBM_DIE2_SOCKET_SHIFT_HIP12 55 #define DVMBM_DIE1_VDIE_SHIFT_HIP12 57 #define DVMBM_DIE2_VDIE_SHIFT_HIP12 53 #define DVMBM_DIE1_CLUSTER_SHIFT_HIP12 6 #define DVMBM_DIE2_CLUSTER_SHIFT_HIP12 0 #define DVMBM_MAX_DIES_HIP12 8 +#define MPIDR_AFF3_DIE_ID_MASK 0x7 +#define MPIDR_AFF3_SOCKET_ID_MASK 0x18 +#define MPIDR_AFF3_SOCKET_ID_SHIFT 3 void probe_hisi_cpu_type(void); bool hisi_ncsnp_supported(void); -- 2.33.0