tree: https://gitee.com/openeuler/kernel.git OLK-6.6 head: 04473ee9ed912a16fff0d8846ad565bbf3d63c77 commit: 5d01c9ec4f3b95b0629a38d936f69bc05e494cc9 [3560/3560] pinctrl: Zhaoxin: Add KH-50000 support config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20251221/202512210228.QnsbClZ7-lkp@i...) compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251221/202512210228.QnsbClZ7-lkp@i...) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202512210228.QnsbClZ7-lkp@intel.com/ All warnings (new ones prefixed by >>): drivers/pinctrl/zhaoxin/pinctrl-zhaoxin.c:123:6: warning: variable 'value_back' set but not used [-Wunused-but-set-variable] 123 | u16 value_back = 0; | ^ drivers/pinctrl/zhaoxin/pinctrl-zhaoxin.c:249:6: warning: variable 'pin' set but not used [-Wunused-but-set-variable] 249 | int pin; | ^ drivers/pinctrl/zhaoxin/pinctrl-zhaoxin.c:270:6: warning: variable 'pin' set but not used [-Wunused-but-set-variable] 270 | int pin; | ^ drivers/pinctrl/zhaoxin/pinctrl-zhaoxin.c:330:6: warning: variable 'base_offset' set but not used [-Wunused-but-set-variable] 330 | int base_offset = 0; | ^ drivers/pinctrl/zhaoxin/pinctrl-zhaoxin.c:363:6: warning: variable 'base_offset' set but not used [-Wunused-but-set-variable] 363 | int base_offset = 0; | ^

...

drivers/pinctrl/zhaoxin/pinctrl-zhaoxin.c:487:6: warning: variable 'test_mask' set but not used [-Wunused-but-set-variable] 487 | u16 test_mask; | ^ 6 warnings generated.

vim +/test_mask +487 drivers/pinctrl/zhaoxin/pinctrl-zhaoxin.c 471 472 static int zhaoxin_gpio_irq_type(struct irq_data *d, unsigned int type) 473 { 474 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 475 struct zhaoxin_pinctrl *pctrl = gpiochip_get_data(gc); 476 unsigned int gpio = irqd_to_hwirq(d); 477 const struct index_cal_array *trigger_cal; 478 unsigned int pin; 479 unsigned long flags; 480 u8 index; 481 int position, point; 482 u16 value; 483 bool isup = true; 484 bool high_bit = false; 485 u16 mask = 0; 486 int bits_num = 0;

487 u16 test_mask; 488 489 trigger_cal = pctrl->pin_topologys->trigger_cal; 490 pin = zhaoxin_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL); 491 if (type & IRQ_TYPE_EDGE_FALLING) 492 isup = true; 493 else if (type & IRQ_TYPE_EDGE_RISING) 494 isup = true; 495 else if (type & IRQ_TYPE_LEVEL_LOW) 496 isup = true; 497 else if (type & IRQ_TYPE_LEVEL_HIGH) 498 isup = false; 499 500 zhaoxin_gpio_set_gpio_mode_and_pull(pctrl, pin, isup); 501 502 for (position = 0; position < trigger_cal->size; position++) 503 if (trigger_cal->cal_array[position] == gpio) 504 break; 505 mask = trigger_cal->mask; 506 bits_num = trigger_cal->bits_num; 507 index = trigger_cal->index + ALIGN(position + 1, 4) / 4 - 1; 508 point = position % 4; 509 if (point > 1) 510 high_bit = true; 511 512 raw_spin_lock_irqsave(&pctrl->lock, flags); 513 514 value = zx_pad_read16(pctrl, index); 515 516 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 517 if (high_bit) { 518 point = point - 2; 519 position = 8; 520 } else 521 position = 0; 522 test_mask = (~(mask << (point * bits_num + position))); 523 value &= (~(mask << (point * bits_num + position))); 524 value |= TRIGGER_BOTH_EDGE << (point * bits_num + position); 525 } else if (type & IRQ_TYPE_EDGE_FALLING) { 526 if (high_bit) { 527 point = point - 2; 528 position = 8; 529 } else 530 position = 0; 531 test_mask = (~(mask << (point * bits_num + position))); 532 value &= (~(mask << (point * bits_num + position))); 533 value |= TRIGGER_FALL_EDGE << (point * bits_num + position); 534 } else if (type & IRQ_TYPE_EDGE_RISING) { 535 if (high_bit) { 536 point = point - 2; 537 position = 8; 538 } else 539 position = 0; 540 test_mask = (~(mask << (point * bits_num + position))); 541 value &= (~(mask << (point * bits_num + position))); 542 value |= TRIGGER_RISE_EDGE << (point * bits_num + position); 543 } else if (type & IRQ_TYPE_LEVEL_LOW) { 544 if (high_bit) { 545 point = point - 2; 546 position = 8; 547 } else 548 position = 0; 549 test_mask = (~(mask << (point * bits_num + position))); 550 value &= (~(mask << (point * bits_num + position))); 551 value |= TRIGGER_LOW_LEVEL << (point * bits_num + position); 552 } else if (type & IRQ_TYPE_LEVEL_HIGH) { 553 if (high_bit) { 554 point = point - 2; 555 position = 8; 556 } else 557 position = 0; 558 test_mask = (~(mask << (point * bits_num + position))); 559 value &= (~(mask << (point * bits_num + position))); 560 value |= TRIGGER_HIGH_LEVEL << (point * bits_num + position); 561 } 562 563 zx_pad_write16(pctrl, index, value); 564 565 if (type & IRQ_TYPE_EDGE_BOTH) 566 irq_set_handler_locked(d, handle_edge_irq); 567 else if (type & IRQ_TYPE_LEVEL_MASK) 568 irq_set_handler_locked(d, handle_level_irq); 569 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 570 571 return 0; 572 } 573

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