[PATCH 0/5] Transition from CPU Type to MIDR Register for Virtualization Feature Detection
Currently, there are two methods for determining whether a chip supports specific virtualization features: 1. Reading the chip's CPU type from BIOS 2. Reading the value of the MIDR register The issue with the first method is that each time a new chip is introduced, the new CPU type must be defined, which leads to poor code portability and maintainability. Therefore, the second method has been adopted to replace the first. This approach eliminates the dependency on CPU type by using the MIDR register and removes the need for defining CPU types and their related interfaces. liqiqi (5): kvm: arm64: use MIDR_HISI_TSV110 to determine whether NCSNP is supported kvm: arm64: Add HIP10, HIP10C MIDR definitions kvm: arm64: Use MIDR to determine whether DVMBM is supported kvm: arm64: Use MIDR to determine whether IPIv is supported kvm: arm64: Remove cpu_type definition and it's related interfaces arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kvm/arm.c | 1 - arch/arm64/kvm/hisilicon/hisi_virt.c | 111 +++------------------------ arch/arm64/kvm/hisilicon/hisi_virt.h | 12 --- 4 files changed, 15 insertions(+), 113 deletions(-) -- 2.43.0
virt inclusion category:bugfix bugzilla:https://atomgit.com/openeuler/kernel/issues/8756 CVE:NA ----------------------------------------------------------- For compatibility reasons, MIDR_HISI_TSV110 is used instead of HI_1620 to determine whether NCSNP is supported. Signed-off-by:Li Qiqi <liqiqi23@huawei.com> --- arch/arm64/kvm/hisilicon/hisi_virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c index d82c7691836e..8133f4704f05 100644 --- a/arch/arm64/kvm/hisilicon/hisi_virt.c +++ b/arch/arm64/kvm/hisilicon/hisi_virt.c @@ -121,7 +121,7 @@ bool hisi_ncsnp_supported(void) unsigned int high; bool supported = false; - if (cpu_type != HI_1620) + if (read_cpuid_id() != MIDR_HISI_TSV110) return supported; base = ioremap(NCSNP_MMIO_BASE, 4); -- 2.43.0
virt inclusion category:bugfix bugzilla:https://atomgit.com/openeuler/kernel/issues/8756 CVE:NA ----------------------------------------------------------- Add MIDR definitions MIDR_HISI_HIP10, MIDR_HISI_HIP10C. Signed-off-by:Li Qiqi <liqiqi23@huawei.com> --- arch/arm64/include/asm/cputype.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 490c2ac36ac0..c9465418c3d6 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -142,6 +142,8 @@ #define HISI_CPU_PART_TSV110 0xD01 #define HISI_CPU_PART_LINXICORE9100 0xD02 +#define HISI_CPU_PART_HIP10 0xD03 +#define HISI_CPU_PART_HIP10C 0xD45 #define HISI_CPU_PART_HIP12 0xD06 #define APPLE_CPU_PART_M1_ICESTORM 0x022 @@ -230,6 +232,8 @@ #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) #define MIDR_HISI_LINXICORE9100 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_LINXICORE9100) +#define MIDR_HISI_HIP10 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP10) +#define MIDR_HISI_HIP10C MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP10C) #define MIDR_HISI_HIP12 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP12) #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) -- 2.43.0
virt inclusion category:bugfix bugzilla:https://atomgit.com/openeuler/kernel/issues/8756 CVE:NA ----------------------------------------------------------- Use the IMPLEMENTOR field of the MIDR register instead of cpu_type to determine whether DVMBM is supported and to handle DVMBM bug fixes for HIP10 and HIP10C chips. Signed-off-by:Li Qiqi <liqiqi23@huawei.com> --- arch/arm64/kvm/hisilicon/hisi_virt.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c index 8133f4704f05..0da705119efc 100644 --- a/arch/arm64/kvm/hisilicon/hisi_virt.c +++ b/arch/arm64/kvm/hisilicon/hisi_virt.c @@ -232,8 +232,7 @@ void ipiv_gicd_init(void) bool hisi_dvmbm_supported(void) { - if (cpu_type != HI_IP10 && cpu_type != HI_IP10C && - cpu_type != HI_IP12) + if (read_cpuid_implementor() != ARM_CPU_IMP_HISI) return false; if (!is_kernel_in_hyp_mode()) { @@ -542,6 +541,7 @@ void kvm_tlbi_dvmbm_vcpu_load(struct kvm_vcpu *vcpu) struct kvm_vcpu *tmp; cpumask_t mask; unsigned long i; + u32 midr; /* Don't bother on old hardware */ if (!kvm_dvmbm_support) @@ -581,10 +581,11 @@ void kvm_tlbi_dvmbm_vcpu_load(struct kvm_vcpu *vcpu) * Re-calculate LSUDVMBM_EL2 for this VM and kick all vcpus * out to reload the LSUDVMBM configuration. */ - if (cpu_type == HI_IP12) - kvm_update_vm_lsudvmbm_hip12(kvm); - else + midr = read_cpuid_id(); + if (midr == MIDR_HISI_HIP10 || midr == MIDR_HISI_HIP10C) kvm_update_vm_lsudvmbm(kvm); + else + kvm_update_vm_lsudvmbm_hip12(kvm); kvm_make_all_cpus_request(kvm, KVM_REQ_RELOAD_TLBI_DVMBM); out_unlock: @@ -608,8 +609,10 @@ void kvm_get_pg_cfg(void) u32 pg_cfgs[MAX_PG_CFG_SOCKETS * MAX_DIES_PER_SOCKET]; u64 mn_phy_base; u32 val; + u32 midr; - if (cpu_type == HI_IP12) + midr = read_cpuid_id(); + if (midr != MIDR_HISI_HIP10 && midr != MIDR_HISI_HIP10C) return; socket_num = kvm_get_socket_num(); -- 2.43.0
virt inclusion category:bugfix bugzilla:https://atomgit.com/openeuler/kernel/issues/8756 CVE:NA ----------------------------------------------------------- Use the IMPLEMENTOR field of the MIDR register instead of cpu_type to judge whether IPIv is supported. Signed-off-by:Li Qiqi <liqiqi23@huawei.com> --- arch/arm64/kvm/hisilicon/hisi_virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c index 0da705119efc..a0a9748f1bec 100644 --- a/arch/arm64/kvm/hisilicon/hisi_virt.c +++ b/arch/arm64/kvm/hisilicon/hisi_virt.c @@ -171,7 +171,7 @@ early_param("kvm-arm.ipiv_enabled", early_ipiv_enable); bool hisi_ipiv_supported(void) { - if (cpu_type != HI_IP12) + if (read_cpuid_implementor() != ARM_CPU_IMP_HISI) return false; /* Determine whether IPIV is supported by the hardware */ -- 2.43.0
virt inclusion category:bugfix bugzilla:https://atomgit.com/openeuler/kernel/issues/8756 CVE:NA ----------------------------------------------------------- Currently, there are two methods for determining whether a chip supports certain features: 1. Reading the chip's CPU type from the BIOS 2. Reading the value of the MIDR register The issue with method 1 is that each time a new chip is introduced, the corresponding CPU type needs to be defined, resulting in poor code compatibility. Therefore, method 2 has been adopted to replace method 1. Previous patches have already eliminated the dependency on CPU type, let's remove the definition of CPU type and its related interfaces. Signed-off-by:Li Qiqi <liqiqi23@huawei.com> --- arch/arm64/kvm/arm.c | 1 - arch/arm64/kvm/hisilicon/hisi_virt.c | 92 ---------------------------- arch/arm64/kvm/hisilicon/hisi_virt.h | 12 ---- 3 files changed, 105 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 7f7dbf90659f..93097a8876df 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -2929,7 +2929,6 @@ static __init int kvm_arm_init(void) return err; } - probe_hisi_cpu_type(); kvm_ncsnp_support = hisi_ncsnp_supported(); kvm_dvmbm_support = hisi_dvmbm_supported(); kvm_info("KVM ncsnp %s\n", kvm_ncsnp_support ? "enabled" : "disabled"); diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c index a0a9748f1bec..1e5fc5d0ed00 100644 --- a/arch/arm64/kvm/hisilicon/hisi_virt.c +++ b/arch/arm64/kvm/hisilicon/hisi_virt.c @@ -10,104 +10,12 @@ #include "hisi_virt.h" #include <linux/bitfield.h> -static enum hisi_cpu_type cpu_type = UNKNOWN_HI_TYPE; - static bool dvmbm_enabled; #ifdef CONFIG_ARM64_HISI_IPIV static bool ipiv_enabled; #endif -static const char * const hisi_cpu_type_str[] = { - "Hisi1612", - "Hisi1616", - "Hisi1620", - "HIP09", - "HIP10", - "HIP10C", - "HIP12", - "Unknown" -}; - -/* ACPI Hisi oem table id str */ -static const char * const oem_str[] = { - "HIP06 ", /* Hisi 1612 */ - "HIP07 ", /* Hisi 1616 */ - "HIP08 ", /* Hisi 1620 */ - "HIP09 ", /* HIP09 */ - "HIP10 ", /* HIP10 */ - "HIP10C ", /* HIP10C */ - "HIP12 " /* HIP12 */ -}; - -/* - * Probe Hisi CPU type form ACPI. - */ -static enum hisi_cpu_type acpi_get_hisi_cpu_type(void) -{ - struct acpi_table_header *table; - acpi_status status; - int i, str_size = ARRAY_SIZE(oem_str); - - /* Get oem table id from ACPI table header */ - status = acpi_get_table(ACPI_SIG_DSDT, 0, &table); - if (ACPI_FAILURE(status)) { - pr_warn("Failed to get ACPI table: %s\n", - acpi_format_exception(status)); - return UNKNOWN_HI_TYPE; - } - - for (i = 0; i < str_size; ++i) { - if (!strncmp(oem_str[i], table->oem_table_id, 8)) - return i; - } - - return UNKNOWN_HI_TYPE; -} - -/* of Hisi cpu model str */ -static const char * const of_model_str[] = { - "Hi1612", - "Hi1616" -}; - -/* - * Probe Hisi CPU type from DT. - */ -static enum hisi_cpu_type of_get_hisi_cpu_type(void) -{ - const char *model; - int ret, i, str_size = ARRAY_SIZE(of_model_str); - - /* - * Note: There may not be a "model" node in FDT, which - * is provided by the vendor. In this case, we are not - * able to get CPU type information through this way. - */ - ret = of_property_read_string(of_root, "model", &model); - if (ret < 0) { - pr_warn("Failed to get Hisi cpu model by OF.\n"); - return UNKNOWN_HI_TYPE; - } - - for (i = 0; i < str_size; ++i) { - if (strstr(model, of_model_str[i])) - return i; - } - - return UNKNOWN_HI_TYPE; -} - -void probe_hisi_cpu_type(void) -{ - if (!acpi_disabled) - cpu_type = acpi_get_hisi_cpu_type(); - else - cpu_type = of_get_hisi_cpu_type(); - - kvm_info("detected: Hisi CPU type '%s'\n", hisi_cpu_type_str[cpu_type]); -} - /* * We have the fantastic HHA ncsnp capability on Kunpeng 920, * with which hypervisor doesn't need to perform a lot of cache diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.h b/arch/arm64/kvm/hisilicon/hisi_virt.h index 180618e42cbc..b89c779e0869 100644 --- a/arch/arm64/kvm/hisilicon/hisi_virt.h +++ b/arch/arm64/kvm/hisilicon/hisi_virt.h @@ -7,16 +7,6 @@ #define __HISI_VIRT_H__ #ifdef CONFIG_KVM_HISI_VIRT -enum hisi_cpu_type { - HI_1612, - HI_1616, - HI_1620, - HI_IP09, - HI_IP10, - HI_IP10C, - HI_IP12, - UNKNOWN_HI_TYPE -}; /* HIP12 */ #ifdef CONFIG_ARM64_HISI_IPIV @@ -91,7 +81,6 @@ enum hisi_cpu_type { #define DVMBM_DIE2_CLUSTER_SHIFT_HIP12 0 #define DVMBM_MAX_DIES_HIP12 8 -void probe_hisi_cpu_type(void); bool hisi_ncsnp_supported(void); bool hisi_dvmbm_supported(void); #ifdef CONFIG_ARM64_HISI_IPIV @@ -110,7 +99,6 @@ void kvm_tlbi_dvmbm_vcpu_load(struct kvm_vcpu *vcpu); void kvm_tlbi_dvmbm_vcpu_put(struct kvm_vcpu *vcpu); void kvm_hisi_reload_lsudvmbm(struct kvm *kvm); #else -static inline void probe_hisi_cpu_type(void) {} static inline bool hisi_ncsnp_supported(void) { return false; -- 2.43.0
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