driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICUJ1T ---------------------------------------------------------------------- The current interrupt policy of the Hip12 preferentially schedules LPI and SGI interrupts with the same priority. As a result, the arch_timer may not be executed when frequent LPI/SGI interrupts are generated, and the watchdog is starved. Signed-off-by: Qinxin Xia <xiaqinxin@huawei.com> Signed-off-by: Hongye Lin <linhongye@h-partners.com> --- arch/arm64/Kconfig | 11 +++++++ arch/arm64/configs/openeuler_defconfig | 1 + drivers/clocksource/arm_arch_timer.c | 44 ++++++++++++++++++++++++++ drivers/irqchip/irq-gic-v3.c | 2 +- include/linux/irqchip/arm-gic-v3.h | 4 +++ 5 files changed, 61 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index bb72e23b183a..5fb0190e8e9a 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1290,6 +1290,17 @@ config HISILICON_ERRATUM_162102203 If unsure, say N. +config HISILICON_ERRATUM_165010801 + bool "Hisilicon erratum 165010801" + depends on ARCH_HISI + default y + help + On HIP12, when GIC receives multiple interrupts of the same priority and + different types, the interrupts are selected in the following sequence: + SPI > LPI > SGI > PPI. This scheduling rule may cause PPI starvation. + To prevent starvation from triggering system watchdog hardlockup, the + interrupt priority is explicitly increased in the arch_timer driver. + config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 8848ca6fdda0..ccb66e9dc1bc 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -6619,6 +6619,7 @@ CONFIG_FSL_ERRATUM_A008585=y CONFIG_HISILICON_ERRATUM_161010101=y CONFIG_ARM64_ERRATUM_858921=y CONFIG_ARM_TIMER_SP804=y +CONFIG_HISILICON_ERRATUM_165010801=y # CONFIG_ARM_ARCH_TIMER_WORKAROUND_IN_USERSPACE is not set # end of Clock Source drivers diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 8a8b579185dc..867b83c37bdb 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -29,6 +29,11 @@ #include <linux/arm-smccc.h> #include <linux/ptp_kvm.h> +#ifdef CONFIG_HISILICON_ERRATUM_165010801 +#include <linux/irqchip/arm-gic-common.h> +#include <linux/irqchip/arm-gic-v3.h> +#endif + #include <asm/arch_timer.h> #include <asm/virt.h> @@ -96,6 +101,9 @@ static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_NONE; static bool vdso_fix; static u16 vdso_shift; #endif +#ifdef CONFIG_HISILICON_ERRATUM_165010801 +static bool prio_setup; +#endif static cpumask_t evtstrm_available = CPU_MASK_NONE; static bool evtstrm_enable __ro_after_init = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM); @@ -359,6 +367,17 @@ static struct ate_acpi_oem_info hisi_161010101_oem_info[] = { }; #endif +#ifdef CONFIG_HISILICON_ERRATUM_165010801 +static struct ate_acpi_oem_info hisi_165010801_oem_info[] = { + { + .oem_id = "HISI ", + .oem_table_id = "HIP12 ", + .oem_revision = 0, + }, + { /* Sentinel indicating the end of the OEM array */ }, +}; +#endif + #ifdef CONFIG_ARM64_ERRATUM_858921 static u64 notrace arm64_858921_read_cntpct_el0(void) { @@ -489,6 +508,13 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .set_next_event_virt = erratum_set_next_event_virt, }, #endif +#ifdef CONFIG_HISILICON_ERRATUM_165010801 + { + .match_type = ate_match_acpi_oem_info, + .id = hisi_165010801_oem_info, + .desc = "HiSilicon erratum 165010801", + }, +#endif #ifdef CONFIG_ARM64_ERRATUM_858921 { .match_type = ate_match_local_cap_id, @@ -596,6 +622,12 @@ void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa if (wa->read_cntvct_el0 || wa->read_cntpct_el0) atomic_set(&timer_unstable_counter_workaround_in_use, 1); +#ifdef CONFIG_HISILICON_ERRATUM_165010801 + if (!strncmp(wa->desc, "HiSilicon erratum 165010801", + strlen("HiSilicon erratum 165010801"))) + prio_setup = true; +#endif + /* * Don't use the vdso fastpath if errata require using the * out-of-line counter accessor. We may change our mind pretty @@ -1030,6 +1062,18 @@ static int arch_timer_starting_cpu(unsigned int cpu) __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk); +#ifdef CONFIG_HISILICON_ERRATUM_165010801 + if (prio_setup && is_kernel_in_hyp_mode()) { + struct irq_data *d = irq_get_irq_data(arch_timer_ppi[arch_timer_uses_ppi]); + + if (!d) + pr_warn("WARNING: Invalid arch_timer ppi irq: %d!\n", + arch_timer_ppi[arch_timer_uses_ppi]); + else + gic_irq_set_prio(d, GICD_INT_DEF_PRI & (GICD_INT_DEF_PRI - 1)); + } +#endif + flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags); diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 4be2dd801cda..849d2e0db4fd 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -558,7 +558,7 @@ static int gic_irq_get_irqchip_state(struct irq_data *d, return 0; } -static void gic_irq_set_prio(struct irq_data *d, u8 prio) +void gic_irq_set_prio(struct irq_data *d, u8 prio) { void __iomem *base = gic_dist_base(d); u32 offset, index; diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 8e97525a3afd..903d79b3b55d 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -771,6 +771,10 @@ enum xint_op { void register_irqchip_proc(struct irq_desc *desc, void *irqp); void unregister_irqchip_proc(struct irq_desc *desc); #endif + +#ifdef CONFIG_HISILICON_ERRATUM_165010801 +extern void gic_irq_set_prio(struct irq_data *d, u8 prio); +#endif #endif #endif -- 2.33.0