hulk inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8NRI6 CVE: NA -------------------------------- This was missed when making specification of a field standard. Fixes: 2ee4c87e5fd2e ("arm64: cpufeature: Always specify and use a field width for capabilities") Signed-off-by: Wang ShaoBo <bobo.shaobowang@huawei.com> --- arch/arm64/kernel/cpufeature.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b13deca20432e..6c07804d94667 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2324,6 +2324,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sys_reg = SYS_ID_AA64PFR0_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64PFR0_MPAM_SHIFT, + .field_width = 4, .min_field_value = ID_AA64PFR0_MPAM, }, #endif /* CONFIG_MPAM */ @@ -2605,6 +2606,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .sys_reg = SYS_ID_AA64MMFR1_EL1, .field_pos = ID_AA64MMFR1_TWED_SHIFT, + .field_width = 4, .sign = FTR_UNSIGNED, .min_field_value = 1, }, @@ -2616,6 +2618,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sys_reg = SYS_ID_AA64ISAR2_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR2_WFXT_SHIFT, + .field_width = 4, .matches = has_cpuid_feature, .min_field_value = ID_AA64ISAR2_WFXT_SUPPORTED, }, @@ -2626,6 +2629,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sys_reg = SYS_ID_AA64ISAR1_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64ISAR1_LRCPC_SHIFT, + .field_width = 4, .matches = has_cpuid_feature, .min_field_value = 1, }, @@ -2635,6 +2639,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sys_reg = SYS_ID_AA64MMFR1_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64MMFR1_HPD_SHIFT, + .field_width = 4, .matches = has_cpuid_feature, .min_field_value = 2, }, @@ -2646,6 +2651,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .sys_reg = SYS_ID_AA64MMFR1_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64MMFR1_HPD_SHIFT, + .field_width = 4, .matches = plat_can_use_pbha_stage1, .min_field_value = 2, .cpu_enable = cpu_enable_pbha, -- 2.25.1