hulk inclusion category: bugfix bugzilla: https://gitee.com/src-openeuler/kernel/issues/I913T5 CVE: NA ----------------------------------------------- The commit 8544c8e14fec ("iommu/arm-smmu-v3: Add a SYNC command to avoid broken page table prefetch") use particular cpu cap the identify the problem with smmu, which is not suitable. So, using the smmu registers to identify the problem. Signed-off-by: Zhang Zekun <zhangzekun11@huawei.com> --- arch/arm64/Kconfig | 2 +- arch/arm64/include/asm/cpucaps.h | 1 - arch/arm64/kernel/cpu_errata.c | 14 -------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 +++++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 +++++ 5 files changed, 15 insertions(+), 17 deletions(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 429a6abb2f4d..5c0178e307a4 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -838,7 +838,7 @@ config HISILICON_ERRATUM_162102203 config HISILICON_ERRATUM_162100602 bool "Hisilicon erratum 162100602" - depends on ARM_SMMU_V3 + depends on ARM_SMMU_V3 && ARCH_HISI default y help On Hisilicon LINXICORE9100 cores, SMMU pagetable prefetch features may diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 0220f10cddd7..ce9fbf260a3c 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -81,7 +81,6 @@ #define ARM64_HAS_PBHA_STAGE2 73 #define ARM64_SME 74 #define ARM64_SME_FA64 75 -#define ARM64_WORKAROUND_HISILICON_ERRATUM_162100602 76 #define ARM64_NCAPS 80 diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 6a3e948d5c2c..7f175b3aac15 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -331,13 +331,6 @@ static const struct midr_range hisilicon_erratum_162100125_cpus[] = { }; #endif -#ifdef CONFIG_HISILICON_ERRATUM_162100602 -static const struct midr_range hisilicon_erratum_162100602_cpus[] = { - MIDR_REV(MIDR_HISI_LINXICORE9100, 0, 0), - {}, -}; -#endif - #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = { { @@ -540,13 +533,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100125_cpus), }, #endif -#ifdef CONFIG_HISILICON_ERRATUM_162100602 - { - .desc = "Hisilicon erratum 162100602", - .capability = ARM64_WORKAROUND_HISILICON_ERRATUM_162100602, - ERRATA_MIDR_RANGE_LIST(hisilicon_erratum_162100602_cpus), - }, -#endif #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 { .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003", diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 458151b7fab2..dd099725c72c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2948,7 +2948,7 @@ static void arm_smmu_iotlb_sync_map(struct iommu_domain *domain, struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); size_t granule_size; - if (!cpus_have_const_cap(ARM64_WORKAROUND_HISILICON_ERRATUM_162100602)) + if (!(smmu_domain->smmu->options | ARM_SMMU_OPT_SYNC_MAP)) return; granule_size = 1 << __ffs(smmu_domain->domain.pgsize_bitmap); @@ -5146,6 +5146,14 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) smmu->oas = 48; } +#ifdef CONFIG_HISILICON_ERRATUM_162100602 + /* IIDR */ + reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR); + if (FIELD_GET(IIDR_VARIANT, reg) == 0x3 && + FIELD_GET(IIDR_REVISON, reg) == 0x2) + smmu->options |= ARM_SMMU_OPT_SYNC_MAP; +#endif + if (arm_smmu_ops.pgsize_bitmap == -1UL) arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; else diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 919473d2217b..776d326de105 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -80,6 +80,10 @@ #define IDR5_VAX GENMASK(11, 10) #define IDR5_VAX_52_BIT 1 +#define ARM_SMMU_IIDR 0x18 +#define IIDR_VARIANT GENMASK(19, 16) +#define IIDR_REVISON GENMASK(15, 12) + #define ARM_SMMU_CR0 0x20 #define CR0_ATSCHK (1 << 4) #define CR0_CMDQEN (1 << 3) @@ -712,6 +716,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) #define ARM_SMMU_OPT_MSIPOLL (1 << 2) +#define ARM_SMMU_OPT_SYNC_MAP (1 << 3) u32 options; union { -- 2.17.1