[PATCH OLK-6.6 0/1] Fix TLBI broadcast optimization loss and incorrect dvmbm handling
Fix 1 In the TLBI broadcast-optimization feature, the SYS_LSUDVM_CTRL_EL2 register controls whether the feature is enabled. When LPI low-power mode is enabled, this register is cleared as the pCPU powers down into LPI mode, causing the TLBI broadcast optimization to stop working. The fix saves and restores this control register in the callbacks for entering and exiting LPI mode. Fix 2 The current TLBI broadcast-optimization logic only supports normal VMs. If the feature is enabled globally, VMs that are not yet adapted for it, such as CCA will use an incorrect TLBI broadcast bitmap, which can cause a panic in CCA VMs. The fix moves the actual enable/disable of the dvmbm functionality into the vcpu load and vcpu put functions. Tian Zheng (1): KVM: arm64: Fix CCA guest panic when dvmbm is enabled arch/arm64/kvm/hisilicon/hisi_virt.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) -- 2.33.0
virt inclusion category: bugfix bugzilla: https://atomgit.com/openeuler/kernel/issues/8610 -------------------------------------------------------------------- Enabling TLBI optimization via kvm-arm.dvmbm_enabled=1 permanently sets the SYS_LSUDVM_CTRL_EL2 control bit. Since CCA doesn't yet support this feature, CCA VMs will read an erroneous bitmap from SYS_LSUDVMBM_EL2 when performing TLB flushes, causing a panic. To avoid this issue, this patch dynamically sets/clears the bit in vcpu_load/vcpu_put, limiting the optimization to normal VMs only. Although the default value of SYS_LSUDVM_CTRL_EL2 is 0, we still reset it to 0 in kvm_arm_init for safety. This patch can also solve another issue: When LPI is enabled, a CPU may enter power-down mode. During this transition, the dvmbm ctrl register is reset to 0 after the cpu powers down, which can cause functional breakdown. Kernel ensures that no threads are running on the pCPU before entering the power-down mode. Therefore, vCPU must have been put before this pCPU powers down. When the vCPU runs again, vcpu_load will rewrite the control register. This guarantees that even if the register is reset to 0 during power-down mode, it will no longer affect the TLBI broadcast optimization. Fixes: e85b97c7e2b4 ("KVM: arm64: Probe and configure DVMBM capability on HiSi CPUs") Signed-off-by: Tian Zheng <zhengtian10@huawei.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> --- arch/arm64/kvm/hisilicon/hisi_virt.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/arch/arm64/kvm/hisilicon/hisi_virt.c b/arch/arm64/kvm/hisilicon/hisi_virt.c index 5731d337b228..d82c7691836e 100644 --- a/arch/arm64/kvm/hisilicon/hisi_virt.c +++ b/arch/arm64/kvm/hisilicon/hisi_virt.c @@ -144,7 +144,7 @@ static int __init early_dvmbm_enable(char *buf) } early_param("kvm-arm.dvmbm_enabled", early_dvmbm_enable); -static void hardware_enable_dvmbm(void *data) +static void hardware_enable_dvmbm(void) { u64 val; @@ -245,18 +245,10 @@ bool hisi_dvmbm_supported(void) if (!(read_sysreg(aidr_el1) & AIDR_EL1_DVMBM_MASK)) return false; - /* User provided kernel command-line parameter */ - if (!dvmbm_enabled) { - on_each_cpu(hardware_disable_dvmbm, NULL, 1); - return false; - } + /* reset */ + on_each_cpu(hardware_disable_dvmbm, NULL, 1); - /* - * Enable TLBI Broadcast optimization by setting - * LSUDVM_CTRL_EL2's bit[0]. - */ - on_each_cpu(hardware_enable_dvmbm, NULL, 1); - return true; + return dvmbm_enabled; } int kvm_sched_affinity_vcpu_init(struct kvm_vcpu *vcpu) @@ -555,6 +547,7 @@ void kvm_tlbi_dvmbm_vcpu_load(struct kvm_vcpu *vcpu) if (!kvm_dvmbm_support) return; + hardware_enable_dvmbm(); cpumask_copy(vcpu->arch.sched_cpus, current->cpus_ptr); if (likely(cpumask_equal(vcpu->arch.sched_cpus, @@ -605,6 +598,7 @@ void kvm_tlbi_dvmbm_vcpu_put(struct kvm_vcpu *vcpu) return; cpumask_copy(vcpu->arch.pre_sched_cpus, vcpu->arch.sched_cpus); + hardware_disable_dvmbm(NULL); } void kvm_get_pg_cfg(void) -- 2.33.0
participants (1)
-
Tian Zheng