[PATCH OLK-6.6 v2 0/5] irqchip: gic: some bugfix of hip10
Patch#1,2: revert hip09 erratum 162200803 and 162200806 Patch#3: fix one soc bug with vPE schedule for gicv4.0 Patch#4: fix another soc bug with inaccurate pending status for gicv4.1 Patch#5: Fix the bug that a large-specification VM fails to be created. Kunkun Jiang (2): KVM: arm64: vgic-v3: Add workaround for HIP10 erratum 162200806 irqchip/gic-v4.1:Check whether indirect table is supported in allocate_vpe_l1_table Zhou Wang (3): Revert "irqchip: gicv3: Add workaround for hip09 erratum 162200806" Revert "irqchip: gicv3: Add workaround for hip09 erratum 162200803" irqchip: gicv3: Add workaround for hip10 erratum 162200803 Documentation/arch/arm64/silicon-errata.rst | 4 +- arch/arm64/kvm/vgic/vgic-mmio-v3.c | 2 +- arch/arm64/kvm/vgic/vgic-mmio.c | 51 ++++++++++++--------- arch/arm64/kvm/vgic/vgic-mmio.h | 3 +- drivers/irqchip/irq-gic-v3-its.c | 8 +++- drivers/irqchip/irq-gic-v3.c | 30 ++++-------- 6 files changed, 49 insertions(+), 49 deletions(-) -- 2.33.0
driver inclusion category: other bugzilla: https://gitee.com/openeuler/kernel/issues/I9KBKD ------------------------------------------------------------------ This reverts commit cb0003ae0500bb69eefa2275722d08bc39a0f157. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: caijian <caijian11@h-partners.com> --- Documentation/arch/arm64/silicon-errata.rst | 2 -- arch/arm64/kvm/vgic/vgic-mmio.c | 17 ----------------- arch/arm64/kvm/vgic/vgic-mmio.h | 1 - drivers/irqchip/irq-gic-v3.c | 16 ---------------- 4 files changed, 36 deletions(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index ef58c86cd10b..66e02dba6cc9 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -215,8 +215,6 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | Hip09 | #162200803 | N/A | +----------------+-----------------+-----------------+-----------------------------+ -| Hisilicon | Hip09 | #162200806 | N/A | -+----------------+-----------------+-----------------+-----------------------------+ | Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | +----------------+-----------------+-----------------+-----------------------------+ | Qualcomm Tech. | Kryo/Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | diff --git a/arch/arm64/kvm/vgic/vgic-mmio.c b/arch/arm64/kvm/vgic/vgic-mmio.c index 56549ee4313c..59b81e5ce1d8 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio.c +++ b/arch/arm64/kvm/vgic/vgic-mmio.c @@ -228,7 +228,6 @@ int vgic_uaccess_write_cenable(struct kvm_vcpu *vcpu, return 0; } -#define VIRTUAL_SGI_PENDING_OFFSET 0x3F0 static unsigned long __read_pending(struct kvm_vcpu *vcpu, gpa_t addr, unsigned int len, bool is_user) @@ -236,7 +235,6 @@ static unsigned long __read_pending(struct kvm_vcpu *vcpu, u32 intid = VGIC_ADDR_TO_INTID(addr, 1); u32 value = 0; int i; - struct its_vpe *vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe; /* Loop over all IRQs affected by this read */ for (i = 0; i < len * 8; i++) { @@ -257,21 +255,6 @@ static unsigned long __read_pending(struct kvm_vcpu *vcpu, if (vgic_direct_sgi_or_ppi(irq)) { int err; - if (irq->hw && vgic_irq_is_sgi(irq->intid) && - (kvm_vgic_global_state.flags & - FLAGS_WORKAROUND_HIP09_ERRATUM_162200806)) { - void *va; - u8 *ptr; - int mask; - bool is_pending; - - mask = BIT(irq->intid % BITS_PER_BYTE); - va = page_address(vpe->vpt_page); - ptr = va + VIRTUAL_SGI_PENDING_OFFSET + - irq->intid / BITS_PER_BYTE; - is_pending = *ptr & mask; - } - val = false; err = irq_get_irqchip_state(irq->host_irq, IRQCHIP_STATE_PENDING, diff --git a/arch/arm64/kvm/vgic/vgic-mmio.h b/arch/arm64/kvm/vgic/vgic-mmio.h index 0477ec95e96c..55f49933e304 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio.h +++ b/arch/arm64/kvm/vgic/vgic-mmio.h @@ -6,7 +6,6 @@ #define __KVM_ARM_VGIC_MMIO_H__ #define FLAGS_WORKAROUND_HIP09_ERRATUM_162200803 (1ULL << 4) -#define FLAGS_WORKAROUND_HIP09_ERRATUM_162200806 (1ULL << 5) struct vgic_register_region { unsigned int reg_offset; diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index d287e7199cfe..34405577c458 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -42,7 +42,6 @@ #define FLAGS_WORKAROUND_MTK_GICR_SAVE (1ULL << 2) #define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 3) #define FLAGS_WORKAROUND_HIP09_ERRATUM_162200803 (1ULL << 4) -#define FLAGS_WORKAROUND_HIP09_ERRATUM_162200806 (1ULL << 5) #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) @@ -2002,15 +2001,6 @@ static bool gic_enable_quirk_hip09_162200803(void *data) return true; } -static bool __maybe_unused gic_enable_quirk_hip09_162200806(void *data) -{ - struct gic_chip_data *d = data; - - d->flags |= FLAGS_WORKAROUND_HIP09_ERRATUM_162200806; - - return true; -} - static const struct gic_quirk gic_quirks[] = { { .desc = "GICv3: Qualcomm MSM8996 broken firmware", @@ -2088,12 +2078,6 @@ static const struct gic_quirk gic_quirks[] = { .mask = 0xffffffff, .init = gic_enable_quirk_hip09_162200803, }, - { - .desc = "GICv3: HIP09 erratum 162200806", - .iidr = 0x01050736, - .mask = 0xffffffff, - .init = gic_enable_quirk_hip09_162200806, - }, { } }; -- 2.33.0
driver inclusion category: other bugzilla: https://gitee.com/openeuler/kernel/issues/I9KBKD ------------------------------------------------------------------ This reverts commit 12e11032205ea40d7046cdecce3b775f69034e2e. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: caijian <caijian11@h-partners.com> --- Documentation/arch/arm64/silicon-errata.rst | 2 -- arch/arm64/kvm/vgic/vgic-init.c | 1 - arch/arm64/kvm/vgic/vgic-mmio-v3.c | 4 ---- arch/arm64/kvm/vgic/vgic-mmio.h | 2 -- drivers/irqchip/irq-gic-v3.c | 20 -------------------- include/kvm/arm_vgic.h | 1 - include/linux/irqchip/arm-gic-v3.h | 2 -- include/linux/irqchip/arm-vgic-info.h | 1 - 8 files changed, 33 deletions(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index 66e02dba6cc9..5230538cedfe 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -213,8 +213,6 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | SMMUv3 | #162100602 | HISILICON_ERRATUM_162100602 | +----------------+-----------------+-----------------+-----------------------------+ -| Hisilicon | Hip09 | #162200803 | N/A | -+----------------+-----------------+-----------------+-----------------------------+ | Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | +----------------+-----------------+-----------------+-----------------------------+ | Qualcomm Tech. | Kryo/Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index db5db9402c3a..60f860a1dcaa 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -615,7 +615,6 @@ int kvm_vgic_hyp_init(void) kvm_vgic_global_state.no_hw_deactivation = true; } - kvm_vgic_global_state.flags = gic_kvm_info->flags; switch (gic_kvm_info->type) { case GIC_V2: ret = vgic_v2_probe(gic_kvm_info); diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c index c29c0b5669a6..d787de1e2c1c 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -83,10 +83,6 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, if (vgic_has_its(vcpu->kvm)) { value |= (INTERRUPT_ID_BITS_ITS - 1) << 19; value |= GICD_TYPER_LPIS; - /* Limit the number of vlpis to 4096 */ - if (kvm_vgic_global_state.flags & FLAGS_WORKAROUND_HIP09_ERRATUM_162200803) - value |= 11 << GICD_TYPER_NUM_LPIS_SHIFT; - } else { value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19; } diff --git a/arch/arm64/kvm/vgic/vgic-mmio.h b/arch/arm64/kvm/vgic/vgic-mmio.h index 55f49933e304..5b490a4dfa5e 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio.h +++ b/arch/arm64/kvm/vgic/vgic-mmio.h @@ -5,8 +5,6 @@ #ifndef __KVM_ARM_VGIC_MMIO_H__ #define __KVM_ARM_VGIC_MMIO_H__ -#define FLAGS_WORKAROUND_HIP09_ERRATUM_162200803 (1ULL << 4) - struct vgic_register_region { unsigned int reg_offset; unsigned int len; diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 34405577c458..f8f2dd7264bb 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -41,7 +41,6 @@ #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) #define FLAGS_WORKAROUND_MTK_GICR_SAVE (1ULL << 2) #define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 3) -#define FLAGS_WORKAROUND_HIP09_ERRATUM_162200803 (1ULL << 4) #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) @@ -1992,15 +1991,6 @@ static bool rd_set_non_coherent(void *data) return true; } -static bool gic_enable_quirk_hip09_162200803(void *data) -{ - struct gic_chip_data *d = data; - - d->flags |= FLAGS_WORKAROUND_HIP09_ERRATUM_162200803; - - return true; -} - static const struct gic_quirk gic_quirks[] = { { .desc = "GICv3: Qualcomm MSM8996 broken firmware", @@ -2072,12 +2062,6 @@ static const struct gic_quirk gic_quirks[] = { .property = "dma-noncoherent", .init = rd_set_non_coherent, }, - { - .desc = "GICv3: HIP09 erratum 162200803", - .iidr = 0x01050736, - .mask = 0xffffffff, - .init = gic_enable_quirk_hip09_162200803, - }, { } }; @@ -2389,8 +2373,6 @@ static void __init gic_of_setup_kvm_info(struct device_node *node) #ifdef CONFIG_VIRT_VTIMER_IRQ_BYPASS gic_v3_kvm_info.has_vtimer = gic_data.rdists.has_vtimer; #endif - if (gic_v3_kvm_info.has_v4) - gic_v3_kvm_info.flags = gic_data.flags; vgic_set_kvm_info(&gic_v3_kvm_info); } @@ -2743,8 +2725,6 @@ static void __init gic_acpi_setup_kvm_info(void) #ifdef CONFIG_VIRT_VTIMER_IRQ_BYPASS gic_v3_kvm_info.has_vtimer = gic_data.rdists.has_vtimer; #endif - if (gic_v3_kvm_info.has_v4) - gic_v3_kvm_info.flags = gic_data.flags; vgic_set_kvm_info(&gic_v3_kvm_info); } diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 0b734d6f3d21..0cbcf4e06761 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -126,7 +126,6 @@ struct vgic_global { struct static_key_false gicv3_cpuif; u32 ich_vtr_el2; - u64 flags; }; extern struct vgic_global kvm_vgic_global_state; diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index ccf464326be7..7a91ec9e2afd 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -81,8 +81,6 @@ #define GICD_CTLR_ENABLE_SS_G1 (1U << 1) #define GICD_CTLR_ENABLE_SS_G0 (1U << 0) -#define GICD_TYPER_NUM_LPIS_SHIFT 11 - #define GICD_TYPER_RSS (1U << 26) #define GICD_TYPER_LPIS (1U << 17) #define GICD_TYPER_MBIS (1U << 16) diff --git a/include/linux/irqchip/arm-vgic-info.h b/include/linux/irqchip/arm-vgic-info.h index eb358cea426d..aa2e9eaa9ad9 100644 --- a/include/linux/irqchip/arm-vgic-info.h +++ b/include/linux/irqchip/arm-vgic-info.h @@ -38,7 +38,6 @@ struct gic_kvm_info { /* vtimer irqbypass support */ bool has_vtimer; #endif - u64 flags; /* Deactivation impared, subpar stuff */ bool no_hw_deactivation; }; -- 2.33.0
driver inclusion category: other bugzilla: https://gitee.com/openeuler/kernel/issues/I9KBKD ------------------------------------------------------------------ For gicv4.0 of hip10, it has a soc bug with vPE schedule: when multiple vPEs are sending vpe schedule/deschedule commands concurrently and repeatly, some vPE schedule command may not be scheduled, and it will cause the command timeout. To avoid the issue, limit the number of vLPI to 4096 for virtual machine. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: caijian <caijian11@h-partners.com> --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/kvm/vgic/vgic-init.c | 1 + arch/arm64/kvm/vgic/vgic-mmio-v3.c | 4 ++++ arch/arm64/kvm/vgic/vgic-mmio.h | 2 ++ drivers/irqchip/irq-gic-v3.c | 26 +++++++++++++++++++++ include/kvm/arm_vgic.h | 1 + include/linux/irqchip/arm-gic-v3.h | 2 ++ include/linux/irqchip/arm-vgic-info.h | 1 + 8 files changed, 39 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index 5230538cedfe..af8be06f11df 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -213,6 +213,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | SMMUv3 | #162100602 | HISILICON_ERRATUM_162100602 | +----------------+-----------------+-----------------+-----------------------------+ +| Hisilicon | Hip{10,10C} | #162200803 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | +----------------+-----------------+-----------------+-----------------------------+ | Qualcomm Tech. | Kryo/Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c index 60f860a1dcaa..db5db9402c3a 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -615,6 +615,7 @@ int kvm_vgic_hyp_init(void) kvm_vgic_global_state.no_hw_deactivation = true; } + kvm_vgic_global_state.flags = gic_kvm_info->flags; switch (gic_kvm_info->type) { case GIC_V2: ret = vgic_v2_probe(gic_kvm_info); diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c index d787de1e2c1c..909584cd21c7 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -83,6 +83,10 @@ static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu, if (vgic_has_its(vcpu->kvm)) { value |= (INTERRUPT_ID_BITS_ITS - 1) << 19; value |= GICD_TYPER_LPIS; + /* Limit the number of vlpis to 4096 */ + if (kvm_vgic_global_state.flags & FLAGS_WORKAROUND_HIP10_ERRATUM_162200803) + value |= 11 << GICD_TYPER_NUM_LPIS_SHIFT; + } else { value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19; } diff --git a/arch/arm64/kvm/vgic/vgic-mmio.h b/arch/arm64/kvm/vgic/vgic-mmio.h index 5b490a4dfa5e..47372c2ceb8d 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio.h +++ b/arch/arm64/kvm/vgic/vgic-mmio.h @@ -5,6 +5,8 @@ #ifndef __KVM_ARM_VGIC_MMIO_H__ #define __KVM_ARM_VGIC_MMIO_H__ +#define FLAGS_WORKAROUND_HIP10_ERRATUM_162200803 (1ULL << 4) + struct vgic_register_region { unsigned int reg_offset; unsigned int len; diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index f8f2dd7264bb..dba80bfc23f0 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -41,6 +41,7 @@ #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) #define FLAGS_WORKAROUND_MTK_GICR_SAVE (1ULL << 2) #define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 3) +#define FLAGS_WORKAROUND_HIP10_ERRATUM_162200803 (1ULL << 4) #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) @@ -1991,6 +1992,15 @@ static bool rd_set_non_coherent(void *data) return true; } +static bool gic_enable_quirk_hip10_10C_162200803(void *data) +{ + struct gic_chip_data *d = data; + + d->flags |= FLAGS_WORKAROUND_HIP10_ERRATUM_162200803; + + return true; +} + static const struct gic_quirk gic_quirks[] = { { .desc = "GICv3: Qualcomm MSM8996 broken firmware", @@ -2062,6 +2072,18 @@ static const struct gic_quirk gic_quirks[] = { .property = "dma-noncoherent", .init = rd_set_non_coherent, }, + { + .desc = "GICv3: HIP10 erratum 162200803", + .iidr = 0x01050736, + .mask = 0xffffffff, + .init = gic_enable_quirk_hip10_10C_162200803, + }, + { + .desc = "GICv3: HIP10C erratum 162200803", + .iidr = 0x00061736, + .mask = 0xffffffff, + .init = gic_enable_quirk_hip10_10C_162200803, + }, { } }; @@ -2373,6 +2395,8 @@ static void __init gic_of_setup_kvm_info(struct device_node *node) #ifdef CONFIG_VIRT_VTIMER_IRQ_BYPASS gic_v3_kvm_info.has_vtimer = gic_data.rdists.has_vtimer; #endif + if (gic_v3_kvm_info.has_v4 && !gic_v3_kvm_info.has_v4_1) + gic_v3_kvm_info.flags = gic_data.flags; vgic_set_kvm_info(&gic_v3_kvm_info); } @@ -2725,6 +2749,8 @@ static void __init gic_acpi_setup_kvm_info(void) #ifdef CONFIG_VIRT_VTIMER_IRQ_BYPASS gic_v3_kvm_info.has_vtimer = gic_data.rdists.has_vtimer; #endif + if (gic_v3_kvm_info.has_v4 && !gic_v3_kvm_info.has_v4_1) + gic_v3_kvm_info.flags = gic_data.flags; vgic_set_kvm_info(&gic_v3_kvm_info); } diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 0cbcf4e06761..0b734d6f3d21 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -126,6 +126,7 @@ struct vgic_global { struct static_key_false gicv3_cpuif; u32 ich_vtr_el2; + u64 flags; }; extern struct vgic_global kvm_vgic_global_state; diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 7a91ec9e2afd..ccf464326be7 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -81,6 +81,8 @@ #define GICD_CTLR_ENABLE_SS_G1 (1U << 1) #define GICD_CTLR_ENABLE_SS_G0 (1U << 0) +#define GICD_TYPER_NUM_LPIS_SHIFT 11 + #define GICD_TYPER_RSS (1U << 26) #define GICD_TYPER_LPIS (1U << 17) #define GICD_TYPER_MBIS (1U << 16) diff --git a/include/linux/irqchip/arm-vgic-info.h b/include/linux/irqchip/arm-vgic-info.h index aa2e9eaa9ad9..eb358cea426d 100644 --- a/include/linux/irqchip/arm-vgic-info.h +++ b/include/linux/irqchip/arm-vgic-info.h @@ -38,6 +38,7 @@ struct gic_kvm_info { /* vtimer irqbypass support */ bool has_vtimer; #endif + u64 flags; /* Deactivation impared, subpar stuff */ bool no_hw_deactivation; }; -- 2.33.0
From: Kunkun Jiang <jiangkunkun@huawei.com> driver inclusion category: other bugzilla: https://gitee.com/openeuler/kernel/issues/I9KBKD ------------------------------------------------------------------ For GICv4.1 of HIP10, it has a soc bug that obtaining vSGI pending status through hardware is inaccurate. Get vSGI pending status by accessing Virtual LPI Pending Table to avoid this problem. This solution is based on the premise that vPE is no resident. During VM live migration, vCPUs are blocked in the userspace. In this case, the vPE is no resident. Therefore, the condition is met. Currently, only VM live migration will obtain the vSGI pending status. In the code implementation, midr is used instead of erratum for simplicity and practicality. Capabilities such as obtaining the vSGI pending status in the guest will be supported later. Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com> Signed-off-by: caijian <caijian11@h-partners.com> --- arch/arm64/kvm/vgic/vgic-mmio.c | 36 ++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-mmio.c b/arch/arm64/kvm/vgic/vgic-mmio.c index 59b81e5ce1d8..dcd7388aa244 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio.c +++ b/arch/arm64/kvm/vgic/vgic-mmio.c @@ -228,11 +228,31 @@ int vgic_uaccess_write_cenable(struct kvm_vcpu *vcpu, return 0; } +#define HIP10_MIDR 0x480fd030 +#define VIRTUAL_SGI_PENDING_OFFSET 0x3F0 +static bool hip10_erratum_162200806_workaround(struct kvm_vcpu *vcpu, + struct vgic_irq *irq) +{ + struct its_vpe *vpe; + void *va; + u8 *ptr; + int mask; + + vpe = &vcpu->arch.vgic_cpu.vgic_v3.its_vpe; + WARN_ON(vpe->resident); + mask = BIT(irq->intid % BITS_PER_BYTE); + va = page_address(vpe->vpt_page); + ptr = va + VIRTUAL_SGI_PENDING_OFFSET + + irq->intid / BITS_PER_BYTE; + return *ptr & mask; +} + static unsigned long __read_pending(struct kvm_vcpu *vcpu, gpa_t addr, unsigned int len, bool is_user) { u32 intid = VGIC_ADDR_TO_INTID(addr, 1); + u32 midr = read_cpuid_id(); u32 value = 0; int i; @@ -252,14 +272,20 @@ static unsigned long __read_pending(struct kvm_vcpu *vcpu, * for handling of ISPENDR and ICPENDR. */ raw_spin_lock_irqsave(&irq->irq_lock, flags); + /* direct ppi has not been commercial used */ if (vgic_direct_sgi_or_ppi(irq)) { - int err; - - val = false; - err = irq_get_irqchip_state(irq->host_irq, + if (midr == HIP10_MIDR) { + val = hip10_erratum_162200806_workaround(vcpu, + irq); + } else { + int err; + + val = false; + err = irq_get_irqchip_state(irq->host_irq, IRQCHIP_STATE_PENDING, &val); - WARN_RATELIMIT(err, "IRQ %d", irq->host_irq); + WARN_RATELIMIT(err, "IRQ %d", irq->host_irq); + } } else if (!is_user && vgic_irq_is_mapped_level(irq)) { val = vgic_get_phys_line_level(irq); } else { -- 2.33.0
From: Kunkun Jiang <jiangkunkun@huawei.com> virt inclusion category: other bugzilla: https://gitee.com/openeuler/kernel/issues/I9SGLA ------------------------------------------------------------- In allocate_vpe_l1_table, when we fail to inherit VPE table from other redistributors or ITSs, and we allocate a new vpe table for current common affinity field without checking whether indirect table is supported. Let's fix it. Signed-off-by: Nianyao Tang <tangnianyao@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com> Signed-off-by: caijian <caijian11@h-partners.com> --- drivers/irqchip/irq-gic-v3-its.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e4d148dde2b3..b6ba3d03a6fd 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -3189,6 +3189,7 @@ static int allocate_vpe_l1_table(void) unsigned int psz = SZ_64K; unsigned int np, epp, esz; struct page *page; + bool indirect; if (!gic_rdists->has_rvpeid) return 0; @@ -3223,10 +3224,12 @@ static int allocate_vpe_l1_table(void) /* First probe the page size */ val = FIELD_PREP(GICR_VPROPBASER_4_1_PAGE_SIZE, GIC_PAGE_SIZE_64K); + val |= GICR_VPROPBASER_4_1_INDIRECT; gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); val = gicr_read_vpropbaser(vlpi_base + GICR_VPROPBASER); gpsz = FIELD_GET(GICR_VPROPBASER_4_1_PAGE_SIZE, val); esz = FIELD_GET(GICR_VPROPBASER_4_1_ENTRY_SIZE, val); + indirect = !!(val & GICR_VPROPBASER_4_1_INDIRECT); switch (gpsz) { default: @@ -3259,7 +3262,7 @@ static int allocate_vpe_l1_table(void) * If we need more than just a single L1 page, flag the table * as indirect and compute the number of required L1 pages. */ - if (epp < ITS_MAX_VPEID) { + if (epp < ITS_MAX_VPEID && indirect) { int nl2; val |= GICR_VPROPBASER_4_1_INDIRECT; @@ -3270,7 +3273,8 @@ static int allocate_vpe_l1_table(void) /* Number of L1 pages to point to the L2 pages */ npg = DIV_ROUND_UP(nl2 * SZ_8, psz); } else { - npg = 1; + npg = DIV_ROUND_UP(ITS_MAX_VPEID, epp); + npg = clamp_val(npg, 1, (GICR_VPROPBASER_4_1_SIZE + 1)); } val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1); -- 2.33.0
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