hulk inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/ICX9YF -------------------------------- The bit mask width indicated in the MPAMF_CPOR_IDR_CPBM_WD IDR register of MPAM is inconsistent with the actual hardware capability. This incorrectly limits the L3 capacity in real use. Therefore, software has to hard-code a workaround to align with the actual CPBM bit width. Fixes: 051d021d1c1a ("arm_mpam: Probe the hardware features resctrl supports") Signed-off-by: Zeng Heng <zengheng4@huawei.com> --- drivers/platform/mpam/mpam_devices.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/platform/mpam/mpam_devices.c b/drivers/platform/mpam/mpam_devices.c index 297531294acf..686dffc084ef 100644 --- a/drivers/platform/mpam/mpam_devices.c +++ b/drivers/platform/mpam/mpam_devices.c @@ -566,6 +566,17 @@ static struct mpam_msc_ris *mpam_get_or_create_ris(struct mpam_msc *msc, return found; } +static void mpam_cpbm_wd_hisi_workaround(struct mpam_props *props) +{ + static const struct midr_range cpus[] = { + MIDR_ALL_VERSIONS(MIDR_HISI_HIP12), + { /* sentinel */ } + }; + + if (is_midr_in_range_list(read_cpuid_id(), cpus)) + props->cpbm_wd = 21; +} + static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) { int err; @@ -596,6 +607,7 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris) u32 cpor_features = mpam_read_partsel_reg(msc, CPOR_IDR); props->cpbm_wd = FIELD_GET(MPAMF_CPOR_IDR_CPBM_WD, cpor_features); + mpam_cpbm_wd_hisi_workaround(props); if (props->cpbm_wd) mpam_set_feature(mpam_feat_cpor_part, props); } -- 2.25.1