driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8LYGD CVE: NA -------------------------------- When the UC enable the power saving mode, the UC power management system will turn off the counters register clock if the PMU is not enabled, and we cannot write values to the counters register. Set the UC PMU enable to turn on the clock, and then restore the UC PMU configuration. Signed-off-by: Junhao He <hejunhao3@huawei.com> --- drivers/perf/hisilicon/hisi_uncore_uc_pmu.c | 28 +++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c b/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c index 636fb79647c8..80811c5d8eab 100644 --- a/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_uc_pmu.c @@ -287,10 +287,38 @@ static u64 hisi_uc_pmu_read_counter(struct hisi_pmu *uc_pmu, return readq(uc_pmu->base + HISI_UC_CNTR_REGn(hwc->idx)); } +static bool hisi_uc_pmu_get_glb_en_state(struct hisi_pmu *uc_pmu) +{ + u32 val; + + val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG); + return !!FIELD_GET(HISI_UC_EVENT_GLB_EN, val); +} + static void hisi_uc_pmu_write_counter(struct hisi_pmu *uc_pmu, struct hw_perf_event *hwc, u64 val) { + bool enable = hisi_uc_pmu_get_glb_en_state(uc_pmu); + + /* + * If the PMU is not enabled, the UC power management system will + * turn off the clock of the counters register and we cannot write + * values to the counters register. Set the UC PMU enable to turn + * on the clock. + */ + if (!enable) + hisi_uc_pmu_start_counters(uc_pmu); + writeq(val, uc_pmu->base + HISI_UC_CNTR_REGn(hwc->idx)); + + /* + * Restore the UC PMU configuration. The Perf schedule will enable PMU + * at appropriate time. + * The irq handler will also call the function to set period. At this + * time, PMU is still enabled and we cannot directly disable the PMU. + */ + if (!enable) + hisi_uc_pmu_stop_counters(uc_pmu); } static void hisi_uc_pmu_enable_counter_int(struct hisi_pmu *uc_pmu, -- 2.33.0