driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I9DOVK CVE: NA --------------------------------------------------------------------------- The sata disk will be locked after the disk sends the DMA Setup frame until all data frame transmission is completed. The CFG_ICT_TIMER_STEP_TRSH register is used for sata disk to configure the step size of the timer which records the time when the disk is locked. The unit is 1us and the default step size is 150ms. If the disk is locked for more than 7 timer steps, the io to be sent to the disk will end abnormally. The current timeout is only about 1 second, it is easy to trigger IO abnormal end when the SATA hard disk returns data slowly. Adjust the timeout to 7 seconds based on ERC time of most disks. Fixes: 510ebd8eb2fe ("scsi: hisi_sas: Change DMA setup lock timeout to 2.5s") Signed-off-by: Xingui Yang <yangxingui@huawei.com> Reviewed-by: Xiang Chen <chenxiang66@hisilicon.com> Reviewed-by: kang fenglong <kangfenglong@huawei.com> --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 79010d02a..35076b9ce 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -48,6 +48,7 @@ #define CQ_INT_CONVERGE_EN 0xb0 #define CFG_AGING_TIME 0xbc #define HGC_DFX_CFG2 0xc0 +#define CFG_ICT_TIMER_STEP_TRSH 0xc8 #define CFG_1US_TIMER_TRSH 0xcc #define CFG_ABT_SET_QUERY_IPTT 0xd4 #define CFG_SET_ABORTED_IPTT_OFF 0 @@ -615,6 +616,7 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) hisi_sas_write32(hisi_hba, TRANS_LOCK_ICT_TIME, 0x4A817C80); hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); + hisi_sas_write32(hisi_hba, CFG_ICT_TIMER_STEP_TRSH, 0xf4240); hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); -- 2.17.1