From: Xiongfeng Wang <xiongfeng.wang@linaro.org> euler inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8XWBL CVE: NA ---------------------------------------- This patch add check for the offset of MSI-X Table. If it is out of range of the BAR space BIR selects, we just fail this MSI-X mapping. Signed-off-by: Xiongfeng Wang <xiongfeng.wang@linaro.org> Reviewed-by: Hanjun Guo <guohanjun@huawei.com> Signed-off-by: Jialin Zhang <zhangjialin11@huawei.com> Conflicts: drivers/pci/msi.c Signed-off-by: Xiongfeng Wang <xiongfeng.wang@linaro.org> --- drivers/pci/msi/msi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 21355bfe58a3..130bf74de69b 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -569,6 +569,12 @@ static void __iomem *msix_map_region(struct pci_dev *dev, return NULL; table_offset &= PCI_MSIX_TABLE_OFFSET; + if (table_offset >= pci_resource_len(dev, bir)) { + dev_err(&dev->dev, + "MSI-X Table offset is out of range of BAR:%d!\n", + bir); + return NULL; + } phys_addr = pci_resource_start(dev, bir) + table_offset; return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE); -- 2.20.1