[PATCH openEuler-1.0-LTS 1/3] drivers : remove drivers/soc/hisilicon/lbc
From: fengsheng <fengsheng5@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4IYWE?from=project-issue CVE: NA ------------------------------------------------------------ This driver is not in use. Remove it. Signed-off-by: fengsheng <fengsheng5@huawei.com> Reviewed-by: lidongming <lidongming5@huawei.com> Reviewed-by: ouyang delong <ouyangdelong@huawei.com> Acked-by: Xie XiuQi <xiexiuqi@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> --- MAINTAINERS | 5 - arch/arm64/configs/hulk_defconfig | 1 - arch/arm64/configs/openeuler_defconfig | 1 - arch/arm64/configs/storage_ci_defconfig | 1 - arch/arm64/configs/syzkaller_defconfig | 1 - arch/x86/configs/openeuler_defconfig | 1 - arch/x86/configs/storage_ci_defconfig | 1 - drivers/soc/hisilicon/Kconfig | 1 - drivers/soc/hisilicon/Makefile | 1 - drivers/soc/hisilicon/lbc/Kconfig | 3 - drivers/soc/hisilicon/lbc/Makefile | 2 - drivers/soc/hisilicon/lbc/hs_lbc_pltfm.c | 466 ----------------------- drivers/soc/hisilicon/lbc/hs_lbc_pltfm.h | 120 ------ 13 files changed, 604 deletions(-) delete mode 100644 drivers/soc/hisilicon/lbc/Kconfig delete mode 100644 drivers/soc/hisilicon/lbc/Makefile delete mode 100644 drivers/soc/hisilicon/lbc/hs_lbc_pltfm.c delete mode 100644 drivers/soc/hisilicon/lbc/hs_lbc_pltfm.h diff --git a/MAINTAINERS b/MAINTAINERS index 15609985b6cc6..b84c7cbd4e555 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16332,11 +16332,6 @@ S: Buried alive in reporters F: * F: */ -HISILICON LOCALBUS DRIVER -M: Feng Sheng <fengsheng5@huawei.com> -S: Maintained -F: drivers/soc/hisilicon/lbc/ - HISILICON SYSCTRL DRIVER M: Feng Sheng <fengsheng5@huawei.com> S: Maintained diff --git a/arch/arm64/configs/hulk_defconfig b/arch/arm64/configs/hulk_defconfig index a2a2216e43f1e..904e9b557122e 100644 --- a/arch/arm64/configs/hulk_defconfig +++ b/arch/arm64/configs/hulk_defconfig @@ -281,7 +281,6 @@ CONFIG_ARCH_XGENE=y # CONFIG_ARCH_ZYNQMP is not set CONFIG_HAVE_LIVEPATCH_WO_FTRACE=y CONFIG_SOC_HISILICON_SYSCTL=m -CONFIG_SOC_HISILICON_LBC=m # # Enable Livepatch diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 089f5be748b10..20ad626791d14 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -5011,7 +5011,6 @@ CONFIG_ARM_SMMU_V3=y # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set -CONFIG_SOC_HISILICON_LBC=m CONFIG_SOC_HISILICON_SYSCTL=m # CONFIG_PM_DEVFREQ is not set CONFIG_EXTCON=y diff --git a/arch/arm64/configs/storage_ci_defconfig b/arch/arm64/configs/storage_ci_defconfig index f468538f22a52..6d671761fd080 100644 --- a/arch/arm64/configs/storage_ci_defconfig +++ b/arch/arm64/configs/storage_ci_defconfig @@ -2219,7 +2219,6 @@ CONFIG_CLKSRC_VERSATILE=y # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set -CONFIG_SOC_HISILICON_LBC=m # CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set # CONFIG_MEMORY is not set diff --git a/arch/arm64/configs/syzkaller_defconfig b/arch/arm64/configs/syzkaller_defconfig index eb045bdc5ef16..7c8eca466e25a 100644 --- a/arch/arm64/configs/syzkaller_defconfig +++ b/arch/arm64/configs/syzkaller_defconfig @@ -281,7 +281,6 @@ CONFIG_ARCH_XGENE=y # CONFIG_ARCH_ZYNQMP is not set CONFIG_HAVE_LIVEPATCH_WO_FTRACE=y CONFIG_SOC_HISILICON_SYSCTL=m -CONFIG_SOC_HISILICON_LBC=m # # Enable Livepatch # diff --git a/arch/x86/configs/openeuler_defconfig b/arch/x86/configs/openeuler_defconfig index 5a56a81e39e19..0700ef6fc0cf0 100644 --- a/arch/x86/configs/openeuler_defconfig +++ b/arch/x86/configs/openeuler_defconfig @@ -6168,7 +6168,6 @@ CONFIG_IRQ_REMAP=y # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set -CONFIG_SOC_HISILICON_LBC=m CONFIG_SOC_HISILICON_SYSCTL=m # CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set diff --git a/arch/x86/configs/storage_ci_defconfig b/arch/x86/configs/storage_ci_defconfig index 0847b17d293a0..27de222f67966 100644 --- a/arch/x86/configs/storage_ci_defconfig +++ b/arch/x86/configs/storage_ci_defconfig @@ -2389,7 +2389,6 @@ CONFIG_PCC=y # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set -CONFIG_SOC_HISILICON_LBC=m CONFIG_SOC_HISILICON_SYSCTL=m # CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set diff --git a/drivers/soc/hisilicon/Kconfig b/drivers/soc/hisilicon/Kconfig index 520f60cec77b7..6dd657e3eaa98 100644 --- a/drivers/soc/hisilicon/Kconfig +++ b/drivers/soc/hisilicon/Kconfig @@ -1,3 +1,2 @@ -source "drivers/soc/hisilicon/lbc/Kconfig" source "drivers/soc/hisilicon/sysctl/Kconfig" diff --git a/drivers/soc/hisilicon/Makefile b/drivers/soc/hisilicon/Makefile index 33a64532ace35..fe68ce0d54c3e 100644 --- a/drivers/soc/hisilicon/Makefile +++ b/drivers/soc/hisilicon/Makefile @@ -1,2 +1 @@ -obj-y += lbc/ obj-y += sysctl/ diff --git a/drivers/soc/hisilicon/lbc/Kconfig b/drivers/soc/hisilicon/lbc/Kconfig deleted file mode 100644 index 054b6634dae9a..0000000000000 --- a/drivers/soc/hisilicon/lbc/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config SOC_HISILICON_LBC - tristate - default m \ No newline at end of file diff --git a/drivers/soc/hisilicon/lbc/Makefile b/drivers/soc/hisilicon/lbc/Makefile deleted file mode 100644 index d7ec052cb42e2..0000000000000 --- a/drivers/soc/hisilicon/lbc/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -lbc-objs := hs_lbc_pltfm.o -obj-$(CONFIG_SOC_HISILICON_LBC) += lbc.o \ No newline at end of file diff --git a/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.c b/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.c deleted file mode 100644 index c188cd308f862..0000000000000 --- a/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.c +++ /dev/null @@ -1,466 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/errno.h> -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/platform_device.h> -#include <linux/of.h> -#include <linux/of_platform.h> -#include <linux/spinlock.h> -#include <linux/of_address.h> -#include <linux/acpi.h> - -#include "hs_lbc_pltfm.h" - -#define LBC_DRIVER_VERSION "1.9.39.0" - -struct hisi_lbc_dev g_lbc_dev = {0}; - -static void lbc_set_cs_base_addr(unsigned int index, unsigned int cs_base_addr) -{ - LBC_REG_REGION *lbc_reg = (LBC_REG_REGION *)(ACCESS_ONCE(g_lbc_dev.regs_base)); - - lbc_reg->cs_base[index] = cs_base_addr; -} - -static void lbc_set_cs_data_width(unsigned int index, unsigned int width) -{ - LBC_REG_REGION *lbc_reg = (LBC_REG_REGION *)(ACCESS_ONCE(g_lbc_dev.regs_base)); - - lbc_reg->cs_ctrl[index].data_width = width; -} - -static void lbc_set_cs_data_offset(unsigned int index, unsigned int offset) -{ - LBC_REG_REGION *lbc_reg = (LBC_REG_REGION *)(ACCESS_ONCE(g_lbc_dev.regs_base)); - - lbc_reg->cs_ctrl[index].addr_offset = offset; -} - -static void lbc_set_cs_mem_size(unsigned int index, u64 mem_size) -{ - unsigned int size = 0; - LBC_REG_REGION *lbc_reg = (LBC_REG_REGION *)(ACCESS_ONCE(g_lbc_dev.regs_base)); - - switch (mem_size) { - case LBC_CS_MEM_SIZE_0: - size = LBC_CS_MEM_SIZE_REG_0; - break; - case LBC_CS_MEM_SIZE_64K: - size = LBC_CS_MEM_SIZE_REG_64K; - break; - case LBC_CS_MEM_SIZE_128K: - size = LBC_CS_MEM_SIZE_REG_128K; - break; - case LBC_CS_MEM_SIZE_256K: - size = LBC_CS_MEM_SIZE_REG_256K; - break; - case LBC_CS_MEM_SIZE_512K: - size = LBC_CS_MEM_SIZE_REG_512K; - break; - case LBC_CS_MEM_SIZE_1M: - size = LBC_CS_MEM_SIZE_REG_1M; - break; - case LBC_CS_MEM_SIZE_2M: - size = LBC_CS_MEM_SIZE_REG_2M; - break; - case LBC_CS_MEM_SIZE_4M: - size = LBC_CS_MEM_SIZE_REG_4M; - break; - case LBC_CS_MEM_SIZE_8M: - size = LBC_CS_MEM_SIZE_REG_8M; - break; - case LBC_CS_MEM_SIZE_16M: - size = LBC_CS_MEM_SIZE_REG_16M; - break; - case LBC_CS_MEM_SIZE_32M: - size = LBC_CS_MEM_SIZE_REG_32M; - break; - case LBC_CS_MEM_SIZE_64M: - size = LBC_CS_MEM_SIZE_REG_64M; - break; - case LBC_CS_MEM_SIZE_128M: - size = LBC_CS_MEM_SIZE_REG_128M; - break; - case LBC_CS_MEM_SIZE_256M: - size = LBC_CS_MEM_SIZE_REG_256M; - break; - default: - size = 0; - } - - lbc_reg->cs_ctrl[index].mem_size = size; -} - -static int hisi_lbc_para_check(unsigned int index, unsigned int offset, unsigned int type) -{ - /* cs index check */ - if (index >= LBC_CS_MAX_NUM) - return -EINVAL; - - /* cs offset check */ - if (offset >= g_lbc_dev.cs[index].size) - return -EINVAL; - - if (type != LBC_RWDATA_WIDTH_8 - && type != LBC_RWDATA_WIDTH_16 - && type != LBC_RWDATA_WIDTH_32) - return -EINVAL; - - /* width check */ - if ((type == LBC_RWDATA_WIDTH_16) - || (type == LBC_RWDATA_WIDTH_32)) { - if (offset % (type * 0x2)) - return -EINVAL; - } - - return 0; -} - -static unsigned int lbc_read(unsigned int index, unsigned int offset, unsigned int type) -{ - void __iomem *base_addr = ACCESS_ONCE(g_lbc_dev.cs[index].cs_base); - unsigned int value; - unsigned long flags; - - spin_lock_irqsave(&g_lbc_dev.cs[index].lock, flags); - - if (type == LBC_RWDATA_WIDTH_8) - value = readb(base_addr + offset) & 0xff; - else if (type == LBC_RWDATA_WIDTH_16) - value = readw(base_addr + offset) & 0xffff; - else - value = readl(base_addr + offset) & 0xffffffff; - - spin_unlock_irqrestore(&g_lbc_dev.cs[index].lock, flags); - - return value; -} - -static unsigned int lbc_read_unlock(unsigned int index, unsigned int offset, unsigned int type) -{ - void __iomem *base_addr = ACCESS_ONCE(g_lbc_dev.cs[index].cs_base); - unsigned int value; - - if (type == LBC_RWDATA_WIDTH_8) - value = readb(base_addr + offset) & 0xff; - else if (type == LBC_RWDATA_WIDTH_16) - value = readw(base_addr + offset) & 0xffff; - else - value = readl(base_addr + offset) & 0xffffffff; - - return value; -} - -static int lbc_write(unsigned int index, unsigned int offset, unsigned int type, unsigned int data) -{ - void __iomem *base_addr = ACCESS_ONCE(g_lbc_dev.cs[index].cs_base); - unsigned long flags; - - spin_lock_irqsave(&g_lbc_dev.cs[index].lock, flags); - - if (type == LBC_RWDATA_WIDTH_8) - writeb(data & 0xff, base_addr + offset); - else if (type == LBC_RWDATA_WIDTH_16) - writew(data & 0xffff, base_addr + offset); - else - writel(data & 0xffffffff, base_addr + offset); - - spin_unlock_irqrestore(&g_lbc_dev.cs[index].lock, flags); - - return 0; -} - -static int lbc_write_unlock(unsigned int index, unsigned int offset, unsigned int type, unsigned int data) -{ - void __iomem *base_addr = ACCESS_ONCE(g_lbc_dev.cs[index].cs_base); - - if (type == LBC_RWDATA_WIDTH_8) - writeb(data & 0xff, base_addr + offset); - else if (type == LBC_RWDATA_WIDTH_16) - writew(data & 0xffff, base_addr + offset); - else - writel(data & 0xffffffff, base_addr + offset); - - return 0; -} - -int lbc_read8(unsigned int index, unsigned int offset, unsigned char *value) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_8)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - if (!value) { - pr_err("value is null\n"); - return -EINVAL; - } - - *value = (unsigned char)lbc_read(index, offset, LBC_RWDATA_WIDTH_8); - - return 0; -} -EXPORT_SYMBOL(lbc_read8); - -int lbc_read8_nolock(unsigned int index, unsigned int offset, unsigned char *value) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_8)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - if (!value) { - pr_err("value is null\n"); - return -EINVAL; - } - - *value = (unsigned char)lbc_read_unlock(index, offset, LBC_RWDATA_WIDTH_8); - return 0; -} -EXPORT_SYMBOL(lbc_read8_nolock); - -unsigned short lbc_read16(unsigned int index, unsigned int offset) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_16)) { - pr_err("Lbc para check failed\n"); - return 0; - } - - return (unsigned short)lbc_read(index, offset, LBC_RWDATA_WIDTH_16); -} - -unsigned int lbc_read32(unsigned int index, unsigned int offset) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_32)) { - pr_err("Lbc para check failed\n"); - return 0; - } - - return lbc_read(index, offset, LBC_RWDATA_WIDTH_32); -} - -int lbc_write8(unsigned int index, unsigned int offset, unsigned char data) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_8)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - return lbc_write(index, offset, LBC_RWDATA_WIDTH_8, (unsigned int)data); -} -EXPORT_SYMBOL(lbc_write8); - -int lbc_write8_nolock(unsigned int index, unsigned int offset, unsigned char data) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_8)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - return lbc_write_unlock(index, offset, LBC_RWDATA_WIDTH_8, (unsigned int)data); -} -EXPORT_SYMBOL(lbc_write8_nolock); - -int lbc_write16(unsigned int index, unsigned int offset, unsigned short data) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_16)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - return lbc_write(index, offset, LBC_RWDATA_WIDTH_16, (unsigned int)data); -} - -int lbc_write32(unsigned int index, unsigned int offset, unsigned int data) -{ - /* para check */ - if (hisi_lbc_para_check(index, offset, LBC_RWDATA_WIDTH_32)) { - pr_err("Lbc para check failed\n"); - return -EINVAL; - } - - return lbc_write(index, offset, LBC_RWDATA_WIDTH_32, (unsigned int)data); -} - -static int hisi_lbc_cs_init(struct platform_device *pdev) -{ - unsigned int index; - unsigned int width; - unsigned int shift; - struct resource *cs_base = NULL; - - if (has_acpi_companion(g_lbc_dev.dev)) { - /* get cs index */ - index = 0; - (void)device_property_read_u32(g_lbc_dev.dev, "index", &index); - - if (index >= LBC_CS_MAX_NUM) { - dev_err(g_lbc_dev.dev, "Cs index error\n"); - return -EINVAL; - } - - /* lock init */ - spin_lock_init(&g_lbc_dev.cs[index].lock); - - /* get cs base address */ - cs_base = platform_get_resource(pdev, IORESOURCE_MEM, 1); - - if (!cs_base) { - dev_err(g_lbc_dev.dev, "Can not find this cs base resource\n"); - return -ENOENT; - } - - g_lbc_dev.cs[index].cs_base = devm_ioremap_resource(&pdev->dev, cs_base); - - if (IS_ERR(g_lbc_dev.cs[index].cs_base)) - return (int)PTR_ERR(g_lbc_dev.cs[index].cs_base); - - g_lbc_dev.cs[index].size = (unsigned int)resource_size(cs_base); - - lbc_set_cs_base_addr(index, (unsigned int)cs_base->start); - lbc_set_cs_mem_size(index, resource_size(cs_base)); - - /* get cs width */ - width = 0; - (void)device_property_read_u32(g_lbc_dev.dev, "width", &width); - - if (width > LBC_CS_WIDTH_32) { - dev_err(g_lbc_dev.dev, "Cs width error\n"); - return -EINVAL; - } - - g_lbc_dev.cs[index].width = width; - lbc_set_cs_data_width(index, width); - - /* get cs address offset */ - shift = 0; - (void)device_property_read_u32(g_lbc_dev.dev, "shift", &shift); - - if (shift > LBC_CS_ADDR_SHIFT_2) { - dev_err(g_lbc_dev.dev, "Cs address shift error\n"); - return -EINVAL; - } - - g_lbc_dev.cs[index].shift = shift; - - lbc_set_cs_data_offset(index, shift); - } - - return 0; -} - -static int hisi_lbc_probe(struct platform_device *pdev) -{ - int ret; - struct resource *regs_base = NULL; - - dev_info(&pdev->dev, "hisi lbc probe\n"); - - if ((!pdev->dev.of_node) && (!ACPI_COMPANION(&pdev->dev))) { - dev_err(&pdev->dev, "Device OF-Node and ACPI-Node is NULL\n"); - return -EFAULT; - } - - g_lbc_dev.dev = &pdev->dev; - - /* get resource num */ - regs_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - if (!g_lbc_dev.is_reg_remaped) { - g_lbc_dev.regs_base = devm_ioremap_resource(&pdev->dev, regs_base); - g_lbc_dev.is_reg_remaped = 1; - } - - if (IS_ERR(g_lbc_dev.regs_base)) { - dev_err(&pdev->dev, "ERROR: regbase\n"); - return (int)PTR_ERR(g_lbc_dev.regs_base); - } - - /* localbus cs init */ - ret = hisi_lbc_cs_init(pdev); - if (ret) { - dev_err(&pdev->dev, "Localbus cs init failed\n"); - return -1; - } - - platform_set_drvdata(pdev, &g_lbc_dev); - dev_info(&pdev->dev, "hisi lbc probe prob ok\n"); - return 0; -} - -static int hisi_lbc_remove(struct platform_device *pdev) -{ - return 0; -} - -static const struct of_device_id g_hisi_lbc_pltfm_match[] = { - { - .compatible = "hisilicon, hi1620_lbc", - }, - {}, -}; - -#ifdef CONFIG_ACPI -static const struct acpi_device_id g_hisi_lbc_acpi_match[] = { - { "HISI0C01", 0 }, - { } -}; -MODULE_DEVICE_TABLE(acpi, g_hisi_lbc_acpi_match); -#endif - -static struct platform_driver g_hisi_lbc_driver = { - .probe = hisi_lbc_probe, - .remove = hisi_lbc_remove, - .driver = { - .name = "hisi-lbc", - .owner = THIS_MODULE, - .of_match_table = g_hisi_lbc_pltfm_match, -#ifdef CONFIG_ACPI - .acpi_match_table = ACPI_PTR(g_hisi_lbc_acpi_match), -#endif - }, - -}; - -static int __init hisi_lbc_init_driver(void) -{ - return platform_driver_register((struct platform_driver *)&g_hisi_lbc_driver); -} - -static void __exit hisi_lbc_exit_driver(void) -{ - platform_driver_unregister((struct platform_driver *)&g_hisi_lbc_driver); -} - -module_init(hisi_lbc_init_driver); -module_exit(hisi_lbc_exit_driver); - -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR("Huawei Tech. Co., Ltd."); -MODULE_VERSION(LBC_DRIVER_VERSION); -MODULE_DESCRIPTION("LBC driver for linux"); diff --git a/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.h b/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.h deleted file mode 100644 index 24ca4366ec512..0000000000000 --- a/drivers/soc/hisilicon/lbc/hs_lbc_pltfm.h +++ /dev/null @@ -1,120 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _HS_LBC_PLTFM_H_ -#define _HS_LBC_PLTFM_H_ -#include <linux/version.h> - -/* RW data width */ -#define LBC_RWDATA_WIDTH_8 (0) -#define LBC_RWDATA_WIDTH_16 (1) -#define LBC_RWDATA_WIDTH_32 (2) - -/* cs width */ -#define LBC_CS_WIDTH_8 (0) -#define LBC_CS_WIDTH_16 (1) -#define LBC_CS_WIDTH_32 (2) - -/* cs address shift */ -#define LBC_CS_ADDR_SHIFT_0 (0) -#define LBC_CS_ADDR_SHIFT_1 (1) -#define LBC_CS_ADDR_SHIFT_2 (2) - -#define LBC_CS_MAX_NUM (4) - -#define LBC_CS_MEM_SIZE_0 (0) -#define LBC_CS_MEM_SIZE_64K (64 * 1024) -#define LBC_CS_MEM_SIZE_128K (LBC_CS_MEM_SIZE_64K << 1) -#define LBC_CS_MEM_SIZE_256K (LBC_CS_MEM_SIZE_128K << 1) -#define LBC_CS_MEM_SIZE_512K (LBC_CS_MEM_SIZE_256K << 1) -#define LBC_CS_MEM_SIZE_1M (LBC_CS_MEM_SIZE_512K << 1) -#define LBC_CS_MEM_SIZE_2M (LBC_CS_MEM_SIZE_1M << 1) -#define LBC_CS_MEM_SIZE_4M (LBC_CS_MEM_SIZE_2M << 1) -#define LBC_CS_MEM_SIZE_8M (LBC_CS_MEM_SIZE_4M << 1) -#define LBC_CS_MEM_SIZE_16M (LBC_CS_MEM_SIZE_8M << 1) -#define LBC_CS_MEM_SIZE_32M (LBC_CS_MEM_SIZE_16M << 1) -#define LBC_CS_MEM_SIZE_64M (LBC_CS_MEM_SIZE_32M << 1) -#define LBC_CS_MEM_SIZE_128M (LBC_CS_MEM_SIZE_64M << 1) -#define LBC_CS_MEM_SIZE_256M (LBC_CS_MEM_SIZE_128M << 1) - -#define LBC_CS_MEM_SIZE_REG_0 (0) -#define LBC_CS_MEM_SIZE_REG_64K (1) -#define LBC_CS_MEM_SIZE_REG_128K (2) -#define LBC_CS_MEM_SIZE_REG_256K (3) -#define LBC_CS_MEM_SIZE_REG_512K (4) -#define LBC_CS_MEM_SIZE_REG_1M (5) -#define LBC_CS_MEM_SIZE_REG_2M (6) -#define LBC_CS_MEM_SIZE_REG_4M (7) -#define LBC_CS_MEM_SIZE_REG_8M (8) -#define LBC_CS_MEM_SIZE_REG_16M (9) -#define LBC_CS_MEM_SIZE_REG_32M (10) -#define LBC_CS_MEM_SIZE_REG_64M (11) -#define LBC_CS_MEM_SIZE_REG_128M (12) -#define LBC_CS_MEM_SIZE_REG_256M (13) -#define LBC_CS_MEM_SIZE_REG_512M (14) -#define LBC_CS_MEM_SIZE_REG_1G (15) -#define LBC_CS_MEM_SIZE_REG_2G (16) -#define LBC_CS_MEM_SIZE_REG_4G (17) - -typedef struct lbc_cs_ctrl { - volatile unsigned int mem_size : 5; - volatile unsigned int data_width : 2; - volatile unsigned int data_order : 1; - volatile unsigned int byte_order : 1; - volatile unsigned int rdy_mode : 1; - volatile unsigned int rdy_pol : 1; - volatile unsigned int addr_offset : 1; - volatile unsigned int lbctl_en : 1; - volatile unsigned int page_en : 1; - volatile unsigned int page_size : 2; - volatile unsigned int rdy_tout_en : 1; - volatile unsigned int rble : 1; - volatile unsigned int reserved : 14; -} LBC_CS_CTRL; - -#define LBC_REG_RSV_MAX_NUM 4 -#define LBC_REG_CRE_MAX_NUM 4 -typedef struct lbc_reg_region { - volatile unsigned int cs_base[LBC_CS_MAX_NUM]; - volatile unsigned int cs_base_reserved[LBC_REG_RSV_MAX_NUM]; - volatile LBC_CS_CTRL cs_ctrl[LBC_CS_MAX_NUM]; - volatile LBC_CS_CTRL cs_ctrl_creserved[LBC_REG_CRE_MAX_NUM]; -} LBC_REG_REGION; - -struct hisi_lbc_cs { - unsigned int index; - spinlock_t lock; - void __iomem *cs_base; - unsigned int size; - unsigned int width; /* width */ - unsigned int shift; /* address shift */ -}; - -struct hisi_lbc_dev { - unsigned char is_reg_remaped; - struct device *dev; - void __iomem *regs_base; /* localbus regs base addr */ - struct hisi_lbc_cs cs[LBC_CS_MAX_NUM]; -}; - -#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 16, 0) -#define __ACCESS_ONCE(x) ({ \ - __maybe_unused typeof(x) __var = (__force typeof(x)) 0; \ - (volatile typeof(x) *)&(x); }) -#define ACCESS_ONCE(x) (*__ACCESS_ONCE(x)) -#endif - -#endif -- 2.25.1
From: fengsheng <fengsheng5@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4IYWW?from=project-issue CVE: NA ------------------------------------------------------------ This driver is not in use. Remove it. Signed-off-by: fengsheng <fengsheng5@huawei.com> Reviewed-by: lidongming <lidongming5@huawei.com> Reviewed-by: ouyang delong <ouyangdelong@huawei.com> Acked-by: Xie XiuQi <xiexiuqi@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> --- MAINTAINERS | 5 - arch/arm64/configs/hulk_defconfig | 1 - arch/arm64/configs/openeuler_defconfig | 1 - arch/arm64/configs/syzkaller_defconfig | 1 - arch/x86/configs/openeuler_defconfig | 1 - arch/x86/configs/storage_ci_defconfig | 1 - drivers/soc/Kconfig | 1 - drivers/soc/Makefile | 1 - drivers/soc/hisilicon/Kconfig | 2 - drivers/soc/hisilicon/Makefile | 1 - drivers/soc/hisilicon/sysctl/Kconfig | 4 - drivers/soc/hisilicon/sysctl/Makefile | 2 - .../soc/hisilicon/sysctl/dmc_c_union_define.h | 42 - drivers/soc/hisilicon/sysctl/dmc_reg_offset.h | 285 ------ .../sysctl/hllc_pcs_c_union_define.h | 45 - .../hisilicon/sysctl/hllc_pcs_reg_offset.h | 97 --- .../sysctl/hllc_ras_c_union_define.h | 78 -- .../hisilicon/sysctl/hllc_ras_reg_offset.h | 39 - .../sysctl/hllc_regs_c_union_define.h | 49 -- .../hisilicon/sysctl/hllc_regs_reg_offset.h | 132 --- .../soc/hisilicon/sysctl/pa_c_union_define.h | 45 - drivers/soc/hisilicon/sysctl/pa_reg_offset.h | 204 ----- .../hisilicon/sysctl/rasc_c_union_define.h | 66 -- .../soc/hisilicon/sysctl/rasc_reg_offset.h | 123 --- drivers/soc/hisilicon/sysctl/sysctl_dfx.c | 378 -------- drivers/soc/hisilicon/sysctl/sysctl_dfx.h | 24 - drivers/soc/hisilicon/sysctl/sysctl_drv.c | 819 ------------------ drivers/soc/hisilicon/sysctl/sysctl_drv.h | 137 --- .../soc/hisilicon/sysctl/sysctl_local_ras.c | 594 ------------- .../soc/hisilicon/sysctl/sysctl_local_ras.h | 250 ------ drivers/soc/hisilicon/sysctl/sysctl_pmbus.c | 720 --------------- drivers/soc/hisilicon/sysctl/sysctl_pmbus.h | 119 --- 32 files changed, 4267 deletions(-) delete mode 100644 drivers/soc/hisilicon/Kconfig delete mode 100644 drivers/soc/hisilicon/Makefile delete mode 100644 drivers/soc/hisilicon/sysctl/Kconfig delete mode 100644 drivers/soc/hisilicon/sysctl/Makefile delete mode 100644 drivers/soc/hisilicon/sysctl/dmc_c_union_define.h delete mode 100644 drivers/soc/hisilicon/sysctl/dmc_reg_offset.h delete mode 100644 drivers/soc/hisilicon/sysctl/hllc_pcs_c_union_define.h delete mode 100644 drivers/soc/hisilicon/sysctl/hllc_pcs_reg_offset.h delete mode 100644 drivers/soc/hisilicon/sysctl/hllc_ras_c_union_define.h delete mode 100644 drivers/soc/hisilicon/sysctl/hllc_ras_reg_offset.h delete mode 100644 drivers/soc/hisilicon/sysctl/hllc_regs_c_union_define.h delete mode 100644 drivers/soc/hisilicon/sysctl/hllc_regs_reg_offset.h delete mode 100644 drivers/soc/hisilicon/sysctl/pa_c_union_define.h delete mode 100644 drivers/soc/hisilicon/sysctl/pa_reg_offset.h delete mode 100644 drivers/soc/hisilicon/sysctl/rasc_c_union_define.h delete mode 100644 drivers/soc/hisilicon/sysctl/rasc_reg_offset.h delete mode 100644 drivers/soc/hisilicon/sysctl/sysctl_dfx.c delete mode 100644 drivers/soc/hisilicon/sysctl/sysctl_dfx.h delete mode 100644 drivers/soc/hisilicon/sysctl/sysctl_drv.c delete mode 100644 drivers/soc/hisilicon/sysctl/sysctl_drv.h delete mode 100644 drivers/soc/hisilicon/sysctl/sysctl_local_ras.c delete mode 100644 drivers/soc/hisilicon/sysctl/sysctl_local_ras.h delete mode 100644 drivers/soc/hisilicon/sysctl/sysctl_pmbus.c delete mode 100644 drivers/soc/hisilicon/sysctl/sysctl_pmbus.h diff --git a/MAINTAINERS b/MAINTAINERS index b84c7cbd4e555..de1f5d368ca88 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16332,11 +16332,6 @@ S: Buried alive in reporters F: * F: */ -HISILICON SYSCTRL DRIVER -M: Feng Sheng <fengsheng5@huawei.com> -S: Maintained -F: drivers/soc/hisilicon/sysctl/ - HISILICON IO_MGMT SUBSYSTEM RDE DRIVER M: hucheng Hu(Cheng) <hucheng.hu@huawei.com> S: Maintained diff --git a/arch/arm64/configs/hulk_defconfig b/arch/arm64/configs/hulk_defconfig index 904e9b557122e..97354a29c914c 100644 --- a/arch/arm64/configs/hulk_defconfig +++ b/arch/arm64/configs/hulk_defconfig @@ -280,7 +280,6 @@ CONFIG_ARCH_XGENE=y # CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQMP is not set CONFIG_HAVE_LIVEPATCH_WO_FTRACE=y -CONFIG_SOC_HISILICON_SYSCTL=m # # Enable Livepatch diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 20ad626791d14..06d57fc62c324 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -5011,7 +5011,6 @@ CONFIG_ARM_SMMU_V3=y # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set -CONFIG_SOC_HISILICON_SYSCTL=m # CONFIG_PM_DEVFREQ is not set CONFIG_EXTCON=y diff --git a/arch/arm64/configs/syzkaller_defconfig b/arch/arm64/configs/syzkaller_defconfig index 7c8eca466e25a..caa022e24fdc3 100644 --- a/arch/arm64/configs/syzkaller_defconfig +++ b/arch/arm64/configs/syzkaller_defconfig @@ -280,7 +280,6 @@ CONFIG_ARCH_XGENE=y # CONFIG_ARCH_ZX is not set # CONFIG_ARCH_ZYNQMP is not set CONFIG_HAVE_LIVEPATCH_WO_FTRACE=y -CONFIG_SOC_HISILICON_SYSCTL=m # # Enable Livepatch # diff --git a/arch/x86/configs/openeuler_defconfig b/arch/x86/configs/openeuler_defconfig index 0700ef6fc0cf0..035d4b454dc80 100644 --- a/arch/x86/configs/openeuler_defconfig +++ b/arch/x86/configs/openeuler_defconfig @@ -6168,7 +6168,6 @@ CONFIG_IRQ_REMAP=y # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set -CONFIG_SOC_HISILICON_SYSCTL=m # CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set # CONFIG_MEMORY is not set diff --git a/arch/x86/configs/storage_ci_defconfig b/arch/x86/configs/storage_ci_defconfig index 27de222f67966..d18d5fcb90b37 100644 --- a/arch/x86/configs/storage_ci_defconfig +++ b/arch/x86/configs/storage_ci_defconfig @@ -2389,7 +2389,6 @@ CONFIG_PCC=y # Xilinx SoC drivers # # CONFIG_XILINX_VCU is not set -CONFIG_SOC_HISILICON_SYSCTL=m # CONFIG_PM_DEVFREQ is not set # CONFIG_EXTCON is not set # CONFIG_MEMORY is not set diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 9cf389b46f400..c07b4a85253f2 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -18,6 +18,5 @@ source "drivers/soc/ux500/Kconfig" source "drivers/soc/versatile/Kconfig" source "drivers/soc/xilinx/Kconfig" source "drivers/soc/zte/Kconfig" -source "drivers/soc/hisilicon/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index acc6b9e4834ea..f0d46b16e08c4 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -25,4 +25,3 @@ obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_PLAT_VERSATILE) += versatile/ obj-y += xilinx/ obj-$(CONFIG_ARCH_ZX) += zte/ -obj-y += hisilicon/ diff --git a/drivers/soc/hisilicon/Kconfig b/drivers/soc/hisilicon/Kconfig deleted file mode 100644 index 6dd657e3eaa98..0000000000000 --- a/drivers/soc/hisilicon/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -source "drivers/soc/hisilicon/sysctl/Kconfig" - diff --git a/drivers/soc/hisilicon/Makefile b/drivers/soc/hisilicon/Makefile deleted file mode 100644 index fe68ce0d54c3e..0000000000000 --- a/drivers/soc/hisilicon/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y += sysctl/ diff --git a/drivers/soc/hisilicon/sysctl/Kconfig b/drivers/soc/hisilicon/sysctl/Kconfig deleted file mode 100644 index b97eafc59952d..0000000000000 --- a/drivers/soc/hisilicon/sysctl/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -config SOC_HISILICON_SYSCTL - tristate - depends on ACPI_APEI_GHES - default m \ No newline at end of file diff --git a/drivers/soc/hisilicon/sysctl/Makefile b/drivers/soc/hisilicon/sysctl/Makefile deleted file mode 100644 index fc70a8a8c1a38..0000000000000 --- a/drivers/soc/hisilicon/sysctl/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -his_sysctl-objs := sysctl_drv.o sysctl_local_ras.o sysctl_dfx.o sysctl_pmbus.o -obj-$(CONFIG_SOC_HISILICON_SYSCTL) += his_sysctl.o diff --git a/drivers/soc/hisilicon/sysctl/dmc_c_union_define.h b/drivers/soc/hisilicon/sysctl/dmc_c_union_define.h deleted file mode 100644 index 63a560719d5d0..0000000000000 --- a/drivers/soc/hisilicon/sysctl/dmc_c_union_define.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __DMC_C_UNION_DEFINE_H__ -#define __DMC_C_UNION_DEFINE_H__ - -/* Define the union dmc_ddrc_u_cfg_ecc */ -typedef union { - /* Define the struct bits */ - struct { - unsigned int ecc_en : 1 ; /* [0] */ - unsigned int reserved_0 : 3 ; /* [3..1] */ - unsigned int eccwb_en : 1 ; /* [4] */ - unsigned int reserved_1 : 3 ; /* [7..5] */ - unsigned int ecc_byp : 1 ; /* [8] */ - unsigned int ecc_msk : 1 ; /* [9] */ - unsigned int reserved_2 : 2 ; /* [11..10] */ - unsigned int ras_en : 1 ; /* [12] */ - unsigned int ras_bps : 1 ; /* [13] */ - unsigned int poison_en : 1 ; /* [14] */ - unsigned int poison_chk_type : 1 ; /* [15] */ - unsigned int reserved_3 : 16 ; /* [31..16] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} dmc_ddrc_u_cfg_ecc; - -#endif /* __DMC_C_UNION_DEFINE_H__ */ diff --git a/drivers/soc/hisilicon/sysctl/dmc_reg_offset.h b/drivers/soc/hisilicon/sysctl/dmc_reg_offset.h deleted file mode 100644 index 7be5ebfd26b61..0000000000000 --- a/drivers/soc/hisilicon/sysctl/dmc_reg_offset.h +++ /dev/null @@ -1,285 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __DMC_REG_OFFSET_H__ -#define __DMC_REG_OFFSET_H__ - -/* DMC Base address of Module's Register */ -#define DMC_DMC_BASE (0x0) - -/******************************************************************************/ -/* xxx DMC Registers' Definitions */ -/******************************************************************************/ -#define DMC_DMC_DDRC_CTRL_SREF_REG (DMC_DMC_BASE + 0x0) -#define DMC_DMC_DDRC_CTRL_INIT_REG (DMC_DMC_BASE + 0x4) -#define DMC_DMC_DDRC_CTRL_DDRRST_REG (DMC_DMC_BASE + 0x8) -#define DMC_DMC_DDRC_CTRL_SFC_REG (DMC_DMC_BASE + 0xC) -#define DMC_DMC_DDRC_CTRL_PERF_REG (DMC_DMC_BASE + 0x10) -#define DMC_DMC_DDRC_CTRL_MTEST_REG (DMC_DMC_BASE + 0x14) -#define DMC_DMC_DDRC_CFG_LP_REG (DMC_DMC_BASE + 0x1C) -#define DMC_DMC_DDRC_CFG_SREF_REG (DMC_DMC_BASE + 0x20) -#define DMC_DMC_DDRC_CFG_PD_REG (DMC_DMC_BASE + 0x28) -#define DMC_DMC_DDRC_CFG_AREF_REG (DMC_DMC_BASE + 0x2C) -#define DMC_DMC_DDRC_CFG_ECC_REG (DMC_DMC_BASE + 0x30) -#define DMC_DMC_DDRC_CFG_ERRINJ_REG (DMC_DMC_BASE + 0x34) -#define DMC_DMC_DDRC_CFG_FIFO_ERRINJ_REG (DMC_DMC_BASE + 0x38) -#define DMC_DMC_DDRC_CFG_OPENPAGE_REG (DMC_DMC_BASE + 0x3C) -#define DMC_DMC_DDRC_CFG_WORKMODE_REG (DMC_DMC_BASE + 0x40) -#define DMC_DMC_DDRC_CFG_WORKMODE2_REG (DMC_DMC_BASE + 0x44) -#define DMC_DMC_DDRC_CFG_WORKMODE3_REG (DMC_DMC_BASE + 0x48) -#define DMC_DMC_DDRC_CFG_DDRMODE_REG (DMC_DMC_BASE + 0x50) -#define DMC_DMC_DDRC_CFG_DIMM_REG (DMC_DMC_BASE + 0x54) -#define DMC_DMC_DDRC_CFG_SCRAMB_REG (DMC_DMC_BASE + 0x58) -#define DMC_DMC_DDRC_CFG_RNKVOL_REG (DMC_DMC_BASE + 0x60) -#define DMC_DMC_DDRC_CFG_ODT_REG (DMC_DMC_BASE + 0xA0) -#define DMC_DMC_DDRC_CFG_CA_ODT_REG (DMC_DMC_BASE + 0xE0) -#define DMC_DMC_DDRC_CFG_TIMING0_REG (DMC_DMC_BASE + 0x100) -#define DMC_DMC_DDRC_CFG_TIMING1_REG (DMC_DMC_BASE + 0x104) -#define DMC_DMC_DDRC_CFG_TIMING2_REG (DMC_DMC_BASE + 0x108) -#define DMC_DMC_DDRC_CFG_TIMING3_REG (DMC_DMC_BASE + 0x10C) -#define DMC_DMC_DDRC_CFG_TIMING4_REG (DMC_DMC_BASE + 0x110) -#define DMC_DMC_DDRC_CFG_TIMING5_REG (DMC_DMC_BASE + 0x114) -#define DMC_DMC_DDRC_CFG_TIMING6_REG (DMC_DMC_BASE + 0x118) -#define DMC_DMC_DDRC_CFG_TIMING7_REG (DMC_DMC_BASE + 0x11C) -#define DMC_DMC_DDRC_CFG_TIMING8_REG (DMC_DMC_BASE + 0x120) -#define DMC_DMC_DDRC_CFG_NXT_TIMING0_REG (DMC_DMC_BASE + 0x124) -#define DMC_DMC_DDRC_CFG_NXT_TIMING1_REG (DMC_DMC_BASE + 0x128) -#define DMC_DMC_DDRC_CFG_NXT_TIMING2_REG (DMC_DMC_BASE + 0x12C) -#define DMC_DMC_DDRC_CFG_NXT_TIMING3_REG (DMC_DMC_BASE + 0x130) -#define DMC_DMC_DDRC_CFG_NXT_TIMING4_REG (DMC_DMC_BASE + 0x134) -#define DMC_DMC_DDRC_CFG_NXT_TIMING5_REG (DMC_DMC_BASE + 0x138) -#define DMC_DMC_DDRC_CFG_NXT_TIMING6_REG (DMC_DMC_BASE + 0x13C) -#define DMC_DMC_DDRC_CFG_NXT_TIMING7_REG (DMC_DMC_BASE + 0x140) -#define DMC_DMC_DDRC_CFG_NXT_TIMING8_REG (DMC_DMC_BASE + 0x144) -#define DMC_DMC_DDRC_CFG_BLDATA_REG (DMC_DMC_BASE + 0x148) -#define DMC_DMC_DDRC_CFG_DMCLVL_REG (DMC_DMC_BASE + 0x14C) -#define DMC_DMC_DDRC_CFG_TIMEOUT_REG (DMC_DMC_BASE + 0x150) -#define DMC_DMC_DDRC_CFG_QOS_REG (DMC_DMC_BASE + 0x154) -#define DMC_DMC_DDRC_CFG_EXMBIST_CMD_REG (DMC_DMC_BASE + 0x158) -#define DMC_DMC_DDRC_CFG_EXMBIST_DAT_REG (DMC_DMC_BASE + 0x15C) -#define DMC_DMC_DDRC_CFG_MBIST_REG (DMC_DMC_BASE + 0x160) -#define DMC_DMC_DDRC_CFG_EXMBIST_CLK_MODE_REG (DMC_DMC_BASE + 0x164) -#define DMC_DMC_DDRC_CFG_OSC_PRD_REG (DMC_DMC_BASE + 0x178) -#define DMC_DMC_DDRC_CFG_OSC_CFG_REG (DMC_DMC_BASE + 0x17C) -#define DMC_DMC_DDRC_CFG_TRAIN_REG (DMC_DMC_BASE + 0x180) -#define DMC_DMC_DDRC_CFG_DFI_LAT0_REG (DMC_DMC_BASE + 0x184) -#define DMC_DMC_DDRC_CFG_DFI_LAT1_REG (DMC_DMC_BASE + 0x188) -#define DMC_DMC_DDRC_CFG_REC0_REG (DMC_DMC_BASE + 0x190) -#define DMC_DMC_DDRC_CFG_REC1_REG (DMC_DMC_BASE + 0x194) -#define DMC_DMC_DDRC_CFG_CRC_REG (DMC_DMC_BASE + 0x198) -#define DMC_DMC_DDRC_CFG_CRC_ERRINJ0_REG (DMC_DMC_BASE + 0x1A0) -#define DMC_DMC_DDRC_CFG_CRC_ERRINJ1_REG (DMC_DMC_BASE + 0x1A4) -#define DMC_DMC_DDRC_CFG_PAR_ERRINJ0_REG (DMC_DMC_BASE + 0x1A8) -#define DMC_DMC_DDRC_CFG_PAR_ERRINJ1_REG (DMC_DMC_BASE + 0x1AC) -#define DMC_DMC_DDRC_CFG_DDRPHY_REG (DMC_DMC_BASE + 0x200) -#define DMC_DMC_DDRC_CFG_AGING_REG (DMC_DMC_BASE + 0x204) -#define DMC_DMC_DDRC_CFG_SFC_TIM_REG (DMC_DMC_BASE + 0x20C) -#define DMC_DMC_DDRC_CFG_SFC_REG (DMC_DMC_BASE + 0x210) -#define DMC_DMC_DDRC_CFG_SFC_ADDR0_REG (DMC_DMC_BASE + 0x214) -#define DMC_DMC_DDRC_CFG_SFC_ADDR1_REG (DMC_DMC_BASE + 0x218) -#define DMC_DMC_DDRC_CFG_SFC_WDATA_REG (DMC_DMC_BASE + 0x21C) -#define DMC_DMC_DDRC_CFG_SFC_WCTRL_REG (DMC_DMC_BASE + 0x220) -#define DMC_DMC_DDRC_CFG_SFC_MASK0_REG (DMC_DMC_BASE + 0x224) -#define DMC_DMC_DDRC_CFG_SFC_MASK1_REG (DMC_DMC_BASE + 0x228) -#define DMC_DMC_DDRC_CFG_TMON_REG (DMC_DMC_BASE + 0x240) -#define DMC_DMC_DDRC_CFG_TMON_RANK_REG (DMC_DMC_BASE + 0x244) -#define DMC_DMC_DDRC_CFG_TMON_AREF_REG (DMC_DMC_BASE + 0x248) -#define DMC_DMC_DDRC_CFG_EXRESP_REG (DMC_DMC_BASE + 0x24C) -#define DMC_DMC_DDRC_CFG_MRR_MAP_REG (DMC_DMC_BASE + 0x250) -#define DMC_DMC_DDRC_CFG_STADAT_REG (DMC_DMC_BASE + 0x254) -#define DMC_DMC_DDRC_CFG_DATMIN_REG (DMC_DMC_BASE + 0x258) -#define DMC_DMC_DDRC_CFG_DATMAX_REG (DMC_DMC_BASE + 0x25C) -#define DMC_DMC_DDRC_CFG_STACMD_REG (DMC_DMC_BASE + 0x260) -#define DMC_DMC_DDRC_CFG_CMDMIN_REG (DMC_DMC_BASE + 0x264) -#define DMC_DMC_DDRC_CFG_CMDMAX_REG (DMC_DMC_BASE + 0x268) -#define DMC_DMC_DDRC_CFG_PERF_REG (DMC_DMC_BASE + 0x26C) -#define DMC_DMC_DDRC_CFG_STAID_REG (DMC_DMC_BASE + 0x270) -#define DMC_DMC_DDRC_CFG_STAIDMSK_REG (DMC_DMC_BASE + 0x274) -#define DMC_DMC_DDRC_CFG_DUM_EN_REG (DMC_DMC_BASE + 0x278) -#define DMC_DMC_DDRC_CFG_DUM_CFG_REG (DMC_DMC_BASE + 0x27C) -#define DMC_DMC_DDRC_INTMSK_REG (DMC_DMC_BASE + 0x280) -#define DMC_DMC_DDRC_RINT_REG (DMC_DMC_BASE + 0x284) -#define DMC_DMC_DDRC_INTSTS_REG (DMC_DMC_BASE + 0x288) -#define DMC_DMC_DDRC_CURR_STATUS_REG (DMC_DMC_BASE + 0x290) -#define DMC_DMC_DDRC_CURR_FUNC_REG (DMC_DMC_BASE + 0x294) -#define DMC_DMC_DDRC_CURR_FUNC2_REG (DMC_DMC_BASE + 0x298) -#define DMC_DMC_DDRC_CURR_FUNC3_REG (DMC_DMC_BASE + 0x29C) -#define DMC_DMC_DDRC_CURR_EXECST_REG (DMC_DMC_BASE + 0x2A0) -#define DMC_DMC_DDRC_CURR_WGFIFOST_REG (DMC_DMC_BASE + 0x2A4) -#define DMC_DMC_DDRC_CFG_ECC_CTRL_REG (DMC_DMC_BASE + 0x2A8) -#define DMC_DMC_DDRC_HIS_SERR_ID_REG (DMC_DMC_BASE + 0x2AC) -#define DMC_DMC_DDRC_HIS_SERR_ADR0_REG (DMC_DMC_BASE + 0x2D0) -#define DMC_DMC_DDRC_HIS_SERR_ADR1_REG (DMC_DMC_BASE + 0x2D4) -#define DMC_DMC_DDRC_HIS_SERR_RDATA0_REG (DMC_DMC_BASE + 0x2D8) -#define DMC_DMC_DDRC_HIS_SERR_RDATA1_REG (DMC_DMC_BASE + 0x2DC) -#define DMC_DMC_DDRC_HIS_SERR_RDATA2_REG (DMC_DMC_BASE + 0x2E0) -#define DMC_DMC_DDRC_HIS_SERR_RDATA3_REG (DMC_DMC_BASE + 0x2E4) -#define DMC_DMC_DDRC_HIS_SERR_RDATA4_REG (DMC_DMC_BASE + 0x2E8) -#define DMC_DMC_DDRC_HIS_SERR_RDATA5_REG (DMC_DMC_BASE + 0x2EC) -#define DMC_DMC_DDRC_HIS_SERR_RDATA6_REG (DMC_DMC_BASE + 0x2F0) -#define DMC_DMC_DDRC_HIS_SERR_RDATA7_REG (DMC_DMC_BASE + 0x2F4) -#define DMC_DMC_DDRC_HIS_SERR_RDATA8_REG (DMC_DMC_BASE + 0x2F8) -#define DMC_DMC_DDRC_HIS_SERR_EXPDATA0_REG (DMC_DMC_BASE + 0x2FC) -#define DMC_DMC_DDRC_HIS_SERR_EXPDATA1_REG (DMC_DMC_BASE + 0x300) -#define DMC_DMC_DDRC_HIS_SERR_EXPDATA2_REG (DMC_DMC_BASE + 0x304) -#define DMC_DMC_DDRC_HIS_SERR_EXPDATA3_REG (DMC_DMC_BASE + 0x308) -#define DMC_DMC_DDRC_HIS_SERR_EXPDATA4_REG (DMC_DMC_BASE + 0x30C) -#define DMC_DMC_DDRC_HIS_SERR_EXPDATA5_REG (DMC_DMC_BASE + 0x310) -#define DMC_DMC_DDRC_HIS_SERR_EXPDATA6_REG (DMC_DMC_BASE + 0x314) -#define DMC_DMC_DDRC_HIS_SERR_EXPDATA7_REG (DMC_DMC_BASE + 0x318) -#define DMC_DMC_DDRC_HIS_SERR_EXPDATA8_REG (DMC_DMC_BASE + 0x31C) -#define DMC_DMC_DDRC_HIS_MERR_ADR0_REG (DMC_DMC_BASE + 0x320) -#define DMC_DMC_DDRC_HIS_MERR_ADR1_REG (DMC_DMC_BASE + 0x324) -#define DMC_DMC_DDRC_HIS_MERR_ID_REG (DMC_DMC_BASE + 0x328) -#define DMC_DMC_DDRC_HIS_MERR_RDATA0_REG (DMC_DMC_BASE + 0x330) -#define DMC_DMC_DDRC_HIS_MERR_RDATA1_REG (DMC_DMC_BASE + 0x334) -#define DMC_DMC_DDRC_HIS_MERR_RDATA2_REG (DMC_DMC_BASE + 0x338) -#define DMC_DMC_DDRC_HIS_MERR_RDATA3_REG (DMC_DMC_BASE + 0x33C) -#define DMC_DMC_DDRC_HIS_MERR_RDATA4_REG (DMC_DMC_BASE + 0x340) -#define DMC_DMC_DDRC_HIS_MERR_RDATA5_REG (DMC_DMC_BASE + 0x344) -#define DMC_DMC_DDRC_HIS_MERR_RDATA6_REG (DMC_DMC_BASE + 0x348) -#define DMC_DMC_DDRC_HIS_MERR_RDATA7_REG (DMC_DMC_BASE + 0x34C) -#define DMC_DMC_DDRC_HIS_MERR_RDATA8_REG (DMC_DMC_BASE + 0x350) -#define DMC_DMC_DDRC_HIS_MERR_EXPDATA0_REG (DMC_DMC_BASE + 0x354) -#define DMC_DMC_DDRC_HIS_MERR_EXPDATA1_REG (DMC_DMC_BASE + 0x358) -#define DMC_DMC_DDRC_HIS_MERR_EXPDATA2_REG (DMC_DMC_BASE + 0x35C) -#define DMC_DMC_DDRC_HIS_MERR_EXPDATA3_REG (DMC_DMC_BASE + 0x360) -#define DMC_DMC_DDRC_HIS_MERR_EXPDATA4_REG (DMC_DMC_BASE + 0x364) -#define DMC_DMC_DDRC_HIS_MERR_EXPDATA5_REG (DMC_DMC_BASE + 0x368) -#define DMC_DMC_DDRC_HIS_MERR_EXPDATA6_REG (DMC_DMC_BASE + 0x36C) -#define DMC_DMC_DDRC_HIS_MERR_EXPDATA7_REG (DMC_DMC_BASE + 0x370) -#define DMC_DMC_DDRC_HIS_MERR_EXPDATA8_REG (DMC_DMC_BASE + 0x374) -#define DMC_DMC_DDRC_HIS_SERRCNT_REG (DMC_DMC_BASE + 0x378) -#define DMC_DMC_DDRC_HIS_MERRCNT_REG (DMC_DMC_BASE + 0x37C) -#define DMC_DMC_DDRC_HIS_FLUX_WR_REG (DMC_DMC_BASE + 0x380) -#define DMC_DMC_DDRC_HIS_FLUX_RD_REG (DMC_DMC_BASE + 0x384) -#define DMC_DMC_DDRC_HIS_FLUX_WCMD_REG (DMC_DMC_BASE + 0x388) -#define DMC_DMC_DDRC_HIS_FLUX_RCMD_REG (DMC_DMC_BASE + 0x38C) -#define DMC_DMC_DDRC_HIS_FLUXID_WR_REG (DMC_DMC_BASE + 0x390) -#define DMC_DMC_DDRC_HIS_FLUXID_RD_REG (DMC_DMC_BASE + 0x394) -#define DMC_DMC_DDRC_HIS_FLUXID_WCMD_REG (DMC_DMC_BASE + 0x398) -#define DMC_DMC_DDRC_HIS_FLUXID_RCMD_REG (DMC_DMC_BASE + 0x39C) -#define DMC_DMC_DDRC_HIS_WLATCNT0_REG (DMC_DMC_BASE + 0x3A0) -#define DMC_DMC_DDRC_HIS_WLATCNT1_REG (DMC_DMC_BASE + 0x3A4) -#define DMC_DMC_DDRC_HIS_RLATCNT0_REG (DMC_DMC_BASE + 0x3A8) -#define DMC_DMC_DDRC_HIS_RLATCNT1_REG (DMC_DMC_BASE + 0x3AC) -#define DMC_DMC_DDRC_HIS_INHERE_RLAT_CNT_REG (DMC_DMC_BASE + 0x3B0) -#define DMC_DMC_DDRC_STAT_RPT_REG (DMC_DMC_BASE + 0x3B4) -#define DMC_DMC_DDRC_HIS_CMD_SUM_REG (DMC_DMC_BASE + 0x3B8) -#define DMC_DMC_DDRC_HIS_DAT_SUM_REG (DMC_DMC_BASE + 0x3BC) -#define DMC_DMC_DDRC_HIS_PRE_CMD_REG (DMC_DMC_BASE + 0x3C0) -#define DMC_DMC_DDRC_HIS_ACT_CMD_REG (DMC_DMC_BASE + 0x3C4) -#define DMC_DMC_DDRC_HIS_BNK_CHG_REG (DMC_DMC_BASE + 0x3C8) -#define DMC_DMC_DDRC_HIS_RNK_CHG_REG (DMC_DMC_BASE + 0x3CC) -#define DMC_DMC_DDRC_HIS_RW_CHG_REG (DMC_DMC_BASE + 0x3D0) -#define DMC_DMC_DDRC_HIS_TMON_ERR_REG (DMC_DMC_BASE + 0x3E0) -#define DMC_DMC_DDRC_HIS_RERR_ADDRL_REG (DMC_DMC_BASE + 0x3F0) -#define DMC_DMC_DDRC_HIS_RERR_ADDRH_REG (DMC_DMC_BASE + 0x3F4) -#define DMC_DMC_DDRC_HIS_RERR_ID_REG (DMC_DMC_BASE + 0x3F8) -#define DMC_DMC_DDRC_HIS_RERR_CNT_REG (DMC_DMC_BASE + 0x3FC) -#define DMC_DMC_DDRC_HIS_REC_ERR0_REG (DMC_DMC_BASE + 0x400) -#define DMC_DMC_DDRC_HIS_REC_ERR1_REG (DMC_DMC_BASE + 0x404) -#define DMC_DMC_DDRC_HIS_EXMBIST_STATUS_REG (DMC_DMC_BASE + 0x40C) -#define DMC_DMC_DDRC_HIS_SFC_RDATA_REG (DMC_DMC_BASE + 0x4A8) -#define DMC_DMC_DDRC_SFC_RCTRL_REG (DMC_DMC_BASE + 0x4AC) -#define DMC_DMC_DDRC_HIS_SFC_RDATA0_DBI_REG (DMC_DMC_BASE + 0x4C8) -#define DMC_DMC_DDRC_HIS_SFC_RDATA1_DBI_REG (DMC_DMC_BASE + 0x4CC) -#define DMC_DMC_DDRC_HIS_SFC_RDATA_ECC_DBI_REG (DMC_DMC_BASE + 0x4D0) -#define DMC_DMC_DDRC_FUNC_STAT0_REG (DMC_DMC_BASE + 0x4D4) -#define DMC_DMC_DDRC_FUNC_STAT1_REG (DMC_DMC_BASE + 0x4D8) -#define DMC_DMC_DDRC_FUNC_STAT2_REG (DMC_DMC_BASE + 0x4DC) -#define DMC_DMC_DDRC_FUNC_STAT3_REG (DMC_DMC_BASE + 0x4E0) -#define DMC_DMC_DDRC_FUNC_STAT4_REG (DMC_DMC_BASE + 0x4E4) -#define DMC_DMC_DDRC_FUNC_STAT5_REG (DMC_DMC_BASE + 0x4E8) -#define DMC_DMC_DDRC_FUNC_STAT6_REG (DMC_DMC_BASE + 0x4EC) -#define DMC_DMC_DDRC_FUNC_STAT7_REG (DMC_DMC_BASE + 0x4F0) -#define DMC_DMC_DDRC_FUNC_STAT8_REG (DMC_DMC_BASE + 0x4F4) -#define DMC_DMC_DDRC_FUNC_STAT9_REG (DMC_DMC_BASE + 0x4F8) -#define DMC_DMC_DDRC_FUNC_STAT10_REG (DMC_DMC_BASE + 0x4FC) -#define DMC_DMC_DDRC_FUNC_STAT11_REG (DMC_DMC_BASE + 0x500) -#define DMC_DMC_DDRC_DMC_STAT12_REG (DMC_DMC_BASE + 0x504) -#define DMC_DMC_DDRC_TEST_RAM_TMOD_REG (DMC_DMC_BASE + 0x508) -#define DMC_DMC_DDRC_TEST_RTL_CFG0_REG (DMC_DMC_BASE + 0x510) -#define DMC_DMC_DDRC_TEST_RTL_CFG1_REG (DMC_DMC_BASE + 0x514) -#define DMC_DMC_DDRC_TEST_RTL_CFG2_REG (DMC_DMC_BASE + 0x518) -#define DMC_DMC_DDRC_OSC_COUNT_REG (DMC_DMC_BASE + 0x520) -#define DMC_DMC_DDRC_EDXN_DQMAP_REG (DMC_DMC_BASE + 0x580) -#define DMC_DMC_DDRC_ODXN_DQMAP_REG (DMC_DMC_BASE + 0x584) -#define DMC_DMC_DDRC_CFG_SFC_EXTCMD_CTRL_REG (DMC_DMC_BASE + 0x600) -#define DMC_DMC_DDRC_CFG_SFC_LOOP_CTRL_REG (DMC_DMC_BASE + 0x604) -#define DMC_DMC_DDRC_CFG_SFC_BER_RD_RPT_REG (DMC_DMC_BASE + 0x608) -#define DMC_DMC_DDRC_CFG_SFC_HEAD_TAIL_CUT_REG (DMC_DMC_BASE + 0x60C) -#define DMC_DMC_DDRC_CFG_SFC_PAT_PRD_REG (DMC_DMC_BASE + 0x610) -#define DMC_DMC_DDRC_CFG_SFC_WL_CTRL_REG (DMC_DMC_BASE + 0x614) -#define DMC_DMC_DDRC_CFG_SFC_ADDR2_REG (DMC_DMC_BASE + 0x618) -#define DMC_DMC_DDRC_CFG_SFC_ADDR3_REG (DMC_DMC_BASE + 0x61C) -#define DMC_DMC_DDRC_CFG_SFC_PAT_SEL_REG (DMC_DMC_BASE + 0x620) -#define DMC_DMC_DDRC_CFG_SFC_PAT_SEL_PTR_REG (DMC_DMC_BASE + 0x624) -#define DMC_DMC_DDRC_CFG_SFC_CMP_MASK_REG (DMC_DMC_BASE + 0x628) -#define DMC_DMC_DDRC_CFG_SFC_CMP_MASK_PTR_REG (DMC_DMC_BASE + 0x62C) -#define DMC_DMC_DDRC_CFG_SFC_TIM2_REG (DMC_DMC_BASE + 0x630) -#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED_REG (DMC_DMC_BASE + 0x634) -#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED1_REG (DMC_DMC_BASE + 0x638) -#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED2_REG (DMC_DMC_BASE + 0x63C) -#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED3_REG (DMC_DMC_BASE + 0x640) -#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED4_REG (DMC_DMC_BASE + 0x644) -#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED5_REG (DMC_DMC_BASE + 0x648) -#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED6_REG (DMC_DMC_BASE + 0x64C) -#define DMC_DMC_DDRC_CFG_SFC_INIT_SEED7_REG (DMC_DMC_BASE + 0x650) -#define DMC_DMC_DDRC_HIS_SFC_DQS_POS_ERR_0_REG (DMC_DMC_BASE + 0x654) -#define DMC_DMC_DDRC_HIS_SFC_DQS_POS_ERR_1_REG (DMC_DMC_BASE + 0x658) -#define DMC_DMC_DDRC_HIS_SFC_DQS_POS_ERR_2_REG (DMC_DMC_BASE + 0x65C) -#define DMC_DMC_DDRC_HIS_SFC_DQS_NEG_ERR_0_REG (DMC_DMC_BASE + 0x660) -#define DMC_DMC_DDRC_HIS_SFC_DQS_NEG_ERR_1_REG (DMC_DMC_BASE + 0x664) -#define DMC_DMC_DDRC_HIS_SFC_DQS_NEG_ERR_2_REG (DMC_DMC_BASE + 0x668) -#define DMC_DMC_DDRC_HIS_SFC_PER_NIB_ERR_REG (DMC_DMC_BASE + 0x66C) -#define DMC_DMC_DDRC_HIS_SFC_PER_BYTE_ERR_REG (DMC_DMC_BASE + 0x670) -#define DMC_DMC_DDRC_HIS_SFC_ANY_ERR_REG (DMC_DMC_BASE + 0x674) -#define DMC_DMC_DDRC_HIS_SFC_QUE_CUR_PTR_REG (DMC_DMC_BASE + 0x678) -#define DMC_DMC_DDRC_HIS_SFC_ERR_NUM_REG (DMC_DMC_BASE + 0x67C) -#define DMC_DMC_DDRC_CFG_AC_ISI_PAT_REG (DMC_DMC_BASE + 0x680) -#define DMC_DMC_DDRC_CFG_AC_ISI_PTR_REG (DMC_DMC_BASE + 0x684) -#define DMC_DMC_DDRC_HIS_BG_CHG_REG (DMC_DMC_BASE + 0x688) -#define DMC_DMC_DDRC_CURR_EXEC_STATE_REG (DMC_DMC_BASE + 0x68C) -#define DMC_DMC_DDRC_PHYUPD_REQ_CNT_REG (DMC_DMC_BASE + 0x690) -#define DMC_DMC_DDRC_PHYUPD_EXIT_WAIT_REG (DMC_DMC_BASE + 0x694) -#define DMC_DMC_DDRC_CFG_TIMING9_REG (DMC_DMC_BASE + 0x698) -#define DMC_DMC_DDRC_CFG_NXT_TIMING9_REG (DMC_DMC_BASE + 0x69C) -#define DMC_DMC_DDRC_CFG_CE_CNT_TH_REG (DMC_DMC_BASE + 0x6A0) -#define DMC_DMC_DDRC_CFG_FUNNEL_CTRL_REG (DMC_DMC_BASE + 0x6A4) -#define DMC_DMC_DDRC_CFG_FUNNEL_BASE_REG (DMC_DMC_BASE + 0x6A8) -#define DMC_DMC_DDRC_CFG_FUNNEL_TH_REG (DMC_DMC_BASE + 0x6AC) -#define DMC_DMC_DDRC_HIS_SRAM_CE_CNT_REG (DMC_DMC_BASE + 0x6B0) -#define DMC_DMC_DDRC_HIS_DP_CE_CNT_REG (DMC_DMC_BASE + 0x6B4) -#define DMC_DMC_DDRC_CFG_AC_PIPE_REG (DMC_DMC_BASE + 0x6B8) -#define DMC_DMC_DDRC_HIS_AREF_PSTPND_CNT_REG (DMC_DMC_BASE + 0x6BC) -#define DMC_DMC_DDRC_PERF_EVENT_EN_REG (DMC_DMC_BASE + 0x6C0) -#define DMC_DMC_DDRC_PERF_INTR_REG (DMC_DMC_BASE + 0x6C4) -#define DMC_DMC_DDRC_PERF_INTM_REG (DMC_DMC_BASE + 0x6C8) -#define DMC_DMC_DDRC_PERF_INTS_REG (DMC_DMC_BASE + 0x6CC) -#define DMC_DMC_DDRC_PERF_INTC_REG (DMC_DMC_BASE + 0x6D0) -#define DMC_DMC_DDRC_CFG_RES0_REG (DMC_DMC_BASE + 0x700) -#define DMC_DMC_DDRC_CFG_RES1_REG (DMC_DMC_BASE + 0x704) -#define DMC_DMC_DDRC_CFG_RES2_REG (DMC_DMC_BASE + 0x708) -#define DMC_DMC_DDRC_CFG_RES3_REG (DMC_DMC_BASE + 0x70C) -#define DMC_DMC_DDRC_CFG_RES4_REG (DMC_DMC_BASE + 0x710) -#define DMC_DMC_DDRC_CFG_RES5_REG (DMC_DMC_BASE + 0x714) -#define DMC_DMC_DDRC_CFG_RES6_REG (DMC_DMC_BASE + 0x718) -#define DMC_DMC_DDRC_CFG_RES7_REG (DMC_DMC_BASE + 0x71C) -#define DMC_DMC_DDRC_CFG_MAGIC_WORD_REG (DMC_DMC_BASE + 0x7F0) -#define DMC_DMC_DDRC_CFG_VERSION_REG (DMC_DMC_BASE + 0xC10) - -#endif diff --git a/drivers/soc/hisilicon/sysctl/hllc_pcs_c_union_define.h b/drivers/soc/hisilicon/sysctl/hllc_pcs_c_union_define.h deleted file mode 100644 index 7236363c511e8..0000000000000 --- a/drivers/soc/hisilicon/sysctl/hllc_pcs_c_union_define.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HLLC_PCS_C_UNION_DEFINE_H__ -#define __HLLC_PCS_C_UNION_DEFINE_H__ - -/* Define the union pcs_u_tx_training_sts */ -typedef union { - /* Define the struct bits */ - struct { - unsigned int tx_curr_st : 7 ; /* [6..0] */ - unsigned int ts1_ack_send_over : 1 ; /* [7] */ - unsigned int ts1_ack_received : 1 ; /* [8] */ - unsigned int ts1_received : 1 ; /* [9] */ - unsigned int ts0_ack_send_over : 1 ; /* [10] */ - unsigned int ts0_ack_received : 1 ; /* [11] */ - unsigned int ts0_received : 1 ; /* [12] */ - unsigned int tx_training_succeed : 1 ; /* [13] */ - unsigned int tx_training_done : 1 ; /* [14] */ - unsigned int tx_training_over : 1 ; /* [15] */ - unsigned int snd_training_done : 1 ; /* [16] */ - unsigned int tx_asyn_fifo_full : 1 ; /* [17] */ - unsigned int tx_asyn_fifo_afull : 1 ; /* [18] */ - unsigned int tx_asyn_push_word_cnt : 5 ; /* [23..19] */ - unsigned int reserved_0 : 8 ; /* [31..24] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} pcs_u_tx_training_sts; - -#endif /* __HLLC_PCS_C_UNION_DEFINE_H__ */ diff --git a/drivers/soc/hisilicon/sysctl/hllc_pcs_reg_offset.h b/drivers/soc/hisilicon/sysctl/hllc_pcs_reg_offset.h deleted file mode 100644 index edef291b6c8f4..0000000000000 --- a/drivers/soc/hisilicon/sysctl/hllc_pcs_reg_offset.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HLLC_PCS_REG_OFFSET_H__ -#define __HLLC_PCS_REG_OFFSET_H__ - -/* HLLC_PCS Base address of Module's Register */ -#define HLLC_HLLC_PCS_BASE (0x0) - -/******************************************************************************/ -/* xxx HLLC_PCS Registers' Definitions */ -/******************************************************************************/ -#define HLLC_HLLC_PCS_PCS_GLOBAL_CFG_REG (HLLC_HLLC_PCS_BASE + 0x0) -#define HLLC_HLLC_PCS_PCS_MISC_CFG_REG (HLLC_HLLC_PCS_BASE + 0x4) -#define HLLC_HLLC_PCS_PCS_POLARITY_CFG_REG (HLLC_HLLC_PCS_BASE + 0x8) -#define HLLC_HLLC_PCS_PCS_TRAINING_CFG_REG (HLLC_HLLC_PCS_BASE + 0xC) -#define HLLC_HLLC_PCS_PLL_PHASE_ADJUST_PARAM_CFG_REG (HLLC_HLLC_PCS_BASE + 0x10) -#define HLLC_HLLC_PCS_PCS_PHASE_ADJUST_MODE_CTRL_REG (HLLC_HLLC_PCS_BASE + 0x14) -#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_EN_CFG_REG (HLLC_HLLC_PCS_BASE + 0x18) -#define HLLC_HLLC_PCS_PCS_SRC_SYNC_RD_PTR_MODE_CFG_REG (HLLC_HLLC_PCS_BASE + 0x1C) -#define HLLC_HLLC_PCS_PCS_SRC_SYNC_RD_PTR_CFG_REG (HLLC_HLLC_PCS_BASE + 0x20) -#define HLLC_HLLC_PCS_PCS_PARALLEL_LOOPBACK_CFG_REG (HLLC_HLLC_PCS_BASE + 0x24) -#define HLLC_HLLC_PCS_PCS_TRAINING_TIMEOUT_CFG_REG (HLLC_HLLC_PCS_BASE + 0x28) -#define HLLC_HLLC_PCS_RAS_INT_MASK_REG (HLLC_HLLC_PCS_BASE + 0x3C) -#define HLLC_HLLC_PCS_RAS_INT_STATUS_REG (HLLC_HLLC_PCS_BASE + 0x40) -#define HLLC_HLLC_PCS_HILINK_STATUS_REG (HLLC_HLLC_PCS_BASE + 0x44) -#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_0_REG (HLLC_HLLC_PCS_BASE + 0x48) -#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_1_REG (HLLC_HLLC_PCS_BASE + 0x4C) -#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_2_REG (HLLC_HLLC_PCS_BASE + 0x50) -#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_3_REG (HLLC_HLLC_PCS_BASE + 0x54) -#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_4_REG (HLLC_HLLC_PCS_BASE + 0x58) -#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_5_REG (HLLC_HLLC_PCS_BASE + 0x5C) -#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_6_REG (HLLC_HLLC_PCS_BASE + 0x60) -#define HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_7_REG (HLLC_HLLC_PCS_BASE + 0x64) -#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_0_REG (HLLC_HLLC_PCS_BASE + 0x68) -#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_1_REG (HLLC_HLLC_PCS_BASE + 0x6C) -#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_2_REG (HLLC_HLLC_PCS_BASE + 0x70) -#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_3_REG (HLLC_HLLC_PCS_BASE + 0x74) -#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_4_REG (HLLC_HLLC_PCS_BASE + 0x78) -#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_5_REG (HLLC_HLLC_PCS_BASE + 0x7C) -#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_6_REG (HLLC_HLLC_PCS_BASE + 0x80) -#define HLLC_HLLC_PCS_PCS_RX_TRAINING_STS_7_REG (HLLC_HLLC_PCS_BASE + 0x84) -#define HLLC_HLLC_PCS_PCS_PHASE_ADJUST_STATUS_REG (HLLC_HLLC_PCS_BASE + 0x90) -#define HLLC_HLLC_PCS_PCS_PHASE_ADJUST_PD_STATUS_REG (HLLC_HLLC_PCS_BASE + 0x94) -#define HLLC_HLLC_PCS_PCS_PHASE_ADJUST_CNT_REG (HLLC_HLLC_PCS_BASE + 0x98) -#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_0_REG (HLLC_HLLC_PCS_BASE + 0xA0) -#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_1_REG (HLLC_HLLC_PCS_BASE + 0xA4) -#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_2_REG (HLLC_HLLC_PCS_BASE + 0xA8) -#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_3_REG (HLLC_HLLC_PCS_BASE + 0xAC) -#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_4_REG (HLLC_HLLC_PCS_BASE + 0xB0) -#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_5_REG (HLLC_HLLC_PCS_BASE + 0xB4) -#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_6_REG (HLLC_HLLC_PCS_BASE + 0xB8) -#define HLLC_HLLC_PCS_PCS_SRC_SYNC_PD_STATUS_7_REG (HLLC_HLLC_PCS_BASE + 0xBC) -#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_0_REG (HLLC_HLLC_PCS_BASE + 0xD0) -#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_1_REG (HLLC_HLLC_PCS_BASE + 0xD4) -#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_2_REG (HLLC_HLLC_PCS_BASE + 0xD8) -#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_3_REG (HLLC_HLLC_PCS_BASE + 0xDC) -#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_4_REG (HLLC_HLLC_PCS_BASE + 0xE0) -#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_5_REG (HLLC_HLLC_PCS_BASE + 0xE4) -#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_6_REG (HLLC_HLLC_PCS_BASE + 0xE8) -#define HLLC_HLLC_PCS_PCS_RX_DESKEW_CNT_7_REG (HLLC_HLLC_PCS_BASE + 0xEC) -#define HLLC_HLLC_PCS_PCS_RX_HEAD_ILLEGAL_STATUS_REG (HLLC_HLLC_PCS_BASE + 0xF0) -#define HLLC_HLLC_PCS_PCS_BIST_START_REG (HLLC_HLLC_PCS_BASE + 0x100) -#define HLLC_HLLC_PCS_PCS_TEST_END_REG (HLLC_HLLC_PCS_BASE + 0x104) -#define HLLC_HLLC_PCS_PCS_BIST_CTRL_CFG_REG (HLLC_HLLC_PCS_BASE + 0x108) -#define HLLC_HLLC_PCS_PCS_BIST_MODE_CFG_REG (HLLC_HLLC_PCS_BASE + 0x10C) -#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_0_REG (HLLC_HLLC_PCS_BASE + 0x110) -#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_1_REG (HLLC_HLLC_PCS_BASE + 0x114) -#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_2_REG (HLLC_HLLC_PCS_BASE + 0x118) -#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_3_REG (HLLC_HLLC_PCS_BASE + 0x11C) -#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_4_REG (HLLC_HLLC_PCS_BASE + 0x120) -#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_5_REG (HLLC_HLLC_PCS_BASE + 0x124) -#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_6_REG (HLLC_HLLC_PCS_BASE + 0x128) -#define HLLC_HLLC_PCS_PCS_BIST_PRBS_STS_7_REG (HLLC_HLLC_PCS_BASE + 0x12C) -#define HLLC_HLLC_PCS_PCS_BIST_FLIT_STS_REG (HLLC_HLLC_PCS_BASE + 0x130) -#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_0_REG (HLLC_HLLC_PCS_BASE + 0x134) -#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_1_REG (HLLC_HLLC_PCS_BASE + 0x138) -#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_2_REG (HLLC_HLLC_PCS_BASE + 0x13C) -#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_3_REG (HLLC_HLLC_PCS_BASE + 0x140) -#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_4_REG (HLLC_HLLC_PCS_BASE + 0x144) -#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_5_REG (HLLC_HLLC_PCS_BASE + 0x148) -#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_6_REG (HLLC_HLLC_PCS_BASE + 0x14C) -#define HLLC_HLLC_PCS_PCS_BIST_SLICE_STS_7_REG (HLLC_HLLC_PCS_BASE + 0x150) -#endif diff --git a/drivers/soc/hisilicon/sysctl/hllc_ras_c_union_define.h b/drivers/soc/hisilicon/sysctl/hllc_ras_c_union_define.h deleted file mode 100644 index c81ab85da62b2..0000000000000 --- a/drivers/soc/hisilicon/sysctl/hllc_ras_c_union_define.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HLLC_RAS_C_UNION_DEFINE_H__ -#define __HLLC_RAS_C_UNION_DEFINE_H__ - -/* Define the union hllc_ras_u_err_misc1l */ -typedef union { - /* Define the struct bits */ - struct { - unsigned int hydra_tx_ch0_2bit_ecc_err : 1 ; /* [0] */ - unsigned int hydra_tx_ch1_2bit_ecc_err : 1 ; /* [1] */ - unsigned int hydra_tx_ch2_2bit_ecc_err : 1 ; /* [2] */ - unsigned int phy_tx_retry_2bit_ecc_err : 1 ; /* [3] */ - unsigned int hydra_rx_ch0_2bit_ecc_err : 1 ; /* [4] */ - unsigned int hydra_rx_ch1_2bit_ecc_err : 1 ; /* [5] */ - unsigned int hydra_rx_ch2_2bit_ecc_err : 1 ; /* [6] */ - unsigned int reserved_0 : 1 ; /* [7] */ - unsigned int phy_rx_retry_ptr_err : 1 ; /* [8] */ - unsigned int phy_tx_retry_buf_ptr_err : 1 ; /* [9] */ - unsigned int phy_tx_retry_ptr_err : 1 ; /* [10] */ - unsigned int reserved_1 : 5 ; /* [15..11] */ - unsigned int hydra_tx_ch0_ovf : 1 ; /* [16] */ - unsigned int hydra_tx_ch1_ovf : 1 ; /* [17] */ - unsigned int hydra_tx_ch2_ovf : 1 ; /* [18] */ - unsigned int phy_tx_retry_buf_ovf : 1 ; /* [19] */ - unsigned int hydra_rx_ch0_ovf : 1 ; /* [20] */ - unsigned int hydra_rx_ch1_ovf : 1 ; /* [21] */ - unsigned int hydra_rx_ch2_ovf : 1 ; /* [22] */ - unsigned int reserved_2 : 1 ; /* [23] */ - unsigned int hydra_pcs_err0 : 1 ; /* [24] */ - unsigned int hydra_pcs_err1 : 1 ; /* [25] */ - unsigned int hydra_pcs_err2 : 1 ; /* [26] */ - unsigned int hydra_pcs_err3 : 1 ; /* [27] */ - unsigned int hydra_pcs_err4 : 1 ; /* [28] */ - unsigned int hydra_pcs_err5 : 1 ; /* [29] */ - unsigned int hydra_pcs_err6 : 1 ; /* [30] */ - unsigned int hydra_pcs_err7 : 1 ; /* [31] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} hllc_ras_u_err_misc1l; - -/* Define the union hllc_ras_u_err_misc1h */ -typedef union { - /* Define the struct bits */ - struct { - unsigned int hydra_tx_ch0_1bit_ecc_err : 1 ; /* [0] */ - unsigned int hydra_tx_ch1_1bit_ecc_err : 1 ; /* [1] */ - unsigned int hydra_tx_ch2_1bit_ecc_err : 1 ; /* [2] */ - unsigned int phy_tx_retry_1bit_ecc_err : 1 ; /* [3] */ - unsigned int hydra_rx_ch0_1bit_ecc_err : 1 ; /* [4] */ - unsigned int hydra_rx_ch1_1bit_ecc_err : 1 ; /* [5] */ - unsigned int hydra_rx_ch2_1bit_ecc_err : 1 ; /* [6] */ - unsigned int reserved_0 : 1 ; /* [7] */ - unsigned int phy_rx_flit_crc_err : 1 ; /* [8] */ - unsigned int reserved_1 : 23 ; /* [31..9] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} hllc_ras_u_err_misc1h; - -#endif /* __C_UNION_DEFINE_HLLC_RAS_H__ */ diff --git a/drivers/soc/hisilicon/sysctl/hllc_ras_reg_offset.h b/drivers/soc/hisilicon/sysctl/hllc_ras_reg_offset.h deleted file mode 100644 index efeba88129320..0000000000000 --- a/drivers/soc/hisilicon/sysctl/hllc_ras_reg_offset.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HLLC_RAS_REG_OFFSET_H__ -#define __HLLC_RAS_REG_OFFSET_H__ - -/* HLLC_RAS Base address of Module's Register */ -#define HLLC_HLLC_RAS_BASE (0x0) - -/******************************************************************************/ -/* xxx HLLC_RAS Registers' Definitions */ -/******************************************************************************/ -#define HLLC_HLLC_RAS_HLLC_ERR_FRL_REG (HLLC_HLLC_RAS_BASE + 0x2000) -#define HLLC_HLLC_RAS_HLLC_ERR_FRH_REG (HLLC_HLLC_RAS_BASE + 0x2004) -#define HLLC_HLLC_RAS_HLLC_ERR_CTRLL_REG (HLLC_HLLC_RAS_BASE + 0x2008) -#define HLLC_HLLC_RAS_HLLC_ERR_CTRLH_REG (HLLC_HLLC_RAS_BASE + 0x200C) -#define HLLC_HLLC_RAS_HLLC_ERR_STATUSL_REG (HLLC_HLLC_RAS_BASE + 0x2010) -#define HLLC_HLLC_RAS_HLLC_ERR_STATUSH_REG (HLLC_HLLC_RAS_BASE + 0x2014) -#define HLLC_HLLC_RAS_HLLC_ERR_ADDRL_REG (HLLC_HLLC_RAS_BASE + 0x2018) -#define HLLC_HLLC_RAS_HLLC_ERR_ADDRH_REG (HLLC_HLLC_RAS_BASE + 0x201C) -#define HLLC_HLLC_RAS_HLLC_ERR_MISC0L_REG (HLLC_HLLC_RAS_BASE + 0x2020) -#define HLLC_HLLC_RAS_HLLC_ERR_MISC0H_REG (HLLC_HLLC_RAS_BASE + 0x2024) -#define HLLC_HLLC_RAS_HLLC_ERR_MISC1L_REG (HLLC_HLLC_RAS_BASE + 0x2028) -#define HLLC_HLLC_RAS_HLLC_ERR_MISC1H_REG (HLLC_HLLC_RAS_BASE + 0x202C) - -#endif diff --git a/drivers/soc/hisilicon/sysctl/hllc_regs_c_union_define.h b/drivers/soc/hisilicon/sysctl/hllc_regs_c_union_define.h deleted file mode 100644 index 34ad887cf1e90..0000000000000 --- a/drivers/soc/hisilicon/sysctl/hllc_regs_c_union_define.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HLLC_REGS_C_UNION_DEFINE_H__ -#define __HLLC_REGS_C_UNION_DEFINE_H__ - -/* Define the union hllc_regs_u_inject_ecc_type */ -typedef union { - /* Define the struct bits */ - struct { - unsigned int inject_ecc_err_type : 2 ; /* [1..0] */ - unsigned int reserved_0 : 30 ; /* [31..2] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} hllc_regs_u_inject_ecc_type; - -/* Define the union hllc_regs_u_inject_ecc_en */ -typedef union { - /* Define the struct bits */ - struct { - unsigned int hydra_rx_inject_ecc_err_en : 3 ; /* [2..0] */ - unsigned int reserved_0 : 1 ; /* [3] */ - unsigned int phy_tx_retry_inject_ecc_err_en : 1 ; /* [4] */ - unsigned int reserved_1 : 3 ; /* [7..5] */ - unsigned int hydra_tx_inject_ecc_err_en : 3 ; /* [10..8] */ - unsigned int reserved_2 : 1 ; /* [11] */ - unsigned int reserved_3 : 20 ; /* [31..12] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} hllc_regs_u_inject_ecc_en; - -#endif /* __HLLC_REGS_C_UNION_DEFINE_H__ */ diff --git a/drivers/soc/hisilicon/sysctl/hllc_regs_reg_offset.h b/drivers/soc/hisilicon/sysctl/hllc_regs_reg_offset.h deleted file mode 100644 index 5208d6ae45f0b..0000000000000 --- a/drivers/soc/hisilicon/sysctl/hllc_regs_reg_offset.h +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HLLC_REGS_REG_OFFSET_H__ -#define __HLLC_REGS_REG_OFFSET_H__ - -/* HLLC_REGS Base address of Module's Register */ -#define HLLC_HLLC_REGS_BASE (0x0) - -/******************************************************************************/ -/* xxx HLLC_REGS Registers' Definitions */ -/******************************************************************************/ -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_AFULL_TH_CFG_REG (HLLC_HLLC_REGS_BASE + 0x0) -#define HLLC_HLLC_REGS_HLLC_TOKEN_CFG_REG (HLLC_HLLC_REGS_BASE + 0x100) -#define HLLC_HLLC_REGS_HLLC_RETRAINING_CFG0_REG (HLLC_HLLC_REGS_BASE + 0x300) -#define HLLC_HLLC_REGS_HLLC_RETRAINING_CFG1_REG (HLLC_HLLC_REGS_BASE + 0x304) -#define HLLC_HLLC_REGS_HLLC_RETRAINING_CFG2_REG (HLLC_HLLC_REGS_BASE + 0x308) -#define HLLC_HLLC_REGS_HLLC_PHY_RX_CRD_RET_CFG_REG (HLLC_HLLC_REGS_BASE + 0x400) -#define HLLC_HLLC_REGS_HLLC_SYS_MAGIC_WORD_REG (HLLC_HLLC_REGS_BASE + 0x7F0) -#define HLLC_HLLC_REGS_HLLC_INT0_SRC_REG (HLLC_HLLC_REGS_BASE + 0x800) -#define HLLC_HLLC_REGS_HLLC_INT0_MSK_REG (HLLC_HLLC_REGS_BASE + 0x804) -#define HLLC_HLLC_REGS_HLLC_INT0_ST_REG (HLLC_HLLC_REGS_BASE + 0x808) -#define HLLC_HLLC_REGS_HLLC_INT0_CLR_REG (HLLC_HLLC_REGS_BASE + 0x80C) -#define HLLC_HLLC_REGS_HLLC_INT1_SRC_REG (HLLC_HLLC_REGS_BASE + 0x810) -#define HLLC_HLLC_REGS_HLLC_INT1_MSK_REG (HLLC_HLLC_REGS_BASE + 0x814) -#define HLLC_HLLC_REGS_HLLC_INT1_ST_REG (HLLC_HLLC_REGS_BASE + 0x818) -#define HLLC_HLLC_REGS_HLLC_INT1_CLR_REG (HLLC_HLLC_REGS_BASE + 0x81C) -#define HLLC_HLLC_REGS_HLLC_ECO0_REG (HLLC_HLLC_REGS_BASE + 0xC00) -#define HLLC_HLLC_REGS_HLLC_ECO1_REG (HLLC_HLLC_REGS_BASE + 0xC04) -#define HLLC_HLLC_REGS_HLLC_ECO2_REG (HLLC_HLLC_REGS_BASE + 0xC08) -#define HLLC_HLLC_REGS_HLLC_ECO3_REG (HLLC_HLLC_REGS_BASE + 0xC0C) -#define HLLC_HLLC_REGS_HLLC_SYS_VERSION_REG (HLLC_HLLC_REGS_BASE + 0xC10) -#define HLLC_HLLC_REGS_HLLC_CNT_EN_REG (HLLC_HLLC_REGS_BASE + 0x1040) -#define HLLC_HLLC_REGS_HLLC_CNT_CLR_REG (HLLC_HLLC_REGS_BASE + 0x1044) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_BP_ST_REG (HLLC_HLLC_REGS_BASE + 0x1100) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_BP_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1140) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_BP_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1148) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_BP_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1150) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_BP_MAX_DURATION_REG (HLLC_HLLC_REGS_BASE + 0x1160) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_BP_MAX_DURATION_REG (HLLC_HLLC_REGS_BASE + 0x1168) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_BP_MAX_DURATION_REG (HLLC_HLLC_REGS_BASE + 0x1170) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_BUF_ST_REG (HLLC_HLLC_REGS_BASE + 0x1180) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x11C0) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x11C8) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x11D0) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_CRD_NUM_REG (HLLC_HLLC_REGS_BASE + 0x1200) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_BP_ST_REG (HLLC_HLLC_REGS_BASE + 0x1220) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_RMT_ACK_NUM_REG (HLLC_HLLC_REGS_BASE + 0x1240) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_ST_REG (HLLC_HLLC_REGS_BASE + 0x1280) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_BUF_ST_REG (HLLC_HLLC_REGS_BASE + 0x1284) -#define HLLC_HLLC_REGS_HLLC_LOC_PHY_TX_RETRY_WR_PTR_REG (HLLC_HLLC_REGS_BASE + 0x1290) -#define HLLC_HLLC_REGS_HLLC_RMT_PHY_RX_RETRY_REQ_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12A0) -#define HLLC_HLLC_REGS_HLLC_RMT_PHY_RX_RETRY_ACK_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12A8) -#define HLLC_HLLC_REGS_PHY_TX_CH0_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12C0) -#define HLLC_HLLC_REGS_PHY_TX_CH1_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12C8) -#define HLLC_HLLC_REGS_PHY_TX_CH2_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12D0) -#define HLLC_HLLC_REGS_PHY_TX_IDLE_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x12D8) -#define HLLC_HLLC_REGS_HLLC_RETRAINING_REQ_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1300) -#define HLLC_HLLC_REGS_HLLC_RETRAINING_ACK_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1308) -#define HLLC_HLLC_REGS_HLLC_PHY_RX_CRD_NUM_REG (HLLC_HLLC_REGS_BASE + 0x1400) -#define HLLC_HLLC_REGS_HLLC_PHY_RX_BP_ST_REG (HLLC_HLLC_REGS_BASE + 0x1420) -#define HLLC_HLLC_REGS_HLLC_PHY_RX_LOC_ACK_NUM_REG (HLLC_HLLC_REGS_BASE + 0x1440) -#define HLLC_HLLC_REGS_HLLC_PHY_RX_RETRY_ST_REG (HLLC_HLLC_REGS_BASE + 0x1480) -#define HLLC_HLLC_REGS_HLLC_LOC_PHY_RX_RETRY_RD_PTR_REG (HLLC_HLLC_REGS_BASE + 0x1490) -#define HLLC_HLLC_REGS_HLLC_LOC_PHY_RX_RETRY_REQ_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14A0) -#define HLLC_HLLC_REGS_HLLC_LOC_PHY_RX_RETRY_ACK_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14A8) -#define HLLC_HLLC_REGS_PHY_RX_CH0_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14C0) -#define HLLC_HLLC_REGS_PHY_RX_CH1_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14C8) -#define HLLC_HLLC_REGS_PHY_RX_CH2_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14D0) -#define HLLC_HLLC_REGS_PHY_RX_IDLE_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x14D8) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_BP_ST_REG (HLLC_HLLC_REGS_BASE + 0x1500) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_BUF_ST_REG (HLLC_HLLC_REGS_BASE + 0x1580) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH0_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x15C0) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH1_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x15C8) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH2_FLIT_CNT_REG (HLLC_HLLC_REGS_BASE + 0x15D0) -#define HLLC_HLLC_REGS_HLLC_INJECT_ECC_TYPE_REG (HLLC_HLLC_REGS_BASE + 0x1600) -#define HLLC_HLLC_REGS_HLLC_INJECT_ECC_EN_REG (HLLC_HLLC_REGS_BASE + 0x1604) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_2BIT_ECC_ERR_ADDR_REG (HLLC_HLLC_REGS_BASE + 0x1680) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1688) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1690) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x1698) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_2BIT_ECC_ERR_ADDR_REG (HLLC_HLLC_REGS_BASE + 0x16A0) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x16A8) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_2BIT_ECC_ERR_ADDR_REG (HLLC_HLLC_REGS_BASE + 0x16C0) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH0_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x16C8) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH1_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x16D0) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH2_1BIT_ECC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x16D8) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_INJECT_1BIT_CRC_ERR_EN_REG (HLLC_HLLC_REGS_BASE + 0x1700) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_INJECT_1BIT_CRC_ERR_TIMES_REG (HLLC_HLLC_REGS_BASE + 0x1704) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_INJECT_1BIT_CRC_ERR_DONE_REG (HLLC_HLLC_REGS_BASE + 0x1780) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_INJECT_1BIT_CRC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x17A0) -#define HLLC_HLLC_REGS_HLLC_PHY_RX_FLIT_CRC_ERR_CNT_REG (HLLC_HLLC_REGS_BASE + 0x17C0) -#define HLLC_HLLC_REGS_HLLC_PHY_RX_PERFORMANCE_TEST_EN_REG (HLLC_HLLC_REGS_BASE + 0x1800) -#define HLLC_HLLC_REGS_HLLC_PHY_RX_PERFORMANCE_TEST_PERIOD_REG (HLLC_HLLC_REGS_BASE + 0x1808) -#define HLLC_HLLC_REGS_HLLC_PHY_RX_PERFORMANCE_TEST_DONE_REG (HLLC_HLLC_REGS_BASE + 0x1880) -#define HLLC_HLLC_REGS_PHY_RX_CH0_FLIT_PERFORMANCE_CNT_REG (HLLC_HLLC_REGS_BASE + 0x18A0) -#define HLLC_HLLC_REGS_PHY_RX_CH1_FLIT_PERFORMANCE_CNT_REG (HLLC_HLLC_REGS_BASE + 0x18A8) -#define HLLC_HLLC_REGS_PHY_RX_CH2_FLIT_PERFORMANCE_CNT_REG (HLLC_HLLC_REGS_BASE + 0x18B0) -#define HLLC_HLLC_REGS_PHY_RX_IDLE_FLIT_PERFORMANCE_CNT_REG (HLLC_HLLC_REGS_BASE + 0x18B8) -#define HLLC_HLLC_REGS_PHY_RX_NULL_FLIT_PERFORMANCE_CNT_REG (HLLC_HLLC_REGS_BASE + 0x18C0) -#define HLLC_HLLC_REGS_HLLC_DEBUG_ECC_CFG_REG (HLLC_HLLC_REGS_BASE + 0x1900) -#define HLLC_HLLC_REGS_HLLC_DEBUG_CRC_CFG_REG (HLLC_HLLC_REGS_BASE + 0x1904) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x1980) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x1984) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x1988) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x1990) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH0_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x19A0) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH1_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x19A4) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH2_1BIT_ECC_ERR_CNT_TMP_REG (HLLC_HLLC_REGS_BASE + 0x19A8) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH0_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19C0) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH1_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19C4) -#define HLLC_HLLC_REGS_HLLC_HYDRA_RX_CH2_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19C8) -#define HLLC_HLLC_REGS_HLLC_PHY_TX_RETRY_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19D0) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH0_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19E0) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH1_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19E4) -#define HLLC_HLLC_REGS_HLLC_HYDRA_TX_CH2_1BIT_ECC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19E8) -#define HLLC_HLLC_REGS_HLLC_PHY_RX_FLIT_CRC_ERR_CNT_SNAPSHOT_REG (HLLC_HLLC_REGS_BASE + 0x19F0) - -#endif diff --git a/drivers/soc/hisilicon/sysctl/pa_c_union_define.h b/drivers/soc/hisilicon/sysctl/pa_c_union_define.h deleted file mode 100644 index b759c47033afd..0000000000000 --- a/drivers/soc/hisilicon/sysctl/pa_c_union_define.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __PA_C_UNION_DEFINE_H__ -#define __PA_C_UNION_DEFINE_H__ - -/* Define the union pa_u_global_cfg */ -typedef union { - /* Define the struct bits */ - struct { - unsigned int intlv_mode_cfg : 3 ; /* [2..0] */ - unsigned int nimbus_extend_en_cfg : 1 ; /* [3] */ - unsigned int rsv1 : 4 ; /* [7..4] */ - unsigned int wb_norely_en_cfg : 1 ; /* [8] */ - unsigned int rsv2 : 7 ; /* [15..9] */ - unsigned int hydra_port_en_cfg : 3 ; /* [18..16] */ - unsigned int rsv3 : 1 ; /* [19] */ - unsigned int ewa_dis_cfg : 1 ; /* [20] */ - unsigned int rsv4 : 3 ; /* [23..21] */ - unsigned int dvm_retry_en_cfg : 1 ; /* [24] */ - unsigned int rsv5 : 3 ; /* [27..25] */ - unsigned int compdata_err_poison_en : 1 ; /* [28] */ - unsigned int reg_goto_pcie_en_cfg : 1 ; /* [29] */ - unsigned int nc_lpid_seq_en_cfg : 1 ; /* [30] */ - unsigned int nc_non_order_en_cfg : 1 ; /* [31] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} pa_u_global_cfg; - -#endif /* __PA_C_UNION_DEFINE_H__ */ diff --git a/drivers/soc/hisilicon/sysctl/pa_reg_offset.h b/drivers/soc/hisilicon/sysctl/pa_reg_offset.h deleted file mode 100644 index 7ca0fdc31583d..0000000000000 --- a/drivers/soc/hisilicon/sysctl/pa_reg_offset.h +++ /dev/null @@ -1,204 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __PA_REG_OFFSET_H__ -#define __PA_REG_OFFSET_H__ - -/* PA Base address of Module's Register */ -#define PA_PA_BASE (0x0) - -/******************************************************************************/ -/* xxx PA Registers' Definitions */ -/******************************************************************************/ -#define PA_PA_ID_MAPPING_CFG_REG (PA_PA_BASE + 0x0) -#define PA_PA_GLOBAL_CFG_REG (PA_PA_BASE + 0x4) -#define PA_PA_LINK_DOWN_CFG_REG (PA_PA_BASE + 0x8) -#define PA_PA_HYDRA_PORT0_MISC_CFG0_REG (PA_PA_BASE + 0xC) -#define PA_PA_HYDRA_PORT1_MISC_CFG0_REG (PA_PA_BASE + 0x10) -#define PA_PA_HYDRA_PORT2_MISC_CFG0_REG (PA_PA_BASE + 0x14) -#define PA_PA_HYDRA_PORT0_MISC_CFG1_REG (PA_PA_BASE + 0x18) -#define PA_PA_HYDRA_PORT1_MISC_CFG1_REG (PA_PA_BASE + 0x1C) -#define PA_PA_HYDRA_PORT2_MISC_CFG1_REG (PA_PA_BASE + 0x20) -#define PA_PA_TX_HALT_CFG_REG (PA_PA_BASE + 0x24) -#define PA_PA_RX_REQHALT_CFG_REG (PA_PA_BASE + 0x28) -#define PA_PA_RX_SNPHALT_CFG_REG (PA_PA_BASE + 0x2C) -#define PA_PA_RX_RSPHALT_CFG_REG (PA_PA_BASE + 0x30) -#define PA_PA_RX_DATHALT_CFG_REG (PA_PA_BASE + 0x34) -#define PA_PA_MEM_ECC_CORRECT_CFG_REG (PA_PA_BASE + 0x38) -#define PA_PA_DAW_BYP_TGTID_CFG_REG (PA_PA_BASE + 0x3C) -#define PA_PA_DDR_UTL_UPDATE_PERIOD_CFG_REG (PA_PA_BASE + 0x40) -#define PA_PA_STREAM_WRITE_SRCID0_CFG_REG (PA_PA_BASE + 0x44) -#define PA_PA_STREAM_WRITE_SRCID1_CFG_REG (PA_PA_BASE + 0x48) -#define PA_PA_COPYBACK_BP_TH_CFG_REG (PA_PA_BASE + 0x4C) -#define PA_PA_EXTEND_DEFAULT_SLV_TGTID_CFG_REG (PA_PA_BASE + 0x50) -#define PA_PA_IO_PERF_OPT_SRCID_CFG_REG (PA_PA_BASE + 0x54) -#define PA_PA_IO_PER_OPT_CTRL_CFG_REG (PA_PA_BASE + 0x58) -#define PA_PA_PREFETCH_TGT_CFG_REG (PA_PA_BASE + 0x5C) -#define PA_PA_ECO_RSV_REG1_REG (PA_PA_BASE + 0x60) -#define PA_PA_EMU_VERSION_REG_REG (PA_PA_BASE + 0x64) -#define PA_PA_FPGA_VERSION_REG_REG (PA_PA_BASE + 0x68) -#define PA_PA_INTMASK_REG (PA_PA_BASE + 0x70) -#define PA_PA_RAWINT_REG (PA_PA_BASE + 0x74) -#define PA_PA_INTSTS_REG (PA_PA_BASE + 0x78) -#define PA_PA_INTCLR_REG (PA_PA_BASE + 0x7C) -#define PA_PA_H0_TX_REQ_CURR_CNT_REG (PA_PA_BASE + 0x400) -#define PA_PA_H0_TX_CA_REQ_CURR_CNT_REG (PA_PA_BASE + 0x404) -#define PA_PA_H0_TX_NC_REQ_CURR_CNT_REG (PA_PA_BASE + 0x408) -#define PA_PA_H0_TX_P2P_CURR_CNT_REG (PA_PA_BASE + 0x40C) -#define PA_PA_H0_TX_FWD_CURR_CNT_REG (PA_PA_BASE + 0x410) -#define PA_PA_H1_TX_REQ_CURR_CNT_REG (PA_PA_BASE + 0x420) -#define PA_PA_H1_TX_CA_REQ_CURR_CNT_REG (PA_PA_BASE + 0x424) -#define PA_PA_H1_TX_NC_REQ_CURR_CNT_REG (PA_PA_BASE + 0x428) -#define PA_PA_H1_TX_P2P_CURR_CNT_REG (PA_PA_BASE + 0x42C) -#define PA_PA_H1_TX_FWD_CURR_CNT_REG (PA_PA_BASE + 0x430) -#define PA_PA_H2_TX_REQ_CURR_CNT_REG (PA_PA_BASE + 0x440) -#define PA_PA_H2_TX_CA_REQ_CURR_CNT_REG (PA_PA_BASE + 0x444) -#define PA_PA_H2_TX_NC_REQ_CURR_CNT_REG (PA_PA_BASE + 0x448) -#define PA_PA_H2_TX_P2P_CURR_CNT_REG (PA_PA_BASE + 0x44C) -#define PA_PA_H2_TX_FWD_CURR_CNT_REG (PA_PA_BASE + 0x450) -#define PA_PA_TX_REQ_CNT_REG (PA_PA_BASE + 0x460) -#define PA_PA_TX_SNP_CNT_REG (PA_PA_BASE + 0x464) -#define PA_PA_TX_RSP_CNT_REG (PA_PA_BASE + 0x468) -#define PA_PA_TX_DAT_CNT_REG (PA_PA_BASE + 0x46C) -#define PA_PA_TX_CA_RETRYACK_CNT_REG (PA_PA_BASE + 0x470) -#define PA_PA_TX_NC_RETRYACK_CNT_REG (PA_PA_BASE + 0x474) -#define PA_PA_TX_P2P_RETRYACK_CNT_REG (PA_PA_BASE + 0x478) -#define PA_PA_TX_CA_PGNT_CNT_REG (PA_PA_BASE + 0x47C) -#define PA_PA_TX_NC_PGNT_CNT_REG (PA_PA_BASE + 0x480) -#define PA_PA_TX_P2P_PGNT_CNT_REG (PA_PA_BASE + 0x484) -#define PA_PA_TX_PCRDRETURN_CNT_REG (PA_PA_BASE + 0x488) -#define PA_PA_TX_MEM_ERR_CNT_REG (PA_PA_BASE + 0x48C) -#define PA_PA_TX_MEM_ERR_HIS_ST_REG (PA_PA_BASE + 0x490) -#define PA_PA_TX_HYDRA_BP_HIS_ST_REG (PA_PA_BASE + 0x494) -#define PA_PA_TX_BUFF_HALT_HIS_ST_REG (PA_PA_BASE + 0x498) -#define PA_PA_TX_BUFF_FIFO_ST_REG (PA_PA_BASE + 0x49C) -#define PA_PA_H0_TX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x4A0) -#define PA_PA_H1_TX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x4A4) -#define PA_PA_H2_TX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x4A8) -#define PA_PA_H0_TX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x4AC) -#define PA_PA_H1_TX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x4B0) -#define PA_PA_H2_TX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x4B4) -#define PA_PA_H0_TX_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x4B8) -#define PA_PA_H1_TX_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x4BC) -#define PA_PA_H2_TX_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x4C0) -#define PA_PA_H0_TX_RSP_ERR_INFO_REG (PA_PA_BASE + 0x4C4) -#define PA_PA_H1_TX_RSP_ERR_INFO_REG (PA_PA_BASE + 0x4C8) -#define PA_PA_H2_TX_RSP_ERR_INFO_REG (PA_PA_BASE + 0x4CC) -#define PA_PA_TX_BUFF_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x4D0) -#define PA_PA_H0_TX_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x4D4) -#define PA_PA_H1_TX_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x4D8) -#define PA_PA_H2_TX_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x4DC) -#define PA_PA_H0_TX_REQ_ERR_INFO_REG (PA_PA_BASE + 0x4E0) -#define PA_PA_H1_TX_REQ_ERR_INFO_REG (PA_PA_BASE + 0x4E4) -#define PA_PA_H2_TX_REQ_ERR_INFO_REG (PA_PA_BASE + 0x4E8) -#define PA_PA_H0_RX_REQ_WDATA_BUFF_CNT_REG (PA_PA_BASE + 0x500) -#define PA_PA_H0_RX_REQ_CA_CURR_CNT_REG (PA_PA_BASE + 0x504) -#define PA_PA_H0_RX_REQ_SW_CURR_CNT_REG (PA_PA_BASE + 0x508) -#define PA_PA_H0_RX_REQ_CA_ADDR_CNT_REG (PA_PA_BASE + 0x50C) -#define PA_PA_H0_RX_REQ_NC_CURR_CNT_REG (PA_PA_BASE + 0x510) -#define PA_PA_H0_RX_REQ_NCFWD_CURR_CNT_REG (PA_PA_BASE + 0x514) -#define PA_PA_H0_RX_SNP_CURR_CNT_REG (PA_PA_BASE + 0x518) -#define PA_PA_H0_RX_COMPDBID_CURR_CNT_REG (PA_PA_BASE + 0x51C) -#define PA_PA_H0_RX_SNPRSP_BUFF_CNT_REG (PA_PA_BASE + 0x520) -#define PA_PA_H0_RX_REQ_RETRY_ACK_CNT_REG (PA_PA_BASE + 0x524) -#define PA_PA_H0_RX_REQ_PGNT_CNT_REG (PA_PA_BASE + 0x528) -#define PA_PA_H0_RX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x52C) -#define PA_PA_H0_RX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x530) -#define PA_PA_H0_RX_REQ_DAW_ERR_INFO_REG (PA_PA_BASE + 0x534) -#define PA_PA_H0_RX_REQ_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x538) -#define PA_PA_H0_RX_SNPRSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x53C) -#define PA_PA_H0_RX_SNP_RSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x540) -#define PA_PA_H0_RX_STREAM_WR_BUFF_CNT_REG (PA_PA_BASE + 0x544) -#define PA_PA_H0_RX_BUFF_OF_HIS_ST_REG (PA_PA_BASE + 0x548) -#define PA_PA_H1_RX_REQ_WDATA_BUFF_CNT_REG (PA_PA_BASE + 0x600) -#define PA_PA_H1_RX_REQ_CA_CURR_CNT_REG (PA_PA_BASE + 0x604) -#define PA_PA_H1_RX_REQ_SW_CURR_CNT_REG (PA_PA_BASE + 0x608) -#define PA_PA_H1_RX_REQ_CA_ADDR_CNT_REG (PA_PA_BASE + 0x60C) -#define PA_PA_H1_RX_REQ_NC_CURR_CNT_REG (PA_PA_BASE + 0x610) -#define PA_PA_H1_RX_REQ_NCFWD_CURR_CNT_REG (PA_PA_BASE + 0x614) -#define PA_PA_H1_RX_SNP_CURR_CNT_REG (PA_PA_BASE + 0x618) -#define PA_PA_H1_RX_COMPDBID_CURR_CNT_REG (PA_PA_BASE + 0x61C) -#define PA_PA_H1_RX_SNPRSP_BUFF_CNT_REG (PA_PA_BASE + 0x620) -#define PA_PA_H1_RX_REQ_RETRY_ACK_CNT_REG (PA_PA_BASE + 0x624) -#define PA_PA_H1_RX_REQ_PGNT_CNT_REG (PA_PA_BASE + 0x628) -#define PA_PA_H1_RX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x62C) -#define PA_PA_H1_RX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x630) -#define PA_PA_H1_RX_REQ_DAW_ERR_INFO_REG (PA_PA_BASE + 0x634) -#define PA_PA_H1_RX_REQ_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x638) -#define PA_PA_H1_RX_SNPRSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x63C) -#define PA_PA_H1_RX_SNP_RSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x640) -#define PA_PA_H1_RX_STREAM_WR_BUFF_CNT_REG (PA_PA_BASE + 0x644) -#define PA_PA_H1_RX_BUFF_OF_HIS_ST_REG (PA_PA_BASE + 0x648) -#define PA_PA_H2_RX_REQ_WDATA_BUFF_CNT_REG (PA_PA_BASE + 0x700) -#define PA_PA_H2_RX_REQ_CA_CURR_CNT_REG (PA_PA_BASE + 0x704) -#define PA_PA_H2_RX_REQ_SW_CURR_CNT_REG (PA_PA_BASE + 0x708) -#define PA_PA_H2_RX_REQ_CA_ADDR_CNT_REG (PA_PA_BASE + 0x70C) -#define PA_PA_H2_RX_REQ_NC_CURR_CNT_REG (PA_PA_BASE + 0x710) -#define PA_PA_H2_RX_REQ_NCFWD_CURR_CNT_REG (PA_PA_BASE + 0x714) -#define PA_PA_H2_RX_SNP_CURR_CNT_REG (PA_PA_BASE + 0x718) -#define PA_PA_H2_RX_COMPDBID_CURR_CNT_REG (PA_PA_BASE + 0x71C) -#define PA_PA_H2_RX_SNPRSP_BUFF_CNT_REG (PA_PA_BASE + 0x720) -#define PA_PA_H2_RX_REQ_RETRY_ACK_CNT_REG (PA_PA_BASE + 0x724) -#define PA_PA_H2_RX_REQ_PGNT_CNT_REG (PA_PA_BASE + 0x728) -#define PA_PA_H2_RX_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x72C) -#define PA_PA_H2_RX_FIFO_FULL_ST_REG (PA_PA_BASE + 0x730) -#define PA_PA_H2_RX_REQ_DAW_ERR_INFO_REG (PA_PA_BASE + 0x734) -#define PA_PA_H2_RX_REQ_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x738) -#define PA_PA_H2_RX_SNPRSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x73C) -#define PA_PA_H2_RX_SNP_RSP_MEM_ERR_ADDR_REG (PA_PA_BASE + 0x740) -#define PA_PA_H2_RX_STREAM_WR_BUFF_CNT_REG (PA_PA_BASE + 0x744) -#define PA_PA_H2_RX_BUFF_OF_HIS_ST_REG (PA_PA_BASE + 0x748) -#define PA_PA_RX_REQ_CNT_REG (PA_PA_BASE + 0x800) -#define PA_PA_RX_SNP_CNT_REG (PA_PA_BASE + 0x804) -#define PA_PA_RX_RSP_CNT_REG (PA_PA_BASE + 0x808) -#define PA_PA_RX_DAT_CNT_REG (PA_PA_BASE + 0x80C) -#define PA_PA_RX_RETINFO_SCH_FIFO_EMPTY_ST_REG (PA_PA_BASE + 0x810) -#define PA_PA_RX_RETINFO_SCH_FIFO_FULL_ST_REG (PA_PA_BASE + 0x814) -#define PA_PA_RX_REQ_SCH_FIFO_ST_REG (PA_PA_BASE + 0x818) -#define PA_PA_RX_SNP_SCH_FIFO_ST_REG (PA_PA_BASE + 0x81C) -#define PA_PA_RX_RSP_SCH_FIFO_ST_REG (PA_PA_BASE + 0x820) -#define PA_PA_RX_DAT_SCH_FIFO_ST_REG (PA_PA_BASE + 0x824) -#define PA_PA_RX_MEM_ECC_1BIT_ERR_HIS_ST_REG (PA_PA_BASE + 0x828) -#define PA_PA_RX_MEM_ECC_2BIT_ERR_HIS_ST_REG (PA_PA_BASE + 0x82C) -#define PA_PA_RX_MEM_ERR_CNT_REG (PA_PA_BASE + 0x830) -#define PA_PA_RX_SKY_LINK_BP_ST_REG (PA_PA_BASE + 0x834) -#define PA_PA_RX_SKY_LINK_BP_HIS_ST_REG (PA_PA_BASE + 0x838) -#define PA_PA_RX_BUFF_HALT_HIS_ST_REG (PA_PA_BASE + 0x83C) -#define PA_PA_RX_SCH_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x840) -#define PA_PA_RX_RETINFO_FIFO_OF_HIS_ST_REG (PA_PA_BASE + 0x844) -#define PA_PA_MEM_ERR_INJECT_CFG_REG (PA_PA_BASE + 0x850) -#define PA_PA_DID_HHA_ID_CFG0_REG (PA_PA_BASE + 0x860) -#define PA_PA_DID_HHA_ID_CFG1_REG (PA_PA_BASE + 0x864) -#define PA_PA_DID_HHA_ID_CFG2_REG (PA_PA_BASE + 0x868) -#define PA_PA_DID_HHA_ID_CFG3_REG (PA_PA_BASE + 0x86C) -#define PA_PA_DID_L3T_ID_CFG_REG (PA_PA_BASE + 0x870) -#define PA_PA_DID_DEFAULT_SLV_ID_CFG_REG (PA_PA_BASE + 0x874) -#define PA_PA_CER_IDR_REG (PA_PA_BASE + 0xC10) -#define PA_PA_CER_IDR_MODIFY_EN_REG (PA_PA_BASE + 0xC14) -#define PA_PA_ERR_FRL_REG (PA_PA_BASE + 0x2000) -#define PA_PA_ERR_FRH_REG (PA_PA_BASE + 0x2004) -#define PA_PA_ERR_CTRLL_REG (PA_PA_BASE + 0x2008) -#define PA_PA_ERR_CTRLH_REG (PA_PA_BASE + 0x200C) -#define PA_PA_ERR_STATUSL_REG (PA_PA_BASE + 0x2010) -#define PA_PA_ERR_STATUSH_REG (PA_PA_BASE + 0x2014) -#define PA_PA_ERR_ADDRL_REG (PA_PA_BASE + 0x2018) -#define PA_PA_ERR_ADDRH_REG (PA_PA_BASE + 0x201C) -#define PA_PA_ERR_MISC0L_REG (PA_PA_BASE + 0x2020) -#define PA_PA_ERR_MISC0H_REG (PA_PA_BASE + 0x2024) -#define PA_PA_ERR_MISC1L_REG (PA_PA_BASE + 0x2028) -#define PA_PA_ERR_MISC1H_REG (PA_PA_BASE + 0x202C) - -#endif diff --git a/drivers/soc/hisilicon/sysctl/rasc_c_union_define.h b/drivers/soc/hisilicon/sysctl/rasc_c_union_define.h deleted file mode 100644 index d4013df759dbf..0000000000000 --- a/drivers/soc/hisilicon/sysctl/rasc_c_union_define.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __RASC_C_UNION_DEFINE_H__ -#define __RASC_C_UNION_DEFINE_H__ - -/* Define the union ddrc_rasc_u_cfg_clr */ -typedef union { - /* Define the struct bits */ - struct { - unsigned int all_errcnt_clr : 1 ; /* [0] */ - unsigned int ha_errcnt_clr : 1 ; /* [1] */ - unsigned int vls_errcnt_clr : 1 ; /* [2] */ - unsigned int rvls_errcnt_clr : 1 ; /* [3] */ - unsigned int pa_errcnt_clr : 1 ; /* [4] */ - unsigned int sp_errcnt_clr : 1 ; /* [5] */ - unsigned int sp_rberrcnt_clr : 1 ; /* [6] */ - unsigned int reserved_0 : 1 ; /* [7] */ - unsigned int corr_errcnt_clr : 1 ; /* [8] */ - unsigned int uncorr_errcnt_clr : 1 ; /* [9] */ - unsigned int reserved_1 : 22 ; /* [31..10] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} ddrc_rasc_u_cfg_clr; - -/* Define the union ddrc_rasc_u_cfg_info_rnk */ -typedef union { - /* Define the struct bits */ - struct { - unsigned int idx_rnk : 4 ; /* [3..0] */ - unsigned int rnk_sel_mode : 1 ; /* [4] */ - unsigned int reserved_0 : 27 ; /* [31..5] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} ddrc_rasc_u_cfg_info_rnk; - -/* Define the union ddrc_rasc_u_his_ha_rankcnt_inf */ -typedef union { - /* Define the struct bits */ - struct { - unsigned int ha_rnk_funnel_corr_cnt : 16 ; /* [15..0] */ - unsigned int ha_rnk_corr_cnt : 16 ; /* [31..16] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} ddrc_rasc_u_his_ha_rankcnt_inf; - -#endif /* __RASC_C_UNION_DEFINE_H__ */ diff --git a/drivers/soc/hisilicon/sysctl/rasc_reg_offset.h b/drivers/soc/hisilicon/sysctl/rasc_reg_offset.h deleted file mode 100644 index b65da72b85f21..0000000000000 --- a/drivers/soc/hisilicon/sysctl/rasc_reg_offset.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __RASC_REG_OFFSET_H__ -#define __RASC_REG_OFFSET_H__ - -/* RASC Base address of Module's Register */ -#define DDRC_RASC_BASE (0x1800) - -/******************************************************************************/ -/* xxx RASC Registers' Definitions */ -/******************************************************************************/ -#define DDRC_RASC_RASC_CTRL_MODE_REG (DDRC_RASC_BASE + 0x0) -#define DDRC_RASC_RASC_CTRL_ADDDC_REG (DDRC_RASC_BASE + 0x4) -#define DDRC_RASC_RASC_CTRL_PASCRUB_REG (DDRC_RASC_BASE + 0x8) -#define DDRC_RASC_RASC_CTRL_SPARING_REG (DDRC_RASC_BASE + 0xC) -#define DDRC_RASC_RASC_CTRL_FLUSH_REG (DDRC_RASC_BASE + 0x10) -#define DDRC_RASC_RASC_CTRL_ERRINJ_REG (DDRC_RASC_BASE + 0x14) -#define DDRC_RASC_RASC_CTRL_FUNNEL_REG (DDRC_RASC_BASE + 0x18) -#define DDRC_RASC_RASC_CFG_MODE_REG (DDRC_RASC_BASE + 0x20) -#define DDRC_RASC_RASC_CFG_RANKMAP_REG (DDRC_RASC_BASE + 0x30) -#define DDRC_RASC_RASC_CFG_CLR_REG (DDRC_RASC_BASE + 0x54) -#define DDRC_RASC_RASC_CFG_INFO_RNK_REG (DDRC_RASC_BASE + 0x58) -#define DDRC_RASC_RASC_CFG_INFO_DEVIDX_REG (DDRC_RASC_BASE + 0x5C) -#define DDRC_RASC_RASC_CFG_INFO_BNKIDX_REG (DDRC_RASC_BASE + 0x60) -#define DDRC_RASC_RASC_CFG_PASTART_REG (DDRC_RASC_BASE + 0x70) -#define DDRC_RASC_RASC_CFG_PAEND_REG (DDRC_RASC_BASE + 0x80) -#define DDRC_RASC_RASC_CFG_PS_REG (DDRC_RASC_BASE + 0x90) -#define DDRC_RASC_RASC_CFG_ADDDC_REGION0_REG (DDRC_RASC_BASE + 0xA0) -#define DDRC_RASC_RASC_CFG_ADDDC_REGION1_REG (DDRC_RASC_BASE + 0xA4) -#define DDRC_RASC_RASC_CFG_ADDDC_RVLS_REG (DDRC_RASC_BASE + 0xA8) -#define DDRC_RASC_RASC_CFG_VLS_INTERVAL_REG (DDRC_RASC_BASE + 0xAC) -#define DDRC_RASC_RASC_CFG_VLS_X8_REG (DDRC_RASC_BASE + 0xB0) -#define DDRC_RASC_RASC_CFG_SP_REG (DDRC_RASC_BASE + 0xC0) -#define DDRC_RASC_RASC_CFG_SPR_INTERVAL_REG (DDRC_RASC_BASE + 0xC4) -#define DDRC_RASC_RASC_CFG_SPR_OUTSTANDING_REG (DDRC_RASC_BASE + 0xC8) -#define DDRC_RASC_RASC_CFG_CE_LVL_REG (DDRC_RASC_BASE + 0xD4) -#define DDRC_RASC_RASC_CFG_FUNNEL_BASE_REG (DDRC_RASC_BASE + 0xE0) -#define DDRC_RASC_RASC_CFG_FUNNEL_TH_REG (DDRC_RASC_BASE + 0xE4) -#define DDRC_RASC_RASC_CFG_ERRINJMODE_REG (DDRC_RASC_BASE + 0xF0) -#define DDRC_RASC_RASC_CFG_ERRINJ_ADDR_L_REG (DDRC_RASC_BASE + 0xF4) -#define DDRC_RASC_RASC_CFG_ERRINJ_ADDR_H_REG (DDRC_RASC_BASE + 0xF8) -#define DDRC_RASC_RASC_CFG_ERRINJ_ADDRMSK_L_REG (DDRC_RASC_BASE + 0xFC) -#define DDRC_RASC_RASC_CFG_ERRINJ_ADDRMSK_H_REG (DDRC_RASC_BASE + 0x100) -#define DDRC_RASC_RASC_CFG_ERR_BUF_SEL_REG (DDRC_RASC_BASE + 0x104) -#define DDRC_RASC_RASC_CFG_ERRINJ_DMSK_REG (DDRC_RASC_BASE + 0x110) -#define DDRC_RASC_RASC_CFG_POISON_REG (DDRC_RASC_BASE + 0x140) -#define DDRC_RASC_RASC_CFG_RAM_ERRINJ_REG (DDRC_RASC_BASE + 0x150) -#define DDRC_RASC_RASC_CFG_RAM_TMOD_REG (DDRC_RASC_BASE + 0x154) -#define DDRC_RASC_RASC_CFG_CORR_TH_REG (DDRC_RASC_BASE + 0x160) -#define DDRC_RASC_RASC_CFG_RH_REG (DDRC_RASC_BASE + 0x164) -#define DDRC_RASC_RASC_CFG_RH_ADJA_OP_REG (DDRC_RASC_BASE + 0x168) -#define DDRC_RASC_RASC_CFG_RH_ADJA_UP_LV1_REG (DDRC_RASC_BASE + 0x16C) -#define DDRC_RASC_RASC_CFG_RH_ADJA_UP_LV2_REG (DDRC_RASC_BASE + 0x170) -#define DDRC_RASC_RASC_CFG_RH_ADJA_UP_LV3_REG (DDRC_RASC_BASE + 0x174) -#define DDRC_RASC_RASC_CFG_RH_ADJA_UP_LV4_REG (DDRC_RASC_BASE + 0x178) -#define DDRC_RASC_RASC_CFG_RH_ADJA_DOWN_LV1_REG (DDRC_RASC_BASE + 0x17C) -#define DDRC_RASC_RASC_CFG_RH_ADJA_DOWN_LV2_REG (DDRC_RASC_BASE + 0x180) -#define DDRC_RASC_RASC_CFG_RH_ADJA_DOWN_LV3_REG (DDRC_RASC_BASE + 0x184) -#define DDRC_RASC_RASC_CFG_RH_ADJA_DOWN_LV4_REG (DDRC_RASC_BASE + 0x188) -#define DDRC_RASC_RASC_CFG_RH_SCRAM_UP_REG (DDRC_RASC_BASE + 0x18C) -#define DDRC_RASC_RASC_CFG_RH_SCRAM_DOWN_REG (DDRC_RASC_BASE + 0x190) -#define DDRC_RASC_RASC_CFG_RH_SCRAM_MSK_LV1_REG (DDRC_RASC_BASE + 0x194) -#define DDRC_RASC_RASC_CFG_RH_SCRAM_MSK_LV2_REG (DDRC_RASC_BASE + 0x198) -#define DDRC_RASC_RASC_CFG_RH_SCRAM_MSK_LV3_REG (DDRC_RASC_BASE + 0x19C) -#define DDRC_RASC_RASC_CFG_RH_SCRAM_MSK_LV4_REG (DDRC_RASC_BASE + 0x1A0) -#define DDRC_RASC_RASC_CFG_RH_TCAL_REG (DDRC_RASC_BASE + 0x1A4) -#define DDRC_RASC_RASC_CFG_RES0_REG (DDRC_RASC_BASE + 0x1F0) -#define DDRC_RASC_RASC_CFG_RES1_REG (DDRC_RASC_BASE + 0x1F4) -#define DDRC_RASC_RASC_CFG_RES2_REG (DDRC_RASC_BASE + 0x1F8) -#define DDRC_RASC_RASC_CFG_RES3_REG (DDRC_RASC_BASE + 0x1FC) -#define DDRC_RASC_RASC_INTMSK_REG (DDRC_RASC_BASE + 0x200) -#define DDRC_RASC_RASC_RINT_REG (DDRC_RASC_BASE + 0x204) -#define DDRC_RASC_RASC_INTSTS_REG (DDRC_RASC_BASE + 0x208) -#define DDRC_RASC_RASC_CURR_STATUS_REG (DDRC_RASC_BASE + 0x220) -#define DDRC_RASC_RASC_CURR_ERRSTATUS_REG (DDRC_RASC_BASE + 0x224) -#define DDRC_RASC_RASC_CURR_SPRNK_STA_REG (DDRC_RASC_BASE + 0x228) -#define DDRC_RASC_RASC_CURR_SPDEV_STA_REG (DDRC_RASC_BASE + 0x22C) -#define DDRC_RASC_RASC_CURR_SPDEV_DEV1_REG (DDRC_RASC_BASE + 0x230) -#define DDRC_RASC_RASC_CURR_CMD_CNT_REG (DDRC_RASC_BASE + 0x234) -#define DDRC_RASC_RASC_CURR_ADDDC_STA_REG (DDRC_RASC_BASE + 0x238) -#define DDRC_RASC_RASC_HIS_UNCORR_CNT_REG (DDRC_RASC_BASE + 0x240) -#define DDRC_RASC_RASC_HIS_CORR_CNT_REG (DDRC_RASC_BASE + 0x244) -#define DDRC_RASC_RASC_HIS_HAERR_CNT_REG (DDRC_RASC_BASE + 0x250) -#define DDRC_RASC_RASC_HIS_PAERR_CNT_REG (DDRC_RASC_BASE + 0x258) -#define DDRC_RASC_RASC_HIS_SPERR_CNT_REG (DDRC_RASC_BASE + 0x25C) -#define DDRC_RASC_RASC_HIS_SPRBERR_CNT_REG (DDRC_RASC_BASE + 0x260) -#define DDRC_RASC_RASC_HIS_VLSERR_CNT_REG (DDRC_RASC_BASE + 0x264) -#define DDRC_RASC_RASC_HIS_RVLSERR_CNT_REG (DDRC_RASC_BASE + 0x268) -#define DDRC_RASC_RASC_HIS_RANKCNT_INF_REG (DDRC_RASC_BASE + 0x280) -#define DDRC_RASC_RASC_HIS_HA_RANKCNT_INF_REG (DDRC_RASC_BASE + 0x284) -#define DDRC_RASC_RASC_HIS_RANK_ERR_REG (DDRC_RASC_BASE + 0x28C) -#define DDRC_RASC_RASC_HIS_OFFSET_ERR_REG (DDRC_RASC_BASE + 0x290) -#define DDRC_RASC_RASC_HIS_SEG_ERR_REG (DDRC_RASC_BASE + 0x2A0) -#define DDRC_RASC_RASC_HIS_WORST_DEV_REG (DDRC_RASC_BASE + 0x2D4) -#define DDRC_RASC_RASC_HIS_WORST_BNK_REG (DDRC_RASC_BASE + 0x2D8) -#define DDRC_RASC_RASC_HIS_RCDTYP_REG (DDRC_RASC_BASE + 0x300) -#define DDRC_RASC_RASC_HIS_UNCORR_ADDR_L_REG (DDRC_RASC_BASE + 0x310) -#define DDRC_RASC_RASC_HIS_UNCORR_ADDR_H_REG (DDRC_RASC_BASE + 0x314) -#define DDRC_RASC_RASC_HIS_UNCORR_RDATA_REG (DDRC_RASC_BASE + 0x320) -#define DDRC_RASC_RASC_HIS_UNCORR_RDATA_CWH_REG (DDRC_RASC_BASE + 0x350) -#define DDRC_RASC_RASC_HIS_CORR_ADDR_L_REG (DDRC_RASC_BASE + 0x380) -#define DDRC_RASC_RASC_HIS_CORR_ADDR_H_REG (DDRC_RASC_BASE + 0x384) -#define DDRC_RASC_RASC_HIS_CORR_RDATA_REG (DDRC_RASC_BASE + 0x390) -#define DDRC_RASC_RASC_HIS_CORR_RDATA_CWH_REG (DDRC_RASC_BASE + 0x3C0) -#define DDRC_RASC_RASC_HIS_CORR_EXPDATA_REG (DDRC_RASC_BASE + 0x400) -#define DDRC_RASC_RASC_HIS_CORR_EXPDATA_CWH_REG (DDRC_RASC_BASE + 0x430) -#define DDRC_RASC_RASC_HIS_ERRINJ_CNT_REG (DDRC_RASC_BASE + 0x460) - -#endif diff --git a/drivers/soc/hisilicon/sysctl/sysctl_dfx.c b/drivers/soc/hisilicon/sysctl/sysctl_dfx.c deleted file mode 100644 index 7bcff53e9e142..0000000000000 --- a/drivers/soc/hisilicon/sysctl/sysctl_dfx.c +++ /dev/null @@ -1,378 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/proc_fs.h> -#include <linux/cper.h> -#include <linux/mutex.h> -#include <linux/uaccess.h> -#include <linux/stat.h> -#include <acpi/ghes.h> -#include <uapi/linux/uuid.h> -#include "sysctl_local_ras.h" - -enum { - /* ARM */ - RAS_MODULE_CPU_CORE, - /* OEM1 */ - RAS_MODULE_PLL, - RAS_MODULE_SLLC, - RAS_MODULE_SIOE, - RAS_MODULE_POE, - RAS_MODULE_DISPATCH, - RAS_MODULE_TDH, - RAS_MODULE_GIC, - RAS_MODULE_RDE, - RAS_MODULE_SAS, - RAS_MODULE_SATA, - RAS_MODULE_USB, - /* OEM2 */ - RAS_MODULE_SMMU, - RAS_MODULE_HHA, - RAS_MODULE_PA, - RAS_MODULE_HLLC, - RAS_MODULE_DDRC, - /* PCIE LOCAL */ - RAS_MODULE_PCIE_AP, - RAS_MODULE_PCIE_DL, - RAS_MODULE_PCIE_MAC, - RAS_MODULE_PCIE_SDI_LOCAL, - RAS_MODULE_PCIE_TL, - /* HPRE */ - RAS_MODULE_ZIP, - RAS_MODULE_SEC, - RAS_MODULE_HPRE, - /* NET */ - RAS_MODULE_NET_GE, - RAS_MODULE_NET_25GE, - RAS_MODULE_NET_25GE_RDMA, - RAS_MODULE_NET_50GE_RDMA, - RAS_MODULE_NET_100G_RDMA, - RAS_MODULE_NET_SDI, - RAS_MODULE_NET_100G_VF, - RAS_MODULE_NET_100G_RDMA_VF, - RAS_MODULE_MAX, -}; - -enum { - SYSCTL_IOCTL_GET_RAS = 0, -}; - -#define SYSCTL_PROC "hisi_sysctl" - -#define SYSCTRL_DFX_DBG_LEVEL 0 -#if SYSCTRL_DFX_DBG_LEVEL -#define SYSCTRL_DFX_DBG(fmt...) printk(fmt) -#else -#define SYSCTRL_DFX_DBG(fmt...) -#endif - -struct ras_node { - u32 cnt; -}; - -struct ras_handle { - guid_t gid; - void (*proc)(const void *err); -}; - -static DEFINE_MUTEX(g_ras_info_lock); -static struct ras_node g_ras_info[RAS_MODULE_MAX] = {0}; - -static void do_ras_oem_type1(const void *error); -static void do_ras_oem_type2(const void *error); -static void do_ras_arm(const void *error); -static void do_ras_pcie(const void *error); -static void do_ras_pcie_local(const void *error); -static const struct ras_handle g_ras_handle_tab[] = { - { - .gid = CPER_SEC_HISI_OEM_1, - .proc = do_ras_oem_type1, - }, - { - .gid = CPER_SEC_HISI_OEM_2, - .proc = do_ras_oem_type2, - }, - { - .gid = CPER_SEC_HISI_PCIE_LOCAL, - .proc = do_ras_pcie_local, - }, - { - .gid = CPER_SEC_PCIE, - .proc = do_ras_pcie, - }, - { - .gid = CPER_SEC_PROC_ARM, - .proc = do_ras_arm, - } -}; - -static void do_ras_oem_type1(const void *error) -{ - u32 ras_moudle_id; - const struct hisi_oem_type1_err_sec *err = error; - - if (!err->validation_bits.module_id_vald) { - pr_err("%s : module id is invalid\n", __func__); - return; - } - - SYSCTRL_DFX_DBG("%s module_id = %u\n", __func__, err->module_id); - switch (err->module_id) { - case (OEM1_MODULE_PLL): - ras_moudle_id = RAS_MODULE_PLL; - break; - case (OEM1_MODULE_SLLC): - ras_moudle_id = RAS_MODULE_SLLC; - break; - case (OEM1_MODULE_SIOE): - ras_moudle_id = RAS_MODULE_SIOE; - break; - case (OEM1_MODULE_POE): - ras_moudle_id = RAS_MODULE_POE; - break; - case (OEM1_MODULE_DISP): - ras_moudle_id = RAS_MODULE_DISPATCH; - break; - case (OEM1_MODULE_TDH): - ras_moudle_id = RAS_MODULE_TDH; - break; - case (OEM1_MODULE_GIC): - ras_moudle_id = RAS_MODULE_GIC; - break; - case (OEM1_MODULE_RDE): - ras_moudle_id = RAS_MODULE_RDE; - break; - case (OEM1_MODULE_SAS): - ras_moudle_id = RAS_MODULE_SAS; - break; - case (OEM1_MODULE_SATA): - ras_moudle_id = RAS_MODULE_SATA; - break; - case (OEM1_MODULE_USB): - ras_moudle_id = RAS_MODULE_USB; - break; - default: - return; - } - - mutex_lock(&g_ras_info_lock); - g_ras_info[ras_moudle_id].cnt++; - mutex_unlock(&g_ras_info_lock); -} - -static void do_ras_oem_type2(const void *error) -{ - u32 ras_moudle_id; - const struct hisi_oem_type2_err_sec *err = error; - - if (!(err->val_bits & HISI_OEM_VALID_MODULE_ID)) { - pr_err("%s: module id is invalid\n", __func__); - return; - } - - SYSCTRL_DFX_DBG("%s module_id= %u\n", __func__, err->module_id); - switch (err->module_id) { - case (OEM2_MODULE_SMMU): - ras_moudle_id = RAS_MODULE_SMMU; - break; - case (OEM2_MODULE_HHA): - ras_moudle_id = RAS_MODULE_HHA; - break; - case (OEM2_MODULE_PA): - ras_moudle_id = RAS_MODULE_PA; - break; - case (OEM2_MODULE_HLLC): - ras_moudle_id = RAS_MODULE_HLLC; - break; - case (OEM2_MODULE_DDRC): - ras_moudle_id = RAS_MODULE_DDRC; - break; - default: - return; - } - - mutex_lock(&g_ras_info_lock); - g_ras_info[ras_moudle_id].cnt++; - mutex_unlock(&g_ras_info_lock); -} - -static bool is_net_subsys_devid(u16 device_id, u32 *module_id) -{ - switch (device_id) { - case (HISI_PCIE_DEV_ID_GE): - *module_id = RAS_MODULE_NET_GE; - break; - case (HISI_PCIE_DEV_ID_25GE): - *module_id = RAS_MODULE_NET_25GE; - break; - case (HISI_PCIE_DEV_ID_25GE_RDMA): - *module_id = RAS_MODULE_NET_25GE_RDMA; - break; - case (HISI_PCIE_DEV_ID_50GE_RDMA): - *module_id = RAS_MODULE_NET_50GE_RDMA; - break; - case (HISI_PCIE_DEV_ID_100G_RDMA): - *module_id = RAS_MODULE_NET_100G_RDMA; - break; - case (HISI_PCIE_DEV_ID_SDI): - *module_id = RAS_MODULE_NET_SDI; - break; - case (HISI_PCIE_DEV_ID_100G_VF): - *module_id = RAS_MODULE_NET_100G_VF; - break; - case (HISI_PCIE_DEV_ID_100G_RDMA_VF): - *module_id = RAS_MODULE_NET_100G_RDMA_VF; - break; - default: - return false; - } - - return true; -} - -static void do_ras_pcie(const void *error) -{ - u32 ras_moudle_id; - const struct cper_sec_pcie *err = error; - - if (!(err->validation_bits & CPER_PCIE_VALID_DEVICE_ID)) { - pr_err("do ras pcie : device id is invalid\n"); - return; - } - - if (err->device_id.vendor_id != HISI_PCIE_VENDOR_ID) { - pr_err("do ras pcie : vendor id is not hisi\n"); - return; - } - - SYSCTRL_DFX_DBG("do ras pcie = 0x%x\n", err->device_id.device_id); - if (err->device_id.device_id == HISI_PCIE_DEV_ID_ZIP) { - ras_moudle_id = RAS_MODULE_ZIP; - } else if (err->device_id.device_id == HISI_PCIE_DEV_ID_SEC) { - ras_moudle_id = RAS_MODULE_SEC; - } else if (err->device_id.device_id == HISI_PCIE_DEV_ID_HPRE) { - ras_moudle_id = RAS_MODULE_HPRE; - } else if (is_net_subsys_devid(err->device_id.device_id, &ras_moudle_id)) { - SYSCTRL_DFX_DBG("RAS: do_net_ras\n"); - } else { - pr_err("do ras pcie : device id=0x%x not support\n", err->device_id.device_id); - return; - } - - mutex_lock(&g_ras_info_lock); - g_ras_info[ras_moudle_id].cnt++; - mutex_unlock(&g_ras_info_lock); -} - -static void do_ras_arm(const void *error) -{ - mutex_lock(&g_ras_info_lock); - g_ras_info[RAS_MODULE_CPU_CORE].cnt++; - mutex_unlock(&g_ras_info_lock); -} - -static void do_ras_pcie_local(const void *error) -{ - u32 ras_moudle_id; - const struct hisi_pcie_local_err_sec *err = error; - - if (!(err->val_bits & HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID)) { - pr_err("%s: module id is invalid\n", __func__); - return; - } - - SYSCTRL_DFX_DBG("%s module_id=%u\n", __func__, err->sub_module_id); - switch (err->sub_module_id) { - case (PCIE_LOCAL_MODULE_AP): - ras_moudle_id = RAS_MODULE_PCIE_AP; - break; - case (PCIE_LOCAL_MODULE_TL): - ras_moudle_id = RAS_MODULE_PCIE_TL; - break; - case (PCIE_LOCAL_MODULE_MAC): - ras_moudle_id = RAS_MODULE_PCIE_MAC; - break; - case (PCIE_LOCAL_MODULE_DL): - ras_moudle_id = RAS_MODULE_PCIE_DL; - break; - case (PCIE_LOCAL_MODULE_SDI): - ras_moudle_id = RAS_MODULE_PCIE_SDI_LOCAL; - break; - default: - return; - } - - mutex_lock(&g_ras_info_lock); - g_ras_info[ras_moudle_id].cnt++; - mutex_unlock(&g_ras_info_lock); -} - -void sysctl_dfx_do_ras(struct acpi_hest_generic_data *gdata) -{ - u32 count; - guid_t *sec_type = NULL; - - SYSCTRL_DFX_DBG("do ras\n"); - if (!gdata) { - pr_err("[ERROR]: err gdata\n"); - return; - } - - sec_type = (guid_t *)gdata->section_type; - for (count = 0; count < ARRAY_SIZE(g_ras_handle_tab); count++) { - if (guid_equal(sec_type, &g_ras_handle_tab[count].gid)) { - g_ras_handle_tab[count].proc(acpi_hest_get_payload(gdata)); - break; - } - } -} - -static long sysctl_proc_ioctl(struct file *file, unsigned int req, unsigned long arg) -{ - if (req == SYSCTL_IOCTL_GET_RAS) { - mutex_lock(&g_ras_info_lock); - if (copy_to_user((void *)arg, &g_ras_info[0], sizeof(g_ras_info))) - pr_err("sysctl proc : copy to user failed\n"); - mutex_unlock(&g_ras_info_lock); - } - - return 0; -} - -static const struct file_operations g_sysctl_proc_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = sysctl_proc_ioctl, -}; - -int sysctl_proc_init(void) -{ - if (!proc_create(SYSCTL_PROC, S_IRUGO, NULL, &g_sysctl_proc_fops)) { - pr_err("sysctl proc create failed\n"); - return -ENOMEM; - } - - SYSCTRL_DFX_DBG("sysctl proc init\n"); - return 0; -} - -void sysctl_proc_exit(void) -{ - SYSCTRL_DFX_DBG("sysctl proc exit\n"); - remove_proc_entry(SYSCTL_PROC, NULL); -} diff --git a/drivers/soc/hisilicon/sysctl/sysctl_dfx.h b/drivers/soc/hisilicon/sysctl/sysctl_dfx.h deleted file mode 100644 index cf0ab99f0e3f2..0000000000000 --- a/drivers/soc/hisilicon/sysctl/sysctl_dfx.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _SYSCTL_DFX_H_ -#define _SYSCTL_DFX_H_ - -int sysctl_proc_init(void); -void sysctl_proc_exit(void); -void sysctl_dfx_do_ras(struct acpi_hest_generic_data *gdata); - -#endif /* _SYSCTL_DFX_H_ */ diff --git a/drivers/soc/hisilicon/sysctl/sysctl_drv.c b/drivers/soc/hisilicon/sysctl/sysctl_drv.c deleted file mode 100644 index c4cb157023689..0000000000000 --- a/drivers/soc/hisilicon/sysctl/sysctl_drv.c +++ /dev/null @@ -1,819 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/ioport.h> -#include <linux/io.h> -#include <linux/cpu.h> -#include <linux/of.h> -#include <linux/platform_device.h> -#include <linux/acpi.h> -#include <linux/delay.h> -#include <linux/mutex.h> -#include "sysctl_drv.h" -#include "hllc_ras_c_union_define.h" -#include "hllc_ras_reg_offset.h" -#include "hllc_regs_c_union_define.h" -#include "hllc_regs_reg_offset.h" -#include "hllc_pcs_c_union_define.h" -#include "hllc_pcs_reg_offset.h" -#include "dmc_c_union_define.h" -#include "dmc_reg_offset.h" -#include "rasc_c_union_define.h" -#include "rasc_reg_offset.h" -#include "pa_c_union_define.h" -#include "pa_reg_offset.h" -#include "sysctl_local_ras.h" -#include "sysctl_pmbus.h" - -#ifdef pr_fmt -#undef pr_fmt -#endif -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -#define DEBUG - -#define SYSCTL_DRIVER_VERSION "1.9.60.0" - -unsigned int g_sysctrl_debug; - -/* sysctrl reg base address */ -struct his_hllc_priv { - void __iomem *hllc_base[CHIP_ID_NUM_MAX][HLLC_NUM_MAX]; - void __iomem *pcs_base[CHIP_ID_NUM_MAX][HLLC_NUM_MAX]; - void __iomem *pa_base[CHIP_ID_NUM_MAX]; - void __iomem *ddrc_tb_base[CHIP_ID_NUM_MAX][DDRC_CH_NUM_MAX]; - void __iomem *ddrc_ta_base[CHIP_ID_NUM_MAX][DDRC_CH_NUM_MAX]; -}; - -struct his_hllc_priv g_hip_hllc_priv; - -int hisi_sysctl_print_debug(u32 print_debug_en) -{ - if (print_debug_en) - g_sysctrl_debug = 0x1; - else - g_sysctrl_debug = 0x0; - - return 0; -} - -u64 get_chip_base(void) -{ - u32 chip_ver; - void __iomem *chip_ver_addr; - u64 chip_module_base; - - chip_ver_addr = ioremap(CHIP_VER_BASE, (u64)0x4); - if (!chip_ver_addr) { - pr_err("sysctl [ERROR] %s chip_ver_base is error.\n", __func__); - return SYSCTL_ERR_FAILED; - } - - chip_ver = readl(chip_ver_addr); - chip_ver = chip_ver>>28; /* bit28 indicates the board type. */ - if (chip_ver == CHIP_VERSION_ES) { - pr_info("sysctl [INFO] chip is es\n"); - chip_module_base = HLLC_CHIP_MODULE_ES; - } else { - chip_module_base = HLLC_CHIP_MODULE_CS; - pr_info("sysctl [INFO] chip is cs\n"); - } - - iounmap((void *)chip_ver_addr); - - pr_info("sysctl [INFO] chip ver=%x\n", chip_ver); - - return chip_module_base; -} - -int his_hllc_init(void) -{ - u32 hllc_num; - u32 chip_id; - u32 ddrc_num; - u64 addr; - u64 chip_module_base; - - pr_info("[INFO] %s start.\n", __func__); - - chip_module_base = get_chip_base(); - - for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) { - for (hllc_num = 0; hllc_num < HLLC_NUM_MAX; hllc_num++) { - addr = (u64)chip_id * chip_module_base + HLLC0_REG_BASE + (u64)hllc_num * 0x10000; - g_hip_hllc_priv.hllc_base[chip_id][hllc_num] = ioremap(addr, (u64)0x10000); - if (!g_hip_hllc_priv.hllc_base[chip_id][hllc_num]) - pr_err("chip=%u, hllc=%u, hllc ioremap failed\n", chip_id, hllc_num); - - addr = (u64)chip_id * chip_module_base + PCS0_REG_BASE + (u64)hllc_num * 0x10000; - g_hip_hllc_priv.pcs_base[chip_id][hllc_num] = ioremap(addr, (u64)0x10000); - if (!g_hip_hllc_priv.pcs_base[chip_id][hllc_num]) - pr_err("chip=%u, hllc=%u, pcs ioremap failed\n", chip_id, hllc_num); - } - - addr = (u64)chip_id * chip_module_base + PA_REG_BASE; - g_hip_hllc_priv.pa_base[chip_id] = ioremap(addr, (u64)0x10000); - if (!g_hip_hllc_priv.pa_base[chip_id]) - pr_err("chip=%u, pa ioremap failed\n", chip_id); - - for (ddrc_num = 0; ddrc_num < DDRC_CH_NUM_MAX; ddrc_num++) { - addr = (u64)chip_id * chip_module_base + DDRC0_TB_REG_BASE + (u64)ddrc_num * 0x10000; - g_hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_num] = ioremap(addr, (u64)0x10000); - if (!g_hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_num]) - pr_err("chip=%u,ddr_ch=%u ddrc tb ioremap failed\n", chip_id, ddrc_num); - - addr = (u64)chip_id * chip_module_base + DDRC0_TA_REG_BASE + (u64)ddrc_num * 0x10000; - g_hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_num] = ioremap(addr, (u64)0x10000); - if (!g_hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_num]) - pr_err("chip=%u,ddr_ch=%u ddrc ta ioremap failed\n", chip_id, ddrc_num); - } - } - - return SYSCTL_ERR_OK; -} - -int his_hllc_deinit(void) -{ - u8 chip_id; - u8 hllc_num; - u8 ddrc_num; - - for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) { - for (hllc_num = 0; hllc_num < HLLC_NUM_MAX; hllc_num++) { - if (g_hip_hllc_priv.hllc_base[chip_id][hllc_num]) - iounmap((void *)g_hip_hllc_priv.hllc_base[chip_id][hllc_num]); - - if (g_hip_hllc_priv.pcs_base[chip_id][hllc_num]) - iounmap((void *)g_hip_hllc_priv.pcs_base[chip_id][hllc_num]); - } - - if (g_hip_hllc_priv.pa_base[chip_id]) - iounmap((void *)g_hip_hllc_priv.pa_base[chip_id]); - - for (ddrc_num = 0; ddrc_num < DDRC_CH_NUM_MAX; ddrc_num++) { - if (g_hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_num]) - iounmap((void *)g_hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_num]); - - if (g_hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_num]) - iounmap((void *)g_hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_num]); - } - } - - return SYSCTL_ERR_OK; -} - -int hisi_sysctl_get_intlv_mode_cfg(u8 chip_id, u8 *intlv_mode_cfg) -{ - pa_u_global_cfg pa_global_cfg; - void __iomem *addr; - int ret = 0; - - debug_sysctrl_print("%s: begin\n", __func__); - - if (intlv_mode_cfg == NULL) - return SYSCTL_ERR_PARAM; - - if (chip_id >= CHIP_ID_NUM_MAX) - return SYSCTL_ERR_PARAM; - - /* set the PLL0 slow */ - if (g_hip_hllc_priv.pa_base[chip_id] == NULL) { - pr_err("%s: g_hip_hllc_priv.pa_base[%u] is NULL.\n", __func__, chip_id); - return SYSCTL_ERR_FAULT; - } - - addr = g_hip_hllc_priv.pa_base[chip_id] + PA_PA_GLOBAL_CFG_REG; - pa_global_cfg.u32 = readl(addr); - - debug_sysctrl_print("addr:%pK, val:0x%x.\n", addr, pa_global_cfg.u32); - - *intlv_mode_cfg = (u8)pa_global_cfg.bits.intlv_mode_cfg; - - debug_sysctrl_print("%s: end\n", __func__); - return ret; -} - -int hisi_sysctl_get_hllc_enable_cfg(u8 chip_id, u8 intlv_mode_cfg, u8 *hllc_eanble_cfg) -{ - pa_u_global_cfg pa_global_cfg; - void __iomem *addr; - int ret = 0; - - debug_sysctrl_print("%s: begin\n", __func__); - - if (hllc_eanble_cfg == NULL) - return SYSCTL_ERR_PARAM; - - switch (intlv_mode_cfg & 0x7) { - case HLLC_INTLV_MODE_2PX8: - if (g_hip_hllc_priv.pa_base[chip_id] == NULL) { - pr_err("%s: g_hip_hllc_priv.pa_base[%u] is NULL.\n", __func__, chip_id); - return SYSCTL_ERR_FAULT; - } - - addr = g_hip_hllc_priv.pa_base[chip_id] + PA_PA_GLOBAL_CFG_REG; - pa_global_cfg.u32 = readl(addr); - - debug_sysctrl_print("addr:%pK, val:0x%x.\n", addr, pa_global_cfg.u32); - - *hllc_eanble_cfg = (u8)pa_global_cfg.bits.hydra_port_en_cfg; - break; - case HLLC_INTLV_MODE_2PX16: - /* 2p x16, port0-port1 */ - *hllc_eanble_cfg = 0x3; - break; - case HLLC_INTLV_MODE_2PX24: - debug_sysctrl_print("2PX24 is no use. pls check\n"); - break; - case HLLC_INTLV_MODE_4PX8: - /* 4P */ - *hllc_eanble_cfg = 0x7; - break; - case HLLC_INTLV_MODE_3P1: - /* 3P */ - *hllc_eanble_cfg = 0x7; - break; - case HLLC_INTLV_MODE_3P2: - /* 3P */ - *hllc_eanble_cfg = 0x7; - break; - default: - debug_sysctrl_print("intlv_mode_cfg[0x%x] is err\n", intlv_mode_cfg); - ret = SYSCTL_ERR_FAILED; - break; - } - - debug_sysctrl_print("hllc_eanble_cfg is 0x%x.\n.", *hllc_eanble_cfg); - - debug_sysctrl_print("%s: end\n", __func__); - return ret; -} - -int hisi_sysctl_clr_hllc_ecc(u8 chip_id, u8 hllc_id, u32 ecc_clr) -{ - void __iomem *addr; - - debug_sysctrl_print("%s: begin\n", __func__); - - if ((chip_id >= CHIP_ID_NUM_MAX) || (hllc_id >= HLLC_NUM_MAX)) - return SYSCTL_ERR_PARAM; - - debug_sysctrl_print("clr_hllc_ecc:chip_id[0x%x], hllc_id[0x%x].\n", chip_id, hllc_id); - - if (g_hip_hllc_priv.hllc_base[chip_id][hllc_id] == NULL) { - pr_err("%s: g_hip_hllc_priv.hllc_base[%u][%u] is NULL.\n", __func__, chip_id, hllc_id); - return SYSCTL_ERR_FAULT; - } - - /* hllc clr ecc */ - addr = g_hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_REGS_HLLC_CNT_CLR_REG; - - writel(ecc_clr & 0x1, addr); - - return SYSCTL_ERR_OK; -} - -int hisi_sysctl_set_hllc_crc_ecc(u8 chip_id, u8 hllc_id, u32 crc_err_times) -{ - void __iomem *addr; - u32 loop = 0x10000; - u32 inject_crc_err_done = 0; - - debug_sysctrl_print("%s: begin\n", __func__); - - if ((chip_id >= CHIP_ID_NUM_MAX) || - (hllc_id >= HLLC_NUM_MAX) || - (crc_err_times == 0)) - return SYSCTL_ERR_PARAM; - - debug_sysctrl_print("set_hllc_crc_ecc:chip_id[0x%x], hllc_id[0x%x], crc_err_times[0x%x].\n", - chip_id, hllc_id, crc_err_times); - - if (g_hip_hllc_priv.hllc_base[chip_id][hllc_id] == NULL) { - pr_err("%s: g_hip_hllc_priv.hllc_base[%u][%u] is NULL.\n", __func__, chip_id, hllc_id); - return SYSCTL_ERR_FAULT; - } - - /* enable crc ecc */ - addr = g_hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_REGS_HLLC_PHY_TX_INJECT_1BIT_CRC_ERR_EN_REG; - writel(0x1, addr); - writel(0x0, addr); - - /* config ecc count */ - addr = g_hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_REGS_HLLC_PHY_TX_INJECT_1BIT_CRC_ERR_TIMES_REG; - writel(crc_err_times, addr); - - /* check done */ - addr = g_hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_REGS_HLLC_PHY_TX_INJECT_1BIT_CRC_ERR_DONE_REG; - while (loop) { - udelay((unsigned long)100); /* Delay 100 subtleties */ - - inject_crc_err_done = readl(addr); - if (inject_crc_err_done & 0x1) - break; - - loop--; - } - - if (!loop) { - pr_err("%s:set hllc crc ecc time out, hllc_base[%u][%u]: %pK.\n", - __func__, chip_id, hllc_id, g_hip_hllc_priv.hllc_base[chip_id][hllc_id]); - return SYSCTL_ERR_TIMEOUT; - } - - debug_sysctrl_print("%s: set_hllc_mem_ecc success\n", __func__); - - return SYSCTL_ERR_OK; -} - -int hisi_sysctl_get_hllc_crc_ecc(u8 chip_id, hllc_crc_ecc_info *hllc_crc_ecc) -{ - u32 phy_rx_flit_crc_err_cnt; - void __iomem *addr; - int ret; - u8 intlv_mode_cfg; - u8 hllc_eanble_cfg = 0; - u8 hllc_num; - - debug_sysctrl_print("%s: begin\n", __func__); - - if (chip_id >= CHIP_ID_NUM_MAX) - return SYSCTL_ERR_PARAM; - - if (hllc_crc_ecc == NULL) - return SYSCTL_ERR_PARAM; - - ret = hisi_sysctl_get_intlv_mode_cfg(chip_id, &intlv_mode_cfg); - if (ret) - return ret; - - ret = hisi_sysctl_get_hllc_enable_cfg(chip_id, intlv_mode_cfg, &hllc_eanble_cfg); - if (ret) - return ret; - - hllc_crc_ecc->hllc_enable = hllc_eanble_cfg; - - for (hllc_num = 0; hllc_num < HLLC_NUM_MAX; hllc_num++) { - if (g_hip_hllc_priv.hllc_base[chip_id][hllc_num] == NULL) { - pr_err("%s: g_hip_hllc_priv.hllc_base[%u][%u] is NULL.\n", - __func__, chip_id, hllc_num); - return SYSCTL_ERR_FAULT; - } - - addr = g_hip_hllc_priv.hllc_base[chip_id][hllc_num] + HLLC_HLLC_REGS_HLLC_PHY_RX_FLIT_CRC_ERR_CNT_REG; - phy_rx_flit_crc_err_cnt = readl(addr); - - debug_sysctrl_print("addr:%pK, crc_err_cnt:0x%x.\n", addr, phy_rx_flit_crc_err_cnt); - - hllc_crc_ecc->hllc_crc_ecc[hllc_num] = phy_rx_flit_crc_err_cnt; - } - - debug_sysctrl_print("hllc_crc_ecc.hllc_enable:0x%x.\n", hllc_crc_ecc->hllc_enable); - - debug_sysctrl_print("%s: get_hllc_crc_ecc success\n", __func__); - - return ret; -} - -int hisi_sysctl_get_hllc_link_status(u8 chip_id, hllc_link_sta_info *hllc_link_sta) -{ - pcs_u_tx_training_sts pcs_tx_training_sts; - void __iomem *addr; - int ret; - u8 intlv_mode_cfg; - u8 hllc_eanble_cfg = 0; - u8 hllc_num; - u8 lane_num; - u8 hllc_link_status; - - debug_sysctrl_print("%s: begin\n", __func__); - - if (chip_id >= CHIP_ID_NUM_MAX) - return SYSCTL_ERR_PARAM; - - if (hllc_link_sta == NULL) - return SYSCTL_ERR_PARAM; - - ret = hisi_sysctl_get_intlv_mode_cfg(chip_id, &intlv_mode_cfg); - if (ret) - return ret; - - ret = hisi_sysctl_get_hllc_enable_cfg(chip_id, intlv_mode_cfg, &hllc_eanble_cfg); - if (ret) - return ret; - - hllc_link_sta->bits.hllc_enable = hllc_eanble_cfg; - hllc_link_sta->bits.hllc_link_status = 0; - - for (hllc_num = 0; hllc_num < HLLC_NUM_MAX; hllc_num++) { - hllc_link_status = 1; - - if (g_hip_hllc_priv.pcs_base[chip_id][hllc_num] == NULL) { - pr_err("%s: g_hip_hllc_priv.pcs_base[%u][%u] is NULL.\n", __func__, chip_id, hllc_num); - return SYSCTL_ERR_FAULT; - } - - for (lane_num = 0; lane_num < HLLC_LANE_NUM_MAX; lane_num++) { - addr = g_hip_hllc_priv.pcs_base[chip_id][hllc_num] \ - + HLLC_HLLC_PCS_PCS_TX_TRAINING_STS_0_REG + lane_num * 0x4; - pcs_tx_training_sts.u32 = readl(addr); - - debug_sysctrl_print("addr:%pK, val:0x%x.\n", addr, pcs_tx_training_sts.u32); - - hllc_link_status &= pcs_tx_training_sts.bits.tx_training_succeed; - } - - hllc_link_sta->bits.hllc_link_status |= hllc_link_status << hllc_num; - } - - debug_sysctrl_print("hllc_crc_ecc:0x%x.\n", hllc_link_sta->u32); - - debug_sysctrl_print("%s: get_hllc_link_status success\n", __func__); - - return ret; -} - -int hisi_sysctl_set_hllc_mem_ecc(u8 chip_id, u8 hllc_id, u8 hllc_ch_bitmap, u8 ecc_err_type) -{ - hllc_regs_u_inject_ecc_type hllc_inject_ecc_type; - hllc_regs_u_inject_ecc_en hllc_inject_ecc_en; - void __iomem *addr; - - debug_sysctrl_print("%s: begin\n", __func__); - - if ((chip_id >= CHIP_ID_NUM_MAX) || (hllc_id >= HLLC_NUM_MAX)) - return SYSCTL_ERR_PARAM; - - debug_sysctrl_print("set_hllc_mem_ecc:chip_id[0x%x], hllc_id[0x%x], hllc_ch_bitmap[0x%x], ecc_err_type[0x%x].\n", - chip_id, hllc_id, hllc_ch_bitmap, ecc_err_type); - - if (g_hip_hllc_priv.hllc_base[chip_id][hllc_id] == NULL) { - pr_err("%s: g_hip_hllc_priv.hllc_base[%u][%u] is NULL.\n", __func__, chip_id, hllc_id); - return SYSCTL_ERR_FAULT; - } - - addr = g_hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_REGS_HLLC_INJECT_ECC_TYPE_REG; - hllc_inject_ecc_type.u32 = readl(addr); - hllc_inject_ecc_type.bits.inject_ecc_err_type = ecc_err_type & 0x3; - writel(hllc_inject_ecc_type.u32, addr); - - debug_sysctrl_print("addr:%pK, val:0x%x.\n", addr, hllc_inject_ecc_type.u32); - - addr = g_hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_REGS_HLLC_INJECT_ECC_EN_REG; - hllc_inject_ecc_en.u32 = readl(addr); - hllc_inject_ecc_en.bits.hydra_tx_inject_ecc_err_en = hllc_ch_bitmap & 0x7; - writel(hllc_inject_ecc_en.u32, addr); - - debug_sysctrl_print("addr:%pK, val:0x%x.\n", addr, hllc_inject_ecc_en.u32); - - debug_sysctrl_print("%s: set_hllc_mem_ecc success\n", __func__); - - return 0; -} - -int hisi_sysctl_get_hllc_mem_ecc(u8 chip_id, u8 hllc_id, hllc_mem_ecc_info *hllc_mem_ecc) -{ - hllc_ras_u_err_misc1h hllc_ras_err_misc1h; - hllc_ras_u_err_misc1l hllc_ras_err_misc1l; - void __iomem *addr; - int ret = 0; - - debug_sysctrl_print("%s: begin\n", __func__); - - if ((chip_id >= CHIP_ID_NUM_MAX) || - (hllc_id >= HLLC_NUM_MAX) || - (hllc_mem_ecc == NULL)) - return SYSCTL_ERR_PARAM; - - debug_sysctrl_print("get_hllc_mem_ecc:chip_id[0x%x], hllc_id[0x%x].\n", chip_id, hllc_id); - - if (g_hip_hllc_priv.hllc_base[chip_id][hllc_id] == NULL) { - pr_err("%s: g_hip_hllc_priv.hllc_base[%u][%u] is NULL.\n", __func__, chip_id, hllc_id); - return SYSCTL_ERR_FAULT; - } - - addr = g_hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_RAS_HLLC_ERR_MISC1H_REG; - hllc_ras_err_misc1h.u32 = readl(addr); - hllc_mem_ecc->u32 = hllc_ras_err_misc1h.u32 & 0x7f; - debug_sysctrl_print("addr:%pK, val:0x%x.\n", addr, hllc_ras_err_misc1h.u32); - - addr = g_hip_hllc_priv.hllc_base[chip_id][hllc_id] + HLLC_HLLC_RAS_HLLC_ERR_MISC1L_REG; - hllc_ras_err_misc1l.u32 = readl(addr); - hllc_mem_ecc->u32 |= (hllc_ras_err_misc1l.u32 & 0x7f) << 0x7; - debug_sysctrl_print("addr:%pK, val:0x%x.\n", addr, hllc_ras_err_misc1l.u32); - - debug_sysctrl_print("hllc_mem_ecc:0x%x.\n", hllc_mem_ecc->u32); - - debug_sysctrl_print("%s: get_hllc_mem_ecc success\n", __func__); - - return ret; -} - -int hisi_sysctl_clr_ddrc_mem_ecc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u32 rasc_cfg_clr) -{ - ddrc_rasc_u_cfg_clr ddrc_rasc_cfg_clr; - void __iomem *addr_ecc_clr; - int ret = 0; - - debug_sysctrl_print("%s: begin\n", __func__); - - if ((chip_id >= CHIP_ID_NUM_MAX) || - (totem >= TOTEM_NUM_MAX) || - (ddrc_ch_id >= DDRC_CH_NUM_MAX)) - return SYSCTL_ERR_PARAM; - - debug_sysctrl_print("clr_ddrc_mem_ecc:chip_id[0x%x], totem[0x%x], ddrc_ch_id[0x%x].\n", - chip_id, totem, ddrc_ch_id); - - if (totem == TOTEM_TA_NUM) { - if (g_hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_ch_id] == NULL) { - pr_err("%s: g_hip_hllc_priv.ddrc_ta_base[%u][%u] is NULL.\n", - __func__, chip_id, ddrc_ch_id); - return SYSCTL_ERR_FAULT; - } - - addr_ecc_clr = g_hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_ch_id] + DDRC_RASC_RASC_CFG_CLR_REG; - } else { - if (g_hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_ch_id] == NULL) { - pr_err("%s: g_hip_hllc_priv.ddrc_tb_base[%u][%u] is NULL.\n", - __func__, chip_id, ddrc_ch_id); - return SYSCTL_ERR_FAULT; - } - - addr_ecc_clr = g_hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_ch_id] + DDRC_RASC_RASC_CFG_CLR_REG; - } - - ddrc_rasc_cfg_clr.u32 = rasc_cfg_clr; - writel(ddrc_rasc_cfg_clr.u32, addr_ecc_clr); - - debug_sysctrl_print("addr:%pK, val:0x%x.\n", addr_ecc_clr, ddrc_rasc_cfg_clr.u32); - - return ret; -} - -static int calc_ddrc_mem_reg_addr(u8 chip_id, u8 totem, u8 ddrc_ch_id, - void __iomem **addr_ecc_cnt, void __iomem **addr_ecc_cfg_info_rnk, void __iomem **addr_ecc_cfg_ecc) -{ - if (totem == TOTEM_TA_NUM) { - if (g_hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_ch_id] == NULL) { - pr_err("%s: g_hip_hllc_priv.ddrc_ta_base[%u][%u] is NULL.\n", - __func__, chip_id, ddrc_ch_id); - return SYSCTL_ERR_FAULT; - } - - *addr_ecc_cfg_info_rnk = g_hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_ch_id] + DDRC_RASC_RASC_CFG_INFO_RNK_REG; - *addr_ecc_cnt = g_hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_ch_id] + DDRC_RASC_RASC_HIS_HA_RANKCNT_INF_REG; - *addr_ecc_cfg_ecc = g_hip_hllc_priv.ddrc_ta_base[chip_id][ddrc_ch_id] + DMC_DMC_DDRC_CFG_ECC_REG; - } else { - if (g_hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_ch_id] == NULL) { - pr_err("%s: g_hip_hllc_priv.ddrc_tb_base[%u][%u] is NULL.\n", - __func__, chip_id, ddrc_ch_id); - return SYSCTL_ERR_FAULT; - } - - *addr_ecc_cfg_info_rnk = g_hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_ch_id] + DDRC_RASC_RASC_CFG_INFO_RNK_REG; - *addr_ecc_cnt = g_hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_ch_id] + DDRC_RASC_RASC_HIS_HA_RANKCNT_INF_REG; - *addr_ecc_cfg_ecc = g_hip_hllc_priv.ddrc_tb_base[chip_id][ddrc_ch_id] + DMC_DMC_DDRC_CFG_ECC_REG; - } - debug_sysctrl_print("addr_ecc_cfg_info_rnk:%pK.\n", addr_ecc_cfg_info_rnk); - - return SYSCTL_ERR_OK; -} - -int hisi_sysctl_get_ddrc_mem_ecc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u8 rank_id, ddrc_mem_ecc_info *ddrc_mem_ecc) -{ - dmc_ddrc_u_cfg_ecc dmc_ddrc_cfg_ecc; - ddrc_rasc_u_cfg_info_rnk ddrc_rasc_cfg_info_rnk; - ddrc_rasc_u_his_ha_rankcnt_inf ddrc_rasc_his_ha_rankcnt_inf; - void __iomem *addr_ecc_cnt; - void __iomem *addr_ecc_cfg_info_rnk; - void __iomem *addr_ecc_cfg_ecc; - int ret; - - debug_sysctrl_print("%s: begin\n", __func__); - - if ((chip_id >= CHIP_ID_NUM_MAX) || - (totem >= TOTEM_NUM_MAX) || - (ddrc_ch_id >= DDRC_CH_NUM_MAX) || - (ddrc_mem_ecc == NULL) || - (rank_id >= DDRC_RANK_NUM_MAX)) - return SYSCTL_ERR_PARAM; - - debug_sysctrl_print("get_ddrc_mem_ecc:chip_id[0x%x], totem[0x%x], ddrc_ch_id[0x%x], rank_id[0x%x].\n", - chip_id, totem, ddrc_ch_id, rank_id); - - ret = calc_ddrc_mem_reg_addr(chip_id, totem, ddrc_ch_id, - &addr_ecc_cnt, &addr_ecc_cfg_info_rnk, &addr_ecc_cfg_ecc); - if (ret) - return ret; - - memset(&ddrc_rasc_cfg_info_rnk, 0, sizeof(ddrc_rasc_u_cfg_info_rnk)); - ddrc_rasc_cfg_info_rnk.bits.idx_rnk = rank_id & 0xf; - writel(ddrc_rasc_cfg_info_rnk.u32, addr_ecc_cfg_info_rnk); - - ddrc_rasc_his_ha_rankcnt_inf.u32 = readl(addr_ecc_cnt); - ddrc_mem_ecc->ddrc_mem_secc = ddrc_rasc_his_ha_rankcnt_inf.u32; - debug_sysctrl_print("addr:%pK, ddrc_serr_cnt.funnel_corr_cnt:0x%x.\n", - addr_ecc_cnt, ddrc_rasc_his_ha_rankcnt_inf.bits.ha_rnk_funnel_corr_cnt); - debug_sysctrl_print("addr:%pK, ddrc_serr_cnt.corr_cnt:0x%x.\n", - addr_ecc_cnt, ddrc_rasc_his_ha_rankcnt_inf.bits.ha_rnk_corr_cnt); - - dmc_ddrc_cfg_ecc.u32 = readl(addr_ecc_cfg_ecc); - if ((dmc_ddrc_cfg_ecc.u32 & DDRC_ECC_EN) == DDRC_ECC_EN) - ddrc_mem_ecc->ddrc_mem_secc_en = 0x1; - else - ddrc_mem_ecc->ddrc_mem_secc_en = 0x0; - - debug_sysctrl_print("addr:%pK, dmc_ddrc_cfg_ecc:0x%x.\n", - addr_ecc_cfg_ecc, dmc_ddrc_cfg_ecc.u32); - - debug_sysctrl_print("%s: get_ddrc_mem_ecc success\n", __func__); - - return ret; -} - -/* check: hisi_sysctl_get_hllc_crc_ecc */ -unsigned long ut_hisi_sysctl_get_hllc_crc_ecc_enable(u8 chip_id) -{ - unsigned int ret; - hllc_crc_ecc_info hllc_crc_ecc; - - memset(&hllc_crc_ecc, 0, sizeof(hllc_crc_ecc_info)); - ret = hisi_sysctl_get_hllc_crc_ecc(chip_id, &hllc_crc_ecc); - pr_info("hllc_crc_ecc.hllc_enable:0x%x.\n", hllc_crc_ecc.hllc_enable); - - return ((unsigned long)hllc_crc_ecc.hllc_enable << 32) | ret; /* the upper 32 bits. */ -} - -unsigned long ut_hisi_sysctl_get_hllc_crc_ecc(u8 chip_id, u32 hllc_id) -{ - unsigned int ret; - hllc_crc_ecc_info hllc_crc_ecc; - - if (hllc_id >= HLLC_NUM_MAX) - return SYSCTL_ERR_PARAM; /* the upper 32 bits. */ - - memset(&hllc_crc_ecc, 0, sizeof(hllc_crc_ecc_info)); - ret = hisi_sysctl_get_hllc_crc_ecc(chip_id, &hllc_crc_ecc); - pr_info("hllc_crc_ecc.hllc_crc_ecc[%d]:0x%x.\n", hllc_id, hllc_crc_ecc.hllc_crc_ecc[hllc_id]); - - return ((unsigned long)hllc_crc_ecc.hllc_crc_ecc[hllc_id] << 32) | ret; /* the upper 32 bits. */ -} - -/* check: hisi_sysctl_get_hllc_link_status */ -unsigned long ut_hisi_sysctl_get_hllc_link_enable(u8 chip_id) -{ - unsigned int ret; - hllc_link_sta_info hllc_link_sta; - - memset(&hllc_link_sta, 0, sizeof(hllc_link_sta_info)); - ret = hisi_sysctl_get_hllc_link_status(chip_id, &hllc_link_sta); - pr_info("hllc_link_sta.bits.hllc_enable:0x%x.\n", hllc_link_sta.bits.hllc_enable); - - return ((unsigned long)hllc_link_sta.bits.hllc_enable << 32) | ret; /* the upper 32 bits. */ -} - -unsigned long ut_hisi_sysctl_get_hllc_link_status(u8 chip_id) -{ - unsigned int ret; - hllc_link_sta_info hllc_link_sta; - - memset(&hllc_link_sta, 0, sizeof(hllc_link_sta_info)); - ret = hisi_sysctl_get_hllc_link_status(chip_id, &hllc_link_sta); - pr_info("hllc_link_sta.bits.hllc_link_status:0x%x.\n", hllc_link_sta.bits.hllc_link_status); - - return ((unsigned long)hllc_link_sta.bits.hllc_link_status << 32) | ret; /* the upper 32 bits. */ -} - -/* check: hisi_sysctl_get_hllc_mem_ecc */ -unsigned long ut_hisi_sysctl_get_hllc_mem_ecc(u8 chip_id, u8 hllc_id) -{ - unsigned int ret; - hllc_mem_ecc_info hllc_mem_ecc; - - memset(&hllc_mem_ecc, 0, sizeof(hllc_mem_ecc_info)); - ret = hisi_sysctl_get_hllc_mem_ecc(chip_id, hllc_id, &hllc_mem_ecc); - pr_info("hllc_mem_ecc.u32:0x%x.\n", hllc_mem_ecc.u32); - - return ((unsigned long)hllc_mem_ecc.u32 << 32) | ret; /* the upper 32 bits. */ -} - -/* check: hisi_sysctl_get_ddrc_mem_ecc */ -unsigned long ut_hisi_sysctl_get_ddrc_mem_secc_en(u8 chip_id, u8 totem, u8 ddrc_ch_id, u8 rank_id) -{ - unsigned int ret; - ddrc_mem_ecc_info ddrc_mem_ecc; - - memset(&ddrc_mem_ecc, 0, sizeof(ddrc_mem_ecc_info)); - ret = hisi_sysctl_get_ddrc_mem_ecc(chip_id, totem, ddrc_ch_id, rank_id, &ddrc_mem_ecc); - pr_info("ddrc_mem_ecc.ddrc_mem_secc_en:0x%x.\n", ddrc_mem_ecc.ddrc_mem_secc_en); - - return ((unsigned long)ddrc_mem_ecc.ddrc_mem_secc_en << 32) | ret; /* the upper 32 bits. */ -} - -unsigned long ut_hisi_sysctl_get_ddrc_mem_secc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u8 rank_id) -{ - unsigned int ret; - ddrc_mem_ecc_info ddrc_mem_ecc; - - memset(&ddrc_mem_ecc, 0, sizeof(ddrc_mem_ecc_info)); - ret = hisi_sysctl_get_ddrc_mem_ecc(chip_id, totem, ddrc_ch_id, rank_id, &ddrc_mem_ecc); - pr_info("ddrc_mem_ecc.ddrc_mem_secc:0x%x.\n", ddrc_mem_ecc.ddrc_mem_secc); - - return ((unsigned long)ddrc_mem_ecc.ddrc_mem_secc << 32) | ret; /* the upper 32 bits. */ -} - -unsigned long ut_hisi_sysctl_get_ddrc_mem_mecc(u8 chip_id, u8 totem, u8 ddrc_ch_id, u8 rank_id) -{ - unsigned int ret; - ddrc_mem_ecc_info ddrc_mem_ecc; - - memset(&ddrc_mem_ecc, 0, sizeof(ddrc_mem_ecc_info)); - ret = hisi_sysctl_get_ddrc_mem_ecc(chip_id, totem, ddrc_ch_id, rank_id, &ddrc_mem_ecc); - pr_info("ddrc_mem_ecc.ddrc_mem_mecc:0x%x.\n", ddrc_mem_ecc.ddrc_mem_mecc); - - return ((unsigned long)ddrc_mem_ecc.ddrc_mem_mecc << 32) | ret; /* the upper 32 bits. */ -} - -int hip_sysctrl_probe(void) -{ - int ret; - - ret = his_hllc_init(); - if (ret != SYSCTL_ERR_OK) { - pr_err("[ERROR] his_hllc_init fail, ret:[0x%x].\n", ret); - return ret; - } - - return SYSCTL_ERR_OK; -} - -int hip_sysctrl_remove(void) -{ - int ret; - - ret = his_hllc_deinit(); - if (ret != SYSCTL_ERR_OK) { - pr_err("[ERROR] his hllc deinit fail, ret:[0x%x].\n", ret); - return ret; - } - - return SYSCTL_ERR_OK; -} - -static int __init his_sysctrl_init(void) -{ - int ret = SYSCTL_ERR_OK; - - (void)hip_sysctl_pmbus_init(); - (void)hip_sysctrl_probe(); - (void)hip_sysctl_local_ras_init(); - - pr_info("[INFO] insmod sysctrl success.\n"); - - return ret; -} - -static void __exit his_sysctrl_exit(void) -{ - (void)hip_sysctl_pmbus_exit(); - (void)hip_sysctrl_remove(); - (void)hip_sysctl_local_ras_exit(); - - pr_info("[INFO] rmmod sysctrl success.\n"); -} - -EXPORT_SYMBOL(hisi_sysctl_get_hllc_crc_ecc); -EXPORT_SYMBOL(hisi_sysctl_get_hllc_link_status); -EXPORT_SYMBOL(hisi_sysctl_set_hllc_mem_ecc); -EXPORT_SYMBOL(hisi_sysctl_get_hllc_mem_ecc); -EXPORT_SYMBOL(hisi_sysctl_get_ddrc_mem_ecc); -EXPORT_SYMBOL(hisi_sysctl_clr_ddrc_mem_ecc); -EXPORT_SYMBOL(his_hllc_init); -EXPORT_SYMBOL(his_hllc_deinit); -EXPORT_SYMBOL(hip_sysctrl_probe); -EXPORT_SYMBOL(hip_sysctrl_remove); - -module_init(his_sysctrl_init); -module_exit(his_sysctrl_exit); - -MODULE_DESCRIPTION("sysctrl for hisilicon platform"); -MODULE_VERSION(SYSCTL_DRIVER_VERSION); -MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:hip-sysctl"); diff --git a/drivers/soc/hisilicon/sysctl/sysctl_drv.h b/drivers/soc/hisilicon/sysctl/sysctl_drv.h deleted file mode 100644 index ccc3234858d5e..0000000000000 --- a/drivers/soc/hisilicon/sysctl/sysctl_drv.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _SYSCTL_DRV_H_ -#define _SYSCTL_DRV_H_ - -/* SYSCTRL ERR */ -#define SYSCTL_ERR_OK 0 /* Ok */ -#define SYSCTL_ERR_PARAM 1 /* Invalid parameter */ -#define SYSCTL_ERR_FAILED 2 /* Operation failed */ -#define SYSCTL_ERR_PORT 3 /* Invalid port */ -#define SYSCTL_ERR_TIMEOUT 4 /* Operation time out */ -#define SYSCTL_ERR_NOMATCH 5 /* Version not match */ -#define SYSCTL_ERR_EXIST 6 /* Entry exists */ -#define SYSCTL_ERR_NOMEM 7 /* Out of memory */ -#define SYSCTL_ERR_INIT 8 /* Feature not initialized */ -#define SYSCTL_ERR_FAULT 9 /* Invalid address */ -#define SYSCTL_ERR_PERM 10 /* Operation not permitted */ -#define SYSCTL_ERR_EMPTY 11 /* Table empty */ -#define SYSCTL_ERR_FULL 12 /* Table full */ -#define SYSCTL_ERR_NOT_FOUND 13 /* Not found */ -#define SYSCTL_ERR_BUSY 14 /* Device or resource busy */ -#define SYSCTL_ERR_RESOURCE 15 /* No resources for operation */ -#define SYSCTL_ERR_CONFIG 16 /* Invalid configuration */ -#define SYSCTL_ERR_UNAVAIL 17 /* Feature unavailable */ -#define SYSCTL_ERR_CRC 18 /* CRC check failed */ -#define SYSCTL_ERR_NXIO 19 /* No such device or address */ -#define SYSCTL_ERR_ROLLBACK 20 /* chip rollback fail */ -#define SYSCTL_ERR_LEN 32 /* Length too short or too long */ -#define SYSCTL_ERR_UNSUPPORT 0xFF /* Feature not supported */ - -#define CHIP_VER_BASE 0x20107E238 -#define PEH_REG_ADDR (0xd7d00008) -#define HLLC0_REG_BASE (0x000200080000) -#define HLLC1_REG_BASE (0x000200090000) -#define HLLC2_REG_BASE (0x0002000a0000) -#define PCS0_REG_BASE (0x0002000c0000) -#define PA_REG_BASE (0x0002001d0000) -#define DDRC0_TB_REG_BASE (0x000094d20000) -#define DDRC0_TA_REG_BASE (0x00009cd20000) - -#define HLLC_INTLV_MODE_2PX8 0x0 -#define HLLC_INTLV_MODE_2PX16 0x1 -#define HLLC_INTLV_MODE_2PX24 0x2 -#define HLLC_INTLV_MODE_4PX8 0x3 -#define HLLC_INTLV_MODE_3P1 0x5 -#define HLLC_INTLV_MODE_3P2 0x6 - -#define CHIP_VERSION_ES (0x1) -#define HLLC_CHIP_MODULE_ES (0x400000000000) -#define HLLC_CHIP_MODULE_CS (0x200000000000) -#define HLLC_NUM_MAX (0x3) -#define HLLC_CH_NUM_MAX (0x3) -#define TOTEM_NUM_MAX (0x2) -#define TOTEM_TA_NUM (0x0) -#define TOTEM_TB_NUM (0x1) -#define DDRC_CH_NUM_MAX (0x4) -#define DDRC_RANK_NUM_MAX (0x8) -#define HLLC_LANE_NUM_MAX (0x8) -#define CHIP_ID_NUM_MAX (0x4) -#define DDRC_ECC_EN (0x5001) - -#define RSV_CHAR_NUM 3 - -extern unsigned int g_sysctrl_debug; - -#define debug_sysctrl_print(fmt...) \ -do { \ - if (g_sysctrl_debug) \ - printk(fmt); \ -} while (0) - -typedef struct { - unsigned char hllc_enable; - unsigned char rvs0[RSV_CHAR_NUM]; - unsigned int hllc_crc_ecc[HLLC_NUM_MAX]; -} hllc_crc_ecc_info; - -typedef union { - /* Define the struct bits */ - struct { - unsigned int hllc_enable : 8 ; /* [7..0] 0:hllc0, 1:hllc1, 2:hllc2 */ - unsigned int hllc_link_status : 8 ; /* [15..8] */ - unsigned int rsv1 : 16 ; /* [31..16] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} hllc_link_sta_info; - -typedef union { - /* Define the struct bits */ - struct { - unsigned int hydra_tx_ch0_bit1_ecc_err : 1 ; /* [0] */ - unsigned int hydra_tx_ch1_bit1_ecc_err : 1 ; /* [1] */ - unsigned int hydra_tx_ch2_bit1_ecc_err : 1 ; /* [2] */ - unsigned int phy_tx_retry_bit1_ecc_err : 1 ; /* [3] */ - unsigned int hydra_rx_ch0_bit1_ecc_err : 1 ; /* [4] */ - unsigned int hydra_rx_ch1_bit1_ecc_err : 1 ; /* [5] */ - unsigned int hydra_rx_ch2_bit1_ecc_err : 1 ; /* [6] */ - unsigned int hydra_tx_ch0_bit2_ecc_err : 1 ; /* [7] */ - unsigned int hydra_tx_ch1_bit2_ecc_err : 1 ; /* [8] */ - unsigned int hydra_tx_ch2_bit2_ecc_err : 1 ; /* [9] */ - unsigned int phy_tx_retry_bit2_ecc_err : 1 ; /* [10] */ - unsigned int hydra_rx_ch0_bit2_ecc_err : 1 ; /* [11] */ - unsigned int hydra_rx_ch1_bit2_ecc_err : 1 ; /* [12] */ - unsigned int hydra_rx_ch2_bit2_ecc_err : 1 ; /* [13] */ - unsigned int rsv1 : 18 ; /* [31..14] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} hllc_mem_ecc_info; - -typedef struct { - unsigned char ddrc_mem_secc_en; - unsigned char rsv0[RSV_CHAR_NUM]; - unsigned int ddrc_mem_secc; - unsigned int ddrc_mem_mecc; -} ddrc_mem_ecc_info; - -u64 get_chip_base(void); - -#endif /* _SYSCTL_DRV_H_ */ diff --git a/drivers/soc/hisilicon/sysctl/sysctl_local_ras.c b/drivers/soc/hisilicon/sysctl/sysctl_local_ras.c deleted file mode 100644 index 803e97f6afc8c..0000000000000 --- a/drivers/soc/hisilicon/sysctl/sysctl_local_ras.c +++ /dev/null @@ -1,594 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/delay.h> -#include <linux/io.h> -#include <acpi/ghes.h> -#include <acpi/apei.h> -#include <ras/ras_event.h> -#include <../drivers/acpi/apei/apei-internal.h> -#include "sysctl_local_ras.h" -#include "sysctl_drv.h" -#include "sysctl_dfx.h" - -static LIST_HEAD(hisi_ghes_list); -static DEFINE_MUTEX(hisi_ghes_mutex); - -#define HISI_GHES_ESTATUS_MAX_SIZE 65536 - -#define SUBCTRL_REG_BASE 0x000201070000 -#define SUBCTRL_TDH_RESET_OFFSET 0xa58 -#define SUBCTRL_TDH_UNRESET_OFFSET 0xa5c - -#define TDH_REG_BASE 0x000201190000 -#define TDH_MEM_ACCESS_OFFSET 0x140 - -#define TDH_IRQ_CNT_MAX 0x1000 - -static u32 g_sysctl_tdh_irq_cnt; -static void __iomem *sysctl_subctrl_tdh_priv[CHIP_ID_NUM_MAX]; -static void __iomem *sysctl_tdh_priv[CHIP_ID_NUM_MAX]; - -static int sysctl_tdh_init(void) -{ - u32 chip_id; - u64 addr; - u64 tdh_addr; - u64 chip_module_base; - - pr_info("[INFO] %s start.\n", __func__); - - chip_module_base = get_chip_base(); - - for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) { - addr = (u64)chip_id * chip_module_base + SUBCTRL_REG_BASE; - sysctl_subctrl_tdh_priv[chip_id] = ioremap(addr, (u64)0x10000); - if (!sysctl_subctrl_tdh_priv[chip_id]) - pr_err("chip=%u, subctrl ioremap failed\n", chip_id); - - tdh_addr = (u64)chip_id * chip_module_base + TDH_REG_BASE; - sysctl_tdh_priv[chip_id] = ioremap(tdh_addr, (u64)0x10000); - if (!sysctl_tdh_priv[chip_id]) - pr_err("chip=%u, tdh ioremap failed\n", chip_id); - } - - return SYSCTL_ERR_OK; -} - -static void sysctl_tdh_deinit(void) -{ - u8 chip_id; - - for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) { - if (sysctl_subctrl_tdh_priv[chip_id]) - iounmap((void *)sysctl_subctrl_tdh_priv[chip_id]); - - if (sysctl_tdh_priv[chip_id]) - iounmap((void *)sysctl_tdh_priv[chip_id]); - } -} - -static int sysctl_tdh_reset(u8 chip_id) -{ - void __iomem *addr; - - if (chip_id >= CHIP_ID_NUM_MAX) { - pr_err("err chip id %u %s\n", chip_id, __func__); - return SYSCTL_ERR_PARAM; - } - - if (!sysctl_subctrl_tdh_priv[chip_id]) - return SYSCTL_ERR_PARAM; - - addr = sysctl_subctrl_tdh_priv[chip_id] + SUBCTRL_TDH_RESET_OFFSET; - writel(0x3, addr); - - return SYSCTL_ERR_OK; -} - -static int sysctl_tdh_unreset(u8 chip_id) -{ - void __iomem *addr; - - if (chip_id >= CHIP_ID_NUM_MAX) { - pr_err("err chip id %u %s\n", chip_id, __func__); - return SYSCTL_ERR_PARAM; - } - - if (!sysctl_subctrl_tdh_priv[chip_id]) - return SYSCTL_ERR_PARAM; - - addr = sysctl_subctrl_tdh_priv[chip_id] + SUBCTRL_TDH_UNRESET_OFFSET; - writel(0x3, addr); - - return SYSCTL_ERR_OK; -} - -static int sysctl_tdh_mem_access_open(u8 chip_id) -{ - void __iomem *addr; - - if (chip_id >= CHIP_ID_NUM_MAX) { - pr_err("err chip id %u %s\n", chip_id, __func__); - return SYSCTL_ERR_PARAM; - } - - if (!sysctl_tdh_priv[chip_id]) - return SYSCTL_ERR_PARAM; - - addr = sysctl_tdh_priv[chip_id] + TDH_MEM_ACCESS_OFFSET; - writel(0x0, addr); - - return SYSCTL_ERR_OK; -} - -static inline bool sysctl_is_hest_type_generic_v2(struct ghes *ghes) -{ - return ghes->generic->header.type == ACPI_HEST_TYPE_GENERIC_ERROR_V2; -} - -static int sysctl_map_gen_v2(const struct ghes *ghes) -{ - return apei_map_generic_address(&ghes->generic_v2->read_ack_register); -} - -static void sysctl_unmap_gen_v2(const struct ghes *ghes) -{ - apei_unmap_generic_address(&ghes->generic_v2->read_ack_register); -} -static int sysctl_correlation_reg_report(const struct hisi_oem_type1_err_sec *ras_cper) -{ - switch (ras_cper->module_id) { - case OEM1_MODULE_TDH: - pr_info("[INFO] SYSCTL RAS tdh correlation_reg info:\n"); - break; - case OEM1_MODULE_USB: - if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB0) { - pr_info("[INFO] SYSCTL RAS usb0 correlation_reg info:\n"); - } else if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB1) { - pr_info("[INFO] SYSCTL RAS usb1 correlation_reg info:\n"); - } else if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB2) { - pr_info("[INFO] SYSCTL RAS usb2 correlation_reg info:\n"); - } else { - pr_err("[ERROR] SYSCTL RAS usb sub_module_id[0x%x] is error.\n", ras_cper->sub_mod_id); - return -1; - } - break; - case OEM1_MODULE_SATA: - pr_info("[INFO] SYSCTL RAS sata correlation_reg info:\n"); - break; - default: - pr_err("[ERROR] SYSCTL RAS module_id[0x%x] is error.\n", ras_cper->module_id); - return -1; - } - - pr_info("[INFO] SYSCTL RAS socket_id: %x.\n", ras_cper->socket_id); - pr_info("[INFO] SYSCTL RAS nimbus_id: %x.\n", ras_cper->nimbus_id); - pr_info("[INFO] SYSCTL RAS err_misc0: %x.\n", ras_cper->err_misc0); - pr_info("[INFO] SYSCTL RAS err_misc1: %x.\n", ras_cper->err_misc1); - pr_info("[INFO] SYSCTL RAS err_misc2: %x.\n", ras_cper->err_misc2); - pr_info("[INFO] SYSCTL RAS err_misc3: %x.\n", ras_cper->err_misc3); - pr_info("[INFO] SYSCTL RAS err_misc4: %x.\n", ras_cper->err_misc4); - pr_info("[INFO] SYSCTL RAS err_addrl: %x.\n", ras_cper->err_addrl); - pr_info("[INFO] SYSCTL RAS err_addrh: %x.\n", ras_cper->err_addrh); - - return 0; -} - -static int sysctl_do_recovery(const struct hisi_oem_type1_err_sec *ras_cper) -{ - int ret = 0; - - switch (ras_cper->module_id) { - case OEM1_MODULE_TDH: - g_sysctl_tdh_irq_cnt++; - - sysctl_tdh_reset(ras_cper->socket_id); - pr_info("[INFO] SYSCTL RAS tdh of chip[%d] reset.\n", ras_cper->socket_id); - pr_info("[INFO] SYSCTL RAS sysctl_tdh_irq_cnt[%d].\n", g_sysctl_tdh_irq_cnt); - udelay(20); /* Delay 20 subtleties */ - - if (g_sysctl_tdh_irq_cnt <= TDH_IRQ_CNT_MAX) { - sysctl_tdh_unreset(ras_cper->socket_id); - pr_info("[INFO] SYSCTL RAS tdh of chip[%d] unreset.\n", ras_cper->socket_id); - - sysctl_tdh_mem_access_open(ras_cper->socket_id); - pr_info("[INFO] SYSCTL RAS tdh of chip[%d] mem access open.\n", - ras_cper->socket_id); - } else { - pr_err("[ERROR] SYSCTL RAS tdh of chip[%d] unreset %d times, won't unreset.\n", - ras_cper->socket_id, TDH_IRQ_CNT_MAX); - } - break; - case OEM1_MODULE_USB: - if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB0) { - pr_info("[INFO] SYSCTL RAS usb0 error.\n"); - } else if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB1) { - pr_info("[INFO] SYSCTL RAS usb1 error.\n"); - } else if (ras_cper->sub_mod_id == OEM1_SUB_MODULE_USB2) { - pr_info("[INFO] SYSCTL RAS usb2 error.\n"); - } else { - pr_err("[ERROR] SYSCTL RAS usb sub_module_id[0x%x] is error.\n", ras_cper->sub_mod_id); - return ret; - } - break; - case OEM1_MODULE_SATA: - pr_info("[INFO] SYSCTL RAS sata error.\n"); - break; - default: - pr_err("[ERROR] SYSCTL RAS module_id[0x%x] is error, has not match process in sysctl.\n", - ras_cper->module_id); - return ret; - } - - (void)sysctl_correlation_reg_report(ras_cper); - - return ret; -} - -static int sysctl_hest_hisi_parse_ghes_count(struct acpi_hest_header *hest_hdr, void *data) -{ - int *count = data; - - if (hest_hdr->type == ACPI_HEST_TYPE_GENERIC_ERROR || - hest_hdr->type == ACPI_HEST_TYPE_GENERIC_ERROR_V2) - (*count)++; - return 0; -} - -static struct ghes *sysctl_ghes_new(struct acpi_hest_generic *sysctl_generic) -{ - struct ghes *sysctl_ghes; - size_t err_block_length; - int ret = 0; - - sysctl_ghes = kzalloc(sizeof(*sysctl_ghes), GFP_KERNEL); - if (!sysctl_ghes) - return ERR_PTR((long)-ENOMEM); - - sysctl_ghes->generic = sysctl_generic; - if (sysctl_is_hest_type_generic_v2(sysctl_ghes)) { - ret = sysctl_map_gen_v2(sysctl_ghes); - if (ret) - goto err_free; - } - - ret = apei_map_generic_address(&sysctl_generic->error_status_address); - if (ret) - goto err_unmap_read_ack_addr; - - err_block_length = sysctl_generic->error_block_length; - if (err_block_length > HISI_GHES_ESTATUS_MAX_SIZE) { - pr_err("SYSCTL RAS Error status block length is too long: %u for " - "generic hardware error source: %d.\n", - (u32)err_block_length, sysctl_generic->header.source_id); - err_block_length = HISI_GHES_ESTATUS_MAX_SIZE; - } - - sysctl_ghes->estatus = NULL; - - return sysctl_ghes; - -err_unmap_read_ack_addr: - if (sysctl_is_hest_type_generic_v2(sysctl_ghes)) - sysctl_unmap_gen_v2(sysctl_ghes); -err_free: - kfree(sysctl_ghes); - return ERR_PTR((long)ret); -} - -static int sysctl_hest_hisi_parse_ghes(struct acpi_hest_header *hest_hdr, void *data) -{ - struct acpi_hest_generic *sysctl_generic; - struct ghes *sysctl_ghes = NULL; - (void)data; - - sysctl_generic = container_of(hest_hdr, struct acpi_hest_generic, header); - if (!sysctl_generic->enabled) - return 0; - - debug_sysctrl_print("[DBG] SYSCTL RAS ghes source id: %x.\n", - hest_hdr->source_id); - debug_sysctrl_print("[DBG] SYSCTL RAS ghes error_block_length: %x.\n", - sysctl_generic->error_block_length); - debug_sysctrl_print("[DBG] SYSCTL RAS ghes notify type: %x.\n", - sysctl_generic->notify.type); - - sysctl_ghes = sysctl_ghes_new(sysctl_generic); - if (!sysctl_ghes) { - pr_err("[ERROR] SYSCTL RAS sysctl_ghes is null.\n"); - return -ENOMEM; - } - - list_add(&sysctl_ghes->list, &hisi_ghes_list); - - return 0; -} - -static int sysctl_ghes_read_estatus_pre(struct ghes **sysctl_ghes, int silent) -{ - struct acpi_hest_generic *g = (*sysctl_ghes)->generic; - u32 err_block_length; - phys_addr_t buf_paddr; - int ret; - - ret = apei_read(&buf_paddr, &g->error_status_address); - if (ret) { - if (!silent && printk_ratelimit()) - pr_err("[ERROR] SYSCTL RAS apei_read fail, source_id: %d.\n", g->header.source_id); - - pr_err("[ERROR] SYSCTL RAS apei_read fail, ret: %d.\n", ret); - return -EIO; - } - - if (!buf_paddr) { - pr_err("[ERROR] SYSCTL RAS buf_paddr is null.\n"); - return -ENOENT; - } - - err_block_length = g->error_block_length; - if (err_block_length > HISI_GHES_ESTATUS_MAX_SIZE) { - pr_info("[INFO] SYSCTL RAS error_block_length: %u, source_id: %d.\n", err_block_length, g->header.source_id); - err_block_length = HISI_GHES_ESTATUS_MAX_SIZE; - } - - (*sysctl_ghes)->estatus = ioremap_wc(buf_paddr, err_block_length); - if (!((*sysctl_ghes)->estatus)) { - pr_err("estatus ioremap failed\n"); - return -ENOENT; - } - - if (!((*sysctl_ghes)->estatus->block_status)) { - iounmap((*sysctl_ghes)->estatus); - return -ENOENT; - } - - (*sysctl_ghes)->buffer_paddr = buf_paddr; - (*sysctl_ghes)->flags |= GHES_TO_CLEAR; - - return 0; -} - -static int sysctl_ghes_read_estatus(struct ghes *sysctl_ghes, int silent) -{ - u32 len; - int ret; - - ret = sysctl_ghes_read_estatus_pre(&sysctl_ghes, silent); - if (ret) - return ret; - - ret = -EIO; - len = cper_estatus_len(sysctl_ghes->estatus); - if (len < sizeof(*sysctl_ghes->estatus)) { - pr_err("[ERROR] SYSCTL RAS len[%d] less than sizeof(*ghes->estatus)[%ld].\n", - len, sizeof(*sysctl_ghes->estatus)); - goto error_read_block; - } - - if (len > sysctl_ghes->generic->error_block_length) { - pr_err("[ERROR] SYSCTL RAS len[%d] more than error_block_length[%d].\n", - len, sysctl_ghes->generic->error_block_length); - goto error_read_block; - } - - if (cper_estatus_check_header(sysctl_ghes->estatus)) { - pr_err("[ERROR] SYSCTL RAS cper_estatus_check_header fail.\n"); - goto error_read_block; - } - - if (cper_estatus_check(sysctl_ghes->estatus)) { - pr_err("[ERROR] SYSCTL RAS cper_estatus_check fail.\n"); - goto error_read_block; - } - - ret = 0; - return ret; - -error_read_block: - pr_err("[ERROR] SYSCTL RAS info of ghes error status block is error.\n"); - iounmap(sysctl_ghes->estatus); - - pr_err("[ERROR] SYSCTL RAS read error status block fail.\n"); - return ret; -} - -void sysctl_ghes_clear_estatus(struct ghes *sysctl_ghes) -{ - sysctl_ghes->estatus->block_status = 0; - if (!(sysctl_ghes->flags & GHES_TO_CLEAR)) - return; - - sysctl_ghes->flags &= ~GHES_TO_CLEAR; -} - -static void sysctl_ghes_do_proc(struct ghes *sysctl_ghes, - struct acpi_hest_generic_status *sysct_estatus) -{ - struct acpi_hest_generic_data *gdata = NULL; - guid_t *sec_type = NULL; - struct hisi_oem_type1_err_sec *ras_cper = NULL; - struct cper_sec_proc_arm *arm_ras_cper = NULL; - (void)sysctl_ghes; - - apei_estatus_for_each_section(sysct_estatus, gdata) { - sec_type = (guid_t *)gdata->section_type; - - sysctl_dfx_do_ras(gdata); - if (guid_equal(sec_type, &CPER_SEC_HISI_OEM_1)) { - ras_cper = acpi_hest_get_payload(gdata); - (void)sysctl_do_recovery(ras_cper); - } else if (guid_equal(sec_type, &CPER_SEC_PROC_ARM)) { - arm_ras_cper = acpi_hest_get_payload(gdata); - if (arm_ras_cper->err_info_num != 1) { - pr_err("[ERROR] SYSCTL RAS err_info_num[0x%x] is error.\n", - arm_ras_cper->err_info_num); - return; - } - } - - cper_estatus_print("[INFO] SYSCTL RAS HISILICON Error : ", - sysctl_ghes->estatus); - } -} - -static int sysctl_ghes_proc(struct ghes *sysctl_ghes) -{ - int ret; - - ret = sysctl_ghes_read_estatus(sysctl_ghes, 0); - if (ret) - return ret; - - sysctl_ghes_do_proc(sysctl_ghes, sysctl_ghes->estatus); - - iounmap(sysctl_ghes->estatus); - - return ret; -} - -static int sysctl_hisi_error_handler(struct work_struct *work) -{ - int ret = 0; - struct ghes *sysctl_ghes = NULL; - (void)work; - - list_for_each_entry(sysctl_ghes, &hisi_ghes_list, list) { - if (!sysctl_ghes_proc(sysctl_ghes)) - ret = NOTIFY_OK; - } - - return ret; -} - -/* acpi hisi hest init */ -static void sysctl_acpi_hisi_hest_init(void) -{ - int ret; - unsigned int ghes_count = 0; - - debug_sysctrl_print("[DBG] SYSCTL RAS %s start.\n", __func__); - - if (hest_disable) { - pr_err("[ERROR] SYSCTL RAS Table parsing disabled.\n"); - return; - } - - ret = apei_hest_parse(sysctl_hest_hisi_parse_ghes_count, &ghes_count); - if (ret) { - pr_err("[ERROR] SYSCTL RAS hest_hisi_parse_ghes_count fail.\n"); - return; - } - debug_sysctrl_print("[DBG] SYSCTL RAS Get ghes count: %d.\n", ghes_count); - - ret = apei_hest_parse(sysctl_hest_hisi_parse_ghes, &ghes_count); - if (ret) { - pr_err("[ERROR] SYSCTL RAS hest_hisi_parse_ghes fail.\n"); - return; - } -} - -int sysctl_notify_hed(struct notifier_block *that, unsigned long event, void *data) -{ - int ret; - (void)event; - (void)data; - (void)that; - - ret = sysctl_hisi_error_handler(NULL); - - return ret; -} - -static struct notifier_block g_sysctl_ghes_hisi_notifier_hed = { - .notifier_call = sysctl_notify_hed, - .priority = INT_MAX, -}; - -int hip_sysctl_local_ras_init(void) -{ - int ret; - - sysctl_proc_init(); - - ret = sysctl_tdh_init(); - if (ret != SYSCTL_ERR_OK) { - pr_err("[ERROR] SYSCTL RAS sysctl_tdh_init fail.\n"); - return ret; - } - - sysctl_acpi_hisi_hest_init(); - - ret = register_acpi_hed_notifier(&g_sysctl_ghes_hisi_notifier_hed); - if (ret != SYSCTL_ERR_OK) { - pr_err("[ERROR] SYSCTL RAS register_acpi_hed_notifier fail.\n"); - return ret; - } - - ret = sysctl_tdh_mem_access_open(0); - if (ret != SYSCTL_ERR_OK) { - pr_err("[ERROR] SYSCTL RAS sysctl_tdh_mem_access_open fail.\n"); - return ret; - } - - return ret; -} - -static void his_ghes_list_free(void) -{ - struct ghes *node = NULL; - struct ghes *tmp_node = NULL; - - list_for_each_entry(node, &hisi_ghes_list, list) { - if (!node) - continue; - - apei_unmap_generic_address(&node->generic->error_status_address); - - if (sysctl_is_hest_type_generic_v2(node)) - sysctl_unmap_gen_v2(node); - - /* Release the node of the previous loop. */ - if (tmp_node != NULL) { - kfree(tmp_node); - tmp_node = NULL; - } - - /* Record the node of the current loop. */ - tmp_node = node; - - /* hisi_ghes_list isn't a member of node. */ - if (node->list.next == &hisi_ghes_list) { - node = NULL; - break; - } - } - - if (tmp_node != NULL) { - kfree(tmp_node); - tmp_node = NULL; - } -} - -void hip_sysctl_local_ras_exit(void) -{ - unregister_acpi_hed_notifier(&g_sysctl_ghes_hisi_notifier_hed); - sysctl_proc_exit(); - sysctl_tdh_deinit(); - his_ghes_list_free(); - - pr_info("[INFO] hip sysctl local ras exit.\n"); -} diff --git a/drivers/soc/hisilicon/sysctl/sysctl_local_ras.h b/drivers/soc/hisilicon/sysctl/sysctl_local_ras.h deleted file mode 100644 index 8f4dd207b46b3..0000000000000 --- a/drivers/soc/hisilicon/sysctl/sysctl_local_ras.h +++ /dev/null @@ -1,250 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef _SYSCTL_LOCAL_RAS_H_ -#define _SYSCTL_LOCAL_RAS_H_ - -enum { - OEM1_SUB_MODULE_USB0 = 0, - OEM1_SUB_MODULE_USB1, - OEM1_SUB_MODULE_USB2, -}; - -enum { - OEM1_MODULE_PLL = 1, - OEM1_MODULE_SLLC = 2, - OEM1_MODULE_SIOE = 4, - OEM1_MODULE_POE = 5, - OEM1_MODULE_DISP = 8, - OEM1_MODULE_TDH = 9, - OEM1_MODULE_GIC = 13, - OEM1_MODULE_RDE = 14, - OEM1_MODULE_SAS = 15, - OEM1_MODULE_SATA = 16, - OEM1_MODULE_USB = 17, -}; - -enum { - OEM2_MODULE_SMMU = 0, - OEM2_MODULE_HHA = 1, - OEM2_MODULE_PA = 2, - OEM2_MODULE_HLLC = 3, - OEM2_MODULE_DDRC = 4, -}; - -enum { - PCIE_LOCAL_MODULE_AP = 0, - PCIE_LOCAL_MODULE_TL = 1, - PCIE_LOCAL_MODULE_MAC = 2, - PCIE_LOCAL_MODULE_DL = 3, - PCIE_LOCAL_MODULE_SDI = 4, -}; - -#define HISI_OEM_VALID_SOC_ID BIT(0) -#define HISI_OEM_VALID_SOCKET_ID BIT(1) -#define HISI_OEM_VALID_NIMBUS_ID BIT(2) -#define HISI_OEM_VALID_MODULE_ID BIT(3) -#define HISI_OEM_VALID_SUB_MODULE_ID BIT(4) -#define HISI_OEM_VALID_ERR_SEVERITY BIT(5) - -#define HISI_OEM_TYPE2_VALID_ERR_FR BIT(6) -#define HISI_OEM_TYPE2_VALID_ERR_CTRL BIT(7) -#define HISI_OEM_TYPE2_VALID_ERR_STATUS BIT(8) -#define HISI_OEM_TYPE2_VALID_ERR_ADDR BIT(9) -#define HISI_OEM_TYPE2_VALID_ERR_MISC_0 BIT(10) -#define HISI_OEM_TYPE2_VALID_ERR_MISC_1 BIT(11) - -#define HISI_PCIE_LOCAL_VALID_VERSION BIT(0) -#define HISI_PCIE_LOCAL_VALID_SOC_ID BIT(1) -#define HISI_PCIE_LOCAL_VALID_SOCKET_ID BIT(2) -#define HISI_PCIE_LOCAL_VALID_NIMBUS_ID BIT(3) -#define HISI_PCIE_LOCAL_VALID_SUB_MODULE_ID BIT(4) -#define HISI_PCIE_LOCAL_VALID_CORE_ID BIT(5) -#define HISI_PCIE_LOCAL_VALID_PORT_ID BIT(6) -#define HISI_PCIE_LOCAL_VALID_ERR_TYPE BIT(7) -#define HISI_PCIE_LOCAL_VALID_ERR_SEVERITY BIT(8) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_0 BIT(9) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_1 BIT(10) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_2 BIT(11) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_3 BIT(12) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_4 BIT(13) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_5 BIT(14) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_6 BIT(15) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_7 BIT(16) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_8 BIT(17) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_9 BIT(18) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_10 BIT(19) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_11 BIT(20) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_12 BIT(21) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_13 BIT(22) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_14 BIT(23) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_15 BIT(24) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_16 BIT(25) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_17 BIT(26) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_18 BIT(27) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_19 BIT(28) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_20 BIT(29) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_21 BIT(30) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_22 BIT(31) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_23 BIT(32) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_24 BIT(33) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_25 BIT(34) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_26 BIT(35) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_27 BIT(36) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_28 BIT(37) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_29 BIT(38) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_30 BIT(39) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_31 BIT(40) -#define HISI_PCIE_LOCAL_VALID_ERR_MISC_32 BIT(41) - -#define HISI_PCIE_VENDOR_ID 0x19e5 - -/* NET Device ID */ -#define HISI_PCIE_DEV_ID_GE 0xa220 -#define HISI_PCIE_DEV_ID_25GE 0xa221 -#define HISI_PCIE_DEV_ID_25GE_RDMA 0xa222 -#define HISI_PCIE_DEV_ID_50GE_RDMA 0xa224 -#define HISI_PCIE_DEV_ID_100G_RDMA 0xa226 -#define HISI_PCIE_DEV_ID_SDI 0xa22a -#define HISI_PCIE_DEV_ID_100G_VF 0xa22e -#define HISI_PCIE_DEV_ID_100G_RDMA_VF 0xa22f - -/* HPRE Device ID */ -#define HISI_PCIE_DEV_ID_ZIP 0xa250 -#define HISI_PCIE_DEV_ID_SEC 0xa255 -#define HISI_PCIE_DEV_ID_HPRE 0xa258 - -#define CPER_SEC_HISI_OEM_1 \ - GUID_INIT(0x1F8161E1, 0x55D6, 0x41E6, 0xBD, 0x10, 0x7A,\ - 0xFD, 0x1D, 0xC5, 0xF7, 0xC5) - -#define CPER_SEC_HISI_OEM_2 \ - GUID_INIT(0x45534EA6, 0xCE23, 0x4115, 0x85, 0x35, 0xE0, 0x7A, \ - 0xB3, 0xAE, 0xF9, 0x1D) - -#define CPER_SEC_HISI_PCIE_LOCAL \ - GUID_INIT(0xb2889fc9, 0xe7d7, 0x4f9d, 0xa8, 0x67, 0xaf, 0x42, \ - 0xe9, 0x8b, 0xe7, 0x72) - -struct oem1_validation_bits { - u32 soc_id_vald : 1; - u32 socket_id_vald : 1; - u32 nimbus_id_vald : 1; - u32 module_id_vald : 1; - u32 submod_id_vald : 1; - u32 err_sever_vald : 1; - u32 err_misc0_vald : 1; - u32 err_misc1_vald : 1; - u32 err_misc2_vald : 1; - u32 err_misc3_vald : 1; - u32 err_misc4_vald : 1; - u32 err_addr_vald : 1; - u32 reserv : 20; -}; - -struct hisi_oem_type1_err_sec { - struct oem1_validation_bits validation_bits; - u8 version; - u8 soc_id; - u8 socket_id; - u8 nimbus_id; - u8 module_id; - u8 sub_mod_id; - u8 err_severity; - u8 resv1; - u32 err_misc0; - u32 err_misc1; - u32 err_misc2; - u32 err_misc3; - u32 err_misc4; - u32 err_addrl; - u32 err_addrh; -}; - -struct hisi_oem_type2_err_sec { - u32 val_bits; - u8 version; - u8 soc_id; - u8 socket_id; - u8 nimbus_id; - u8 module_id; - u8 sub_module_id; - u8 err_severity; - u8 reserv; - u32 err_fr_0; - u32 err_fr_1; - u32 err_ctrl_0; - u32 err_ctrl_1; - u32 err_status_0; - u32 err_status_1; - u32 err_addr_0; - u32 err_addr_1; - u32 err_misc0_0; - u32 err_misc0_1; - u32 err_misc1_0; - u32 err_misc1_1; -}; - -struct hisi_pcie_local_err_sec { - u64 val_bits; - u8 version; - u8 soc_id; - u8 socket_id; - u8 nimbus_id; - u8 sub_module_id; - u8 core_id; - u8 port_id; - u8 err_severity; - u16 err_type; - u8 reserv[2]; /* reserv 2 bytes */ - u32 err_misc_0; - u32 err_misc_1; - u32 err_misc_2; - u32 err_misc_3; - u32 err_misc_4; - u32 err_misc_5; - u32 err_misc_6; - u32 err_misc_7; - u32 err_misc_8; - u32 err_misc_9; - u32 err_misc_10; - u32 err_misc_11; - u32 err_misc_12; - u32 err_misc_13; - u32 err_misc_14; - u32 err_misc_15; - u32 err_misc_16; - u32 err_misc_17; - u32 err_misc_18; - u32 err_misc_19; - u32 err_misc_20; - u32 err_misc_21; - u32 err_misc_22; - u32 err_misc_23; - u32 err_misc_24; - u32 err_misc_25; - u32 err_misc_26; - u32 err_misc_27; - u32 err_misc_28; - u32 err_misc_29; - u32 err_misc_30; - u32 err_misc_31; - u32 err_misc_32; -}; - -int hip_sysctl_local_ras_init(void); -void hip_sysctl_local_ras_exit(void); - -#endif diff --git a/drivers/soc/hisilicon/sysctl/sysctl_pmbus.c b/drivers/soc/hisilicon/sysctl/sysctl_pmbus.c deleted file mode 100644 index 92eeba61df8a3..0000000000000 --- a/drivers/soc/hisilicon/sysctl/sysctl_pmbus.c +++ /dev/null @@ -1,720 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/io.h> -#include <linux/delay.h> -#include "sysctl_drv.h" -#include "sysctl_pmbus.h" - -#define SLAVE_ADDR_MAX (1 << 7) -#define CPU_VOL_MIN 500 - -static void __iomem *g_sysctl_pmbus_base[CHIP_ID_NUM_MAX]; - -static void his_sysctrl_reg_rd(const void __iomem *addr, u32 reg, unsigned int *val) -{ - *val = readl(addr + reg); -} - -static void his_sysctrl_reg_wr(void __iomem *addr, u32 reg, unsigned int val) -{ - writel(val, addr + reg); -} - -static int sysctl_pmbus_init(void) -{ - u32 chip_id; - u64 addr; - u64 chip_module_base; - - pr_info("[INFO] %s.\n", __func__); - chip_module_base = get_chip_base(); - - for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) { - addr = (u64)chip_id * chip_module_base + PMBUS_REG_BASE; - g_sysctl_pmbus_base[chip_id] = ioremap(addr, (u64)0x10000); - if (!g_sysctl_pmbus_base[chip_id]) - pr_err("chip=%u, pmbus ioremap failed\n", chip_id); - } - - return SYSCTL_ERR_OK; -} - -static void sysctl_pmbus_deinit(void) -{ - u8 chip_id; - - for (chip_id = 0; chip_id < CHIP_ID_NUM_MAX; chip_id++) { - if (g_sysctl_pmbus_base[chip_id]) - iounmap((void *)g_sysctl_pmbus_base[chip_id]); - } -} - -int sysctl_reg_read8(u64 addr, u32 data_len) -{ - u32 loop; - u8 data; - void __iomem *reg_addr = NULL; - void __iomem *reg_base = NULL; - - if ((data_len >= 0x10000) || (data_len == 0)) { - pr_err("%s: data_len[%u] is ERR, be range (0x0--0x10000).\n", - __func__, data_len); - return SYSCTL_ERR_PARAM; - } - - reg_base = ioremap(addr, (u64)0x10000); - if (!reg_base) { - pr_err("%s ioremap failed\n", __func__); - return SYSCTL_ERR_FAILED; - } - - for (loop = 0; loop < data_len; loop++) { - reg_addr = reg_base + loop; - data = readb(reg_addr); - pr_info("0x%llx: 0x%2.2x\n", addr + loop, data); - } - - if (reg_base) - iounmap((void *)reg_base); - - return SYSCTL_ERR_OK; -} - -int sysctl_reg_write8(u64 addr, u8 data) -{ - void __iomem *reg_base = NULL; - - reg_base = ioremap(addr, (u64)0x100); - if (!reg_base) { - pr_err("%s ioremap failed\n", __func__); - return SYSCTL_ERR_FAILED; - } - - writeb(data, reg_base); - - if (reg_base) - iounmap((void *)reg_base); - - return SYSCTL_ERR_OK; -} - -int sysctl_reg_read32(u64 addr, u32 data_len) -{ - u32 loop; - u32 data; - void __iomem *reg_addr = NULL; - void __iomem *reg_base = NULL; - - if ((data_len >= 0x10000) || - (data_len == 0) || - ((addr % 0x4) != 0)) { - pr_err("%s: data_len[%u] is ERR, be range[0x0--0x10000].\n", __func__, data_len); - return SYSCTL_ERR_PARAM; - } - - reg_base = ioremap(addr, (u64)0x10000); - if (!reg_base) { - pr_err("%s ioremap failed\n", __func__); - return SYSCTL_ERR_FAILED; - } - - for (loop = 0; loop < data_len; loop++) { - reg_addr = reg_base + loop * 0x4; - data = readl(reg_addr); - pr_info("0x%llx: 0x%8.8x\n", addr + (u64)loop * 0x4, data); - } - - if (reg_base) - iounmap((void *)reg_base); - - return SYSCTL_ERR_OK; -} - -int sysctl_reg_write32(u64 addr, u32 data) -{ - void __iomem *reg_base = NULL; - - if ((addr % 0x4) != 0) { - pr_err("%s: reg_addr is err.\n", __func__); - return SYSCTL_ERR_PARAM; - } - - reg_base = ioremap(addr, (u64)0x100); - if (!reg_base) { - pr_err("%s ioremap failed\n", __func__); - return SYSCTL_ERR_FAILED; - } - - writel(data, reg_base); - - if (reg_base) - iounmap((void *)reg_base); - - return SYSCTL_ERR_OK; -} - -int InitPmbus(u8 chip_id) -{ - void __iomem *base = NULL; - - if (chip_id >= CHIP_ID_NUM_MAX) { - pr_err("[sysctl pmbus]read chip_id range[0x0-0x3]is err!\n"); - return SYSCTL_ERR_PARAM; - } - - base = g_sysctl_pmbus_base[chip_id]; - - debug_sysctrl_print("Initialize Pmbus\n"); - - his_sysctrl_reg_wr(base, PMBUS_WR_OPEN_OFFSET, 0x1ACCE551); - his_sysctrl_reg_wr(base, AVS_WR_OPEN_OFFSET, 0x1ACCE551); - his_sysctrl_reg_wr(base, I2C_LOCK_OFFSET, 0x36313832); - - his_sysctrl_reg_wr(base, I2C_ENABLE_OFFSET, 0); - his_sysctrl_reg_wr(base, I2C_CON_OFFSET, 0x63); - /* ulSclHigh > 1us */ - his_sysctrl_reg_wr(base, I2C_SS_SCL_HCNT_OFFSET, I2C_SS_SCLHCNT); - /* ulSclLow > 1.5us */ - his_sysctrl_reg_wr(base, I2C_SS_SCL_LCNT_OFFSET, I2C_SS_SCLLCNT); - /* set sda_hold_fs 1us > 250ns */ - his_sysctrl_reg_wr(base, I2C_SDA_HOLD_OFFSET, I2C_SS_SDA_HOLD_FS); - - his_sysctrl_reg_wr(base, I2C_ENABLE_OFFSET, 0x1); - - debug_sysctrl_print("Initialize Pmbus end\n"); - - return 0; -} - -int DeInitPmbus(u8 chip_id) -{ - void __iomem *base = NULL; - - if (chip_id >= CHIP_ID_NUM_MAX) { - pr_err("[sysctl pmbus]read chip_id range[0x0-0x3]is err!\n"); - return SYSCTL_ERR_PARAM; - } - - base = g_sysctl_pmbus_base[chip_id]; - - his_sysctrl_reg_wr(base, PMBUS_WR_OPEN_OFFSET, 0); - his_sysctrl_reg_wr(base, AVS_WR_OPEN_OFFSET, 0); - - return 0; -} - -int sysctl_pmbus_cfg(u8 chip_id, u8 addr, u8 page, u32 slave_addr) -{ - void __iomem *base = NULL; - - if ((chip_id >= CHIP_ID_NUM_MAX) || (slave_addr >= SLAVE_ADDR_MAX)) { - pr_err("[sysctl pmbus] cfg param err,chipid=0x%x,slave_addr=0x%x\n", - chip_id, slave_addr); - return SYSCTL_ERR_PARAM; - } - - base = g_sysctl_pmbus_base[chip_id]; - - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x2 << 0x8) | slave_addr); - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, addr); - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x4 << 0x8) | page); - - return 0; -} - -int sysctl_pmbus_write_common(u8 chip_id, u32 slave_addr, u32 data_len, u8 *buf) -{ - u32 i = 0; - u32 temp = 0; - u32 loop = 0x1000; - u32 temp_data; - void __iomem *base = NULL; - - if ((chip_id >= CHIP_ID_NUM_MAX) || - (slave_addr >= SLAVE_ADDR_MAX) || - (!data_len) || (data_len > PMBUS_WRITE_LEN_MAX) || - (!buf)) { - pr_err("[sysctl pmbus] write param err,chipid=0x%x,data_len=0x%x,slave_addr=0x%x!\n", - chip_id, data_len, slave_addr); - return SYSCTL_ERR_PARAM; - } - - /* clear all interrupt */ - base = g_sysctl_pmbus_base[chip_id]; - his_sysctrl_reg_wr(base, I2C_INTR_RAW_OFFSET, 0x3ffff); - - /* send: slave_addr[7bit] + write[1bit] */ - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x2 << 0x8) | slave_addr); - - /* write data */ - for (i = 0; i < data_len - 1; i++) - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, buf[i]); - - /* last data should send stop */ - temp_data = buf[i]; - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x4 << 0x8) | temp_data); - - /* poll until send done */ - for (;;) { - udelay(100); /* Delay 100 subtleties */ - - his_sysctrl_reg_rd(base, I2C_INTR_RAW_OFFSET, &temp); - - /* send data failed */ - if (temp & I2C_TX_ABRT) { - his_sysctrl_reg_rd(base, I2C_TX_ABRT_SRC_REG, &temp); - pr_err("[sysctl pmbus]write data fail, chip_id:0x%x,slave_addr:0x%x\r\n", - chip_id, slave_addr); - - his_sysctrl_reg_rd(base, I2C_CLR_TX_ABRT_REG, &temp); - return SYSCTL_ERR_FAILED; - } - - his_sysctrl_reg_rd(base, I2C_STATUS_REG, &temp); - /* send done */ - if (temp & I2C_TX_FIFO_EMPTY) { - his_sysctrl_reg_rd(base, I2C_TX_FIFO_DATA_NUM_REG, &temp); - if (temp == 0) - break; - } - - loop--; - if (loop == 0) { - pr_err("[sysctl pmbus]write data retry fail, chip_id:0x%x,slave_addr:0x%x\r\n", - chip_id, slave_addr); - return SYSCTL_ERR_FAILED; - } - } - - return SYSCTL_ERR_OK; -} - -int sysctl_pmbus_write(u8 chip_id, u8 addr, u32 slave_addr, u32 data_len, u32 buf) -{ -#define TMP_LEN_MAX 5 - u8 i; - u8 tmp[TMP_LEN_MAX] = {0}; - - if (data_len > DATA_NUM_MAX) { - pr_err("[sysctl pmbus] write param err,data_len=0x%x!\n", data_len); - return SYSCTL_ERR_PARAM; - } - - tmp[0] = addr; - for (i = 0; i < data_len; i++) - tmp[i + 1] = (buf >> (i * 0x8)) & 0xff; - - return sysctl_pmbus_write_common(chip_id, slave_addr, data_len + sizeof(addr), &tmp[0]); -} - -static int sysctl_pmbus_read_pre(void __iomem *base, u32 cmd_len, u8 *cmd, u32 slave_addr, u32 data_len) -{ - u32 i = 0; - u32 fifo_num = 0; - u32 temp_byte = 0; - - if (base == NULL) { - pr_err("[sysctl pmbus] pmbus_read_pre, base is null.\n"); - return SYSCTL_ERR_PARAM; - } - - /* clear all interrupt */ - his_sysctrl_reg_wr(base, I2C_INTR_RAW_OFFSET, 0x3ffff); - /* clear rx fifo */ - his_sysctrl_reg_rd(base, I2C_RXFLR_OFFSET, &fifo_num); - for (i = 0; i < fifo_num; i++) - his_sysctrl_reg_rd(base, I2C_DATA_CMD_OFFSET, &temp_byte); - - /* send cmd */ - if (cmd_len) { - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x2 << 0x8) | slave_addr); - for (i = 0; i < cmd_len; i++) - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, cmd[i]); - } - - /* read data */ - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x3 << 0x8) | slave_addr); - i = data_len; - while ((i - 1) > 0) { - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0x100); - i--; - } - - /* last data should send stop */ - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0x500); - - return 0; -} - -static int sysctl_pmbus_wait_data(void __iomem *base, u32 data_len) -{ - u32 i = 0; - u32 loop = 0x100; - u32 fifo_num = 0; - u32 temp_byte = 0; - - if (base == NULL) { - pr_err("[sysctl pmbus] pmbus_wait_data, base is null.\n"); - return SYSCTL_ERR_PARAM; - } - - while (loop) { - udelay(100); /* Delay 100 subtleties */ - his_sysctrl_reg_rd(base, I2C_RXFLR_OFFSET, &fifo_num); - debug_sysctrl_print("[sysctl_pmbus_read_byte]read pmbus, read rx fifo num:%d\r\n", fifo_num); - if (data_len == fifo_num) { - debug_sysctrl_print("[sysctl_pmbus_read_byte]read pmbus, Loop:%d\r\n", 0xffff - loop); - break; - } - - loop -= 1; - } - - if (loop == 0) { - pr_err("[sysctl pmbus]read pmbus error, I2C_RXFLR = %d\n", fifo_num); - for (i = 0; i < fifo_num; i++) - his_sysctrl_reg_rd(base, I2C_DATA_CMD_OFFSET, &temp_byte); - - his_sysctrl_reg_wr(base, I2C_INTR_RAW_OFFSET, 0x3FFFF); - return SYSCTL_ERR_TIMEOUT; - } - - return SYSCTL_ERR_OK; -} - -int sysctl_pmbus_read_common(u8 chip_id, struct pmbus_read_op *op) -{ - u32 ret; - u32 i = 0; - u32 temp_byte = 0; - void __iomem *base = NULL; - - if ((chip_id >= CHIP_ID_NUM_MAX) || (!op)) { - pr_err("[sysctl pmbus]read param err,chipid=0x%x!\n", chip_id); - return SYSCTL_ERR_PARAM; - } - - if ((op->slave_addr >= SLAVE_ADDR_MAX) || - (!op->data_len) || ((op->cmd_len + op->data_len) > PMBUS_READ_LEN_MAX) || - (!op->data) || ((op->cmd_len) && (!op->cmd))) { - pr_err("[sysctl pmbus]read param err,data_len=0x%x,cmd_len=0x%x,slave_addr=0x%x\n", - op->data_len, op->cmd_len, op->slave_addr); - return SYSCTL_ERR_PARAM; - } - - base = g_sysctl_pmbus_base[chip_id]; - ret = sysctl_pmbus_read_pre(base, op->cmd_len, op->cmd, op->slave_addr, op->data_len); - if (ret != SYSCTL_ERR_OK) - return ret; - - ret = sysctl_pmbus_wait_data(base, op->data_len); - if (ret != SYSCTL_ERR_OK) - return ret; - - for (i = 0; i < op->data_len; i++) { - his_sysctrl_reg_rd(base, I2C_DATA_CMD_OFFSET, &temp_byte); - op->data[i] = temp_byte & 0xff; - } - - return SYSCTL_ERR_OK; -} - -int sysctl_pmbus_read(u8 chip_id, u8 addr, u32 slave_addr, u32 data_len, u32 *buf) -{ - u32 ret; - u32 i = 0; - u32 temp_byte = 0; - u32 temp = 0; - void __iomem *base = NULL; - - if ((chip_id >= CHIP_ID_NUM_MAX) || - (data_len > DATA_NUM_MAX) || - (data_len == 0x0) || - (slave_addr >= SLAVE_ADDR_MAX)) { - pr_err("[sysctl pmbus]read param err,chipid=0x%x,data_len=0x%x,slave_addr=0x%x!\n", - chip_id, data_len, slave_addr); - return SYSCTL_ERR_PARAM; - } - - base = g_sysctl_pmbus_base[chip_id]; - - ret = sysctl_pmbus_read_pre(base, sizeof(addr), &addr, slave_addr, data_len); - if (ret != SYSCTL_ERR_OK) - return ret; - - ret = sysctl_pmbus_wait_data(base, data_len); - if (ret != SYSCTL_ERR_OK) - return ret; - - for (i = 0; i < data_len; i++) { - his_sysctrl_reg_rd(base, I2C_DATA_CMD_OFFSET, &temp_byte); - temp |= temp_byte << (i * 0x8); - } - - pr_info("[sysctl pmbus]read pmbus temp = 0x%x\n", temp); - - if (!buf) { - pr_err("[sysctl pmbus]read pmbus error, buf is NULL\n"); - return SYSCTL_ERR_PARAM; - } - - *buf = temp; - - return 0; -} - -int sysctl_cpu_voltage_password_cfg(u8 chip_id, u32 slave_addr) -{ - void __iomem *base = NULL; - - if ((chip_id >= CHIP_ID_NUM_MAX) || (slave_addr >= SLAVE_ADDR_MAX)) { - pr_err("[sysctl pmbus] voltage_password_cfg param err,chipid=0x%x,slave_addr=0x%x!\n", - chip_id, slave_addr); - return SYSCTL_ERR_PARAM; - } - - base = g_sysctl_pmbus_base[chip_id]; - - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x2 << 0x8) | slave_addr); - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0x27); - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0x7c); - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x4 << 0x8) | 0xb3); - - return 0; -} - -static int hi_vrd_info_check_params(u8 chip_id, u8 page, u32 data_len, u32 slave_addr) -{ - if (chip_id >= CHIP_ID_NUM_MAX) { - pr_err("[sysctl pmbus] read chip_id range[0x0-0x3]is err!\n"); - return SYSCTL_ERR_PARAM; - } - - if (page >= PAGE_NUM_MAX) { - pr_err("[sysctl pmbus] read page range[0x0-0x6f]is err!\n"); - return SYSCTL_ERR_PARAM; - } - - if ((data_len > DATA_NUM_MAX) || (data_len == 0)) { - pr_err("[sysctl pmbus] read data len range[0x1-0x4]is err!\n"); - return SYSCTL_ERR_PARAM; - } - - if (slave_addr >= SLAVE_ADDR_MAX) { - pr_err("[sysctl pmbus] vrd_info slave_addr=0x%x err!\n", slave_addr); - return SYSCTL_ERR_PARAM; - } - - return SYSCTL_ERR_OK; -} - -int hi_vrd_info_get(u8 chip_id, u8 addr, u8 page, u32 slave_addr, u32 data_len, u32 *buf) -{ - u32 retry_time = 0x10; - u32 ret; - - ret = hi_vrd_info_check_params(chip_id, page, data_len, slave_addr); - if (ret != SYSCTL_ERR_OK) - return ret; - - ret = InitPmbus(chip_id); - if (ret != SYSCTL_ERR_OK) - return ret; - - /* read val */ - ret = sysctl_pmbus_cfg(chip_id, 0x0, page, slave_addr); - if (ret != SYSCTL_ERR_OK) - return ret; - - while (retry_time) { - ret = sysctl_pmbus_read(chip_id, addr, slave_addr, data_len, buf); - if (ret != SYSCTL_ERR_TIMEOUT) - break; - - retry_time--; - - udelay(100); /* Delay 100 subtleties */ - } - - if (!retry_time) { - pr_err("[sysctl pmbus] read voltage mode time out!\n"); - ret = DeInitPmbus(chip_id); - if (ret != SYSCTL_ERR_OK) - return ret; - - return SYSCTL_ERR_TIMEOUT; - } - - if (!buf) { - pr_err("[sysctl pmbus]read vrd info error, buf is NULL\n"); - return SYSCTL_ERR_PARAM; - } - - pr_info("read val:0x%x !\n", *buf); - - ret = DeInitPmbus(chip_id); - if (ret != SYSCTL_ERR_OK) - return ret; - - return 0; -} - -int sysctl_cpu_voltage_read(u8 chip_id, u8 loop, u32 slave_addr) -{ - pmbus_vout_mode vout_mode; - u32 val = 0; - u32 ret; - - if (chip_id >= CHIP_ID_NUM_MAX) { - pr_err("[sysctl pmbus] read chip_id range[0x0-0x3]is err!\n"); - return SYSCTL_ERR_PARAM; - } - - if (loop >= VOL_LOOP_NUM_MAX) { - pr_err("[sysctl pmbus] read voltage loop range[0x0-0x2]is err!\n"); - return SYSCTL_ERR_PARAM; - } - - if (slave_addr >= SLAVE_ADDR_MAX) { - pr_err("[sysctl pmbus] cpu_voltage_read slave_addr=0x%x err!\n", slave_addr); - return SYSCTL_ERR_PARAM; - } - - /* read voltage mode */ - ret = hi_vrd_info_get(chip_id, 0x20, loop, slave_addr, 0x1, (u32 *)&vout_mode); - if (ret) - return ret; - - if (vout_mode.bits.vout_mode_surport != 0x1) - pr_err("[sysctl pmbus]Warning: voltage mode is not supported!\n"); - - /* read voltage vlave */ - ret = hi_vrd_info_get (chip_id, 0x8b, loop, slave_addr, 0x2, (u32 *)&val); - if (ret) - return ret; - - if (vout_mode.bits.vid_table == CPU_VOUT_MODE_VR125) - val = 2 * ((val - 1) * 5 + 250); /* 2 1 5 and 250 are the number of relationships. */ - else if (vout_mode.bits.vid_table == CPU_VOUT_MODE_VR120) - val = (val - 1) * 5 + 250; /* 1 5 and 250 are the number of relationships. */ - else - pr_err("vout mode[0x%x] is err, voltage is invalid!\n", vout_mode.bits.vid_table); - - pr_info("voltage :%dmV!\n", val); - - return 0; -} - -static int sysctl_cpu_convert_vol_to_vid(u32 vid_table, u32 value, u32 *vid) -{ - if (vid_table == CPU_VOUT_MODE_VR125) { - *vid = (value / 2 - 250) / 5 + 1; /* 2 1 5 and 250 are the number of relationships. */ - } else if (vid_table == CPU_VOUT_MODE_VR120) { - *vid = (value - 250) / 5 + 1; /* 1 5 and 250 are the number of relationships. */ - } else { - pr_err("voltage adjust vout mode[0x%x] is err!\n", vid_table); - return SYSCTL_ERR_FAILED; - } - - return SYSCTL_ERR_OK; -} - -int sysctl_cpu_voltage_adjust(u8 chip_id, u8 loop, u32 slave_addr, u32 value) -{ - u32 ret; - u32 vid; - pmbus_vout_mode vout_mode; - void __iomem *base = NULL; - - if ((chip_id >= CHIP_ID_NUM_MAX) || - (slave_addr >= SLAVE_ADDR_MAX) || - (value < CPU_VOL_MIN)) { - pr_err("[sysctl pmbus]cpu_voltage_adjust param err,chipid=0x%x,slave_addr=0x%x,value=0x%x!\n", - chip_id, slave_addr, value); - return SYSCTL_ERR_PARAM; - } - - base = g_sysctl_pmbus_base[chip_id]; - - /* read voltage mode */ - ret = hi_vrd_info_get(chip_id, 0x20, loop, slave_addr, 0x1, (u32 *)&vout_mode); - if (ret) - return ret; - - if (vout_mode.bits.vout_mode_surport != 0x1) - pr_err("[sysctl pmbus]Warning: voltage mode is not supported!\n"); - - ret = sysctl_cpu_convert_vol_to_vid(vout_mode.bits.vid_table, value, &vid); - if (ret != SYSCTL_ERR_OK) - return ret; - - ret = InitPmbus(chip_id); - if (ret != SYSCTL_ERR_OK) - return ret; - - ret = sysctl_pmbus_cfg(chip_id, 0x0, 0x3f, slave_addr); - if (ret != SYSCTL_ERR_OK) - return ret; - - ret = sysctl_cpu_voltage_password_cfg (chip_id, slave_addr); - if (ret != SYSCTL_ERR_OK) - return ret; - - ret = sysctl_pmbus_cfg(chip_id, 0x0, loop, slave_addr); - if (ret != SYSCTL_ERR_OK) - return ret; - - his_sysctrl_reg_wr(base, I2C_INTR_RAW_OFFSET, 0x3ffff); - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x2 << 0x8) | slave_addr); - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0x21); - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, 0xff & vid); - his_sysctrl_reg_wr(base, I2C_DATA_CMD_OFFSET, (0x4 << 0x8) | (0xff & (vid >> 0x8))); - - udelay(100); /* Delay 100 subtleties */ - - his_sysctrl_reg_wr(base, PMBUS_WR_OPEN_OFFSET, 0x0); - his_sysctrl_reg_wr(base, AVS_WR_OPEN_OFFSET, 0x0); - - return SYSCTL_ERR_OK; -} - -int hip_sysctl_pmbus_init(void) -{ - int ret; - - ret = sysctl_pmbus_init(); - if (ret != SYSCTL_ERR_OK) - pr_err("[ERROR] %s fail, ret:[0x%x].\n", __func__, ret); - - return ret; -} - -void hip_sysctl_pmbus_exit(void) -{ - sysctl_pmbus_deinit(); - pr_info("[INFO] hip sysctl pmbus exit.\n"); -} - -EXPORT_SYMBOL(sysctl_cpu_voltage_read); -EXPORT_SYMBOL(hi_vrd_info_get); -EXPORT_SYMBOL(sysctl_cpu_voltage_adjust); -EXPORT_SYMBOL(sysctl_pmbus_write); -EXPORT_SYMBOL(sysctl_pmbus_read); -EXPORT_SYMBOL(sysctl_pmbus_write_common); -EXPORT_SYMBOL(sysctl_pmbus_read_common); -EXPORT_SYMBOL(InitPmbus); -EXPORT_SYMBOL(DeInitPmbus); diff --git a/drivers/soc/hisilicon/sysctl/sysctl_pmbus.h b/drivers/soc/hisilicon/sysctl/sysctl_pmbus.h deleted file mode 100644 index ce1d83dbbb9a8..0000000000000 --- a/drivers/soc/hisilicon/sysctl/sysctl_pmbus.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#ifndef _HIS_SYSCTL_PMBUS_H_ -#define _HIS_SYSCTL_PMBUS_H_ - -#define VOL_LOOP_NUM_MAX (0x3) -#define PAGE_NUM_MAX (0x6f) -#define DATA_NUM_MAX (0x4) - -#define I2C_FIFO_DEPTH (256) - -/* slave_addr use 1 fifo */ -#define PMBUS_READ_LEN_MAX (I2C_FIFO_DEPTH - 1) -/* slave_addr use 2 fifo */ -#define PMBUS_WRITE_LEN_MAX (I2C_FIFO_DEPTH - 2) - -#define I2C_TX_ABRT (0x040) -#define I2C_TX_ABRT_SRC_REG (0x0880) -#define I2C_CLR_TX_ABRT_REG (0x0854) -#define I2C_STATUS_REG (0x0870) -#define I2C_TX_FIFO_EMPTY (0x04) -#define I2C_TX_FIFO_DATA_NUM_REG (0x0874) - -#define I2C_SS_SCLHCNT 0x3db -#define I2C_SS_SCLLCNT 0x3e6 -#define I2C_SS_SDA_HOLD_FS 0xfa - -/* AVS_REG_GEN */ -#define AVS_WR_OPEN_OFFSET 0x0004 -#define AVS_INT_STATUS_OFFSET 0x0008 -#define AVS_ERROR_INT_STATUS_OFFSET 0x000C -#define AVS_PARITY_INT_STATUS_OFFSET 0x0010 -#define AVS_INT_CLEAR_OFFSET 0x0020 -#define AVS_ERROR_INT_CLEAR_OFFSET 0x0024 -#define AVS_INT_MASK_OFFSET 0x0034 - -/* PMBUSIF_REG_GEN */ -#define I2C_CON_OFFSET 0x0800 -#define I2C_DATA_CMD_OFFSET 0x0810 -#define I2C_SS_SCL_HCNT_OFFSET 0x0814 -#define I2C_SS_SCL_LCNT_OFFSET 0x0818 -#define I2C_FS_SCL_HCNT_OFFSET 0x081C -#define I2C_FS_SCL_LCNT_OFFSET 0x0820 -#define I2C_INTR_STAT_OFFSET 0x082C -#define I2C_INTR_MASK_OFFSET 0x0830 -#define I2C_INTR_RAW_OFFSET 0x0834 -#define I2C_ENABLE_OFFSET 0x086C -#define I2C_RXFLR_OFFSET 0x0878 -#define I2C_SDA_HOLD_OFFSET 0x087C -#define I2C_SCL_SWITCH_OFFSET 0x08A0 -#define I2C_SCL_SIM_OFFSET 0x08A4 -#define I2C_LOCK_OFFSET 0x08AC -#define I2C_SDA_SWITCH_OFFSET 0x08B0 -#define I2C_SDA_SIM_OFFSET 0x08B4 -#define I2C_PMBUS_CTRL_OFFSET 0x0904 -#define I2C_LOW_TIMEOUT_OFFSET 0x0908 -#define I2C_PMBUS_SCL_DET_OFFSET 0x092C -#define I2C_PMBUS_IDLECNT_OFFSET 0x0930 -#define I2C_PMBUS_RST_OFFSET 0x0934 - -/* PMBUS_PROC_REG_GEN */ -#define PMBUS_REG_BASE (0x000094180000) -#define PMBUS_WR_OPEN_OFFSET 0x0A04 -#define PMBUS_INT_OFFSET 0x0A08 -#define PMBUS_INT_CLR_OFFSET 0x0A10 -#define PMBUS_PROC_TIMEOUT_TH_OFFSET 0x0A1C -#define PMBUS_VOLTAGE_STABLE_OFFSET 0x0A20 -#define READ_VOUD_INTERVAL_OFFSET 0x0A28 -#define PMBUS_OTHER_CFG_OFFSET 0x0A2C -#define VOLTAGE_ADDR_CFG_OFFSET 0x0A30 -#define VOLTAGE_CONVERT_CFG_OFFSET 0x0A34 -#define STATUS_RPT_OFFSET 0x0AA4 -#define STATUS_ERR_RPT_OFFSET 0x0AA8 - -struct pmbus_read_op { - u32 slave_addr; - u32 cmd_len; - u32 data_len; - u8 *cmd; - u8 *data; -}; - -/* Define the union pmbus_vout_mode */ -typedef union { - /* Define the struct bits */ - struct { - unsigned int vid_table : 5 ; /* [4..0] */ - unsigned int vout_mode_surport : 3 ; /* [7..5] */ - unsigned int reserved_0 : 24 ; /* [31..8] */ - } bits; - - /* Define an unsigned member */ - unsigned int u32; -} pmbus_vout_mode; - -enum { - CPU_VOUT_MODE_INVALID = 0, - CPU_VOUT_MODE_VR120, - CPU_VOUT_MODE_VR125, - CPU_VOUT_MODE_MAX, -}; - -int hip_sysctl_pmbus_init(void); -void hip_sysctl_pmbus_exit(void); - -#endif -- 2.25.1
From: fengsheng <fengsheng5@huawei.com> driver inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4IYX7?from=project-issue CVE: NA ------------------------------------------------------------ This driver is not in use. Remove it. Signed-off-by: fengsheng <fengsheng5@huawei.com> Reviewed-by: lidongming <lidongming5@huawei.com> Reviewed-by: ouyang delong <ouyangdelong@huawei.com> Acked-by: Xie XiuQi <xiexiuqi@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> --- MAINTAINERS | 5 - arch/arm64/configs/hulk_defconfig | 1 - arch/arm64/configs/openeuler_defconfig | 2 - arch/arm64/configs/storage_ci_defconfig | 1 - arch/arm64/configs/syzkaller_defconfig | 1 - arch/x86/configs/openeuler_defconfig | 1 - arch/x86/configs/storage_ci_defconfig | 1 - drivers/mtd/Kconfig | 2 - drivers/mtd/Makefile | 2 +- drivers/mtd/hisilicon/Kconfig | 1 - drivers/mtd/hisilicon/Makefile | 1 - drivers/mtd/hisilicon/sfc/Kconfig | 3 - drivers/mtd/hisilicon/sfc/Makefile | 3 - drivers/mtd/hisilicon/sfc/hrd_common.h | 106 -- drivers/mtd/hisilicon/sfc/hrd_sfc_driver.c | 242 ---- drivers/mtd/hisilicon/sfc/hrd_sflash_core.c | 539 -------- drivers/mtd/hisilicon/sfc/hrd_sflash_core.h | 160 --- drivers/mtd/hisilicon/sfc/hrd_sflash_driver.c | 390 ------ drivers/mtd/hisilicon/sfc/hrd_sflash_driver.h | 105 -- drivers/mtd/hisilicon/sfc/hrd_sflash_hal.c | 1159 ----------------- drivers/mtd/hisilicon/sfc/hrd_sflash_hal.h | 31 - drivers/mtd/hisilicon/sfc/hrd_sflash_spec.h | 376 ------ 22 files changed, 1 insertion(+), 3131 deletions(-) delete mode 100644 drivers/mtd/hisilicon/Kconfig delete mode 100644 drivers/mtd/hisilicon/Makefile delete mode 100644 drivers/mtd/hisilicon/sfc/Kconfig delete mode 100644 drivers/mtd/hisilicon/sfc/Makefile delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_common.h delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sfc_driver.c delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_core.c delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_core.h delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_driver.c delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_driver.h delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_hal.c delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_hal.h delete mode 100644 drivers/mtd/hisilicon/sfc/hrd_sflash_spec.h diff --git a/MAINTAINERS b/MAINTAINERS index de1f5d368ca88..d95d71e0ba4eb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5904,11 +5904,6 @@ F: drivers/ptp/ptp_qoriq.c F: include/linux/fsl/ptp_qoriq.h F: Documentation/devicetree/bindings/ptp/ptp-qoriq.txt -HISILICON SFC DRIVER -M: Feng Sheng <fengsheng5@huawei.com> -S: Maintained -F: drivers/mtd/hisilicon/sfc/ - FREESCALE QUAD SPI DRIVER M: Han Xu <han.xu@nxp.com> L: linux-mtd@lists.infradead.org diff --git a/arch/arm64/configs/hulk_defconfig b/arch/arm64/configs/hulk_defconfig index 97354a29c914c..413667c434ee6 100644 --- a/arch/arm64/configs/hulk_defconfig +++ b/arch/arm64/configs/hulk_defconfig @@ -1818,7 +1818,6 @@ CONFIG_MTD=m # CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AFS_PARTS is not set CONFIG_MTD_OF_PARTS=m -CONFIG_MTD_HISILICON_SFC=m # CONFIG_MTD_AR7_PARTS is not set # diff --git a/arch/arm64/configs/openeuler_defconfig b/arch/arm64/configs/openeuler_defconfig index 06d57fc62c324..c63a2f829db02 100644 --- a/arch/arm64/configs/openeuler_defconfig +++ b/arch/arm64/configs/openeuler_defconfig @@ -1905,14 +1905,12 @@ CONFIG_MTD_SPI_NOR=m CONFIG_MTD_MT81xx_NOR=m CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y # CONFIG_SPI_CADENCE_QUADSPI is not set -CONFIG_SPI_HISI_SFC=m CONFIG_MTD_UBI=m CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_MTD_UBI_FASTMAP is not set CONFIG_MTD_UBI_GLUEBI=m # CONFIG_MTD_UBI_BLOCK is not set -CONFIG_MTD_HISILICON_SFC=m CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set diff --git a/arch/arm64/configs/storage_ci_defconfig b/arch/arm64/configs/storage_ci_defconfig index 6d671761fd080..941f76b15c099 100644 --- a/arch/arm64/configs/storage_ci_defconfig +++ b/arch/arm64/configs/storage_ci_defconfig @@ -1061,7 +1061,6 @@ CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_GLUEBI=y CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_HISILICON_SFC=m CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set diff --git a/arch/arm64/configs/syzkaller_defconfig b/arch/arm64/configs/syzkaller_defconfig index caa022e24fdc3..d82959f4027cf 100644 --- a/arch/arm64/configs/syzkaller_defconfig +++ b/arch/arm64/configs/syzkaller_defconfig @@ -1772,7 +1772,6 @@ CONFIG_MTD=m # CONFIG_MTD_CMDLINE_PARTS is not set # CONFIG_MTD_AFS_PARTS is not set CONFIG_MTD_OF_PARTS=m -CONFIG_MTD_HISILICON_SFC=m # CONFIG_MTD_AR7_PARTS is not set # diff --git a/arch/x86/configs/openeuler_defconfig b/arch/x86/configs/openeuler_defconfig index 035d4b454dc80..854f10c491880 100644 --- a/arch/x86/configs/openeuler_defconfig +++ b/arch/x86/configs/openeuler_defconfig @@ -1943,7 +1943,6 @@ CONFIG_MTD_UBI_BEB_LIMIT=20 # CONFIG_MTD_UBI_FASTMAP is not set # CONFIG_MTD_UBI_GLUEBI is not set # CONFIG_MTD_UBI_BLOCK is not set -CONFIG_MTD_HISILICON_SFC=m # CONFIG_OF is not set CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y CONFIG_PARPORT=m diff --git a/arch/x86/configs/storage_ci_defconfig b/arch/x86/configs/storage_ci_defconfig index d18d5fcb90b37..51df58940ac6e 100644 --- a/arch/x86/configs/storage_ci_defconfig +++ b/arch/x86/configs/storage_ci_defconfig @@ -1200,7 +1200,6 @@ CONFIG_MTD_UBI_BEB_LIMIT=20 CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_GLUEBI=y CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_HISILICON_SFC=m # CONFIG_OF is not set CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y # CONFIG_PARPORT is not set diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index cf6d18da3527e..c77f537323ecb 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -339,6 +339,4 @@ source "drivers/mtd/spi-nor/Kconfig" source "drivers/mtd/ubi/Kconfig" -source "drivers/mtd/hisilicon/Kconfig" - endif # MTD diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index a6972d6b38103..93473d215a387 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -32,7 +32,7 @@ obj-$(CONFIG_MTD_SWAP) += mtdswap.o nftl-objs := nftlcore.o nftlmount.o inftl-objs := inftlcore.o inftlmount.o -obj-y += chips/ lpddr/ maps/ devices/ nand/ tests/ hisilicon/ +obj-y += chips/ lpddr/ maps/ devices/ nand/ tests/ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/ obj-$(CONFIG_MTD_UBI) += ubi/ diff --git a/drivers/mtd/hisilicon/Kconfig b/drivers/mtd/hisilicon/Kconfig deleted file mode 100644 index 117c92d3547df..0000000000000 --- a/drivers/mtd/hisilicon/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source "drivers/mtd/hisilicon/sfc/Kconfig" diff --git a/drivers/mtd/hisilicon/Makefile b/drivers/mtd/hisilicon/Makefile deleted file mode 100644 index 127b108941e3b..0000000000000 --- a/drivers/mtd/hisilicon/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-$(CONFIG_MTD_HISILICON_SFC) += sfc/ diff --git a/drivers/mtd/hisilicon/sfc/Kconfig b/drivers/mtd/hisilicon/sfc/Kconfig deleted file mode 100644 index 5bead1f871b66..0000000000000 --- a/drivers/mtd/hisilicon/sfc/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config MTD_HISILICON_SFC - tristate - default m diff --git a/drivers/mtd/hisilicon/sfc/Makefile b/drivers/mtd/hisilicon/sfc/Makefile deleted file mode 100644 index 153825dc9983c..0000000000000 --- a/drivers/mtd/hisilicon/sfc/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -hi-sfc-objs := hrd_sfc_driver.o hrd_sflash_driver.o hrd_sflash_hal.o hrd_sflash_core.o -obj-$(CONFIG_MTD_HISILICON_SFC) += hi-sfc.o diff --git a/drivers/mtd/hisilicon/sfc/hrd_common.h b/drivers/mtd/hisilicon/sfc/hrd_common.h deleted file mode 100644 index 71dcaa98be16e..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_common.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http: - */ - -#ifndef __HRD_COMMON_H__ -#define __HRD_COMMON_H__ - -#define HRD_OK (int)(0) -#define HRD_ERR (int)(-1) - -#define HRD_ERR_BASE (int)(-1024) - -#define HRD_COMMON_ERR_BASE (int)(HRD_ERR_BASE) -#define HRD_COMMON_ERR_NULL_POINTER (int)(HRD_COMMON_ERR_BASE - 1) -#define HRD_COMMON_ERR_UNKNOW_DEVICE (int)(HRD_COMMON_ERR_BASE - 2) -#define HRD_COMMON_ERR_UNKNOW_FUNCTION (int)(HRD_COMMON_ERR_BASE - 3) -#define HRD_COMMON_ERR_OPEN_FAIL (int)(HRD_COMMON_ERR_BASE - 4) -#define HRD_COMMON_ERR_READ_FAIL (int)(HRD_COMMON_ERR_BASE - 5) -#define HRD_COMMON_ERR_WRITE_FAIL (int)(HRD_COMMON_ERR_BASE - 6) -#define HRD_COMMON_ERR_MMAP_FAIL (int)(HRD_COMMON_ERR_BASE - 7) -#define HRD_COMMON_ERR_GET_MEN_RES_FAIL (int)(HRD_COMMON_ERR_BASE - 8) -#define HRD_COMMON_ERR_GET_IRQ_RES_FAIL (int)(HRD_COMMON_ERR_BASE - 9) -#define HRD_COMMON_ERR_INPUT_INVALID (int)(HRD_COMMON_ERR_BASE - 10) -#define HRD_COMMON_ERR_UNKNOW_MODE (int)(HRD_COMMON_ERR_BASE - 11) -#define HRD_COMMON_ERR_NOT_ENOUGH_RES (int)(HRD_COMMON_ERR_BASE - 12) -#define HRD_COMMON_ERR_RES_NOT_EXIST (int)(HRD_COMMON_ERR_BASE - 13) - -/* 16 bit nibble swap. example 0x1234 -> 0x2143 */ -#define HRD_NIBBLE_SWAP_16BIT(X) ((((X) & 0xf) << 4) | \ - (((X) & 0xF0) >> 4) | \ - (((X) & 0xF00) << 4) | \ - (((X) & 0xF000) >> 4)) - -/* 32 bit nibble swap. example 0x12345678 -> 0x21436587 */ -#define HRD_NIBBLE_SWAP_32BIT(X) ((((X) & 0xF) << 4) | \ - (((X) & 0xF0) >> 4) | \ - (((X) & 0xF00) << 4) | \ - (((X) & 0xF000) >> 4) | \ - (((X) & 0xF0000) << 4) | \ - (((X) & 0xF00000) >> 4) | \ - (((X) & 0xF000000) << 4) | \ - (((X) & 0xF0000000) >> 4)) - -/* 16 bit byte swap. example 0x1234->0x3412 */ -#define HRD_BYTE_SWAP_16BIT(X) ((((X) & 0xFF) << 8) | (((X) & 0xFF00) >> 8)) - -/* 32 bit byte swap. example 0x12345678->0x78563412 */ -#define HRD_BYTE_SWAP_32BIT(X) ((((X) & 0xFF) << 24) | \ - (((X) & 0xFF00) << 8) | \ - (((X) & 0xFF0000) >> 8) | \ - (((X) & 0xFF000000) >> 24)) - -/* 64 bit byte swap. example 0x11223344.55667788 -> 0x88776655.44332211 */ -#define HRD_BYTE_SWAP_64BIT(X) ((l64) ((((X) & 0xFFULL) << 56) | \ - (((X) & 0xFF00ULL) << 40) | \ - (((X) & 0xFF0000ULL) << 24) | \ - (((X) & 0xFF000000ULL) << 8) | \ - (((X) & 0xFF00000000ULL) >> 8) | \ - (((X) & 0xFF0000000000ULL) >> 24) | \ - (((X) & 0xFF000000000000ULL) >> 40) | \ - (((X) & 0xFF00000000000000ULL) >> 56))) - -/* -- Endianess macros. */ -#ifdef HRD_ENDNESS_BIGEND -#define HRD_16BIT_LE(X) HRD_BYTE_SWAP_16BIT(X) -#define HRD_32BIT_LE(X) HRD_BYTE_SWAP_32BIT(X) -#define HRD_64BIT_LE(X) HRD_BYTE_SWAP_64BIT(X) -#define HRD_16BIT_BE(X) (X) -#define HRD_32BIT_BE(X) (X) -#define HRD_64BIT_BE(X) (X) -#else -#define HRD_16BIT_LE(X) (X) -#define HRD_32BIT_LE(X) (X) -#define HRD_64BIT_LE(X) (X) -#define HRD_16BIT_BE(X) HRD_BYTE_SWAP_16BIT(X) -#define HRD_32BIT_BE(X) HRD_BYTE_SWAP_32BIT(X) -#define HRD_64BIT_BE(X) HRD_BYTE_SWAP_64BIT(X) -#endif - -#ifndef NULL -#define NULL ((void *)0) -#endif - -#define MTD_FLASH_MAP_DEBUG - -#ifdef MTD_FLASH_MAP_DEBUG -#define DB(x) x -#else -#define DB(x) -#endif - -#endif diff --git a/drivers/mtd/hisilicon/sfc/hrd_sfc_driver.c b/drivers/mtd/hisilicon/sfc/hrd_sfc_driver.c deleted file mode 100644 index 69fb1b306f0da..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sfc_driver.c +++ /dev/null @@ -1,242 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/module.h> -#include <linux/types.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/map.h> -#include <linux/mtd/partitions.h> -#include <linux/platform_device.h> -#include <linux/acpi.h> -#include "hrd_common.h" -#include "hrd_sflash_driver.h" - -#define SFC_DRIVER_VERSION "1.9.60.0" - -static const char *g_sflashMtdList[] = {"sflash", NULL}; - -static unsigned int hrd_flash_info_fill(struct maps_init_info *maps, - struct resource *flash_iores, struct platform_device *pdev) -{ - u32 i; - - memset((void *)maps, 0x0, sizeof(struct maps_init_info)*MTD_MAX_FLASH_NUMBER); - - for (i = 0; i < MTD_MAX_FLASH_NUMBER; i++) { - maps[i].mtdDrv = g_sflashMtdList; - maps[i].mapInfo.name = pdev->name; - maps[i].mapInfo.phys = flash_iores->start; - maps[i].mapInfo.size = resource_size(flash_iores); - maps[i].mapInfo.bankwidth = 0x8; - DB(pr_info("[SFC] i is 0x%x, phys 0x%llx,size 0x%lx\n", - (u32) i, maps[i].mapInfo.phys, - maps[i].mapInfo.size)); - - DB(pr_info("[SFC] INFO: Found %s %d - base 0x%08x, size 0x%x\n", - maps[i].mapInfo.name, i, - (unsigned int)maps[i].mapInfo.phys, - (unsigned int)maps[i].mapInfo.size)); - } - - DB(pr_info("[SFC] INFO: %s - Found %d Flash Devices\n", __func__, i)); - return i; -} - -static int _hrd_flashProbe(const char **mtdDrv, struct map_info *map, - struct resource *sfc_regres, struct mtd_info **mtd) -{ - *mtd = NULL; - - for (; (!(*mtd) && *mtdDrv); mtdDrv++) { - DB(pr_info - ("[SFC] Using %s probe %s at addr 0x%llx,size 0x%x, width %dm\n", - *mtdDrv, map->name, (u64) map->phys, - (unsigned int)map->size, map->bankwidth)); - - *mtd = sflash_probe(map, sfc_regres); - if (*mtd) { - (*mtd)->owner = THIS_MODULE; - - if (mtd_device_register(*mtd, NULL, 0)) { - pr_err("probe: Failed to add the mtd device\n"); - iounmap((void *)map->virt); - map->virt = 0; - return -ENXIO; - } - - return HRD_OK; - } - DB(pr_info("[SFC] - Not detected\n")); - } - - return HRD_ERR; -} - -static int hrd_flashProbe(const char **mtdDrv, struct map_info *map, - struct resource *sfc_regres, struct mtd_info **mtd) -{ - int ret; - - if ((mtdDrv == NULL) - || (map == NULL) - || (mtd == NULL)) { - pr_err("[SFC] ERROR: NULL pointer parameter at %s entry\n", __func__); - return -EINVAL; - } - - map->virt = ioremap(map->phys, map->size); - if (!map->virt) { - pr_err("[SFC] Failed ioremap Flash device at base 0x%x.\n", - (unsigned int)map->phys); - return -EIO; - } - - DB(pr_info - ("[SFC] Io remapped ok.phy addr:0x%llx, virt addr:0x%llx\n", - (u64) map->phys, (u64) map->virt)); - - /* Skip bankwidths that are not supported */ - if (!map_bankwidth_supported(map->bankwidth)) { - pr_err("[SFC] ERROR: bankwidth %d not supported.\n", - (unsigned int)map->bankwidth); - iounmap((void *)map->virt); - return -EIO; - } - - ret = _hrd_flashProbe(mtdDrv, map, sfc_regres, mtd); - if (ret == HRD_OK) - return 0; - - iounmap((void *)map->virt); - map->virt = 0; - pr_err("[SFC] ERROR: %s - probe failed\n", __func__); - - return -ENXIO; -} - -static int flash_map_init(struct platform_device *pdev) -{ - u32 i; - u32 mapsNum; - struct device *dev = &pdev->dev; - struct resource *sfc_regres = NULL; - struct resource *flash_iores = NULL; - struct sfc_host *host = NULL; - - pr_info("SFC Driver\n"); - host = devm_kzalloc(dev, sizeof(struct sfc_host), GFP_KERNEL); - if (!host) { - pr_err("[SFC] ERROR: %s devm_kzalloc failed\n", __func__); - return -ENOMEM; - } - - sfc_regres = platform_get_resource(pdev, IORESOURCE_MEM, 0); - flash_iores = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (!sfc_regres || !flash_iores) - return -EFAULT; - - if (sfc_regres->end <= sfc_regres->start) { - pr_err("ERROR: sfc register error\n"); - return -EFAULT; - } - - if (flash_iores->end <= flash_iores->start) { - pr_err("[SFC] ERROR: flash addr error\n"); - return -EFAULT; - } - - mapsNum = hrd_flash_info_fill(host->maps, flash_iores, pdev); - DB(pr_info("[SFC] INFO: DEtected %d devices\n", mapsNum)); - - for (i = 0; i < mapsNum; i++) { - DB(pr_info("[SFC] MTD: Initialize the %s device at address 0x%08x\n", - host->maps[i].mapInfo.name, (unsigned int)host->maps[i].mapInfo.phys)); - - if (hrd_flashProbe - (host->maps[i].mtdDrv, &host->maps[i].mapInfo, sfc_regres, - &host->maps[i].mtdInfo) == 0) { - DB(pr_info("[SFC]- OK.\n")); - } else { - host->maps[i].mtdInfo = NULL; - DB(pr_err(" [SFC]- FAILED!\n")); - } - } - - host->mapsNum = mapsNum; - platform_set_drvdata(pdev, host); - - return 0; -} - -static void __exit flash_map_exit(struct platform_device *pdev) -{ - u32 i; - - struct sfc_host *host = platform_get_drvdata(pdev); - - for (i = 0; i < host->mapsNum; i++) { - if (host->maps[i].mtdInfo) - (void)mtd_device_unregister(host->maps[i].mtdInfo); - - if (host->maps[i].mapInfo.virt) { - iounmap((void *)host->maps[i].mapInfo.virt); - host->maps[i].mapInfo.virt = 0; - } - - if (host->maps[i].mtdInfo) - sflash_destroy(host->maps[i].mtdInfo); - } - -} - -static int hisi_sfc_probe(struct platform_device *pdev) -{ - return flash_map_init(pdev); -} - -static int hisi_sfc_remove(struct platform_device *pdev) -{ - flash_map_exit(pdev); - - return 0; -} - -static const struct acpi_device_id g_sfc_acpi_match[] = { - {"HISI0343", 0}, - {} -}; - -MODULE_DEVICE_TABLE(acpi, g_sfc_acpi_match); - -static struct platform_driver g_hisi_sfc_driver = { - .probe = hisi_sfc_probe, - .remove = hisi_sfc_remove, - .driver = { - .name = "hisi_sfc", - .acpi_match_table = ACPI_PTR(g_sfc_acpi_match), - }, -}; - -module_platform_driver(g_hisi_sfc_driver); - -MODULE_LICENSE("GPL v2"); -MODULE_AUTHOR("Huawei Tech. Co., Ltd."); -MODULE_DESCRIPTION("Hi16xx SFC driver"); -MODULE_VERSION(SFC_DRIVER_VERSION); - - diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_core.c b/drivers/mtd/hisilicon/sfc/hrd_sflash_core.c deleted file mode 100644 index 68547d8e1d31b..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_core.c +++ /dev/null @@ -1,539 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/of_gpio.h> -#include <linux/of_platform.h> -#include <linux/of_address.h> -#include <linux/platform_device.h> -#include <linux/resource.h> -#include <linux/signal.h> -#include <linux/types.h> -#include "hrd_common.h" -#include "hrd_sflash_spec.h" -#include "hrd_sflash_core.h" - -u32 SFC_RegisterRead(u64 reg_addr) -{ - u32 ulResult; - - ulResult = *(__iomem u32 *) (reg_addr); - - return HRD_32BIT_LE(ulResult); -} - -void SFC_RegisterWrite(u64 reg_addr, u32 ulValue) -{ - *(__iomem u32 *) (reg_addr) = HRD_32BIT_LE(ulValue); -} - -/* Judging sfc whether something is wrong */ -bool SFC_IsOpErr(u64 reg_addr) -{ - u32 IntStatus; - - IntStatus = SFC_RegisterRead(reg_addr + (u32) INTRAWSTATUS); - if ((IntStatus & SFC_OP_ERR_MASK) != 0) { - pr_err("%s ERROR: Int status=%x not cleared, clear\r\n", __func__, IntStatus); - SFC_RegisterWrite(reg_addr + INTCLEAR, INT_MASK); - return true; - } - - return false; -} - -s32 SFC_ClearInt(u64 reg_addr) -{ - u32 IntStatus; - - IntStatus = SFC_RegisterRead(reg_addr + (u32) INTRAWSTATUS); - if ((IntStatus & INT_MASK) != 0) { - pr_err("[SFC] [%s %d]: Int status=%x not cleared, clear\r\n", - __func__, __LINE__, IntStatus); - SFC_RegisterWrite(reg_addr + INTCLEAR, INT_MASK); - } - - return 0; -} - -s32 SFC_WaitInt(u64 reg_addr) -{ - u32 ulRegValue; - u32 ulCount = 0; - - ulRegValue = SFC_RegisterRead(reg_addr + (u32) INTRAWSTATUS); - while (((ulRegValue & CMD_OP_END_INT_BIT) != CMD_OP_END_INT_BIT) - && (ulCount < SFC_INT_WAIT_CNT)) { - udelay(1); - ulRegValue = SFC_RegisterRead(reg_addr + INTRAWSTATUS); - ulCount++; - } - - if (ulCount >= SFC_INT_WAIT_CNT) { - pr_err("[SFC] [%s %d]: wait int time out\n", __func__, __LINE__); - return WAIT_TIME_OUT; - } - - SFC_RegisterWrite(reg_addr + INTCLEAR, CMD_OP_END_INT_BIT); - - return HRD_OK; -} - -s32 SFC_WriteEnable(struct SFC_SFLASH_INFO *sflash) -{ - u32 ulRegValue; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, sflash->sflash_dev_params.ucOpcodeWREN); - - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(1 << ADDR_EN)) & (~(1 << DATA_EN)) & (~(1 << SEL_CS)); - ulRegValue |= (0x1 << LOCK_FLASH) | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - - return SFC_WaitInt(sflash->sfc_reg_base); -} - -void SFC_FlashUnlock(struct SFC_SFLASH_INFO *sflash) -{ - u32 ulRegValue; - - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(1 << LOCK_FLASH)); - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); -} - -u32 SFC_ReadStatus(struct SFC_SFLASH_INFO *sflash) -{ - u32 ulRegValue; - s32 ulRet; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - sflash->sflash_dev_params.ucOpcodeRDSR); - - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= - (~(0xff << DATA_CNT)) & (~(0x1 << RW_DATA)) & (~(0x1 << SEL_CS)); - ulRegValue |= (0x3 << DATA_CNT) | (0x1 << RW_DATA) | (0x1 << DATA_EN) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) - return WAIT_TIME_OUT; - - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1); - ulRegValue = ulRegValue & 0xff; - - return ulRegValue; -} - -s32 SFC_CheckBusy(struct SFC_SFLASH_INFO *sflash, u32 ulTimeOut) -{ - u32 ulRegValue; - u32 ulWaitCount = 0; - - ulRegValue = SFC_ReadStatus(sflash); - if (ulRegValue == WAIT_TIME_OUT) { - pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", __func__, __LINE__); - return HRD_ERR; - } - - while (((ulRegValue & STATUS_REG_BUSY_BIT) == STATUS_REG_BUSY_BIT) - && (ulWaitCount < ulTimeOut)) { - udelay((unsigned long)1); - - ulRegValue = SFC_ReadStatus(sflash); - if (ulRegValue == WAIT_TIME_OUT) { - pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", __func__, __LINE__); - return HRD_ERR; - } - - if ((sflash->manufacturerId == HISI_SPANSION_MANF_ID) - && (ulRegValue & (STATUS_REG_P_ERR | STATUS_REG_E_ERR))) { - pr_err("[SFC] [%s %d]: program err or erase err, status = %08x\n", - __func__, __LINE__, ulRegValue); - return HRD_ERR; - } - - ulWaitCount++; - if ((ulWaitCount > 0) && (ulWaitCount % 1000 == 0)) { /* Every cycle 1000 times, sleep 1 ms */ - msleep(1); - } - } - - if (ulWaitCount >= ulTimeOut) { - pr_err("[SFC] [%s %d]: CheckBusy time out\n", __func__, __LINE__); - return WAIT_TIME_OUT; - } - - return HRD_OK; -} - -s32 SFC_ClearStatus(struct SFC_SFLASH_INFO *sflash) -{ - u32 ulRegValue = 0; - s32 ulRet = HRD_ERR; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - if (sflash->manufacturerId == HISI_SPANSION_MANF_ID) { - /* 30 for spansion , clear status */ - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, 0x30); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - - ulRegValue &= (~(1 << ADDR_EN)) & (~(1 << DATA_EN)) & (~(1 << SEL_CS)); - ulRegValue |= (SFC_CHIP_CS << SEL_CS) | (1 << START); - - wmb(); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - - /* wait operate end */ - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) - return ulRet; - } - - return HRD_OK; -} - -void SFC_CheckErr(struct SFC_SFLASH_INFO *sflash) -{ - u32 ulRegValue = 0; - unsigned long delay_us = 50; /* delay 50us */ - - if (sflash->manufacturerId == HISI_SPANSION_MANF_ID) { - ulRegValue = SFC_ReadStatus(sflash); - if (ulRegValue == WAIT_TIME_OUT) { - pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", - __func__, __LINE__); - return; - } - - udelay(delay_us); - - if (ulRegValue & (STATUS_REG_P_ERR | STATUS_REG_E_ERR)) { - pr_err("[SFC] [%s %d]: program err or erase err, status = %08x\n", - __func__, __LINE__, ulRegValue); - - if (SFC_ClearStatus(sflash) != HRD_OK) { - pr_err("[SFC] [%s %d]: clear status failed\r\n", - __func__, __LINE__); - return; - } - - udelay(delay_us); - } - } -} - -s32 SFC_CheckCmdExcStatus(struct SFC_SFLASH_INFO *sflash) -{ - u32 temp; - u32 timeout = 1000; - - temp = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - while (temp & 1) { - udelay(1); - temp = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - timeout--; - - if (timeout == 0) { - pr_err("[SFC] %s (%d):Check cmd execute status time out!\n", __func__, __LINE__); - return HRD_ERR; - } - } - - return HRD_OK; -} - -int SFC_WaitFlashIdle(struct SFC_SFLASH_INFO *sflash) -{ - union UN_SFC_CMD_CONFIG temp; - u32 temp2 = 0; - u32 timeout = 10000; - int ret; - - temp.u32 = 0; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_RDSR); - do { - temp.bits.rw = SFC_CMD_CFG_READ; - temp.bits.addr_en = false; - temp.bits.data_en = true; - temp.bits.data_cnt = SFC_CMD_DATA_CNT(1); - temp.bits.sel_cs = SFC_CHIP_CS; - temp.bits.start = true; - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, temp.u32); - - ret = SFC_CheckCmdExcStatus(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: cmd execute timeout\r\n", __func__, __LINE__); - return ret; - } - - udelay(80); /* Delay 80 subtleties */ - temp2 = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1); - if (!(temp2 & SPI_CMD_SR_WIP)) { - return HRD_OK; - } - - udelay(20); /* Delay 20 subtleties */ - } while (timeout--); - - pr_err("[SFC] [%s %d]: Write in progress!\r\n", __func__, __LINE__); - - return HRD_ERR; -} - -int SFC_GetDeviceId(struct SFC_SFLASH_INFO *sflash, u32 *id) -{ - int ret; - union UN_SFC_CMD_CONFIG temp; - - temp.u32 = 0; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - SFLASH_DEFAULT_RDID_OPCD); - - temp.bits.rw = SFC_CMD_CFG_READ; - temp.bits.addr_en = false; - temp.bits.data_en = true; - temp.bits.data_cnt = SFC_CMD_DATA_CNT(1); - temp.bits.sel_cs = SFC_CHIP_CS; - temp.bits.start = true; - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, temp.u32); - - ret = SFC_CheckCmdExcStatus(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] %s %d\n", __func__, __LINE__); - return ret; - } - - *id = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1); - pr_info("[SFC] %s(%d):get_device_id: 0x%x !\n", __func__, __LINE__, *id); - - return ret; -} - -s32 SFC_RegWordAlignRead(struct SFC_SFLASH_INFO *sflash, - u32 ulOffsetAddr, u32 *pulData, u32 ulReadLen) -{ - u32 i; - u32 ulDataCnt; - u32 ulRegValue; - s32 ulRet; - - if (!ulReadLen || ulReadLen > SFC_HARD_BUF_LEN || (ulReadLen & 0x3)) { - pr_err("[SFC] [%s %d]: len=%u err\n", __func__, __LINE__, ulReadLen); - return HRD_ERR; - } - - ulDataCnt = ulReadLen >> 0x2; - (void)SFC_ClearInt(sflash->sfc_reg_base); - - /* configure INS reg,send RDDATA operate */ - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - sflash->sflash_dev_params.ucOpcodeREAD); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_ADDR, ulOffsetAddr); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(0xff << DATA_CNT) & (~(1 << SEL_CS))); - ulRegValue |= - ((ulReadLen - 1) << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN) | (1 << RW_DATA) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__); - return ulRet; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) - return HRD_ERR; - - for (i = 0; i < ulDataCnt; i++) - pulData[i] = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1 + (u32)(0x4 * i)); - - return ulRet; -} - -s32 SFC_RegByteRead(struct SFC_SFLASH_INFO *sflash, - u32 ulOffsetAddr, u8 *pucData) -{ - u32 ulRegValue; - s32 ulRet; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - /* configure INS reg,send RDDATA operate */ - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - sflash->sflash_dev_params.ucOpcodeREAD); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_ADDR, ulOffsetAddr); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(0xff << DATA_CNT) & (~(1 << SEL_CS))); - ulRegValue |= - (0 << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN) | (1 << RW_DATA) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__); - return ulRet; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) - return HRD_ERR; - - *pucData = SFC_RegisterRead(sflash->sfc_reg_base + DATABUFFER1) & 0xff; - - return ulRet; -} - -/* 4bytes align, ulDataLen <=256 */ -s32 SFC_RegWordAlignWrite(struct SFC_SFLASH_INFO *sflash, - const u32 *ulData, u32 ulOffsetAddr, u32 ulWriteLen) -{ - u32 i; - u32 ulDataCnt; - u32 ulRegValue; - s32 ulRet; - - ulRet = SFC_WriteEnable(sflash); - if ((!ulWriteLen) || (ulWriteLen > SFC_HARD_BUF_LEN) || (ulWriteLen & 0x3)) { - pr_err("[SFC] [%s %d]: len=%u err\n", __func__, __LINE__, ulWriteLen); - ulRet = HRD_ERR; - goto rel; - } - - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WriteEnable fail\n", __func__, __LINE__); - goto rel; - } - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, sflash->sflash_dev_params.ucOpcodePP); - - ulDataCnt = ulWriteLen >> 0x2; - for (i = 0; i < ulDataCnt; i++) { - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1 + (u32)(0x4 * i), ulData[i]); - } - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_ADDR, ulOffsetAddr); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= - (~(0xff << DATA_CNT)) & (~(1 << RW_DATA) & (~(1 << SEL_CS))); - ulRegValue |= ((ulWriteLen - 1) << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__); - goto rel; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) { - ulRet = HRD_ERR; - goto rel; - } - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - sflash->sflash_dev_params.ucOpcodeRDSR); - ulRet = SFC_CheckBusy(sflash, FLASH_WRITE_BUSY_WAIT_CNT); - - rel: - SFC_FlashUnlock(sflash); - - return ulRet; -} - -s32 SFC_RegByteWrite(struct SFC_SFLASH_INFO *sflash, - u8 ucData, u32 ulOffsetAddr) -{ - u32 ulRegValue; - s32 ulRet; - - ulRet = SFC_WriteEnable(sflash); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WriteEnable failed\r\n", __func__, __LINE__); - goto rel; - } - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, sflash->sflash_dev_params.ucOpcodePP); - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, ucData); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_ADDR, ulOffsetAddr); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= - (~(0xff << DATA_CNT)) & (~(1 << RW_DATA)) & (~(1 << SEL_CS)); - ulRegValue |= (0 << DATA_CNT) | (1 << ADDR_EN) | (1 << DATA_EN) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: wait int failed\r\n", __func__, __LINE__); - goto rel; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) { - ulRet = HRD_ERR; - goto rel; - } - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, sflash->sflash_dev_params.ucOpcodeRDSR); - ulRet = SFC_CheckBusy(sflash, FLASH_WRITE_BUSY_WAIT_CNT); - - rel: - SFC_FlashUnlock(sflash); - - return ulRet; -} diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_core.h b/drivers/mtd/hisilicon/sfc/hrd_sflash_core.h deleted file mode 100644 index ccf1d48334bdd..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_core.h +++ /dev/null @@ -1,160 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HRD_SFLASH_CORE_H__ -#define __HRD_SFLASH_CORE_H__ - -#include "hrd_sflash_driver.h" - -#define SFC_HARD_BUF_LEN (256) -#define SPI_FLASH_PAGE_SIZE (256) - -#define SPI_CMD_SR_WIP 1 /* Write in Progress bit in status register position */ -#define SPI_CMD_RDSR 0x05 /* Read Status Register */ - -/* 3Byte or 4Byte addr */ -#define SPI_FLASH_3BYTE_ADDR (1) -#define SPI_FLASH_4BYTE_ADDR (1 << 1) - - /* Standard SPI */ -#define STANDARD_SPI_IF (1) - -/* Dual Input/Dual Output SPI */ -#define DUAL_IN_DUAL_OUT_SPI_IF (1 << 1) -/* Dual I/O SPI */ -#define DUAL_IO_SPI_IF (1 << 2) -/* Full Dual I/O SPI */ -#define FULL_DUAL_IO_SPI_IF (1 << 3) -/* Quad Input/Quad Output SPI */ -#define QUAD_IN_DUAL_OUT_SPI_IF (1 << 5) -/* Quad I/O SPI */ -#define QUAD_IO_SPI_IF (1 << 6) -/* Full Quad SPI */ -#define FULL_QUAD_IO_SPI_IF (1 << 7) - -#define SFC_CHIP_CS 0 -#define WAIT_TIME_OUT 0xFFFFFF -#define ERASE_WAIT_TIME 50 - -#define SFC_INT_WAIT_CNT 1000000 -#define FLASH_ERASE_BUSY_WAIT_CNT 1000000 -#define FLASH_WRITE_BUSY_WAIT_CNT 1000 - -#define STATUS_REG_P_ERR (1 << 6) -#define STATUS_REG_E_ERR (1 << 5) -#define STATUS_REG_BUSY_BIT 0x1 -#define FLASH_SIZE_CS_BIT(x) (8 * (x)) - -#define SFC_OP_ERR_MASK (0x1EC) - -/* SFC REG */ -#define GLOBAL_CONFIG (0x0100) -#define TIMING (0x0110) -#define INTRAWSTATUS (0x0120) -#define INTSTATUS (0x0124) -#define INTMASK (0x0128) -#define INTCLEAR (0x012C) -#define VERSION (0x01F8) -#define VERSION_SEL (0x01FC) -#define BUS_CONFIG1 (0x0200) -#define BUS_CONFIG2 (0x0204) -#define BUS_FLASH_SIZE (0x0210) -#define BUS_BASE_ADDR_CS0 (0x0214) -#define BUS_BASE_ADDR_CS1 (0x0218) -#define BUS_ALIAS_ADDR (0x021C) -#define BUS_ALIAS_CS (0x0220) -#define BUS_DMA_CTRL (0x0240) -#define BUS_DMA_MEM_SADDR (0x0244) -#define BUS_DMA_FLASH_SADDR (0x0248) -#define BUS_DMA_LEN (0x024C) -#define BUS_DMA_AHB_CTRL (0x0250) -#define CMD_CONFIG (0x0300) -#define CMD_INS (0x0308) -#define CMD_ADDR (0x030C) - -#define CMD_DATABUF(x) (0x0400 + 4 * ((x) - 1)) - -#define CONFIG BUS_CONFIG1 -#define CMD CMD_CONFIG -#define INS CMD_INS -#define ADDR CMD_ADDR -#define DATABUFFER1 CMD_DATABUF(1) -#define DATABUFFER2 CMD_DATABUF(2) -#define DATABUFFER3 CMD_DATABUF(3) -#define DATABUFFER4 CMD_DATABUF(4) -#define DATABUFFER5 CMD_DATABUF(5) -#define DATABUFFER6 CMD_DATABUF(6) -#define DATABUFFER7 CMD_DATABUF(7) -#define DATABUFFER8 CMD_DATABUF(8) - -/* INT */ -#define INT_MASK (0x1ff) -#define CMD_OP_END_INT_BIT (1) - -/* CMD_CONFIG */ -#define LOCK_FLASH 20 -#define MEM_TYPE 17 -#define DATA_CNT 9 -#define RW_DATA 8 /* 0 read 1 write */ -#define DATA_EN 7 -#define CMD_DUMMY 4 -#define ADDR_EN 3 -#define SEL_CS 1 -#define START 0 - -union UN_SFC_CMD_CONFIG { - struct { - unsigned int start:1; - unsigned int sel_cs:1; - unsigned int rsv0:1; - unsigned int addr_en:1; - unsigned int dummy_byte_cnt:3; - unsigned int data_en:1; -#define SFC_CMD_CFG_READ 1 -#define SFC_CMD_CFG_WRITE 0 - unsigned int rw:1; -#define SFC_CMD_DATA_CNT(x) ((x) - 1) - unsigned int data_cnt:8; - unsigned int mem_if_type:3; - unsigned int rsv1:12; - } bits; - unsigned int u32; -}; - -u32 SFC_RegisterRead(u64 reg_addr); -void SFC_RegisterWrite(u64 reg_addr, u32 ulValue); -s32 SFC_ClearInt(u64 reg_addr); -s32 SFC_WaitInt(u64 reg_addr); -bool SFC_IsOpErr(u64 reg_addr); -s32 SFC_WriteEnable(struct SFC_SFLASH_INFO *sflash); -void SFC_FlashUnlock(struct SFC_SFLASH_INFO *sflash); -u32 SFC_ReadStatus(struct SFC_SFLASH_INFO *sflash); -s32 SFC_CheckBusy(struct SFC_SFLASH_INFO *sflash, u32 ulTimeOut); -s32 SFC_ClearStatus(struct SFC_SFLASH_INFO *sflash); -void SFC_CheckErr(struct SFC_SFLASH_INFO *sflash); -s32 SFC_CheckCmdExcStatus(struct SFC_SFLASH_INFO *sflash); -int SFC_WaitFlashIdle(struct SFC_SFLASH_INFO *sflash); -int SFC_GetDeviceId(struct SFC_SFLASH_INFO *sflash, u32 *id); -s32 SFC_RegWordAlignRead(struct SFC_SFLASH_INFO *sflash, - u32 ulOffsetAddr, u32 *pulData, u32 ulReadLen); -s32 SFC_RegByteRead(struct SFC_SFLASH_INFO *sflash, - u32 ulOffsetAddr, u8 *pucData); -s32 SFC_RegWordAlignWrite(struct SFC_SFLASH_INFO *sflash, - const u32 *ulData, u32 ulOffsetAddr, u32 ulWriteLen); -s32 SFC_RegByteWrite(struct SFC_SFLASH_INFO *sflash, - u8 ucData, u32 ulOffsetAddr); - -#endif diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.c b/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.c deleted file mode 100644 index 399c52481b9ad..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.c +++ /dev/null @@ -1,390 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/types.h> -#include <linux/sched.h> -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/blkdev.h> -#include <linux/console.h> -#include <linux/delay.h> -#include <linux/seq_file.h> -#include <linux/string.h> -#include <linux/slab.h> -#include <linux/device.h> -#include <linux/interrupt.h> -#include <linux/mtd/map.h> -#include <linux/mtd/mtd.h> -#include <linux/mutex.h> -#include <linux/version.h> -#include "hrd_common.h" -#include "hrd_sflash_driver.h" -#include "hrd_sflash_hal.h" - -#ifdef MTD_SFLASH_DEBUG -#define DB_LOCAL(x) x -#else -#define DB_LOCAL(x) -#endif - -#define SFLASH_SIZE_4K 0x1000 -#define SFLASH_SIZE_64K 0x10000 - -#define sflash_disable_irqs(flags, sflash_in_irq) \ - do { \ - sflash_in_irq = in_interrupt(); \ - if (!(sflash_in_irq)) \ - local_irq_save(flags); \ - } while (0) - -#define sflash_enable_irqs(flags, sflash_in_irq) \ - do { \ - if (!(sflash_in_irq)) \ - local_irq_restore(flags); \ - } while (0) - -static int sflash_read(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf); -static int sflash_write(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, const u_char *buf); -static int sflash_erase(struct mtd_info *mtd, struct erase_info *instr); -static void sflash_sync(struct mtd_info *mtd); -static int sflash_suspend(struct mtd_info *mtd); -static void sflash_resume(struct mtd_info *mtd); -static int sflash_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len); -static int sflash_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len); -static int sflash_block_isbad(struct mtd_info *mtd, loff_t ofs); -static int sflash_block_markbad(struct mtd_info *mtd, loff_t ofs); - -struct mtd_info *sflash_probe(struct map_info *map, struct resource *sfc_regres) -{ - struct mtd_info *mtd = NULL; - struct SFC_SFLASH_INFO *sflash = NULL; - unsigned long flags = 0; - unsigned long sflash_in_irq = 0; - - DB_LOCAL(pr_info("[SFC] INFO: entering %s\n", __func__)); - mtd = kmalloc(sizeof(*mtd), GFP_KERNEL); - if (!mtd) { - pr_err("ERROR: %s - Failed to allocate memory for mtd structure\n", __func__); - return NULL; - } - - sflash = kmalloc(sizeof(struct SFC_SFLASH_INFO), GFP_KERNEL); - if (!sflash) { - pr_err("[SFC] ERROR: %s - Failed to allocate memory for sflash structure\n", __func__); - kfree(mtd); - return NULL; - } - - memset(mtd, 0, sizeof(*mtd)); - memset(sflash, 0, sizeof(*sflash)); - - DB_LOCAL(pr_info("[SFC] INFO: %s - Base address %llx\n", __func__, map->phys)); - sflash->baseAddr = (u64) ioremap(map->phys, map->size); - if (!sflash->baseAddr) { - pr_err("[SFC] ERROR: %s - map flash error\n", __func__); - goto exit0; - } - - sflash->sfc_reg_base = (u64)ioremap_nocache(sfc_regres->start, resource_size(sfc_regres)); - - if (!sflash->sfc_reg_base) { - pr_err("[SFC] ERROR: %s - map register error\n", __func__); - goto exit1; - } - - mutex_init(&sflash->lock); - sflash->index = INVALID_DEVICE_NUMBER; - sflash_disable_irqs(flags, sflash_in_irq); - - if (hrd_sflash_init(sflash) != HRD_OK) { - sflash_enable_irqs(flags, sflash_in_irq); - pr_err("[SFC] ERROR: %s - Failed to initialize the SFlash.\n", __func__); - goto exit2; - } - - sflash_enable_irqs(flags, sflash_in_irq); - mtd->erasesize = sflash->sectorSize; - mtd->size = (u64) sflash->sectorSize * (u64) sflash->sectorNumber; - mtd->priv = map; - mtd->type = MTD_NORFLASH; - mtd->_erase = sflash_erase; - mtd->_read = sflash_read; - mtd->_write = sflash_write; - mtd->_sync = sflash_sync; - mtd->_suspend = sflash_suspend; - mtd->_resume = sflash_resume; - mtd->_lock = sflash_lock; - mtd->_unlock = sflash_unlock; - mtd->_block_isbad = sflash_block_isbad; - mtd->_block_markbad = sflash_block_markbad; - /* just like MTD_CAP_NORFLASH */ - mtd->flags = (MTD_WRITEABLE | MTD_BIT_WRITEABLE); - mtd->name = map->name; - mtd->writesize = 1; - - map->fldrv_priv = sflash; - - DB_LOCAL(pr_info("[SFC] INFO: %s - Detected SFlash device (size 0x%llx)\n", __func__, mtd->size)); - DB_LOCAL(pr_info("[SFC] Base Address : 0x%llx\n", sflash->baseAddr)); - DB_LOCAL(pr_info("[SFC] Manufacturer ID : 0x%02x\n", sflash->manufacturerId)); - DB_LOCAL(pr_info("[SFC] Device ID : 0x%04x\n", sflash->deviceId)); - DB_LOCAL(pr_info("[SFC] Sector Size : 0x%x\n", sflash->sectorSize)); - DB_LOCAL(pr_info("[SFC] Sector Number : %d\n", sflash->sectorNumber)); - - pr_info("[SFC] detected name:%s\n", sflash->sflash_dev_params.deviceModel); - - return mtd; - - exit0: - kfree(mtd); - kfree(sflash); - return NULL; - exit1: - iounmap((void *)sflash->baseAddr); - kfree(mtd); - kfree(sflash); - return NULL; - exit2: - iounmap((void *)sflash->baseAddr); - iounmap((void *)sflash->sfc_reg_base); - kfree(mtd); - kfree(sflash); - return NULL; -} - -void sflash_destroy(struct mtd_info *mtd) -{ - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - - DB_LOCAL(pr_info("[SFC] INFO: %s called\n", __func__)); - - if (sflash->baseAddr != 0) - iounmap((void *)sflash->baseAddr); - - if (sflash->sfc_reg_base != 0) - iounmap((void *)sflash->sfc_reg_base); - - kfree(mtd); - kfree(sflash); -} - -static int sflash_read(struct mtd_info *mtd, loff_t from, size_t len, - size_t *retlen, u_char *buf) -{ - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - u32 offset = ((u32) from); - int ret; - - *retlen = 0; - - DB_LOCAL(pr_info("[SFC] INFO: %s - offset %08x, len %d\n", __func__, offset, (int)len)); - - mutex_lock(&sflash->lock); - ret = SFC_RegModeRead(sflash, offset, (u8 *) buf, (u32) len); - if (ret != HRD_OK) { - mutex_unlock(&sflash->lock); - pr_err("[SFC] ERROR: %s - Failed to read block\n", __func__); - return -1; - } - - mutex_unlock(&sflash->lock); - *retlen = len; - - DB_LOCAL(pr_info(" [SFC] - OK\n")); - return 0; -} - -static int sflash_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t *retlen, const u_char *buf) -{ - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - u32 offset = ((u32) to); - int ret; - - *retlen = 0; - DB_LOCAL(pr_info("[SFC] INFO: %s-offset %08x, len %d\n", __func__, offset, (u32) len)); - - mutex_lock(&sflash->lock); - - ret = SFC_RegModeWrite(sflash, offset, buf, (u32) len); - if (ret != HRD_OK) { - mutex_unlock(&sflash->lock); - pr_err("[SFC] ERROR: %s - Failed to write block\n", __func__); - return -1; - } - - mutex_unlock(&sflash->lock); - - *retlen = len; - - DB_LOCAL(pr_info("[SFC] - OK")); - return 0; -} - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -static int sflash_erase(struct mtd_info *mtd, struct erase_info *instr) -{ - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - u64 fsec, lsec; - u64 i; - - DB_LOCAL(pr_info("[SFC] INFO: %s - Addr %08llx, len %lld\n", __func__, instr->addr, instr->len)); - - if (!sflash) { - pr_err("[SFC] Error: sflash is NULL\n"); - return -EINVAL; - } - - if (instr->addr & (mtd->erasesize - 1)) { - pr_err("[SFC] Error: %s - Erase address not sector alligned\n", __func__); - return -EINVAL; - } - - if (instr->len & (mtd->erasesize - 1)) { - pr_err("[SFC] Error: %s - Erase length is not sector alligned\n", __func__); - return -EINVAL; - } - - if (instr->len + instr->addr > mtd->size) { - pr_err("[SFC] Error: %s - Erase exceeded flash size\n", __func__); - return -EINVAL; - } - - /* The start 64k of SPANSION flash can be erased only by using the 4k. */ - { - fsec = instr->addr; - do_div(fsec, SFLASH_SIZE_4K); - lsec = MIN(instr->addr + instr->len, SFLASH_SIZE_64K); - do_div(lsec, SFLASH_SIZE_4K); - - if (fsec < lsec) { - pr_info("[SFC] INFO: %s - for 4K from sector %lld to %lld\n", __func__, fsec, lsec - 1); - mutex_lock(&sflash->lock); - - SFC_CheckErr(sflash); - - for (i = fsec; i < lsec; i++) { - if (SFC_BlockErase(sflash, ((u32)i) * SFLASH_SIZE_4K, 0x20) != HRD_OK) { - mutex_unlock(&sflash->lock); - pr_err("[SFC] Error: %s - mvSFlashSectorErase on sector %lld\n", __func__, i); - return -1; - } - } - - mutex_unlock(&sflash->lock); - } - } - - fsec = instr->addr; - do_div(fsec, mtd->erasesize); - lsec = instr->len; - do_div(lsec, mtd->erasesize); - lsec = (fsec + lsec); - - DB_LOCAL(pr_info("[SFC] INFO: %s - from sector %u to %u\n", __func__, fsec, lsec - 1)); - - mutex_lock(&sflash->lock); - - for (i = fsec; i < lsec; i++) { - if (SFC_BlockErase(sflash, ((u32) i) * mtd->erasesize, 0) != HRD_OK) { - mutex_unlock(&sflash->lock); - pr_err("[SFC] Error: %s - mvSFlashSectorErase on sector %lld\n", __func__, i); -#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 16, 0) - instr->fail_addr = ((u32) i) * mtd->erasesize; -#endif - - return -1; - } - } - - mutex_unlock(&sflash->lock); - -#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0) - instr->state = MTD_ERASE_DONE; - mtd_erase_callback(instr); -#endif - - return 0; -} - -static int sflash_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) -{ - int ret; - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - - DB_LOCAL(pr_info("[SFC] INFO: %s called\n", __func__)); - - mutex_lock(&sflash->lock); - ret = SFC_WPSet(sflash, true); - mutex_unlock(&sflash->lock); - - return ret; -} - -static int sflash_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) -{ - int ret; - struct map_info *map = mtd->priv; - struct SFC_SFLASH_INFO *sflash = map->fldrv_priv; - - pr_info("[SFC] INFO: %s called\n", __func__); - - mutex_lock(&sflash->lock); - ret = SFC_WPSet(sflash, false); - mutex_unlock(&sflash->lock); - - return ret; -} - -static void sflash_sync(struct mtd_info *mtd) -{ - DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__)); -} - -static int sflash_suspend(struct mtd_info *mtd) -{ - DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY()\n", __func__)); - return 0; -} - -static void sflash_resume(struct mtd_info *mtd) -{ - DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__)); -} - -static int sflash_block_isbad(struct mtd_info *mtd, loff_t ofs) -{ - DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__)); - return 0; -} - -static int sflash_block_markbad(struct mtd_info *mtd, loff_t ofs) -{ - DB_LOCAL(pr_info("[SFC] INFO: %s called - DUMMY\n", __func__)); - return 0; -} - - diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.h b/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.h deleted file mode 100644 index f659758257847..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_driver.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _HRD_SFLASH_DRIVER_H -#define _HRD_SFLASH_DRIVER_H - -#include <linux/mtd/map.h> - -#define INVALID_DEVICE_NUMBER 0xFFFFFFFF - -/* SFC cs num */ -#define SFC_CS_MAX_NUM 2 - -#define MTD_MAX_FLASH_NUMBER 1 - -/* SFC cs size 1GByte */ -#define SFC_CS_MAX_SIZE 0x40000000 - -#define HI_ARRAY_SIZE(a) ((sizeof(a)) / (sizeof(a[0]))) - -struct maps_init_info { - struct map_info mapInfo; - const char **mtdDrv; - struct mtd_info *mtdInfo; -}; - -struct sfc_host { - u32 mapsNum; - struct maps_init_info maps[MTD_MAX_FLASH_NUMBER]; -}; - -struct SPI_FLASH_DEVICE_PARAMS { - u8 ucOpcodeWREN; /* Write enable opcode */ - u8 ucOpcodeWRDI; /* Write disable opcode */ - u8 ucOpcodeRDID; /* Read ID opcode */ - u8 ucOpcodeRDSR; /* Read Status Register opcode */ - u8 ucOpcodeWRSR; /* Write Status register opcode */ - u8 ucOpcodeREAD; /* Read opcode */ - u8 ucOpcodeFSTRD; /* Fast Read opcode */ - u8 ucOpcodePP; /* Page program opcode */ - u8 ucOpcodeSSE; /* SubSector erase opcode */ - u8 ucOpcodeSE; /* Sector erase opcode */ - u8 ucOpcodeBE; /* Bulk erase opcode */ - u8 ucOpcodeRES; /* Read electronic signature */ - u8 ucOpcodePwrSave; /* Go into power save mode */ - u8 ucOpcodeRDVECR; /* Read Volatile Enhanced Configuration Reg */ - u8 ucOpcodeWRVECR; /* Write Volatile Enhanced Configuration Reg */ - u8 ucOpcodeEN4BAddr; /* Enter 4-byte address mode */ - u8 ucOpcodeEX4BAddr; /* Exit 4-byte address mode */ - u8 ucBusyFlagBit; - u8 ucReserve1; - u8 ucReserve2; - u32 ulSectorSize; /* Size of each sector */ - u32 ulBlockNumber; /* Number of blocks */ - u32 ulBlockSize; /* size of each block */ - const char *deviceModel; /* string with the device model */ - u32 ulManufacturerId; /* The manufacturer ID */ - u32 ulDeviceId; /* Device ID */ - u32 ulIdCFILen; /* ID-CFI Length - number bytes following */ - u32 ulPhySecArch; /* Physical Sector Architecture */ - u32 ulFId; /* Family ID */ - /* The MAX frequency that can be used with the device */ - u32 ulSpiMaxFreq; - /* The MAX frequency that can be used with the device for fast reads */ - u32 ulSpiMaxFastFreq; - /* Number of dumy bytes to read before real data when working in fast read mode. */ - u32 ulSpiFastRdDummyBytes; - u32 ulAddrModeSuport; /* it[1:0]:4/3Byte addr mode, 1:support */ - u32 ulIfTypeSuport; /* bit[6:0]:show 7 type, 1:supporu */ -}; - -struct SFC_SFLASH_INFO { - u64 baseAddr; /* Flash Base Address used in fast mode */ - u64 sfc_reg_base; /* sfc reg base addr */ - u32 space_size; - u8 manufacturerId; /* Manufacturer ID */ - u16 deviceId; /* Device ID */ - u32 sectorSize; /* Size of each sector - all the same */ - u32 sectorNumber; /* Number of sectors */ - u32 pageSize; /* Page size - affect allignment */ - /* index of the device in the sflash table (internal parameter) */ - u32 index; - u32 addr_mode; - u32 sfc_type_flag; - struct SPI_FLASH_DEVICE_PARAMS sflash_dev_params; - struct mutex lock; -}; - -extern struct mtd_info *sflash_probe(struct map_info *map, struct resource *sfc_regres); -extern void sflash_destroy(struct mtd_info *mtd); - -#endif /* _HRD_SLASH_DRIVER_H */ diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.c b/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.c deleted file mode 100644 index 81fed47ec15e5..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.c +++ /dev/null @@ -1,1159 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/clk.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/of_gpio.h> -#include <linux/of_platform.h> -#include <linux/of_address.h> -#include <linux/platform_device.h> -#include <linux/resource.h> -#include <linux/signal.h> -#include <linux/types.h> -#include "hrd_common.h" -#include "hrd_sflash_driver.h" -#include "hrd_sflash_core.h" -#include "hrd_sflash_spec.h" - -#define BIT0 (1<<0) -#define SPI_CMD_WRR 0x01 /* Write Register */ -#define SPI_CMD_CLSR 0x30 /* Clear Status Register */ - -struct SPI_FLASH_DEVICE_PARAMS g_stSPIFlashDevTable[] = { - /* NUMONYX N25Q128 SPI flash, 16MB, 256 sectors of 64K each */ - { - HISI_N25Q_WREN_CMND_OPCD, - HISI_N25Q_WRDI_CMND_OPCD, - HISI_N25Q_RDID_CMND_OPCD, - HISI_N25Q_RDSR_CMND_OPCD, - HISI_N25Q_WRSR_CMND_OPCD, - HISI_N25Q_READ_CMND_OPCD, - HISI_N25Q_FAST_RD_CMND_OPCD, - HISI_N25Q_PP_CMND_OPCD, - HISI_N25Q_SSE_CMND_OPCD, - HISI_N25Q_SE_CMND_OPCD, - HISI_N25Q_BE_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_N25Q_RDVECR_CMND_OPCD, - HISI_N25Q_WRVECR_CMND_OPCD, - HISI_N25Q_EN4BADDR_CMND_OPCD, - HISI_N25Q_EX4BADDR_CMND_OPCD, - HISI_N25Q_BUSY_FLAG_BIT, - 0, - 0, - HISI_N25Q128_PAGE_SIZE, - HISI_N25Q128_SECTOR_NUMBER, - HISI_N25Q128_SECTOR_SIZE, - "NUMONYX N25Q128", - HISI_N25Q128_MANF_ID, - HISI_N25Q128_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_N25Q128_MAX_SPI_FREQ, - HISI_N25Q128_MAX_FAST_SPI_FREQ, - HISI_N25Q128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* MIRCON MT25QU128AB SPI flash, 16MB, 256 sectors of 64K each */ - { - HISI_N25Q_WREN_CMND_OPCD, - HISI_N25Q_WRDI_CMND_OPCD, - HISI_N25Q_RDID_CMND_OPCD, - HISI_N25Q_RDSR_CMND_OPCD, - HISI_N25Q_WRSR_CMND_OPCD, - HISI_N25Q_READ_CMND_OPCD, - HISI_N25Q_FAST_RD_CMND_OPCD, - HISI_N25Q_PP_CMND_OPCD, - HISI_N25Q_SSE_CMND_OPCD, - HISI_N25Q_SE_CMND_OPCD, - HISI_N25Q_BE_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_N25Q_RDVECR_CMND_OPCD, - HISI_N25Q_WRVECR_CMND_OPCD, - HISI_N25Q_EN4BADDR_CMND_OPCD, - HISI_N25Q_EX4BADDR_CMND_OPCD, - HISI_N25Q_BUSY_FLAG_BIT, - 0, - 0, - HISI_N25Q128_PAGE_SIZE, - HISI_N25Q128_SECTOR_NUMBER, - HISI_N25Q128_SECTOR_SIZE, - "MIRCON MT25QU128AB", - HISI_N25Q128B_MANF_ID, - HISI_N25Q128B_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_N25Q128_MAX_SPI_FREQ, - HISI_N25Q128_MAX_FAST_SPI_FREQ, - HISI_N25Q128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* NUMONYX N25Q256 SPI flash, 32MB, 256 sectors of 64K each */ - { - HISI_N25Q_WREN_CMND_OPCD, - HISI_N25Q_WRDI_CMND_OPCD, - HISI_N25Q_RDID_CMND_OPCD, - HISI_N25Q_RDSR_CMND_OPCD, - HISI_N25Q_WRSR_CMND_OPCD, - HISI_N25Q_READ_CMND_OPCD, - HISI_N25Q_FAST_RD_CMND_OPCD, - HISI_N25Q_PP_CMND_OPCD, - HISI_N25Q_SSE_CMND_OPCD, - HISI_N25Q_SE_CMND_OPCD, - HISI_N25Q_BE_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_N25Q_RDVECR_CMND_OPCD, - HISI_N25Q_WRVECR_CMND_OPCD, - HISI_N25Q_EN4BADDR_CMND_OPCD, - HISI_N25Q_EX4BADDR_CMND_OPCD, - HISI_N25Q_BUSY_FLAG_BIT, - 0, - 0, - HISI_N25Q256_PAGE_SIZE, - HISI_N25Q256_SECTOR_NUMBER, - HISI_N25Q256_SECTOR_SIZE, - "NUMONYX N25Q256", - HISI_N25Q256_MANF_ID, - HISI_N25Q256_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_N25Q256_MAX_SPI_FREQ, - HISI_N25Q256_MAX_FAST_SPI_FREQ, - HISI_N25Q256_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* ST M25P80 SPI flash, 1MB, 16 sectors of 64K each */ - { - HISI_M25P_WREN_CMND_OPCD, - HISI_M25P_WRDI_CMND_OPCD, - HISI_M25P_RDID_CMND_OPCD, - HISI_M25P_RDSR_CMND_OPCD, - HISI_M25P_WRSR_CMND_OPCD, - HISI_M25P_READ_CMND_OPCD, - HISI_M25P_FAST_RD_CMND_OPCD, - HISI_M25P_PP_CMND_OPCD, - HISI_M25P_SSE_CMND_OPCD, - HISI_M25P_SE_CMND_OPCD, - HISI_M25P_BE_CMND_OPCD, - HISI_M25P_RES_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_M25P_PAGE_SIZE, - HISI_M25P80_SECTOR_NUMBER, - HISI_M25P80_SECTOR_SIZE, - "ST M25P80", - HISI_M25PXXX_ST_MANF_ID, - HISI_M25P80_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_M25P80_MAX_SPI_FREQ, - HISI_M25P80_MAX_FAST_SPI_FREQ, - HISI_M25P80_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* ST M25P32 SPI flash, 4MB, 64 sectors of 64K each */ - { - HISI_M25P_WREN_CMND_OPCD, - HISI_M25P_WRDI_CMND_OPCD, - HISI_M25P_RDID_CMND_OPCD, - HISI_M25P_RDSR_CMND_OPCD, - HISI_M25P_WRSR_CMND_OPCD, - HISI_M25P_READ_CMND_OPCD, - HISI_M25P_FAST_RD_CMND_OPCD, - HISI_M25P_PP_CMND_OPCD, - HISI_M25P_SSE_CMND_OPCD, - HISI_M25P_SE_CMND_OPCD, - HISI_M25P_BE_CMND_OPCD, - HISI_M25P_RES_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_M25P_PAGE_SIZE, - HISI_M25P32_SECTOR_NUMBER, - HISI_M25P32_SECTOR_SIZE, - "ST M25P32", - HISI_M25PXXX_ST_MANF_ID, - HISI_M25P32_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_M25P32_MAX_SPI_FREQ, - HISI_M25P32_MAX_FAST_SPI_FREQ, - HISI_M25P32_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* ST M25P64 SPI flash, 8MB, 128 sectors of 64K each */ - { - HISI_M25P_WREN_CMND_OPCD, - HISI_M25P_WRDI_CMND_OPCD, - HISI_M25P_RDID_CMND_OPCD, - HISI_M25P_RDSR_CMND_OPCD, - HISI_M25P_WRSR_CMND_OPCD, - HISI_M25P_READ_CMND_OPCD, - HISI_M25P_FAST_RD_CMND_OPCD, - HISI_M25P_PP_CMND_OPCD, - HISI_M25P_SSE_CMND_OPCD, - HISI_M25P_SE_CMND_OPCD, - HISI_M25P_BE_CMND_OPCD, - HISI_M25P_RES_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_M25P_PAGE_SIZE, - HISI_M25P64_SECTOR_NUMBER, - HISI_M25P64_SECTOR_SIZE, - "ST M25P64", - HISI_M25PXXX_ST_MANF_ID, - HISI_M25P64_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_M25P64_MAX_SPI_FREQ, - HISI_M25P64_MAX_FAST_SPI_FREQ, - HISI_M25P64_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* ST M25P128 SPI flash, 16MB, 64 sectors of 256K each */ - { - HISI_M25P_WREN_CMND_OPCD, - HISI_M25P_WRDI_CMND_OPCD, - HISI_M25P_RDID_CMND_OPCD, - HISI_M25P_RDSR_CMND_OPCD, - HISI_M25P_WRSR_CMND_OPCD, - HISI_M25P_READ_CMND_OPCD, - HISI_M25P_FAST_RD_CMND_OPCD, - HISI_M25P_PP_CMND_OPCD, - HISI_M25P_SSE_CMND_OPCD, - HISI_M25P_SE_CMND_OPCD, - HISI_M25P_BE_CMND_OPCD, - HISI_M25P_RES_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_M25P_PAGE_SIZE, - HISI_M25P128_SECTOR_NUMBER, - HISI_M25P128_SECTOR_SIZE, - "ST M25P128", - HISI_M25PXXX_ST_MANF_ID, - HISI_M25P128_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_M25P128_MAX_SPI_FREQ, - HISI_M25P128_MAX_FAST_SPI_FREQ, - HISI_M25P128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* Macronix MXIC MX25L6405 SPI flash, 8MB, 128 sectors of 64K each */ - { - HISI_MX25L_WREN_CMND_OPCD, - HISI_MX25L_WRDI_CMND_OPCD, - HISI_MX25L_RDID_CMND_OPCD, - HISI_MX25L_RDSR_CMND_OPCD, - HISI_MX25L_WRSR_CMND_OPCD, - HISI_MX25L_READ_CMND_OPCD, - HISI_MX25L_FAST_RD_CMND_OPCD, - HISI_MX25L_PP_CMND_OPCD, - HISI_MX25L_SSE_CMND_OPCD, - HISI_MX25L_SE_CMND_OPCD, - HISI_MX25L_BE_CMND_OPCD, - HISI_MX25L_RES_CMND_OPCD, - HISI_MX25L_DP_CMND_OPCD, - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_MXIC_PAGE_SIZE, - HISI_MX25L6405_SECTOR_NUMBER, - HISI_MX25L6405_SECTOR_SIZE, - "MXIC MX25L6405", - HISI_MXIC_MANF_ID, - HISI_MX25L6405_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_MX25L6405_MAX_SPI_FREQ, - HISI_MX25L6405_MAX_FAST_SPI_FREQ, - HISI_MX25L6405_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* Macronix MXIC MX25L1606E SPI flash, 2MB, 32 sectors of 64K each */ - { - HISI_MX25L_WREN_CMND_OPCD, - HISI_MX25L_WRDI_CMND_OPCD, - HISI_MX25L_RDID_CMND_OPCD, - HISI_MX25L_RDSR_CMND_OPCD, - HISI_MX25L_WRSR_CMND_OPCD, - HISI_MX25L_READ_CMND_OPCD, - HISI_MX25L_FAST_RD_CMND_OPCD, - HISI_MX25L_PP_CMND_OPCD, - HISI_MX25L_SSE_CMND_OPCD, - HISI_MX25L_SE_CMND_OPCD, - HISI_MX25L_BE_CMND_OPCD, - HISI_MX25L_RES_CMND_OPCD, - HISI_MX25L_DP_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* can't support next 5 code */ - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - 0, - 0, - HISI_MXIC_PAGE_SIZE, - HISI_MX25L1606E_SECTOR_NUMBER, - HISI_MX25L1606E_SECTOR_SIZE, - "MXIC MX25L1606E", - HISI_MXIC_MANF_ID, - HISI_MX25L1606E_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_MX25L1606E_MAX_SPI_FREQ, - HISI_MX25L1606E_MAX_FAST_SPI_FREQ, - HISI_MX25L1606E_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* Macronix MXIC MX25U12835F SPI flash, 16MB, 255 sectors of 64K each */ - { - HISI_MX25U12835F_WREN_CMND_OPCD, - HISI_MX25U12835F_WRDI_CMND_OPCD, - HISI_MX25U12835F_RDID_CMND_OPCD, - HISI_MX25U12835F_RDSR_CMND_OPCD, - HISI_MX25U12835F_WRSR_CMND_OPCD, - HISI_MX25U12835F_READ_CMND_OPCD, - HISI_MX25U12835F_FAST_RD_CMND_OPCD, - HISI_MX25U12835F_PP_CMND_OPCD, - HISI_MX25U12835F_SSE_CMND_OPCD, - HISI_MX25U12835F_SE_CMND_OPCD, - HISI_MX25U12835F_BE_CMND_OPCD, - HISI_MX25U12835F_RES_CMND_OPCD, - HISI_MX25U12835F_DP_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* can't support next 5 code */ - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - 0, - 0, - HISI_MX25U12835F_PAGE_SIZE, - HISI_MX25U12835F_SECTOR_NUMBER, - HISI_MX25U12835F_SECTOR_SIZE, - "MXIC MX25U12835F", - HISI_MX25U12835F_MANF_ID, - HISI_MX25U12835F_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_MX25U12835F_MAX_SPI_FREQ, - HISI_MX25U12835F_MAX_FAST_SPI_FREQ, - HISI_MX25U12835F_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* SPANSION S25FL128P SPI flash, 16MB, 64 sectors of 256K each */ - { - HISI_S25FL_WREN_CMND_OPCD, - HISI_S25FL_WRDI_CMND_OPCD, - HISI_S25FL_RDID_CMND_OPCD, - HISI_S25FL_RDSR_CMND_OPCD, - HISI_S25FL_WRSR_CMND_OPCD, - HISI_S25FL_READ_CMND_OPCD, - HISI_S25FL_FAST_RD_CMND_OPCD, - HISI_S25FL_PP_CMND_OPCD, - HISI_S25FL_SSE_CMND_OPCD, - HISI_S25FL_SE_CMND_OPCD, - HISI_S25FL_BE_CMND_OPCD, - HISI_S25FL_RES_CMND_OPCD, - HISI_S25FL_DP_CMND_OPCD, - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_S25FL_PAGE_SIZE, - HISI_S25FL128_SECTOR_NUMBER, - HISI_S25FL128_SECTOR_SIZE, - "SPANSION S25FL128", - HISI_SPANSION_MANF_ID, - HISI_S25FL128_DEVICE_ID, - 0xff, - 0xff, - 0x80, - HISI_S25FL128_MAX_SPI_FREQ, - HISI_M25P128_MAX_FAST_SPI_FREQ, - HISI_M25P128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* SPANSION S25FS128S SPI flash, 16MB, 255 sectors of 64K each + */ - { - HISI_S25FL_WREN_CMND_OPCD, - HISI_S25FL_WRDI_CMND_OPCD, - HISI_S25FL_RDID_CMND_OPCD, - HISI_S25FL_RDSR_CMND_OPCD, - HISI_S25FL_WRSR_CMND_OPCD, - HISI_S25FL_READ_CMND_OPCD, - HISI_S25FL_FAST_RD_CMND_OPCD, - HISI_S25FL_PP_CMND_OPCD, - HISI_S25FL_SSE_CMND_OPCD, - HISI_S25FL_SE_CMND_OPCD, - HISI_S25FL_BE_CMND_OPCD, - HISI_S25FL_RES_CMND_OPCD, - HISI_S25FL_DP_CMND_OPCD, - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_S25FL_PAGE_SIZE, - HISI_S25FL128_SECTOR_NUMBER, - HISI_S25FL128_SECTOR_SIZE, - "SPANSION S25FS128", - HISI_SPANSION_MANF_ID, - HISI_S25FL128_DEVICE_ID, - 0xff, - 0xff, - 0x81, - HISI_S25FL128_MAX_SPI_FREQ, - HISI_M25P128_MAX_FAST_SPI_FREQ, - HISI_M25P128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - /* ATMEL AT25DF641 SPI flash, 8MB, 128 sectors of 64K each */ - { - HISI_AT25DF_WREN_CMND_OPCD, - HISI_AT25DF_WRDI_CMND_OPCD, - HISI_AT25DF_RDID_CMND_OPCD, - HISI_AT25DF_RDSR_CMND_OPCD, - HISI_AT25DF_WRSR_CMND_OPCD, - HISI_AT25DF_READ_CMND_OPCD, - HISI_AT25DF_FAST_RD_CMND_OPCD, - HISI_AT25DF_PP_CMND_OPCD, - HISI_AT25DF_SSE_CMND_OPCD, - HISI_AT25DF_SE_CMND_OPCD, - HISI_AT25DF_BE_CMND_OPCD, - HISI_AT25DF_RES_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, /* power save not supported */ - HISI_SFLASH_UNKOWN_OPCD, /* next code need see datasheet */ - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_AT25DF_PAGE_SIZE, - HISI_AT25DF641_SECTOR_NUMBER, - HISI_AT25DF641_SECTOR_SIZE, - "AT 25DF641", - HISI_AT25DFXXX_AT_MANF_ID, - HISI_AT25DF641_DEVICE_ID, - 0xff, - 0xff, - 0xff, - HISI_AT25DF641_MAX_SPI_FREQ, - HISI_AT25DF641_MAX_FAST_SPI_FREQ, - HISI_AT25DF641_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* MIRCON DEFAULT */ - { - HISI_N25Q_WREN_CMND_OPCD, - HISI_N25Q_WRDI_CMND_OPCD, - HISI_N25Q_RDID_CMND_OPCD, - HISI_N25Q_RDSR_CMND_OPCD, - HISI_N25Q_WRSR_CMND_OPCD, - HISI_N25Q_READ_CMND_OPCD, - HISI_N25Q_FAST_RD_CMND_OPCD, - HISI_N25Q_PP_CMND_OPCD, - HISI_N25Q_SSE_CMND_OPCD, - HISI_N25Q_SE_CMND_OPCD, - HISI_N25Q_BE_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_N25Q_RDVECR_CMND_OPCD, - HISI_N25Q_WRVECR_CMND_OPCD, - HISI_N25Q_EN4BADDR_CMND_OPCD, - HISI_N25Q_EX4BADDR_CMND_OPCD, - HISI_N25Q_BUSY_FLAG_BIT, - 0, - 0, - HISI_N25Q128_PAGE_SIZE, - HISI_N25Q128_SECTOR_NUMBER, - HISI_N25Q128_SECTOR_SIZE, - "MIRCON DEFAULT", - HISI_N25Q128B_MANF_ID, - 0xffff, - 0xff, - 0xff, - 0xff, - HISI_N25Q128_MAX_SPI_FREQ, - HISI_N25Q128_MAX_FAST_SPI_FREQ, - HISI_N25Q128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* MIXC DEFAULT */ - { - HISI_MX25U12835F_WREN_CMND_OPCD, - HISI_MX25U12835F_WRDI_CMND_OPCD, - HISI_MX25U12835F_RDID_CMND_OPCD, - HISI_MX25U12835F_RDSR_CMND_OPCD, - HISI_MX25U12835F_WRSR_CMND_OPCD, - HISI_MX25U12835F_READ_CMND_OPCD, - HISI_MX25U12835F_FAST_RD_CMND_OPCD, - HISI_MX25U12835F_PP_CMND_OPCD, - HISI_MX25U12835F_SSE_CMND_OPCD, - HISI_MX25U12835F_SE_CMND_OPCD, - HISI_MX25U12835F_BE_CMND_OPCD, - HISI_MX25U12835F_RES_CMND_OPCD, - HISI_MX25U12835F_DP_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - 0, - 0, - HISI_MX25U12835F_PAGE_SIZE, - HISI_MX25U12835F_SECTOR_NUMBER, - HISI_MX25U12835F_SECTOR_SIZE, - "MIXC DEFAULT", - HISI_MX25U12835F_MANF_ID, - 0xffff, - 0xff, - 0xff, - 0xff, - HISI_MX25U12835F_MAX_SPI_FREQ, - HISI_MX25U12835F_MAX_FAST_SPI_FREQ, - HISI_MX25U12835F_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* SPANSION DEFAULT */ - { - HISI_S25FL_WREN_CMND_OPCD, - HISI_S25FL_WRDI_CMND_OPCD, - HISI_S25FL_RDID_CMND_OPCD, - HISI_S25FL_RDSR_CMND_OPCD, - HISI_S25FL_WRSR_CMND_OPCD, - HISI_S25FL_READ_CMND_OPCD, - HISI_S25FL_FAST_RD_CMND_OPCD, - HISI_S25FL_PP_CMND_OPCD, - HISI_S25FL_SSE_CMND_OPCD, - HISI_S25FL_SE_CMND_OPCD, - HISI_S25FL_BE_CMND_OPCD, - HISI_S25FL_RES_CMND_OPCD, - HISI_S25FL_DP_CMND_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - HISI_SFLASH_UNKOWN_OPCD, - 0, - 0, - HISI_S25FL_PAGE_SIZE, - HISI_S25FL128_SECTOR_NUMBER, - HISI_S25FL128_SECTOR_SIZE, - "SPANSION DEFAULT", - HISI_SPANSION_MANF_ID, - 0xffff, - 0xff, - 0xff, - 0xff, - HISI_S25FL128_MAX_SPI_FREQ, - HISI_M25P128_MAX_FAST_SPI_FREQ, - HISI_M25P128_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF}, - - /* DEFAULT */ - { - HISI_MX25U12835F_WREN_CMND_OPCD, - HISI_MX25U12835F_WRDI_CMND_OPCD, - HISI_MX25U12835F_RDID_CMND_OPCD, - HISI_MX25U12835F_RDSR_CMND_OPCD, - HISI_MX25U12835F_WRSR_CMND_OPCD, - HISI_MX25U12835F_READ_CMND_OPCD, - HISI_MX25U12835F_FAST_RD_CMND_OPCD, - HISI_MX25U12835F_PP_CMND_OPCD, - HISI_MX25U12835F_SSE_CMND_OPCD, - HISI_MX25U12835F_SE_CMND_OPCD, - HISI_MX25U12835F_BE_CMND_OPCD, - HISI_MX25U12835F_RES_CMND_OPCD, - HISI_MX25U12835F_DP_CMND_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - HISI_SFLASH_NO_SPECIFIC_OPCD, - 0, - 0, - HISI_MX25U12835F_PAGE_SIZE, - HISI_MX25U12835F_SECTOR_NUMBER, - HISI_MX25U12835F_SECTOR_SIZE, - "DEFAULT", - 0xff, - 0xffff, - 0xff, - 0xff, - 0xff, - HISI_MX25U12835F_MAX_SPI_FREQ, - HISI_MX25U12835F_MAX_FAST_SPI_FREQ, - HISI_MX25U12835F_FAST_READ_DUMMY_BYTES, - SPI_FLASH_3BYTE_ADDR, - STANDARD_SPI_IF} -}; - -s32 SFC_BlockErase(struct SFC_SFLASH_INFO *sflash, u32 ulAddr, u32 ErCmd) -{ - u32 ulRegValue; - s32 ulRet; - - ulRet = SFC_WriteEnable(sflash); - if (ulRet != HRD_OK) { - pr_err("[%s %d]: SFC_WriteEnable fail\n", __func__, __LINE__); - goto rel; - } - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, - ErCmd ? ErCmd : sflash->sflash_dev_params.ucOpcodeSE); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_ADDR, ulAddr); - - /* set configure reg and startup */ - ulRegValue = SFC_RegisterRead(sflash->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(1 << DATA_EN) & (~(1 << SEL_CS))); - ulRegValue |= ((SFC_CHIP_CS << SEL_CS) | (1 << START) | (1 << ADDR_EN)); - - wmb(); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, ulRegValue); - ulRet = SFC_WaitInt(sflash->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitInt fail\n", __func__, __LINE__); - goto rel; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) { - ulRet = HRD_ERR; - goto rel; - } - - ulRet = SFC_CheckBusy(sflash, FLASH_ERASE_BUSY_WAIT_CNT); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_CheckBusy fail\n", __func__, __LINE__); - goto rel; - } - - rel: - SFC_FlashUnlock(sflash); - return ulRet; -} - -static s32 _SFC_RegModeWrite(struct SFC_SFLASH_INFO *sflash, - u32 offset, const u8 *pucSrc, u32 ulWriteLen) -{ - u32 i; - s32 slRet; - u32 ulRemain; - u32 ulAlignLen; - - ulRemain = ulWriteLen % SFC_HARD_BUF_LEN; - ulAlignLen = ulWriteLen - ulRemain; - - for (i = 0; i < ulAlignLen; i += SFC_HARD_BUF_LEN) { - slRet = SFC_RegWordAlignWrite(sflash, (const u32 *)(pucSrc + i), offset + i, SFC_HARD_BUF_LEN); - if (slRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegWordWrite fail\n", __func__, __LINE__); - return slRet; - } - - if ((i > 0) && (i % 8192 == 0)) { /* After write 8192 bytes of data, sleep 1 ms. */ - msleep(1); - } - } - - if (ulRemain >= 0x4) { - slRet = SFC_RegWordAlignWrite(sflash, (const u32 *)(pucSrc + i), offset + i, ulRemain & (~0x3)); - if (slRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegWordAlignWrite fail\n", __func__, __LINE__); - return slRet; - } - i += ulRemain & (~0x3); - } - - for (; i < ulWriteLen; i++) { - slRet = SFC_RegByteWrite(sflash, *(const u8 *)(pucSrc + i), offset + i); - if (slRet != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegByteWrite fail\n", __func__, __LINE__); - return slRet; - } - } - - return HRD_OK; -} - -s32 SFC_RegModeWrite(struct SFC_SFLASH_INFO *sflash, - u32 offset, const u8 *pucSrc, u32 ulWriteLen) -{ - s32 slRet; - u32 ulPageRemain; - u32 offsetTmp = offset; - u8 *pucSrcTmp = (u8 *)pucSrc; - - if (!pucSrc) { - pr_err("[SFC] [%s %d]: Pointer is null\n", __func__, __LINE__); - return HRD_COMMON_ERR_NULL_POINTER; - } - - if (ulWriteLen > sflash->space_size) { - pr_err("[SFC] [%s %d]: ulReadLen is invalid\n", __func__, __LINE__); - return HRD_COMMON_ERR_INPUT_INVALID; - } - - SFC_CheckErr(sflash); - - /* the size of data remaining on the first page */ - ulPageRemain = SPI_FLASH_PAGE_SIZE - (offset % SPI_FLASH_PAGE_SIZE); - if (ulWriteLen >= ulPageRemain) { - slRet = _SFC_RegModeWrite(sflash, offsetTmp, pucSrcTmp, ulPageRemain); - if (slRet != HRD_OK) - return slRet; - - offsetTmp += ulPageRemain; - pucSrcTmp += ulPageRemain; - ulWriteLen -= ulPageRemain; - } - - if (ulWriteLen) { - slRet = _SFC_RegModeWrite(sflash, offsetTmp, pucSrcTmp, ulWriteLen); - if (slRet != HRD_OK) - return slRet; - } - - if (SFC_IsOpErr(sflash->sfc_reg_base)) - return HRD_ERR; - - return HRD_OK; -} - -s32 SFC_RegModeRead(struct SFC_SFLASH_INFO *sflash, - u32 offset, u8 *pucDest, u32 ulReadLen) -{ - u32 i; - u32 ulRemain; - u32 ulAlignLen; - s32 ret = HRD_OK; - - if (!sflash || !pucDest) { - pr_err("[SFC] [%s %d]: Pointer is null\n", __func__, __LINE__); - return HRD_COMMON_ERR_NULL_POINTER; - } - - if (ulReadLen > sflash->space_size) { - pr_err("[SFC] [%s %d]: ulReadLen is invalid\n", __func__, __LINE__); - return HRD_COMMON_ERR_INPUT_INVALID; - } - - SFC_CheckErr(sflash); - - ulRemain = ulReadLen % SFC_HARD_BUF_LEN; - ulAlignLen = ulReadLen - ulRemain; - - for (i = 0; i < ulAlignLen; i += SFC_HARD_BUF_LEN) { - ret = SFC_RegWordAlignRead(sflash, offset + i, (u32 *) (pucDest + i), SFC_HARD_BUF_LEN); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegWordAlignRead fail\n", __func__, __LINE__); - return ret; - } - } - - if (ulRemain >= 0x4) { - ret = SFC_RegWordAlignRead(sflash, offset + i, (u32 *) (pucDest + i), ulRemain & (~0x3)); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegWordAlignRead fail\n", __func__, __LINE__); - return ret; - } - i += ulRemain & (~0x3); - } - - for (; i < ulReadLen; i++) { - ret = SFC_RegByteRead(sflash, offset + i, pucDest + i); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_RegByteRead fail\n", __func__, __LINE__); - return ret; - } - } - - return ret; -} - -static s32 SFC_SPIFlashIdGet(struct SFC_SFLASH_INFO *pFlinfo, - u8 *pulManuId, u16 *pulDevId, u8 *pcfi_len, u8 *psec_arch, u8 *pfid) -{ - u8 ulID0; - u16 ulID1; - u16 ulID2; - s32 ulRet; - u32 ulRegValue; - u32 readid_cmd; - - if (!pulManuId || !pulDevId) { - pr_err("[SFC] [%s %d]: input params is invalid\n", __func__, __LINE__); - return HRD_COMMON_ERR_NULL_POINTER; - } - - (void)SFC_ClearInt(pFlinfo->sfc_reg_base); - - if (pFlinfo->index >= HI_ARRAY_SIZE(g_stSPIFlashDevTable)) - readid_cmd = SFLASH_DEFAULT_RDID_OPCD; - else - readid_cmd = g_stSPIFlashDevTable[pFlinfo->index].ucOpcodeRDID; - - SFC_RegisterWrite(pFlinfo->sfc_reg_base + CMD_INS, readid_cmd); - - ulRegValue = SFC_RegisterRead(pFlinfo->sfc_reg_base + CMD_CONFIG); - ulRegValue &= (~(0xff << DATA_CNT)) & (~(1 << RW_DATA)) - & (~(1 << SEL_CS)) & (~(1 << ADDR_EN)); - ulRegValue |= (0x5 << DATA_CNT) | (0x1 << RW_DATA) | (0x1 << DATA_EN) - | (SFC_CHIP_CS << SEL_CS) | (0x1 << START); - - wmb(); - SFC_RegisterWrite(pFlinfo->sfc_reg_base + CMD_CONFIG, ulRegValue); - ulRet = SFC_WaitInt(pFlinfo->sfc_reg_base); - if (ulRet != HRD_OK) { - pr_err("[SFC] [%s %d]: wait int failed\r\n", __func__, __LINE__); - return WAIT_TIME_OUT; - } - - ulRet = SFC_CheckCmdExcStatus(pFlinfo); - if (ulRet) { - pr_err("[SFC] [%s %d]: cmd execute timeout\r\n", __func__, __LINE__); - return WAIT_TIME_OUT; - } - - ulRegValue = SFC_RegisterRead(pFlinfo->sfc_reg_base + DATABUFFER1); - - ulID0 = ulRegValue & 0xff; - ulID1 = (ulRegValue >> 0x8) & 0xff; - ulID2 = (ulRegValue >> 0x10) & 0xff; - - *pulManuId = ulID0; - *pulDevId = (u16) (ulID1 << 0x8) | ulID2; - *pcfi_len = (ulRegValue >> 0x18) & 0xff; - - ulRegValue = SFC_RegisterRead(pFlinfo->sfc_reg_base + DATABUFFER2); - *psec_arch = ulRegValue & 0xff; - *pfid = (ulRegValue >> 0x8) & 0xff; - - pr_info("[SFC] [%s %d]:ulManuId=0x%x, ulDevId=0x%x cfi_len=0x%x, sec_arch=0x%x, fid=0x%x\n", - __func__, __LINE__, *pulManuId, *pulDevId, *pcfi_len, *psec_arch, *pfid); - - return HRD_OK; -} - -static int MirconWPSet(struct SFC_SFLASH_INFO *sflash, bool val) -{ - int ret; - - ret = SFC_WriteEnable(sflash); - if (ret != HRD_OK) { - pr_err("SFC_WriteEnable fail\n"); - return ret; - } - - if (val) - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, 0xDC); - else - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, 0x0); - - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_WRR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x81); - udelay((unsigned long)10); /* Delay 10 subtleties */ - - return ret; -} - -static int SpansionWPSet(struct SFC_SFLASH_INFO *sflash, bool val) -{ - int ret; - - ret = SFC_WriteEnable(sflash); - if (ret != HRD_OK) { - pr_err("SFC_WriteEnable fail\n"); - return ret; - } - - if (val) { - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, 0x9C); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_WRR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x81); - } else { - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_CLSR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x1); - udelay(50); /* Delay 50 subtleties */ - ret = SFC_CheckCmdExcStatus(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_CheckCmdExcStatus fail\n", __func__, __LINE__); - return ret; - } - - udelay(50); /* Delay 50 subtleties */ - ret = SFC_WaitFlashIdle(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitFlashIdle fail\n", __func__, __LINE__); - return ret; - } - - udelay(200); /* Delay 200 subtleties */ - ret = SFC_WriteEnable(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WriteEnable fail\n", __func__, __LINE__); - return ret; - } - - udelay(50); /* Delay 50 subtleties */ - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, 0); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_WRR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x81); - } - - return ret; -} - -static int MxicWPSet(struct SFC_SFLASH_INFO *sflash, bool val) -{ - u32 status; - int ret; - - ret = SFC_WriteEnable(sflash); - if (ret != HRD_OK) { - pr_err("SFC_WriteEnable fail\n"); - return ret; - } - - /* status register[7:0] : bit7[SRWD], bit6[QE], bit5~bit2[BP3 ~ BP0], bit1[WEL], bit0[WIP] */ - status = SFC_ReadStatus(sflash); - if (status == WAIT_TIME_OUT) { - ret = HRD_ERR; - pr_err("[SFC] [%s %d]: SFC_ReadStatus time out\n", __func__, __LINE__); - return ret; - } - - if (((status >> 1) & 0x1) != 1) { - ret = HRD_ERR; - pr_err("[SFC] [%s %d]: Write enable fail\n", __func__, __LINE__); - return ret; - } - - if (val) { - status |= 0x3c; - status &= (~(u32) 0x2); - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, status); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_WRR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x81); - } else { - status = status & (~(u32) 0x3c); - status = status & (~(u32) 0x2); - SFC_RegisterWrite(sflash->sfc_reg_base + DATABUFFER1, status); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_INS, SPI_CMD_WRR); - SFC_RegisterWrite(sflash->sfc_reg_base + CMD_CONFIG, 0x81); - } - - ret = SFC_WaitInt(sflash->sfc_reg_base); - if (ret != HRD_OK) - return ret; - - return ret; -} - -int SFC_WPSet(struct SFC_SFLASH_INFO *sflash, bool val) -{ - u32 device_id; - int ret; - - (void)SFC_ClearInt(sflash->sfc_reg_base); - - SFC_CheckErr(sflash); - - /* First try to read the Manufacturer and Device IDs */ - ret = SFC_GetDeviceId(sflash, &device_id); - if (ret != HRD_OK) { - pr_err("[SFC][%s %d]: Failed to get the device id\n", __func__, __LINE__); - return ret; - } - - sflash->manufacturerId = device_id; - ret = SFC_WaitFlashIdle(sflash); - if (ret != HRD_OK) { - pr_err("[SFC][%s %d]: SFC_WaitFlashIdle fail\n", __func__, __LINE__); - return ret; - } - - /* WP will lock sfc */ - if (HISI_M25PXXX_ST_MANF_ID == (u8) (device_id)) { - ret = MirconWPSet(sflash, val); - } else if (HISI_SPANSION_MANF_ID == (u8) (device_id)) { - ret = SpansionWPSet(sflash, val); - } else if (HISI_MX25U12835F_MANF_ID == (u8) (device_id)) { - ret = MxicWPSet(sflash, val); - /* default */ - } else { - ret = MxicWPSet(sflash, val); - } - - if (ret != HRD_OK) - goto done; - - udelay(10); /* delay 10 us */ - - ret = SFC_CheckCmdExcStatus(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_CheckCmdExcStatus fail\n", __func__, __LINE__); - goto done; - } - - ret = SFC_WaitFlashIdle(sflash); - if (ret != HRD_OK) { - pr_err("[SFC] [%s %d]: SFC_WaitFlashIdle fail\n", __func__, __LINE__); - goto done; - } - -done: - SFC_FlashUnlock(sflash); - return ret; -} - -#define CMP_MANF_ID(indx, id) \ - ((g_stSPIFlashDevTable[indx].ulManufacturerId != 0xff) ? (g_stSPIFlashDevTable[indx].ulManufacturerId == (id)) : 1) - -#define CMP_DEVICE_ID(indx, id) \ - ((g_stSPIFlashDevTable[indx].ulDeviceId != 0xffff) ? (g_stSPIFlashDevTable[indx].ulDeviceId == (id)) : 1) - -#define CMP_EXTERN_ID(indx, cfi_len, sec_arch, fid) \ - (((g_stSPIFlashDevTable[indx].ulIdCFILen != 0xff) ? (g_stSPIFlashDevTable[indx].ulIdCFILen == (cfi_len)) : 1) && \ - ((g_stSPIFlashDevTable[indx].ulPhySecArch != 0xff) ? (g_stSPIFlashDevTable[indx].ulPhySecArch == (sec_arch)) : 1) && \ - ((g_stSPIFlashDevTable[indx].ulFId != 0xff) ? (g_stSPIFlashDevTable[indx].ulFId == (fid)) : 1)) - -static bool SFC_IsFlashIdErr(u8 manf, u16 dev) -{ - if (((manf == 0xFF) && (dev == 0xFFFF)) - || ((manf == 0x0) && (dev == 0x0))) { - return true; - } - - return false; -} - -int hrd_sflash_init(struct SFC_SFLASH_INFO *pFlinfo) -{ - int ret; - u8 manf; - u16 dev; - u8 cfi_len; - u8 sec_arch; - u8 fid; - u32 indx; - bool detectFlag = false; - - /* check for NULL pointer */ - if (pFlinfo == NULL) { - pr_err("[SFC] %s HRD_ERR: Null pointer parameter!\n", __func__); - return HRD_COMMON_ERR_INPUT_INVALID; - } - - /* First try to read the Manufacturer and Device IDs */ - ret = SFC_SPIFlashIdGet(pFlinfo, &manf, &dev, &cfi_len, &sec_arch, &fid); - if (ret != HRD_OK) { - pr_err("[SFC] %s HRD_ERR: Failed to get the SFlash ID!\n", __func__); - return ret; - } - - if (SFC_IsFlashIdErr(manf, dev)) { - pr_err("flash id err, manf=0x%x,dev=0x%x\n", manf, dev); - return HRD_ERR; - } - - /* loop over the whole table and look for the appropriate SFLASH */ - for (indx = 0; indx < HI_ARRAY_SIZE(g_stSPIFlashDevTable); indx++) { - if ((CMP_MANF_ID(indx, manf)) - && (CMP_DEVICE_ID(indx, dev)) - && (CMP_EXTERN_ID(indx, cfi_len, sec_arch, fid))) { - pFlinfo->manufacturerId = manf; - pFlinfo->deviceId = dev; - pFlinfo->index = indx; - pFlinfo->addr_mode = g_stSPIFlashDevTable[indx].ulAddrModeSuport; - pFlinfo->sfc_type_flag = g_stSPIFlashDevTable[indx].ulIfTypeSuport; - detectFlag = true; - break; - } - } - - if (!detectFlag) { - pr_err("[SFC] %s HRD_ERR: manf:0x%x, dev:0x%x, Unknown SPI flash device!\n", __func__, manf, dev); - return HRD_ERR; - } - - /* fill the info based on the model detected */ - pFlinfo->sectorSize = g_stSPIFlashDevTable[pFlinfo->index].ulBlockSize; - pFlinfo->sectorNumber = g_stSPIFlashDevTable[pFlinfo->index].ulBlockNumber; - pFlinfo->pageSize = g_stSPIFlashDevTable[pFlinfo->index].ulSectorSize; - pFlinfo->space_size = pFlinfo->sectorSize * pFlinfo->sectorNumber; - memcpy(&pFlinfo->sflash_dev_params, - &g_stSPIFlashDevTable[pFlinfo->index], - sizeof(struct SPI_FLASH_DEVICE_PARAMS)); - - return ret; -} diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.h b/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.h deleted file mode 100644 index f612731d06cd4..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_hal.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HRD_SFLASH_HAL_H__ -#define __HRD_SFLASH_HAL_H__ -#include "hrd_sflash_driver.h" - -extern void SFC_CheckErr(struct SFC_SFLASH_INFO *sflash); -extern s32 SFC_RegModeRead(struct SFC_SFLASH_INFO *sflash, u32 offset, - u8 *pucDest, u32 ulReadLen); -extern s32 SFC_RegModeWrite(struct SFC_SFLASH_INFO *sflash, u32 offset, - const u8 *pucSrc, u32 ulWriteLen); -extern s32 SFC_BlockErase(struct SFC_SFLASH_INFO *sflash, u32 ulAddr, - u32 ErCmd); -extern int hrd_sflash_init(struct SFC_SFLASH_INFO *pFlinfo); -extern int SFC_WPSet(struct SFC_SFLASH_INFO *sflash, bool val); - -#endif diff --git a/drivers/mtd/hisilicon/sfc/hrd_sflash_spec.h b/drivers/mtd/hisilicon/sfc/hrd_sflash_spec.h deleted file mode 100644 index 151957d62d351..0000000000000 --- a/drivers/mtd/hisilicon/sfc/hrd_sflash_spec.h +++ /dev/null @@ -1,376 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Hisilicon Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __HRD_SFLASH_SPEC_H__ -#define __HRD_SFLASH_SPEC_H__ - -#define SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ -#define SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ - -/* Constants */ -#define HISI_SFLASH_READ_CMND_LENGTH 4 /* 1B opcode + 3B address */ -#define HISI_SFLASH_SE_CMND_LENGTH 4 /* 1B opcode + 3B address */ -#define HISI_SFLASH_BE_CMND_LENGTH 1 /* 1B opcode */ -#define HISI_SFLASH_PP_CMND_LENGTH 4 /* 1B opcode + 3B address */ -#define HISI_SFLASH_WREN_CMND_LENGTH 1 /* 1B opcode */ -#define HISI_SFLASH_WRDI_CMND_LENGTH 1 /* 1B opcode */ -#define HISI_SFLASH_RDID_CMND_LENGTH 1 /* 1B opcode */ -/* 1B manf ID and 2B device ID */ -#define HISI_SFLASH_RDID_REPLY_LENGTH 3 -#define HISI_SFLASH_RDSR_CMND_LENGTH 1 /* 1B opcode */ -#define HISI_SFLASH_RDSR_REPLY_LENGTH 1 /* 1B status */ -/* 1B opcode + 1B status value */ -#define HISI_SFLASH_WRSR_CMND_LENGTH 2 -#define HISI_SFLASH_DP_CMND_LENGTH 1 /* 1B opcode */ -#define HISI_SFLASH_RES_CMND_LENGTH 1 /* 1B opcode */ - -/* Status Register Bit Masks */ -/* bit 0; write in progress */ -#define HISI_SFLASH_STATUS_REG_WIP_OFFSET 0 -/* bit 2-4; write protect option */ -#define HISI_SFLASH_STATUS_REG_WP_OFFSET 2 -/* bit 7; lock status register write */ -#define HISI_SFLASH_STATUS_REG_SRWD_OFFSET 7 -#define HISI_SFLASH_STATUS_REG_WIP_MASK \ - (0x1 << HISI_SFLASH_STATUS_REG_WIP_OFFSET) -#define HISI_SFLASH_STATUS_REG_SRWD_MASK \ - (0x1 << HISI_SFLASH_STATUS_REG_SRWD_OFFSET) - -#define HISI_SFLASH_MAX_WAIT_LOOP 1000000 -#define HISI_SFLASH_CHIP_ERASE_MAX_WAIT_LOOP 0x50000000 - -#define HISI_SFLASH_DEFAULT_RDID_OPCD 0x9F /* Default Read ID */ -#define HISI_SFLASH_DEFAULT_WREN_OPCD 0x06 /* Default Write Enable */ -#define HISI_SFLASH_NO_SPECIFIC_OPCD 0x00 -#define HISI_SFLASH_UNKOWN_OPCD 0xFF - -/********************************/ -/* ST M25Pxxx Device Specific */ -/********************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_M25PXXX_ST_MANF_ID 0x20 -#define HISI_M25P80_DEVICE_ID 0x2014 -#define HISI_M25P80_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_M25P80_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_M25P80_FAST_READ_DUMMY_BYTES 1 -#define HISI_M25P32_DEVICE_ID 0x2016 -#define HISI_M25P32_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_M25P32_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_M25P32_FAST_READ_DUMMY_BYTES 1 -#define HISI_M25P64_DEVICE_ID 0x2017 -#define HISI_M25P64_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_M25P64_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_M25P64_FAST_READ_DUMMY_BYTES 1 -#define HISI_M25P128_DEVICE_ID 0x2018 -#define HISI_M25P128_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_M25P128_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_M25P128_FAST_READ_DUMMY_BYTES 1 - -/* Sector Sizes and population per device model */ -#define HISI_M25P80_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_M25P32_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_M25P64_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_M25P128_SECTOR_SIZE 0x40000 /* 256K */ -#define HISI_M25P80_SECTOR_NUMBER 16 -#define HISI_M25P32_SECTOR_NUMBER 64 -#define HISI_M25P64_SECTOR_NUMBER 128 -#define HISI_M25P128_SECTOR_NUMBER 64 -#define HISI_M25P_PAGE_SIZE 0x100 /* 256 byte */ - -#define HISI_M25P_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_M25P_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_M25P_RDID_CMND_OPCD 0x9F /* Read ID */ -/* Read Status Register */ -#define HISI_M25P_RDSR_CMND_OPCD 0x05 -/* Write Status Register */ -#define HISI_M25P_WRSR_CMND_OPCD 0x01 -#define HISI_M25P_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_M25P_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_M25P_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_M25P_SSE_CMND_OPCD 0x20 /* SubSectorErase */ -#define HISI_M25P_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_M25P_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -/* Read Electronic Signature */ -#define HISI_M25P_RES_CMND_OPCD 0xAB - -/* Status Register Write Protect Bit Masks - 3bits */ -#define HISI_M25P_STATUS_REG_WP_MASK (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_NONE (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_64 (0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_32 (0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_16 (0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_8 (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_4 (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_1_OF_2 (0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_M25P_STATUS_BP_ALL (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -/************************************/ -/* MXIC MX25L6405 Device Specific */ -/************************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_MXIC_MANF_ID 0xC2 -#define HISI_MX25L6405_DEVICE_ID 0x2017 -#define HISI_MX25L6405_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_MX25L6405_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_MX25L6405_FAST_READ_DUMMY_BYTES 1 -#define HISI_MXIC_DP_EXIT_DELAY 30 /* 30 ms */ - -/* Sector Sizes and population per device model */ -#define HISI_MX25L6405_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_MX25L6405_SECTOR_NUMBER 128 -#define HISI_MXIC_PAGE_SIZE 0x100 /* 256 byte */ - -#define HISI_MX25L_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_MX25L_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_MX25L_RDID_CMND_OPCD 0x9F /* Read ID */ -/* Read Status Register */ -#define HISI_MX25L_RDSR_CMND_OPCD 0x05 -/* Write Status Register */ -#define HISI_MX25L_WRSR_CMND_OPCD 0x01 -#define HISI_MX25L_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_MX25L_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_MX25L_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_MX25L_SSE_CMND_OPCD 0x20 /* SubSector Erase */ -#define HISI_MX25L_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_MX25L_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -#define HISI_MX25L_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -/* Read Electronic Signature */ -#define HISI_MX25L_RES_CMND_OPCD 0xAB - -/* Status Register Write Protect Bit Masks - 4bits */ -#define HISI_MX25L_STATUS_REG_WP_MASK (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_NONE (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_128 (0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_64 (0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_32 (0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_16 (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_8 (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_4 (0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_1_OF_2 (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25L_STATUS_BP_ALL (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -/************************************/ -/* MXIC MX25LU12835F Device Specific */ -/************************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_MX25U12835F_MANF_ID 0xC2 -#define HISI_MX25U12835F_DEVICE_ID 0x2538 -#define HISI_MX25U12835F_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_MX25U12835F_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_MX25U12835F_FAST_READ_DUMMY_BYTES 1 -#define HISI_MX25U12835F_DP_EXIT_DELAY 30 /* 30 ms */ - -/* Sector Sizes and population per device model */ -#define HISI_MX25U12835F_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_MX25U12835F_SECTOR_NUMBER 256 -#define HISI_MX25U12835F_PAGE_SIZE 0x1000 /* 4KB */ - -#define HISI_MX25U12835F_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_MX25U12835F_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_MX25U12835F_RDID_CMND_OPCD 0x9F /* Read ID */ -/* Read Status Register */ -#define HISI_MX25U12835F_RDSR_CMND_OPCD 0x05 -/* Write Status Register */ -#define HISI_MX25U12835F_WRSR_CMND_OPCD 0x01 -#define HISI_MX25U12835F_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_MX25U12835F_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_MX25U12835F_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_MX25U12835F_SSE_CMND_OPCD 0x20 /* SubSector Erase */ -#define HISI_MX25U12835F_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_MX25U12835F_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -#define HISI_MX25U12835F_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -/* Read Electronic Signature */ -#define HISI_MX25U12835F_RES_CMND_OPCD 0xAB - -/* Status Register Write Protect Bit Masks - 4bits */ -#define HISI_MX25U12835F_STATUS_REG_WP_MASK (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_NONE (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_128 (0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_64 (0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_32 (0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_16 (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_8 (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_4 (0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_1_OF_2 (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_MX25U12835F_STATUS_BP_ALL (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -/************************************/ -/* MXIC MX25L1606E Device Specific */ -/************************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_MX25L1606E_DEVICE_ID 0x2015 -#define HISI_MX25L1606E_MAX_SPI_FREQ 33000000 /* 33MHz */ -#define HISI_MX25L1606E_MAX_FAST_SPI_FREQ 86000000 /* 86MHz */ -#define HISI_MX25L1606E_FAST_READ_DUMMY_BYTES 1 - -#define HISI_MX25L1606E_PAGE_SIZE 0x1000 /* 4K */ -#define HISI_MX25L1606E_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_MX25L1606E_SECTOR_NUMBER 32 - -/************************************/ -/* SPANSION S25Fx128 Device Specific */ -/************************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_SPANSION_MANF_ID 0x01 -#define HISI_S25FL128_DEVICE_ID 0x2018 -#define HISI_S25FL128_MAX_SPI_FREQ 33000000 /* 33MHz */ -#define HISI_S25FL128_MAX_FAST_SPI_FREQ 104000000 /* 104MHz */ -#define HISI_S25FL128_FAST_READ_DUMMY_BYTES 1 - -/* Sector Sizes and population per device model */ -#define HISI_S25FL128_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_S25FL128_SECTOR_NUMBER 256 -#define HISI_S25FL_PAGE_SIZE 0x100 /* 256 byte */ - -#define HISI_S25FL_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_S25FL_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_S25FL_RDID_CMND_OPCD 0x9F /* Read ID */ -/* Read Status Register */ -#define HISI_S25FL_RDSR_CMND_OPCD 0x05 -/* Write Status Register */ -#define HISI_S25FL_WRSR_CMND_OPCD 0x01 -#define HISI_S25FL_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_S25FL_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_S25FL_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_S25FL_SSE_CMND_OPCD 0x20 /* SubSector Erase */ -#define HISI_S25FL_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_S25FL_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -#define HISI_S25FL_DP_CMND_OPCD 0xB9 /* Deep Power Down */ -/* Read Electronic Signature */ -#define HISI_S25FL_RES_CMND_OPCD 0xAB - -/* Status Register Write Protect Bit Masks - 4bits */ -#define HISI_S25FL_STATUS_REG_WP_MASK \ - (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_NONE \ - (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_128 \ - (0x01 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_64 \ - (0x02 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_32 \ - (0x03 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_16 \ - (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_8 \ - (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_4 \ - (0x06 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_1_OF_2 \ - (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_S25FL_STATUS_BP_ALL \ - (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -/********************************/ -/* ATMEL ATxx Device Specific */ -/********************************/ -/* Manufacturer IDs and Device IDs for SFLASHs supported by the driver */ -#define HISI_AT25DFXXX_AT_MANF_ID 0x1F -#define HISI_AT25DF641_DEVICE_ID 0x4800 -#define HISI_AT25DF641_MAX_SPI_FREQ 20000000 /* 20MHz */ -#define HISI_AT25DF641_MAX_FAST_SPI_FREQ 50000000 /* 50MHz */ -#define HISI_AT25DF641_FAST_READ_DUMMY_BYTES 1 - -/* Sector Sizes and population per device model */ -#define HISI_AT25DF641_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_AT25DF641_SECTOR_NUMBER 128 -#define HISI_AT25DF_PAGE_SIZE 0x100 /* 256 byte */ - -#define HISI_AT25DF_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_AT25DF_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_AT25DF_RDID_CMND_OPCD 0x9F /* Read ID */ -#define HISI_AT25DF_RDSR_CMND_OPCD 0x05 /* Read Status Register */ -#define HISI_AT25DF_WRSR_CMND_OPCD 0x01 /* Write Status Register */ -#define HISI_AT25DF_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_AT25DF_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_AT25DF_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_AT25DF_SSE_CMND_OPCD 0x20 /* SubSector Erase */ -#define HISI_AT25DF_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_AT25DF_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -#define HISI_AT25DF_RES_CMND_OPCD 0xAB /* Read Electronic Signature */ - -/* Status Register Write Protect Bit Masks - 4bits */ -#define HISI_AT25DF_STATUS_REG_WP_MASK \ - (0x0F << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_AT25DF_STATUS_BP_NONE \ - (0x00 << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -#define HISI_AT25DF_STATUS_BP_WP_NONE (0x04 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_AT25DF_STATUS_BP_SOME (0x05 << HISI_SFLASH_STATUS_REG_WP_OFFSET) -#define HISI_AT25DF_STATUS_BP_ALL (0x07 << HISI_SFLASH_STATUS_REG_WP_OFFSET) - -/********************************/ -/* NUMONYX N25Q Device Specific */ -/********************************/ -#define HISI_N25Q_WREN_CMND_OPCD 0x06 /* Write Enable */ -#define HISI_N25Q_WRDI_CMND_OPCD 0x04 /* Write Disable */ -#define HISI_N25Q_RDID_CMND_OPCD 0x9F /* Read ID */ -/* Read Status Register */ -#define HISI_N25Q_RDSR_CMND_OPCD 0x05 -/* Write Status Register */ -#define HISI_N25Q_WRSR_CMND_OPCD 0x01 -#define HISI_N25Q_READ_CMND_OPCD 0x03 /* Sequential Read */ -#define HISI_N25Q_FAST_RD_CMND_OPCD 0x0B /* Fast Read */ -#define HISI_N25Q_PP_CMND_OPCD 0x02 /* Page Program */ -#define HISI_N25Q_SSE_CMND_OPCD 0x20 /* SubSectorErase */ -#define HISI_N25Q_SE_CMND_OPCD 0xD8 /* Sector Erase */ -#define HISI_N25Q_BE_CMND_OPCD 0xC7 /* Bulk Erase */ -/* Read Volatile Enhanced Configuration Register */ -#define HISI_N25Q_RDVECR_CMND_OPCD 0x65 -/* Write Volatile Enhanced Configuration Register */ -#define HISI_N25Q_WRVECR_CMND_OPCD 0x61 -/* Enter 4-byte address mode */ -#define HISI_N25Q_EN4BADDR_CMND_OPCD 0xB7 -/* Exit 4-byte address mode */ -#define HISI_N25Q_EX4BADDR_CMND_OPCD 0xE9 -/* STATUS REGISTER BUSY BIT */ -#define HISI_N25Q_BUSY_FLAG_BIT 0xC7 - -#define HISI_N25Q256_MANF_ID 0x20 -#define HISI_N25Q256_DEVICE_ID 0xBA19 -#define HISI_N25Q256_MAX_SPI_FREQ 108000000 /* 108MHz */ -#define HISI_N25Q256_MAX_FAST_SPI_FREQ 432000000 /* 432MHz */ -#define HISI_N25Q256_FAST_READ_DUMMY_BYTES 8 - -#define HISI_N25Q256_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_N25Q256_SECTOR_NUMBER 512 -#define HISI_N25Q256_PAGE_SIZE 0x1000 /* 4K */ - -/* support 3byte and 4byte addr */ -#define HISI_N25Q256_3B_4B_SUPPORT 0x3 -/* support ESPI, FULL DIO, FULL QIO mode */ -#define HISI_N25Q256_IF_TYPE_SUPPORT 0x89 - -#define HISI_N25Q128_MANF_ID 0x20 -#define HISI_N25Q128_DEVICE_ID 0xBA18 -#define HISI_N25Q128_MAX_SPI_FREQ 108000000 /* 108MHz */ -#define HISI_N25Q128_MAX_FAST_SPI_FREQ 432000000 /* 432MHz */ -#define HISI_N25Q128_FAST_READ_DUMMY_BYTES 8 - -#define HISI_N25Q128_SECTOR_SIZE 0x10000 /* 64K */ -#define HISI_N25Q128_SECTOR_NUMBER 256 -#define HISI_N25Q128_PAGE_SIZE 0x1000 /* 4K */ - -/* NUMONYX N25Q128B SPI flash */ -#define HISI_N25Q128B_MANF_ID 0x20 -#define HISI_N25Q128B_DEVICE_ID 0xBB18 - -/* support 3byte and 4byte addr */ -#define HISI_N25Q128_3B_4B_SUPPORT 0x3 -/* support ESPI, FULL DIO, FULL QIO mode */ -#define HISI_N25Q128_IF_TYPE_SUPPORT 0x89 - -#endif -- 2.25.1
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