tree: https://gitee.com/openeuler/kernel.git OLK-6.6 head: 4eddc7e6b3a11653b493da4617c18cdc2e6e6777 commit: 6460d9d3c42d1357c8292d7be5c26cb7b84e84d7 [2853/2853] yt6801: Add Motorcomm yt6801 PCIe driver config: loongarch-randconfig-001-20250905 (https://download.01.org/0day-ci/archive/20250905/202509050145.rJ98GKyh-lkp@i...) compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250905/202509050145.rJ98GKyh-lkp@i...) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202509050145.rJ98GKyh-lkp@intel.com/ All errors (new ones prefixed by >>):

...

drivers/net/ethernet/motorcomm/yt6801/yt6801_main.c:751:23: error: use of undeclared identifier 'IEEE_8021QAZ_MAX_TCS' 751 | min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, priv->rx_q_count); | ^ drivers/net/ethernet/motorcomm/yt6801/yt6801_main.c:752:8: error: use of undeclared identifier 'IEEE_8021QAZ_MAX_TCS' 752 | ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; | ^ drivers/net/ethernet/motorcomm/yt6801/yt6801_main.c:753:14: error: use of undeclared identifier 'IEEE_8021QAZ_MAX_TCS' 753 | ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; | ^ drivers/net/ethernet/motorcomm/yt6801/yt6801_main.c:1715:35: warning: variable 'mac_hfr2' set but not used [-Wunused-but-set-variable] 1715 | unsigned int mac_hfr0, mac_hfr1, mac_hfr2, mac_hfr3; | ^ 1 warning and 3 errors generated.

vim +/IEEE_8021QAZ_MAX_TCS +751 drivers/net/ethernet/motorcomm/yt6801/yt6801_main.c 742 743 static void fxgmac_config_queue_mapping(struct fxgmac_pdata *priv) 744 { 745 unsigned int ppq, ppq_extra, prio_queues; 746 unsigned int __maybe_unused prio; 747 unsigned int reg, val, mask; 748 749 /* Map the 8 VLAN priority values to available MTL Rx queues */ 750 prio_queues =

751 min_t(unsigned int, IEEE_8021QAZ_MAX_TCS, priv->rx_q_count); 752 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues; 753 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues; 754 755 reg = MAC_RQC2R; 756 for (u32 i = 0, prio = 0; i < prio_queues;) { 757 val = 0; 758 mask = 0; 759 for (u32 j = 0; j < ppq; j++) { 760 mask |= (1 << prio); 761 prio++; 762 } 763 764 if (i < ppq_extra) { 765 mask |= (1 << prio); 766 prio++; 767 } 768 769 val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); 770 771 if ((i % MAC_RQC2_Q_PER_REG) && i != prio_queues) 772 continue; 773 774 fxgmac_io_wr(priv, reg, val); 775 reg += MAC_RQC2_INC; 776 } 777 778 /* Configure one to one, MTL Rx queue to DMA Rx channel mapping 779 * ie Q0 <--> CH0, Q1 <--> CH1 ... Q7 <--> CH7 780 */ 781 val = fxgmac_io_rd(priv, MTL_RQDCM0R); 782 val |= (MTL_RQDCM0R_Q0MDMACH | MTL_RQDCM0R_Q1MDMACH | 783 MTL_RQDCM0R_Q2MDMACH | MTL_RQDCM0R_Q3MDMACH); 784 fxgmac_io_wr(priv, MTL_RQDCM0R, val); 785 786 val = fxgmac_io_rd(priv, MTL_RQDCM0R + MTL_RQDCM_INC); 787 val |= (MTL_RQDCM1R_Q4MDMACH | MTL_RQDCM1R_Q5MDMACH | 788 MTL_RQDCM1R_Q6MDMACH | MTL_RQDCM1R_Q7MDMACH); 789 fxgmac_io_wr(priv, MTL_RQDCM0R + MTL_RQDCM_INC, val); 790 } 791

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