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[PATCH v2 for-next 0/5] RDMA/hns: Fix and refactor CMDQ related code
by Weihang Li 10 Feb '21

10 Feb '21

Remove some dead code in process of CMDQ transmission, and fix an issue about missing error code. Changes since v1: * Drop #2 from the v1 series because the compatibility with the firmware needs to be considered. * Link: https://patchwork.kernel.org/project/linux-rdma/cover/1612419786-39173-1-gi… Lang Cheng (5): RDMA/hns: Remove unused member and variable of CMDQ RDMA/hns: Fixes missing error code of CMDQ RDMA/hns: Remove redundant operations on CMDQ RDMA/hns: Adjust fields and variables about CMDQ tail/head RDMA/hns: Refactor process of posting CMDQ drivers/infiniband/hw/hns/hns_roce_common.h | 4 +- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 125 ++++++++-------------------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 5 -- 3 files changed, 37 insertions(+), 97 deletions(-) -- 2.8.1

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[RFC PATCH 0/2] sched/topology: Get rid of overlapping groups
by Valentin Schneider 09 Feb '21

09 Feb '21

Hi folks, My keyboard still hasn't been taken away from me, so I went down and did what I was rambling about in [1]. The preemptive degeneration check is the worst wart, but I think I'll have to sleep on it before I can figure out a better way. Something tells me the increase in group numbers isn't going to make me any friends, so I've included 3/2 which is Barry's approach (with the subset check condensed in a single spot). Cheers, Valentin [1]: http://lore.kernel.org/r/jhj4kiu4hz8.mognet@arm.com Valentin Schneider (2): sched/topology: Get rid of NUMA overlapping groups Revert "sched/topology: Warn when NUMA diameter > 2" kernel/sched/topology.c | 77 +++++++++++++++++++++++------------------ 1 file changed, 43 insertions(+), 34 deletions(-) -- 2.27.0

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[PATCH for-next 00/12] RDMA/hns: Updates for 5.12
by Weihang Li 09 Feb '21

09 Feb '21

As usual, this series collects some miscellaneous fixes and cleanups at the end of 5.12 for the hns driver: * #1 ~ #3 fix some non-urgent issues. * #4 ~ #6 make some changes on existing features. * #7 ~ #12 are cleanups, just do some refactor and delete dead code. This series is made based on the series named "RDMA/hns: Several fixes and cleanups of RQ/SRQ" which is still being reviewed: https://patchwork.kernel.org/project/linux-rdma/cover/1611997090-48820-1-gi… I'm worried that it will be too late for 5.12 if any patch of this series needs changes, so I send it before the previous one is merged. If there is any comment or merge conflict on it, I will fix them as soon as possible, thanks. Lang Cheng (3): RDMA/hns: Replace wmb&__raw_writeq with writeq RDMA/hns: Move HIP06 related definitions into hns_roce_hw_v1.h RDMA/hns: Avoid unnecessary memset on WQEs in post_send Lijun Ou (1): RDMA/hns: Disable RQ inline by default Weihang Li (2): RDMA/hns: Avoid filling sgid index when modifying QP to RTR RDMA/hns: Fix type of sq_signal_bits Xi Wang (1): RDMA/hns: Add mapped page count checking for MTR Xinhao Liu (2): RDMA/hns: Remove some magic numbers RDMA/hns: Delete redundant judgment when preparing descriptors Yixian Liu (1): RDMA/hns: Remove unnecessary wrap around for EQ's consumer index Yixing Liu (2): RDMA/hns: Adjust definition of FRMR fields RDMA/hns: Skip qp_flow_control_init() for HIP09 drivers/infiniband/hw/hns/hns_roce_device.h | 45 +--------- drivers/infiniband/hw/hns/hns_roce_hem.c | 9 +- drivers/infiniband/hw/hns/hns_roce_hw_v1.c | 31 +++---- drivers/infiniband/hw/hns/hns_roce_hw_v1.h | 43 ++++++++++ drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 125 +++++++++------------------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 12 +-- drivers/infiniband/hw/hns/hns_roce_main.c | 16 ---- drivers/infiniband/hw/hns/hns_roce_mr.c | 56 ++++++++----- 8 files changed, 148 insertions(+), 189 deletions(-) -- 2.8.1

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[PATCH v1 0/2] irqchip/gic-v3-its: don't set bitmap for LPI which user didn't allocate
by Luo Jiaxing 09 Feb '21

09 Feb '21

When the number of online CPUs is less than 16, we found that it will fail to allocate 32 MSI interrupts (including 16 affinity interrupts) after the hisi_sas module is unloaded and then reloaded. After analysis, it is found that a bug exists when the ITS releases interrupt resources, and this patch set contains a bugfix patch and a patch for appending debugging information. Luo Jiaxing (2): irqchip/gic-v3-its: don't set bitmap for LPI which user didn't allocate genirq/msi: add an error print when __irq_domain_alloc_irqs() failed drivers/irqchip/irq-gic-v3-its.c | 4 ++++ kernel/irq/msi.c | 1 + 2 files changed, 5 insertions(+) -- 2.7.4

4 5

[PATCH net-next 00/12] net: hns3: some cleanups for -next
by Huazhong Tan 09 Feb '21

09 Feb '21

There are some cleanups for the HNS3 ethernet driver. Huazhong Tan (2): net: hns3: remove redundant return value of hns3_uninit_all_ring() net: hns3: remove an unused parameter in hclge_vf_rate_param_check() Jian Shen (2): net: hns3: remove redundant client_setup_tc handle net: hns3: cleanup for endian issue for VF RSS Jiaran Zhang (1): net: hns3: modify some unmacthed types print parameter Peng Li (4): net: hns3: remove the shaper param magic number net: hns3: change hclge_parse_speed() param type net: hns3: change hclge_query_bd_num() param type net: hns3: remove unused macro definition Yonglong Liu (1): net: hns3: clean up some incorrect variable types in hclge_dbg_dump_tm_map() Yufeng Mo (2): net: hns3: check cmdq message parameters sent from VF net: hns3: clean up unnecessary parentheses in macro definitions drivers/net/ethernet/hisilicon/hns3/hnae3.h | 7 +++-- drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 2 +- drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 31 ++++------------------ drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 11 ++++---- drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 2 +- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 4 +-- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c | 27 ------------------- .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 11 ++++---- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c | 4 +-- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 21 ++++++++++----- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 5 +--- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c | 31 ++++++++++++++++++---- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 14 +++++----- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h | 6 ++--- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h | 11 ++++---- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 19 ++++++++----- 16 files changed, 93 insertions(+), 113 deletions(-) -- 2.7.4

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[dpdk-dev] [Question about 'rte_eth_tx_prepare']
by Chengchang Tang 09 Feb '21

09 Feb '21

Hi, Thomas Monjalon and Ferruh Yigit and others. I have some questions about 'rte_eth_tx_prepare'. When I use TSO offload in bond mode, the checksum error occurs. It is because the bond PMD does not implement 'tx_prepare'. So, it will not invoke the 'tx_prepare' of each PMDs to do prepare for the PMDs. I am not sure whether to add the 'tx_preapre' implementation for the bond PMD or put the process of pseudo header in the apps. And we are now designing the outer UDP cksum offload for HNS3 PMD. I find that many PMDs process these pseudo headers in 'tx_prepare', but does not process the pseudo header for outer UDP checksum offload. Instead, it is processed in csum forward mode of testpmd. Does this mean that the pseudo header should be completed by the apps and the apps does not need to call 'tx_prepare' to avoid repeated processing? (it seems not transplantable) If so, it seems that PMDs need to avoid doing this in 'tx_prepare'. Here are two questions: 1. What functions should be included in the 'tx_prepare' for PMDs? 2. Whether an app must invoke 'rte_eth_tx_prepare' or under which conditions an app must invoke the 'rte_eth_tx_prepare'? Thanks Chengchang Tang

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[PATCH v2 for-next] RDMA/hns: Add support of direct wqe
by Weihang Li 09 Feb '21

09 Feb '21

From: Yixing Liu <liuyixing1(a)huawei.com> Direct wqe is a mechanism to fill wqe directly into the hardware. In the case of light load, the wqe will be filled into pcie bar space of the hardware, this will reduce one memory access operation and therefore reduce the latency. Signed-off-by: Yixing Liu <liuyixing1(a)huawei.com> Signed-off-by: Lang Cheng <chenglang(a)huawei.com> Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- Changes since v1: * Delete an extra blank line. * Link: https://patchwork.kernel.org/project/linux-rdma/patch/1611395717-11081-1-gi… drivers/infiniband/hw/hns/hns_roce_device.h | 6 ++++ drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 44 ++++++++++++++++++++++++++++- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 13 +++++++++ 3 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index f62851f..907bf71 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -90,6 +90,7 @@ #define HNS_ROCE_MAX_PORTS 6 #define HNS_ROCE_GID_SIZE 16 #define HNS_ROCE_SGE_SIZE 16 +#define HNS_ROCE_DWQE_SIZE 65536 #define HNS_ROCE_HOP_NUM_0 0xff @@ -643,6 +644,10 @@ struct hns_roce_work { u32 queue_num; }; +enum { + HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5), +}; + struct hns_roce_qp { struct ib_qp ibqp; struct hns_roce_wq rq; @@ -984,6 +989,7 @@ struct hns_roce_dev { struct mutex pgdir_mutex; int irq[HNS_ROCE_MAX_IRQ_NUM]; u8 __iomem *reg_base; + void __iomem *mem_base; struct hns_roce_caps caps; struct xarray qp_table_xa; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c index a5bbfb1..8ae3317 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c @@ -503,6 +503,8 @@ static inline int set_ud_wqe(struct hns_roce_qp *qp, if (ret) return ret; + qp->sl = to_hr_ah(ud_wr(wr)->ah)->av.sl; + set_extend_sge(qp, wr->sg_list, &curr_idx, valid_num_sge); /* @@ -635,6 +637,8 @@ static inline void update_sq_db(struct hns_roce_dev *hr_dev, V2_DB_BYTE_4_TAG_S, qp->doorbell_qpn); roce_set_field(sq_db.byte_4, V2_DB_BYTE_4_CMD_M, V2_DB_BYTE_4_CMD_S, HNS_ROCE_V2_SQ_DB); + /* indicates data on new BAR, 0 : SQ doorbell, 1 : DWQE */ + roce_set_bit(sq_db.byte_4, V2_DB_FLAG_S, 0); roce_set_field(sq_db.parameter, V2_DB_PARAMETER_IDX_M, V2_DB_PARAMETER_IDX_S, qp->sq.head); roce_set_field(sq_db.parameter, V2_DB_PARAMETER_SL_M, @@ -644,6 +648,38 @@ static inline void update_sq_db(struct hns_roce_dev *hr_dev, } } +static void hns_roce_write512(struct hns_roce_dev *hr_dev, u64 *val, + u64 __iomem *dest) +{ +#define HNS_ROCE_WRITE_TIMES 8 + struct hns_roce_v2_priv *priv = (struct hns_roce_v2_priv *)hr_dev->priv; + struct hnae3_handle *handle = priv->handle; + const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + int i; + + if (!hr_dev->dis_db && !ops->get_hw_reset_stat(handle)) + for (i = 0; i < HNS_ROCE_WRITE_TIMES; i++) + writeq_relaxed(*(val + i), dest + i); +} + +static void write_dwqe(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp, + void *wqe) +{ + struct hns_roce_v2_rc_send_wqe *rc_sq_wqe = wqe; + + /* All kinds of DirectWQE have the same header field layout */ + roce_set_bit(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_FLAG_S, 1); + roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M, + V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S, qp->sl); + roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M, + V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S, qp->sl >> 2); + roce_set_field(rc_sq_wqe->byte_4, V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M, + V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S, qp->sq.head); + + hns_roce_write512(hr_dev, wqe, hr_dev->mem_base + + HNS_ROCE_DWQE_SIZE * qp->ibqp.qp_num); +} + static int hns_roce_v2_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, const struct ib_send_wr **bad_wr) @@ -710,7 +746,12 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp, qp->next_sge = sge_idx; /* Memory barrier */ wmb(); - update_sq_db(hr_dev, qp); + + if (nreq == 1 && qp->sq.head == qp->sq.tail + 1 && + (qp->en_flags & HNS_ROCE_QP_CAP_DIRECT_WQE)) + write_dwqe(hr_dev, qp, wqe); + else + update_sq_db(hr_dev, qp); } spin_unlock_irqrestore(&qp->sq.lock, flags); @@ -6273,6 +6314,7 @@ static void hns_roce_hw_v2_get_cfg(struct hns_roce_dev *hr_dev, /* Get info from NIC driver. */ hr_dev->reg_base = handle->rinfo.roce_io_base; + hr_dev->mem_base = handle->rinfo.roce_mem_base; hr_dev->caps.num_ports = 1; hr_dev->iboe.netdevs[0] = handle->rinfo.netdev; hr_dev->iboe.phy_port[0] = 0; diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h index 69bc072..add1816 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h @@ -1098,6 +1098,8 @@ struct hns_roce_v2_mpt_entry { #define V2_DB_BYTE_4_CMD_S 24 #define V2_DB_BYTE_4_CMD_M GENMASK(27, 24) +#define V2_DB_FLAG_S 31 + #define V2_DB_PARAMETER_IDX_S 0 #define V2_DB_PARAMETER_IDX_M GENMASK(15, 0) @@ -1194,6 +1196,15 @@ struct hns_roce_v2_rc_send_wqe { #define V2_RC_SEND_WQE_BYTE_4_OPCODE_S 0 #define V2_RC_SEND_WQE_BYTE_4_OPCODE_M GENMASK(4, 0) +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_S 5 +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_L_M GENMASK(6, 5) + +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_S 13 +#define V2_RC_SEND_WQE_BYTE_4_DB_SL_H_M GENMASK(14, 13) + +#define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_S 15 +#define V2_RC_SEND_WQE_BYTE_4_WQE_INDEX_M GENMASK(30, 15) + #define V2_RC_SEND_WQE_BYTE_4_OWNER_S 7 #define V2_RC_SEND_WQE_BYTE_4_CQE_S 8 @@ -1216,6 +1227,8 @@ struct hns_roce_v2_rc_send_wqe { #define V2_RC_FRMR_WQE_BYTE_4_LW_S 23 +#define V2_RC_SEND_WQE_BYTE_4_FLAG_S 31 + #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S 0 #define V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M GENMASK(23, 0) -- 2.8.1

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[PATCH for-next 00/12] RDMA/hns: Several fixes and cleanups of RQ/SRQ
by Weihang Li 09 Feb '21

09 Feb '21

There are some issues when using SRQ on HIP08/HIP09, the first part of this series is some fixes on them. In addition, the codes about RQ/SRQ including the creation and post recv flow are a bit hard to understand, they need to be refactored. Lang Cheng (2): RDMA/hns: Allocate one more recv SGE for HIP08 RDMA/hns: Use new interfaces to write SRQC Wenpeng Liang (8): RDMA/hns: Bugfix for checking whether the srq is full when post wr RDMA/hns: Force srq_limit to 0 when creating SRQ RDMA/hns: Fixed wrong judgments in the goto branch RDMA/hns: Remove the reserved WQE of SRQ RDMA/hns: Refactor hns_roce_create_srq() RDMA/hns: Refactor code about SRQ Context RDMA/hns: Refactor hns_roce_v2_post_srq_recv() RDMA/hns: Add verification of QP type when post_recv Xi Wang (2): RDMA/hns: Refactor post recv flow RDMA/hns: Clear remaining unused sges when post_recv drivers/infiniband/hw/hns/hns_roce_device.h | 16 +- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 407 +++++++++++++++------------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 72 +++-- drivers/infiniband/hw/hns/hns_roce_main.c | 3 +- drivers/infiniband/hw/hns/hns_roce_qp.c | 37 ++- drivers/infiniband/hw/hns/hns_roce_srq.c | 329 ++++++++++++---------- 6 files changed, 510 insertions(+), 354 deletions(-) -- 2.8.1

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[PATCH] mmc: cavium: Replace spin_lock_irqsave with spin_lock in hard IRQ
by Xiaofei Tan 08 Feb '21

08 Feb '21

It is redundant to do irqsave and irqrestore in hardIRQ context, where it has been in a irq-disabled context. Signed-off-by: Xiaofei Tan <tanxiaofei(a)huawei.com> --- drivers/mmc/host/cavium.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/cavium.c b/drivers/mmc/host/cavium.c index c5da3aa..4bb8f28 100644 --- a/drivers/mmc/host/cavium.c +++ b/drivers/mmc/host/cavium.c @@ -436,12 +436,11 @@ irqreturn_t cvm_mmc_interrupt(int irq, void *dev_id) { struct cvm_mmc_host *host = dev_id; struct mmc_request *req; - unsigned long flags = 0; u64 emm_int, rsp_sts; bool host_done; if (host->need_irq_handler_lock) - spin_lock_irqsave(&host->irq_handler_lock, flags); + spin_lock(&host->irq_handler_lock); else __acquire(&host->irq_handler_lock); @@ -504,7 +503,7 @@ irqreturn_t cvm_mmc_interrupt(int irq, void *dev_id) host->release_bus(host); out: if (host->need_irq_handler_lock) - spin_unlock_irqrestore(&host->irq_handler_lock, flags); + spin_unlock(&host->irq_handler_lock); else __release(&host->irq_handler_lock); return IRQ_RETVAL(emm_int != 0); -- 2.8.1

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[PATCH for-next 00/32] spin lock usage optimization for SCSI drivers
by Xiaofei Tan 07 Feb '21

07 Feb '21

Replace spin_lock_irqsave with spin_lock in hard IRQ of SCSI drivers. There are no function changes, but may speed up if interrupt happen too often. Xiaofei Tan (32): scsi: 53c700: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: ipr: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: lpfc: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: qla4xxx: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: BusLogic: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: a100u2w: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: a2091: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: a3000: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: aha1740: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: bfa: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: esp_scsi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: gvp11: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: hptiop: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: ibmvscsi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: initio: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: megaraid: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: mac53c94: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: mesh: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: mvumi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: myrb: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: myrs: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: ncr53c8xx: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: nsp32: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: pmcraid: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: pcmcia: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: qlogicfas408: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: qlogicpti: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: sgiwd93: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: stex: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: vmw_pvscsi: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: wd719x: Replace spin_lock_irqsave with spin_lock in hard IRQ scsi: advansys: Replace spin_lock_irqsave with spin_lock in hard IRQ drivers/scsi/53c700.c | 5 ++-- drivers/scsi/BusLogic.c | 5 ++-- drivers/scsi/a100u2w.c | 5 ++-- drivers/scsi/a2091.c | 5 ++-- drivers/scsi/a3000.c | 5 ++-- drivers/scsi/advansys.c | 5 ++-- drivers/scsi/aha1740.c | 5 ++-- drivers/scsi/bfa/bfad.c | 20 ++++++------- drivers/scsi/esp_scsi.c | 5 ++-- drivers/scsi/gvp11.c | 5 ++-- drivers/scsi/hptiop.c | 5 ++-- drivers/scsi/ibmvscsi/ibmvfc.c | 5 ++-- drivers/scsi/initio.c | 5 ++-- drivers/scsi/ipr.c | 21 ++++++------- drivers/scsi/lpfc/lpfc_sli.c | 49 +++++++++++++------------------ drivers/scsi/mac53c94.c | 5 ++-- drivers/scsi/megaraid.c | 10 +++---- drivers/scsi/megaraid/megaraid_sas_base.c | 5 ++-- drivers/scsi/mesh.c | 5 ++-- drivers/scsi/mvumi.c | 7 ++--- drivers/scsi/myrb.c | 20 +++++-------- drivers/scsi/myrs.c | 15 ++++------ drivers/scsi/ncr53c8xx.c | 5 ++-- drivers/scsi/nsp32.c | 5 ++-- drivers/scsi/pcmcia/sym53c500_cs.c | 5 ++-- drivers/scsi/pmcraid.c | 8 ++--- drivers/scsi/qla4xxx/ql4_isr.c | 15 ++++------ drivers/scsi/qlogicfas408.c | 5 ++-- drivers/scsi/qlogicpti.c | 5 ++-- drivers/scsi/sgiwd93.c | 5 ++-- drivers/scsi/stex.c | 16 +++++----- drivers/scsi/vmw_pvscsi.c | 4 +-- drivers/scsi/wd719x.c | 7 ++--- 33 files changed, 122 insertions(+), 175 deletions(-) -- 2.8.1

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[PATCH for-next 0/6] RDMA/hns: Fix and refactor CMDQ related code
by Weihang Li 07 Feb '21

07 Feb '21

Remove some dead code in process of CMDQ transmission, and fix an issue about missing error code. Lang Cheng (6): RDMA/hns: Remove unused member and variable of CMDQ RDMA/hns: Remove unsupported CMDQ mode RDMA/hns: Fixes missing error code of CMDQ RDMA/hns: Remove redundant operations on CMDQ RDMA/hns: Adjust fields and variables about CMDQ tail/head RDMA/hns: Refactor process of posting CMDQ drivers/infiniband/hw/hns/hns_roce_common.h | 4 +- drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 142 ++++++++-------------------- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 7 -- 3 files changed, 42 insertions(+), 111 deletions(-) -- 2.8.1

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[PATCH v2 RFC 0/7] RDMA/hns: Add support for Dynamic Context Attachment
by Weihang Li 07 Feb '21

07 Feb '21

The hip09 introduces the DCA(Dynamic Context Attachment) feature which supports many RC QPs to share the WQE buffer in a memory pool. If a QP enables DCA feature, the WQE's buffer will not be allocated when creating but when the users start to post WRs. This will reduce the memory consumption when there are too many QPs are inactive. Changes since v1: * Replace all GFP_ATOMIC with GFP_NOWAIT, because the former may use emergency pool if no regular memory can be found. * Change size of cap_flags of alloc_ucontext_resp from 32 to 64 to avoid a potential problem when pass it back to the userspace. * Move definition of HNS_ROCE_CAP_FLAG_DCA_MODE to hns-abi.h. * Rename free_mem_states() to free_dca_states() in #1. * Link: https://patchwork.kernel.org/project/linux-rdma/cover/1610706138-4219-1-git… Xi Wang (7): RDMA/hns: Introduce DCA for RC QP RDMA/hns: Add method for shrinking DCA memory pool RDMA/hns: Configure DCA mode for the userspace QP RDMA/hns: Add method for attaching WQE buffer RDMA/hns: Setup the configuration of WQE addressing to QPC RDMA/hns: Add method to detach WQE buffer RDMA/hns: Add method to query WQE buffer's address drivers/infiniband/hw/hns/Makefile | 2 +- drivers/infiniband/hw/hns/hns_roce_dca.c | 1264 +++++++++++++++++++++++++++ drivers/infiniband/hw/hns/hns_roce_dca.h | 68 ++ drivers/infiniband/hw/hns/hns_roce_device.h | 31 + drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 223 ++++- drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 3 + drivers/infiniband/hw/hns/hns_roce_main.c | 27 +- drivers/infiniband/hw/hns/hns_roce_qp.c | 119 ++- include/uapi/rdma/hns-abi.h | 64 ++ 9 files changed, 1754 insertions(+), 47 deletions(-) create mode 100644 drivers/infiniband/hw/hns/hns_roce_dca.c create mode 100644 drivers/infiniband/hw/hns/hns_roce_dca.h -- 2.8.1

3 9

[PATCH V2 net-next 0/6] net: hns3: updates for -nex
by Huazhong Tan 07 Feb '21

07 Feb '21

This series adds some code optimizations and compatibility handlings for the HNS3 ethernet driver. change log: V2: refactor #2 as Jukub Kicinski reported and remove the part about RSS size which will not be different in different hw. updates netdev->max_mtu as well in #4 reported by Jakub Kicinski. previous version: V1: https://patchwork.kernel.org/project/netdevbpf/cover/1612269593-18691-1-git… Guangbin Huang (3): net: hns3: RSS indirection table use device specification net: hns3: debugfs add max tm rate specification print net: hns3: replace macro of max qset number with specification GuoJia Liao (1): net: hns3: optimize the code when update the tc info Jian Shen (1): net: hns3: add api capability bits for firmware Yufeng Mo (1): net: hns3: add support for obtaining the maximum frame size drivers/net/ethernet/hisilicon/hns3/hnae3.h | 5 +- drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 3 ++ drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 3 +- drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 5 +- drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 6 +-- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c | 10 ++++ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 9 +++- .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 8 ++- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 57 +++++++++++++++------- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 8 +-- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 15 ++++-- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c | 10 ++++ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h | 9 +++- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 47 ++++++++++++------ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 8 +-- 15 files changed, 140 insertions(+), 63 deletions(-) -- 2.7.4

2 7

[PATCH for-next] RDMA/pvrdma: Replace spin_lock_irqsave with spin_lock in hard IRQ
by Weihang Li 06 Feb '21

06 Feb '21

There is no need to do irqsave and irqrestore in context of hard IRQ. Signed-off-by: Weihang Li <liweihang(a)huawei.com> --- drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c index 00a3309..4b6019e 100644 --- a/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c +++ b/drivers/infiniband/hw/vmw_pvrdma/pvrdma_main.c @@ -474,7 +474,6 @@ static irqreturn_t pvrdma_intrx_handler(int irq, void *dev_id) int ring_slots = (dev->dsr->cq_ring_pages.num_pages - 1) * PAGE_SIZE / sizeof(struct pvrdma_cqne); unsigned int head; - unsigned long flags; dev_dbg(&dev->pdev->dev, "interrupt x (completion) handler\n"); @@ -483,11 +482,11 @@ static irqreturn_t pvrdma_intrx_handler(int irq, void *dev_id) struct pvrdma_cq *cq; cqne = get_cqne(dev, head); - spin_lock_irqsave(&dev->cq_tbl_lock, flags); + spin_lock(&dev->cq_tbl_lock); cq = dev->cq_tbl[cqne->info % dev->dsr->caps.max_cq]; if (cq) refcount_inc(&cq->refcnt); - spin_unlock_irqrestore(&dev->cq_tbl_lock, flags); + spin_unlock(&dev->cq_tbl_lock); if (cq && cq->ibcq.comp_handler) cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); -- 2.8.1

2 1

[PATCH v3 1/2] dma-mapping: benchmark: use u8 for reserved field in uAPI structure
by Barry Song 05 Feb '21

05 Feb '21

The original code put five u32 before a u64 expansion[10] array. Five is odd, this will cause trouble in the extension of the structure by adding new features. This patch moves to use u8 for reserved field to avoid future alignment risk. Meanwhile, it also clears the memory of struct map_benchmark in tools, otherwise, if users use old version to run on newer kernel, the random expansion value will cause side effect on newer kernel. Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- kernel/dma/map_benchmark.c | 2 +- tools/testing/selftests/dma/dma_map_benchmark.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/kernel/dma/map_benchmark.c b/kernel/dma/map_benchmark.c index 1b1b8ff875cb..da95df381483 100644 --- a/kernel/dma/map_benchmark.c +++ b/kernel/dma/map_benchmark.c @@ -36,7 +36,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ - __u64 expansion[10]; /* For future use */ + __u8 expansion[84]; /* For future use */ }; struct map_benchmark_data { diff --git a/tools/testing/selftests/dma/dma_map_benchmark.c b/tools/testing/selftests/dma/dma_map_benchmark.c index 7065163a8388..537d65968c48 100644 --- a/tools/testing/selftests/dma/dma_map_benchmark.c +++ b/tools/testing/selftests/dma/dma_map_benchmark.c @@ -6,6 +6,7 @@ #include <fcntl.h> #include <stdio.h> #include <stdlib.h> +#include <string.h> #include <unistd.h> #include <sys/ioctl.h> #include <sys/mman.h> @@ -35,7 +36,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ - __u64 expansion[10]; /* For future use */ + __u8 expansion[84]; /* For future use */ }; int main(int argc, char **argv) @@ -102,6 +103,7 @@ int main(int argc, char **argv) exit(1); } + memset(&map, 0, sizeof(map)); map.seconds = seconds; map.threads = threads; map.node = node; -- 2.25.1

2 2

[PATCH v2] dma-mapping: benchmark: pretend DMA is transmitting
by Barry Song 05 Feb '21

05 Feb '21

In a real dma mapping user case, after dma_map is done, data will be transmit. Thus, in multi-threaded user scenario, IOMMU contention should not be that severe. For example, if users enable multiple threads to send network packets through 1G/10G/100Gbps NIC, usually the steps will be: map -> transmission -> unmap. Transmission delay reduces the contention of IOMMU. Here a delay is added to simulate the transmission between map and unmap so that the tested result could be more accurate for TX and simple RX. A typical TX transmission for NIC would be like: map -> TX -> unmap since the socket buffers come from OS. Simple RX model eg. disk driver, is also map -> RX -> unmap, but real RX model in a NIC could be more complicated considering packets can come spontaneously and many drivers are using pre-mapped buffers pool. This is in the TBD list. Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- -v2: cleanup according to Robin's feedback. thanks, Robin. kernel/dma/map_benchmark.c | 10 ++++++++++ .../testing/selftests/dma/dma_map_benchmark.c | 19 +++++++++++++++++-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/kernel/dma/map_benchmark.c b/kernel/dma/map_benchmark.c index 1b1b8ff875cb..06636406a245 100644 --- a/kernel/dma/map_benchmark.c +++ b/kernel/dma/map_benchmark.c @@ -21,6 +21,7 @@ #define DMA_MAP_BENCHMARK _IOWR('d', 1, struct map_benchmark) #define DMA_MAP_MAX_THREADS 1024 #define DMA_MAP_MAX_SECONDS 300 +#define DMA_MAP_MAX_TRANS_DELAY (10 * NSEC_PER_MSEC) /* 10ms */ #define DMA_MAP_BIDIRECTIONAL 0 #define DMA_MAP_TO_DEVICE 1 @@ -36,6 +37,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ + __u32 dma_trans_ns; /* time for DMA transmission in ns */ __u64 expansion[10]; /* For future use */ }; @@ -87,6 +89,9 @@ static int map_benchmark_thread(void *data) map_etime = ktime_get(); map_delta = ktime_sub(map_etime, map_stime); + /* Pretend DMA is transmitting */ + ndelay(map->bparam.dma_trans_ns); + unmap_stime = ktime_get(); dma_unmap_single(map->dev, dma_addr, PAGE_SIZE, map->dir); unmap_etime = ktime_get(); @@ -218,6 +223,11 @@ static long map_benchmark_ioctl(struct file *file, unsigned int cmd, return -EINVAL; } + if (map->bparam.dma_trans_ns > DMA_MAP_MAX_TRANS_DELAY) { + pr_err("invalid transmission delay\n"); + return -EINVAL; + } + if (map->bparam.node != NUMA_NO_NODE && !node_possible(map->bparam.node)) { pr_err("invalid numa node\n"); diff --git a/tools/testing/selftests/dma/dma_map_benchmark.c b/tools/testing/selftests/dma/dma_map_benchmark.c index 7065163a8388..a370290d9503 100644 --- a/tools/testing/selftests/dma/dma_map_benchmark.c +++ b/tools/testing/selftests/dma/dma_map_benchmark.c @@ -11,9 +11,12 @@ #include <sys/mman.h> #include <linux/types.h> +#define NSEC_PER_MSEC 1000000L + #define DMA_MAP_BENCHMARK _IOWR('d', 1, struct map_benchmark) #define DMA_MAP_MAX_THREADS 1024 #define DMA_MAP_MAX_SECONDS 300 +#define DMA_MAP_MAX_TRANS_DELAY (10 * NSEC_PER_MSEC) /* 10ms */ #define DMA_MAP_BIDIRECTIONAL 0 #define DMA_MAP_TO_DEVICE 1 @@ -35,6 +38,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ + __u32 dma_trans_ns; /* delay for DMA transmission in ns */ __u64 expansion[10]; /* For future use */ }; @@ -45,12 +49,12 @@ int main(int argc, char **argv) /* default single thread, run 20 seconds on NUMA_NO_NODE */ int threads = 1, seconds = 20, node = -1; /* default dma mask 32bit, bidirectional DMA */ - int bits = 32, dir = DMA_MAP_BIDIRECTIONAL; + int bits = 32, xdelay = 0, dir = DMA_MAP_BIDIRECTIONAL; int cmd = DMA_MAP_BENCHMARK; char *p; - while ((opt = getopt(argc, argv, "t:s:n:b:d:")) != -1) { + while ((opt = getopt(argc, argv, "t:s:n:b:d:x:")) != -1) { switch (opt) { case 't': threads = atoi(optarg); @@ -67,6 +71,9 @@ int main(int argc, char **argv) case 'd': dir = atoi(optarg); break; + case 'x': + xdelay = atoi(optarg); + break; default: return -1; } @@ -84,6 +91,12 @@ int main(int argc, char **argv) exit(1); } + if (xdelay < 0 || xdelay > DMA_MAP_MAX_TRANS_DELAY) { + fprintf(stderr, "invalid transmit delay, must be in 0-%ld\n", + DMA_MAP_MAX_TRANS_DELAY); + exit(1); + } + /* suppose the mininum DMA zone is 1MB in the world */ if (bits < 20 || bits > 64) { fprintf(stderr, "invalid dma mask bit, must be in 20-64\n"); @@ -107,6 +120,8 @@ int main(int argc, char **argv) map.node = node; map.dma_bits = bits; map.dma_dir = dir; + map.dma_trans_ns = xdelay; + if (ioctl(fd, cmd, &map)) { perror("ioctl"); exit(1); -- 2.25.1

3 5

[PATCH] perf metricgroup: Fix system PMU metrics
by John Garry 05 Feb '21

05 Feb '21

Joakim reports that getting "perf stat" for multiple system PMU metrics segfaults: ./perf stat -a -I 1000 -M imx8mm_ddr_write.all,imx8mm_ddr_write.all Segmentation fault While the same works without issue for a single metric. The logic in metricgroup__add_metric_sys_event_iter() is broken, in that add_metric() @m argument should be NULL for each new metric. Fix by not passing a holder for that, and rather make local in metricgroup__add_metric_sys_event_iter(). Fixes: be335ec28efa ("perf metricgroup: Support adding metrics for system PMUs") Reported-by: Joakim Zhang <qiangqing.zhang(a)nxp.com> Signed-off-by: John Garry <john.garry(a)huawei.com> diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index ee94d3e8dd65..2e60ee170abc 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -766,7 +766,6 @@ int __weak arch_get_runtimeparam(struct pmu_event *pe __maybe_unused) struct metricgroup_add_iter_data { struct list_head *metric_list; const char *metric; - struct metric **m; struct expr_ids *ids; int *ret; bool *has_match; @@ -1058,12 +1057,13 @@ static int metricgroup__add_metric_sys_event_iter(struct pmu_event *pe, void *data) { struct metricgroup_add_iter_data *d = data; + struct metric *m = NULL; int ret; if (!match_pe_metric(pe, d->metric)) return 0; - ret = add_metric(d->metric_list, pe, d->metric_no_group, d->m, NULL, d->ids); + ret = add_metric(d->metric_list, pe, d->metric_no_group, &m, NULL, d->ids); if (ret) return ret; @@ -1114,7 +1114,6 @@ static int metricgroup__add_metric(const char *metric, bool metric_no_group, .metric_list = &list, .metric = metric, .metric_no_group = metric_no_group, - .m = &m, .ids = &ids, .has_match = &has_match, .ret = &ret, -- 2.26.2

4 15

[PATCH] dma-mapping: benchmark: pretend DMA is transmitting
by Barry Song 05 Feb '21

05 Feb '21

In a real dma mapping user case, after dma_map is done, data will be transmit. Thus, in multi-threaded user scenario, IOMMU contention should not be that severe. For example, if users enable multiple threads to send network packets through 1G/10G/100Gbps NIC, usually the steps will be: map -> transmission -> unmap. Transmission delay reduces the contention of IOMMU. Here a delay is added to simulate the transmission for TX case so that the tested result could be more accurate. RX case would be much more tricky. It is not supported yet. Signed-off-by: Barry Song <song.bao.hua(a)hisilicon.com> --- kernel/dma/map_benchmark.c | 11 +++++++++++ tools/testing/selftests/dma/dma_map_benchmark.c | 17 +++++++++++++++-- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/kernel/dma/map_benchmark.c b/kernel/dma/map_benchmark.c index 1b1b8ff875cb..1976db7e34e4 100644 --- a/kernel/dma/map_benchmark.c +++ b/kernel/dma/map_benchmark.c @@ -21,6 +21,7 @@ #define DMA_MAP_BENCHMARK _IOWR('d', 1, struct map_benchmark) #define DMA_MAP_MAX_THREADS 1024 #define DMA_MAP_MAX_SECONDS 300 +#define DMA_MAP_MAX_TRANS_DELAY (10 * 1000 * 1000) /* 10ms */ #define DMA_MAP_BIDIRECTIONAL 0 #define DMA_MAP_TO_DEVICE 1 @@ -36,6 +37,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ + __u32 dma_trans_ns; /* time for DMA transmission in ns */ __u64 expansion[10]; /* For future use */ }; @@ -87,6 +89,10 @@ static int map_benchmark_thread(void *data) map_etime = ktime_get(); map_delta = ktime_sub(map_etime, map_stime); + /* Pretend DMA is transmitting */ + if (map->dir != DMA_FROM_DEVICE) + ndelay(map->bparam.dma_trans_ns); + unmap_stime = ktime_get(); dma_unmap_single(map->dev, dma_addr, PAGE_SIZE, map->dir); unmap_etime = ktime_get(); @@ -218,6 +224,11 @@ static long map_benchmark_ioctl(struct file *file, unsigned int cmd, return -EINVAL; } + if (map->bparam.dma_trans_ns > DMA_MAP_MAX_TRANS_DELAY) { + pr_err("invalid transmission delay\n"); + return -EINVAL; + } + if (map->bparam.node != NUMA_NO_NODE && !node_possible(map->bparam.node)) { pr_err("invalid numa node\n"); diff --git a/tools/testing/selftests/dma/dma_map_benchmark.c b/tools/testing/selftests/dma/dma_map_benchmark.c index 7065163a8388..dbf426e2fb7f 100644 --- a/tools/testing/selftests/dma/dma_map_benchmark.c +++ b/tools/testing/selftests/dma/dma_map_benchmark.c @@ -14,6 +14,7 @@ #define DMA_MAP_BENCHMARK _IOWR('d', 1, struct map_benchmark) #define DMA_MAP_MAX_THREADS 1024 #define DMA_MAP_MAX_SECONDS 300 +#define DMA_MAP_MAX_TRANS_DELAY (10 * 1000 * 1000) /* 10ms */ #define DMA_MAP_BIDIRECTIONAL 0 #define DMA_MAP_TO_DEVICE 1 @@ -35,6 +36,7 @@ struct map_benchmark { __s32 node; /* which numa node this benchmark will run on */ __u32 dma_bits; /* DMA addressing capability */ __u32 dma_dir; /* DMA data direction */ + __u32 dma_trans_ns; /* delay for DMA transmission in ns */ __u64 expansion[10]; /* For future use */ }; @@ -45,12 +47,12 @@ int main(int argc, char **argv) /* default single thread, run 20 seconds on NUMA_NO_NODE */ int threads = 1, seconds = 20, node = -1; /* default dma mask 32bit, bidirectional DMA */ - int bits = 32, dir = DMA_MAP_BIDIRECTIONAL; + int bits = 32, xdelay = 0, dir = DMA_MAP_BIDIRECTIONAL; int cmd = DMA_MAP_BENCHMARK; char *p; - while ((opt = getopt(argc, argv, "t:s:n:b:d:")) != -1) { + while ((opt = getopt(argc, argv, "t:s:n:b:d:x:")) != -1) { switch (opt) { case 't': threads = atoi(optarg); @@ -67,6 +69,9 @@ int main(int argc, char **argv) case 'd': dir = atoi(optarg); break; + case 'x': + xdelay = atoi(optarg); + break; default: return -1; } @@ -84,6 +89,12 @@ int main(int argc, char **argv) exit(1); } + if (xdelay < 0 || xdelay > DMA_MAP_MAX_TRANS_DELAY) { + fprintf(stderr, "invalid transmit delay, must be in 0-%d\n", + DMA_MAP_MAX_TRANS_DELAY); + exit(1); + } + /* suppose the mininum DMA zone is 1MB in the world */ if (bits < 20 || bits > 64) { fprintf(stderr, "invalid dma mask bit, must be in 20-64\n"); @@ -107,6 +118,8 @@ int main(int argc, char **argv) map.node = node; map.dma_bits = bits; map.dma_dir = dir; + map.dma_trans_ns = xdelay; + if (ioctl(fd, cmd, &map)) { perror("ioctl"); exit(1); -- 2.25.1

3 2

[PATCH] spi: clps711xx: remove redundant white-space
by Yicong Yang 05 Feb '21

05 Feb '21

From: Junhao He <hejunhao2(a)hisilicon.com> Remove redundant white-space, no functional change. Signed-off-by: Junhao He <hejunhao2(a)hisilicon.com> Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> --- drivers/spi/spi-clps711x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-clps711x.c b/drivers/spi/spi-clps711x.c index 5e900f2..0bef5ce 100644 --- a/drivers/spi/spi-clps711x.c +++ b/drivers/spi/spi-clps711x.c @@ -104,7 +104,7 @@ static int spi_clps711x_probe(struct platform_device *pdev) master->use_gpio_descriptors = true; master->bus_num = -1; master->mode_bits = SPI_CPHA | SPI_CS_HIGH; - master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8); + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8); master->dev.of_node = pdev->dev.of_node; master->prepare_message = spi_clps711x_prepare_message; master->transfer_one = spi_clps711x_transfer_one; -- 2.8.1

2 1

[PATCH 00/11] critical bugfixes for hns3
by Lijun Ou 04 Feb '21

04 Feb '21

Based on some suggestions, we reorganize the fixes and resend the only fixes. Chengchang Tang (4): net/hns3: fix stats flip overflow net/hns3: replace all atomic type with C11 atomic builtins net/hns3: fix cmdq cleared during firmware process net/hns3: fix VF reset after MBX failed Chengwen Feng (3): net/hns3: constraint TM peak rate net/hns3: remove MPLS type from supported flow items net/hns3: fix FD rule residue in hardware when malloc fail Huisong Li (3): net/hns3: fix query order of link status and link info net/hns3: fix link status change from firmware net/hns3: add check for max pkt length of Rx Lijun Ou (1): net/hns3: fix RSS indirection table size drivers/net/hns3/hns3_cmd.c | 36 ++++++++++-- drivers/net/hns3/hns3_cmd.h | 18 +++++- drivers/net/hns3/hns3_dcb.c | 2 +- drivers/net/hns3/hns3_ethdev.c | 116 ++++++++++++++++++++++++++++++-------- drivers/net/hns3/hns3_ethdev.h | 4 +- drivers/net/hns3/hns3_ethdev_vf.c | 62 ++++++++++++++------ drivers/net/hns3/hns3_flow.c | 36 ++++++------ drivers/net/hns3/hns3_intr.c | 22 +++++--- drivers/net/hns3/hns3_mbx.c | 4 +- drivers/net/hns3/hns3_rss.c | 28 ++++----- drivers/net/hns3/hns3_rss.h | 5 +- drivers/net/hns3/hns3_stats.c | 21 +++++-- drivers/net/hns3/hns3_tm.c | 6 ++ 13 files changed, 258 insertions(+), 102 deletions(-) -- 2.7.4

2 12

[PATCH net-next 0/7] net: hns3: updates for -next
by Huazhong Tan 04 Feb '21

04 Feb '21

This series includes some updates for the HNS3 ethernet driver. #1~#6 add some code optimizations and compatibility handlings. #7 fixes a clang warning. Guangbin Huang (3): net: hns3: RSS indirection table and key use device specifications net: hns3: debugfs add max tm rate specification print net: hns3: replace macro of max qset number with specification GuoJia Liao (1): net: hns3: optimize the code when update the tc info Huazhong Tan (1): net: hns3: remove unnecessary check in hns3_dbg_read() Jian Shen (1): net: hns3: add api capability bits for firmware Yufeng Mo (1): net: hns3: add support for obtaining the maximum frame length drivers/net/ethernet/hisilicon/hns3/hnae3.h | 8 +--- drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 5 +- drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 12 ++--- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c | 10 ++++ .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 9 +++- .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 8 ++-- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 53 ++++++++++++---------- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 14 ++++-- .../net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c | 15 ++++-- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c | 10 ++++ .../ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h | 6 ++- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 44 ++++++++---------- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 11 +++-- 13 files changed, 115 insertions(+), 90 deletions(-) -- 2.7.4

2 11

[PATCH hulk-4.19-next for SDI] net: hns3: adds support for setting pf max tx rate via sysfs
by Yonglong Liu 04 Feb '21

04 Feb '21

driver inclusion category: feature bugzilla: NA CVE: NA DTS:SR20210201768145 ---------------------------- This patch adds support for setting/getting pf max tx rate via sysfs: echo <rate Mbit/s> > /sys/class/net/<eth name>/kunpeng/pf/max_tx_rate cat /sys/class/net/<eth name>/kunpeng/pf/max_tx_rate Signed-off-by: Yonglong Liu <liuyonglong(a)huawei.com> --- drivers/net/ethernet/hisilicon/hns3/Makefile | 3 +- drivers/net/ethernet/hisilicon/hns3/hnae3.h | 6 + .../hns3/hns3_extension/hns3pf/hclge_main_it.c | 33 +++++ .../hns3/hns3_extension/hns3pf/hclge_sysfs.c | 140 +++++++++++++++++++++ .../hns3/hns3_extension/hns3pf/hclge_sysfs.h | 14 +++ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 17 +++ .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 3 + 7 files changed, 215 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c create mode 100644 drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h diff --git a/drivers/net/ethernet/hisilicon/hns3/Makefile b/drivers/net/ethernet/hisilicon/hns3/Makefile index bd607c0..5efa685 100644 --- a/drivers/net/ethernet/hisilicon/hns3/Makefile +++ b/drivers/net/ethernet/hisilicon/hns3/Makefile @@ -38,7 +38,8 @@ HCLGE_OBJ = hns3pf/hclge_main.o \ hns3pf/hclge_err.o -HCLGE_OBJ_IT_MAIN = hns3_extension/hns3pf/hclge_main_it.o +HCLGE_OBJ_IT_MAIN = hns3_extension/hns3pf/hclge_main_it.o \ + hns3_extension/hns3pf/hclge_sysfs.o obj-$(CONFIG_HNS3_HCLGE) += hclge.o hclge-objs := $(HCLGE_OBJ) $(HCLGE_OBJ_IT_MAIN) hclge-$(CONFIG_HNS3_DCB) += hns3pf/hclge_dcb.o diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h index 3c56cbc..ac8a7c1 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h @@ -578,6 +578,9 @@ struct hnae3_ae_ops { int (*ecc_handle)(struct hnae3_ae_dev *ae_dev); int (*priv_ops)(struct hnae3_handle *handle, int opcode, void *data, int length); + void (*ext_init)(struct hnae3_handle *handle); + void (*ext_uninit)(struct hnae3_handle *handle); + void (*ext_reset_done)(struct hnae3_handle *handle); #endif }; @@ -713,6 +716,9 @@ struct hnae3_handle { /* Network interface message level enabled bits */ u32 msg_enable; + + /* for sysfs */ + struct kobject *kobj; }; #define hnae3_set_field(origin, mask, shift, val) \ diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c index 01f0e19..59e2878 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_main_it.c @@ -18,6 +18,9 @@ #include "hclge_main.h" #include "hnae3.h" #include "hclge_main_it.h" +#ifdef CONFIG_HNS3_TEST +#include "hclge_sysfs.h" +#endif #ifdef CONFIG_IT_VALIDATION #define HCLGE_RESET_MAX_FAIL_CNT 1 @@ -174,8 +177,38 @@ bool hclge_reset_done_it(struct hnae3_handle *handle, bool done) return done; } +#ifdef CONFIG_HNS3_TEST +void hclge_ext_init(struct hnae3_handle *handle) +{ + hclge_sysfs_init(handle); +} + +void hclge_ext_uninit(struct hnae3_handle *handle) +{ + struct hclge_vport *vport = hclge_get_vport(handle); + struct hclge_dev *hdev = vport->back; + + hclge_reset_pf_rate(hdev); + hclge_sysfs_uninit(handle); +} + +void hclge_ext_reset_done(struct hnae3_handle *handle) +{ + struct hclge_vport *vport = hclge_get_vport(handle); + struct hclge_dev *hdev = vport->back; + + hclge_resume_pf_rate(hdev); +} +#endif + int hclge_init_it(void) { +#ifdef CONFIG_HNS3_TEST + hclge_ops.ext_init = hclge_ext_init; + hclge_ops.ext_uninit = hclge_ext_uninit; + hclge_ops.ext_reset_done = hclge_ext_reset_done; +#endif + hclge_ops.reset_event = hclge_reset_event_it; hclge_ops.reset_done = hclge_reset_done_it; hclge_ops.handle_imp_error = hclge_handle_imp_error_it; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c new file mode 100644 index 00000000..86e6093 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (c) 2018-2021 Hisilicon Limited. */ + +#include <linux/device.h> +#include "hnae3.h" +#include "hclge_main.h" +#include "hclge_tm.h" +#include "hclge_sysfs.h" + +void hclge_reset_pf_rate(struct hclge_dev *hdev) +{ + struct hclge_vport *vport = &hdev->vport[0]; + int ret; + + /* zero means max rate, if max_tx_rate is zero, just return */ + if (!vport->vf_info.max_tx_rate) + return; + + vport->vf_info.max_tx_rate = 0; + + ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); + if (ret) + dev_err(&hdev->pdev->dev, + "failed to reset pf tx rate to default, ret = %d.\n", + ret); +} + +int hclge_resume_pf_rate(struct hclge_dev *hdev) +{ + struct hclge_vport *vport = &hdev->vport[0]; + int ret; + + /* zero means max rate, after reset, firmware already set it to + * max rate, so just continue. + */ + if (!vport->vf_info.max_tx_rate) + return 0; + + ret = hclge_tm_qs_shaper_cfg(vport, vport->vf_info.max_tx_rate); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to resume pf tx rate:%u, ret = %d.\n", + vport->vf_info.max_tx_rate, ret); + return ret; + } + + return 0; +} + +static ssize_t hclge_max_tx_rate_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + struct hclge_vport *vport = + container_of(kobj, struct hclge_vport, kobj); + + return sprintf(buf, "%d Mbit/s (0 means no limit)\n", + vport->vf_info.max_tx_rate); +} + +static ssize_t hclge_max_tx_rate_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, + size_t size) +{ + struct hclge_vport *vport = + container_of(kobj, struct hclge_vport, kobj); + struct hclge_dev *hdev = vport->back; + int max_tx_rate; + int ret; + + ret = kstrtoint(buf, 0, &max_tx_rate); + if (ret) + return -EINVAL; + + if (max_tx_rate < 0 || max_tx_rate > hdev->hw.mac.max_speed) { + dev_err(&hdev->pdev->dev, + "invalid max_tx_rate:%d [0, %u]\n", + max_tx_rate, hdev->hw.mac.max_speed); + return -EINVAL; + } + + ret = hclge_tm_qs_shaper_cfg(vport, max_tx_rate); + if (ret) + return ret; + + vport->vf_info.max_tx_rate = max_tx_rate; + + return ret ? (ssize_t)ret : size; +} + +static struct kobj_attribute hclge_attr_max_tx_rate = { + .attr = {.name = "max_tx_rate", + .mode = 0644 }, + .show = hclge_max_tx_rate_show, + .store = hclge_max_tx_rate_store, +}; + +static struct attribute *hclge_sysfs_attrs[] = { + &hclge_attr_max_tx_rate.attr, + NULL, +}; + +static struct kobj_type hclge_sysfs_type = { + .sysfs_ops = &kobj_sysfs_ops, + .default_attrs = hclge_sysfs_attrs, +}; + +void hclge_sysfs_init(struct hnae3_handle *handle) +{ + struct net_device *netdev = handle->netdev; + struct hclge_vport *vport = hclge_get_vport(handle); + int ret; + + handle->kobj = kobject_create_and_add("kunpeng", &netdev->dev.kobj); + if (!handle->kobj) { + netdev_err(netdev, "failed to create kobj, ret = %d\n", ret); + return; + } + + ret = kobject_init_and_add(&vport->kobj, &hclge_sysfs_type, + handle->kobj, "pf"); + if (ret) { + netdev_err(netdev, "failed to init kobj, ret = %d\n", ret); + kobject_put(handle->kobj); + handle->kobj = NULL; + } +} + +void hclge_sysfs_uninit(struct hnae3_handle *handle) +{ + struct hclge_vport *vport = hclge_get_vport(handle); + + if (!handle->kobj) + return; + + kobject_put(&vport->kobj); + kobject_put(handle->kobj); + handle->kobj = NULL; +} diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h new file mode 100644 index 00000000..8eb3335 --- /dev/null +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_extension/hns3pf/hclge_sysfs.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * Copyright (c) 2018-2021 Hisilicon Limited. + */ + +#ifndef __HCLGE_SYSFS_H +#define __HCLGE_SYSFS_H + +void hclge_reset_pf_rate(struct hclge_dev *hdev); +int hclge_resume_pf_rate(struct hclge_dev *hdev); + +void hclge_sysfs_init(struct hnae3_handle *handle); +void hclge_sysfs_uninit(struct hnae3_handle *handle); + +#endif diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index b40cf43..7b6d7c1 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -9946,6 +9946,11 @@ static int hclge_init_nic_client_instance(struct hnae3_ae_dev *ae_dev, if (ret) return ret; +#ifdef CONFIG_HNS3_TEST + if (ae_dev->ops->ext_init) + ae_dev->ops->ext_init(&vport->nic); +#endif + set_bit(HCLGE_STATE_NIC_REGISTERED, &hdev->state); if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) || rst_cnt != hdev->rst_stats.reset_cnt) { @@ -10087,6 +10092,13 @@ static void hclge_uninit_client_instance(struct hnae3_client *client, struct hclge_vport *vport; int i; +#ifdef CONFIG_HNS3_TEST + if (ae_dev->ops->ext_uninit) { + vport = &hdev->vport[0]; + ae_dev->ops->ext_uninit(&vport->nic); + } +#endif + for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { vport = &hdev->vport[i]; if (hdev->roce_client) { @@ -10817,6 +10829,11 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) if (ret) return ret; +#ifdef CONFIG_HNS3_TEST + if (ae_dev->ops->ext_reset_done) + ae_dev->ops->ext_reset_done(&hdev->vport->nic); +#endif + dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", HCLGE_DRIVER_NAME); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h index 08d17ba..a0d2b4d 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h @@ -970,6 +970,9 @@ struct hclge_vport { struct list_head uc_mac_list; /* Store VF unicast table */ struct list_head mc_mac_list; /* Store VF multicast table */ struct list_head vlan_list; /* Store VF vlan table */ + + /* for sysfs */ + struct kobject kobj; }; int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, -- 2.7.4

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[RFC PATCH 0/4] hw/cxl/ + /hw/pci/: PCI DOE + CXL CDAT emulation
by Jonathan Cameron 04 Feb '21

04 Feb '21

Whilst I know others are working on an implementation of at least some of this, a desire to work on the kernel user of this required an implementation so I threw this together in the meantime and am sending it out on the basis that it may be of use to others. As it is an RFC I have been lazy on some cleanup and error handling. Will fix that in a future version if we decide to take this forwards. Based on Ben's cxl-2.0v3 branch from https://gitlab.com/bwidawsk/qemu Possible I've picked an unstable branch so this may or may not currently apply :) I'll rebase on Ben's next version when avaialble. Jonathan Cameron (4): include/standard-headers/linux/pci_regs: temp hack to add necessary DOE definitions. hw/pci/pcie_doe: Introduce utility functions for PCIe DOE hw/cxl/cxl-cdat: Initial CDAT implementation for use by CXL devices hw/mem/cxl_type3: Enabled DOE mailbox for access to CDAT hw/cxl/cxl-cdat.c | 252 +++++++++++++++++++++ hw/cxl/meson.build | 1 + hw/mem/cxl_type3.c | 49 ++++- hw/pci/meson.build | 2 +- hw/pci/pcie_doe.c | 257 ++++++++++++++++++++++ include/hw/cxl/cxl.h | 1 + include/hw/cxl/cxl_cdat.h | 101 +++++++++ include/hw/pci/doe.h | 40 ++++ include/hw/pci/pci_ids.h | 2 + include/standard-headers/linux/pci_regs.h | 33 ++- 10 files changed, 734 insertions(+), 4 deletions(-) create mode 100644 hw/cxl/cxl-cdat.c create mode 100644 hw/pci/pcie_doe.c create mode 100644 include/hw/cxl/cxl_cdat.h create mode 100644 include/hw/pci/doe.h -- 2.19.1

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[RFC PATCH 0/3] hw/arm/virt: CXL enablement including gpex-acpi
by Jonathan Cameron 04 Feb '21

04 Feb '21

Very basic initial enablement of CXL on arm virt with relevant ACPI table construction. Includes changes in gpex-acpi to ensure correct DSDT for any pci_expand_bridge/pxb-cxl bridges. Note not looking to do the primary root bridge yet. Based on Ben's tree cxl-2.0v3 at https://gitlab.com/bwidawsk/qemu To actually get the memory appropriately exposed to the OS a few additional changes are needed as discussed in thread https://lore.kernel.org/qemu-devel/20210128174009.00007536@Huawei.com/ I will rebase this on future versions of Ben's series as needed. Jonathan Cameron (3): hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl hw/cxl/cxl-device-utils: Allow incorrect read lengths hw/arm/Kconfig | 1 + hw/arm/virt-acpi-build.c | 27 +++++++++++++++++++++++++++ hw/arm/virt.c | 3 ++- hw/cxl/cxl-device-utils.c | 4 ++-- hw/pci-host/gpex-acpi.c | 22 +++++++++++++++++++--- 5 files changed, 51 insertions(+), 6 deletions(-) -- 2.19.1

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[PATCH] PCI/DPC: Check host->native_dpc before enable dpc service
by Yicong Yang 03 Feb '21

03 Feb '21

Per PCI Firmware Specification Rev. 3.2 Table 4-6, Interpretation of _OSC Control Field Returned Value, for bit 7 of _OSC control return value: "Firmware sets this bit to 1 to grant the OS control over PCI Express Downstream Port Containment configuration." "If control of this feature was requested and denied, or was not requested, the firmware returns this bit set to 0." We store bit 7 of _OSC control return value in host->native_dpc, check it before enable the dpc service as the firmware may not grant the control. Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> --- drivers/pci/pcie/portdrv_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index e1fed664..7445d03 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -253,7 +253,8 @@ static int get_port_device_capability(struct pci_dev *dev) */ if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC) && pci_aer_available() && - (pcie_ports_dpc_native || (services & PCIE_PORT_SERVICE_AER))) + (pcie_ports_dpc_native || + ((services & PCIE_PORT_SERVICE_AER) && host->native_dpc))) services |= PCIE_PORT_SERVICE_DPC; if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM || -- 2.8.1

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