From: Qingtong Jia <jiaqingtong@huawei.com> Signed-off-by: Qingtong Jia <jiaqingtong@huawei.com> --- scripts/arm-gen-cpu-sysregs-header.awk | 5 ++++- scripts/gen-cpu-sysreg-properties.awk | 21 +++++++++++++++++++++ target/arm/cpu-sysreg-properties.c | 19 +++++++++++++++++++ target/arm/cpu-sysregs.h.inc | 4 +++- target/arm/cpu64.c | 2 +- 5 files changed, 48 insertions(+), 3 deletions(-) diff --git a/scripts/arm-gen-cpu-sysregs-header.awk b/scripts/arm-gen-cpu-sysregs-header.awk index f92bbbafa7..9f16e420f8 100755 --- a/scripts/arm-gen-cpu-sysregs-header.awk +++ b/scripts/arm-gen-cpu-sysregs-header.awk @@ -9,7 +9,10 @@ BEGIN { print "/* GENERATED FILE, DO NOT EDIT */" print "/* use arm-gen-cpu-sysregs-header.awk to regenerate */" } END { - print "" + /* add MIDR, REVIDR, and AIDR */ + print "DEF(MIDR_EL1, 3, 0, 0, 0, 0)" + print "DEF(REVIDR_EL1, 3, 0, 0, 0, 6)" + print "DEF(AIDR_EL1, 3, 1, 0, 0, 7)" } # skip blank lines and comment lines diff --git a/scripts/gen-cpu-sysreg-properties.awk b/scripts/gen-cpu-sysreg-properties.awk index da00d377ff..56d9d8f002 100755 --- a/scripts/gen-cpu-sysreg-properties.awk +++ b/scripts/gen-cpu-sysreg-properties.awk @@ -106,6 +106,27 @@ END { if (__current_block_depth != 0) fatal("Missing terminator for " block_current() " block") + # Manually add MIDR/REVIDR/AIDR + print "" + print " /* MIDR_EL1 */" + print " ARM64SysReg *MIDR_EL1 = arm64_sysreg_get(MIDR_EL1_IDX);" + print " MIDR_EL1->name = \"MIDR_EL1\";" + print " arm64_sysreg_add_field(MIDR_EL1, \"Implementer\", 24, 31);" + print " arm64_sysreg_add_field(MIDR_EL1, \"Variant\", 20, 23);" + print " arm64_sysreg_add_field(MIDR_EL1, \"Architecture\", 16, 19);" + print " arm64_sysreg_add_field(MIDR_EL1, \"PartNum\", 4, 15);" + print " arm64_sysreg_add_field(MIDR_EL1, \"Revision\", 0, 3);" + print "" + print " /* REVIDR_EL1 */" + print " ARM64SysReg *REVIDR_EL1 = arm64_sysreg_get(REVIDR_EL1_IDX);" + print " REVIDR_EL1->name = \"REVIDR_EL1\";" + print " arm64_sysreg_add_field(REVIDR_EL1, \"IMPDEF\", 0, 63);" + print "" + print " /* AIDR_EL1 */" + print " ARM64SysReg *AIDR_EL1 = arm64_sysreg_get(AIDR_EL1_IDX);" + print " AIDR_EL1->name = \"AIDR_EL1\";" + print " arm64_sysreg_add_field(AIDR_EL1, \"IMPDEF\", 0, 63);" + print "" print "}" } diff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-properties.c index 94cc496438..c8a43c9eb4 100644 --- a/target/arm/cpu-sysreg-properties.c +++ b/target/arm/cpu-sysreg-properties.c @@ -742,4 +742,23 @@ void initialize_cpu_sysreg_properties(void) /* For S2PIR_EL2 fields see PIRx_ELx */ + /* MIDR_EL1 */ + ARM64SysReg *MIDR_EL1 = arm64_sysreg_get(MIDR_EL1_IDX); + MIDR_EL1->name = "MIDR_EL1"; + arm64_sysreg_add_field(MIDR_EL1, "Implementer", 24, 31); + arm64_sysreg_add_field(MIDR_EL1, "Variant", 20, 23); + arm64_sysreg_add_field(MIDR_EL1, "Architecture", 16, 19); + arm64_sysreg_add_field(MIDR_EL1, "PartNum", 4, 15); + arm64_sysreg_add_field(MIDR_EL1, "Revision", 0, 3); + + /* REVIDR_EL1 */ + ARM64SysReg *REVIDR_EL1 = arm64_sysreg_get(REVIDR_EL1_IDX); + REVIDR_EL1->name = "REVIDR_EL1"; + arm64_sysreg_add_field(REVIDR_EL1, "IMPDEF", 0, 63); + + /* AIDR_EL1 */ + ARM64SysReg *AIDR_EL1 = arm64_sysreg_get(AIDR_EL1_IDX); + AIDR_EL1->name = "AIDR_EL1"; + arm64_sysreg_add_field(AIDR_EL1, "IMPDEF", 0, 63); + } diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 1dddd3d357..e3e81e11ee 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -50,4 +50,6 @@ DEF(GMID_EL1, 3, 1, 0, 0, 4) DEF(SMIDR_EL1, 3, 1, 0, 0, 6) DEF(CTR_EL0, 3, 3, 0, 0, 1) DEF(DCZID_EL0, 3, 3, 0, 0, 7) - +DEF(MIDR_EL1, 3, 0, 0, 0, 0) +DEF(REVIDR_EL1, 3, 0, 0, 0, 6) +DEF(AIDR_EL1, 3, 1, 0, 0, 7) \ No newline at end of file diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index bf8a242c80..593bfea299 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -53,7 +53,7 @@ int get_sysreg_idx(ARMSysRegs sysreg) switch (sysreg) { #include "cpu-sysregs.h.inc" } - g_assert_not_reached(); + return -1; } #undef DEF -- 2.33.0