[PATCH qemu-8.2.0] hw/intc: fix the issue of vNMI not supporting live migration

5 Nov 2025

Add the migration of GICR_INMIR0. vNMI migration for SPI is not
supported, only supports SGI and PPI in guest.

Sign-off-by: Jinqian Yang <yangjinqian1@huawei.com>
---
 hw/intc/arm_gicv3_common.c         | 20 ++++++++++++++++++++
 hw/intc/arm_gicv3_kvm.c            | 22 ++++++++++++++++++++++
 hw/intc/gicv3_internal.h           |  1 +
 include/hw/intc/arm_gicv3_common.h |  3 +++
 4 files changed, 46 insertions(+)

diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 5667d9f40b..8bf4d15fd3 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -164,6 +164,24 @@ const VMStateDescription vmstate_gicv3_gicv4 = {
     }
 };
 
+static bool gicv3_inmir_needed(void *opaque)
+{
+    GICv3CPUState *cs = opaque;
+
+    return cs->gic->inmir_support;
+}
+
+const VMStateDescription vmstate_gicv3_cpu_inmir = {
+    .name = "arm_gicv3_cpu/inmir",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = gicv3_inmir_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(gicr_inmir0, GICv3CPUState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription vmstate_gicv3_cpu = {
     .name = "arm_gicv3_cpu",
     .version_id = 1,
@@ -196,6 +214,7 @@ static const VMStateDescription vmstate_gicv3_cpu = {
         &vmstate_gicv3_cpu_virt,
         &vmstate_gicv3_cpu_sre_el1,
         &vmstate_gicv3_gicv4,
+        &vmstate_gicv3_cpu_inmir,
         NULL
     }
 };
@@ -554,6 +573,7 @@ static void arm_gicv3_common_reset_hold(Object *obj)
         cs->edge_trigger = 0xffff;
         cs->gicr_igrpmodr0 = 0;
         cs->gicr_nsacr = 0;
+        cs->gicr_inmir0 = 0;
         memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
 
         cs->hppi.prio = 0xff;
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index dd2a60fa20..77e82e6e2a 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -397,6 +397,9 @@ static void kvm_arm_gicv3_put(GICv3State *s)
         reg = c->gicr_iactiver0;
         kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true);
 
+        reg = c->gicr_inmir0;
+        kvm_gicr_access(s, GICR_INMIR0, ncpu, ®, true);
+
         for (i = 0; i < GIC_INTERNAL; i += 4) {
             reg = c->gicr_ipriorityr[i] |
                 (c->gicr_ipriorityr[i + 1] << 8) |
@@ -561,6 +564,8 @@ static void kvm_arm_gicv3_get(GICv3State *s)
         c->gicr_ipendr0 = reg;
         kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false);
         c->gicr_iactiver0 = reg;
+        kvm_gicr_access(s, GICR_INMIR0, ncpu, ®, false);
+        c->gicr_inmir0 = reg;
 
         for (i = 0; i < GIC_INTERNAL; i += 4) {
             kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false);
@@ -809,6 +814,17 @@ static void kvm_gicv3_init_cpu_reginfo(CPUState *cs)
     define_arm_cp_regs(ARM_CPU(cs), gicv3_cpuif_reginfo);
 }
 
+static bool kvm_gicv3_check_inmir(GICv3State *s, int cpu)
+{
+    uint32_t value = 0;
+    return !kvm_device_access(s->dev_fd,
+                             KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
+                             KVM_VGIC_ATTR(GICR_INMIR0, cpu),
+                             &value,
+                             false,
+                             NULL) && value != 0;
+}
+
 static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
 {
     GICv3State *s = KVM_ARM_GICV3(dev);
@@ -918,6 +934,12 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
                               KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES)) {
         qemu_add_vm_change_state_handler(vm_change_state_handler, s);
     }
+
+    if (kvm_gicv3_check_inmir(s, 0)) {
+        s->inmir_support = true;
+    } else {
+        s->inmir_support = false;
+    }
 }
 
 static void kvm_arm_gicv3_class_init(ObjectClass *klass, void *data)
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
index 0bed0f6e2a..2b982716d6 100644
--- a/hw/intc/gicv3_internal.h
+++ b/hw/intc/gicv3_internal.h
@@ -109,6 +109,7 @@
 #define GICR_ICFGR1           (GICR_SGI_OFFSET + 0x0C04)
 #define GICR_IGRPMODR0        (GICR_SGI_OFFSET + 0x0D00)
 #define GICR_NSACR            (GICR_SGI_OFFSET + 0x0E00)
+#define GICR_INMIR0           (GICR_SGI_OFFSET + 0x0F80)
 
 /* VLPI redistributor registers, offsets from VLPI_base */
 #define GICR_VPROPBASER       (GICR_VLPI_OFFSET + 0x70)
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h
index b5f8ba17ff..4b8012bd89 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -173,6 +173,7 @@ struct GICv3CPUState {
     uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */
     uint32_t gicr_igrpmodr0;
     uint32_t gicr_nsacr;
+    uint32_t gicr_inmir0;
     uint8_t gicr_ipriorityr[GIC_INTERNAL];
     /* VLPI_base page registers */
     uint64_t gicr_vpropbaser;
@@ -284,6 +285,8 @@ struct GICv3State {
     GICv3CPUState *cpu;
     /* List of all ITSes connected to this GIC */
     GPtrArray *itslist;
+
+    bool inmir_support;
 };
 
 #define GICV3_BITMAP_ACCESSORS(BMP)                                     \
-- 
2.33.0

    

Jinqian Yang

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