[PATCH qemu-8.2.0 0/9] Add support for heterogeneous live migration in QEMU
Patch#1 target/arm: Introduce a kunpeng CPU model Patch#2 target/arm: Add support for KVM_ARM_GET_REG_WRITABLE_MASKS Patch#3 target/arm: Retrieve additional register information from host Patch#4 target/arm: Update kunpeng 920 register to a common minimum feature list Patch#5 target/arm: Write ID register CPU state values to list Patch#6 target/arm: Ignore invariant register write errors Patch#7 target/arm: Disable SVE extensions when SVE is disabled Patch#8 target/arm: Add ID_AA64MMFR3_EL1 Patch#9 target/arm: update cpu->prop_pauth after change isar2 value Marcin Juszkiewicz (1): target/arm: Disable SVE extensions when SVE is disabled Shameer Kolothum (6): target/arm: Introduce a kunpeng CPU model target/arm: Add support for KVM_ARM_GET_REG_WRITABLE_MASKS target/arm: Retrieve additional register information from host target/arm: Update kunpeng 920 register to a common minimum feature list target/arm: Write ID register CPU state values to list target/arm: Ignore invariant register write errors yangjinqian (2): target/arm: Add ID_AA64MMFR3_EL1 target/arm: update cpu->prop_pauth after change isar2 value hw/arm/virt.c | 3 ++ target/arm/cpregs.h | 9 ++++++ target/arm/cpu.h | 20 +++++++++++++ target/arm/cpu64.c | 22 ++++++++++++++ target/arm/helper.c | 58 +++++++++++++++++++++++++----------- target/arm/hvf/hvf.c | 2 ++ target/arm/kunpeng920-regs.c | 55 ++++++++++++++++++++++++++++++++++ target/arm/kvm.c | 19 ++++++++++++ target/arm/kvm64.c | 21 +++++++++++++ target/arm/kvm_arm.h | 4 +++ target/arm/meson.build | 2 +- 11 files changed, 196 insertions(+), 19 deletions(-) create mode 100644 target/arm/kunpeng920-regs.c -- 2.33.0
From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> virt inclusion category: feature bugzilla: https://gitee.com/openeuler/qemu/issues/IBSJV9 ------------------------------------------------------------------------ For now this is the same as the host CPU. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- hw/arm/virt.c | 3 +++ target/arm/cpu64.c | 15 +++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8823f2ed1c..0ce826a0fd 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -232,6 +232,9 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("Kunpeng-920"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), +#if defined(CONFIG_KVM) + ARM_CPU_TYPE_NAME("kunpeng-920"), +#endif /* CONFIG_KVM */ }; static CPUArchId *virt_find_cpu_slot(MachineState *ms, int vcpuid); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6eca55ac29..69c3f5710e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -817,6 +817,18 @@ static void aarch64_max_initfn(Object *obj) } } +static void aarch64_kunpeng_920_initfn_hack(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + if (kvm_enabled()) { + aarch64_host_initfn(obj); + } else { + cpu->host_cpu_probe_failed = true; + return; + } +} + static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, @@ -825,6 +837,9 @@ static const ARMCPUInfo aarch64_cpus[] = { #if defined(CONFIG_KVM) || defined(CONFIG_HVF) { .name = "host", .initfn = aarch64_host_initfn }, #endif +#if defined(CONFIG_KVM) + { .name = "kunpeng-920", .initfn = aarch64_kunpeng_920_initfn_hack }, +#endif }; static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) -- 2.33.0
From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> virt inclusion category: feature bugzilla: https://gitee.com/openeuler/qemu/issues/IBSJV9 ------------------------------------------------------------------------ The retrieved mask will be used later to check whether we can write to ID register fields. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- target/arm/cpu.h | 2 ++ target/arm/kvm.c | 1 + target/arm/kvm64.c | 11 +++++++++++ target/arm/kvm_arm.h | 1 + 4 files changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a5ba7f2a26..6622256bdd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1121,6 +1121,8 @@ struct ArchCPU { /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; + + uint64_t *writable_masks; }; typedef struct ARMCPUInfo { diff --git a/target/arm/kvm.c b/target/arm/kvm.c index ee5ba68305..01ff28671f 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -188,6 +188,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) cpu->kvm_target = arm_host_cpu_features.target; cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; cpu->isar = arm_host_cpu_features.isar; + cpu->writable_masks = arm_host_cpu_features.writable_masks; env->features = arm_host_cpu_features.features; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index b099287ed0..540da767c1 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -281,6 +281,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) */ struct kvm_vcpu_init init = { .target = -1, }; + struct reg_mask_range range; + uint64_t *writable_masks; /* * Ask for SVE if supported, so that we can query ID_AA64ZFR0, * which is otherwise RAZ. @@ -454,6 +456,15 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } } + writable_masks = g_new0(uint64_t, KVM_ARM_FEATURE_ID_RANGE_SIZE); + memset(&range, 0, sizeof(range)); + range.addr = (__u64)writable_masks; + if (!ioctl(fdarray[1], KVM_ARM_GET_REG_WRITABLE_MASKS, &range)) { + ahcf->writable_masks = writable_masks; + } else { + g_free(writable_masks); + } + kvm_arm_destroy_scratch_host_vcpu(fdarray); if (err < 0) { diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 31457a57f7..bbf869860b 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -242,6 +242,7 @@ typedef struct ARMHostCPUFeatures { uint64_t features; uint32_t target; const char *dtb_compatible; + uint64_t *writable_masks; } ARMHostCPUFeatures; /** -- 2.33.0
From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> virt inclusion category: feature bugzilla: https://gitee.com/openeuler/qemu/issues/IBSJV9 ------------------------------------------------------------------------ This is useful to determine the host CPU vendor and can be used for migration support. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- target/arm/kvm.c | 3 +++ target/arm/kvm64.c | 8 ++++++++ target/arm/kvm_arm.h | 3 +++ 3 files changed, 14 insertions(+) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 01ff28671f..d98c3d1bf5 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -188,6 +188,9 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) cpu->kvm_target = arm_host_cpu_features.target; cpu->dtb_compatible = arm_host_cpu_features.dtb_compatible; cpu->isar = arm_host_cpu_features.isar; + cpu->midr = arm_host_cpu_features.midr; + cpu->revidr = arm_host_cpu_features.revidr; + cpu->ctr = arm_host_cpu_features.ctr; cpu->writable_masks = arm_host_cpu_features.writable_masks; env->features = arm_host_cpu_features.features; } diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 540da767c1..237de8015d 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -356,6 +356,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, ARM64_SYS_REG(3, 0, 0, 7, 2)); + err |= read_sys_reg64(fdarray[2], &ahcf->midr, + ARM64_SYS_REG(3, 0, 0, 0, 0)); + err |= read_sys_reg64(fdarray[2], &ahcf->revidr, + ARM64_SYS_REG(3, 0, 0, 0, 6)); + + err |= read_sys_reg64(fdarray[2], &ahcf->ctr, + ARM64_SYS_REG(3, 3, 0, 0, 1)); + /* * Note that if AArch32 support is not present in the host, * the AArch32 sysregs are present to be read, but will diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index bbf869860b..af95698b2b 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -242,6 +242,9 @@ typedef struct ARMHostCPUFeatures { uint64_t features; uint32_t target; const char *dtb_compatible; + uint64_t midr; + uint64_t revidr; + uint64_t ctr; uint64_t *writable_masks; } ARMHostCPUFeatures; -- 2.33.0
From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> virt inclusion category: feature bugzilla: https://gitee.com/openeuler/qemu/issues/IBSJV9 ------------------------------------------------------------------------ The register set represents a common minimum between HIP09、HIP10 and HIP12. We need to check the writable masks to verify whether we can actually update KVM with these new register values. Otherwise KVM set reg may fail later. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- target/arm/cpregs.h | 9 ++++++++ target/arm/cpu64.c | 5 +++++ target/arm/kunpeng920-regs.c | 42 ++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 2 +- 4 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 target/arm/kunpeng920-regs.c diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index f1293d16c0..d0e34c2ae1 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -1077,6 +1077,15 @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif +#ifdef CONFIG_KVM +int kunpeng920_update_registers(ARMCPU *cpu); +#else +static inline int kunpeng920_update_registers(ARMCPU *cpu) +{ + return -EINVAL; +} +#endif + CPAccessResult access_tvm_trvm(CPUARMState *, const ARMCPRegInfo *, bool); #endif /* TARGET_ARM_CPREGS_H */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 69c3f5710e..6a03fa97bc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -827,6 +827,11 @@ static void aarch64_kunpeng_920_initfn_hack(Object *obj) cpu->host_cpu_probe_failed = true; return; } + + if (kunpeng920_update_registers(cpu)) { + cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; + return; + } } static const ARMCPUInfo aarch64_cpus[] = { diff --git a/target/arm/kunpeng920-regs.c b/target/arm/kunpeng920-regs.c new file mode 100644 index 0000000000..8a764a2011 --- /dev/null +++ b/target/arm/kunpeng920-regs.c @@ -0,0 +1,42 @@ +/* + * HiSilicon Kunpeng 920 registers + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpregs.h" + +int kunpeng920_update_registers(ARMCPU *cpu) +{ + /* + * Check host is indeed a supported HiSilicon 920 platform and + * kernel supports writable ID reg. + * We now only supports HIP09 & HIP10 & HIP12. + */ + if ((cpu->midr != 0x480fd020 && cpu->midr != 0x480fd030 && + cpu->midr != 0x480fd060) || !cpu->writable_masks) { + return -EINVAL; + } + + /* + * Set a miniumum set of features between HIP09、HIP10 and HIP12. + * This is to enable migration between these two. + * We need to make use of writable_masks to check + * whether we can actually change the host returned values. + * If not, KVM write reg will fail later. + */ + cpu->isar.id_aa64pfr0 = 0x1101001121111111; + cpu->isar.id_aa64pfr1 = 0x21; + cpu->isar.id_aa64isar2 = 0; + cpu->isar.id_aa64mmfr1 = 0x110212122; + cpu->isar.id_aa64mmfr2 = 0x1221011110000010; + cpu->isar.id_aa64dfr0 = 0xf010305409; + cpu->isar.id_aa64zfr0 = 0x100000100000; + cpu->ctr = 0xb4448004; + + return 0; +} diff --git a/target/arm/meson.build b/target/arm/meson.build index 389ee54658..902602a93e 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -8,7 +8,7 @@ arm_ss.add(files( )) arm_ss.add(zlib) -arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c', 'kvm64.c'), if_false: files('kvm-stub.c')) +arm_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c', 'kvm64.c', 'kunpeng920-regs.c'), if_false: files('kvm-stub.c')) arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c', 'kvm-tmm.c'), if_false: files('kvm-stub.c')) -- 2.33.0
From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> virt inclusion category: feature bugzilla: https://gitee.com/openeuler/qemu/issues/IBSJV9 ------------------------------------------------------------------------ At present CPU state ID register values are not updated to list. Only the list values are later synced to KVM. Hence update the list with ID register values. Whether use the KVM to set up reg here is worth considering. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- target/arm/helper.c | 54 +++++++++++++++++++++++++++++++-------------- 1 file changed, 38 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0370a739e3..4c73005a2e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -116,6 +116,25 @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri) return true; } + +static bool is_id_register(const ARMCPRegInfo *ri) +{ + /* + * (Op0, Op1, CRn, CRm, Op2) of ID registers is (3, 0, 0, crm, op2), + * where 1<=crm<8, 0<=op2<8. + */ + if (ri->opc0 == 3 && ri->opc1 == 0 && ri->crn == 0 && + ri->crm > 0 && ri->crm < 8) { + return true; + } else if (ri->opc0 == 3 && ri->opc1 == 3 && ri->crn == 0 && + ri->crm == 0 && ri->opc2 == 1) { + /* CTR_EL0 */ + return true; + } + + return false; +} + bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) { /* Write the coprocessor state from cpu->env to the (index,value) list. */ @@ -132,30 +151,33 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) ok = false; continue; } - if (ri->type & ARM_CP_NO_RAW) { + if (ri->type & ARM_CP_NO_RAW && !(kvm_sync && is_id_register(ri))) { continue; } newval = read_raw_cp_reg(&cpu->env, ri); if (kvm_sync) { - /* - * Only sync if the previous list->cpustate sync succeeded. - * Rather than tracking the success/failure state for every - * item in the list, we just recheck "does the raw write we must - * have made in write_list_to_cpustate() read back OK" here. - */ - uint64_t oldval = cpu->cpreg_values[i]; + /* Check we need to attempt a KVM sync when ri is id register. */ + if (!is_id_register(ri)) { + /* + * Only sync if the previous list->cpustate sync succeeded. + * Rather than tracking the success/failure state for every + * item in the list, we just recheck "does the raw write we must + * have made in write_list_to_cpustate() read back OK" here. + */ + uint64_t oldval = cpu->cpreg_values[i]; - if (oldval == newval) { - continue; - } + if (oldval == newval) { + continue; + } - write_raw_cp_reg(&cpu->env, ri, oldval); - if (read_raw_cp_reg(&cpu->env, ri) != oldval) { - continue; - } + write_raw_cp_reg(&cpu->env, ri, oldval); + if (read_raw_cp_reg(&cpu->env, ri) != oldval) { + continue; + } - write_raw_cp_reg(&cpu->env, ri, newval); + write_raw_cp_reg(&cpu->env, ri, newval); + } } cpu->cpreg_values[i] = newval; } -- 2.33.0
From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> virt inclusion category: feature bugzilla: https://gitee.com/openeuler/qemu/issues/IBSJV9 ------------------------------------------------------------------------ MIDR/AIDR/REVIDR are treated as invariant registers by ARM64 KVM and hence not possible to write a value that differs from host CPU. This will break migration if they are different. Ignore invariant register difference and keep the host value for Kunpeng 920 for now. Find a better way to do this. Also investigate KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 difference. Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- target/arm/cpu.h | 1 + target/arm/kunpeng920-regs.c | 5 +++++ target/arm/kvm.c | 15 +++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6622256bdd..db59ce8644 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1123,6 +1123,7 @@ struct ArchCPU { uint64_t gt_cntfrq_hz; uint64_t *writable_masks; + bool ignore_invariant_reg; }; typedef struct ARMCPUInfo { diff --git a/target/arm/kunpeng920-regs.c b/target/arm/kunpeng920-regs.c index 8a764a2011..a424a14d28 100644 --- a/target/arm/kunpeng920-regs.c +++ b/target/arm/kunpeng920-regs.c @@ -38,5 +38,10 @@ int kunpeng920_update_registers(ARMCPU *cpu) cpu->isar.id_aa64zfr0 = 0x100000100000; cpu->ctr = 0xb4448004; + /* + * MIDR/REVIDR/AIDR are invariant registers and not writable. + * Ignore any differences between HIP09、HIP10 and HIP12 for now. + */ + cpu->ignore_invariant_reg = true; return 0; } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d98c3d1bf5..eb72f44eaa 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -602,6 +602,18 @@ bool write_kvmstate_to_list(ARMCPU *cpu) return ok; } +static bool is_invariant_reg(uint64_t regidx) +{ + /* We need a better way to handle this */ + if ((regidx == ARM64_SYS_REG(3, 0, 0, 0, 0)) || /*MIDR*/ + (regidx == ARM64_SYS_REG(3, 1, 0, 0, 7)) || /*AIDR*/ + (regidx == KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3)) { + return true; + } + + return false; +} + bool write_list_to_kvmstate(ARMCPU *cpu, int level) { CPUState *cs = CPU(cpu); @@ -628,6 +640,9 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) break; case KVM_REG_SIZE_U64: ret = kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i); + if (ret && cpu->ignore_invariant_reg && is_invariant_reg(regidx)) { + ret = kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i); + } break; default: g_assert_not_reached(); -- 2.33.0
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> virt inclusion category: feature bugzilla: https://gitee.com/openeuler/qemu/issues/IBSJV9 ------------------------------------------------------------------------ Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304 Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20240526204551.553282-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> (cherry picked from commit daf9748ac002ec35258e5986b6257961fd04b565) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- target/arm/cpu64.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6a03fa97bc..30769832c9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -231,6 +231,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) error_append_hint(errp, "SVE must be enabled to enable vector " "lengths.\n"); error_append_hint(errp, "Add sve=on to the CPU property list.\n"); + /* Disable all SVE extensions as well. */ + cpu->isar.id_aa64zfr0 = 0; return; } -- 2.33.0
virt inclusion category: feature bugzilla: https://gitee.com/openeuler/qemu/issues/IBSJV9 ------------------------------------------------------------------------ Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- target/arm/cpu.h | 17 +++++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 2 ++ target/arm/kvm64.c | 2 ++ 4 files changed, 23 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index db59ce8644..2442099b6a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1039,6 +1039,7 @@ struct ArchCPU { uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; + uint64_t id_aa64mmfr3; uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; uint64_t id_aa64zfr0; @@ -2368,6 +2369,22 @@ FIELD(ID_AA64MMFR2, BBM, 52, 4) FIELD(ID_AA64MMFR2, EVT, 56, 4) FIELD(ID_AA64MMFR2, E0PD, 60, 4) +FIELD(ID_AA64MMFR3, TCRX, 0, 4) +FIELD(ID_AA64MMFR3, SCTLRX, 4, 4) +FIELD(ID_AA64MMFR3, S1PIE, 8, 4) +FIELD(ID_AA64MMFR3, S2PIE, 12, 4) +FIELD(ID_AA64MMFR3, S1POE, 16, 4) +FIELD(ID_AA64MMFR3, S2POE, 20, 4) +FIELD(ID_AA64MMFR3, AIE, 24, 4) +FIELD(ID_AA64MMFR3, MEC, 28, 4) +FIELD(ID_AA64MMFR3, D128, 32, 4) +FIELD(ID_AA64MMFR3, D128_2, 36, 4) +FIELD(ID_AA64MMFR3, SNERR, 40, 4) +FIELD(ID_AA64MMFR3, ANERR, 44, 4) +FIELD(ID_AA64MMFR3, SDERR, 52, 4) +FIELD(ID_AA64MMFR3, ADERR, 56, 4) +FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) + FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) FIELD(ID_AA64DFR0, TRACEVER, 4, 4) FIELD(ID_AA64DFR0, PMUVER, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index 4c73005a2e..fc131d770d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8526,11 +8526,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64mmfr2 }, - { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64mmfr3 }, { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index d7cc00a084..fc32f20463 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -493,6 +493,7 @@ static struct hvf_sreg_match hvf_sreg_match[] = { #endif { HV_SYS_REG_ID_AA64MMFR1_EL1, HVF_SYSREG(0, 7, 3, 0, 1) }, { HV_SYS_REG_ID_AA64MMFR2_EL1, HVF_SYSREG(0, 7, 3, 0, 2) }, + /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ { HV_SYS_REG_MDSCR_EL1, HVF_SYSREG(0, 2, 2, 0, 2) }, { HV_SYS_REG_SCTLR_EL1, HVF_SYSREG(1, 0, 3, 0, 0) }, @@ -851,6 +852,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, + /* Add ID_AA64MMFR3_EL1 here when HVF supports it */ }; hv_vcpu_t fd; hv_return_t r = HV_SUCCESS; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 237de8015d..539cb466e3 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -355,6 +355,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 7, 1)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, ARM64_SYS_REG(3, 0, 0, 7, 2)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3, + ARM64_SYS_REG(3, 0, 0, 7, 3)); err |= read_sys_reg64(fdarray[2], &ahcf->midr, ARM64_SYS_REG(3, 0, 0, 0, 0)); -- 2.33.0
virt inclusion category: feature bugzilla: https://gitee.com/openeuler/qemu/issues/IBSJV9 ------------------------------------------------------------------------ Signed-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- target/arm/kunpeng920-regs.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/kunpeng920-regs.c b/target/arm/kunpeng920-regs.c index a424a14d28..a95befc32d 100644 --- a/target/arm/kunpeng920-regs.c +++ b/target/arm/kunpeng920-regs.c @@ -9,6 +9,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "cpregs.h" +#include "cpu-features.h" int kunpeng920_update_registers(ARMCPU *cpu) { @@ -38,6 +39,13 @@ int kunpeng920_update_registers(ARMCPU *cpu) cpu->isar.id_aa64zfr0 = 0x100000100000; cpu->ctr = 0xb4448004; + /* + * cpu->prop_pauth is initialized in aarch64_host_initfn. + * After the register value is updated, cpu->prop_pauth needs + * to be updated. + */ + cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); + /* * MIDR/REVIDR/AIDR are invariant registers and not writable. * Ignore any differences between HIP09、HIP10 and HIP12 for now. -- 2.33.0
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