virt inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/ICVB8V CVE: NA -------------------------------- Add the migration of GICR_INMIR0. vNMI migration for SPI is not supported, only supports SGI and PPI in guest. Sign-off-by: Jinqian Yang <yangjinqian1@huawei.com> --- hw/intc/arm_gicv3_common.c | 2 ++ hw/intc/arm_gicv3_kvm.c | 5 +++++ hw/intc/gicv3_internal.h | 1 + include/hw/intc/arm_gicv3_common.h | 1 + 4 files changed, 9 insertions(+) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 5667d9f40b..f566080836 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -183,6 +183,7 @@ static const VMStateDescription vmstate_gicv3_cpu = { VMSTATE_UINT32(edge_trigger, GICv3CPUState), VMSTATE_UINT32(gicr_igrpmodr0, GICv3CPUState), VMSTATE_UINT32(gicr_nsacr, GICv3CPUState), + VMSTATE_UINT32(gicr_inmir0, GICv3CPUState), VMSTATE_UINT8_ARRAY(gicr_ipriorityr, GICv3CPUState, GIC_INTERNAL), VMSTATE_UINT64_ARRAY(icc_ctlr_el1, GICv3CPUState, 2), VMSTATE_UINT64(icc_pmr_el1, GICv3CPUState), @@ -554,6 +555,7 @@ static void arm_gicv3_common_reset_hold(Object *obj) cs->edge_trigger = 0xffff; cs->gicr_igrpmodr0 = 0; cs->gicr_nsacr = 0; + cs->gicr_inmir0 = 0; memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr)); cs->hppi.prio = 0xff; diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index dd2a60fa20..a293c04690 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -397,6 +397,9 @@ static void kvm_arm_gicv3_put(GICv3State *s) reg = c->gicr_iactiver0; kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, true); + reg = c->gicr_inmir0; + kvm_gicr_access(s, GICR_INMIR0, ncpu, ®, true); + for (i = 0; i < GIC_INTERNAL; i += 4) { reg = c->gicr_ipriorityr[i] | (c->gicr_ipriorityr[i + 1] << 8) | @@ -561,6 +564,8 @@ static void kvm_arm_gicv3_get(GICv3State *s) c->gicr_ipendr0 = reg; kvm_gicr_access(s, GICR_ISACTIVER0, ncpu, ®, false); c->gicr_iactiver0 = reg; + kvm_gicr_access(s, GICR_INMIR0, ncpu, ®, false); + c->gicr_inmir0 = reg; for (i = 0; i < GIC_INTERNAL; i += 4) { kvm_gicr_access(s, GICR_IPRIORITYR + i, ncpu, ®, false); diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h index 0bed0f6e2a..2b982716d6 100644 --- a/hw/intc/gicv3_internal.h +++ b/hw/intc/gicv3_internal.h @@ -109,6 +109,7 @@ #define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04) #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00) #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00) +#define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80) /* VLPI redistributor registers, offsets from VLPI_base */ #define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index b5f8ba17ff..8a5b8ae648 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -173,6 +173,7 @@ struct GICv3CPUState { uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */ uint32_t gicr_igrpmodr0; uint32_t gicr_nsacr; + uint32_t gicr_inmir0; uint8_t gicr_ipriorityr[GIC_INTERNAL]; /* VLPI_base page registers */ uint64_t gicr_vpropbaser; -- 2.33.0