------------------ Original ------------------ From: "Lorenzo Pieralisi" <email@example.com>; Date: Sat, Dec 17, 2022 00:14 AM To: "Zhangfei Gao"<firstname.lastname@example.org>; Cc: "Joyce Qi"<email@example.com>;"jean-philippe"<firstname.lastname@example.org>;"linaro-open-discussions"<email@example.com>;"linux"<firstname.lastname@example.org>; Subject: Re: [Linaro-open-discussions] Re: Linaro-open-discussions Digest, Vol 25, Issue 3
On Thu, Oct 27, 2022 at 12:06:59PM +0800, Zhangfei Gao wrote: > Hi, Lorenzo > > When we debug vsva, sva on guest with 2-stage translation, > we found tlb miss impact performance a lot, with Jean's help. > > Currently we are using huge page feature in glibc to overcome this issue. > With huge page, vsva in guest can achieve comparable performance as sva in > host. > > More details: https://docs.qq.com/doc/DRXlpQmpTSlBZTGZZ > Will do some > > Basically we are using two optimization methods/ > host sva: using memset fist to overcome io page fault, since cpu alloc > physical memory is much faster than smmu. > guest vsva: using huge page to overcome tlbmiss. > > The customer are asking whether (next version) silicon (smmu) can do some > help to concur tlb miss issue or io page fault issue.
I can bring this up with the SMMU architect - thank you for taking time to describe the use cases and SW you are deploying.
> If so, software can be simpler. > Any suggestions?
Talking to SMMU architects - there is not much SW can do other than what you are doing already.
> Thanks > > > On 2022/10/20 下午8:47, Joyce Qi via Linaro-open-discussions wrote: > > Hi Jonathan,Lorenzo,all, > > > > Do we have any topic to sync on our LOD meeting next week? > > > > Thanks:) > > Joyce > > > > > > >