Re: [PATCH RESEND OLK-5.10 1/3] coresight: etm4x: Modify core-commit to avoid HiSilicon ETM overflow

On 2022/2/21 11:43, Qi Liu wrote:

mainline inclusion from mainline-v5.10-rc7

你这个版本号不对啊，当前 openEuler 内核是 5.10 的 base，你这补丁怎么可能来自 5.10-rc7

commit e72550928ff0 category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I4UA33 CVE: NA

Reference: https://lore.kernel.org/r/20201208182651.1597945-4-mathieu.poirier@linaro.or...

---

The ETM device can't keep up with the core pipeline when cpu core is at full speed. This may cause overflow within core and its ETM. This is a common phenomenon on ETM devices.

On HiSilicon Hip08 platform, a specific feature is added to set core pipeline. So commit rate can be reduced manually to avoid ETM overflow.

Reviewed-by: Suzuki K Poulose suzuki.poulose@arm.com Signed-off-by: Qi Liu liuqi115@huawei.com [Modified changelog title and Kconfig description] Signed-off-by: Mathieu Poirier mathieu.poirier@linaro.org Link: https://lore.kernel.org/r/20201208182651.1597945-4-mathieu.poirier@linaro.or... Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org Signed-off-by: Qi Liu liuqi115@huawei.com

---

drivers/hwtracing/coresight/Kconfig | 8 ++ .../coresight/coresight-etm4x-core.c | 98 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-etm4x.h | 8 ++ 3 files changed, 114 insertions(+)

diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index c1198245461d..7b44ba22cbe1 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -110,6 +110,14 @@ config CORESIGHT_SOURCE_ETM4X To compile this driver as a module, choose M here: the module will be called coresight-etm4x.

+config ETM4X_IMPDEF_FEATURE

• bool "Control implementation defined overflow support in ETM 4.x driver"
• depends on CORESIGHT_SOURCE_ETM4X
• help

•  This control provides implementation define control for CoreSight
  

•  ETM 4.x tracer module that can't reduce commit rate automatically.
  

•  This avoids overflow between the ETM tracer module and the cpu core.
  

config CORESIGHT_STM tristate "CoreSight System Trace Macrocell driver" depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 74d3e2fe43d4..02d0b92cf510 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -3,6 +3,7 @@

• Copyright (c) 2014, The Linux Foundation. All rights reserved.

*/

+#include <linux/bitops.h> #include <linux/kernel.h> #include <linux/moduleparam.h> #include <linux/init.h> @@ -28,7 +29,9 @@ #include <linux/perf_event.h> #include <linux/pm_runtime.h> #include <linux/property.h>

#include <asm/sections.h> +#include <asm/sysreg.h> #include <asm/local.h> #include <asm/virt.h>

@@ -103,6 +106,97 @@ struct etm4_enable_arg { int rc; };

+#ifdef CONFIG_ETM4X_IMPDEF_FEATURE

+#define HISI_HIP08_AMBA_ID 0x000b6d01 +#define ETM4_AMBA_MASK 0xfffff +#define HISI_HIP08_CORE_COMMIT_MASK 0x3000 +#define HISI_HIP08_CORE_COMMIT_SHIFT 12 +#define HISI_HIP08_CORE_COMMIT_FULL 0b00 +#define HISI_HIP08_CORE_COMMIT_LVL_1 0b01 +#define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5)

+struct etm4_arch_features {

• void (*arch_callback)(bool enable);

+};

+static bool etm4_hisi_match_pid(unsigned int id) +{

• return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;

+}

+static void etm4_hisi_config_core_commit(bool enable) +{

• u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :

•     HISI_HIP08_CORE_COMMIT_FULL;
  

• u64 val;
• /*

• * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
  

• * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
  

• * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
  

• * speed(minimun value). So bit 12 and 13 should be cleared together.
  

• */
  

• val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
• val &= ~HISI_HIP08_CORE_COMMIT_MASK;
• val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
• write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);

+}

+static struct etm4_arch_features etm4_features[] = {

• [ETM4_IMPDEF_HISI_CORE_COMMIT] = {

• .arch_callback = etm4_hisi_config_core_commit,
  

• },
• {},

+};

+static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) +{

• struct etm4_arch_features *ftr;
• int bit;
• for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {

• ftr = &etm4_features[bit];
  

• if (ftr->arch_callback)
  

• 	ftr->arch_callback(true);
  

• }

+}

+static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) +{

• struct etm4_arch_features *ftr;
• int bit;
• for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {

• ftr = &etm4_features[bit];
  

• if (ftr->arch_callback)
  

• 	ftr->arch_callback(false);
  

• }

+}

+static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,

• 		      unsigned int id)
  

+{

• if (etm4_hisi_match_pid(id))

• set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
  

+} +#else +static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) +{ +}

+static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) +{ +}

+static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,

• 		     unsigned int id)
  

+{ +} +#endif /* CONFIG_ETM4X_IMPDEF_FEATURE */

static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; @@ -110,6 +204,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) struct device *etm_dev = &drvdata->csdev->dev;

CS_UNLOCK(drvdata->base);

• etm4_enable_arch_specific(drvdata);

  etm4_os_unlock(drvdata);

@@ -480,6 +575,7 @@ static void etm4_disable_hw(void *info) int i;

CS_UNLOCK(drvdata->base);

• etm4_disable_arch_specific(drvdata);

  if (!drvdata->skip_power_up) { /* power can be removed from the trace unit now */

@@ -1563,6 +1659,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) drvdata->boot_enable = true; }

• etm4_check_arch_features(drvdata, id->id);
• return 0;

}

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index eefc7371c6c4..3dd3e0633328 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -8,6 +8,7 @@

#include <asm/local.h> #include <linux/spinlock.h> +#include <linux/types.h> #include "coresight-priv.h"

/* @@ -203,6 +204,11 @@ /* Interpretation of resource numbers change at ETM v4.3 architecture */ #define ETM4X_ARCH_4V3 0x43

+enum etm_impdef_type {

• ETM4_IMPDEF_HISI_CORE_COMMIT,
• ETM4_IMPDEF_FEATURE_MAX,

+};

/**

• struct etmv4_config - configuration information related to an ETMv4
• @mode: Controls various modes supported by this ETM.

@@ -415,6 +421,7 @@ struct etmv4_save_state {

• @state_needs_restore: True when there is context to restore after PM exit
• @skip_power_up: Indicates if an implementation can skip powering up

•    the trace unit.
  

• • @arch_features: Bitmap of arch features of etmv4 devices.
  */

struct etmv4_drvdata { void __iomem *base; @@ -463,6 +470,7 @@ struct etmv4_drvdata { struct etmv4_save_state *save_state; bool state_needs_restore; bool skip_power_up;

• DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);

};

/* Address comparator access types */