[PATCH OLK-6.6 2/2] Coda feature

1 Aug 2024

From: JunBin Li lijunbin4@huawei.com
virtcca inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IADD42
--------------------------------
virtCCA feature
Signed-off-by: JunBin Li lijunbin4@huawei.com
---
 arch/arm64/include/asm/kvm_tmi.h              |  81 +-
 arch/arm64/include/asm/kvm_tmm.h              |  23 +
 arch/arm64/kvm/mmu.c                          |  23 +
 arch/arm64/kvm/tmi.c                          | 140 ++-
 arch/arm64/kvm/virtcca_cvm.c                  | 181 +++-
 drivers/iommu/arm/arm-smmu-v3/Makefile        |   1 +
 drivers/iommu/arm/arm-smmu-v3/arm-s-smmu-v3.c | 808 ++++++++++++++++++
 drivers/iommu/arm/arm-smmu-v3/arm-s-smmu-v3.h | 160 ++++
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c   | 178 +++-
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h   |  16 +
 drivers/iommu/io-pgtable-arm.c                |  60 ++
 drivers/iommu/iommu.c                         |  11 +
 drivers/pci/access.c                          |  33 +
 drivers/pci/msi/msi.c                         |  90 +-
 drivers/vfio/pci/vfio_pci_core.c              |   5 +
 drivers/vfio/pci/vfio_pci_rdwr.c              |  61 ++
 drivers/vfio/vfio_iommu_type1.c               |  17 +
 drivers/vfio/vfio_main.c                      |  18 +
 include/linux/iommu.h                         |   9 +
 include/linux/iopoll.h                        |  38 +
 include/linux/pci.h                           |   4 +
 include/linux/vfio.h                          |   5 +
 include/uapi/linux/vfio.h                     |   5 +
 virt/kvm/vfio.c                               | 122 ++-
 virt/kvm/vfio.h                               |  10 +
 25 files changed, 2082 insertions(+), 17 deletions(-)
 create mode 100644 drivers/iommu/arm/arm-smmu-v3/arm-s-smmu-v3.c
 create mode 100644 drivers/iommu/arm/arm-smmu-v3/arm-s-smmu-v3.h

diff --git a/arch/arm64/include/asm/kvm_tmi.h b/arch/arm64/include/asm/kvm_tmi.h
index fc4fe9a711..69bf908f9b 100644
--- a/arch/arm64/include/asm/kvm_tmi.h
+++ b/arch/arm64/include/asm/kvm_tmi.h
@@ -11,8 +11,6 @@
 #include <linux/virtio_ring.h>
 #include <asm/sysreg.h>
-#define GRANULE_SIZE		4096
-
 #define NO_NUMA			0 /* numa bitmap */
#define TMM_TTT_LEVEL_2 2
@@ -68,6 +66,39 @@ struct tmi_tec_params {
    uint64_t ram_size;
 };
+struct tmi_smmu_ste_params {
+	uint64_t ns_src;     /* non-secure STE source address */
+	uint64_t sid;        /* stream id */
+	uint64_t smmu_id;    /* smmu id */
+};
+
+struct tmi_smmu_cfg_params {
+	uint64_t smmu_id;
+	uint64_t ioaddr;
+	uint8_t strtab_base_RA_bit : 1;
+	uint8_t q_base_RA_WA_bit : 1;
+	uint8_t is_cmd_queue : 1;
+};
+
+#define TMI_SMMU_CMD_QUEUE  1
+#define TMI_SMMU_EVT_QUEUE  2
+struct tmi_smmu_queue_params {
+	uint64_t ns_src;     /* non-secure queue source address */
+	uint64_t smmu_base_addr;       /* smmu base address */
+	uint64_t size;       /* queue size */
+	uint64_t smmu_id;    /* smmu id */
+	uint64_t type;       /* cmdq or evtq */
+};
+
+#define MAX_DEV_PER_PORT 256
+struct tmi_dev_delegate_params {
+	/* BDF of PCIe root bus, F=0. BD are used to calculate APB base and port number. */
+	uint16_t root_bd;
+	uint16_t num_dev; /* number of attachable devices */
+	uint32_t _reserved; /* padding for 64-bit alignment */
+	uint16_t devs[MAX_DEV_PER_PORT]; /* BDF of each attachable device */
+};
+
 #define TEC_ENTRY_FLAG_EMUL_MMIO		(1UL << 0U)
 #define TEC_ENTRY_FLAG_INJECT_SEA		(1UL << 1U)
 #define TEC_ENTRY_FLAG_TRAP_WFI		(1UL << 2U)
@@ -202,6 +233,21 @@ struct tmi_tec_run {
 #define TMI_FNUM_TTT_UNMAP_RANGE		U(0x26E)
 #define TMI_FNUM_INF_TEST              U(0x270)
+#define TMI_FNUM_SMMU_QUEUE_CREATE		U(0x277)
+#define TMI_FNUM_SMMU_QUEUE_WRITE		U(0x278)
+#define TMI_FNUM_SMMU_STE_CREATE		U(0x279)
+#define TMI_FNUM_MMIO_MAP				U(0x27A)
+#define TMI_FNUM_MMIO_UNMAP				U(0x27B)
+#define TMI_FNUM_MMIO_WRITE				U(0x27C)
+#define TMI_FNUM_MMIO_READ				U(0x27D)
+#define TMI_FNUM_DEV_DELEGATE			U(0x27E)
+#define TMI_FNUM_DEV_ATTACH				U(0x27F)
+#define TMI_FNUM_HANDLE_S_EVTQ			U(0x280)
+#define TMI_FNUM_SMMU_DEVICE_RESET		U(0x281)
+#define TMI_FNUM_SMMU_WRITE				U(0x282)
+#define TMI_FNUM_SMMU_READ				U(0x283)
+#define TMI_FNUM_SMMU_PCIE_CORE_CHECK	U(0x284)
+
 /* TMI SMC64 PIDs handled by the SPMD */
 #define TMI_TMM_VERSION_REQ			TMI_FID(SMC_64, TMI_FNUM_VERSION_REQ)
 #define TMI_TMM_DATA_CREATE			TMI_FID(SMC_64, TMI_FNUM_DATA_CREATE)
@@ -220,6 +266,21 @@ struct tmi_tec_run {
 #define TMI_TMM_TTT_UNMAP_RANGE			TMI_FID(SMC_64, TMI_FNUM_TTT_UNMAP_RANGE)
 #define TMI_TMM_INF_TEST                TMI_FID(SMC_64, TMI_FNUM_INF_TEST)
+#define TMI_TMM_SMMU_QUEUE_CREATE		TMI_FID(SMC_64, TMI_FNUM_SMMU_QUEUE_CREATE)
+#define TMI_TMM_SMMU_QUEUE_WRITE		TMI_FID(SMC_64, TMI_FNUM_SMMU_QUEUE_WRITE)
+#define TMI_TMM_SMMU_STE_CREATE			TMI_FID(SMC_64, TMI_FNUM_SMMU_STE_CREATE)
+#define TMI_TMM_MMIO_MAP				TMI_FID(SMC_64, TMI_FNUM_MMIO_MAP)
+#define TMI_TMM_MMIO_UNMAP				TMI_FID(SMC_64, TMI_FNUM_MMIO_UNMAP)
+#define TMI_TMM_MMIO_WRITE				TMI_FID(SMC_64, TMI_FNUM_MMIO_WRITE)
+#define TMI_TMM_MMIO_READ				TMI_FID(SMC_64, TMI_FNUM_MMIO_READ)
+#define TMI_TMM_DEV_DELEGATE			TMI_FID(SMC_64, TMI_FNUM_DEV_DELEGATE)
+#define TMI_TMM_DEV_ATTACH				TMI_FID(SMC_64, TMI_FNUM_DEV_ATTACH)
+#define TMI_TMM_HANDLE_S_EVTQ			TMI_FID(SMC_64, TMI_FNUM_HANDLE_S_EVTQ)
+#define TMI_TMM_SMMU_DEVICE_RESET		TMI_FID(SMC_64, TMI_FNUM_SMMU_DEVICE_RESET)
+#define TMI_TMM_SMMU_WRITE				TMI_FID(SMC_64, TMI_FNUM_SMMU_WRITE)
+#define TMI_TMM_SMMU_READ				TMI_FID(SMC_64, TMI_FNUM_SMMU_READ)
+#define TMI_TMM_SMMU_PCIE_CORE_CHECK	TMI_FID(SMC_64, TMI_FNUM_SMMU_PCIE_CORE_CHECK)
+
 #define TMI_ABI_VERSION_GET_MAJOR(_version) ((_version) >> 16)
 #define TMI_ABI_VERSION_GET_MINOR(_version) ((_version) & 0xFFFF)
@@ -321,6 +382,22 @@ u64 tmi_ttt_map_range(u64 rd, u64 map_addr, u64 size, u64 cur_node, u64 target_n
 u64 tmi_ttt_unmap_range(u64 rd, u64 map_addr, u64 size, u64 node_id);
 u64 tmi_mem_info_show(u64 mem_info_addr);
+u64 va_to_pa(void *addr);
+u64 tmi_smmu_queue_create(u64 params_ptr);
+u64 tmi_smmu_queue_write(uint64_t cmd0, uint64_t cmd1, u64 smmu_id);
+u64 tmi_smmu_ste_create(u64 params_ptr);
+u64 tmi_mmio_map(u64 rd, u64 map_addr, u64 level, u64 ttte);
+u64 tmi_mmio_unmap(u64 rd, u64 map_addr, u64 level);
+u64 tmi_mmio_write(u64 addr, u64 val, u64 bits, u64 dev_num);
+u64 tmi_mmio_read(u64 addr, u64 bits, u64 dev_num);
+u64 tmi_dev_delegate(u64 params);
+u64 tmi_dev_attach(u64 vdev, u64 rd, u64 smmu_id);
+u64 tmi_handle_s_evtq(u64 smmu_id);
+u64 tmi_smmu_device_reset(u64 params);
+u64 tmi_smmu_pcie_core_check(u64 smmu_base);
+u64 tmi_smmu_write(u64 smmu_base, u64 reg_offset, u64 val, u64 bits);
+u64 tmi_smmu_read(u64 smmu_base, u64 reg_offset, u64 bits);
+
 void kvm_cvm_vcpu_put(struct kvm_vcpu *vcpu);
 int kvm_load_user_data(struct kvm *kvm, unsigned long arg);
 unsigned long cvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu,
diff --git a/arch/arm64/include/asm/kvm_tmm.h b/arch/arm64/include/asm/kvm_tmm.h
index 96532ca8fd..c87e43e794 100644
--- a/arch/arm64/include/asm/kvm_tmm.h
+++ b/arch/arm64/include/asm/kvm_tmm.h
@@ -7,6 +7,9 @@
#include <uapi/linux/kvm.h>
+#define CVM_MSI_ORIG_IOVA 0x8000000
+#define CVM_MSI_IOVA_OFFSET (-0x1000000)
+
 enum virtcca_cvm_state {
    CVM_STATE_NONE = 1,
    CVM_STATE_NEW,
@@ -44,6 +47,7 @@ struct cvm {
    u64 initrd_size;
    u64 ram_size;
    struct kvm_numa_info numa_info;
+	struct list_head list;
    struct tmi_cvm_params *params;
    bool is_cvm;
 };
@@ -59,6 +63,7 @@ struct virtcca_cvm {
    u64 ram_size;
    struct kvm_numa_info numa_info;
    struct tmi_cvm_params *params;
+	bool is_mapped;
 };
/*
@@ -70,6 +75,13 @@ struct virtcca_cvm_tec {
    void *tec_run;
 };
+struct cvm_ttt_addr {
+	struct list_head list;
+	u64 addr;
+};
+
+struct iommu_group {};
+
 int kvm_init_tmm(void);
 int kvm_cvm_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap);
 void kvm_destroy_cvm(struct kvm *kvm);
@@ -83,9 +95,20 @@ int cvm_psci_complete(struct kvm_vcpu *calling, struct kvm_vcpu *target);
void kvm_cvm_unmap_destroy_range(struct kvm *kvm);
+int kvm_cvm_map_range(struct kvm *kvm);
+int cvm_arm_smmu_domain_set_kvm(struct iommu_group *group);
+int kvm_cvm_map_unmap_ipa_range(struct kvm *kvm, phys_addr_t ipa_base, phys_addr_t pa,
+	unsigned long map_size, uint32_t is_map);
+int kvm_cvm_map_ipa_mmio(struct kvm *kvm, phys_addr_t ipa_base,
+	phys_addr_t pa, unsigned long map_size);
+
 #define CVM_TTT_BLOCK_LEVEL	2
 #define CVM_TTT_MAX_LEVEL	3
+#define CVM_MAP_IPA_RAM	1
+#define CVM_MAP_IPA_SMMU	2
+#define CVM_MAP_IPA_UNPROTECTED	4
+
 #define CVM_PAGE_SHIFT		12
 #define CVM_PAGE_SIZE		BIT(CVM_PAGE_SHIFT)
 #define CVM_TTT_LEVEL_SHIFT(l)	\
diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index 15c68b3c85..1d034117a4 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -1392,6 +1392,23 @@ static bool kvm_vma_mte_allowed(struct vm_area_struct *vma)
    return vma->vm_flags & VM_MTE_ALLOWED;
 }
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+static int kvm_cvm_map_ipa(struct kvm *kvm, phys_addr_t ipa, kvm_pfn_t pfn,
+	unsigned long map_size, enum kvm_pgtable_prot prot)
+{
+	struct page *dst_page = pfn_to_page(pfn);
+	phys_addr_t dst_phys = page_to_phys(dst_page);
+
+	if (WARN_ON(!(prot & KVM_PGTABLE_PROT_W)))
+		return -EFAULT;
+
+	if (prot & KVM_PGTABLE_PROT_DEVICE)
+		return kvm_cvm_map_ipa_mmio(kvm, ipa, dst_phys, map_size);
+
+	return 0;
+}
+#endif
+
 static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
    		  struct kvm_memory_slot *memslot, unsigned long hva,
    		  unsigned long fault_status)
@@ -1602,6 +1619,12 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
    				     memcache,
    				     KVM_PGTABLE_WALK_HANDLE_FAULT |
    				     KVM_PGTABLE_WALK_SHARED);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (kvm_is_virtcca_cvm(kvm)) {
+		ret = kvm_cvm_map_ipa(kvm, fault_ipa, pfn, vma_pagesize, prot);
+		WARN_ON(ret);
+	}
+#endif
/* Mark the page dirty only if the fault is handled successfully */
    if (writable && !ret) {
diff --git a/arch/arm64/kvm/tmi.c b/arch/arm64/kvm/tmi.c
index c1f22139d7..262bd2daa5 100644
--- a/arch/arm64/kvm/tmi.c
+++ b/arch/arm64/kvm/tmi.c
@@ -6,6 +6,30 @@
 #include <asm/kvm_tmi.h>
 #include <asm/memory.h>
+u64 va_to_pa(void *addr)
+{
+	uint64_t pa, par_el1;
+
+	asm volatile(
+		"AT S1E1W, %0\n"
+		::"r"((uint64_t)(addr))
+	);
+	isb();
+	asm volatile(
+		"mrs %0, par_el1\n"
+		:"=r"(par_el1)
+	);
+
+	pa = ((uint64_t)(addr) & (PAGE_SIZE - 1)) |
+		(par_el1 & ULL(0x000ffffffffff000));
+
+	if (par_el1 & UL(1 << 0))
+		return (uint64_t)(addr);
+	else
+		return pa;
+}
+EXPORT_SYMBOL(va_to_pa);
+
 u64 tmi_version(void)
 {
    struct arm_smccc_res res;
@@ -138,4 +162,118 @@ u64 tmi_tmm_inf_test(u64 x1, u64 x2, u64 x3, u64 x4, u64 x5)
    arm_smccc_1_1_smc(TMI_TMM_INF_TEST, x1, vttbr_el2_pa, cvm_params_pa, tec_params_pa, x5, &res);
    return res.a1;
 }
-EXPORT_SYMBOL_GPL(tmi_tmm_inf_test);
\ No newline at end of file
+EXPORT_SYMBOL_GPL(tmi_tmm_inf_test);
+
+u64 tmi_smmu_queue_create(u64 params_ptr)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_SMMU_QUEUE_CREATE, params_ptr, &res);
+	return res.a1;
+}
+
+u64 tmi_smmu_queue_write(uint64_t cmd0, uint64_t cmd1, u64 smmu_id)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_SMMU_QUEUE_WRITE, cmd0, cmd1, smmu_id, &res);
+	return res.a1;
+}
+
+u64 tmi_smmu_ste_create(u64 params_ptr)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_SMMU_STE_CREATE, params_ptr, &res);
+	return res.a1;
+}
+
+u64 tmi_mmio_map(u64 rd, u64 map_addr, u64 level, u64 ttte)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_MMIO_MAP, rd, map_addr, level, ttte, &res);
+	return res.a1;
+}
+
+u64 tmi_mmio_unmap(u64 rd, u64 map_addr, u64 level)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_MMIO_UNMAP, rd, map_addr, level, &res);
+	return res.a1;
+}
+
+u64 tmi_mmio_write(u64 addr, u64 val, u64 bits, u64 dev_num)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_MMIO_WRITE, addr, val, bits, dev_num, &res);
+	return res.a1;
+}
+EXPORT_SYMBOL(tmi_mmio_write);
+
+u64 tmi_mmio_read(u64 addr, u64 bits, u64 dev_num)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_MMIO_READ, addr, bits, dev_num, &res);
+	return res.a1;
+}
+EXPORT_SYMBOL(tmi_mmio_read);
+
+u64 tmi_dev_delegate(u64 params)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_DEV_DELEGATE, params, &res);
+	return res.a1;
+}
+
+u64 tmi_dev_attach(u64 vdev, u64 rd, u64 smmu_id)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_DEV_ATTACH, vdev, rd, smmu_id, &res);
+	return res.a1;
+}
+
+u64 tmi_handle_s_evtq(u64 smmu_id)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_HANDLE_S_EVTQ, smmu_id, &res);
+	return res.a1;
+}
+
+u64 tmi_smmu_device_reset(u64 params)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_SMMU_DEVICE_RESET, params, &res);
+	return res.a1;
+}
+
+u64 tmi_smmu_pcie_core_check(u64 smmu_base)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_SMMU_PCIE_CORE_CHECK, smmu_base, &res);
+	return res.a1;
+}
+
+u64 tmi_smmu_write(u64 smmu_base, u64 reg_offset, u64 val, u64 bits)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_SMMU_WRITE, smmu_base, reg_offset, val, bits, &res);
+	return res.a1;
+}
+
+u64 tmi_smmu_read(u64 smmu_base, u64 reg_offset, u64 bits)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_1_1_smc(TMI_TMM_SMMU_READ, smmu_base, reg_offset, bits, &res);
+	return res.a1;
+}
diff --git a/arch/arm64/kvm/virtcca_cvm.c b/arch/arm64/kvm/virtcca_cvm.c
index 367bbf4fa3..0d6c78cbe1 100644
--- a/arch/arm64/kvm/virtcca_cvm.c
+++ b/arch/arm64/kvm/virtcca_cvm.c
@@ -4,6 +4,7 @@
  */
 #include <linux/kvm_host.h>
 #include <linux/kvm.h>
+#include <linux/vfio.h>
 #include <asm/kvm_tmi.h>
 #include <asm/kvm_pgtable.h>
 #include <asm/kvm_emulate.h>
@@ -12,6 +13,7 @@
 #include <linux/arm-smccc.h>
 #include <kvm/arm_hypercalls.h>
 #include <kvm/arm_psci.h>
+#include "../virt/kvm/vfio.h"
/* Protects access to cvm_vmid_bitmap */
 static DEFINE_SPINLOCK(cvm_vmid_lock);
@@ -155,6 +157,27 @@ static u64 kvm_get_first_binded_numa_set(struct kvm *kvm)
    return NO_NUMA;
 }
+int cvm_arm_smmu_domain_set_kvm(struct iommu_group *group)
+{
+	struct arm_smmu_domain *arm_smmu_domain = NULL;
+	struct iommu_domain *domain;
+	struct kvm *kvm;
+
+	domain = iommu_group_get_domain(group);
+	if (!domain)
+		return -ENXIO;
+
+	arm_smmu_domain = to_smmu_domain(domain);
+	if (arm_smmu_domain->kvm)
+		return 0;
+
+	kvm = arm_smmu_get_kvm(arm_smmu_domain);
+	if (kvm && kvm_is_virtcca_cvm(kvm))
+		arm_smmu_domain->kvm = kvm;
+
+	return 0;
+}
+
 int kvm_arm_create_cvm(struct kvm *kvm)
 {
    int ret;
@@ -210,10 +233,18 @@ void kvm_destroy_cvm(struct kvm *kvm)
 {
    struct virtcca_cvm *cvm = kvm->arch.virtcca_cvm;
    uint32_t cvm_vmid;
+	struct arm_smmu_domain *arm_smmu_domain;
+	struct list_head smmu_domain_group_list;
if (!cvm)
    	return;
+	kvm_get_arm_smmu_domain(kvm, &smmu_domain_group_list);
+	list_for_each_entry(arm_smmu_domain, &smmu_domain_group_list, node) {
+		if (arm_smmu_domain->kvm && arm_smmu_domain->kvm == kvm)
+			arm_smmu_domain->kvm = NULL;
+	}
+
    cvm_vmid = cvm->cvm_vmid;
    kfree(cvm->params);
    cvm->params = NULL;
@@ -228,6 +259,7 @@ void kvm_destroy_cvm(struct kvm *kvm)
    if (!tmi_cvm_destroy(cvm->rd))
    	kvm_info("KVM has destroyed cVM: %d\n", cvm->cvm_vmid);
+	cvm->is_mapped = false;
    kfree(cvm);
    kvm->arch.virtcca_cvm = NULL;
 }
@@ -262,6 +294,133 @@ int kvm_cvm_create_ttt_levels(struct kvm *kvm, struct virtcca_cvm *cvm,
    return 0;
 }
+static int kvm_cvm_map_unmap_ipa_internal(struct kvm *kvm, phys_addr_t ipa_base,
+	phys_addr_t pa, unsigned long map_size, uint32_t is_map)
+{
+	struct virtcca_cvm *virtcca_cvm = (struct virtcca_cvm *)kvm->arch.virtcca_cvm;
+	phys_addr_t rd = virtcca_cvm->rd;
+	unsigned long ipa = ipa_base;
+	unsigned long phys = pa;
+	unsigned long size;
+	int map_level = 3;
+	int ret = 0;
+
+	for (size = 0; size < map_size; size += PAGE_SIZE) {
+		if (is_map)
+			ret = tmi_mmio_map(rd, ipa, CVM_TTT_MAX_LEVEL, phys);
+		else
+			ret = tmi_mmio_unmap(rd, ipa, CVM_TTT_MAX_LEVEL);
+
+		if (TMI_RETURN_STATUS(ret) == TMI_ERROR_TTT_WALK) {
+			/* Create missing TTTs and retry */
+			int level_fault = TMI_RETURN_INDEX(ret);
+
+			if (is_map) {
+				ret = kvm_cvm_create_ttt_levels(kvm, virtcca_cvm, ipa, level_fault,
+						CVM_TTT_MAX_LEVEL, NULL);
+				if (ret)
+					goto err;
+				ret = tmi_mmio_map(rd, ipa, CVM_TTT_MAX_LEVEL, phys);
+			} else {
+				ret = tmi_mmio_unmap(rd, ipa, level_fault);
+			}
+		}
+
+		WARN_ON(ret);
+		if (ret)
+			goto err;
+
+		if (size + PAGE_SIZE >= map_size)
+			break;
+		ipa += PAGE_SIZE;
+		phys += PAGE_SIZE;
+	}
+
+	if (WARN_ON(ret))
+		goto err;
+	return 0;
+
+err:
+	while (size > 0) {
+		phys -= PAGE_SIZE;
+		size -= PAGE_SIZE;
+		ipa -= PAGE_SIZE;
+
+		WARN_ON(tmi_data_destroy(rd, ipa, map_level));
+	}
+	return -ENXIO;
+}
+
+int kvm_cvm_map_unmap_ipa_range(struct kvm *kvm, phys_addr_t ipa_base,
+	phys_addr_t pa, unsigned long map_size, uint32_t is_map)
+{
+	return kvm_cvm_map_unmap_ipa_internal(kvm, ipa_base, pa, map_size, is_map);
+}
+
+int kvm_cvm_map_ipa_mmio(struct kvm *kvm, phys_addr_t ipa_base,
+	phys_addr_t pa, unsigned long map_size)
+{
+	struct virtcca_cvm *virtcca_cvm = (struct virtcca_cvm *)kvm->arch.virtcca_cvm;
+	phys_addr_t rd = virtcca_cvm->rd;
+	unsigned long ipa = ipa_base;
+	unsigned long phys = pa;
+	unsigned long size;
+	int map_level = 3;
+	int ret = 0;
+	gfn_t gfn;
+	kvm_pfn_t pfn;
+
+	if (WARN_ON(!IS_ALIGNED(ipa, map_size)))
+		return -EINVAL;
+
+	for (size = 0; size < map_size; size += PAGE_SIZE) {
+		ret = tmi_mmio_map(rd, ipa, CVM_TTT_MAX_LEVEL, phys);
+		if (ret == TMI_ERROR_TTT_CREATED) {
+			ret = 0;
+			goto label;
+		}
+		if (TMI_RETURN_STATUS(ret) == TMI_ERROR_TTT_WALK) {
+			/* Create missing TTTs and retry */
+			int level_fault = TMI_RETURN_INDEX(ret);
+
+			ret = kvm_cvm_create_ttt_levels(kvm, virtcca_cvm, ipa, level_fault,
+					CVM_TTT_MAX_LEVEL, NULL);
+
+			if (ret)
+				goto err;
+			ret = tmi_mmio_map(rd, ipa, CVM_TTT_MAX_LEVEL, phys);
+		}
+
+		WARN_ON(ret);
+		if (ret)
+			goto err;
+label:
+		if (size + PAGE_SIZE >= map_size)
+			break;
+
+		ipa += PAGE_SIZE;
+		gfn = gpa_to_gfn(ipa);
+		pfn = gfn_to_pfn(kvm, gfn);
+		kvm_set_pfn_accessed(pfn);
+		kvm_release_pfn_clean(pfn);
+		phys = (uint64_t)__pfn_to_phys(pfn);
+
+	}
+	if (WARN_ON(ret))
+		goto err;
+
+	return 0;
+
+err:
+	while (size > 0) {
+		phys -= PAGE_SIZE;
+		size -= PAGE_SIZE;
+		ipa -= PAGE_SIZE;
+		WARN_ON(tmi_data_destroy(rd, ipa, map_level));
+	}
+	return -ENXIO;
+}
+
 static int kvm_cvm_create_protected_data_page(struct kvm *kvm, struct virtcca_cvm *cvm,
    		unsigned long ipa, int level, struct page *src_page, u64 numa_set)
 {
@@ -521,7 +680,7 @@ static int kvm_tmm_config_cvm(struct kvm *kvm, struct kvm_enable_cap *cap)
    return r;
 }
-static int kvm_cvm_map_range(struct kvm *kvm)
+int kvm_cvm_map_range(struct kvm *kvm)
 {
    int ret;
    u64 curr_numa_set;
@@ -550,19 +709,37 @@ static int kvm_cvm_map_range(struct kvm *kvm)
    	}
    }
+	cvm->is_mapped = true;
    return ret;
 }
static int kvm_activate_cvm(struct kvm *kvm)
 {
+	int ret;
+	struct arm_smmu_domain *arm_smmu_domain;
+	struct list_head smmu_domain_group_list;
    struct virtcca_cvm *cvm = kvm->arch.virtcca_cvm;
if (virtcca_cvm_state(kvm) != CVM_STATE_NEW)
    	return -EINVAL;
-	if (kvm_cvm_map_range(kvm))
+	if (!cvm->is_mapped && kvm_cvm_map_range(kvm))
    	return -EFAULT;
+	if (kvm_get_arm_smmu_domain(kvm, &smmu_domain_group_list)) {
+		kvm_err("tmi activate cvm: get arm smmu domain failed!\n");
+		return -EFAULT;
+	}
+
+	list_for_each_entry(arm_smmu_domain, &smmu_domain_group_list, node) {
+		if (arm_smmu_domain && arm_smmu_domain->secure) {
+			ret = arm_smmu_tmi_dev_attach(arm_smmu_domain, kvm);
+			if (ret) {
+				return ret;
+			}
+		}
+	}
+
    if (tmi_cvm_activate(cvm->rd)) {
    	kvm_err("tmi_cvm_activate failed!\n");
    	return -ENXIO;
diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm-smmu-v3/Makefile
index 54feb1eccc..e4020cafcc 100644
--- a/drivers/iommu/arm/arm-smmu-v3/Makefile
+++ b/drivers/iommu/arm/arm-smmu-v3/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o
 arm_smmu_v3-objs-y += arm-smmu-v3.o
+arm_smmu_v3-objs-$(CONFIG_HISI_VIRTCCA_HOST) += arm-s-smmu-v3.o
 arm_smmu_v3-objs-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
 arm_smmu_v3-objs := $(arm_smmu_v3-objs-y)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-s-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-s-smmu-v3.c
new file mode 100644
index 0000000000..e3978967f1
--- /dev/null
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-s-smmu-v3.c
@@ -0,0 +1,808 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2024, The Linux Foundation. All rights reserved.
+ */
+#include <linux/crash_dump.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/iopoll.h>
+#include <linux/pci.h>
+#include <linux/hashtable.h>
+#include <asm/kvm_tmi.h>
+
+#include "arm-smmu-v3.h"
+#include "arm-s-smmu-v3.h"
+#include "../../dma-iommu.h"
+
+struct cc_dev_config {
+	u32	sid; /* BDF number of the device */
+	u32	vmid;
+	u32	root_bd; /* root bus and device number. Multiple sid can have the same root_bd. */
+	bool secure;
+	struct hlist_node node;
+};
+
+static bool g_smmu_id_map_init = false;
+
+static DEFINE_HASHTABLE(g_cc_dev_htable, MAX_CC_DEV_NUM_ORDER);
+static DECLARE_BITMAP(g_smmu_id_map, ARM_SMMU_MAX_IDS);
+
+/* Traverse pcie topology to find the root <bus,device> number
+ * return -1 if error
+ * return -1 if not pci device
+ */
+int get_root_bd(struct device *dev)
+{
+	struct pci_dev *pdev;
+
+	if (!dev_is_pci(dev))
+		return -1;
+	pdev = to_pci_dev(dev);
+	if (pdev->bus == NULL)
+		return -1;
+	while (pdev->bus->parent != NULL)
+		pdev = pdev->bus->self;
+
+	return pci_dev_id(pdev) & 0xfff8;
+}
+
+/* if dev is a bridge, get all it's children.
+ * if dev is a regular device, get itself.
+ */
+void get_child_devices_rec(struct pci_dev *dev, uint16_t *devs, int max_devs, int *ndev)
+{
+	struct pci_bus *bus = dev->subordinate;
+
+	if (bus) { /* dev is a bridge */
+		struct pci_dev *child;
+
+		list_for_each_entry(child, &bus->devices, bus_list) {
+			get_child_devices_rec(child, devs, max_devs, ndev);
+		}
+	} else { /* dev is a regular device */
+		uint16_t bdf = pci_dev_id(dev);
+		int i;
+		/* check if bdf is already in devs */
+		for (i = 0; i < *ndev; i++) {
+			if (devs[i] == bdf)
+				return;
+		}
+		/* check overflow */
+		if (*ndev >= max_devs) {
+			WARN_ON(1);
+			return;
+		}
+		devs[*ndev] = bdf;
+		*ndev = *ndev + 1;
+	}
+}
+
+/* get all devices which share the same root_bd as dev
+ * return 0 on failure
+ */
+int get_sibling_devices(struct device *dev, uint16_t *devs, int max_devs)
+{
+	int ndev = 0;
+	struct pci_dev *pdev;
+
+	if (!dev_is_pci(dev))
+		return ndev;
+
+	pdev = to_pci_dev(dev);
+	if (pdev->bus == NULL)
+		return ndev;
+
+	while (pdev->bus->parent != NULL)
+		pdev = pdev->bus->self;
+
+	get_child_devices_rec(pdev, devs, max_devs, &ndev);
+	return ndev;
+}
+
+void set_g_cc_dev(u32 sid, u32 vmid, u32 root_bd, bool secure)
+{
+	struct cc_dev_config *obj;
+
+	hash_for_each_possible(g_cc_dev_htable, obj, node, sid) {
+		if (obj->sid == sid) {
+			obj->vmid = vmid;
+			obj->root_bd = root_bd;
+			obj->secure = secure;
+			return;
+		}
+	}
+
+	obj = kzalloc(sizeof(*obj), GFP_KERNEL);
+	if (!obj) {
+		WARN_ON(1);
+		return;
+	}
+
+	obj->sid = sid;
+	obj->vmid = vmid;
+	obj->root_bd = root_bd;
+	obj->secure = secure;
+
+	hash_add(g_cc_dev_htable, &obj->node, sid);
+}
+
+void free_g_cc_dev_htable(void)
+{
+	int i;
+	struct cc_dev_config *obj;
+	struct hlist_node *tmp;
+
+	hash_for_each_safe(g_cc_dev_htable, i, tmp, obj, node) {
+		hash_del(&obj->node);
+		kfree(obj);
+	}
+}
+
+/* Has the root bus device number switched to secure? */
+bool is_cc_root_bd(u32 root_bd)
+{
+	int bkt;
+	struct cc_dev_config *obj;
+
+	hash_for_each(g_cc_dev_htable, bkt, obj, node) {
+		if (obj->root_bd == root_bd && obj->secure)
+			return true;
+	}
+
+	return false;
+}
+
+static bool is_cc_vmid(u32 vmid)
+{
+	int bkt;
+	struct cc_dev_config *obj;
+
+	hash_for_each(g_cc_dev_htable, bkt, obj, node) {
+		if (vmid > 0 && obj->vmid == vmid)
+			return true;
+	}
+
+	return false;
+}
+
+bool is_cc_dev(u32 sid)
+{
+	struct cc_dev_config *obj;
+
+	hash_for_each_possible(g_cc_dev_htable, obj, node, sid) {
+		if (obj != NULL && obj->sid == sid)
+			return obj->secure;
+	}
+
+	return false;
+}
+EXPORT_SYMBOL(is_cc_dev);
+
+void s_smmu_cmdq_need_forward(u64 cmd0, u64 cmd1, u64 *forward)
+{
+	u64 opcode = FIELD_GET(CMDQ_0_OP, cmd0);
+
+	switch (opcode) {
+	case CMDQ_OP_TLBI_EL2_ALL:
+	case CMDQ_OP_TLBI_NSNH_ALL:
+		*forward = 1;
+		break;
+	case CMDQ_OP_PREFETCH_CFG:
+	case CMDQ_OP_CFGI_CD:
+	case CMDQ_OP_CFGI_STE:
+	case CMDQ_OP_CFGI_CD_ALL:
+		*forward = (uint64_t)is_cc_dev(FIELD_GET(CMDQ_CFGI_0_SID, cmd0));
+		break;
+
+	case CMDQ_OP_CFGI_ALL:
+		*forward = 1;
+		break;
+	case CMDQ_OP_TLBI_NH_VA:
+	case CMDQ_OP_TLBI_S2_IPA:
+	case CMDQ_OP_TLBI_NH_ASID:
+	case CMDQ_OP_TLBI_S12_VMALL:
+		*forward = (uint64_t)is_cc_vmid(FIELD_GET(CMDQ_TLBI_0_VMID, cmd0));
+		break;
+	case CMDQ_OP_TLBI_EL2_VA:
+	case CMDQ_OP_TLBI_EL2_ASID:
+		*forward = 0;
+		break;
+	case CMDQ_OP_ATC_INV:
+		*forward = (uint64_t)is_cc_dev(FIELD_GET(CMDQ_ATC_0_SID, cmd0));
+		break;
+	case CMDQ_OP_PRI_RESP:
+		*forward = (uint64_t)is_cc_dev(FIELD_GET(CMDQ_PRI_0_SID, cmd0));
+		break;
+	case CMDQ_OP_RESUME:
+		*forward = (uint64_t)is_cc_dev(FIELD_GET(CMDQ_RESUME_0_SID, cmd0));
+		break;
+	case CMDQ_OP_CMD_SYNC:
+		*forward = 0;
+		break;
+	default:
+		*forward = 0;
+	}
+}
+
+void s_queue_write(struct arm_smmu_device *smmu, u64 *src, size_t n_dwords)
+{
+	u64 cmd0, cmd1;
+	u64 forward = 0;
+
+	if (smmu->id != ARM_SMMU_INVALID_ID) {
+		if (n_dwords == 2) {
+			cmd0 = cpu_to_le64(src[0]);
+			cmd1 = cpu_to_le64(src[1]);
+			s_smmu_cmdq_need_forward(cmd0, cmd1, &forward);
+
+			/* need forward queue command to TMM */
+			if (forward) {
+				if (tmi_smmu_queue_write(cmd0, cmd1, smmu->id))
+					pr_err("tmi_smmu_queue_write err!\n");
+			}
+		}
+	}
+}
+
+void arm_s_smmu_cmdq_write_entries(struct arm_smmu_device *smmu, u64 *cmds, int n)
+{
+	int i;
+
+	if (smmu->id != ARM_SMMU_INVALID_ID) {
+		for (i = 0; i < n; ++i) {
+			u64 *cmd = &cmds[i * CMDQ_ENT_DWORDS];
+
+			s_queue_write(smmu, cmd, CMDQ_ENT_DWORDS);
+		}
+	}
+}
+
+int arm_s_smmu_init_one_queue(struct arm_smmu_device *smmu,
+							  struct arm_smmu_queue *q,
+							  size_t qsz, const char *name)
+{
+	if (smmu->id != ARM_SMMU_INVALID_ID) {
+		struct tmi_smmu_queue_params *params_ptr = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
+
+		if (!params_ptr)
+			return -ENOMEM;
+
+		if (!strcmp(name, "cmdq")) {
+			params_ptr->ns_src = q->base_dma;
+			params_ptr->smmu_base_addr = smmu->ioaddr;
+			params_ptr->size = qsz;
+			params_ptr->smmu_id = smmu->id;
+			params_ptr->type = TMI_SMMU_CMD_QUEUE;
+			tmi_smmu_queue_create(__pa(params_ptr));
+		}
+
+		if (!strcmp(name, "evtq")) {
+			params_ptr->ns_src = q->base_dma;
+			params_ptr->smmu_base_addr = smmu->ioaddr;
+			params_ptr->size = qsz;
+			params_ptr->smmu_id = smmu->id;
+			params_ptr->type = TMI_SMMU_EVT_QUEUE;
+			tmi_smmu_queue_create(__pa(params_ptr));
+		}
+
+		kfree(params_ptr);
+	}
+
+	return 0;
+}
+
+int arm_smmu_write_s_reg_sync(struct arm_smmu_device *smmu, u32 val, u32 cmp_val,
+				   unsigned int reg_off, unsigned int ack_off)
+{
+	u32 reg;
+
+	if (tmi_smmu_write(smmu->ioaddr, reg_off, val, 32))
+		return -ENXIO;
+
+	return kvm_cvm_read_poll_timeout_atomic(tmi_smmu_read, reg, reg == cmp_val,
+				       1, ARM_SMMU_POLL_TIMEOUT_US, false,
+				       smmu->ioaddr, ack_off, 32);
+}
+
+int arm_smmu_update_s_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr)
+{
+	int ret;
+	u32 reg;
+
+	ret = kvm_cvm_read_poll_timeout_atomic(tmi_smmu_read, reg, !(reg & S_GBPA_UPDATE),
+				       1, ARM_SMMU_POLL_TIMEOUT_US, false,
+				       smmu->ioaddr, ARM_SMMU_S_GBPA, 32);
+	if (ret)
+		return ret;
+
+	reg &= ~clr;
+	reg |= set;
+
+	ret = tmi_smmu_write(smmu->ioaddr, ARM_SMMU_S_GBPA, reg | S_GBPA_UPDATE, 32);
+	if (ret)
+		return ret;
+
+	ret = kvm_cvm_read_poll_timeout_atomic(tmi_smmu_read, reg, !(reg & S_GBPA_UPDATE),
+			1, ARM_SMMU_POLL_TIMEOUT_US, false,
+			smmu->ioaddr, ARM_SMMU_S_GBPA, 32);
+	if (ret)
+		dev_err(smmu->dev, "S_GBPA not responding to update\n");
+	return ret;
+}
+
+irqreturn_t arm_smmu_s_evtq_thread(int irq, void *dev)
+{
+	struct arm_smmu_device *smmu = dev;
+
+	if (smmu->id != ARM_SMMU_INVALID_ID)
+		tmi_handle_s_evtq(smmu->id);
+
+	return IRQ_HANDLED;
+}
+
+irqreturn_t arm_smmu_s_gerror_handler(int irq, void *dev)
+{
+	u32 gerror, gerrorn, active;
+	u64 ret;
+	struct arm_smmu_device *smmu = dev;
+
+	ret = tmi_smmu_read(smmu->ioaddr, ARM_SMMU_S_GERROR, 32);
+	if (ret >> 32) {
+		dev_err(smmu->dev, "Get ARM_SMMU_S_GERROR register failed\n");
+		return IRQ_NONE;
+	}
+	gerror = (u32)ret;
+
+	ret = tmi_smmu_read(smmu->ioaddr, ARM_SMMU_S_GERRORN, 32);
+	if (ret >> 32) {
+		dev_err(smmu->dev, "Get ARM_SMMU_S_GERRORN register failed\n");
+		return IRQ_NONE;
+	}
+	gerrorn = (u32)ret;
+
+	active = gerror ^ gerrorn;
+	if (!(active & GERROR_ERR_MASK))
+		return IRQ_NONE; /* No errors pending */
+
+	dev_warn(smmu->dev,
+		 "unexpected secure global error reported, this could be serious, active %x\n",
+		 active);
+
+	if (active & GERROR_SFM_ERR) {
+		dev_err(smmu->dev, "device has entered Service Failure Mode!\n");
+		arm_s_smmu_device_disable(smmu);
+	}
+
+	if (active & GERROR_MSI_GERROR_ABT_ERR)
+		dev_warn(smmu->dev, "GERROR MSI write aborted\n");
+
+	if (active & GERROR_MSI_PRIQ_ABT_ERR)
+		dev_warn(smmu->dev, "PRIQ MSI write aborted\n");
+
+	if (active & GERROR_MSI_EVTQ_ABT_ERR)
+		dev_warn(smmu->dev, "EVTQ MSI write aborted\n");
+
+	if (active & GERROR_MSI_CMDQ_ABT_ERR)
+		dev_warn(smmu->dev, "CMDQ MSI write aborted\n");
+
+	if (active & GERROR_PRIQ_ABT_ERR)
+		dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n");
+
+	if (active & GERROR_EVTQ_ABT_ERR)
+		dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n");
+
+	if (active & GERROR_CMDQ_ERR)
+		dev_warn(smmu->dev, "CMDQ ERR\n");
+
+	if (tmi_smmu_write(smmu->ioaddr, ARM_SMMU_S_GERRORN, gerror, 32)) {
+		dev_err(smmu->dev, "SMMU write ARM_SMMU_S_GERRORN failed\n");
+		return IRQ_NONE;
+	}
+
+	return IRQ_HANDLED;
+}
+
+int arm_smmu_disable_s_irq(struct arm_smmu_device *smmu)
+{
+	int ret;
+
+	if (smmu->id != ARM_SMMU_INVALID_ID) {
+		ret = arm_smmu_write_s_reg_sync(smmu, 0, 0,
+			ARM_SMMU_S_IRQ_CTRL, ARM_SMMU_S_IRQ_CTRLACK);
+		if (ret) {
+			dev_err(smmu->dev, "failed to disable secure irqs\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int arm_smmu_enable_s_irq(struct arm_smmu_device *smmu, u32 irqen_flags)
+{
+	int ret;
+
+	if (smmu->id != ARM_SMMU_INVALID_ID) {
+		ret = arm_smmu_write_s_reg_sync(smmu, irqen_flags,
+			irqen_flags, ARM_SMMU_S_IRQ_CTRL, ARM_SMMU_S_IRQ_CTRLACK);
+		if (ret) {
+			dev_err(smmu->dev, "failed to enable irq for secure evtq\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+void arm_s_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)
+{
+	int irq, ret;
+
+	irq = smmu->s_evtq_irq;
+	if (irq && smmu->id != ARM_SMMU_INVALID_ID) {
+		ret = devm_request_threaded_irq(smmu->dev, irq, NULL,
+						arm_smmu_s_evtq_thread,
+						IRQF_ONESHOT,
+						"arm-smmu-v3-s_evtq", smmu);
+		if (ret < 0)
+			dev_warn(smmu->dev, "failed to enable s_evtq irq\n");
+	} else {
+		dev_warn(smmu->dev, "no s_evtq irq - events will not be reported!\n");
+	}
+
+	irq = smmu->s_gerr_irq;
+	if (irq && smmu->id != ARM_SMMU_INVALID_ID) {
+		ret = devm_request_irq(smmu->dev, irq, arm_smmu_s_gerror_handler,
+				       0, "arm-smmu-v3-s_gerror", smmu);
+		if (ret < 0)
+			dev_warn(smmu->dev, "failed to enable s_gerror irq\n");
+	} else {
+		dev_warn(smmu->dev, "no s_gerr irq - errors will not be reported!\n");
+	}
+}
+
+void arm_smmu_write_s_msi_msg(struct arm_smmu_device *smmu, phys_addr_t *cfg,
+							  struct msi_msg *msg, phys_addr_t doorbell)
+{
+	tmi_smmu_write((u64)smmu->ioaddr, cfg[0], doorbell, 64);
+	tmi_smmu_write((u64)smmu->ioaddr, cfg[1], msg->data, 32);
+	tmi_smmu_write((u64)smmu->ioaddr, cfg[2], ARM_SMMU_MEMATTR_DEVICE_nGnRE, 32);
+}
+
+void platform_get_s_irq_byname_optional(struct platform_device *pdev, struct arm_smmu_device *smmu)
+{
+	int irq;
+
+	if (smmu->id != ARM_SMMU_INVALID_ID) {
+		irq = platform_get_irq_byname_optional(pdev, "s_eventq");
+		if (irq > 0)
+			smmu->s_evtq_irq = irq;
+
+		irq = platform_get_irq_byname_optional(pdev, "s_gerror");
+		if (irq > 0)
+			smmu->s_gerr_irq = irq;
+	}
+}
+
+int arm_smmu_enable_secure(struct iommu_domain *domain)
+{
+	int ret = 0;
+	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
+
+	mutex_lock(&smmu_domain->init_mutex);
+	if (smmu_domain->smmu)
+		ret = -EPERM;
+	else
+		smmu_domain->secure = true;
+	mutex_unlock(&smmu_domain->init_mutex);
+
+	return ret;
+}
+
+u32 arm_smmu_tmi_dev_attach(struct arm_smmu_domain *arm_smmu_domain,
+	struct kvm *kvm)
+{
+	int ret = -1;
+	u64 cmd[CMDQ_ENT_DWORDS] = {0};
+	unsigned long flags;
+	int i, j;
+	struct arm_smmu_master *master;
+	struct virtcca_cvm *virtcca_cvm = (struct virtcca_cvm *)kvm->arch.virtcca_cvm;
+
+	spin_lock_irqsave(&arm_smmu_domain->devices_lock, flags);
+	list_for_each_entry(master, &arm_smmu_domain->devices, domain_head) {
+		if (master && master->num_streams >= 0) {
+			for (i = 0; i < master->num_streams; ++i) {
+				u32 sid = master->streams[i].id;
+
+				for (j = 0; j < i; j++)
+					if (master->streams[j].id == sid)
+						break;
+				if (j < i)
+					continue;
+				ret = tmi_dev_attach(sid, virtcca_cvm->rd, arm_smmu_domain->smmu->id);
+				if (ret) {
+					kvm_err("dev protected failed!\n");
+					ret = -ENXIO;
+					goto out;
+				}
+				cmd[0] |= FIELD_PREP(CMDQ_0_OP, CMDQ_OP_CFGI_STE);
+				cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, sid);
+				cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, true);
+				tmi_smmu_queue_write(cmd[0], cmd[1], arm_smmu_domain->smmu->id);
+			}
+		}
+	}
+
+out:
+	spin_unlock_irqrestore(&arm_smmu_domain->devices_lock, flags);
+	return ret;
+}
+
+int arm_smmu_secure_dev_ste_create(struct arm_smmu_device *smmu,
+	struct arm_smmu_master *master, u32 sid)
+{
+	struct tmi_smmu_ste_params *params_ptr;
+	struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
+	struct arm_smmu_strtab_l1_desc *desc = &cfg->l1_desc[sid >> STRTAB_SPLIT];
+
+	params_ptr = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
+	if (!params_ptr)
+		return -ENOMEM;
+
+	/* Sync Level 2 STE to TMM */
+	params_ptr->ns_src = desc->l2ptr_dma + ((sid & ((1 << STRTAB_SPLIT) - 1)) * STE_ENTRY_SIZE);
+	params_ptr->sid = sid;
+	params_ptr->smmu_id = smmu->id;
+
+	if (tmi_smmu_ste_create(__pa(params_ptr)) != 0)
+		dev_err(smmu->dev, "failed to create STE level 2");
+
+	kfree(params_ptr);
+
+	return 0;
+}
+
+int arm_smmu_secure_set_dev(struct arm_smmu_domain *smmu_domain, struct arm_smmu_master *master,
+	struct device *dev)
+{
+	int i, j;
+	u64 ret = 0;
+	uint16_t root_bd = get_root_bd(dev);
+
+	WARN_ON_ONCE(root_bd < 0);
+	if (!is_cc_root_bd(root_bd)) {
+		struct tmi_dev_delegate_params *params = kzalloc(
+			sizeof(struct tmi_dev_delegate_params), GFP_KERNEL);
+
+		params->root_bd = root_bd;
+		params->num_dev = get_sibling_devices(dev, params->devs, MAX_DEV_PER_PORT);
+		WARN_ON_ONCE(params->num_dev == 0);
+		pr_info("Delegate %d devices as %02x:%02x to secure\n",
+				params->num_dev, root_bd >> 8, (root_bd & 0xff) >> 3);
+		ret = tmi_dev_delegate(__pa(params));
+		if (!ret) {
+			for (i = 0; i < params->num_dev; i++)
+				set_g_cc_dev(params->devs[i], 0, root_bd, true);
+		}
+		kfree(params);
+	}
+
+	if (ret)
+		return ret;
+
+	for (i = 0; i < master->num_streams; ++i) {
+		u32 sid = master->streams[i].id;
+
+		for (j = 0; j < i; j++)
+			if (master->streams[j].id == sid)
+				break;
+		if (j < i)
+			continue;
+		WARN_ON_ONCE(!is_cc_dev(sid));
+		set_g_cc_dev(sid, smmu_domain->s2_cfg.vmid, root_bd, true);
+	}
+
+	return ret;
+}
+
+int arm_smmu_id_alloc(void)
+{
+	int idx;
+
+	do {
+		idx = find_first_zero_bit(g_smmu_id_map, ARM_SMMU_MAX_IDS);
+		if (idx == ARM_SMMU_MAX_IDS)
+			return -ENOSPC;
+	} while (test_and_set_bit(idx, g_smmu_id_map));
+
+	return idx;
+}
+
+void arm_smmu_id_free(int idx)
+{
+	if (idx != ARM_SMMU_INVALID_ID)
+		clear_bit(idx, g_smmu_id_map);
+}
+
+void arm_smmu_map_init(struct arm_smmu_device *smmu, resource_size_t ioaddr)
+{
+	if (!g_smmu_id_map_init) {
+		set_bit(0, g_smmu_id_map);
+		g_smmu_id_map_init = true;
+	}
+	smmu->ioaddr = ioaddr;
+
+	if (tmi_smmu_pcie_core_check(ioaddr))
+		smmu->id = arm_smmu_id_alloc();
+	else
+		smmu->id = ARM_SMMU_INVALID_ID;
+
+	hash_init(g_cc_dev_htable);
+}
+
+int arm_s_smmu_device_disable(struct arm_smmu_device *smmu)
+{
+	int ret = 0;
+
+	if (smmu->id != ARM_SMMU_INVALID_ID) {
+		ret = arm_smmu_write_s_reg_sync(smmu, 0, 0, ARM_SMMU_S_CR0, ARM_SMMU_S_CR0ACK);
+		if (ret) {
+			dev_err(smmu->dev, "failed to clear s_cr0\n");
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+int arm_s_smmu_device_reset(struct arm_smmu_device *smmu)
+{
+	int ret;
+	u64 rv;
+	u32 reg, enables;
+	struct tmi_smmu_cfg_params *params_ptr;
+
+	if (smmu->id == ARM_SMMU_INVALID_ID)
+		return 0;
+
+	rv = tmi_smmu_read(smmu->ioaddr, ARM_SMMU_S_CR0, 32);
+	if (rv >> 32)
+		return -ENXIO;
+
+	ret = (int)rv;
+	if (ret & S_CR0_SMMUEN) {
+		dev_warn(smmu->dev, "Secure SMMU currently enabled! Resetting...\n");
+		arm_smmu_update_s_gbpa(smmu, S_GBPA_ABORT, 0);
+	}
+
+	ret = arm_s_smmu_device_disable(smmu);
+	if (ret)
+		return ret;
+
+	/* CR1 (table and queue memory attributes) */
+	reg = FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) |
+	      FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) |
+	      FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) |
+	      FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) |
+	      FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) |
+	      FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB);
+
+	ret = tmi_smmu_write(smmu->ioaddr, ARM_SMMU_S_CR1, reg, 32);
+	if (ret)
+		return ret;
+
+	/* CR2 (random crap) */
+	reg = CR2_RECINVSID;
+
+	if (smmu->features & ARM_SMMU_FEAT_E2H)
+		reg |= CR2_E2H;
+
+	ret = tmi_smmu_write(smmu->ioaddr, ARM_SMMU_S_CR2, reg, 32);
+	if (ret)
+		return ret;
+
+	params_ptr = kzalloc(PAGE_SIZE, GFP_KERNEL_ACCOUNT);
+	if (!params_ptr)
+		return -ENOMEM;
+
+	params_ptr->is_cmd_queue = 1;
+	params_ptr->smmu_id = smmu->id;
+	params_ptr->ioaddr = smmu->ioaddr;
+	params_ptr->strtab_base_RA_bit =
+		(smmu->strtab_cfg.strtab_base >> S_STRTAB_BASE_RA_SHIFT) & 0x1;
+	params_ptr->q_base_RA_WA_bit =
+		(smmu->cmdq.q.q_base >> S_CMDQ_BASE_RA_SHIFT) & 0x1;
+	if (tmi_smmu_device_reset(__pa(params_ptr)) != 0) {
+		dev_err(smmu->dev, "failed to set s cmd queue regs\n");
+		return -ENXIO;
+	}
+
+	enables = CR0_CMDQEN;
+	ret = arm_smmu_write_s_reg_sync(smmu, enables, enables, ARM_SMMU_S_CR0,
+				      ARM_SMMU_S_CR0ACK);
+	if (ret) {
+		dev_err(smmu->dev, "failed to enable secure command queue\n");
+		return ret;
+	}
+
+	enables |= CR0_EVTQEN;
+
+	/* Secure event queue */
+	memset(params_ptr, 0, sizeof(struct tmi_smmu_ste_params));
+	params_ptr->is_cmd_queue = 0;
+	params_ptr->ioaddr = smmu->ioaddr;
+	params_ptr->smmu_id = smmu->id;
+	params_ptr->q_base_RA_WA_bit =
+		 (smmu->evtq.q.q_base >> S_EVTQ_BASE_WA_SHIFT) & 0x1;
+	params_ptr->strtab_base_RA_bit =
+		(smmu->strtab_cfg.strtab_base >> S_STRTAB_BASE_RA_SHIFT) & 0x1;
+	if (tmi_smmu_device_reset(__pa(params_ptr)) != 0) {
+		dev_err(smmu->dev, "failed to set s event queue regs");
+		return -ENXIO;
+	}
+
+	/* Enable secure eventq */
+	ret = arm_smmu_write_s_reg_sync(smmu, enables, enables, ARM_SMMU_S_CR0,
+					ARM_SMMU_S_CR0ACK);
+	if (ret) {
+		dev_err(smmu->dev, "failed to disable secure event queue\n");
+		return ret;
+	}
+
+	ret = arm_smmu_write_s_reg_sync(smmu, SMMU_S_INIT_INV_ALL, 0,
+		ARM_SMMU_S_INIT, ARM_SMMU_S_INIT);
+	if (ret) {
+		dev_err(smmu->dev, "failed to write S_INIT\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int arm_s_smmu_device_enable(struct arm_smmu_device *smmu,
+	u32 enables, bool bypass, bool disable_bypass)
+{
+	int ret = 0;
+
+	if (smmu->id != ARM_SMMU_INVALID_ID) {
+		/* Enable the SMMU interface, or ensure bypass */
+		if (!bypass || disable_bypass) {
+			enables |= CR0_SMMUEN;
+		} else {
+			ret = arm_smmu_update_s_gbpa(smmu, 0, S_GBPA_ABORT);
+			if (ret)
+				return ret;
+		}
+		/* Mask BIT1 and BIT4 which are RES0 in SMMU_S_CRO */
+		ret = arm_smmu_write_s_reg_sync(smmu, enables & ~SMMU_S_CR0_RESERVED,
+			enables & ~SMMU_S_CR0_RESERVED, ARM_SMMU_S_CR0, ARM_SMMU_S_CR0ACK);
+	}
+	return ret;
+}
+
+int arm_smmu_s_idr1_support_secure(struct arm_smmu_device *smmu)
+{
+	u32 ret;
+	u64 rv;
+
+	if (smmu->id != ARM_SMMU_INVALID_ID) {
+		rv = tmi_smmu_read(smmu->ioaddr, ARM_SMMU_S_IDR1, 32);
+		if (rv >> 32) {
+			dev_err(smmu->dev, "Get ARM_SMMU_S_IDR1 register failed!\n");
+			return -ENXIO;
+		}
+		ret = (u32)rv;
+		if (!(ret & S_IDR1_SECURE_IMPL)) {
+			dev_err(smmu->dev, "SMMUv3 does not implement secure state!\n");
+			return -ENXIO;
+		}
+
+		if (!(ret & S_IDR1_SEL2)) {
+			dev_err(smmu->dev, "SMMUv3: Secure stage2 translation not supported!\n");
+			return -ENXIO;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-s-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-s-smmu-v3.h
new file mode 100644
index 0000000000..fa2061d94a
--- /dev/null
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-s-smmu-v3.h
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2024, The Linux Foundation. All rights reserved.
+ */
+#ifndef _ARM_S_SMMU_V3_H
+#define _ARM_S_SMMU_V3_H
+
+#include <linux/platform_device.h>
+
+#define MAX_CC_DEV_NUM_ORDER 8
+#define STE_ENTRY_SIZE			0x40
+
+#define ARM_SMMU_MAX_IDS		(1 << 5)
+#define ARM_SMMU_INVALID_ID		ARM_SMMU_MAX_IDS
+
+/* Secure MMIO registers */
+#define ARM_SMMU_S_IDR0			0x8000
+#define S_IDR0_STALL_MODEL		GENMASK(25, 24)
+#define S_IDR0_ECMDQ			(1 << 31)
+#define S_IDR0_MSI			    (1 << 13)
+
+#define ARM_SMMU_S_IDR1			0x8004
+#define S_IDR1_SECURE_IMPL	    (1 << 31)
+#define S_IDR1_SEL2	            (1 << 29)
+#define S_IDR1_SIDSIZE			GENMASK(5, 0)
+
+#define ARM_SMMU_S_IDR3			0x800c
+#define S_IDR3_SAMS			    (1 << 6)
+
+#define ARM_SMMU_S_CR0		    0x8020
+#define S_CR0_SIF			    (1 << 9)
+#define S_CR0_NSSTALLD			(1 << 5)
+#define S_CR0_CMDQEN			(1 << 3)
+#define S_CR0_EVTQEN			(1 << 2)
+#define S_CR0_SMMUEN			(1 << 0)
+
+#define ARM_SMMU_S_CR0ACK		0x8024
+
+#define ARM_SMMU_S_CR1			0x8028
+#define S_CR1_TABLE_SH			GENMASK(11, 10)
+#define S_CR1_TABLE_OC			GENMASK(9, 8)
+#define S_CR1_TABLE_IC			GENMASK(7, 6)
+#define S_CR1_QUEUE_SH			GENMASK(5, 4)
+#define S_CR1_QUEUE_OC			GENMASK(3, 2)
+#define S_CR1_QUEUE_IC			GENMASK(1, 0)
+
+/* S_CR1 cacheability fields don't quite follow the usual TCR-style encoding */
+#define S_CR1_CACHE_NC			0
+#define S_CR1_CACHE_WB			1
+#define S_CR1_CACHE_WT			2
+
+#define ARM_SMMU_S_CR2			0x802c
+#define S_CR2_PTM				(1 << 2)
+#define S_CR2_RECINVSID			(1 << 1)
+#define S_CR2_E2H				(1 << 0)
+
+#define ARM_SMMU_S_INIT			U(0x803c)
+/* SMMU_S_INIT register fields */
+#define SMMU_S_INIT_INV_ALL		(1UL << 0)
+
+#define ARM_SMMU_S_GBPA			0x8044
+#define S_GBPA_UPDATE			(1 << 31)
+#define S_GBPA_ABORT			(1 << 20)
+
+#define ARM_SMMU_S_IRQ_CTRL		0x8050
+#define S_IRQ_CTRL_EVTQ_IRQEN		(1 << 2)
+#define S_IRQ_CTRL_GERROR_IRQEN		(1 << 0)
+
+#define ARM_SMMU_S_IRQ_CTRLACK		0x8054
+
+#define ARM_SMMU_S_GERROR			0x8060
+#define S_GERROR_SFM_ERR			(1 << 8)
+#define S_GERROR_MSI_GERROR_ABT_ERR	(1 << 7)
+#define S_GERROR_MSI_EVTQ_ABT_ERR		(1 << 5)
+#define S_GERROR_MSI_CMDQ_ABT_ERR		(1 << 4)
+#define S_GERROR_EVTQ_ABT_ERR		(1 << 2)
+#define S_GERROR_CMDQ_ERR			(1 << 0)
+
+#define ARM_SMMU_S_GERRORN		    0x8064
+
+#define ARM_SMMU_S_GERROR_IRQ_CFG0	0x8068
+#define ARM_SMMU_S_GERROR_IRQ_CFG1	0x8070
+#define ARM_SMMU_S_GERROR_IRQ_CFG2	0x8074
+
+#define ARM_SMMU_S_STRTAB_BASE		0x8080
+#define S_STRTAB_BASE_RA_SHIFT		62
+#define S_STRTAB_BASE_RA			(1UL << S_STRTAB_BASE_RA_SHIFT)
+#define S_STRTAB_BASE_ADDR_MASK		GENMASK_ULL(51, 6)
+
+#define ARM_SMMU_S_STRTAB_BASE_CFG	0x8088
+#define S_STRTAB_BASE_CFG_FMT		GENMASK(17, 16)
+#define S_STRTAB_BASE_CFG_SPLIT		GENMASK(10, 6)
+#define S_STRTAB_BASE_CFG_LOG2SIZE	GENMASK(5, 0)
+
+#define ARM_SMMU_S_CMDQ_BASE		0x8090
+#define ARM_SMMU_S_CMDQ_PROD		0x8098
+#define ARM_SMMU_S_CMDQ_CONS		0x809c
+#define S_CMDQ_BASE_ADDR_MASK		GENMASK_ULL(51, 5)
+#define S_CMDQ_BASE_RA_SHIFT		62
+
+#define ARM_SMMU_S_EVTQ_BASE		0x80a0
+#define ARM_SMMU_S_EVTQ_PROD		0x80a8
+#define ARM_SMMU_S_EVTQ_CONS		0x80ac
+#define ARM_SMMU_S_EVTQ_IRQ_CFG0	0x80b0
+#define ARM_SMMU_S_EVTQ_IRQ_CFG1	0x80b8
+#define ARM_SMMU_S_EVTQ_IRQ_CFG2	0x80bc
+#define S_EVTQ_BASE_ADDR_MASK		GENMASK_ULL(51, 5)
+#define S_EVTQ_BASE_WA_SHIFT		62
+
+/*
+ * BIT1 is PRIQEN, BIT4 is ATSCHK in SMMU_CRO
+ * BIT1 and BIT4 are RES0 in SMMU_S_CRO
+ */
+#define SMMU_S_CR0_RESERVED 0xFFFFFC12
+
+int get_root_bd(struct device *dev);
+void get_child_devices_rec(struct pci_dev *dev, uint16_t *devs, int max_devs, int *ndev);
+int get_sibling_devices(struct device *dev, uint16_t *devs, int max_devs);
+void set_g_cc_dev(u32 sid, u32 vmid, u32 root_bd, bool secure);
+void free_g_cc_dev_htable(void);
+/* Has the root bus device number switched to secure? */
+bool is_cc_root_bd(u32 root_bd);
+bool is_cc_dev(u32 sid);
+
+void s_smmu_cmdq_need_forward(u64 cmd0, u64 cmd1, u64 *forward);
+void s_queue_write(struct arm_smmu_device *smmu, u64 *src, size_t n_dwords);
+void arm_s_smmu_cmdq_write_entries(struct arm_smmu_device *smmu, u64 *cmds, int n);
+int arm_s_smmu_init_one_queue(struct arm_smmu_device *smmu,
+							  struct arm_smmu_queue *q,
+							  size_t qsz, const char *name);
+int arm_smmu_write_s_reg_sync(struct arm_smmu_device *smmu, u32 val, u32 cmp_val,
+				   unsigned int reg_off, unsigned int ack_off);
+int arm_smmu_update_s_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr);
+
+irqreturn_t arm_smmu_s_evtq_thread(int irq, void *dev);
+irqreturn_t arm_smmu_s_gerror_handler(int irq, void *dev);
+int arm_smmu_disable_s_irq(struct arm_smmu_device *smmu);
+int arm_smmu_enable_s_irq(struct arm_smmu_device *smmu, u32 irqen_flags);
+void arm_s_smmu_setup_unique_irqs(struct arm_smmu_device *smmu);
+void arm_smmu_write_s_msi_msg(struct arm_smmu_device *smmu, phys_addr_t *cfg,
+	struct msi_msg *msg, phys_addr_t doorbell);
+void platform_get_s_irq_byname_optional(struct platform_device *pdev, struct arm_smmu_device *smmu);
+int arm_smmu_enable_secure(struct iommu_domain *domain);
+u32 arm_smmu_tmi_dev_attach(struct arm_smmu_domain *arm_smmu_domain,
+	struct kvm *kvm);
+int arm_smmu_secure_dev_ste_create(struct arm_smmu_device *smmu,
+	struct arm_smmu_master *master, u32 sid);
+int arm_smmu_secure_set_dev(struct arm_smmu_domain *smmu_domain, struct arm_smmu_master *master,
+	 struct device *dev);
+
+int arm_smmu_id_alloc(void);
+void arm_smmu_id_free(int idx);
+void arm_smmu_map_init(struct arm_smmu_device *smmu, resource_size_t ioaddr);
+int arm_s_smmu_device_disable(struct arm_smmu_device *smmu);
+int arm_s_smmu_device_reset(struct arm_smmu_device *smmu);
+int arm_s_smmu_device_enable(struct arm_smmu_device *smmu,
+	u32 enables, bool bypass, bool disable_bypass);
+int arm_smmu_s_idr1_support_secure(struct arm_smmu_device *smmu);
+
+#endif /* _ARM_S_SMMU_V3_H */
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 16217647fd..157538d22f 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -30,6 +30,11 @@
 #include "arm-smmu-v3.h"
 #include "../../dma-iommu.h"
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#include <asm/kvm_tmi.h>
+#include "arm-s-smmu-v3.h"
+#endif
+
 static bool disable_bypass = true;
 module_param(disable_bypass, bool, 0444);
 MODULE_PARM_DESC(disable_bypass,
@@ -102,6 +107,10 @@ static int arm_smmu_bypass_dev_domain_type(struct device *dev)
 enum arm_smmu_msi_index {
    EVTQ_MSI_INDEX,
    GERROR_MSI_INDEX,
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	S_EVTQ_MSI_INDEX,
+	S_GERROR_MSI_INDEX,
+#endif
    PRIQ_MSI_INDEX,
    ARM_SMMU_MAX_MSIS,
 };
@@ -117,6 +126,18 @@ static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
    	ARM_SMMU_GERROR_IRQ_CFG1,
    	ARM_SMMU_GERROR_IRQ_CFG2,
    },
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	[S_EVTQ_MSI_INDEX] = {
+		ARM_SMMU_S_EVTQ_IRQ_CFG0,
+		ARM_SMMU_S_EVTQ_IRQ_CFG1,
+		ARM_SMMU_S_EVTQ_IRQ_CFG2,
+	},
+	[S_GERROR_MSI_INDEX] = {
+		ARM_SMMU_S_GERROR_IRQ_CFG0,
+		ARM_SMMU_S_GERROR_IRQ_CFG1,
+		ARM_SMMU_S_GERROR_IRQ_CFG2,
+	},
+#endif
    [PRIQ_MSI_INDEX] = {
    	ARM_SMMU_PRIQ_IRQ_CFG0,
    	ARM_SMMU_PRIQ_IRQ_CFG1,
@@ -995,11 +1016,16 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu,
     * Dependency ordering from the cmpxchg() loop above.
     */
    arm_smmu_cmdq_write_entries(cmdq, cmds, llq.prod, n);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	arm_s_smmu_cmdq_write_entries(smmu, cmds, n);
+#endif
    if (sync) {
    	prod = queue_inc_prod_n(&llq, n);
    	arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod);
    	queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS);
-
+		#ifdef CONFIG_HISI_VIRTCCA_HOST
+		s_queue_write(smmu, cmd_sync, CMDQ_ENT_DWORDS);
+		#endif
    	/*
    	 * In order to determine completion of our CMD_SYNC, we must
    	 * ensure that the queue can't wrap twice without us noticing.
@@ -2368,6 +2394,12 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain)
    if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
    	smmu_domain->stage = ARM_SMMU_DOMAIN_S1;
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (smmu_domain->secure) {
+		smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
+	}
+#endif
+
    switch (smmu_domain->stage) {
    case ARM_SMMU_DOMAIN_S1:
    	ias = (smmu->features & ARM_SMMU_FEAT_VAX) ? 52 : 48;
@@ -2588,6 +2620,52 @@ static void arm_smmu_detach_dev(struct arm_smmu_master *master)
    	arm_smmu_write_ctx_desc(master, IOMMU_NO_PASID, NULL);
 }
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+static void arm_smmu_secure_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
+{
+	struct arm_smmu_cmdq_ent prefetch_cmd = {
+		.opcode         = CMDQ_OP_PREFETCH_CFG,
+		.prefetch       = {
+		.sid            = sid,
+		},
+	};
+	arm_smmu_sync_ste_for_sid(smmu, sid);
+
+	/* It's likely that we'll want to use the new STE soon */
+	if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH))
+		arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);
+}
+
+static int arm_smmu_secure_dev_operator(struct arm_smmu_domain *smmu_domain,
+	struct arm_smmu_device *smmu, struct arm_smmu_master *master, struct device *dev)
+{
+	int i, j;
+	int ret;
+
+	ret = arm_smmu_secure_set_dev(smmu_domain, master, dev);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < master->num_streams; ++i) {
+		u32 sid = master->streams[i].id;
+		/* Bridged PCI devices may end up with duplicated IDs */
+		for (j = 0; j < i; j++)
+			if (master->streams[j].id == sid)
+				break;
+		if (j < i)
+			continue;
+		if (arm_smmu_secure_dev_ste_create(smmu, master, sid))
+			return -ENOMEM;
+
+		arm_smmu_secure_sync_ste_for_sid(smmu, sid);
+	}
+
+	dev_info(smmu->dev, "attach confidential dev: %s", dev_name(dev));
+
+	return ret;
+}
+#endif
+
 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
 {
    int ret = 0;
@@ -2669,6 +2747,11 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
arm_smmu_install_ste_for_dev(master);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (smmu_domain->secure)
+		ret = arm_smmu_secure_dev_operator(smmu_domain, smmu, master, dev);
+#endif
+
    arm_smmu_enable_ats(master);
    return 0;
@@ -3300,6 +3383,9 @@ static struct iommu_ops arm_smmu_ops = {
    .def_domain_type	= arm_smmu_def_domain_type,
    .pgsize_bitmap		= -1UL, /* Restricted during device attach */
    .owner			= THIS_MODULE,
+	#ifdef CONFIG_HISI_VIRTCCA_HOST
+	.iommu_enable_secure = arm_smmu_enable_secure,
+	#endif
    .default_domain_ops = &(const struct iommu_domain_ops) {
    	.attach_dev		= arm_smmu_attach_dev,
    	.map_pages		= arm_smmu_map_pages,
@@ -3362,6 +3448,13 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
    q->q_base |= FIELD_PREP(Q_BASE_LOG2SIZE, q->llq.max_n_shift);
q->llq.prod = q->llq.cons = 0;
+
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (arm_s_smmu_init_one_queue(smmu, q, qsz, name)) {
+		return -ENOMEM;
+	};
+#endif
+
    return 0;
 }
@@ -3665,6 +3758,15 @@ static void arm_smmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
    desc->msg.data = msg->data;
 #endif
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if ((desc->msi_index == S_EVTQ_MSI_INDEX ||
+		desc->msi_index == S_GERROR_MSI_INDEX) &&
+		smmu->id != ARM_SMMU_INVALID_ID) {
+		arm_smmu_write_s_msi_msg(smmu, cfg, msg, doorbell);
+		return;
+	}
+#endif
+
    writeq_relaxed(doorbell, smmu->base + cfg[0]);
    writel_relaxed(msg->data, smmu->base + cfg[1]);
    writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]);
@@ -3679,6 +3781,15 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
    writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0);
    writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (smmu->id != ARM_SMMU_INVALID_ID) {
+		if (tmi_smmu_write(smmu->ioaddr, ARM_SMMU_S_GERROR_IRQ_CFG0, 0, 64))
+			return;
+		if (tmi_smmu_write(smmu->ioaddr, ARM_SMMU_S_EVTQ_IRQ_CFG0, 0, 64))
+			return;
+	}
+#endif
+
    if (smmu->features & ARM_SMMU_FEAT_PRI)
    	writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0);
    else
@@ -3703,6 +3814,13 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
    smmu->gerr_irq = msi_get_virq(dev, GERROR_MSI_INDEX);
    smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (smmu->id != ARM_SMMU_INVALID_ID) {
+		smmu->s_evtq_irq = msi_get_virq(dev, S_EVTQ_MSI_INDEX);
+		smmu->s_gerr_irq = msi_get_virq(dev, S_GERROR_MSI_INDEX);
+	}
+#endif
+
    /* Add callback to free MSIs on teardown */
    devm_add_action(dev, arm_smmu_free_msis, dev);
 }
@@ -3791,6 +3909,11 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu, bool resume
    		dev_warn(smmu->dev, "no priq irq - PRI will be broken\n");
    	}
    }
+
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	arm_s_smmu_setup_unique_irqs(smmu);
+#endif
+
 }
static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu, bool resume)
@@ -3806,6 +3929,12 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu, bool resume)
    	return ret;
    }
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	ret = arm_smmu_disable_s_irq(smmu);
+	if (ret)
+		return ret;
+#endif
+
    irq = smmu->combined_irq;
    if (irq) {
    	/*
@@ -3831,6 +3960,12 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu, bool resume)
    if (ret)
    	dev_warn(smmu->dev, "failed to enable irqs\n");
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	ret = arm_smmu_enable_s_irq(smmu, IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN);
+	if (ret)
+		return ret;
+#endif
+
    return 0;
 }
@@ -3842,6 +3977,10 @@ static int arm_smmu_device_disable(struct arm_smmu_device *smmu)
    if (ret)
    	dev_err(smmu->dev, "failed to clear cr0\n");
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	ret = arm_s_smmu_device_disable(smmu);
+#endif
+
    return ret;
 }
@@ -3935,6 +4074,12 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool resume)
          FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB);
    writel_relaxed(reg, smmu->base + ARM_SMMU_CR1);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	ret = arm_s_smmu_device_reset(smmu);
+	if (ret)
+		return ret;
+#endif
+
    /* CR2 (random crap) */
    reg = CR2_PTM | CR2_RECINVSID;
@@ -4027,6 +4172,14 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool resume)
    if (is_kdump_kernel())
    	enables &= ~(CR0_EVTQEN | CR0_PRIQEN);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	ret = arm_s_smmu_device_enable(smmu, enables, smmu->bypass, disable_bypass);
+	if (ret) {
+		dev_err(smmu->dev, "failed to enable secure SMMU interface\n");
+		return ret;
+	}
+#endif
+
    /* Enable the SMMU interface, or ensure bypass */
    if (!smmu->bypass || disable_bypass) {
    	enables |= CR0_SMMUEN;
@@ -4358,6 +4511,11 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
    	smmu->features |= ARM_SMMU_FEAT_ECMDQ;
 #endif
+#ifndef CONFIG_HISI_VIRTCCA_HOST
+	if (reg & IDR1_ECMDQ)
+		smmu->features |= ARM_SMMU_FEAT_ECMDQ;
+#endif
+
    /* Queue sizes, capped to ensure natural alignment */
    smmu->cmdq.q.llq.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT,
    				     FIELD_GET(IDR1_CMDQS, reg));
@@ -4390,6 +4548,11 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
    if (smmu->sid_bits <= STRTAB_SPLIT)
    	smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB;
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (arm_smmu_s_idr1_support_secure(smmu))
+		return -ENXIO;
+#endif
+
    /* IDR3 */
    reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3);
    switch (FIELD_GET(IDR3_BBML, reg)) {
@@ -4748,6 +4911,10 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
    }
    ioaddr = res->start;
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	arm_smmu_map_init(smmu, ioaddr);
+#endif
+
    /*
     * Don't map the IMPLEMENTATION DEFINED regions, since they may contain
     * the PMCG registers which are reserved by the PMU driver.
@@ -4782,6 +4949,11 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
    	irq = platform_get_irq_byname_optional(pdev, "gerror");
    	if (irq > 0)
    		smmu->gerr_irq = irq;
+
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+		platform_get_s_irq_byname_optional(pdev, smmu);
+#endif
+
    }
    /* Probe the h/w */
    ret = arm_smmu_device_hw_probe(smmu);
@@ -4829,6 +5001,10 @@ static void arm_smmu_device_remove(struct platform_device *pdev)
    arm_smmu_device_disable(smmu);
    iopf_queue_free(smmu->evtq.iopf);
    ida_destroy(&smmu->vmid_map);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	free_g_cc_dev_htable();
+	arm_smmu_id_free(smmu->id);
+#endif
 }
static void arm_smmu_device_shutdown(struct platform_device *pdev)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 859d217298..43121c17a2 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -13,6 +13,9 @@
 #include <linux/kernel.h>
 #include <linux/mmzone.h>
 #include <linux/sizes.h>
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#include <linux/kvm_host.h>
+#endif
/* MMIO registers */
 #define ARM_SMMU_IDR0			0x0
@@ -750,6 +753,13 @@ struct arm_smmu_device {
    struct mutex			streams_mutex;
bool				bypass;
+
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	int				s_evtq_irq;
+	int				s_gerr_irq;
+	resource_size_t ioaddr;
+	uint64_t		id;
+#endif
 };
struct arm_smmu_stream {
@@ -802,6 +812,12 @@ struct arm_smmu_domain {
    spinlock_t			devices_lock;
struct list_head		mmu_notifiers;
+
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	bool secure;
+	struct list_head node;
+	struct kvm *kvm;
+#endif
 };
static inline struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 79aa11d88c..0f46148871 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -22,6 +22,16 @@
#include "io-pgtable-arm.h"
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#include <asm/kvm_tmi.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_tmm.h>
+#include <linux/kvm_host.h>
+#include <linux/kvm.h>
+#include <asm/kvm.h>
+#include "../virt/kvm/vfio.h"
+#endif
+
 #define ARM_LPAE_MAX_ADDR_BITS		52
 #define ARM_LPAE_S2_MAX_CONCAT_PAGES	16
 #define ARM_LPAE_MAX_LEVELS		4
@@ -493,6 +503,41 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
    return pte;
 }
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+static int arm_lpae_cvm_map_unmap_pages(struct arm_lpae_io_pgtable *data, unsigned long iova,
+	phys_addr_t paddr, size_t size, uint32_t is_map)
+{
+	struct arm_smmu_domain *smmu_domain = (struct arm_smmu_domain *)data->iop.cookie;
+	int ret = 0;
+	struct kvm *kvm;
+	u64 loader_start;
+	u64 ram_size;
+	static bool smmu_mapped = false;
+
+	kvm = smmu_domain->kvm;
+	if (kvm && kvm_is_virtcca_cvm(kvm) && virtcca_cvm_state(kvm) != CVM_STATE_DYING) {
+		struct virtcca_cvm *virtcca_cvm = (struct virtcca_cvm *)kvm->arch.virtcca_cvm;
+
+		loader_start = virtcca_cvm->loader_start;
+		ram_size = virtcca_cvm->ram_size;
+		if (!smmu_mapped && iova >= loader_start &&
+			iova < loader_start + ram_size &&
+			is_map && !virtcca_cvm->is_mapped) {
+			ret = kvm_cvm_map_range(kvm);
+			if (!ret)
+				smmu_mapped = true;
+			WARN_ON(ret);
+		} else if (iova < loader_start) {
+			if (iova == CVM_MSI_ORIG_IOVA)
+				iova += CVM_MSI_IOVA_OFFSET;
+			ret = kvm_cvm_map_unmap_ipa_range(kvm, iova, paddr, size, is_map);
+			WARN_ON(ret);
+		}
+	}
+	return ret;
+}
+#endif
+
 static int arm_lpae_map_pages(struct io_pgtable_ops *ops, unsigned long iova,
    		      phys_addr_t paddr, size_t pgsize, size_t pgcount,
    		      int iommu_prot, gfp_t gfp, size_t *mapped)
@@ -517,6 +562,11 @@ static int arm_lpae_map_pages(struct io_pgtable_ops *ops, unsigned long iova,
    	return 0;
prot = arm_lpae_prot_to_pte(data, iommu_prot);
+
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	ret = arm_lpae_cvm_map_unmap_pages(data, iova, paddr, pgsize * pgcount, true);
+#endif
+
    ret = __arm_lpae_map(data, iova, paddr, pgsize, pgcount, prot, lvl,
    		     ptep, gfp, mapped);
    /*
@@ -703,6 +753,16 @@ static size_t arm_lpae_unmap_pages(struct io_pgtable_ops *ops, unsigned long iov
    if (WARN_ON(iaext))
    	return 0;
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	int ret;
+
+	ret = arm_lpae_cvm_map_unmap_pages(data, iova, 0, pgsize * pgcount, false);
+	WARN_ON(ret);
+	if (ret)
+		pr_err("%s %d failed to unmap pages, iova %lx, size %lx\n",
+			__func__, __LINE__, iova, pgsize);
+#endif
+
    return __arm_lpae_unmap(data, gather, iova, pgsize, pgcount,
    			data->start_level, ptep);
 }
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index 28f63ad432..07a084c9d9 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -592,6 +592,17 @@ static int __iommu_probe_device(struct device *dev, struct list_head *group_list
    return ret;
 }
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+struct iommu_domain *iommu_group_get_domain(struct iommu_group *iommu_group)
+{
+	if (iommu_group)
+		return iommu_group->domain;
+
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(iommu_group_get_domain);
+#endif
+
 int iommu_probe_device(struct device *dev)
 {
    const struct iommu_ops *ops;
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 6554a2e89d..813198abfc 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -7,6 +7,10 @@
#include "pci.h"
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#include <asm/kvm_tmi.h>
+#endif
+
 /*
  * This interrupt-safe spinlock protects all accesses to PCI
  * configuration space.
@@ -86,6 +90,19 @@ int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
    if (!addr)
    	return PCIBIOS_DEVICE_NOT_FOUND;
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (is_cc_dev((bus->number << 8) | devfn)) {
+		if (size == 1)
+			*val = tmi_mmio_read(va_to_pa(addr), 8, ((bus->number << 8) | devfn));
+		else if (size == 2)
+			*val = tmi_mmio_read(va_to_pa(addr), 16, ((bus->number << 8) | devfn));
+		else
+			*val = tmi_mmio_read(va_to_pa(addr), 32, ((bus->number << 8) | devfn));
+
+		return PCIBIOS_SUCCESSFUL;
+	}
+#endif
+
    if (size == 1)
    	*val = readb(addr);
    else if (size == 2)
@@ -106,6 +123,22 @@ int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
    if (!addr)
    	return PCIBIOS_DEVICE_NOT_FOUND;
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (is_cc_dev((bus->number << 8) | devfn)) {
+		if (size == 1)
+			WARN_ON(tmi_mmio_write(va_to_pa(addr), val,
+				8, ((bus->number << 8) | devfn)));
+		else if (size == 2)
+			WARN_ON(tmi_mmio_write(va_to_pa(addr), val,
+				16, ((bus->number << 8) | devfn)));
+		else
+			WARN_ON(tmi_mmio_write(va_to_pa(addr), val,
+				32, ((bus->number << 8) | devfn)));
+
+		return PCIBIOS_SUCCESSFUL;
+	}
+#endif
+
    if (size == 1)
    	writeb(val, addr);
    else if (size == 2)
diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c
index 7078200be1..c98fb0cbe1 100644
--- a/drivers/pci/msi/msi.c
+++ b/drivers/pci/msi/msi.c
@@ -13,6 +13,11 @@
 #include "../pci.h"
 #include "msi.h"
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#include <asm/kvm_tmm.h>
+#include <asm/kvm_tmi.h>
+#endif
+
 int pci_msi_enable = 1;
 int pci_msi_ignore_mask;
@@ -159,9 +164,23 @@ void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
    	if (WARN_ON_ONCE(entry->pci.msi_attrib.is_virtual))
    		return;
-		msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
-		msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
-		msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+		u64 pbase = va_to_pa(base);
+
+		if (dev != NULL && is_cc_dev(pci_dev_id(dev))) {
+			msg->address_lo = tmi_mmio_read(pbase + PCI_MSIX_ENTRY_LOWER_ADDR,
+				32, pci_dev_id(dev));
+			msg->address_hi = tmi_mmio_read(pbase + PCI_MSIX_ENTRY_UPPER_ADDR,
+				32, pci_dev_id(dev));
+			msg->data = tmi_mmio_read(pbase + PCI_MSIX_ENTRY_DATA, 32, pci_dev_id(dev));
+		} else {
+#endif
+			msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
+			msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
+			msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+		}
+#endif
    } else {
    	int pos = dev->msi_cap;
    	u16 data;
@@ -221,15 +240,41 @@ static inline void pci_write_msg_msix(struct msi_desc *desc, struct msi_msg *msg
    if (unmasked)
    	pci_msix_write_vector_ctrl(desc, ctrl | PCI_MSIX_ENTRY_CTRL_MASKBIT);
-	writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
-	writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
-	writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	u64 pbase = va_to_pa(base);
+
+	struct pci_dev *pdev = (desc->dev != NULL &&
+		dev_is_pci(desc->dev)) ? to_pci_dev(desc->dev) : NULL;
+
+	if (pdev != NULL && is_cc_dev(pci_dev_id(pdev))) {
+		u64 addr = (u64)msg->address_lo | ((u64)msg->address_hi << 32);
+
+		addr += CVM_MSI_IOVA_OFFSET;
+		tmi_mmio_write(pbase + PCI_MSIX_ENTRY_LOWER_ADDR,
+			lower_32_bits(addr), 32, pci_dev_id(pdev));
+		tmi_mmio_write(pbase + PCI_MSIX_ENTRY_UPPER_ADDR,
+			upper_32_bits(addr), 32, pci_dev_id(pdev));
+		tmi_mmio_write(pbase + PCI_MSIX_ENTRY_DATA,
+			msg->data, 32, pci_dev_id(pdev));
+	} else {
+#endif
+		writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
+		writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
+		writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	}
+#endif
if (unmasked)
    	pci_msix_write_vector_ctrl(desc, ctrl);
/* Ensure that the writes are visible in the device */
-	readl(base + PCI_MSIX_ENTRY_DATA);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (pdev != NULL && is_cc_dev(pci_dev_id(pdev)))
+		tmi_mmio_read(va_to_pa(pbase + PCI_MSIX_ENTRY_DATA), 32, pci_dev_id(pdev));
+	else
+#endif
+		readl(base + PCI_MSIX_ENTRY_DATA);
 }
void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
@@ -632,7 +677,12 @@ void msix_prepare_msi_desc(struct pci_dev *dev, struct msi_desc *desc)
if (desc->pci.msi_attrib.can_mask) {
    	void __iomem *addr = pci_msix_desc_addr(desc);
-
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (is_cc_dev(pci_dev_id(dev)))
+		desc->pci.msix_ctrl = tmi_mmio_read(va_to_pa(addr + PCI_MSIX_ENTRY_VECTOR_CTRL),
+			32, pci_dev_id(dev));
+	else
+#endif
    	desc->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
    }
 }
@@ -684,6 +734,23 @@ static void msix_mask_all(void __iomem *base, int tsize)
    	writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
 }
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+static void msix_mask_all_cc(void __iomem *base, int tsize, u64 dev_num)
+{
+	u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
+	int i;
+	u64 pbase = va_to_pa(base);
+
+	if (pci_msi_ignore_mask)
+		return;
+
+	for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE) {
+		tmi_mmio_write(pbase + PCI_MSIX_ENTRY_VECTOR_CTRL,
+			ctrl, 32, dev_num);
+	}
+}
+#endif
+
 static int msix_setup_interrupts(struct pci_dev *dev, struct msix_entry *entries,
    			 int nvec, struct irq_affinity *affd)
 {
@@ -770,7 +837,12 @@ static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
     * which takes the MSI-X mask bits into account even
     * when MSI-X is disabled, which prevents MSI delivery.
     */
-	msix_mask_all(dev->msix_base, tsize);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (is_cc_dev(pci_dev_id(dev)))
+		msix_mask_all_cc(dev->msix_base, tsize, pci_dev_id(dev));
+	else
+#endif
+		msix_mask_all(dev->msix_base, tsize);
    pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
pcibios_free_irq(dev);
diff --git a/drivers/vfio/pci/vfio_pci_core.c b/drivers/vfio/pci/vfio_pci_core.c
index 1929103ee5..0f3976692b 100644
--- a/drivers/vfio/pci/vfio_pci_core.c
+++ b/drivers/vfio/pci/vfio_pci_core.c
@@ -975,6 +975,11 @@ static int vfio_pci_ioctl_get_info(struct vfio_pci_core_device *vdev,
    if (vdev->reset_works)
    	info.flags |= VFIO_DEVICE_FLAGS_RESET;
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (is_cc_dev(pci_dev_id(vdev->pdev)))
+		info.flags |= VFIO_DEVICE_FLAGS_SECURE;
+#endif
+
    info.num_regions = VFIO_PCI_NUM_REGIONS + vdev->num_regions;
    info.num_irqs = VFIO_PCI_NUM_IRQS;
diff --git a/drivers/vfio/pci/vfio_pci_rdwr.c b/drivers/vfio/pci/vfio_pci_rdwr.c
index e27de61ac9..e4deb868dc 100644
--- a/drivers/vfio/pci/vfio_pci_rdwr.c
+++ b/drivers/vfio/pci/vfio_pci_rdwr.c
@@ -18,6 +18,9 @@
 #include <linux/vgaarb.h>
#include "vfio_pci_priv.h"
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#include <asm/kvm_tmi.h>
+#endif
#ifdef __LITTLE_ENDIAN
 #define vfio_ioread64	ioread64
@@ -37,6 +40,34 @@
 #define vfio_ioread8	ioread8
 #define vfio_iowrite8	iowrite8
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#define VFIO_IOWRITE(size) \
+static int vfio_pci_iowrite##size(struct vfio_pci_core_device *vdev,		\
+			bool test_mem, u##size val, void __iomem *io)	\
+{									\
+	struct pci_dev *pdev = vdev->pdev;				\
+	bool cc_dev = pdev == NULL ? false : is_cc_dev(pci_dev_id(pdev)); \
+									\
+	if (test_mem) {							\
+		down_read(&vdev->memory_lock);				\
+		if (!__vfio_pci_memory_enabled(vdev)) {			\
+			up_read(&vdev->memory_lock);			\
+			return -EIO;					\
+		}							\
+	}								\
+									\
+	if (cc_dev) {							\
+		WARN_ON(tmi_mmio_write(va_to_pa(io), val, size, pci_dev_id(pdev)));	\
+	} else {							\
+		vfio_iowrite##size(val, io);				\
+	}								\
+									\
+	if (test_mem)							\
+		up_read(&vdev->memory_lock);				\
+									\
+	return 0;							\
+}
+#else /* not CONFIG_HISI_VIRTCCA_HOST */
 #define VFIO_IOWRITE(size) \
 static int vfio_pci_iowrite##size(struct vfio_pci_core_device *vdev,		\
    		bool test_mem, u##size val, void __iomem *io)	\
@@ -56,6 +87,7 @@ static int vfio_pci_iowrite##size(struct vfio_pci_core_device *vdev,		\
    								\
    return 0;							\
 }
+#endif /* CONFIG_HISI_VIRTCCA_HOST */
VFIO_IOWRITE(8)
 VFIO_IOWRITE(16)
@@ -64,6 +96,34 @@ VFIO_IOWRITE(32)
 VFIO_IOWRITE(64)
 #endif
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#define VFIO_IOREAD(size) \
+static int vfio_pci_ioread##size(struct vfio_pci_core_device *vdev,		\
+			bool test_mem, u##size *val, void __iomem *io)	\
+{									\
+	struct pci_dev *pdev = vdev->pdev;				\
+	bool cc_dev = pdev == NULL ? false : is_cc_dev(pci_dev_id(pdev)); \
+									\
+	if (test_mem) {							\
+		down_read(&vdev->memory_lock);				\
+		if (!__vfio_pci_memory_enabled(vdev)) {			\
+			up_read(&vdev->memory_lock);			\
+			return -EIO;					\
+		}							\
+	}								\
+									\
+	if (cc_dev) {							\
+		*val = tmi_mmio_read(va_to_pa(io), size, pci_dev_id(pdev));		\
+	} else {							\
+		*val = vfio_ioread##size(io);				\
+	}								\
+									\
+	if (test_mem)							\
+		up_read(&vdev->memory_lock);				\
+									\
+	return 0;							\
+}
+#else /* not CONFIG_HISI_VIRTCCA_HOST */
 #define VFIO_IOREAD(size) \
 static int vfio_pci_ioread##size(struct vfio_pci_core_device *vdev,		\
    		bool test_mem, u##size *val, void __iomem *io)	\
@@ -83,6 +143,7 @@ static int vfio_pci_ioread##size(struct vfio_pci_core_device *vdev,		\
    								\
    return 0;							\
 }
+#endif
VFIO_IOREAD(8)
 VFIO_IOREAD(16)
diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c
index 9c4adf11db..021f054088 100644
--- a/drivers/vfio/vfio_iommu_type1.c
+++ b/drivers/vfio/vfio_iommu_type1.c
@@ -77,6 +77,9 @@ struct vfio_iommu {
    bool			dirty_page_tracking;
    struct list_head	emulated_iommu_groups;
    bool			dirty_log_get_no_clear;
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	bool            secure;
+#endif
 };
struct vfio_domain {
@@ -2454,6 +2457,11 @@ static int vfio_iommu_type1_attach_group(void *iommu_data,
    		goto out_domain;
    }
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	if (iommu->secure)
+		domain->domain->owner->iommu_enable_secure(domain->domain);
+#endif
+
    ret = iommu_attach_group(domain->domain, group->iommu_group);
    if (ret)
    	goto out_domain;
@@ -2807,6 +2815,12 @@ static void *vfio_iommu_type1_open(unsigned long arg)
    case VFIO_TYPE1v2_IOMMU:
    	iommu->v2 = true;
    	break;
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	case VFIO_TYPE1v2_S_IOMMU:
+		iommu->v2 = true;
+		iommu->secure = true;
+		break;
+#endif
    default:
    	kfree(iommu);
    	return ERR_PTR(-EINVAL);
@@ -2898,6 +2912,9 @@ static int vfio_iommu_type1_check_extension(struct vfio_iommu *iommu,
    switch (arg) {
    case VFIO_TYPE1_IOMMU:
    case VFIO_TYPE1v2_IOMMU:
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	case VFIO_TYPE1v2_S_IOMMU:
+#endif
    case VFIO_TYPE1_NESTING_IOMMU:
    case VFIO_UNMAP_ALL:
    	return 1;
diff --git a/drivers/vfio/vfio_main.c b/drivers/vfio/vfio_main.c
index a96d97da36..0d45ed89ab 100644
--- a/drivers/vfio/vfio_main.c
+++ b/drivers/vfio/vfio_main.c
@@ -318,6 +318,24 @@ static int __vfio_register_dev(struct vfio_device *device,
    return ret;
 }
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+bool vfio_iommu_group(struct vfio_group *vfio_group, struct iommu_group *iommu_group)
+{
+	if (vfio_group->iommu_group == iommu_group)
+		return true;
+	return false;
+}
+EXPORT_SYMBOL_GPL(vfio_iommu_group);
+
+struct iommu_group *vfio_get_iommu_group(struct vfio_group *vfio_group)
+{
+	if (vfio_group)
+		return vfio_group->iommu_group;
+	return NULL;
+}
+EXPORT_SYMBOL_GPL(vfio_get_iommu_group);
+#endif
+
 int vfio_register_group_dev(struct vfio_device *device)
 {
    return __vfio_register_dev(device, VFIO_IOMMU);
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 1d70dd0d0c..a957310861 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -635,7 +635,11 @@ struct iommu_ops {
    struct iommu_domain *blocked_domain;
    struct iommu_domain *default_domain;
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	KABI_USE(1, int (*iommu_enable_secure)(struct iommu_domain *domain))
+#else
    KABI_RESERVE(1)
+#endif
    KABI_RESERVE(2)
    KABI_RESERVE(3)
    KABI_RESERVE(4)
@@ -1148,6 +1152,11 @@ static inline void *dev_iommu_priv_get(struct device *dev)
 void dev_iommu_priv_set(struct device *dev, void *priv);
extern struct mutex iommu_probe_device_lock;
+
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+struct iommu_domain *iommu_group_get_domain(struct iommu_group *iommu_group);
+#endif
+
 int iommu_probe_device(struct device *dev);
int iommu_dev_enable_feature(struct device *dev, enum iommu_dev_features f);
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
index 19a7b00baf..865938aebf 100644
--- a/include/linux/iopoll.h
+++ b/include/linux/iopoll.h
@@ -113,6 +113,44 @@
    (cond) ? 0 : -ETIMEDOUT; \
 })
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#define kvm_cvm_read_poll_timeout_atomic(op, val, cond, delay_us, timeout_us, \
+					delay_before_read, args...) \
+({ \
+	u64 __timeout_us = (timeout_us); \
+	u64 rv = 0; \
+	int result = 0; \
+	unsigned long __delay_us = (delay_us); \
+	ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
+	if (delay_before_read && __delay_us) \
+		udelay(__delay_us); \
+	for (;;) { \
+		rv = op(args); \
+		if (rv >> 32) { \
+			result = -ENXIO; \
+			break; \
+		} \
+		(val) = (u32)rv; \
+		if (cond) \
+			break; \
+		if (__timeout_us && \
+		    ktime_compare(ktime_get(), __timeout) > 0) { \
+			rv = op(args); \
+			if (rv >> 32) { \
+				result = -ENXIO; \
+				break; \
+			} \
+			(val) = (u32)rv; \
+			break; \
+		} \
+		if (__delay_us) \
+			udelay(__delay_us); \
+		cpu_relax(); \
+	} \
+	result ? result : ((cond) ? 0 : -ETIMEDOUT); \
+})
+#endif
+
 /**
  * readx_poll_timeout - Periodically poll an address until a condition is met or a timeout occurs
  * @op: accessor function (takes @addr as its only argument)
diff --git a/include/linux/pci.h b/include/linux/pci.h
index dcc442ca8b..1e5240d13e 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -2727,4 +2727,8 @@ void pci_uevent_ers(struct pci_dev *pdev, enum  pci_ers_result err_type);
    WARN_ONCE(condition, "%s %s: " fmt, \
    	  dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+bool is_cc_dev(u32 sid);
+#endif
+
 #endif /* LINUX_PCI_H */
diff --git a/include/linux/vfio.h b/include/linux/vfio.h
index 5ac5f182ce..d231eb5bf7 100644
--- a/include/linux/vfio.h
+++ b/include/linux/vfio.h
@@ -123,6 +123,11 @@ struct vfio_device_ops {
    			  void __user *arg, size_t argsz);
 };
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+extern bool vfio_iommu_group(struct vfio_group *vfio_group, struct iommu_group *iommu_group);
+extern struct iommu_group *vfio_get_iommu_group(struct vfio_group *vfio_group);
+#endif
+
 #if IS_ENABLED(CONFIG_IOMMUFD)
 struct iommufd_ctx *vfio_iommufd_device_ictx(struct vfio_device *vdev);
 int vfio_iommufd_get_dev_id(struct vfio_device *vdev, struct iommufd_ctx *ictx);
diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h
index 2b78d03c0c..cb88e78805 100644
--- a/include/uapi/linux/vfio.h
+++ b/include/uapi/linux/vfio.h
@@ -25,6 +25,8 @@
 #define VFIO_TYPE1_IOMMU		1
 #define VFIO_SPAPR_TCE_IOMMU		2
 #define VFIO_TYPE1v2_IOMMU		3
+#define VFIO_TYPE1v2_S_IOMMU	12
+
 /*
  * IOMMU enforces DMA cache coherence (ex. PCIe NoSnoop stripping).  This
  * capability is subject to change as groups are added or removed.
@@ -224,6 +226,9 @@ struct vfio_device_info {
 #define VFIO_DEVICE_FLAGS_FSL_MC (1 << 6)	/* vfio-fsl-mc device */
 #define VFIO_DEVICE_FLAGS_CAPS	(1 << 7)	/* Info supports caps */
 #define VFIO_DEVICE_FLAGS_CDX	(1 << 8)	/* vfio-cdx device */
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#define VFIO_DEVICE_FLAGS_SECURE (1 << 8)
+#endif
    __u32	num_regions;	/* Max region index + 1 */
    __u32	num_irqs;	/* Max IRQ index + 1 */
    __u32   cap_offset;	/* Offset within info struct of first cap */
diff --git a/virt/kvm/vfio.c b/virt/kvm/vfio.c
index ca24ce1209..6c99956ee7 100644
--- a/virt/kvm/vfio.c
+++ b/virt/kvm/vfio.c
@@ -17,6 +17,10 @@
 #include <linux/vfio.h>
 #include "vfio.h"
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#include <asm/kvm_emulate.h>
+#endif
+
 #ifdef CONFIG_SPAPR_TCE_IOMMU
 #include <asm/kvm_ppc.h>
 #endif
@@ -80,7 +84,7 @@ static bool kvm_vfio_file_is_valid(struct file *file)
    return ret;
 }
-#ifdef CONFIG_SPAPR_TCE_IOMMU
+#if defined CONFIG_SPAPR_TCE_IOMMU || defined CONFIG_HISI_VIRTCCA_HOST
 static struct iommu_group *kvm_vfio_file_iommu_group(struct file *file)
 {
    struct iommu_group *(*fn)(struct file *file);
@@ -96,7 +100,9 @@ static struct iommu_group *kvm_vfio_file_iommu_group(struct file *file)
return ret;
 }
+#endif
+#ifdef ONFIG_SPAPR_TCE_IOMMU
 static void kvm_spapr_tce_release_vfio_group(struct kvm *kvm,
    				     struct kvm_vfio_file *kvf)
 {
@@ -142,6 +148,9 @@ static void kvm_vfio_update_coherency(struct kvm_device *dev)
static int kvm_vfio_file_add(struct kvm_device *dev, unsigned int fd)
 {
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	struct iommu_group *iommu_group;
+#endif
    struct kvm_vfio *kv = dev->private;
    struct kvm_vfio_file *kvf;
    struct file *filp;
@@ -179,6 +188,18 @@ static int kvm_vfio_file_add(struct kvm_device *dev, unsigned int fd)
    kvm_vfio_file_set_kvm(kvf->file, dev->kvm);
    kvm_vfio_update_coherency(dev);
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+	iommu_group = kvm_vfio_file_iommu_group(filp);
+	if (!iommu_group) {
+		ret = -ENXIO;
+		goto out_unlock;
+	}
+	if (cvm_arm_smmu_domain_set_kvm(iommu_group)) {
+		ret = -ENXIO;
+		goto out_unlock;
+	}
+#endif
+
 out_unlock:
    mutex_unlock(&kv->lock);
 out_fput:
@@ -226,7 +247,7 @@ static int kvm_vfio_file_del(struct kvm_device *dev, unsigned int fd)
    return ret;
 }
-#ifdef CONFIG_SPAPR_TCE_IOMMU
+#ifdef CONFIG_SPAPR_TCE_IOMMU 
 static int kvm_vfio_file_set_spapr_tce(struct kvm_device *dev,
    			       void __user *arg)
 {
@@ -392,3 +413,100 @@ void kvm_vfio_ops_exit(void)
 {
    kvm_unregister_device_ops(KVM_DEV_TYPE_VFIO);
 }
+
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+struct kvm *arm_smmu_get_kvm(struct arm_smmu_domain *domain)
+{
+	int ret = -1;
+	struct kvm *kvm;
+	struct kvm_device *dev;
+	struct kvm_vfio *kv;
+	struct kvm_vfio_file *kvf;
+	struct iommu_group *iommu_group;
+
+	unsigned long flags;
+	struct arm_smmu_master *master;
+
+	spin_lock_irqsave(&domain->devices_lock, flags);
+	list_for_each_entry(master, &domain->devices, domain_head) {
+		if (master && master->num_streams >= 0) {
+			ret = 0;
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&domain->devices_lock, flags);
+	if (ret)
+		return NULL;
+
+	ret = -1;
+	iommu_group = master->dev->iommu_group;
+	mutex_lock(&kvm_lock);
+	list_for_each_entry(kvm, &vm_list, vm_list) {
+		mutex_lock(&kvm->lock);
+		list_for_each_entry(dev, &kvm->devices, vm_node) {
+			if (dev->ops && strcmp(dev->ops->name, "kvm-vfio") == 0) {
+				kv = (struct kvm_vfio *)dev->private;
+				mutex_lock(&kv->lock);
+				list_for_each_entry(kvf, &kv->file_list, node) {
+					if (kvm_vfio_file_iommu_group(kvf->file) == iommu_group) {
+						ret = 0;
+						break;
+					}
+				}
+				mutex_unlock(&kv->lock);
+				if (!ret)
+					break;
+			}
+		}
+		mutex_unlock(&kvm->lock);
+		if (!ret)
+			break;
+	}
+	mutex_unlock(&kvm_lock);
+
+	if (ret)
+		return NULL;
+	return kvm;
+}
+
+int kvm_get_arm_smmu_domain(struct kvm *kvm, struct list_head *smmu_domain_group_list)
+{
+	int ret = 0;
+	struct kvm_device *dev;
+	struct kvm_vfio *kv;
+	struct kvm_vfio_file *kvf;
+	struct iommu_group *iommu_group;
+	struct arm_smmu_domain *arm_smmu_domain = NULL;
+	struct arm_smmu_domain *arm_smmu_domain_node = NULL;
+
+	INIT_LIST_HEAD(smmu_domain_group_list);
+
+	list_for_each_entry(dev, &kvm->devices, vm_node) {
+		if (dev->ops && strcmp(dev->ops->name, "kvm-vfio") == 0) {
+			kv = (struct kvm_vfio *)dev->private;
+			mutex_lock(&kv->lock);
+			list_for_each_entry(kvf, &kv->file_list, node) {
+				ret = 0;
+				iommu_group = kvm_vfio_file_iommu_group(kvf->file);
+				if (iommu_group && iommu_group_get_domain(iommu_group)) {
+					arm_smmu_domain =
+						to_smmu_domain(iommu_group_get_domain(iommu_group));
+					list_for_each_entry(arm_smmu_domain_node,
+						smmu_domain_group_list, node) {
+						if (arm_smmu_domain_node == arm_smmu_domain) {
+							ret = -1;
+							break;
+						}
+					}
+					if (!ret)
+						list_add_tail(&arm_smmu_domain->node,
+							smmu_domain_group_list);
+				}
+			}
+			mutex_unlock(&kv->lock);
+		}
+	}
+
+	return 0;
+}
+#endif
diff --git a/virt/kvm/vfio.h b/virt/kvm/vfio.h
index e130a4a035..43c303bcf6 100644
--- a/virt/kvm/vfio.h
+++ b/virt/kvm/vfio.h
@@ -2,6 +2,12 @@
 #ifndef __KVM_VFIO_H
 #define __KVM_VFIO_H
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+#include <linux/kvm_host.h>
+#include "../drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h"
+#include "../drivers/iommu/arm/arm-smmu-v3/arm-s-smmu-v3.h"
+#endif
+
 #ifdef CONFIG_KVM_VFIO
 int kvm_vfio_ops_init(void);
 void kvm_vfio_ops_exit(void);
@@ -15,4 +21,8 @@ static inline void kvm_vfio_ops_exit(void)
 }
 #endif
+#ifdef CONFIG_HISI_VIRTCCA_HOST
+struct kvm *arm_smmu_get_kvm(struct arm_smmu_domain *domain);
+int kvm_get_arm_smmu_domain(struct kvm *kvm, struct list_head *smmu_domain_group_list);
+#endif
 #endif
-- 
2.25.1


    

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[PATCH OLK-6.6 2/2] Coda feature