[PATCH OLK-5.10 1/9] Revert "crypto: hisilicon/qm - save capability registers in qm init process"

From: JiangShui 1175135535@qq.com

driver inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I8IVG6 CVE: NA

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This modificating is incomplete, now replace it with a better solution This reverts commit b9b5cb5e9700b618afff4febb7f959989ed81ad4.

Signed-off-by: JiangShui Yang yangjiangshui@h-partners.com --- drivers/crypto/hisilicon/qm.c | 43 +++++++---------------------------- include/linux/hisi_acc_qm.h | 5 ---- 2 files changed, 8 insertions(+), 40 deletions(-)

diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index 9ddfbe951be8..d413ad5ebe3d 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -302,13 +302,6 @@ enum qm_basic_type { QM_VF_IRQ_NUM_CAP, };

-enum qm_irq_type_caps_idx { - QM_EQ_IRQ_TYPE_CAP_IDX, - QM_AEQ_IRQ_TYPE_CAP_IDX, - QM_ABN_IRQ_TYPE_CAP_IDX, - QM_PF2VF_IRQ_TYPE_CAP_IDX -}; - static const struct hisi_qm_cap_info qm_cap_info_comm[] = { {QM_SUPPORT_DB_ISOLATION, 0x30, 0, BIT(0), 0x0, 0x0, 0x0}, {QM_SUPPORT_FUNC_QOS, 0x3100, 0, BIT(8), 0x0, 0x0, 0x1}, @@ -338,13 +331,6 @@ static const struct hisi_qm_cap_info qm_basic_info[] = { {QM_VF_IRQ_NUM_CAP, 0x311c, 0, GENMASK(15, 0), 0x1, 0x2, 0x3}, };

-static struct hisi_qm_cap_record qm_irq_type_caps[] = { - {QM_EQ_IRQ_TYPE_CAP, 0x10000}, - {QM_AEQ_IRQ_TYPE_CAP, 0x10001}, - {QM_ABN_IRQ_TYPE_CAP, 0x10003}, - {QM_PF2VF_IRQ_TYPE_CAP, 0x10002}, -}; - struct qm_mailbox { __le16 w0; __le16 queue_num; @@ -5031,7 +5017,7 @@ static void qm_unregister_abnormal_irq(struct hisi_qm *qm) if (qm->fun_type == QM_HW_VF) return;

- val = qm_irq_type_caps[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val; + val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm->cap_ver); if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK)) return;

@@ -5048,7 +5034,7 @@ static int qm_register_abnormal_irq(struct hisi_qm *qm) if (qm->fun_type == QM_HW_VF) return 0;

- val = qm_irq_type_caps[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val; + val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm->cap_ver); if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK)) return 0;

@@ -5065,7 +5051,7 @@ static void qm_unregister_mb_cmd_irq(struct hisi_qm *qm) struct pci_dev *pdev = qm->pdev; u32 irq_vector, val;

- val = qm_irq_type_caps[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val; + val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm->cap_ver); if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) return;

@@ -5079,7 +5065,7 @@ static int qm_register_mb_cmd_irq(struct hisi_qm *qm) u32 irq_vector, val; int ret;

- val = qm_irq_type_caps[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val; + val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm->cap_ver); if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) return 0;

@@ -5096,7 +5082,7 @@ static void qm_unregister_aeq_irq(struct hisi_qm *qm) struct pci_dev *pdev = qm->pdev; u32 irq_vector, val;

- val = qm_irq_type_caps[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val; + val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm->cap_ver); if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) return;

@@ -5110,7 +5096,7 @@ static int qm_register_aeq_irq(struct hisi_qm *qm) u32 irq_vector, val; int ret;

- val = qm_irq_type_caps[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val; + val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm->cap_ver); if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) return 0;

@@ -5128,7 +5114,7 @@ static void qm_unregister_eq_irq(struct hisi_qm *qm) struct pci_dev *pdev = qm->pdev; u32 irq_vector, val;

- val = qm_irq_type_caps[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val; + val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm->cap_ver); if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) return;

@@ -5142,7 +5128,7 @@ static int qm_register_eq_irq(struct hisi_qm *qm) u32 irq_vector, val; int ret;

- val = qm_irq_type_caps[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val; + val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm->cap_ver); if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK)) return 0;

@@ -5229,16 +5215,6 @@ static int qm_get_qp_num(struct hisi_qm *qm) return 0; }

-static void qm_pre_store_irq_type_caps(struct hisi_qm *qm) -{ - int i, size; - - size = ARRAY_SIZE(qm_irq_type_caps); - for (i = 0; i < size; i++) - qm_irq_type_caps[i].cap_val = hisi_qm_get_hw_info(qm, qm_basic_info, - qm_irq_type_caps[i].type, qm->cap_ver); -} - static void qm_get_hw_caps(struct hisi_qm *qm) { const struct hisi_qm_cap_info *cap_info = qm->fun_type == QM_HW_PF ? @@ -5270,9 +5246,6 @@ static void qm_get_hw_caps(struct hisi_qm *qm) if (val) set_bit(cap_info[i].type, &qm->caps); } - - /* Fetch and save the value of irq type related capability registers */ - qm_pre_store_irq_type_caps(qm); }

static int qm_get_pci_res(struct hisi_qm *qm) diff --git a/include/linux/hisi_acc_qm.h b/include/linux/hisi_acc_qm.h index 0f18b0e0e460..1ce2e1f2b941 100644 --- a/include/linux/hisi_acc_qm.h +++ b/include/linux/hisi_acc_qm.h @@ -285,11 +285,6 @@ struct hisi_qm_cap_info { u32 v3_val; };

-struct hisi_qm_cap_record { - u32 type; - u32 cap_val; -}; - struct hisi_qm_list { struct mutex lock; struct list_head list;