From: Anshuman Khandual anshuman.khandual@arm.com
mainline inclusion from mainline-v6.5-rc1 commit 5a1c7097472fcde5745654e3a59f55140903d9cc category: cleanup bugzilla: https://gitee.com/openeuler/kernel/issues/I89TNS CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=...
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Coresight device pid can be retrieved from its iomem base address, which is stored in 'struct etm4x_drvdata'. This drops pid argument from etm4_probe() and 'struct etm4_init_arg'. Instead etm4_check_arch_features() derives the coresight device pid with a new helper coresight_get_pid(), right before it is consumed in etm4_hisi_match_pid().
Cc: Mathieu Poirier mathieu.poirier@linaro.org Cc: Suzuki K Poulose suzuki.poulose@arm.com Cc: Mike Leach mike.leach@linaro.org Cc: Leo Yan leo.yan@linaro.org Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual anshuman.khandual@arm.com Signed-off-by: Suzuki K Poulose suzuki.poulose@arm.com Link: https://lore.kernel.org/r/20230710062500.45147-4-anshuman.khandual@arm.com Signed-off-by: Junhao He hejunhao3@huawei.com --- .../coresight/coresight-etm4x-core.c | 29 ++++++++++--------- include/linux/coresight.h | 12 ++++++++ 2 files changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 9827753cc9fa..372495da71d4 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -358,14 +358,22 @@ static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) }
static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, - unsigned int id) + struct csdev_access *csa) { - if (etm4_hisi_match_pid(id)) { + /* + * TRCPIDR* registers are not required for ETMs with system + * instructions. They must be identified by the MIDR+REVIDRs. + * Skip the TRCPID checks for now. + */ + if (!csa->io_mem) + return; + + if (etm4_hisi_match_pid(coresight_get_pid(csa))) { set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features); set_bit(ETM4_IMPDEF_HISI_SET_AUXCTRLR, drvdata->arch_features); }
- if (etm4_hisi_hip09_match_pid(id)) + if (etm4_hisi_hip09_match_pid(coresight_get_pid(csa))) set_bit(ETM4_IMPDEF_HISI_SET_AUXCTRLR, drvdata->arch_features); } #else @@ -381,7 +389,7 @@ static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) }
static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, - unsigned int id) + struct csdev_access *csa) { } #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */ @@ -1911,7 +1919,7 @@ static void etm4_pm_clear(void) } }
-static int etm4_probe(struct device *dev, u32 etm_pid) +static int etm4_probe(struct device *dev) { int ret; struct coresight_platform_data *pdata = NULL; @@ -2007,7 +2015,7 @@ static int etm4_probe(struct device *dev, u32 etm_pid) drvdata->boot_enable = true; }
- etm4_check_arch_features(drvdata, etm_pid); + etm4_check_arch_features(drvdata, &desc.access);
return 0; } @@ -2031,7 +2039,7 @@ static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
drvdata->base = base; dev_set_drvdata(dev, drvdata); - ret = etm4_probe(dev, id->id); + ret = etm4_probe(dev); if (!ret) pm_runtime_put(&adev->dev);
@@ -2053,12 +2061,7 @@ static int etm4_probe_platform_dev(struct platform_device *pdev) pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev);
- /* - * System register based devices could match the - * HW by reading appropriate registers on the HW - * and thus we could skip the PID. - */ - ret = etm4_probe(&pdev->dev, 0); + ret = etm4_probe(&pdev->dev);
pm_runtime_put(&pdev->dev); return ret; diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 36e6913e50fd..ba16553c6d83 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -370,6 +370,18 @@ static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa, return csa->read(offset, true, false); }
+#define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4)) + +static inline u32 coresight_get_pid(struct csdev_access *csa) +{ + u32 i, pid = 0; + + for (i = 0; i < 4; i++) + pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8); + + return pid; +} + static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa, u32 lo_offset, u32 hi_offset) {