ascend inclusion category: feature bugzilla: https://gitee.com/openeuler/kernel/issues/I8P62V CVE: NA
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Some platforms with LINXICORE9100 or CORTEX_A55, sccl and ccl are keep in aff2 if mt.
Signed-off-by: Chen Jun chenjun102@huawei.com --- drivers/perf/hisilicon/hisi_uncore_pmu.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c index f22bcebb26c9..0b483c440414 100644 --- a/drivers/perf/hisilicon/hisi_uncore_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c @@ -451,13 +451,21 @@ static void hisi_read_sccl_and_ccl_id(int *scclp, int *cclp) int aff1 = MPIDR_AFFINITY_LEVEL(mpidr, 1); bool mt = mpidr & MPIDR_MT_BITMASK; int sccl, ccl; - - if (mt && read_cpuid_part_number() == HISI_CPU_PART_TSV110) { - sccl = aff2 >> 3; - ccl = aff2 & 0x7; - } else if (mt) { - sccl = aff3; - ccl = aff2; + const struct midr_range workaround_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), + MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), + MIDR_REV(MIDR_HISI_LINXICORE9100, 1, 0), + { /* sentinel */ } + }; + + if (mt) { + if (is_midr_in_range_list(read_cpuid_id(), workaround_list)) { + sccl = aff2 >> 3; + ccl = aff2 & 0x7; + } else { + sccl = aff3; + ccl = aff2; + } } else { sccl = aff2; ccl = aff1;