From: Yanling Song songyl@ramaxel.com
Ramaxel inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I4OENF CVE: NA
Rearragne the order and add some flag bits for future use.
Signed-off-by: Yanling Song songyl@ramaxel.com Reviewed-by: Yang Gan yanggan@ramaxel.com Acked-by: Xie XiuQi xiexiuqi@huawei.com Acked-by: Xie XiuQi xiexiuqi@huawei.com Signed-off-by: Zheng Zengkai zhengzengkai@huawei.com --- .../net/ethernet/ramaxel/spnic/hw/sphw_hw.h | 28 ++++++++----------- 1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet/ramaxel/spnic/hw/sphw_hw.h b/drivers/net/ethernet/ramaxel/spnic/hw/sphw_hw.h index 2fc99c5f6096..74607ff24f09 100644 --- a/drivers/net/ethernet/ramaxel/spnic/hw/sphw_hw.h +++ b/drivers/net/ethernet/ramaxel/spnic/hw/sphw_hw.h @@ -605,28 +605,24 @@ void sphw_event_callback(void *hwdev, struct sphw_event_info *event); void sphw_link_event_stats(void *dev, u8 link);
enum func_reset_flag { - RES_TYPE_COMM = 0, - RES_TYPE_NIC = 1, - RES_TYPE_OVS = 2, - RES_TYPE_VBS = 3, - RES_TYPE_ROCE = 4, - RES_TYPE_FC = 5, - RES_TYPE_TOE = 6, - - RES_TYPE_FLUSH_BIT = 7, + RES_TYPE_FLUSH_BIT = 0, RES_TYPE_MQM, RES_TYPE_SMF, - RES_TYPE_CMDQ_ROOTCTX, - RES_TYPE_SQ_CI_TABLE, - RES_TYPE_PF_BW_CFG, - RES_TYPE_CEQ, - RES_TYPE_MBOX, - RES_TYPE_AEQ, + + RES_TYPE_COMM = 10, + RES_TYPE_COMM_MGMT_CH, + RES_TYPE_COMM_CMD_CH, + RES_TYPE_NIC, + RES_TYPE_OVS, + RES_TYPE_VBS, + RES_TYPE_ROCE, + RES_TYPE_FC, + RES_TYPE_TOE, RES_TYPE_IPSEC, };
#define SPHW_COMM_RES (BIT(RES_TYPE_COMM) | BIT(RES_TYPE_FLUSH_BIT) | BIT(RES_TYPE_MQM) | \ - BIT(RES_TYPE_SMF) | BIT(RES_TYPE_CMDQ_ROOTCTX)) + BIT(RES_TYPE_SMF) | BIT(RES_TYPE_COMM_CMD_CH))
#define SPHW_NIC_RES BIT(RES_TYPE_NIC) #define SPHW_FC_RES BIT(RES_TYPE_FC)