Hi， Jackie & Zengkai:
在 2022/2/23 10:36, Zheng Zengkai 写道:
Hi Jackie, Leo
在 2022/2/22 17:46, Jackie Liu 写道:
在 2022/2/22 下午4:16, Zheng Zengkai 写道:
From: LeoLiu-oc LeoLiu-oc@zhaoxin.com
zhaoxin inclusion category: bugfix bugzilla: https://gitee.com/openeuler/kernel/issues/I40QDN CVE: NA
When the RTC divider is changed from reset to an operating time base, the first update cycle should be 500ms later. But on some Zhaoxin SOCs, this first update cycle is one second later. So set RTC time on these Zhaoxin SOCs will causing 500ms delay. Skip setup RTC divider on these SOCs in mc146818_set_time to fix it.
Signed-off-by: LeoLiu-oc LeoLiu-oc@zhaoxin.com Signed-off-by: Zheng Zengkai zhengzengkai@huawei.com
drivers/rtc/rtc-mc146818-lib.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/drivers/rtc/rtc-mc146818-lib.c b/drivers/rtc/rtc-mc146818-lib.c index 2ecd8752b088..96d9d0219394 100644 --- a/drivers/rtc/rtc-mc146818-lib.c +++ b/drivers/rtc/rtc-mc146818-lib.c @@ -171,8 +171,17 @@ int mc146818_set_time(struct rtc_time *time) save_control = CMOS_READ(RTC_CONTROL); CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); +#ifdef CONFIG_X86 + if (!((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR || + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) && + (boot_cpu_data.x86 <= 7 && boot_cpu_data.x86_model <= 59))) { + save_freq_select = CMOS_READ(RTC_FREQ_SELECT); + CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); + } +#else save_freq_select = CMOS_READ(RTC_FREQ_SELECT); CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); +#endif #ifdef CONFIG_MACH_DECSTATION CMOS_WRITE(real_yrs, RTC_DEC_YEAR); @@ -190,7 +199,14 @@ int mc146818_set_time(struct rtc_time *time) #endif CMOS_WRITE(save_control, RTC_CONTROL); +#ifdef CONFIG_X86 + if (!((boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR || + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) && + (boot_cpu_data.x86 <= 7 && boot_cpu_data.x86_model <= 59)))
在这里直接写个 #endif 后面的 else 和 endif 就不需要了
+ CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); +#else CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); +#endif
这里依据上次兆芯同事解释的代码逻辑：
X86架构情况下，兆芯的相应平台不执行CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT), 即 commit message中Skip setup RTC divider on these SOCs in mc146818_set_time to fix it;
而其他架构(#else 分支)，仍然需要执行CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
@Jackie @ Leo，
两位看下理解是否OK？
是的，上面的理解是正确的，判断的目的是只有在Zhaoxin平台上跳过下面的CMOS_WRITE操作。如果去掉后面的#else，会导致X86架构的其他平台也不执行CMOS_WRITE操作。会改变通用代码逻辑。
Leo
spin_unlock_irqrestore(&rtc_lock, flags);
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